diff options
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
17 files changed, 526 insertions, 120 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index ccaca29200bb..60d1b1acf9a0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -70,6 +70,22 @@ clocks = <&zynqmp_clk ACPU>; }; +&cpu0_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu1_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu2_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + +&cpu3_debug { + clocks = <&zynqmp_clk DBF_FPD>; +}; + &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; @@ -230,18 +246,30 @@ &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART0_REF>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; + assigned-clocks = <&zynqmp_clk UART1_REF>; }; -&dwc3_0 { +&usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; -&dwc3_1 { +&dwc3_0 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; +}; + +&usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +}; + +&dwc3_1 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 92f4190d564d..95d16904d765 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -22,6 +22,17 @@ /plugin/; &{/} { + compatible = "xlnx,zynqmp-sk-kv260-revA", + "xlnx,zynqmp-sk-kv260-revY", + "xlnx,zynqmp-sk-kv260-revZ", + "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; + model = "ZynqMP KV260 revA"; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -68,7 +79,12 @@ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - /* u14 - 0x40 - ina260 */ + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; @@ -139,7 +155,7 @@ bus-width = <4>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; @@ -166,9 +182,28 @@ }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -185,6 +220,7 @@ conf-tx { pins = "MIO36"; bias-disable; + output-enable; }; mux { @@ -207,7 +243,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = <SLEW_RATE_SLOW>; @@ -236,6 +272,7 @@ conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; + output-enable; low-power-disable; }; @@ -243,6 +280,7 @@ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; + output-enable; low-power-enable; }; @@ -251,6 +289,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; mux-mdio { @@ -281,6 +320,7 @@ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = <SLEW_RATE_SLOW>; }; @@ -297,6 +337,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; conf-cd { @@ -319,6 +360,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index f88b71f5b07a..a74d0ac7e07a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -17,6 +17,17 @@ /plugin/; &{/} { + compatible = "xlnx,zynqmp-sk-kv260-rev2", + "xlnx,zynqmp-sk-kv260-rev1", + "xlnx,zynqmp-sk-kv260-revB", + "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; + model = "ZynqMP KV260 revB"; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -52,6 +63,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -63,8 +86,13 @@ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - /* u14 - 0x40 - ina260 */ - /* u43 - 0x2d - usb5744 */ + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + /* u43 - 0x2d - USB hub */ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; @@ -81,6 +109,14 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; + + ports { + port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; &zynqmp_dpdma { @@ -94,6 +130,7 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + assigned-clock-rates = <250000000>, <20000000>; }; &dwc3_0 { @@ -122,7 +159,7 @@ bus-width = <4>; }; -&gem3 { /* required by spec */ +&gem3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; @@ -149,9 +186,28 @@ }; }; -&pinctrl0 { /* required by spec */ +&pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -168,6 +224,7 @@ conf-tx { pins = "MIO36"; bias-disable; + output-enable; }; mux { @@ -190,7 +247,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = <SLEW_RATE_SLOW>; @@ -219,6 +276,7 @@ conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; + output-enable; low-power-disable; }; @@ -226,6 +284,7 @@ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; + output-enable; low-power-enable; }; @@ -234,6 +293,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; mux-mdio { @@ -264,6 +324,7 @@ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; + output-enable; drive-strength = <4>; slew-rate = <SLEW_RATE_SLOW>; }; @@ -280,6 +341,7 @@ slew-rate = <SLEW_RATE_SLOW>; power-source = <IO_STANDARD_LVCMOS18>; bias-disable; + output-enable; }; conf-cd { @@ -302,6 +364,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 51622896b1b1..bfa7ea6b9224 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP SM-K26 rev1/B/A + * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -17,8 +18,9 @@ #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> / { - model = "ZynqMP SM-K26 Rev1/B/A"; - compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", + model = "ZynqMP SM-K26 Rev2/1/B/A"; + compatible = "xlnx,zynqmp-sm-k26-rev2", + "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; @@ -88,18 +90,10 @@ }; }; - ams { - compatible = "iio-hwmon"; - io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, - <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, - <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, - <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, - <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, - <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, - <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, - <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, - <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, - <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; + pwm-fan { + compatible = "pwm-fan"; + status = "okay"; + pwms = <&ttc0 2 40000 0>; }; }; @@ -107,6 +101,11 @@ label = "modepin"; }; +&ttc0 { + status = "okay"; + #pwm-cells = <3>; +}; + &uart1 { /* MIO36/MIO37 */ status = "okay"; }; @@ -353,10 +352,6 @@ "", "", "", ""; /* 170 - 173 */ }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts index 85b0d1677240..b804abe89d1d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dts @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A + * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -10,8 +11,9 @@ #include "zynqmp-sm-k26-revA.dts" / { - model = "ZynqMP SMK-K26 Rev1/B/A"; - compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", + model = "ZynqMP SMK-K26 Rev2/1/B/A"; + compatible = "xlnx,zynqmp-smk-k26-rev2", + "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 73491626e01e..6aff22d43361 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -148,7 +148,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index f767708fb50d..1850325e1d6c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -219,7 +219,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index b1857e17ab7e..53aa3dca1dca 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -125,7 +125,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_74_grp", "gpio0_75_grp"; function = "gpio0"; @@ -152,7 +152,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_76_grp", "gpio0_77_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 52f998c22538..62c2503a502a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -275,7 +275,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; @@ -590,10 +590,6 @@ status = "okay"; }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts index c8f71a1aec89..495ca94b45db 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts @@ -14,6 +14,14 @@ compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; +&rproc_split { + status = "okay"; +}; + +&rproc_lockstep { + status = "disabled"; +}; + &eeprom { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 84952c14f021..7e26489a1539 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -603,7 +603,7 @@ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; @@ -689,7 +689,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -716,7 +716,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; @@ -941,6 +941,7 @@ &pcie { status = "okay"; + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>; }; &psgtr { @@ -1027,10 +1028,6 @@ status = "okay"; }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 5084ddcee00f..eb2090673ec1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -272,7 +272,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; @@ -511,10 +511,6 @@ status = "okay"; }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index b273bd1d920a..4694d0a841f1 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -284,7 +284,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; @@ -523,10 +523,6 @@ status = "okay"; }; -&xilinx_ams { - status = "okay"; -}; - &ams_ps { status = "okay"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 50c384aa253e..7beedd730f94 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -605,7 +605,7 @@ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; @@ -700,7 +700,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -727,7 +727,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 617cb0405a7d..b67ff7ecf3c3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -589,7 +589,7 @@ }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -616,7 +616,7 @@ }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index c406017b0348..a38c2baeba6c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * dts file for Xilinx ZynqMP ZC1275 + * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017 - 2021, Xilinx, Inc. * diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index eaba466804bc..e11d282462bd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -18,17 +18,26 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x20000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { + #cooling-cells = <2>; compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; @@ -39,6 +48,7 @@ }; cpu1: cpu@1 { + #cooling-cells = <2>; compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; @@ -49,6 +59,7 @@ }; cpu2: cpu@2 { + #cooling-cells = <2>; compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; @@ -59,6 +70,7 @@ }; cpu3: cpu@3 { + #cooling-cells = <2>; compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; @@ -162,7 +174,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, @@ -180,13 +192,18 @@ }; firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; method = "smc"; bootph-all; - zynqmp_power: zynqmp-power { + zynqmp_power: power-management { bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; @@ -195,13 +212,71 @@ mbox-names = "tx", "rx"; }; - nvmem-firmware { + soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - soc_revision: soc-revision@0 { - reg = <0x0 0x4>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + soc_revision: soc-revision@0 { + reg = <0x0 0x4>; + }; + /* efuse access */ + efuse_dna: efuse-dna@c { + reg = <0xc 0xc>; + }; + efuse_usr0: efuse-usr0@20 { + reg = <0x20 0x4>; + }; + efuse_usr1: efuse-usr1@24 { + reg = <0x24 0x4>; + }; + efuse_usr2: efuse-usr2@28 { + reg = <0x28 0x4>; + }; + efuse_usr3: efuse-usr3@2c { + reg = <0x2c 0x4>; + }; + efuse_usr4: efuse-usr4@30 { + reg = <0x30 0x4>; + }; + efuse_usr5: efuse-usr5@34 { + reg = <0x34 0x4>; + }; + efuse_usr6: efuse-usr6@38 { + reg = <0x38 0x4>; + }; + efuse_usr7: efuse-usr7@3c { + reg = <0x3c 0x4>; + }; + efuse_miscusr: efuse-miscusr@40 { + reg = <0x40 0x4>; + }; + efuse_chash: efuse-chash@50 { + reg = <0x50 0x4>; + }; + efuse_pufmisc: efuse-pufmisc@54 { + reg = <0x54 0x4>; + }; + efuse_sec: efuse-sec@58 { + reg = <0x58 0x4>; + }; + efuse_spkid: efuse-spkid@5c { + reg = <0x5c 0x4>; + }; + efuse_aeskey: efuse-aeskey@60 { + reg = <0x60 0x20>; + }; + efuse_ppk0hash: efuse-ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + efuse_ppk1hash: efuse-ppk1hash@d0 { + reg = <0xd0 0x30>; + }; + efuse_pufuser: efuse-pufuser@100 { + reg = <0x100 0x7F>; + }; }; }; @@ -240,7 +315,7 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; @@ -248,23 +323,175 @@ ranges; }; - remoteproc { + rproc_lockstep: remoteproc@ffe00000 { compatible = "xlnx,zynqmp-r5fss"; xlnx,cluster-mode = <1>; + xlnx,tcm-mode = <1>; - r5f-0 { + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, + <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; + + r5f@0 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_0>; + reg = <0x0 0x0 0x0 0x10000>, + <0x0 0x20000 0x0 0x10000>, + <0x0 0x10000 0x0 0x10000>, + <0x0 0x30000 0x0 0x10000>; + reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; memory-region = <&rproc_0_fw_image>; }; - r5f-1 { + r5f@1 { compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware PD_RPU_1>; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; memory-region = <&rproc_1_fw_image>; }; }; + rproc_split: remoteproc-split@ffe00000 { + status = "disabled"; + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <0>; + xlnx,tcm-mode = <0>; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; + memory-region = <&rproc_0_fw_image>; + }; + + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>; + }; + }; + + ams { + compatible = "iio-hwmon"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, + <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, + <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, + <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, + <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, + <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, + <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; + }; + + + tsens_apu: thermal-sensor-apu { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&xilinx_ams 7>; + io-channel-names = "sensor-channel"; + }; + + tsens_rpu: thermal-sensor-rpu { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&xilinx_ams 8>; + io-channel-names = "sensor-channel"; + }; + + tsens_pl: thermal-sensor-pl { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&xilinx_ams 20>; + io-channel-names = "sensor-channel"; + }; + + thermal-zones { + apu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tsens_apu>; + + trips { + apu_passive: passive { + temperature = <93000>; + hysteresis = <3500>; + type = "passive"; + }; + + apu_critical: critical { + temperature = <96500>; + hysteresis = <3500>; + type = "critical"; + }; + }; + + cooling-maps { + map { + trip = <&apu_passive>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + rpu-thermal { + polling-delay = <10000>; + thermal-sensors = <&tsens_rpu>; + + trips { + critical { + temperature = <96500>; + hysteresis = <3500>; + type = "critical"; + }; + }; + }; + + pl-thermal { + polling-delay = <10000>; + thermal-sensors = <&tsens_pl>; + + trips { + critical { + temperature = <96500>; + hysteresis = <3500>; + type = "critical"; + }; + }; + }; + }; + amba: axi { compatible = "simple-bus"; bootph-all; @@ -281,6 +508,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; @@ -293,6 +521,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; @@ -316,6 +545,34 @@ }; }; + cpu0_debug: debug@fec10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfec10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + cpu1_debug: debug@fed10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + cpu2_debug: debug@fee10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfee10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + cpu3_debug: debug@fef10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x0 0xfef10000 0x0 0x1000>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; @@ -326,7 +583,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e8>; + /* iommus = <&smmu 0x14e8>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -339,7 +596,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e9>; + /* iommus = <&smmu 0x14e9>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -352,7 +609,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ea>; + /* iommus = <&smmu 0x14ea>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -365,7 +622,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14eb>; + /* iommus = <&smmu 0x14eb>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -378,7 +635,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ec>; + /* iommus = <&smmu 0x14ec>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -391,7 +648,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ed>; + /* iommus = <&smmu 0x14ed>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -404,7 +661,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ee>; + /* iommus = <&smmu 0x14ee>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -417,7 +674,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ef>; + /* iommus = <&smmu 0x14ef>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -462,7 +719,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x868>; + /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -475,7 +732,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x869>; + /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -488,7 +745,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86a>; + /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -501,7 +758,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86b>; + /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -514,7 +771,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86c>; + /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -527,7 +784,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86d>; + /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -540,7 +797,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86e>; + /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -553,7 +810,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86f>; + /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -573,7 +830,7 @@ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x872>; + /* iommus = <&smmu 0x872>; */ power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -585,7 +842,7 @@ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x874>; + /* iommus = <&smmu 0x874>; */ power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; @@ -599,7 +856,7 @@ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x875>; + /* iommus = <&smmu 0x875>; */ power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; @@ -613,7 +870,7 @@ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x876>; + /* iommus = <&smmu 0x876>; */ power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; @@ -627,7 +884,7 @@ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x877>; + /* iommus = <&smmu 0x877>; */ power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; @@ -670,6 +927,13 @@ power-domains = <&zynqmp_firmware PD_I2C_1>; }; + ocm: memory-controller@ff960000 { + compatible = "xlnx,zynqmp-ocmc-1.0"; + reg = <0x0 0xff960000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + }; + pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; @@ -689,7 +953,7 @@ msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ @@ -699,7 +963,7 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - iommus = <&smmu 0x4d0>; + /* iommus = <&smmu 0x4d0>; */ power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; @@ -720,7 +984,7 @@ <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x873>; + /* iommus = <&smmu 0x873>; */ power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -752,8 +1016,7 @@ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, - <&smmu 0x4c2>, <&smmu 0x4c3>; + /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ }; sdhci0: mmc@ff160000 { @@ -764,7 +1027,7 @@ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x870>; + /* iommus = <&smmu 0x870>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; @@ -779,7 +1042,7 @@ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x871>; + /* iommus = <&smmu 0x871>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; @@ -893,6 +1156,7 @@ reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_UART0>; }; uart1: serial@ff010000 { @@ -904,6 +1168,7 @@ reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_UART1>; }; usb0: usb@ff9d0000 { @@ -912,6 +1177,7 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, @@ -922,14 +1188,16 @@ dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "bus_early", "ref"; - iommus = <&smmu 0x860>; + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ref"; + /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations; /* dma-coherent; */ @@ -942,6 +1210,7 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, @@ -951,14 +1220,16 @@ dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "host", "peripheral", "otg"; + interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "bus_early", "ref"; - iommus = <&smmu 0x861>; + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "ref"; + /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations; /* dma-coherent; */ @@ -986,7 +1257,6 @@ xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; - status = "disabled"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xffa50000 0x0 0x800>; @@ -1005,8 +1275,6 @@ compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; - #address-cells = <1>; - #size-cells = <0>; }; }; @@ -1018,6 +1286,7 @@ interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; + /* iommus = <&smmu 0xce4>; */ #dma-cells = <1>; }; @@ -1032,15 +1301,19 @@ reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; + /* iommus = <&smmu 0xce3>; */ clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; - dma-names = "vid0", "vid1", "vid2", "gfx0"; + dma-names = "vid0", "vid1", "vid2", "gfx0", + "aud0", "aud1"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, - <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; + <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>, + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>, + <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>; ports { #address-cells = <1>; |