diff options
Diffstat (limited to 'arch/arm')
335 files changed, 2001 insertions, 15283 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7fd33a337130..43449305961e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -303,6 +303,7 @@ config ARCH_BCMRING depends on MMU select CPU_V6 select ARM_AMBA + select ARM_TIMER_SP804 select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB @@ -372,6 +373,7 @@ config ARCH_MXC select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_MMIO select HAVE_SCHED_CLOCK help Support for Freescale MXC/iMX-based family of processors @@ -381,21 +383,13 @@ config ARCH_MXS select GENERIC_CLOCKEVENTS select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_MMIO help Support for Freescale MXS-based family of processors -config ARCH_STMP3XXX - bool "Freescale STMP3xxx" - select CPU_ARM926T - select CLKDEV_LOOKUP - select ARCH_REQUIRE_GPIOLIB - select GENERIC_CLOCKEVENTS - select USB_ARCH_HAS_EHCI - help - Support for systems based on the Freescale 3xxx CPUs. - config ARCH_NETX bool "Hilscher NetX based" + select CLKSRC_MMIO select CPU_ARM926T select ARM_VIC select GENERIC_CLOCKEVENTS @@ -463,6 +457,7 @@ config ARCH_IXP2000 config ARCH_IXP4XX bool "IXP4xx-based" depends on MMU + select CLKSRC_MMIO select CPU_XSCALE select GENERIC_GPIO select GENERIC_CLOCKEVENTS @@ -503,6 +498,7 @@ config ARCH_LOKI config ARCH_LPC32XX bool "NXP LPC32XX" + select CLKSRC_MMIO select CPU_ARM926T select ARCH_REQUIRE_GPIOLIB select HAVE_IDE @@ -560,23 +556,12 @@ config ARCH_KS8695 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. -config ARCH_NS9XXX - bool "NetSilicon NS9xxx" - select CPU_ARM926T - select GENERIC_GPIO - select GENERIC_CLOCKEVENTS - select HAVE_CLK - help - Say Y here if you intend to run this kernel on a NetSilicon NS9xxx - System. - - <http://www.digi.com/products/microprocessors/index.jsp> - config ARCH_W90X900 bool "Nuvoton W90X900 CPU" select CPU_ARM926T select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_MMIO select GENERIC_CLOCKEVENTS help Support for Nuvoton (Winbond logic dept.) ARM9 processor, @@ -598,6 +583,7 @@ config ARCH_NUC93X config ARCH_TEGRA bool "NVIDIA Tegra" select CLKDEV_LOOKUP + select CLKSRC_MMIO select GENERIC_TIME select GENERIC_CLOCKEVENTS select GENERIC_GPIO @@ -623,6 +609,7 @@ config ARCH_PXA select ARCH_MTD_XIP select ARCH_HAS_CPUFREQ select CLKDEV_LOOKUP + select CLKSRC_MMIO select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS select HAVE_SCHED_CLOCK @@ -673,6 +660,7 @@ config ARCH_RPC config ARCH_SA1100 bool "SA1100-based" + select CLKSRC_MMIO select CPU_SA1100 select ISA select ARCH_SPARSEMEM_ENABLE @@ -809,6 +797,7 @@ config ARCH_SHARK config ARCH_TCC_926 bool "Telechips TCC ARM926-based systems" + select CLKSRC_MMIO select CPU_ARM926T select HAVE_CLK select CLKDEV_LOOKUP @@ -819,6 +808,7 @@ config ARCH_TCC_926 config ARCH_U300 bool "ST-Ericsson U300 Series" depends on MMU + select CLKSRC_MMIO select CPU_ARM926T select HAVE_SCHED_CLOCK select HAVE_TCM @@ -880,6 +870,7 @@ config PLAT_SPEAR select ARM_AMBA select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP + select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select HAVE_CLK help @@ -957,8 +948,6 @@ source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" source "arch/arm/plat-nomadik/Kconfig" -source "arch/arm/mach-ns9xxx/Kconfig" - source "arch/arm/mach-nuc93x/Kconfig" source "arch/arm/plat-omap/Kconfig" @@ -1011,8 +1000,6 @@ source "arch/arm/mach-exynos4/Kconfig" source "arch/arm/mach-shmobile/Kconfig" -source "arch/arm/plat-stmp3xxx/Kconfig" - source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-u300/Kconfig" @@ -1039,6 +1026,7 @@ config PLAT_IOP config PLAT_ORION bool + select CLKSRC_MMIO select HAVE_SCHED_CLOCK config PLAT_PXA @@ -1049,6 +1037,7 @@ config PLAT_VERSATILE config ARM_TIMER_SP804 bool + select CLKSRC_MMIO source arch/arm/mm/Kconfig @@ -2030,7 +2019,7 @@ menu "Power management options" source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE - depends on !ARCH_S5P64X0 && !ARCH_S5P6442 + depends on !ARCH_S5P64X0 && !ARCH_S5P6442 && !ARCH_S5PC100 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE def_bool y diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c7d321a3d95d..458a01516676 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -164,7 +164,6 @@ machine-$(CONFIG_ARCH_MXC91231) := mxc91231 machine-$(CONFIG_ARCH_MXS) := mxs machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NOMADIK) := nomadik -machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx machine-$(CONFIG_ARCH_OMAP1) := omap1 machine-$(CONFIG_ARCH_OMAP2) := omap2 machine-$(CONFIG_ARCH_OMAP3) := omap2 @@ -185,8 +184,6 @@ machine-$(CONFIG_ARCH_EXYNOS4) := exynos4 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHMOBILE) := shmobile -machine-$(CONFIG_ARCH_STMP378X) := stmp378x -machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx machine-$(CONFIG_ARCH_TCC8K) := tcc8k machine-$(CONFIG_ARCH_TEGRA) := tegra machine-$(CONFIG_ARCH_U300) := u300 @@ -207,7 +204,6 @@ machine-$(CONFIG_MACH_SPEAR600) := spear6xx plat-$(CONFIG_ARCH_MXC) := mxc plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_S3C64XX) := samsung -plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx plat-$(CONFIG_ARCH_TCC_926) := tcc plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_NOMADIK) := nomadik diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 8ebbb511c783..0c6852d93506 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -74,7 +74,7 @@ ZTEXTADDR := $(CONFIG_ZBOOT_ROM_TEXT) ZBSSADDR := $(CONFIG_ZBOOT_ROM_BSS) else ZTEXTADDR := 0 -ZBSSADDR := ALIGN(4) +ZBSSADDR := ALIGN(8) endif SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index ae7ecc286e7a..6fdf4abb718b 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -179,15 +179,14 @@ not_angel: bl cache_on restart: adr r0, LC0 - ldmia r0, {r1, r2, r3, r5, r6, r9, r11, r12} - ldr sp, [r0, #32] + ldmia r0, {r1, r2, r3, r6, r9, r11, r12} + ldr sp, [r0, #28] /* * We might be running at a different address. We need * to fix up various pointers. */ sub r0, r0, r1 @ calculate the delta offset - add r5, r5, r0 @ _start add r6, r6, r0 @ _edata #ifndef CONFIG_ZBOOT_ROM @@ -206,31 +205,40 @@ restart: adr r0, LC0 /* * Check to see if we will overwrite ourselves. * r4 = final kernel address - * r5 = start of this image * r9 = size of decompressed image * r10 = end of this image, including bss/stack/malloc space if non XIP * We basically want: - * r4 >= r10 -> OK - * r4 + image length <= r5 -> OK + * r4 - 16k page directory >= r10 -> OK + * r4 + image length <= current position (pc) -> OK */ + add r10, r10, #16384 cmp r4, r10 bhs wont_overwrite add r10, r4, r9 - cmp r10, r5 + ARM( cmp r10, pc ) + THUMB( mov lr, pc ) + THUMB( cmp r10, lr ) bls wont_overwrite /* * Relocate ourselves past the end of the decompressed kernel. - * r5 = start of this image * r6 = _edata * r10 = end of the decompressed kernel * Because we always copy ahead, we need to do it from the end and go * backward in case the source and destination overlap. */ - /* Round up to next 256-byte boundary. */ - add r10, r10, #256 + /* + * Bump to the next 256-byte boundary with the size of + * the relocation code added. This avoids overwriting + * ourself when the offset is small. + */ + add r10, r10, #((reloc_code_end - restart + 256) & ~255) bic r10, r10, #255 + /* Get start of code we want to copy and align it down. */ + adr r5, restart + bic r5, r5, #31 + sub r9, r6, r5 @ size to copy add r9, r9, #31 @ rounded up to a multiple bic r9, r9, #31 @ ... of 32 bytes @@ -245,6 +253,11 @@ restart: adr r0, LC0 /* Preserve offset to relocated code. */ sub r6, r9, r6 +#ifndef CONFIG_ZBOOT_ROM + /* cache_clean_flush may use the stack, so relocate it */ + add sp, sp, r6 +#endif + bl cache_clean_flush adr r0, BSYM(restart) @@ -333,7 +346,6 @@ not_relocated: mov r0, #0 LC0: .word LC0 @ r1 .word __bss_start @ r2 .word _end @ r3 - .word _start @ r5 .word _edata @ r6 .word _image_size @ r9 .word _got_start @ r11 @@ -1078,6 +1090,7 @@ memdump: mov r12, r0 #endif .ltorg +reloc_code_end: .align .section ".stack", "aw", %nobits diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in index 5309909d7282..ea80abe78844 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.in +++ b/arch/arm/boot/compressed/vmlinux.lds.in @@ -54,6 +54,7 @@ SECTIONS .bss : { *(.bss) } _end = .; + . = ALIGN(8); /* the stack must be 64-bit aligned */ .stack : { *(.stack) } .stab 0 : { *(.stab) } diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index a12b33c0dc42..9c49a46a2b7a 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -185,14 +185,6 @@ static struct sa1111_dev_info sa1111_devices[] = { }, }; -void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes) -{ - unsigned int sz = SZ_1M >> PAGE_SHIFT; - - size[1] = size[0] - sz; - size[0] = sz; -} - /* * SA1111 interrupt support. Since clearing an IRQ while there are * active IRQs causes the interrupt output to pulse, the upper levels diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c index 6ef3342153b9..41df47875122 100644 --- a/arch/arm/common/timer-sp.c +++ b/arch/arm/common/timer-sp.c @@ -18,53 +18,67 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include <linux/clk.h> #include <linux/clocksource.h> #include <linux/clockchips.h> +#include <linux/err.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> #include <asm/hardware/arm_timer.h> -/* - * These timers are currently always setup to be clocked at 1MHz. - */ -#define TIMER_FREQ_KHZ (1000) -#define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ) +static long __init sp804_get_clock_rate(const char *name) +{ + struct clk *clk; + long rate; + int err; + + clk = clk_get_sys("sp804", name); + if (IS_ERR(clk)) { + pr_err("sp804: %s clock not found: %d\n", name, + (int)PTR_ERR(clk)); + return PTR_ERR(clk); + } -static void __iomem *clksrc_base; + err = clk_enable(clk); + if (err) { + pr_err("sp804: %s clock failed to enable: %d\n", name, err); + clk_put(clk); + return err; + } -static cycle_t sp804_read(struct clocksource *cs) -{ - return ~readl(clksrc_base + TIMER_VALUE); -} + rate = clk_get_rate(clk); + if (rate < 0) { + pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate); + clk_disable(clk); + clk_put(clk); + } -static struct clocksource clocksource_sp804 = { - .name = "timer3", - .rating = 200, - .read = sp804_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; + return rate; +} -void __init sp804_clocksource_init(void __iomem *base) +void __init sp804_clocksource_init(void __iomem *base, const char *name) { - struct clocksource *cs = &clocksource_sp804; + long rate = sp804_get_clock_rate(name); - clksrc_base = base; + if (rate < 0) + return; /* setup timer 0 as free-running clocksource */ - writel(0, clksrc_base + TIMER_CTRL); - writel(0xffffffff, clksrc_base + TIMER_LOAD); - writel(0xffffffff, clksrc_base + TIMER_VALUE); + writel(0, base + TIMER_CTRL); + writel(0xffffffff, base + TIMER_LOAD); + writel(0xffffffff, base + TIMER_VALUE); writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - clksrc_base + TIMER_CTRL); + base + TIMER_CTRL); - clocksource_register_khz(cs, TIMER_FREQ_KHZ); + clocksource_mmio_init(base + TIMER_VALUE, name, + rate, 200, 32, clocksource_mmio_readl_down); } static void __iomem *clkevt_base; +static unsigned long clkevt_reload; /* * IRQ handler for the timer @@ -90,7 +104,7 @@ static void sp804_set_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD); + writel(clkevt_reload, clkevt_base + TIMER_LOAD); ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; break; @@ -120,7 +134,6 @@ static int sp804_set_next_event(unsigned long next, } static struct clock_event_device sp804_clockevent = { - .name = "timer0", .shift = 32, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_mode = sp804_set_mode, @@ -136,17 +149,24 @@ static struct irqaction sp804_timer_irq = { .dev_id = &sp804_clockevent, }; -void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq) +void __init sp804_clockevents_init(void __iomem *base, unsigned int irq, + const char *name) { struct clock_event_device *evt = &sp804_clockevent; + long rate = sp804_get_clock_rate(name); + + if (rate < 0) + return; clkevt_base = base; + clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ); - evt->irq = timer_irq; - evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift); + evt->name = name; + evt->irq = irq; + evt->mult = div_sc(rate, NSEC_PER_SEC, evt->shift); evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); evt->min_delta_ns = clockevent_delta2ns(0xf, evt); - setup_irq(timer_irq, &sp804_timer_irq); + setup_irq(irq, &sp804_timer_irq); clockevents_register_device(evt); } diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 113085a77123..7aa4262ada7a 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -22,17 +22,16 @@ #include <linux/init.h> #include <linux/list.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/device.h> #include <linux/amba/bus.h> #include <asm/mach/irq.h> #include <asm/hardware/vic.h> -#if defined(CONFIG_PM) +#ifdef CONFIG_PM /** * struct vic_device - VIC PM device - * @sysdev: The system device which is registered. * @irq: The IRQ number for the base of the VIC. * @base: The register base for the VIC. * @resume_sources: A bitmask of interrupts for resume. @@ -43,8 +42,6 @@ * @protect: Save for VIC_PROTECT. */ struct vic_device { - struct sys_device sysdev; - void __iomem *base; int irq; u32 resume_sources; @@ -59,11 +56,6 @@ struct vic_device { static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; static int vic_id; - -static inline struct vic_device *to_vic(struct sys_device *sys) -{ - return container_of(sys, struct vic_device, sysdev); -} #endif /* CONFIG_PM */ /** @@ -85,10 +77,9 @@ static void vic_init2(void __iomem *base) writel(32, base + VIC_PL190_DEF_VECT_ADDR); } -#if defined(CONFIG_PM) -static int vic_class_resume(struct sys_device *dev) +#ifdef CONFIG_PM +static void resume_one_vic(struct vic_device *vic) { - struct vic_device *vic = to_vic(dev); void __iomem *base = vic->base; printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); @@ -107,13 +98,18 @@ static int vic_class_resume(struct sys_device *dev) writel(vic->soft_int, base + VIC_INT_SOFT); writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); +} - return 0; +static void vic_resume(void) +{ + int id; + + for (id = vic_id - 1; id >= 0; id--) + resume_one_vic(vic_devices + id); } -static int vic_class_suspend(struct sys_device *dev, pm_message_t state) +static void suspend_one_vic(struct vic_device *vic) { - struct vic_device *vic = to_vic(dev); void __iomem *base = vic->base; printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); @@ -128,14 +124,21 @@ static int vic_class_suspend(struct sys_device *dev, pm_message_t state) writel(vic->resume_irqs, base + VIC_INT_ENABLE); writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); +} + +static int vic_suspend(void) +{ + int id; + + for (id = 0; id < vic_id; id++) + suspend_one_vic(vic_devices + id); return 0; } -struct sysdev_class vic_class = { - .name = "vic", - .suspend = vic_class_suspend, - .resume = vic_class_resume, +struct syscore_ops vic_syscore_ops = { + .suspend = vic_suspend, + .resume = vic_resume, }; /** @@ -147,30 +150,8 @@ struct sysdev_class vic_class = { */ static int __init vic_pm_init(void) { - struct vic_device *dev = vic_devices; - int err; - int id; - - if (vic_id == 0) - return 0; - - err = sysdev_class_register(&vic_class); - if (err) { - printk(KERN_ERR "%s: cannot register class\n", __func__); - return err; - } - - for (id = 0; id < vic_id; id++, dev++) { - dev->sysdev.id = id; - dev->sysdev.cls = &vic_class; - - err = sysdev_register(&dev->sysdev); - if (err) { - printk(KERN_ERR "%s: failed to register device\n", - __func__); - return err; - } - } + if (vic_id > 0) + register_syscore_ops(&vic_syscore_ops); return 0; } diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig new file mode 100644 index 000000000000..2bf224310fb4 --- /dev/null +++ b/arch/arm/configs/mxs_defconfig @@ -0,0 +1,129 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_MXS=y +CONFIG_MACH_STMP378X_DEVB=y +CONFIG_MACH_TX28=y +# CONFIG_ARM_THUMB is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_AUTO_ZRELADDR=y +CONFIG_FPE_NWFPE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_SYN_COOKIES=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_IPV6 is not set +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_DEV=m +CONFIG_CAN_FLEXCAN=m +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_BLK_DEV is not set +CONFIG_NETDEVICES=y +CONFIG_NET_ETHERNET=y +CONFIG_ENC28J60=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_TSC2007=m +# CONFIG_SERIO is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=m +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MXS=m +CONFIG_SPI=y +CONFIG_SPI_GPIO=m +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +# CONFIG_MFD_SUPPORT is not set +CONFIG_DISPLAY_SUPPORT=m +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +CONFIG_MMC_MXS=y +CONFIG_RTC_CLASS=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_DMADEVICES=y +CONFIG_MXS_DMA=y +CONFIG_EXT3_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_PRINTK_TIME=y +CONFIG_FRAME_WARN=2048 +CONFIG_MAGIC_SYSRQ=y +CONFIG_UNUSED_SYMBOLS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_TIMER_STATS=y +CONFIG_PROVE_LOCKING=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y +CONFIG_DEBUG_INFO=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_STRICT_DEVMEM=y +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC7=m diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig deleted file mode 100644 index 1f528a002983..000000000000 --- a/arch/arm/configs/ns9xxx_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_NS9XXX=y -CONFIG_MACH_CC9P9360DEV=y -CONFIG_MACH_CC9P9360JS=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_FPE_NWFPE=y -CONFIG_NET=y -CONFIG_PACKET=m -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_SYN_COOKIES=y -CONFIG_MTD=m -CONFIG_MTD_CONCAT=m -CONFIG_MTD_CHAR=m -CONFIG_MTD_BLOCK=m -CONFIG_MTD_CFI=m -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_PHYSMAP=m -CONFIG_BLK_DEV_LOOP=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=m -CONFIG_I2C_GPIO=m -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m -CONFIG_LEDS_GPIO=m -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_RTC_CLASS=m -CONFIG_EXT2_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=m -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig index 5ca7a61f7c01..abe61bf379d2 100644 --- a/arch/arm/configs/realview-smp_defconfig +++ b/arch/arm/configs/realview-smp_defconfig @@ -38,7 +38,7 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_ARM_INTEGRATOR=y +CONFIG_MTD_PHYSMAP=y CONFIG_ARM_CHARLCD=y CONFIG_NETDEVICES=y CONFIG_SMSC_PHY=y diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig index fcaa60328051..7079cbe898a8 100644 --- a/arch/arm/configs/realview_defconfig +++ b/arch/arm/configs/realview_defconfig @@ -37,7 +37,7 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_ARM_INTEGRATOR=y +CONFIG_MTD_PHYSMAP=y CONFIG_ARM_CHARLCD=y CONFIG_NETDEVICES=y CONFIG_SMSC_PHY=y diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig deleted file mode 100644 index 824e44418b18..000000000000 --- a/arch/arm/configs/spear310_defconfig +++ /dev/null @@ -1,52 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_PLAT_SPEAR=y -CONFIG_MACH_SPEAR310=y -CONFIG_BINFMT_MISC=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_PL061=y -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_AUTOFS4_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -CONFIG_TMPFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=m -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_INFO=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig deleted file mode 100644 index 842f7f3c512a..000000000000 --- a/arch/arm/configs/spear320_defconfig +++ /dev/null @@ -1,52 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_PLAT_SPEAR=y -CONFIG_MACH_SPEAR320=y -CONFIG_BINFMT_MISC=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_RAW_DRIVER=y -CONFIG_MAX_RAW_DEVS=8192 -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_PL061=y -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_AUTOFS4_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -CONFIG_TMPFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=m -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_INFO=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear3xx_defconfig index cf29f3e56922..fea7e1f026a3 100644 --- a/arch/arm/configs/spear300_defconfig +++ b/arch/arm/configs/spear3xx_defconfig @@ -7,6 +7,9 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PLAT_SPEAR=y +CONFIG_BOARD_SPEAR300_EVB=y +CONFIG_BOARD_SPEAR310_EVB=y +CONFIG_BOARD_SPEAR320_EVB=y CONFIG_BINFMT_MISC=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_RAM=y @@ -24,7 +27,6 @@ CONFIG_MAX_RAW_DEVS=8192 CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y diff --git a/arch/arm/configs/spear600_defconfig b/arch/arm/configs/spear6xx_defconfig index 6777c11f63e7..cef2e836afd2 100644 --- a/arch/arm/configs/spear600_defconfig +++ b/arch/arm/configs/spear6xx_defconfig @@ -8,6 +8,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR6XX=y +CONFIG_BOARD_SPEAR600_EVB=y CONFIG_BINFMT_MISC=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_RAM=y @@ -22,7 +23,6 @@ CONFIG_MAX_RAW_DEVS=8192 CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_EXT2_FS=y diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig deleted file mode 100644 index 1079c2b6eb3a..000000000000 --- a/arch/arm/configs/stmp378x_defconfig +++ /dev/null @@ -1,128 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-default" -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_STMP3XXX=y -CONFIG_ARCH_STMP378X=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M" -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NET_SCHED=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -CONFIG_MTD=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_GLUEBI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=4 -CONFIG_BLK_DEV_RAM_SIZE=6144 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_INPUT_POLLDEV=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=m -# CONFIG_MISC_FILESYSTEMS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_SELFTEST=y -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_SLAB=y -CONFIG_DEBUG_SLAB_LEAK=y -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_PROVE_LOCKING=y -CONFIG_DEBUG_SPINLOCK_SLEEP=y -CONFIG_DEBUG_KOBJECT=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_BOOT_TRACER=y -CONFIG_STACK_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC16=y diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig deleted file mode 100644 index 564a5cc44085..000000000000 --- a/arch/arm/configs/stmp37xx_defconfig +++ /dev/null @@ -1,108 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-default" -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_STMP3XXX=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel" -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NET_SCHED=y -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_STANDALONE is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=4 -CONFIG_BLK_DEV_RAM_SIZE=6144 -# CONFIG_MISC_DEVICES is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_INPUT_POLLDEV=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240 -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=m -# CONFIG_MISC_FILESYSTEMS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_BOOT_TRACER=y -CONFIG_STACK_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_DEBUG_LL=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=m -CONFIG_CRC16=y diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig index 0ce710f47500..cdd4d2bd3962 100644 --- a/arch/arm/configs/versatile_defconfig +++ b/arch/arm/configs/versatile_defconfig @@ -32,7 +32,7 @@ CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_ARM_INTEGRATOR=y +CONFIG_MTD_PHYSMAP=y CONFIG_BLK_DEV_RAM=y CONFIG_EEPROM_LEGACY=m CONFIG_NETDEVICES=y diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index ca51143f97f1..42005542932b 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h @@ -6,8 +6,10 @@ /* * This is the maximum virtual address which can be DMA'd from. */ -#ifndef MAX_DMA_ADDRESS +#ifndef ARM_DMA_ZONE_SIZE #define MAX_DMA_ADDRESS 0xffffffff +#else +#define MAX_DMA_ADDRESS (PAGE_OFFSET + ARM_DMA_ZONE_SIZE) #endif #ifdef CONFIG_ISA_DMA_API diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h index 21e75e30d497..4384d81eee79 100644 --- a/arch/arm/include/asm/hardware/timer-sp.h +++ b/arch/arm/include/asm/hardware/timer-sp.h @@ -1,2 +1,2 @@ -void sp804_clocksource_init(void __iomem *); -void sp804_clockevents_init(void __iomem *, unsigned int); +void sp804_clocksource_init(void __iomem *, const char *); +void sp804_clockevents_init(void __iomem *, unsigned int, const char *); diff --git a/arch/arm/include/asm/i8253.h b/arch/arm/include/asm/i8253.h new file mode 100644 index 000000000000..70656b69d5ce --- /dev/null +++ b/arch/arm/include/asm/i8253.h @@ -0,0 +1,15 @@ +#ifndef __ASMARM_I8253_H +#define __ASMARM_I8253_H + +/* i8253A PIT registers */ +#define PIT_MODE 0x43 +#define PIT_CH0 0x40 + +#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ) + +extern raw_spinlock_t i8253_lock; + +#define outb_pit outb_p +#define inb_pit inb_p + +#endif diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index 883f6be5117a..d5adaae5ee2c 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h @@ -34,7 +34,6 @@ * timer interrupt which may be pending. */ struct sys_timer { - struct sys_device dev; void (*init)(void); void (*suspend)(void); void (*resume)(void); diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 431077c5a867..af44a8fb3480 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -209,14 +209,10 @@ static inline unsigned long __phys_to_virt(unsigned long x) * allocations. This must be the smallest DMA mask in the system, * so a successful GFP_DMA allocation will always satisfy this. */ -#ifndef ISA_DMA_THRESHOLD +#ifndef ARM_DMA_ZONE_SIZE #define ISA_DMA_THRESHOLD (0xffffffffULL) -#endif - -#ifndef arch_adjust_zones -#define arch_adjust_zones(size,holes) do { } while (0) -#elif !defined(CONFIG_ZONE_DMA) -#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA" +#else +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1) #endif /* diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h index 316bb2b2be3d..154b89b81d3e 100644 --- a/arch/arm/include/asm/sizes.h +++ b/arch/arm/include/asm/sizes.h @@ -16,44 +16,6 @@ /* Size definitions * Copyright (C) ARM Limited 1998. All rights reserved. */ +#include <asm-generic/sizes.h> -#ifndef __sizes_h -#define __sizes_h 1 - -/* handy sizes */ -#define SZ_16 0x00000010 -#define SZ_32 0x00000020 -#define SZ_64 0x00000040 -#define SZ_128 0x00000080 -#define SZ_256 0x00000100 -#define SZ_512 0x00000200 - -#define SZ_1K 0x00000400 -#define SZ_2K 0x00000800 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_48M 0x03000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#endif - -/* END */ +#define SZ_48M (SZ_32M + SZ_16M) diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 96ed521f2408..a87664f54f93 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -14,8 +14,6 @@ #include <linux/cpumask.h> #include <linux/thread_info.h> -#include <mach/smp.h> - #ifndef CONFIG_SMP # error "<asm/smp.h> included in non-SMP build" #endif @@ -47,9 +45,9 @@ extern void smp_init_cpus(void); /* - * Raise an IPI cross call on CPUs in callmap. + * Provide a function to raise an IPI cross call on CPUs in callmap. */ -extern void smp_cross_call(const struct cpumask *mask, int ipi); +extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int)); /* * Boot a secondary CPU, and assign it the specified idle task. diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h index fdd3820edff8..65fa3c88095c 100644 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h @@ -5,6 +5,8 @@ #error SMP not supported on pre-ARMv6 CPUs #endif +#include <asm/processor.h> + /* * sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K * extensions, so when running on UP, we have to patch these instructions away. diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 885be097769d..832888d0c20c 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -159,7 +159,7 @@ extern unsigned int user_debug; #include <mach/barriers.h> #elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP) #define mb() do { dsb(); outer_sync(); } while (0) -#define rmb() dmb() +#define rmb() dsb() #define wmb() mb() #else #include <asm/memory.h> diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c index 31a316c1777b..0f107dcb0347 100644 --- a/arch/arm/kernel/leds.c +++ b/arch/arm/kernel/leds.c @@ -10,6 +10,7 @@ #include <linux/module.h> #include <linux/init.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <asm/leds.h> @@ -69,36 +70,37 @@ static ssize_t leds_store(struct sys_device *dev, static SYSDEV_ATTR(event, 0200, NULL, leds_store); -static int leds_suspend(struct sys_device *dev, pm_message_t state) +static struct sysdev_class leds_sysclass = { + .name = "leds", +}; + +static struct sys_device leds_device = { + .id = 0, + .cls = &leds_sysclass, +}; + +static int leds_suspend(void) { leds_event(led_stop); return 0; } -static int leds_resume(struct sys_device *dev) +static void leds_resume(void) { leds_event(led_start); - return 0; } -static int leds_shutdown(struct sys_device *dev) +static void leds_shutdown(void) { leds_event(led_halted); - return 0; } -static struct sysdev_class leds_sysclass = { - .name = "leds", +static struct syscore_ops leds_syscore_ops = { .shutdown = leds_shutdown, .suspend = leds_suspend, .resume = leds_resume, }; -static struct sys_device leds_device = { - .id = 0, - .cls = &leds_sysclass, -}; - static int __init leds_init(void) { int ret; @@ -107,6 +109,8 @@ static int __init leds_init(void) ret = sysdev_register(&leds_device); if (ret == 0) ret = sysdev_create_file(&leds_device, &attr_event); + if (ret == 0) + register_syscore_ops(&leds_syscore_ops); return ret; } diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 139e3c827369..d53c0abc4dd3 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -560,11 +560,6 @@ static int armpmu_event_init(struct perf_event *event) event->destroy = hw_perf_event_destroy; if (!atomic_inc_not_zero(&active_events)) { - if (atomic_read(&active_events) > armpmu->num_events) { - atomic_dec(&active_events); - return -ENOSPC; - } - mutex_lock(&pmu_reserve_mutex); if (atomic_read(&active_events) == 0) { err = armpmu_reserve_hardware(); diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index cb8398317644..0340224cf73c 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -597,19 +597,13 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info, return err; } -static inline void setup_syscall_restart(struct pt_regs *regs) -{ - regs->ARM_r0 = regs->ARM_ORIG_r0; - regs->ARM_pc -= thumb_mode(regs) ? 2 : 4; -} - /* * OK, we're invoking a handler */ static int handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *oldset, - struct pt_regs * regs, int syscall) + struct pt_regs * regs) { struct thread_info *thread = current_thread_info(); struct task_struct *tsk = current; @@ -617,26 +611,6 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, int ret; /* - * If we were from a system call, check for system call restarting... - */ - if (syscall) { - switch (regs->ARM_r0) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - regs->ARM_r0 = -EINTR; - break; - case -ERESTARTSYS: - if (!(ka->sa.sa_flags & SA_RESTART)) { - regs->ARM_r0 = -EINTR; - break; - } - /* fallthrough */ - case -ERESTARTNOINTR: - setup_syscall_restart(regs); - } - } - - /* * translate the signal */ if (usig < 32 && thread->exec_domain && thread->exec_domain->signal_invmap) @@ -685,6 +659,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, */ static void do_signal(struct pt_regs *regs, int syscall) { + unsigned int retval = 0, continue_addr = 0, restart_addr = 0; struct k_sigaction ka; siginfo_t info; int signr; @@ -698,18 +673,61 @@ static void do_signal(struct pt_regs *regs, int syscall) if (!user_mode(regs)) return; + /* + * If we were from a system call, check for system call restarting... + */ + if (syscall) { + continue_addr = regs->ARM_pc; + restart_addr = continue_addr - (thumb_mode(regs) ? 2 : 4); + retval = regs->ARM_r0; + + /* + * Prepare for system call restart. We do this here so that a + * debugger will see the already changed PSW. + */ + switch (retval) { + case -ERESTARTNOHAND: + case -ERESTARTSYS: + case -ERESTARTNOINTR: + regs->ARM_r0 = regs->ARM_ORIG_r0; + regs->ARM_pc = restart_addr; + break; + case -ERESTART_RESTARTBLOCK: + regs->ARM_r0 = -EINTR; + break; + } + } + if (try_to_freeze()) goto no_signal; + /* + * Get the signal to deliver. When running under ptrace, at this + * point the debugger may change all our registers ... + */ signr = get_signal_to_deliver(&info, &ka, regs, NULL); if (signr > 0) { sigset_t *oldset; + /* + * Depending on the signal settings we may need to revert the + * decision to restart the system call. But skip this if a + * debugger has chosen to restart at a different PC. + */ + if (regs->ARM_pc == restart_addr) { + if (retval == -ERESTARTNOHAND + || (retval == -ERESTARTSYS + && !(ka.sa.sa_flags & SA_RESTART))) { + regs->ARM_r0 = -EINTR; + regs->ARM_pc = continue_addr; + } + } + if (test_thread_flag(TIF_RESTORE_SIGMASK)) oldset = ¤t->saved_sigmask; else oldset = ¤t->blocked; - if (handle_signal(signr, &ka, &info, oldset, regs, syscall) == 0) { + if (handle_signal(signr, &ka, &info, oldset, regs) == 0) { /* * A signal was successfully delivered; the saved * sigmask will have been stored in the signal frame, @@ -723,11 +741,14 @@ static void do_signal(struct pt_regs *regs, int syscall) } no_signal: - /* - * No signal to deliver to the process - restart the syscall. - */ if (syscall) { - if (regs->ARM_r0 == -ERESTART_RESTARTBLOCK) { + /* + * Handle restarting a different system call. As above, + * if a debugger has chosen to restart at a different PC, + * ignore the restart. + */ + if (retval == -ERESTART_RESTARTBLOCK + && regs->ARM_pc == continue_addr) { if (thumb_mode(regs)) { regs->ARM_r7 = __NR_restart_syscall - __NR_SYSCALL_BASE; regs->ARM_pc -= 2; @@ -750,11 +771,6 @@ static void do_signal(struct pt_regs *regs, int syscall) #endif } } - if (regs->ARM_r0 == -ERESTARTNOHAND || - regs->ARM_r0 == -ERESTARTSYS || - regs->ARM_r0 == -ERESTARTNOINTR) { - setup_syscall_restart(regs); - } /* If there's no signal to deliver, we just put the saved sigmask * back. diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index f29b8a29b174..d439a8f4c078 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -376,6 +376,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } +static void (*smp_cross_call)(const struct cpumask *, unsigned int); + +void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) +{ + smp_cross_call = fn; +} + void arch_send_call_function_ipi_mask(const struct cpumask *mask) { smp_cross_call(mask, IPI_CALL_FUNC); @@ -560,10 +567,7 @@ asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) break; case IPI_RESCHEDULE: - /* - * nothing more to do - eveything is - * done on the interrupt return path - */ + scheduler_ipi(); break; case IPI_CALL_FUNC: diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 1ff46cabc7ef..cb634c3e28e9 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -21,7 +21,7 @@ #include <linux/timex.h> #include <linux/errno.h> #include <linux/profile.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/timer.h> #include <linux/irq.h> @@ -115,48 +115,37 @@ void timer_tick(void) #endif #if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS) -static int timer_suspend(struct sys_device *dev, pm_message_t state) +static int timer_suspend(void) { - struct sys_timer *timer = container_of(dev, struct sys_timer, dev); - - if (timer->suspend != NULL) - timer->suspend(); + if (system_timer->suspend) + system_timer->suspend(); return 0; } -static int timer_resume(struct sys_device *dev) +static void timer_resume(void) { - struct sys_timer *timer = container_of(dev, struct sys_timer, dev); - - if (timer->resume != NULL) - timer->resume(); - - return 0; + if (system_timer->resume) + system_timer->resume(); } #else #define timer_suspend NULL #define timer_resume NULL #endif -static struct sysdev_class timer_sysclass = { - .name = "timer", +static struct syscore_ops timer_syscore_ops = { .suspend = timer_suspend, .resume = timer_resume, }; -static int __init timer_init_sysfs(void) +static int __init timer_init_syscore_ops(void) { - int ret = sysdev_class_register(&timer_sysclass); - if (ret == 0) { - system_timer->dev.cls = &timer_sysclass; - ret = sysdev_register(&system_timer->dev); - } + register_syscore_ops(&timer_syscore_ops); - return ret; + return 0; } -device_initcall(timer_init_sysfs); +device_initcall(timer_init_syscore_ops); void __init time_init(void) { diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 3b54ad19d489..d52eec268b47 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -234,7 +234,6 @@ static int __die(const char *str, int err, struct thread_info *thread, struct pt printk(KERN_EMERG "Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", str, err, ++die_counter); - sysfs_printk_last_file(); /* trap and error numbers are mostly meaningless on ARM */ ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, SIGSEGV); diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c index 73eb066d2329..a604b9ebb501 100644 --- a/arch/arm/mach-bcmring/arch.c +++ b/arch/arm/mach-bcmring/arch.c @@ -169,6 +169,7 @@ MACHINE_START(BCMRING, "BCMRING") /* Maintainer: Broadcom Corporation */ .fixup = bcmring_fixup, .map_io = bcmring_map_io, + .init_early = bcmring_init_early, .init_irq = bcmring_init_irq, .timer = &bcmring_timer, .init_machine = bcmring_init_machine diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index 8fc2035759fb..43eadbcc29ed 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c @@ -28,8 +28,6 @@ #include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/amba/bus.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> #include <linux/clkdev.h> #include <mach/csp/mm_addr.h> @@ -37,6 +35,7 @@ #include <linux/io.h> #include <asm/irq.h> #include <asm/hardware/arm_timer.h> +#include <asm/hardware/timer-sp.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -97,6 +96,35 @@ static struct clk dummy_apb_pclk = { .mode = CLK_MODE_XTAL, }; +/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */ +#if defined(CONFIG_ARCH_FPGA11107) +/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */ +/* slow down Linux's sense of time */ +#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) +#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) +#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30) +#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30) +#else +#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ +#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ +#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ +#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000) +#endif + +static struct clk sp804_timer012_clk = { + .name = "sp804-timer-0,1,2", + .type = CLK_TYPE_PRIMARY, + .mode = CLK_MODE_XTAL, + .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000, +}; + +static struct clk sp804_timer3_clk = { + .name = "sp804-timer-3", + .type = CLK_TYPE_PRIMARY, + .mode = CLK_MODE_XTAL, + .rate_hz = TIMER3_FREQUENCY_KHZ * 1000, +}; + static struct clk_lookup lookups[] = { { /* Bus clock */ .con_id = "apb_pclk", @@ -107,6 +135,18 @@ static struct clk_lookup lookups[] = { }, { /* UART1 */ .dev_id = "uartb", .clk = &uart_clk, + }, { /* SP804 timer 0 */ + .dev_id = "sp804", + .con_id = "timer0", + .clk = &sp804_timer012_clk, + }, { /* SP804 timer 1 */ + .dev_id = "sp804", + .con_id = "timer1", + .clk = &sp804_timer012_clk, + }, { /* SP804 timer 3 */ + .dev_id = "sp804", + .con_id = "timer3", + .clk = &sp804_timer3_clk, } }; @@ -151,8 +191,6 @@ void __init bcmring_amba_init(void) chipcHw_busInterfaceClockEnable(bus_clock); - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); @@ -162,170 +200,18 @@ void __init bcmring_amba_init(void) /* * Where is the timer (VA)? */ -#define TIMER0_VA_BASE MM_IO_BASE_TMR -#define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20) -#define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40) -#define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60) - -/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */ -#if defined(CONFIG_ARCH_FPGA11107) -/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */ -/* slow down Linux's sense of time */ -#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) -#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) -#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30) -#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30) -#else -#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ -#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ -#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ -#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000) -#endif - -#define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ - -/* - * These are useconds NOT ticks. - * - */ -#define mSEC_1 1000 -#define mSEC_5 (mSEC_1 * 5) -#define mSEC_10 (mSEC_1 * 10) -#define mSEC_25 (mSEC_1 * 25) -#define SEC_1 (mSEC_1 * 1000) - -/* - * How long is the timer interval? - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) -#if TIMER_INTERVAL >= 0x100000 -#define TIMER_RELOAD (TIMER_INTERVAL >> 8) -#define TIMER_DIVISOR (TIMER_CTRL_DIV256) -#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) -#elif TIMER_INTERVAL >= 0x10000 -#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ -#define TIMER_DIVISOR (TIMER_CTRL_DIV16) -#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) -#else -#define TIMER_RELOAD (TIMER_INTERVAL) -#define TIMER_DIVISOR (TIMER_CTRL_DIV1) -#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) -#endif - -static void timer_set_mode(enum clock_event_mode mode, - struct clock_event_device *clk) -{ - unsigned long ctrl; - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); - - ctrl = TIMER_CTRL_PERIODIC; - ctrl |= - TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE | - TIMER_CTRL_ENABLE; - break; - case CLOCK_EVT_MODE_ONESHOT: - /* period set, and timer enabled in 'next_event' hook */ - ctrl = TIMER_CTRL_ONESHOT; - ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE; - break; - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - default: - ctrl = 0; - } - - writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); -} - -static int timer_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); - - writel(evt, TIMER0_VA_BASE + TIMER_LOAD); - writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); - - return 0; -} - -static struct clock_event_device timer0_clockevent = { - .name = "timer0", - .shift = 32, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = timer_set_mode, - .set_next_event = timer_set_next_event, -}; - -/* - * IRQ handler for the timer - */ -static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &timer0_clockevent; - - writel(1, TIMER0_VA_BASE + TIMER_INTCLR); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction bcmring_timer_irq = { - .name = "bcmring Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = bcmring_timer_interrupt, -}; - -static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs) -{ - return ~readl(TIMER1_VA_BASE + TIMER_VALUE); -} - -static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs) -{ - return ~readl(TIMER3_VA_BASE + TIMER_VALUE); -} - -static struct clocksource clocksource_bcmring_timer1 = { - .name = "timer1", - .rating = 200, - .read = bcmring_get_cycles_timer1, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static struct clocksource clocksource_bcmring_timer3 = { - .name = "timer3", - .rating = 100, - .read = bcmring_get_cycles_timer3, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; +#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR) +#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20)) +#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40)) +#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60)) static int __init bcmring_clocksource_init(void) { /* setup timer1 as free-running clocksource */ - writel(0, TIMER1_VA_BASE + TIMER_CTRL); - writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD); - writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE); - writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - TIMER1_VA_BASE + TIMER_CTRL); - - clocksource_register_khz(&clocksource_bcmring_timer1, - TIMER1_FREQUENCY_MHZ * 1000); + sp804_clocksource_init(TIMER1_VA_BASE, "timer1"); /* setup timer3 as free-running clocksource */ - writel(0, TIMER3_VA_BASE + TIMER_CTRL); - writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); - writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); - writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, - TIMER3_VA_BASE + TIMER_CTRL); - - clocksource_register_khz(&clocksource_bcmring_timer3, - TIMER3_FREQUENCY_KHZ); + sp804_clocksource_init(TIMER3_VA_BASE, "timer3"); return 0; } @@ -347,21 +233,16 @@ void __init bcmring_init_timer(void) /* * Make irqs happen for the system timer */ - setup_irq(IRQ_TIMER0, &bcmring_timer_irq); - bcmring_clocksource_init(); - timer0_clockevent.mult = - div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); - timer0_clockevent.max_delta_ns = - clockevent_delta2ns(0xffffffff, &timer0_clockevent); - timer0_clockevent.min_delta_ns = - clockevent_delta2ns(0xf, &timer0_clockevent); - - timer0_clockevent.cpumask = cpumask_of(0); - clockevents_register_device(&timer0_clockevent); + sp804_clockevents_register(TIMER0_VA_BASE, IRQ_TIMER0, "timer0"); } struct sys_timer bcmring_timer = { .init = bcmring_init_timer, }; + +void __init bcmring_init_early(void) +{ + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); +} diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h index b197ba48e36e..e0e02c48f9b1 100644 --- a/arch/arm/mach-bcmring/core.h +++ b/arch/arm/mach-bcmring/core.h @@ -25,6 +25,7 @@ void __init bcmring_amba_init(void); void __init bcmring_map_io(void); void __init bcmring_init_irq(void); +void __init bcmring_init_early(void); extern struct sys_timer bcmring_timer; #endif diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c index 0a95be1512bb..41669ecc1f91 100644 --- a/arch/arm/mach-davinci/cpufreq.c +++ b/arch/arm/mach-davinci/cpufreq.c @@ -94,9 +94,7 @@ static int davinci_target(struct cpufreq_policy *policy, if (freqs.old == freqs.new) return ret; - cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, - dev_driver_string(cpufreq.dev), - "transition: %u --> %u\n", freqs.old, freqs.new); + dev_dbg(&cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new); ret = cpufreq_frequency_table_target(policy, pdata->freq_table, freqs.new, relation, &idx); diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h index 78822723f382..491249ef209c 100644 --- a/arch/arm/mach-davinci/include/mach/memory.h +++ b/arch/arm/mach-davinci/include/mach/memory.h @@ -41,27 +41,11 @@ */ #define CONSISTENT_DMA_SIZE (14<<20) -#ifndef __ASSEMBLY__ /* * Restrict DMA-able region to workaround silicon bug. The bug * restricts buffers available for DMA to video hardware to be * below 128M */ -static inline void -__arch_adjust_zones(unsigned long *size, unsigned long *holes) -{ - unsigned int sz = (128<<20) >> PAGE_SHIFT; - - size[1] = size[0] - sz; - size[0] = sz; -} - -#define arch_adjust_zones(zone_size, holes) \ - if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20)) - -#endif +#define ARM_DMA_ZONE_SIZE SZ_128M #endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index a5a9ff70b198..415dce37b88c 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c @@ -356,29 +356,6 @@ static int ep93xx_gpio_set_debounce(struct gpio_chip *chip, return 0; } -static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); - u8 data_reg, data_dir_reg; - int gpio, i; - - data_reg = __raw_readb(ep93xx_chip->data_reg); - data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg); - - gpio = ep93xx_chip->chip.base; - for (i = 0; i < chip->ngpio; i++, gpio++) { - int is_out = data_dir_reg & (1 << i); - int irq = gpio_to_irq(gpio); - - seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n", - chip->label, i, gpio, - gpiochip_is_requested(chip, i) ? : "", - is_out ? "out" : "in ", - (data_reg & (1<< i)) ? "hi" : "lo", - (!is_out && irq>= 0) ? "(interrupt)" : ""); - } -} - #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \ { \ .chip = { \ @@ -387,7 +364,6 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) .direction_output = ep93xx_gpio_direction_output, \ .get = ep93xx_gpio_get, \ .set = ep93xx_gpio_set, \ - .dbg_show = ep93xx_gpio_dbg_show, \ .base = base_gpio, \ .ngpio = 8, \ }, \ diff --git a/arch/arm/mach-exynos4/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h deleted file mode 100644 index a463dcebcfd3..000000000000 --- a/arch/arm/mach-exynos4/include/mach/smp.h +++ /dev/null @@ -1,19 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/smp.h - * - * Cloned from arch/arm/mach-realview/include/mach/smp.h -*/ - -#ifndef ASM_ARCH_SMP_H -#define ASM_ARCH_SMP_H __FILE__ - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c index 6d35878ec1aa..c5e65a02be8d 100644 --- a/arch/arm/mach-exynos4/platsmp.c +++ b/arch/arm/mach-exynos4/platsmp.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <asm/unified.h> @@ -104,7 +105,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the boot monitor to read the system wide flags register, * and branch to the address found there. */ - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -147,6 +148,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 10d917d9e3ad..8755ca8dd48d 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/suspend.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <asm/cacheflush.h> @@ -372,7 +373,27 @@ void exynos4_scu_enable(void __iomem *scu_base) flush_cache_all(); } -static int exynos4_pm_resume(struct sys_device *dev) +static struct sysdev_driver exynos4_pm_driver = { + .add = exynos4_pm_add, +}; + +static __init int exynos4_pm_drvinit(void) +{ + unsigned int tmp; + + s3c_pm_init(); + + /* All wakeup disable */ + + tmp = __raw_readl(S5P_WAKEUP_MASK); + tmp |= ((0xFF << 8) | (0x1F << 1)); + __raw_writel(tmp, S5P_WAKEUP_MASK); + + return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); +} +arch_initcall(exynos4_pm_drvinit); + +static void exynos4_pm_resume(void) { /* For release retention */ @@ -394,27 +415,15 @@ static int exynos4_pm_resume(struct sys_device *dev) /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); #endif - - return 0; } -static struct sysdev_driver exynos4_pm_driver = { - .add = exynos4_pm_add, +static struct syscore_ops exynos4_pm_syscore_ops = { .resume = exynos4_pm_resume, }; -static __init int exynos4_pm_drvinit(void) +static __init int exynos4_pm_syscore_init(void) { - unsigned int tmp; - - s3c_pm_init(); - - /* All wakeup disable */ - - tmp = __raw_readl(S5P_WAKEUP_MASK); - tmp |= ((0xFF << 8) | (0x1F << 1)); - __raw_writel(tmp, S5P_WAKEUP_MASK); - - return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver); + register_syscore_ops(&exynos4_pm_syscore_ops); + return 0; } -arch_initcall(exynos4_pm_drvinit); +arch_initcall(exynos4_pm_syscore_init); diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig index bdd257921cfb..46adca068f2c 100644 --- a/arch/arm/mach-footbridge/Kconfig +++ b/arch/arm/mach-footbridge/Kconfig @@ -4,6 +4,7 @@ menu "Footbridge Implementations" config ARCH_CATS bool "CATS" + select CLKSRC_I8253 select FOOTBRIDGE_HOST select ISA select ISA_DMA @@ -59,6 +60,7 @@ config ARCH_EBSA285_HOST config ARCH_NETWINDER bool "NetWinder" + select CLKSRC_I8253 select FOOTBRIDGE_HOST select ISA select ISA_DMA diff --git a/arch/arm/mach-footbridge/isa-timer.c b/arch/arm/mach-footbridge/isa-timer.c index 441c6ce0d555..7020f1a3feca 100644 --- a/arch/arm/mach-footbridge/isa-timer.c +++ b/arch/arm/mach-footbridge/isa-timer.c @@ -10,53 +10,16 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/io.h> +#include <linux/spinlock.h> #include <linux/timex.h> #include <asm/irq.h> - +#include <asm/i8253.h> #include <asm/mach/time.h> #include "common.h" -#define PIT_MODE 0x43 -#define PIT_CH0 0x40 - -#define PIT_LATCH ((PIT_TICK_RATE + HZ / 2) / HZ) - -static cycle_t pit_read(struct clocksource *cs) -{ - unsigned long flags; - static int old_count; - static u32 old_jifs; - int count; - u32 jifs; - - raw_local_irq_save(flags); - - jifs = jiffies; - outb_p(0x00, PIT_MODE); /* latch the count */ - count = inb_p(PIT_CH0); /* read the latched count */ - count |= inb_p(PIT_CH0) << 8; - - if (count > old_count && jifs == old_jifs) - count = old_count; - - old_count = count; - old_jifs = jifs; - - raw_local_irq_restore(flags); - - count = (PIT_LATCH - 1) - count; - - return (cycle_t)(jifs * PIT_LATCH) + count; -} - -static struct clocksource pit_cs = { - .name = "pit", - .rating = 110, - .read = pit_read, - .mask = CLOCKSOURCE_MASK(32), -}; +DEFINE_RAW_SPINLOCK(i8253_lock); static void pit_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) @@ -121,7 +84,7 @@ static void __init isa_timer_init(void) pit_ce.max_delta_ns = clockevent_delta2ns(0x7fff, &pit_ce); pit_ce.min_delta_ns = clockevent_delta2ns(0x000f, &pit_ce); - clocksource_register_hz(&pit_cs, PIT_TICK_RATE); + clocksource_i8253_init(); setup_irq(pit_ce.irq, &pit_timer_irq); clockevents_register_device(&pit_ce); diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h index 9d3687651462..b0b3baec9acf 100644 --- a/arch/arm/mach-h720x/include/mach/memory.h +++ b/arch/arm/mach-h720x/include/mach/memory.h @@ -13,7 +13,6 @@ * There should not be more than (0xd0000000 - 0xc0000000) * bytes of RAM. */ -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) +#define ARM_DMA_ZONE_SIZE SZ_256M #endif diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index d701d32a07f1..dfd18f3b50e8 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -4,6 +4,7 @@ menu "Integrator Options" config ARCH_INTEGRATOR_AP bool "Support Integrator/AP and Integrator/PP2 platforms" + select CLKSRC_MMIO select MIGHT_HAVE_PCI help Include support for the ARM(R) Integrator/AP and diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 980803ff348c..2fbbdd5eac35 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -24,13 +24,14 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/string.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/amba/bus.h> #include <linux/amba/kmi.h> #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/mtd/physmap.h> #include <mach/hardware.h> #include <mach/platform.h> @@ -43,7 +44,6 @@ #include <mach/lm.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -180,13 +180,13 @@ static void __init ap_init_irq(void) #ifdef CONFIG_PM static unsigned long ic_irq_enable; -static int irq_suspend(struct sys_device *dev, pm_message_t state) +static int irq_suspend(void) { ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); return 0; } -static int irq_resume(struct sys_device *dev) +static void irq_resume(void) { /* disable all irq sources */ writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); @@ -194,33 +194,25 @@ static int irq_resume(struct sys_device *dev) writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); - return 0; } #else #define irq_suspend NULL #define irq_resume NULL #endif -static struct sysdev_class irq_class = { - .name = "irq", +static struct syscore_ops irq_syscore_ops = { .suspend = irq_suspend, .resume = irq_resume, }; -static struct sys_device irq_device = { - .id = 0, - .cls = &irq_class, -}; - -static int __init irq_init_sysfs(void) +static int __init irq_syscore_init(void) { - int ret = sysdev_class_register(&irq_class); - if (ret == 0) - ret = sysdev_register(&irq_device); - return ret; + register_syscore_ops(&irq_syscore_ops); + + return 0; } -device_initcall(irq_init_sysfs); +device_initcall(irq_syscore_init); /* * Flash handling. @@ -230,7 +222,7 @@ device_initcall(irq_init_sysfs); #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) -static int ap_flash_init(void) +static int ap_flash_init(struct platform_device *dev) { u32 tmp; @@ -247,7 +239,7 @@ static int ap_flash_init(void) return 0; } -static void ap_flash_exit(void) +static void ap_flash_exit(struct platform_device *dev) { u32 tmp; @@ -263,15 +255,14 @@ static void ap_flash_exit(void) } } -static void ap_flash_set_vpp(int on) +static void ap_flash_set_vpp(struct platform_device *pdev, int on) { void __iomem *reg = on ? SC_CTRLS : SC_CTRLC; writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); } -static struct flash_platform_data ap_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data ap_flash_data = { .width = 4, .init = ap_flash_init, .exit = ap_flash_exit, @@ -285,7 +276,7 @@ static struct resource cfi_flash_resource = { }; static struct platform_device cfi_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &ap_flash_data, @@ -343,25 +334,9 @@ static void __init ap_init(void) static unsigned long timer_reload; -static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE; - -static cycle_t timersp_read(struct clocksource *cs) -{ - return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff); -} - -static struct clocksource clocksource_timersp = { - .name = "timer2", - .rating = 200, - .read = timersp_read, - .mask = CLOCKSOURCE_MASK(16), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static void integrator_clocksource_init(u32 khz) { - struct clocksource *cs = &clocksource_timersp; - void __iomem *base = clksrc_base; + void __iomem *base = (void __iomem *)TIMER2_VA_BASE; u32 ctrl = TIMER_CTRL_ENABLE; if (khz >= 1500) { @@ -372,7 +347,8 @@ static void integrator_clocksource_init(u32 khz) writel(ctrl, base + TIMER_CTRL); writel(0xffff, base + TIMER_LOAD); - clocksource_register_khz(cs, khz); + clocksource_mmio_init(base + TIMER_VALUE, "timer2", + khz * 1000, 200, 16, clocksource_mmio_readl_down); } static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 9e3ce26023e8..4eb03ab5cb46 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/gfp.h> #include <linux/clkdev.h> +#include <linux/mtd/physmap.h> #include <mach/hardware.h> #include <mach/platform.h> @@ -35,7 +36,6 @@ #include <mach/lm.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -229,17 +229,24 @@ static struct clk cp_auxclk = { .vcoreg = CM_AUXOSC, }; +static struct clk sp804_clk = { + .rate = 1000000, +}; + static struct clk_lookup cp_lookups[] = { { /* CLCD */ .dev_id = "mb:c0", .clk = &cp_auxclk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .clk = &sp804_clk, }, }; /* * Flash handling. */ -static int intcp_flash_init(void) +static int intcp_flash_init(struct platform_device *dev) { u32 val; @@ -250,7 +257,7 @@ static int intcp_flash_init(void) return 0; } -static void intcp_flash_exit(void) +static void intcp_flash_exit(struct platform_device *dev) { u32 val; @@ -259,7 +266,7 @@ static void intcp_flash_exit(void) writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); } -static void intcp_flash_set_vpp(int on) +static void intcp_flash_set_vpp(struct platform_device *pdev, int on) { u32 val; @@ -271,8 +278,7 @@ static void intcp_flash_set_vpp(int on) writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); } -static struct flash_platform_data intcp_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data intcp_flash_data = { .width = 4, .init = intcp_flash_init, .exit = intcp_flash_exit, @@ -286,7 +292,7 @@ static struct resource intcp_flash_resource = { }; static struct platform_device intcp_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &intcp_flash_data, @@ -476,8 +482,8 @@ static void __init intcp_timer_init(void) writel(0, TIMER1_VA_BASE + TIMER_CTRL); writel(0, TIMER2_VA_BASE + TIMER_CTRL); - sp804_clocksource_init(TIMER2_VA_BASE); - sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1); + sp804_clocksource_init(TIMER2_VA_BASE, "timer2"); + sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1"); } static struct sys_timer cp_timer = { diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index a54b3db80366..e9a589395723 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -342,29 +342,6 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); } -/* - * Only first 64MB of memory can be accessed via PCI. - * We use GFP_DMA to allocate safe buffers to do map/unmap. - * This is really ugly and we need a better way of specifying - * DMA-capable regions of memory. - */ -void __init ixp4xx_adjust_zones(unsigned long *zone_size, - unsigned long *zhole_size) -{ - unsigned int sz = SZ_64M >> PAGE_SHIFT; - - /* - * Only adjust if > 64M on current system - */ - if (zone_size[0] <= sz) - return; - - zone_size[1] = zone_size[0] - sz; - zone_size[0] = sz; - zhole_size[1] = zhole_size[0]; - zhole_size[0] = 0; -} - void __init ixp4xx_pci_preinit(void) { unsigned long cpuid = read_cpuid_id(); diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index ed19bc314318..74ed81a3cb1a 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -419,26 +419,14 @@ static void notrace ixp4xx_update_sched_clock(void) /* * clocksource */ -static cycle_t ixp4xx_get_cycles(struct clocksource *cs) -{ - return *IXP4XX_OSTS; -} - -static struct clocksource clocksource_ixp4xx = { - .name = "OSTS", - .rating = 200, - .read = ixp4xx_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ; EXPORT_SYMBOL(ixp4xx_timer_freq); static void __init ixp4xx_clocksource_init(void) { init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq); - clocksource_register_hz(&clocksource_ixp4xx, ixp4xx_timer_freq); + clocksource_mmio_init(&IXP4XX_OSTS, "OSTS", ixp4xx_timer_freq, 200, 32, + clocksource_mmio_readl_up); } /* diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h index 6d388c9d0e20..34e79404671a 100644 --- a/arch/arm/mach-ixp4xx/include/mach/memory.h +++ b/arch/arm/mach-ixp4xx/include/mach/memory.h @@ -14,16 +14,8 @@ */ #define PLAT_PHYS_OFFSET UL(0x00000000) -#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) - -void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(size, holes) \ - ixp4xx_adjust_zones(size, holes) - -#define ISA_DMA_THRESHOLD (SZ_64M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) - +#ifdef CONFIG_PCI +#define ARM_DMA_ZONE_SIZE SZ_64M #endif #endif diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index 6162ac308c20..b42c909bbeeb 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c @@ -31,19 +31,6 @@ #include <mach/platform.h> #include "common.h" -static cycle_t lpc32xx_clksrc_read(struct clocksource *cs) -{ - return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE)); -} - -static struct clocksource lpc32xx_clksrc = { - .name = "lpc32xx_clksrc", - .rating = 300, - .read = lpc32xx_clksrc_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static int lpc32xx_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) { @@ -170,7 +157,9 @@ static void __init lpc32xx_timer_init(void) __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); - clocksource_register_hz(&lpc32xx_clksrc, clkrate); + + clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE), + "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up); } struct sys_timer lpc32xx_timer = { diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h deleted file mode 100644 index 3c01000ecc80..000000000000 --- a/arch/arm/mach-msm/include/mach/smp.h +++ /dev/null @@ -1,23 +0,0 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARCH_MSM_SMP_H -#define __ASM_ARCH_MSM_SMP_H - -#include <asm/hardware/gic.h> - -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 0f427bc94447..2034098cf015 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -119,7 +119,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the boot monitor to read the system wide flags register, * and branch to the address found there. */ - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -151,6 +151,8 @@ void __init smp_init_cpus(void) for (i = 0; i < NR_CPUS; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 4522fbb235d5..edacefac2270 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -17,6 +17,16 @@ config SOC_IMX28 comment "MXS platforms:" +config MACH_STMP378X_DEVB + bool "Support STMP378x_devb Platform" + select SOC_IMX23 + select MXS_HAVE_AMBA_DUART + select MXS_HAVE_PLATFORM_AUART + select MXS_HAVE_PLATFORM_MXS_MMC + help + Include support for STMP378x-devb platform. This includes specific + configurations for the board and its peripherals. + config MACH_MX23EVK bool "Support MX23EVK Platform" select SOC_IMX23 diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 2f1f6141ca71..58e892376bf2 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o +obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o obj-$(CONFIG_MODULE_TX28) += module-tx28.o diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c new file mode 100644 index 000000000000..7f38d82b69af --- /dev/null +++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c @@ -0,0 +1,120 @@ +/* + * board setup for STMP378x-Development-Board + * + * based on mx23evk board setup and information gained form the original + * plat-stmp based board setup, now converted to mach-mxs. + * + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/platform_device.h> +#include <linux/gpio.h> +#include <linux/irq.h> +#include <linux/spi/spi.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include <mach/common.h> +#include <mach/iomux-mx23.h> + +#include "devices-mx23.h" + +#define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) +#define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) + +#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL) + +static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = { + /* duart (extended setup missing in old boardcode, too */ + MX23_PAD_PWM0__DUART_RX, + MX23_PAD_PWM1__DUART_TX, + + /* auart */ + MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART, + MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART, + MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART, + MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART, + + /* mmc */ + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_CMD__SSP1_CMD | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + MX23_PAD_SSP1_DETECT__SSP1_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_SSP1_SCK__SSP1_SCK | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */ + MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */ +}; + +static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = { + .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT, +}; + +static struct spi_board_info spi_board_info[] __initdata = { +#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) + { + .modalias = "enc28j60", + .max_speed_hz = 6 * 1000 * 1000, + .bus_num = 1, + .chip_select = 0, + .platform_data = NULL, + }, +#endif +}; + +static void __init stmp378x_dvb_init(void) +{ + int ret; + + mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads, + ARRAY_SIZE(stmp378x_dvb_pads)); + + mx23_add_duart(); + mx23_add_auart0(); + + /* power on mmc slot */ + ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER, + GPIOF_OUT_INIT_LOW, "mmc0-slot-power"); + if (ret) + pr_warn("could not power mmc (%d)\n", ret); + + mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata); + + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); +} + +static void __init stmp378x_dvb_timer_init(void) +{ + mx23_clocks_init(); +} + +static struct sys_timer stmp378x_dvb_timer = { + .init = stmp378x_dvb_timer_init, +}; + +MACHINE_START(STMP378X, "STMP378X") + .map_io = mx23_map_io, + .init_irq = mx23_init_irq, + .init_machine = stmp378x_dvb_init, + .timer = &stmp378x_dvb_timer, +MACHINE_END diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c index 13647f301860..cace0d2e5a55 100644 --- a/arch/arm/mach-mxs/timer.c +++ b/arch/arm/mach-mxs/timer.c @@ -101,11 +101,6 @@ static cycle_t timrotv1_get_cycles(struct clocksource *cs) & 0xffff0000) >> 16); } -static cycle_t timrotv2_get_cycles(struct clocksource *cs) -{ - return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1)); -} - static int timrotv1_set_next_event(unsigned long evt, struct clock_event_device *dev) { @@ -230,8 +225,8 @@ static int __init mxs_clockevent_init(struct clk *timer_clk) static struct clocksource clocksource_mxs = { .name = "mxs_timer", .rating = 200, - .read = timrotv2_get_cycles, - .mask = CLOCKSOURCE_MASK(32), + .read = timrotv1_get_cycles, + .mask = CLOCKSOURCE_MASK(16), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; @@ -239,12 +234,11 @@ static int __init mxs_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - if (timrot_is_v1()) { - clocksource_mxs.read = timrotv1_get_cycles; - clocksource_mxs.mask = CLOCKSOURCE_MASK(16); - } - - clocksource_register_hz(&clocksource_mxs, c); + if (timrot_is_v1()) + clocksource_register_hz(&clocksource_mxs, c); + else + clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1), + "mxs_timer", c, 200, 32, clocksource_mmio_readl_down); return 0; } diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c index f12f22d09b6c..e24c141ba489 100644 --- a/arch/arm/mach-netx/time.c +++ b/arch/arm/mach-netx/time.c @@ -104,19 +104,6 @@ static struct irqaction netx_timer_irq = { .handler = netx_timer_interrupt, }; -cycle_t netx_get_cycles(struct clocksource *cs) -{ - return readl(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE)); -} - -static struct clocksource clocksource_netx = { - .name = "netx_timer", - .rating = 200, - .read = netx_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - /* * Set up timer interrupt */ @@ -150,7 +137,8 @@ static void __init netx_timer_init(void) writel(NETX_GPIO_COUNTER_CTRL_RUN, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); - clocksource_register_hz(&clocksource_netx, CLOCK_TICK_RATE); + clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE), + "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, netx_clockevent.shift); diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig deleted file mode 100644 index dd0cd5ac4b8b..000000000000 --- a/arch/arm/mach-ns9xxx/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -if ARCH_NS9XXX - -menu "NS9xxx Implementations" - -config NS9XXX_HAVE_SERIAL8250 - bool - -config PROCESSOR_NS9360 - bool - -config MODULE_CC9P9360 - bool - select PROCESSOR_NS9360 - -config BOARD_A9M9750DEV - select NS9XXX_HAVE_SERIAL8250 - bool - -config BOARD_JSCC9P9360 - bool - -config MACH_CC9P9360DEV - bool "ConnectCore 9P 9360 on an A9M9750 Devboard" - select MODULE_CC9P9360 - select BOARD_A9M9750DEV - help - Say Y here if you are using the Digi ConnectCore 9P 9360 - on an A9M9750 Development Board. - -config MACH_CC9P9360JS - bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard" - select MODULE_CC9P9360 - select BOARD_JSCC9P9360 - help - Say Y here if you are using the Digi ConnectCore 9P 9360 - on an JSCC9P9360 Development Board. - -endmenu - -endif diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile deleted file mode 100644 index 41efaf9ad50b..000000000000 --- a/arch/arm/mach-ns9xxx/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -obj-y := clock.o generic.o gpio.o irq.o - -obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o -obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o - -obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o - -obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o -obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o - -# platform devices -obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o diff --git a/arch/arm/mach-ns9xxx/Makefile.boot b/arch/arm/mach-ns9xxx/Makefile.boot deleted file mode 100644 index 54654919229b..000000000000 --- a/arch/arm/mach-ns9xxx/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ -zreladdr-y := 0x8000 -params_phys-y := 0x100 diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c deleted file mode 100644 index e27687d53504..000000000000 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-a9m9750dev.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/irq.h> - -#include <asm/mach/map.h> -#include <asm/gpio.h> - -#include <mach/board.h> -#include <mach/processor-ns9360.h> -#include <mach/regs-sys-ns9360.h> -#include <mach/regs-mem.h> -#include <mach/regs-bbu.h> -#include <mach/regs-board-a9m9750dev.h> - -#include "board-a9m9750dev.h" - -static struct map_desc board_a9m9750dev_io_desc[] __initdata = { - { /* FPGA on CS0 */ - .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)), - .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)), - .length = NS9XXX_CS0STAT_LENGTH, - .type = MT_DEVICE, - }, -}; - -void __init board_a9m9750dev_map_io(void) -{ - iotable_init(board_a9m9750dev_io_desc, - ARRAY_SIZE(board_a9m9750dev_io_desc)); -} - -static void a9m9750dev_fpga_ack_irq(struct irq_data *d) -{ - /* nothing */ -} - -static void a9m9750dev_fpga_mask_irq(struct irq_data *d) -{ - u8 ier; - - ier = __raw_readb(FPGA_IER); - - ier &= ~(1 << (d->irq - FPGA_IRQ(0))); - - __raw_writeb(ier, FPGA_IER); -} - -static void a9m9750dev_fpga_maskack_irq(struct irq_data *d) -{ - a9m9750dev_fpga_mask_irq(d); - a9m9750dev_fpga_ack_irq(d); -} - -static void a9m9750dev_fpga_unmask_irq(struct irq_data *d) -{ - u8 ier; - - ier = __raw_readb(FPGA_IER); - - ier |= 1 << (d->irq - FPGA_IRQ(0)); - - __raw_writeb(ier, FPGA_IER); -} - -static struct irq_chip a9m9750dev_fpga_chip = { - .irq_ack = a9m9750dev_fpga_ack_irq, - .irq_mask = a9m9750dev_fpga_mask_irq, - .irq_mask_ack = a9m9750dev_fpga_maskack_irq, - .irq_unmask = a9m9750dev_fpga_unmask_irq, -}; - -static void a9m9750dev_fpga_demux_handler(unsigned int irq, - struct irq_desc *desc) -{ - u8 stat = __raw_readb(FPGA_ISR); - - desc->irq_data.chip->irq_mask_ack(&desc->irq_data); - - while (stat != 0) { - int irqno = fls(stat) - 1; - - stat &= ~(1 << irqno); - - generic_handle_irq(FPGA_IRQ(irqno)); - } - - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -void __init board_a9m9750dev_init_irq(void) -{ - u32 eic; - int i; - - if (gpio_request(11, "board a9m9750dev extirq2") == 0) - ns9360_gpio_configure(11, 0, 1); - else - printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n", - __func__); - - for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { - irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip, - handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - - /* IRQ_NS9XXX_EXT2: level sensitive + active low */ - eic = __raw_readl(SYS_EIC(2)); - REGSET(eic, SYS_EIC, PLTY, AL); - REGSET(eic, SYS_EIC, LVEDG, LEVEL); - __raw_writel(eic, SYS_EIC(2)); - - irq_set_chained_handler(IRQ_NS9XXX_EXT2, - a9m9750dev_fpga_demux_handler); -} - -void __init board_a9m9750dev_init_machine(void) -{ - u32 reg; - - /* setup static CS0: memory base ... */ - reg = __raw_readl(SYS_SMCSSMB(0)); - REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12); - __raw_writel(reg, SYS_SMCSSMB(0)); - - /* ... and mask */ - reg = __raw_readl(SYS_SMCSSMM(0)); - REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff); - REGSET(reg, SYS_SMCSSMM, CSEx, EN); - __raw_writel(reg, SYS_SMCSSMM(0)); - - /* setup static CS0: memory configuration */ - reg = __raw_readl(MEM_SMC(0)); - REGSET(reg, MEM_SMC, PSMC, OFF); - REGSET(reg, MEM_SMC, BSMC, OFF); - REGSET(reg, MEM_SMC, EW, OFF); - REGSET(reg, MEM_SMC, PB, 1); - REGSET(reg, MEM_SMC, PC, AL); - REGSET(reg, MEM_SMC, PM, DIS); - REGSET(reg, MEM_SMC, MW, 8); - __raw_writel(reg, MEM_SMC(0)); - - /* setup static CS0: timing */ - __raw_writel(0x2, MEM_SMWED(0)); - __raw_writel(0x2, MEM_SMOED(0)); - __raw_writel(0x6, MEM_SMRD(0)); - __raw_writel(0x6, MEM_SMWD(0)); -} diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.h b/arch/arm/mach-ns9xxx/board-a9m9750dev.h deleted file mode 100644 index edc75abbc5dd..000000000000 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-a9m9750dev.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/init.h> - -void __init board_a9m9750dev_map_io(void); -void __init board_a9m9750dev_init_machine(void); -void __init board_a9m9750dev_init_irq(void); diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.c b/arch/arm/mach-ns9xxx/board-jscc9p9360.c deleted file mode 100644 index 4bd3eec04bfe..000000000000 --- a/arch/arm/mach-ns9xxx/board-jscc9p9360.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-jscc9p9360.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include "board-jscc9p9360.h" - -void __init board_jscc9p9360_init_machine(void) -{ - /* TODO: reserve GPIOs for push buttons, etc pp */ -} - diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.h b/arch/arm/mach-ns9xxx/board-jscc9p9360.h deleted file mode 100644 index 1a81a074df45..000000000000 --- a/arch/arm/mach-ns9xxx/board-jscc9p9360.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/board-jscc9p9360.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/init.h> - -void __init board_jscc9p9360_init_machine(void); diff --git a/arch/arm/mach-ns9xxx/clock.c b/arch/arm/mach-ns9xxx/clock.c deleted file mode 100644 index cf81cbc57544..000000000000 --- a/arch/arm/mach-ns9xxx/clock.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/clock.c - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/err.h> -#include <linux/module.h> -#include <linux/list.h> -#include <linux/clk.h> -#include <linux/string.h> -#include <linux/platform_device.h> -#include <linux/semaphore.h> - -#include "clock.h" - -static LIST_HEAD(clocks); -static DEFINE_SPINLOCK(clk_lock); - -struct clk *clk_get(struct device *dev, const char *id) -{ - struct clk *p, *ret = NULL, *retgen = NULL; - unsigned long flags; - int idno; - - if (dev == NULL || dev->bus != &platform_bus_type) - idno = -1; - else - idno = to_platform_device(dev)->id; - - spin_lock_irqsave(&clk_lock, flags); - list_for_each_entry(p, &clocks, node) { - if (strcmp(id, p->name) == 0) { - if (p->id == idno) { - if (!try_module_get(p->owner)) - continue; - ret = p; - break; - } else if (p->id == -1) - /* remember match with id == -1 in case there is - * no clock for idno */ - retgen = p; - } - } - - if (!ret && retgen && try_module_get(retgen->owner)) - ret = retgen; - - if (ret) - ++ret->refcount; - - spin_unlock_irqrestore(&clk_lock, flags); - - return ret ? ret : ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ - module_put(clk->owner); - --clk->refcount; -} -EXPORT_SYMBOL(clk_put); - -static int clk_enable_unlocked(struct clk *clk) -{ - int ret = 0; - if (clk->parent) { - ret = clk_enable_unlocked(clk->parent); - if (ret) - return ret; - } - - if (clk->usage++ == 0 && clk->endisable) - ret = clk->endisable(clk, 1); - - return ret; -} - -int clk_enable(struct clk *clk) -{ - int ret; - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - ret = clk_enable_unlocked(clk); - - spin_unlock_irqrestore(&clk_lock, flags); - - return ret; -} -EXPORT_SYMBOL(clk_enable); - -static void clk_disable_unlocked(struct clk *clk) -{ - if (--clk->usage == 0 && clk->endisable) - clk->endisable(clk, 0); - - if (clk->parent) - clk_disable_unlocked(clk->parent); -} - -void clk_disable(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - clk_disable_unlocked(clk); - - spin_unlock_irqrestore(&clk_lock, flags); -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - if (clk->get_rate) - return clk->get_rate(clk); - - if (clk->rate) - return clk->rate; - - if (clk->parent) - return clk_get_rate(clk->parent); - - return 0; -} -EXPORT_SYMBOL(clk_get_rate); - -int clk_register(struct clk *clk) -{ - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - list_add(&clk->node, &clocks); - - if (clk->parent) - ++clk->parent->refcount; - - spin_unlock_irqrestore(&clk_lock, flags); - - return 0; -} - -int clk_unregister(struct clk *clk) -{ - int ret = 0; - unsigned long flags; - - spin_lock_irqsave(&clk_lock, flags); - - if (clk->usage || clk->refcount) - ret = -EBUSY; - else - list_del(&clk->node); - - if (clk->parent) - --clk->parent->refcount; - - spin_unlock_irqrestore(&clk_lock, flags); - - return ret; -} - -#if defined CONFIG_DEBUG_FS - -#include <linux/debugfs.h> -#include <linux/seq_file.h> - -static int clk_debugfs_show(struct seq_file *s, void *null) -{ - unsigned long flags; - struct clk *p; - - spin_lock_irqsave(&clk_lock, flags); - - list_for_each_entry(p, &clocks, node) - seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n", - p->name, p->id, p->usage, p->refcount, - p->usage ? clk_get_rate(p) : 0); - - spin_unlock_irqrestore(&clk_lock, flags); - - return 0; -} - -static int clk_debugfs_open(struct inode *inode, struct file *file) -{ - return single_open(file, clk_debugfs_show, NULL); -} - -static const struct file_operations clk_debugfs_operations = { - .open = clk_debugfs_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init clk_debugfs_init(void) -{ - struct dentry *dentry; - - dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL, - &clk_debugfs_operations); - return IS_ERR(dentry) ? PTR_ERR(dentry) : 0; -} -subsys_initcall(clk_debugfs_init); - -#endif /* if defined CONFIG_DEBUG_FS */ diff --git a/arch/arm/mach-ns9xxx/clock.h b/arch/arm/mach-ns9xxx/clock.h deleted file mode 100644 index b86c30dd79eb..000000000000 --- a/arch/arm/mach-ns9xxx/clock.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/clock.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __NS9XXX_CLOCK_H -#define __NS9XXX_CLOCK_H - -#include <linux/list.h> - -struct clk { - struct module *owner; - const char *name; - int id; - - struct clk *parent; - - unsigned long rate; - int (*endisable)(struct clk *, int enable); - unsigned long (*get_rate)(struct clk *); - - struct list_head node; - unsigned long refcount; - unsigned long usage; -}; - -int clk_register(struct clk *clk); -int clk_unregister(struct clk *clk); - -#endif /* ifndef __NS9XXX_CLOCK_H */ diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c deleted file mode 100644 index 1e0f467879cc..000000000000 --- a/arch/arm/mach-ns9xxx/generic.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/generic.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <asm/memory.h> - -#include "generic.h" - -void __init ns9xxx_init_machine(void) -{ -} diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h deleted file mode 100644 index 82493191aad6..000000000000 --- a/arch/arm/mach-ns9xxx/generic.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/generic.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/time.h> -#include <asm/mach/time.h> -#include <linux/init.h> - -void __init ns9xxx_init_irq(void); -void __init ns9xxx_init_machine(void); diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c deleted file mode 100644 index 377330c1b250..000000000000 --- a/arch/arm/mach-ns9xxx/gpio-ns9360.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/gpio-ns9360.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/bug.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/kernel.h> -#include <linux/module.h> - -#include <mach/regs-bbu.h> -#include <mach/processor-ns9360.h> - -#include "gpio-ns9360.h" - -static inline int ns9360_valid_gpio(unsigned gpio) -{ - return gpio <= 72; -} - -static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio) -{ - if (gpio < 56) - return BBU_GCONFb1(gpio / 8); - else - /* - * this could be optimised away on - * ns9750 only builds, but it isn't ... - */ - return BBU_GCONFb2((gpio - 56) / 8); -} - -static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio) -{ - if (gpio < 32) - return BBU_GCTRL1; - else if (gpio < 64) - return BBU_GCTRL2; - else - /* this could be optimised away on ns9750 only builds */ - return BBU_GCTRL3; -} - -static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio) -{ - if (gpio < 32) - return BBU_GSTAT1; - else if (gpio < 64) - return BBU_GSTAT2; - else - /* this could be optimised away on ns9750 only builds */ - return BBU_GSTAT3; -} - -/* - * each gpio can serve for 4 different purposes [0..3]. These are called - * "functions" and passed in the parameter func. Functions 0-2 are always some - * special things, function 3 is GPIO. If func == 3 dir specifies input or - * output, and with inv you can enable an inverter (independent of func). - */ -int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func) -{ - void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio); - u32 confval; - - confval = __raw_readl(conf); - REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir); - REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv); - REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func); - __raw_writel(confval, conf); - - return 0; -} - -int ns9360_gpio_configure(unsigned gpio, int inv, int func) -{ - if (likely(ns9360_valid_gpio(gpio))) { - if (func == 3) { - printk(KERN_WARNING "use gpio_direction_input " - "or gpio_direction_output\n"); - return -EINVAL; - } else - return __ns9360_gpio_configure(gpio, 0, inv, func); - } else - return -EINVAL; -} -EXPORT_SYMBOL(ns9360_gpio_configure); - -int ns9360_gpio_get_value(unsigned gpio) -{ - void __iomem *stat = ns9360_gpio_get_gstataddr(gpio); - int ret; - - ret = 1 & (__raw_readl(stat) >> (gpio & 31)); - - return ret; -} - -void ns9360_gpio_set_value(unsigned gpio, int value) -{ - void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio); - u32 ctrlval; - - ctrlval = __raw_readl(ctrl); - - if (value) - ctrlval |= 1 << (gpio & 31); - else - ctrlval &= ~(1 << (gpio & 31)); - - __raw_writel(ctrlval, ctrl); -} diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.h b/arch/arm/mach-ns9xxx/gpio-ns9360.h deleted file mode 100644 index 131cd1715caa..000000000000 --- a/arch/arm/mach-ns9xxx/gpio-ns9360.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/gpio-ns9360.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func); -int ns9360_gpio_get_value(unsigned gpio); -void ns9360_gpio_set_value(unsigned gpio, int value); diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c deleted file mode 100644 index 5503ca09c4ae..000000000000 --- a/arch/arm/mach-ns9xxx/gpio.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/gpio.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/compiler.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/module.h> -#include <linux/bitops.h> - -#include <mach/gpio.h> -#include <mach/processor.h> -#include <mach/processor-ns9360.h> -#include <asm/bug.h> -#include <asm/types.h> - -#include "gpio-ns9360.h" - -#if defined(CONFIG_PROCESSOR_NS9360) -#define GPIO_MAX 72 -#elif defined(CONFIG_PROCESSOR_NS9750) -#define GPIO_MAX 49 -#endif - -/* protects BBU_GCONFx and BBU_GCTRLx */ -static spinlock_t gpio_lock = __SPIN_LOCK_UNLOCKED(gpio_lock); - -/* only access gpiores with atomic ops */ -static DECLARE_BITMAP(gpiores, GPIO_MAX + 1); - -static inline int ns9xxx_valid_gpio(unsigned gpio) -{ -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - return gpio <= 72; - else -#endif -#if defined(CONFIG_PROCESSOR_NS9750) - if (processor_is_ns9750()) - return gpio <= 49; - else -#endif - { - BUG(); - return 0; - } -} - -int gpio_request(unsigned gpio, const char *label) -{ - if (likely(ns9xxx_valid_gpio(gpio))) - return test_and_set_bit(gpio, gpiores) ? -EBUSY : 0; - else - return -EINVAL; -} -EXPORT_SYMBOL(gpio_request); - -void gpio_free(unsigned gpio) -{ - might_sleep(); - clear_bit(gpio, gpiores); - return; -} -EXPORT_SYMBOL(gpio_free); - -int gpio_direction_input(unsigned gpio) -{ - if (likely(ns9xxx_valid_gpio(gpio))) { - int ret = -EINVAL; - unsigned long flags; - - spin_lock_irqsave(&gpio_lock, flags); -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - ret = __ns9360_gpio_configure(gpio, 0, 0, 3); - else -#endif - BUG(); - - spin_unlock_irqrestore(&gpio_lock, flags); - - return ret; - - } else - return -EINVAL; -} -EXPORT_SYMBOL(gpio_direction_input); - -int gpio_direction_output(unsigned gpio, int value) -{ - if (likely(ns9xxx_valid_gpio(gpio))) { - int ret = -EINVAL; - unsigned long flags; - - gpio_set_value(gpio, value); - - spin_lock_irqsave(&gpio_lock, flags); -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - ret = __ns9360_gpio_configure(gpio, 1, 0, 3); - else -#endif - BUG(); - - spin_unlock_irqrestore(&gpio_lock, flags); - - return ret; - } else - return -EINVAL; -} -EXPORT_SYMBOL(gpio_direction_output); - -int gpio_get_value(unsigned gpio) -{ -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - return ns9360_gpio_get_value(gpio); - else -#endif - { - BUG(); - return -EINVAL; - } -} -EXPORT_SYMBOL(gpio_get_value); - -void gpio_set_value(unsigned gpio, int value) -{ - unsigned long flags; - spin_lock_irqsave(&gpio_lock, flags); -#if defined(CONFIG_PROCESSOR_NS9360) - if (processor_is_ns9360()) - ns9360_gpio_set_value(gpio, value); - else -#endif - BUG(); - - spin_unlock_irqrestore(&gpio_lock, flags); -} -EXPORT_SYMBOL(gpio_set_value); diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h deleted file mode 100644 index 19ca6de46a45..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/board.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/board.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_BOARD_H -#define __ASM_ARCH_BOARD_H - -#include <asm/mach-types.h> - -#define board_is_a9m9750dev() (0 \ - || machine_is_cc9p9750dev() \ - ) - -#define board_is_a9mvali() (0 \ - || machine_is_cc9p9750val() \ - ) - -#define board_is_jscc9p9210() (0 \ - || machine_is_cc9p9210js() \ - ) - -#define board_is_jscc9p9215() (0 \ - || machine_is_cc9p9215js() \ - ) - -#define board_is_jscc9p9360() (0 \ - || machine_is_cc9p9360js() \ - ) - -#define board_is_uncbas() (0 \ - || machine_is_cc7ucamry() \ - ) - -#endif /* ifndef __ASM_ARCH_BOARD_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S deleted file mode 100644 index 5a2acbdc3d67..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/debug-macro.S - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <mach/hardware.h> -#include <asm/memory.h> - -#include <mach/regs-board-a9m9750dev.h> - - .macro addruart, rp, rv - ldr \rp, =NS9XXX_CSxSTAT_PHYS(0) - ldr \rv, =io_p2v(NS9XXX_CSxSTAT_PHYS(0)) - .endm - -#define UART_SHIFT 2 -#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S b/arch/arm/mach-ns9xxx/include/mach/entry-macro.S deleted file mode 100644 index 71ca0319b547..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S +++ /dev/null @@ -1,28 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/entry-macro.S - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <mach/hardware.h> -#include <mach/regs-sys-common.h> - - .macro get_irqnr_preamble, base, tmp - ldr \base, =SYS_ISRADDR - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)] - cmp \irqstat, #0 - ldrne \irqnr, [\base] - .endm - - .macro disable_fiq - .endm diff --git a/arch/arm/mach-ns9xxx/include/mach/gpio.h b/arch/arm/mach-ns9xxx/include/mach/gpio.h deleted file mode 100644 index 5eb349032579..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/gpio.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/gpio.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. -*/ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#include <asm/errno.h> - -int gpio_request(unsigned gpio, const char *label); - -void gpio_free(unsigned gpio); - -int ns9xxx_gpio_configure(unsigned gpio, int inv, int func); - -int gpio_direction_input(unsigned gpio); - -int gpio_direction_output(unsigned gpio, int value); - -int gpio_get_value(unsigned gpio); - -void gpio_set_value(unsigned gpio, int value); - -/* - * ns9xxx can use gpio pins to trigger an irq, but it's not generic - * enough to be supported by the gpio_to_irq/irq_to_gpio interface - */ -static inline int gpio_to_irq(unsigned gpio) -{ - return -EINVAL; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return -EINVAL; -} - -/* get the cansleep() stubs */ -#include <asm-generic/gpio.h> - -#endif /* ifndef __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h deleted file mode 100644 index 76631128e11c..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/hardware.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/hardware.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * NetSilicon NS9xxx internal mapping: - * - * physical <--> virtual - * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff - * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff - */ -#define io_p2v(x) (0xf0000000 \ - + (((x) & 0xf0000000) >> 4) \ - + ((x) & 0x00ffffff)) - -#define io_v2p(x) ((((x) & 0x0f000000) << 4) \ - + ((x) & 0x00ffffff)) - -#define __REGSHIFT(mask) ((mask) & (-(mask))) - -#define __REGBIT(bit) ((u32)1 << (bit)) -#define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit)) -#define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask)) - -#ifndef __ASSEMBLY__ - -# define __REG(x) ((void __iomem __force *)io_p2v((x))) -# define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y))) - -# define __REGSET(var, field, value) \ - ((var) = (((var) & ~((field) & ~(value))) | (value))) - -# define REGSET(var, reg, field, value) \ - __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value) - -# define REGSET_IDX(var, reg, field, idx, value) \ - __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx))) - -# define REGSETIM(var, reg, field, value) \ - __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value))) - -# define REGSETIM_IDX(var, reg, field, idx, value) \ - __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value))) - -# define __REGGET(var, field) \ - (((var) & (field))) - -# define REGGET(var, reg, field) \ - __REGGET(var, reg ## _ ## field) - -# define REGGET_IDX(var, reg, field, idx) \ - __REGGET(var, reg ## _ ## field((idx))) - -# define REGGETIM(var, reg, field) \ - __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) - -# define REGGETIM_IDX(var, reg, field, idx) \ - __REGGET(var, reg ## _ ## field((idx))) / \ - __REGSHIFT(reg ## _ ## field((idx))) - -#else - -# define __REG(x) io_p2v(x) -# define __REG2(x, y) io_p2v((x) + 4 * (y)) - -#endif - -#endif /* ifndef __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h deleted file mode 100644 index f08451d2e1bc..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/io.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/io.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff /* XXX */ - -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) -#define __mem_isa(a) (IO_BASE + (a)) - -#endif /* ifndef __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/irqs.h b/arch/arm/mach-ns9xxx/include/mach/irqs.h deleted file mode 100644 index 13483949e210..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/irqs.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/irqs.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* NetSilicon 9360 */ -#define IRQ_NS9XXX_WATCHDOG 0 -#define IRQ_NS9XXX_AHBBUSERR 1 -#define IRQ_NS9360_BBUSAGG 2 -/* irq 3 is reserved for NS9360 */ -#define IRQ_NS9XXX_ETHRX 4 -#define IRQ_NS9XXX_ETHTX 5 -#define IRQ_NS9XXX_ETHPHY 6 -#define IRQ_NS9360_LCD 7 -#define IRQ_NS9360_SERBRX 8 -#define IRQ_NS9360_SERBTX 9 -#define IRQ_NS9360_SERARX 10 -#define IRQ_NS9360_SERATX 11 -#define IRQ_NS9360_SERCRX 12 -#define IRQ_NS9360_SERCTX 13 -#define IRQ_NS9360_I2C 14 -#define IRQ_NS9360_BBUSDMA 15 -#define IRQ_NS9360_TIMER0 16 -#define IRQ_NS9360_TIMER1 17 -#define IRQ_NS9360_TIMER2 18 -#define IRQ_NS9360_TIMER3 19 -#define IRQ_NS9360_TIMER4 20 -#define IRQ_NS9360_TIMER5 21 -#define IRQ_NS9360_TIMER6 22 -#define IRQ_NS9360_TIMER7 23 -#define IRQ_NS9360_RTC 24 -#define IRQ_NS9360_USBHOST 25 -#define IRQ_NS9360_USBDEVICE 26 -#define IRQ_NS9360_IEEE1284 27 -#define IRQ_NS9XXX_EXT0 28 -#define IRQ_NS9XXX_EXT1 29 -#define IRQ_NS9XXX_EXT2 30 -#define IRQ_NS9XXX_EXT3 31 - -#define BBUS_IRQ(irq) (32 + irq) - -#define IRQ_BBUS_DMA BBUS_IRQ(0) -#define IRQ_BBUS_SERBRX BBUS_IRQ(2) -#define IRQ_BBUS_SERBTX BBUS_IRQ(3) -#define IRQ_BBUS_SERARX BBUS_IRQ(4) -#define IRQ_BBUS_SERATX BBUS_IRQ(5) -#define IRQ_BBUS_SERCRX BBUS_IRQ(6) -#define IRQ_BBUS_SERCTX BBUS_IRQ(7) -#define IRQ_BBUS_SERDRX BBUS_IRQ(8) -#define IRQ_BBUS_SERDTX BBUS_IRQ(9) -#define IRQ_BBUS_I2C BBUS_IRQ(10) -#define IRQ_BBUS_1284 BBUS_IRQ(11) -#define IRQ_BBUS_UTIL BBUS_IRQ(12) -#define IRQ_BBUS_RTC BBUS_IRQ(13) -#define IRQ_BBUS_USBHST BBUS_IRQ(14) -#define IRQ_BBUS_USBDEV BBUS_IRQ(15) -#define IRQ_BBUS_AHBDMA1 BBUS_IRQ(24) -#define IRQ_BBUS_AHBDMA2 BBUS_IRQ(25) - -/* - * these Interrupts are specific for the a9m9750dev board. - * They are generated by an FPGA that interrupts the CPU on - * IRQ_NS9360_EXT2 - */ -#define FPGA_IRQ(irq) (64 + irq) - -#define IRQ_FPGA_UARTA FPGA_IRQ(0) -#define IRQ_FPGA_UARTB FPGA_IRQ(1) -#define IRQ_FPGA_UARTC FPGA_IRQ(2) -#define IRQ_FPGA_UARTD FPGA_IRQ(3) -#define IRQ_FPGA_TOUCH FPGA_IRQ(4) -#define IRQ_FPGA_CF FPGA_IRQ(5) -#define IRQ_FPGA_CAN0 FPGA_IRQ(6) -#define IRQ_FPGA_CAN1 FPGA_IRQ(7) - -#define NR_IRQS 72 - -#endif /* __ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h deleted file mode 100644 index 5c65aee6e7a9..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/memory.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/memory.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. -*/ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* x in [0..3] */ -#define NS9XXX_CSxSTAT_PHYS(x) UL(((x) + 4) << 28) - -#define NS9XXX_CS0STAT_LENGTH UL(0x1000) -#define NS9XXX_CS1STAT_LENGTH UL(0x1000) -#define NS9XXX_CS2STAT_LENGTH UL(0x1000) -#define NS9XXX_CS3STAT_LENGTH UL(0x1000) - -#define PLAT_PHYS_OFFSET UL(0x00000000) - -#endif diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h deleted file mode 100644 index 628e9752589b..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/module.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/module.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_MODULE_H -#define __ASM_ARCH_MODULE_H - -#include <asm/mach-types.h> - -#define module_is_cc7ucamry() (0 \ - || machine_is_cc7ucamry() \ - ) - -#define module_is_cc9c() (0 \ - ) - -#define module_is_cc9p9210() (0 \ - || machine_is_cc9p9210() \ - || machine_is_cc9p9210js() \ - ) - -#define module_is_cc9p9215() (0 \ - || machine_is_cc9p9215() \ - || machine_is_cc9p9215js() \ - ) - -#define module_is_cc9p9360() (0 \ - || machine_is_cc9p9360dev() \ - || machine_is_cc9p9360js() \ - ) - -#define module_is_cc9p9750() (0 \ - || machine_is_a9m9750() \ - || machine_is_cc9p9750js() \ - || machine_is_cc9p9750val() \ - ) - -#define module_is_ccw9c() (0 \ - ) - -#define module_is_inc20otter() (0 \ - || machine_is_inc20otter() \ - ) - -#define module_is_otter() (0 \ - || machine_is_otter() \ - ) - -#endif /* ifndef __ASM_ARCH_MODULE_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h deleted file mode 100644 index f41deda5129e..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_PROCESSORNS9360_H -#define __ASM_ARCH_PROCESSORNS9360_H - -#include <linux/init.h> - -void ns9360_reset(char mode); - -unsigned long ns9360_systemclock(void) __attribute__((const)); - -static inline unsigned long ns9360_cpuclock(void) __attribute__((const)); -static inline unsigned long ns9360_cpuclock(void) -{ - return ns9360_systemclock() / 2; -} - -void __init ns9360_map_io(void); - -extern struct sys_timer ns9360_timer; - -int ns9360_gpio_configure(unsigned gpio, int inv, int func); - -#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/processor.h b/arch/arm/mach-ns9xxx/include/mach/processor.h deleted file mode 100644 index 9f77f746a386..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/processor.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/processor.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_PROCESSOR_H -#define __ASM_ARCH_PROCESSOR_H - -#include <mach/module.h> - -#define processor_is_ns9210() (0 \ - || module_is_cc7ucamry() \ - || module_is_cc9p9210() \ - || module_is_inc20otter() \ - || module_is_otter() \ - ) - -#define processor_is_ns9215() (0 \ - || module_is_cc9p9215() \ - ) - -#define processor_is_ns9360() (0 \ - || module_is_cc9p9360() \ - || module_is_cc9c() \ - || module_is_ccw9c() \ - ) - -#define processor_is_ns9750() (0 \ - || module_is_cc9p9750() \ - ) - -#define processor_is_ns921x() (0 \ - || processor_is_ns9210() \ - || processor_is_ns9215() \ - ) - -#endif /* ifndef __ASM_ARCH_PROCESSOR_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h deleted file mode 100644 index af227c058fb9..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-bbu.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSBBU_H -#define __ASM_ARCH_REGSBBU_H - -#include <mach/hardware.h> - -/* BBus Utility */ - -/* GPIO Configuration Registers block 1 */ -/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is - * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register - * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */ -#define BBU_GCONFb1(x) __REG2(0x90600010, (x)) -#define BBU_GCONFb2(x) __REG2(0x90600100, (x)) - -#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2)) -#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0) -#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1) -#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2)) -#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0) -#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1) -#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2) -#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0) -#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1) -#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2) -#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3) - -#define BBU_GCTRL1 __REG(0x90600030) -#define BBU_GCTRL2 __REG(0x90600034) -#define BBU_GCTRL3 __REG(0x90600120) - -#define BBU_GSTAT1 __REG(0x90600040) -#define BBU_GSTAT2 __REG(0x90600044) -#define BBU_GSTAT3 __REG(0x90600130) - -#endif /* ifndef __ASM_ARCH_REGSBBU_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h b/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h deleted file mode 100644 index cd1593693f56..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSBOARDA9M9750_H -#define __ASM_ARCH_REGSBOARDA9M9750_H - -#include <mach/hardware.h> - -#define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0)) -#define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08) -#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10) -#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18) - -#define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50) -#define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60) - -#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h b/arch/arm/mach-ns9xxx/include/mach/regs-mem.h deleted file mode 100644 index f1625bf8cdce..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-mem.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSMEM_H -#define __ASM_ARCH_REGSMEM_H - -#include <mach/hardware.h> - -/* Memory Module */ - -/* Control register */ -#define MEM_CTRL __REG(0xa0700000) - -/* Status register */ -#define MEM_STAT __REG(0xa0700004) - -/* Configuration register */ -#define MEM_CONF __REG(0xa0700008) - -/* Dynamic Memory Control register */ -#define MEM_DMCTRL __REG(0xa0700020) - -/* Dynamic Memory Refresh Timer */ -#define MEM_DMRT __REG(0xa0700024) - -/* Dynamic Memory Read Configuration register */ -#define MEM_DMRC __REG(0xa0700028) - -/* Dynamic Memory Precharge Command Period (tRP) */ -#define MEM_DMPCP __REG(0xa0700030) - -/* Dynamic Memory Active to Precharge Command Period (tRAS) */ -#define MEM_DMAPCP __REG(0xa0700034) - -/* Dynamic Memory Self-Refresh Exit Time (tSREX) */ -#define MEM_DMSRET __REG(0xa0700038) - -/* Dynamic Memory Last Data Out to Active Time (tAPR) */ -#define MEM_DMLDOAT __REG(0xa070003c) - -/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */ -#define MEM_DMDIACT __REG(0xa0700040) - -/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */ -#define MEM_DMWRT __REG(0xa0700044) - -/* Dynamic Memory Active to Active Command Period (tRC) */ -#define MEM_DMAACP __REG(0xa0700048) - -/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */ -#define MEM_DMARP __REG(0xa070004c) - -/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */ -#define MEM_DMESRAC __REG(0xa0700050) - -/* Dynamic Memory Active Bank A to Active B Time (tRRD) */ -#define MEM_DMABAABT __REG(0xa0700054) - -/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */ -#define MEM_DMLMACT __REG(0xa0700058) - -/* Static Memory Extended Wait */ -#define MEM_SMEW __REG(0xa0700080) - -/* Dynamic Memory Configuration Register x */ -#define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3) - -/* Dynamic Memory RAS and CAS Delay x */ -#define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3) - -/* Static Memory Configuration Register x */ -#define MEM_SMC(x) __REG2(0xa0700200, (x) << 3) - -/* Static Memory Configuration Register x: Write protect */ -#define MEM_SMC_PSMC __REGBIT(20) -#define MEM_SMC_PSMC_OFF __REGVAL(MEM_SMC_PSMC, 0) -#define MEM_SMC_PSMC_ON __REGVAL(MEM_SMC_PSMC, 1) - -/* Static Memory Configuration Register x: Buffer enable */ -#define MEM_SMC_BSMC __REGBIT(19) -#define MEM_SMC_BSMC_OFF __REGVAL(MEM_SMC_BSMC, 0) -#define MEM_SMC_BSMC_ON __REGVAL(MEM_SMC_BSMC, 1) - -/* Static Memory Configuration Register x: Extended Wait */ -#define MEM_SMC_EW __REGBIT(8) -#define MEM_SMC_EW_OFF __REGVAL(MEM_SMC_EW, 0) -#define MEM_SMC_EW_ON __REGVAL(MEM_SMC_EW, 1) - -/* Static Memory Configuration Register x: Byte lane state */ -#define MEM_SMC_PB __REGBIT(7) -#define MEM_SMC_PB_0 __REGVAL(MEM_SMC_PB, 0) -#define MEM_SMC_PB_1 __REGVAL(MEM_SMC_PB, 1) - -/* Static Memory Configuration Register x: Chip select polarity */ -#define MEM_SMC_PC __REGBIT(6) -#define MEM_SMC_PC_AL __REGVAL(MEM_SMC_PC, 0) -#define MEM_SMC_PC_AH __REGVAL(MEM_SMC_PC, 1) - -/* static memory configuration register x: page mode*/ -#define MEM_SMC_PM __REGBIT(3) -#define MEM_SMC_PM_DIS __REGVAL(MEM_SMC_PM, 0) -#define MEM_SMC_PM_ASYNC __REGVAL(MEM_SMC_PM, 1) - -/* static memory configuration register x: Memory width */ -#define MEM_SMC_MW __REGBITS(1, 0) -#define MEM_SMC_MW_8 __REGVAL(MEM_SMC_MW, 0) -#define MEM_SMC_MW_16 __REGVAL(MEM_SMC_MW, 1) -#define MEM_SMC_MW_32 __REGVAL(MEM_SMC_MW, 2) - -/* Static Memory Write Enable Delay x */ -#define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3) - -/* Static Memory Output Enable Delay x */ -#define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3) - -/* Static Memory Read Delay x */ -#define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3) - -/* Static Memory Page Mode Read Delay 0 */ -#define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3) - -/* Static Memory Write Delay */ -#define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3) - -/* Static Memory Turn Round Delay x */ -#define MEM_SWT(x) __REG2(0xa0700218, (x) << 3) - -#endif /* ifndef __ASM_ARCH_REGSMEM_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h deleted file mode 100644 index 14f91dfd5736..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_REGSSYSCOMMON_H -#define __ASM_ARCH_REGSSYSCOMMON_H -#include <mach/hardware.h> - -/* Interrupt Vector Address Register Level x */ -#define SYS_IVA(x) __REG2(0xa09000c4, (x)) - -/* Interrupt Configuration registers */ -#define SYS_IC(x) __REG2(0xa0900144, (x)) - -/* ISRADDR */ -#define SYS_ISRADDR __REG(0xa0900164) - -/* Interrupt Status Active */ -#define SYS_ISA __REG(0xa0900168) - -/* Interrupt Status Raw */ -#define SYS_ISR __REG(0xa090016c) - -#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h deleted file mode 100644 index 8ff254d9901c..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_REGSSYSNS9360_H -#define __ASM_ARCH_REGSSYSNS9360_H - -#include <mach/hardware.h> - -/* System Control Module */ - -/* AHB Arbiter Gen Configuration */ -#define SYS_AHBAGENCONF __REG(0xa0900000) - -/* BRC */ -#define SYS_BRC(x) __REG2(0xa0900004, (x)) - -/* Timer x Reload Count register */ -#define SYS_TRC(x) __REG2(0xa0900044, (x)) - -/* Timer x Read register */ -#define SYS_TR(x) __REG2(0xa0900084, (x)) - -/* Timer Interrupt Status register */ -#define SYS_TIS __REG(0xa0900170) - -/* PLL Configuration register */ -#define SYS_PLL __REG(0xa0900188) - -/* PLL FS status */ -#define SYS_PLL_FS __REGBITS(24, 23) - -/* PLL ND status */ -#define SYS_PLL_ND __REGBITS(20, 16) - -/* PLL Configuration register: PLL SW change */ -#define SYS_PLL_SWC __REGBIT(15) -#define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0) -#define SYS_PLL_SWC_YES __REGVAL(SYS_PLL_SWC, 1) - -/* Timer x Control register */ -#define SYS_TC(x) __REG2(0xa0900190, (x)) - -/* Timer x Control register: Timer enable */ -#define SYS_TCx_TEN __REGBIT(15) -#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0) -#define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1) - -/* Timer x Control register: CPU debug mode */ -#define SYS_TCx_TDBG __REGBIT(10) -#define SYS_TCx_TDBG_CONT __REGVAL(SYS_TCx_TDBG, 0) -#define SYS_TCx_TDBG_STOP __REGVAL(SYS_TCx_TDBG, 1) - -/* Timer x Control register: Interrupt clear */ -#define SYS_TCx_INTC __REGBIT(9) -#define SYS_TCx_INTC_UNSET __REGVAL(SYS_TCx_INTC, 0) -#define SYS_TCx_INTC_SET __REGVAL(SYS_TCx_INTC, 1) - -/* Timer x Control register: Timer clock select */ -#define SYS_TCx_TLCS __REGBITS(8, 6) -#define SYS_TCx_TLCS_CPU __REGVAL(SYS_TCx_TLCS, 0) /* CPU clock */ -#define SYS_TCx_TLCS_DIV2 __REGVAL(SYS_TCx_TLCS, 1) /* CPU clock / 2 */ -#define SYS_TCx_TLCS_DIV4 __REGVAL(SYS_TCx_TLCS, 2) /* CPU clock / 4 */ -#define SYS_TCx_TLCS_DIV8 __REGVAL(SYS_TCx_TLCS, 3) /* CPU clock / 8 */ -#define SYS_TCx_TLCS_DIV16 __REGVAL(SYS_TCx_TLCS, 4) /* CPU clock / 16 */ -#define SYS_TCx_TLCS_DIV32 __REGVAL(SYS_TCx_TLCS, 5) /* CPU clock / 32 */ -#define SYS_TCx_TLCS_DIV64 __REGVAL(SYS_TCx_TLCS, 6) /* CPU clock / 64 */ -#define SYS_TCx_TLCS_EXT __REGVAL(SYS_TCx_TLCS, 7) - -/* Timer x Control register: Timer mode */ -#define SYS_TCx_TM __REGBITS(5, 4) -#define SYS_TCx_TM_IEE __REGVAL(SYS_TCx_TM, 0) /* Internal timer or external event */ -#define SYS_TCx_TM_ELL __REGVAL(SYS_TCx_TM, 1) /* External low-level, gated timer */ -#define SYS_TCx_TM_EHL __REGVAL(SYS_TCx_TM, 2) /* External high-level, gated timer */ -#define SYS_TCx_TM_CONCAT __REGVAL(SYS_TCx_TM, 3) /* Concatenate the lower timer. */ - -/* Timer x Control register: Interrupt select */ -#define SYS_TCx_INTS __REGBIT(3) -#define SYS_TCx_INTS_DIS __REGVAL(SYS_TCx_INTS, 0) -#define SYS_TCx_INTS_EN __REGVAL(SYS_TCx_INTS, 1) - -/* Timer x Control register: Up/down select */ -#define SYS_TCx_UDS __REGBIT(2) -#define SYS_TCx_UDS_UP __REGVAL(SYS_TCx_UDS, 0) -#define SYS_TCx_UDS_DOWN __REGVAL(SYS_TCx_UDS, 1) - -/* Timer x Control register: 32- or 16-bit timer */ -#define SYS_TCx_TSZ __REGBIT(1) -#define SYS_TCx_TSZ_16 __REGVAL(SYS_TCx_TSZ, 0) -#define SYS_TCx_TSZ_32 __REGVAL(SYS_TCx_TSZ, 1) - -/* Timer x Control register: Reload enable */ -#define SYS_TCx_REN __REGBIT(0) -#define SYS_TCx_REN_DIS __REGVAL(SYS_TCx_REN, 0) -#define SYS_TCx_REN_EN __REGVAL(SYS_TCx_REN, 1) - -/* System Memory Chip Select x Dynamic Memory Base */ -#define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1) - -/* System Memory Chip Select x Dynamic Memory Mask */ -#define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1) - -/* System Memory Chip Select x Static Memory Base */ -#define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1) - -/* System Memory Chip Select x Static Memory Base: Chip select x base */ -#define SYS_SMCSSMB_CSxB __REGBITS(31, 12) - -/* System Memory Chip Select x Static Memory Mask */ -#define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1) - -/* System Memory Chip Select x Static Memory Mask: Chip select x mask */ -#define SYS_SMCSSMM_CSxM __REGBITS(31, 12) - -/* System Memory Chip Select x Static Memory Mask: Chip select x enable */ -#define SYS_SMCSSMM_CSEx __REGBIT(0) -#define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0) -#define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1) - -/* General purpose, user-defined ID register */ -#define SYS_GENID __REG(0xa0900210) - -/* External Interrupt x Control register */ -#define SYS_EIC(x) __REG2(0xa0900214, (x)) - -/* External Interrupt x Control register: Status */ -#define SYS_EIC_STS __REGBIT(3) - -/* External Interrupt x Control register: Clear */ -#define SYS_EIC_CLR __REGBIT(2) - -/* External Interrupt x Control register: Polarity */ -#define SYS_EIC_PLTY __REGBIT(1) -#define SYS_EIC_PLTY_AH __REGVAL(SYS_EIC_PLTY, 0) -#define SYS_EIC_PLTY_AL __REGVAL(SYS_EIC_PLTY, 1) - -/* External Interrupt x Control register: Level edge */ -#define SYS_EIC_LVEDG __REGBIT(0) -#define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0) -#define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1) - -#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h deleted file mode 100644 index 1561588ca364..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/system.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/system.h - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <asm/proc-fns.h> -#include <mach/processor.h> -#include <mach/processor-ns9360.h> - -static inline void arch_idle(void) -{ - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ -#ifdef CONFIG_PROCESSOR_NS9360 - if (processor_is_ns9360()) - ns9360_reset(mode); - else -#endif - BUG(); - - BUG(); -} - -#endif /* ifndef __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/timex.h b/arch/arm/mach-ns9xxx/include/mach/timex.h deleted file mode 100644 index 734a8d8bd578..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/timex.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/timex.h - * - * Copyright (C) 2005-2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -/* - * value for CLOCK_TICK_RATE stolen from arch/arm/mach-s3c2410/include/mach/timex.h. - * See there for an explanation. - */ -#define CLOCK_TICK_RATE 12000000 - -#endif /* ifndef __ASM_ARCH_TIMEX_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h deleted file mode 100644 index 770a68c46e81..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/uncompress.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <linux/io.h> - -#define __REG(x) ((void __iomem __force *)(x)) - -static void putc_dummy(char c, void __iomem *base) -{ - /* nothing */ -} - -static int timeout; - -static void putc_ns9360(char c, void __iomem *base) -{ - do { - if (timeout) - --timeout; - - if (__raw_readl(base + 8) & (1 << 3)) { - __raw_writeb(c, base + 16); - timeout = 0x10000; - break; - } - } while (timeout); -} - -static void putc_a9m9750dev(char c, void __iomem *base) -{ - do { - if (timeout) - --timeout; - - if (__raw_readb(base + 5) & (1 << 5)) { - __raw_writeb(c, base); - timeout = 0x10000; - break; - } - } while (timeout); - -} - -static void putc_ns921x(char c, void __iomem *base) -{ - do { - if (timeout) - --timeout; - - if (!(__raw_readl(base) & (1 << 11))) { - __raw_writeb(c, base + 0x0028); - timeout = 0x10000; - break; - } - } while (timeout); -} - -#define MSCS __REG(0xA0900184) - -#define NS9360_UARTA __REG(0x90200040) -#define NS9360_UARTB __REG(0x90200000) -#define NS9360_UARTC __REG(0x90300000) -#define NS9360_UARTD __REG(0x90300040) - -#define NS9360_UART_ENABLED(base) \ - (__raw_readl(NS9360_UARTA) & (1 << 31)) - -#define A9M9750DEV_UARTA __REG(0x40000000) - -#define NS921XSYS_CLOCK __REG(0xa090017c) -#define NS921X_UARTA __REG(0x90010000) -#define NS921X_UARTB __REG(0x90018000) -#define NS921X_UARTC __REG(0x90020000) -#define NS921X_UARTD __REG(0x90028000) - -#define NS921X_UART_ENABLED(base) \ - (__raw_readl((base) + 0x1000) & (1 << 29)) - -static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base) -{ - timeout = 0x10000; - if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) { - /* ns9360 or ns9750 */ - if (NS9360_UART_ENABLED(NS9360_UARTA)) { - *putc = putc_ns9360; - *base = NS9360_UARTA; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTB)) { - *putc = putc_ns9360; - *base = NS9360_UARTB; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTC)) { - *putc = putc_ns9360; - *base = NS9360_UARTC; - return; - } else if (NS9360_UART_ENABLED(NS9360_UARTD)) { - *putc = putc_ns9360; - *base = NS9360_UARTD; - return; - } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) { - *putc = putc_a9m9750dev; - *base = A9M9750DEV_UARTA; - return; - } - } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) { - /* ns921x */ - u32 clock = __raw_readl(NS921XSYS_CLOCK); - - if ((clock & (1 << 1)) && - NS921X_UART_ENABLED(NS921X_UARTA)) { - *putc = putc_ns921x; - *base = NS921X_UARTA; - return; - } else if ((clock & (1 << 2)) && - NS921X_UART_ENABLED(NS921X_UARTB)) { - *putc = putc_ns921x; - *base = NS921X_UARTB; - return; - } else if ((clock & (1 << 3)) && - NS921X_UART_ENABLED(NS921X_UARTC)) { - *putc = putc_ns921x; - *base = NS921X_UARTC; - return; - } else if ((clock & (1 << 4)) && - NS921X_UART_ENABLED(NS921X_UARTD)) { - *putc = putc_ns921x; - *base = NS921X_UARTD; - return; - } - } - - *putc = putc_dummy; -} - -void (*myputc)(char, void __iomem *); -void __iomem *base; - -static void putc(char c) -{ - myputc(c, base); -} - -static void arch_decomp_setup(void) -{ - autodetect(&myputc, &base); -} -#define arch_decomp_wdog() - -static void flush(void) -{ - /* nothing */ -} - -#endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h deleted file mode 100644 index c8651974c4b0..000000000000 --- a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/include/mach/vmalloc.h - * - * Copyright (C) 2006 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#ifndef __ASM_ARCH_VMALLOC_H -#define __ASM_ARCH_VMALLOC_H - -#define VMALLOC_END (0xf0000000UL) - -#endif /* ifndef __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c deleted file mode 100644 index 37ab0a2b83ad..000000000000 --- a/arch/arm/mach-ns9xxx/irq.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/irq.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/interrupt.h> -#include <linux/kernel_stat.h> -#include <linux/io.h> -#include <asm/mach/irq.h> -#include <mach/regs-sys-common.h> -#include <mach/irqs.h> -#include <mach/board.h> - -#include "generic.h" - -/* simple interrupt prio table: prio(x) < prio(y) <=> x < y */ -#define irq2prio(i) (i) -#define prio2irq(p) (p) - -static void ns9xxx_mask_irq(struct irq_data *d) -{ - /* XXX: better use cpp symbols */ - int prio = irq2prio(d->irq); - u32 ic = __raw_readl(SYS_IC(prio / 4)); - ic &= ~(1 << (7 + 8 * (3 - (prio & 3)))); - __raw_writel(ic, SYS_IC(prio / 4)); -} - -static void ns9xxx_eoi_irq(struct irq_data *d) -{ - __raw_writel(0, SYS_ISRADDR); -} - -static void ns9xxx_unmask_irq(struct irq_data *d) -{ - /* XXX: better use cpp symbols */ - int prio = irq2prio(d->irq); - u32 ic = __raw_readl(SYS_IC(prio / 4)); - ic |= 1 << (7 + 8 * (3 - (prio & 3))); - __raw_writel(ic, SYS_IC(prio / 4)); -} - -static struct irq_chip ns9xxx_chip = { - .irq_eoi = ns9xxx_eoi_irq, - .irq_mask = ns9xxx_mask_irq, - .irq_unmask = ns9xxx_unmask_irq, -}; - -void __init ns9xxx_init_irq(void) -{ - int i; - - /* disable all IRQs */ - for (i = 0; i < 8; ++i) - __raw_writel(prio2irq(4 * i) << 24 | - prio2irq(4 * i + 1) << 16 | - prio2irq(4 * i + 2) << 8 | - prio2irq(4 * i + 3), - SYS_IC(i)); - - for (i = 0; i < 32; ++i) - __raw_writel(prio2irq(i), SYS_IVA(i)); - - for (i = 0; i <= 31; ++i) { - irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq); - set_irq_flags(i, IRQF_VALID); - irq_set_status_flags(i, IRQ_LEVEL); - } -} diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c deleted file mode 100644 index 2858417d8d8a..000000000000 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/processor-ns9360.h> - -#include "board-a9m9750dev.h" -#include "generic.h" - -static void __init mach_cc9p9360dev_map_io(void) -{ - ns9360_map_io(); - board_a9m9750dev_map_io(); -} - -static void __init mach_cc9p9360dev_init_irq(void) -{ - ns9xxx_init_irq(); - board_a9m9750dev_init_irq(); -} - -static void __init mach_cc9p9360dev_init_machine(void) -{ - ns9xxx_init_machine(); - board_a9m9750dev_init_machine(); -} - -MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard") - .map_io = mach_cc9p9360dev_map_io, - .init_irq = mach_cc9p9360dev_init_irq, - .init_machine = mach_cc9p9360dev_init_machine, - .timer = &ns9360_timer, - .boot_params = 0x100, -MACHINE_END diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c deleted file mode 100644 index 729f68da4293..000000000000 --- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/mach-cc9p9360js.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include <mach/processor-ns9360.h> - -#include "board-jscc9p9360.h" -#include "generic.h" - -static void __init mach_cc9p9360js_init_machine(void) -{ - ns9xxx_init_machine(); - board_jscc9p9360_init_machine(); -} - -MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard") - .map_io = ns9360_map_io, - .init_irq = ns9xxx_init_irq, - .init_machine = mach_cc9p9360js_init_machine, - .timer = &ns9360_timer, - .boot_params = 0x100, -MACHINE_END diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c deleted file mode 100644 index 463e92465fda..000000000000 --- a/arch/arm/mach-ns9xxx/plat-serial8250.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/plat-serial8250.c - * - * Copyright (C) 2008 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/slab.h> - -#include <mach/regs-board-a9m9750dev.h> -#include <mach/board.h> - -#define DRIVER_NAME "serial8250" - -static int __init ns9xxx_plat_serial8250_init(void) -{ - struct plat_serial8250_port *pdata; - struct platform_device *pdev; - int ret = -ENOMEM; - int i; - - if (!board_is_a9m9750dev()) - return -ENODEV; - - pdev = platform_device_alloc(DRIVER_NAME, 0); - if (!pdev) - goto err; - - pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL); - if (!pdata) - goto err; - - pdev->dev.platform_data = pdata; - - pdata[0].iobase = FPGA_UARTA_BASE; - pdata[1].iobase = FPGA_UARTB_BASE; - pdata[2].iobase = FPGA_UARTC_BASE; - pdata[3].iobase = FPGA_UARTD_BASE; - - for (i = 0; i < 4; ++i) { - pdata[i].membase = (void __iomem *)pdata[i].iobase; - pdata[i].mapbase = pdata[i].iobase; - pdata[i].iotype = UPIO_MEM; - pdata[i].uartclk = 18432000; - pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; - } - - pdata[0].irq = IRQ_FPGA_UARTA; - pdata[1].irq = IRQ_FPGA_UARTB; - pdata[2].irq = IRQ_FPGA_UARTC; - pdata[3].irq = IRQ_FPGA_UARTD; - - ret = platform_device_add(pdev); - if (ret) { -err: - platform_device_put(pdev); - - printk(KERN_WARNING "Could not add %s (errno=%d)\n", - DRIVER_NAME, ret); - } - - return 0; -} - -arch_initcall(ns9xxx_plat_serial8250_init); diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c deleted file mode 100644 index aed1999d24fc..000000000000 --- a/arch/arm/mach-ns9xxx/processor-ns9360.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/processor-ns9360.c - * - * Copyright (C) 2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/io.h> -#include <linux/kernel.h> - -#include <asm/page.h> -#include <asm/mach/map.h> -#include <mach/processor-ns9360.h> -#include <mach/regs-sys-ns9360.h> - -void ns9360_reset(char mode) -{ - u32 reg; - - reg = __raw_readl(SYS_PLL) >> 16; - REGSET(reg, SYS_PLL, SWC, YES); - __raw_writel(reg, SYS_PLL); -} - -#define CRYSTAL 29491200 /* Hz */ -unsigned long ns9360_systemclock(void) -{ - u32 pll = __raw_readl(SYS_PLL); - return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1) - >> REGGETIM(pll, SYS_PLL, FS); -} - -static struct map_desc ns9360_io_desc[] __initdata = { - { /* BBus */ - .virtual = io_p2v(0x90000000), - .pfn = __phys_to_pfn(0x90000000), - .length = 0x00700000, - .type = MT_DEVICE, - }, { /* AHB */ - .virtual = io_p2v(0xa0100000), - .pfn = __phys_to_pfn(0xa0100000), - .length = 0x00900000, - .type = MT_DEVICE, - }, -}; - -void __init ns9360_map_io(void) -{ - iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc)); -} diff --git a/arch/arm/mach-ns9xxx/time-ns9360.c b/arch/arm/mach-ns9xxx/time-ns9360.c deleted file mode 100644 index 9ca32f55728b..000000000000 --- a/arch/arm/mach-ns9xxx/time-ns9360.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * arch/arm/mach-ns9xxx/time-ns9360.c - * - * Copyright (C) 2006,2007 by Digi International Inc. - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - */ -#include <linux/jiffies.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/stringify.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> - -#include <mach/processor-ns9360.h> -#include <mach/regs-sys-ns9360.h> -#include <mach/irqs.h> -#include <mach/system.h> -#include "generic.h" - -#define TIMER_CLOCKSOURCE 0 -#define TIMER_CLOCKEVENT 1 -static u32 latch; - -static cycle_t ns9360_clocksource_read(struct clocksource *cs) -{ - return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); -} - -static struct clocksource ns9360_clocksource = { - .name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE), - .rating = 300, - .read = ns9360_clocksource_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static void ns9360_clockevent_setmode(enum clock_event_mode mode, - struct clock_event_device *clk) -{ - u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); - REGSET(tc, SYS_TCx, REN, EN); - REGSET(tc, SYS_TCx, INTS, EN); - REGSET(tc, SYS_TCx, TEN, EN); - break; - - case CLOCK_EVT_MODE_ONESHOT: - REGSET(tc, SYS_TCx, REN, DIS); - REGSET(tc, SYS_TCx, INTS, EN); - - /* fall through */ - - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - default: - REGSET(tc, SYS_TCx, TEN, DIS); - break; - } - - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); -} - -static int ns9360_clockevent_setnextevent(unsigned long evt, - struct clock_event_device *clk) -{ - u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); - - if (REGGET(tc, SYS_TCx, TEN)) { - REGSET(tc, SYS_TCx, TEN, DIS); - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); - } - - REGSET(tc, SYS_TCx, TEN, EN); - - __raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT)); - - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); - - return 0; -} - -static struct clock_event_device ns9360_clockevent_device = { - .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), - .shift = 20, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_mode = ns9360_clockevent_setmode, - .set_next_event = ns9360_clockevent_setnextevent, -}; - -static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id) -{ - int timerno = irq - IRQ_NS9360_TIMER0; - u32 tc; - - struct clock_event_device *evt = &ns9360_clockevent_device; - - /* clear irq */ - tc = __raw_readl(SYS_TC(timerno)); - if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) { - REGSET(tc, SYS_TCx, TEN, DIS); - __raw_writel(tc, SYS_TC(timerno)); - } - REGSET(tc, SYS_TCx, INTC, SET); - __raw_writel(tc, SYS_TC(timerno)); - REGSET(tc, SYS_TCx, INTC, UNSET); - __raw_writel(tc, SYS_TC(timerno)); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction ns9360_clockevent_action = { - .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = ns9360_clockevent_handler, -}; - -static void __init ns9360_timer_init(void) -{ - int tc; - - tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE)); - if (REGGET(tc, SYS_TCx, TEN)) { - REGSET(tc, SYS_TCx, TEN, DIS); - __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); - } - - __raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE)); - - REGSET(tc, SYS_TCx, TEN, EN); - REGSET(tc, SYS_TCx, TDBG, STOP); - REGSET(tc, SYS_TCx, TLCS, CPU); - REGSET(tc, SYS_TCx, TM, IEE); - REGSET(tc, SYS_TCx, INTS, DIS); - REGSET(tc, SYS_TCx, UDS, UP); - REGSET(tc, SYS_TCx, TSZ, 32); - REGSET(tc, SYS_TCx, REN, EN); - - __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); - - clocksource_register_hz(&ns9360_clocksource, ns9360_cpuclock()); - - latch = SH_DIV(ns9360_cpuclock(), HZ, 0); - - tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); - REGSET(tc, SYS_TCx, TEN, DIS); - REGSET(tc, SYS_TCx, TDBG, STOP); - REGSET(tc, SYS_TCx, TLCS, CPU); - REGSET(tc, SYS_TCx, TM, IEE); - REGSET(tc, SYS_TCx, INTS, DIS); - REGSET(tc, SYS_TCx, UDS, DOWN); - REGSET(tc, SYS_TCx, TSZ, 32); - REGSET(tc, SYS_TCx, REN, EN); - __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); - - ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(), - NSEC_PER_SEC, ns9360_clockevent_device.shift); - ns9360_clockevent_device.max_delta_ns = - clockevent_delta2ns(-1, &ns9360_clockevent_device); - ns9360_clockevent_device.min_delta_ns = - clockevent_delta2ns(1, &ns9360_clockevent_device); - - ns9360_clockevent_device.cpumask = cpumask_of(0); - clockevents_register_device(&ns9360_clockevent_device); - - setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT, - &ns9360_clockevent_action); -} - -struct sys_timer ns9360_timer = { - .init = ns9360_timer_init, -}; diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c index acd161666408..1749cb37dda0 100644 --- a/arch/arm/mach-omap1/flash.c +++ b/arch/arm/mach-omap1/flash.c @@ -13,7 +13,7 @@ #include <plat/tc.h> #include <plat/flash.h> -void omap1_set_vpp(struct map_info *map, int enable) +void omap1_set_vpp(struct platform_device *pdev, int enable) { static int count; u32 l; diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c index 6588c22b8a64..fe31d933f0ed 100644 --- a/arch/arm/mach-omap1/pm_bus.c +++ b/arch/arm/mach-omap1/pm_bus.c @@ -24,75 +24,50 @@ #ifdef CONFIG_PM_RUNTIME static int omap1_pm_runtime_suspend(struct device *dev) { - struct clk *iclk, *fclk; - int ret = 0; + int ret; dev_dbg(dev, "%s\n", __func__); ret = pm_generic_runtime_suspend(dev); + if (ret) + return ret; - fclk = clk_get(dev, "fck"); - if (!IS_ERR(fclk)) { - clk_disable(fclk); - clk_put(fclk); - } - - iclk = clk_get(dev, "ick"); - if (!IS_ERR(iclk)) { - clk_disable(iclk); - clk_put(iclk); + ret = pm_runtime_clk_suspend(dev); + if (ret) { + pm_generic_runtime_resume(dev); + return ret; } return 0; -}; +} static int omap1_pm_runtime_resume(struct device *dev) { - struct clk *iclk, *fclk; - dev_dbg(dev, "%s\n", __func__); - iclk = clk_get(dev, "ick"); - if (!IS_ERR(iclk)) { - clk_enable(iclk); - clk_put(iclk); - } + pm_runtime_clk_resume(dev); + return pm_generic_runtime_resume(dev); +} - fclk = clk_get(dev, "fck"); - if (!IS_ERR(fclk)) { - clk_enable(fclk); - clk_put(fclk); - } +static struct dev_power_domain default_power_domain = { + .ops = { + .runtime_suspend = omap1_pm_runtime_suspend, + .runtime_resume = omap1_pm_runtime_resume, + USE_PLATFORM_PM_SLEEP_OPS + }, +}; - return pm_generic_runtime_resume(dev); +static struct pm_clk_notifier_block platform_bus_notifier = { + .pwr_domain = &default_power_domain, + .con_ids = { "ick", "fck", NULL, }, }; static int __init omap1_pm_runtime_init(void) { - const struct dev_pm_ops *pm; - struct dev_pm_ops *omap_pm; - if (!cpu_class_is_omap1()) return -ENODEV; - pm = platform_bus_get_pm_ops(); - if (!pm) { - pr_err("%s: unable to get dev_pm_ops from platform_bus\n", - __func__); - return -ENODEV; - } - - omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); - if (!omap_pm) { - pr_err("%s: unable to alloc memory for new dev_pm_ops\n", - __func__); - return -ENOMEM; - } - - omap_pm->runtime_suspend = omap1_pm_runtime_suspend; - omap_pm->runtime_resume = omap1_pm_runtime_resume; - - platform_bus_set_pm_ops(omap_pm); + pm_runtime_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); return 0; } diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 6885d2fac183..03e1e1062ad4 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -68,49 +68,50 @@ typedef struct { } omap_mpu_timer_regs_t; #define omap_mpu_timer_base(n) \ -((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ +((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ (n)*OMAP_MPU_TIMER_OFFSET)) static inline unsigned long notrace omap_mpu_timer_read(int nr) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); - return timer->read_tim; + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); + return readl(&timer->read_tim); } static inline void omap_mpu_set_autoreset(int nr) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); - timer->cntl = timer->cntl | MPU_TIMER_AR; + writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); } static inline void omap_mpu_remove_autoreset(int nr) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); - timer->cntl = timer->cntl & ~MPU_TIMER_AR; + writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); } static inline void omap_mpu_timer_start(int nr, unsigned long load_val, int autoreset) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); - unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST); + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); + unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST; - if (autoreset) timerflags |= MPU_TIMER_AR; + if (autoreset) + timerflags |= MPU_TIMER_AR; - timer->cntl = MPU_TIMER_CLOCK_ENABLE; + writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); udelay(1); - timer->load_tim = load_val; + writel(load_val, &timer->load_tim); udelay(1); - timer->cntl = timerflags; + writel(timerflags, &timer->cntl); } static inline void omap_mpu_timer_stop(int nr) { - volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); - timer->cntl &= ~MPU_TIMER_ST; + writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); } /* @@ -189,38 +190,11 @@ static __init void omap_init_mpu_timer(unsigned long rate) * --------------------------------------------------------------------------- */ -static unsigned long omap_mpu_timer2_overflows; - -static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id) -{ - omap_mpu_timer2_overflows++; - return IRQ_HANDLED; -} - -static struct irqaction omap_mpu_timer2_irq = { - .name = "mpu_timer2", - .flags = IRQF_DISABLED, - .handler = omap_mpu_timer2_interrupt, -}; - -static cycle_t mpu_read(struct clocksource *cs) -{ - return ~omap_mpu_timer_read(1); -} - -static struct clocksource clocksource_mpu = { - .name = "mpu_timer2", - .rating = 300, - .read = mpu_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static DEFINE_CLOCK_DATA(cd); static inline unsigned long long notrace _omap_mpu_sched_clock(void) { - u32 cyc = mpu_read(&clocksource_mpu); + u32 cyc = ~omap_mpu_timer_read(1); return cyc_to_sched_clock(&cd, cyc, (u32)~0); } @@ -238,21 +212,22 @@ static unsigned long long notrace omap_mpu_sched_clock(void) static void notrace mpu_update_sched_clock(void) { - u32 cyc = mpu_read(&clocksource_mpu); + u32 cyc = ~omap_mpu_timer_read(1); update_sched_clock(&cd, cyc, (u32)~0); } static void __init omap_init_clocksource(unsigned long rate) { + omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1); static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; - setup_irq(INT_TIMER2, &omap_mpu_timer2_irq); omap_mpu_timer_start(1, ~0, 1); init_sched_clock(&cd, mpu_update_sched_clock, 32, rate); - if (clocksource_register_hz(&clocksource_mpu, rate)) - printk(err, clocksource_mpu.name); + if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, + 300, 32, clocksource_mmio_readl_down)) + printk(err, "mpu_timer2"); } static void __init omap_mpu_timer_init(void) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 512b15204450..66dfbccacd25 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -59,10 +59,10 @@ endif # Power Management ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \ - cpuidle34xx.o pm_bus.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o + cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index b2b1e37bb6bb..d6e34dd9e7e7 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -115,6 +115,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); + clk->rate = rate; return 0; } diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index de441c05a6a6..e4bd87619734 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h @@ -33,4 +33,11 @@ extern void __iomem *gic_dist_base_addr; extern void __init gic_init_irq(void); extern void omap_smc1(u32 fn, u32 arg); +#ifdef CONFIG_SMP +/* Needed for secondary core boot */ +extern void omap_secondary_startup(void); +extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); +extern void omap_auxcoreboot_addr(u32 cpu_addr); +extern u32 omap_read_auxcoreboot0(void); +#endif #endif diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index b66cfe8bc464..ecfe93c4b585 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -21,6 +21,7 @@ #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <mach/hardware.h> #include <mach/omap4-common.h> @@ -63,7 +64,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) omap_modify_auxcoreboot0(0x200, 0xfffffdff); flush_cache_all(); smp_wmb(); - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); /* * Now the secondary core is starting up let it run its @@ -118,6 +119,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c deleted file mode 100644 index 5acd2ab298b1..000000000000 --- a/arch/arm/mach-omap2/pm_bus.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Runtime PM support code for OMAP - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * Copyright (C) 2010 Texas Instruments, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/pm_runtime.h> -#include <linux/platform_device.h> -#include <linux/mutex.h> - -#include <plat/omap_device.h> -#include <plat/omap-pm.h> - -#ifdef CONFIG_PM_RUNTIME -static int omap_pm_runtime_suspend(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - int r, ret = 0; - - dev_dbg(dev, "%s\n", __func__); - - ret = pm_generic_runtime_suspend(dev); - - if (!ret && dev->parent == &omap_device_parent) { - r = omap_device_idle(pdev); - WARN_ON(r); - } - - return ret; -}; - -static int omap_pm_runtime_resume(struct device *dev) -{ - struct platform_device *pdev = to_platform_device(dev); - int r; - - dev_dbg(dev, "%s\n", __func__); - - if (dev->parent == &omap_device_parent) { - r = omap_device_enable(pdev); - WARN_ON(r); - } - - return pm_generic_runtime_resume(dev); -}; -#else -#define omap_pm_runtime_suspend NULL -#define omap_pm_runtime_resume NULL -#endif /* CONFIG_PM_RUNTIME */ - -static int __init omap_pm_runtime_init(void) -{ - const struct dev_pm_ops *pm; - struct dev_pm_ops *omap_pm; - - pm = platform_bus_get_pm_ops(); - if (!pm) { - pr_err("%s: unable to get dev_pm_ops from platform_bus\n", - __func__); - return -ENODEV; - } - - omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); - if (!omap_pm) { - pr_err("%s: unable to alloc memory for new dev_pm_ops\n", - __func__); - return -ENOMEM; - } - - omap_pm->runtime_suspend = omap_pm_runtime_suspend; - omap_pm->runtime_resume = omap_pm_runtime_resume; - - platform_bus_set_pm_ops(omap_pm); - - return 0; -} -core_initcall(omap_pm_runtime_init); diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index bfbecec6d05f..810a982a66f8 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/bitops.h> diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c index 1ce090448493..1d5859d9a0e3 100644 --- a/arch/arm/mach-pxa/clock-pxa2xx.c +++ b/arch/arm/mach-pxa/clock-pxa2xx.c @@ -9,7 +9,7 @@ #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/pxa2xx-regs.h> @@ -33,32 +33,22 @@ const struct clkops clk_pxa2xx_cken_ops = { #ifdef CONFIG_PM static uint32_t saved_cken; -static int pxa2xx_clock_suspend(struct sys_device *d, pm_message_t state) +static int pxa2xx_clock_suspend(void) { saved_cken = CKEN; return 0; } -static int pxa2xx_clock_resume(struct sys_device *d) +static void pxa2xx_clock_resume(void) { CKEN = saved_cken; - return 0; } #else #define pxa2xx_clock_suspend NULL #define pxa2xx_clock_resume NULL #endif -struct sysdev_class pxa2xx_clock_sysclass = { - .name = "pxa2xx-clock", +struct syscore_ops pxa2xx_clock_syscore_ops = { .suspend = pxa2xx_clock_suspend, .resume = pxa2xx_clock_resume, }; - -static int __init pxa2xx_clock_init(void) -{ - if (cpu_is_pxa2xx()) - return sysdev_class_register(&pxa2xx_clock_sysclass); - return 0; -} -postcore_initcall(pxa2xx_clock_init); diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c index 3f864cd0bd28..2a37a9a8f621 100644 --- a/arch/arm/mach-pxa/clock-pxa3xx.c +++ b/arch/arm/mach-pxa/clock-pxa3xx.c @@ -10,6 +10,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/syscore_ops.h> #include <mach/smemc.h> #include <mach/pxa3xx-regs.h> @@ -182,7 +183,7 @@ const struct clkops clk_pxa3xx_pout_ops = { static uint32_t cken[2]; static uint32_t accr; -static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state) +static int pxa3xx_clock_suspend(void) { cken[0] = CKENA; cken[1] = CKENB; @@ -190,28 +191,18 @@ static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state) return 0; } -static int pxa3xx_clock_resume(struct sys_device *d) +static void pxa3xx_clock_resume(void) { ACCR = accr; CKENA = cken[0]; CKENB = cken[1]; - return 0; } #else #define pxa3xx_clock_suspend NULL #define pxa3xx_clock_resume NULL #endif -struct sysdev_class pxa3xx_clock_sysclass = { - .name = "pxa3xx-clock", +struct syscore_ops pxa3xx_clock_syscore_ops = { .suspend = pxa3xx_clock_suspend, .resume = pxa3xx_clock_resume, }; - -static int __init pxa3xx_clock_init(void) -{ - if (cpu_is_pxa3xx() || cpu_is_pxa95x()) - return sysdev_class_register(&pxa3xx_clock_sysclass); - return 0; -} -postcore_initcall(pxa3xx_clock_init); diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index f9f349a21b54..1f2fb9c43f06 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h @@ -1,5 +1,5 @@ #include <linux/clkdev.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> struct clkops { void (*enable)(struct clk *); @@ -54,7 +54,7 @@ extern const struct clkops clk_pxa2xx_cken_ops; void clk_pxa2xx_cken_enable(struct clk *clk); void clk_pxa2xx_cken_disable(struct clk *clk); -extern struct sysdev_class pxa2xx_clock_sysclass; +extern struct syscore_ops pxa2xx_clock_syscore_ops; #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) #define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ @@ -74,5 +74,6 @@ extern const struct clkops clk_pxa3xx_smemc_ops; extern void clk_pxa3xx_cken_enable(struct clk *); extern void clk_pxa3xx_cken_disable(struct clk *); -extern struct sysdev_class pxa3xx_clock_sysclass; +extern struct syscore_ops pxa3xx_clock_syscore_ops; + #endif diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index b88d601a8090..13518a705399 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -10,7 +10,6 @@ */ #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/irq.h> #include <linux/gpio.h> #include <linux/delay.h> diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index 8b1a30959fae..1afc0fb7d6d5 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -29,33 +29,6 @@ unsigned long it8152_base_address; static int cmx2xx_it8152_irq_gpio; -/* - * Only first 64MB of memory can be accessed via PCI. - * We use GFP_DMA to allocate safe buffers to do map/unmap. - * This is really ugly and we need a better way of specifying - * DMA-capable regions of memory. - */ -void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size, - unsigned long *zhole_size) -{ - unsigned int sz = SZ_64M >> PAGE_SHIFT; - - if (machine_is_armcore()) { - pr_info("Adjusting zones for CM-X2XX\n"); - - /* - * Only adjust if > 64M on current system - */ - if (zone_size[0] <= sz) - return; - - zone_size[1] = zone_size[0] - sz; - zone_size[0] = sz; - zhole_size[1] = zhole_size[0]; - zhole_size[0] = 0; - } -} - static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) { /* clear our parent irq */ diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index 8225e2e58c6e..a10996782476 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -10,7 +10,7 @@ */ #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/irq.h> #include <linux/gpio.h> @@ -388,7 +388,7 @@ static inline void cmx2xx_init_display(void) {} #ifdef CONFIG_PM static unsigned long sleep_save_msc[10]; -static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state) +static int cmx2xx_suspend(void) { cmx2xx_pci_suspend(); @@ -412,7 +412,7 @@ static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int cmx2xx_resume(struct sys_device *dev) +static void cmx2xx_resume(void) { cmx2xx_pci_resume(); @@ -420,27 +420,18 @@ static int cmx2xx_resume(struct sys_device *dev) __raw_writel(sleep_save_msc[0], MSC0); __raw_writel(sleep_save_msc[1], MSC1); __raw_writel(sleep_save_msc[2], MSC2); - - return 0; } -static struct sysdev_class cmx2xx_pm_sysclass = { - .name = "pm", +static struct syscore_ops cmx2xx_pm_syscore_ops = { .resume = cmx2xx_resume, .suspend = cmx2xx_suspend, }; -static struct sys_device cmx2xx_pm_device = { - .cls = &cmx2xx_pm_sysclass, -}; - static int __init cmx2xx_pm_init(void) { - int error; - error = sysdev_class_register(&cmx2xx_pm_sysclass); - if (error == 0) - error = sysdev_register(&cmx2xx_pm_device); - return error; + register_syscore_ops(&cmx2xx_pm_syscore_ops); + + return 0; } #else static int __init cmx2xx_pm_init(void) { return 0; } diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c index 81c3c433e2d6..d28e802e2448 100644 --- a/arch/arm/mach-pxa/colibri-evalboard.c +++ b/arch/arm/mach-pxa/colibri-evalboard.c @@ -13,7 +13,6 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/gpio.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index 44c1b77ece67..80538b8806ed 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c @@ -22,7 +22,6 @@ #include <linux/platform_device.h> #include <linux/pwm_backlight.h> #include <linux/i2c/pxa-i2c.h> -#include <linux/sysdev.h> #include <asm/irq.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index 6fc5d328ba7f..7545a48ed88b 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c @@ -17,7 +17,6 @@ #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/ucb1400.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index a079d8baa45a..e6c9344a95ae 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -61,10 +61,10 @@ extern unsigned pxa3xx_get_clk_frequency_khz(int); #define pxa3xx_get_clk_frequency_khz(x) (0) #endif -extern struct sysdev_class pxa_irq_sysclass; -extern struct sysdev_class pxa_gpio_sysclass; -extern struct sysdev_class pxa2xx_mfp_sysclass; -extern struct sysdev_class pxa3xx_mfp_sysclass; +extern struct syscore_ops pxa_irq_syscore_ops; +extern struct syscore_ops pxa_gpio_syscore_ops; +extern struct syscore_ops pxa2xx_mfp_syscore_ops; +extern struct syscore_ops pxa3xx_mfp_syscore_ops; void __init pxa_set_ffuart_info(void *info); void __init pxa_set_btuart_info(void *info); diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 9cdcca597924..f941a495a4a8 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -735,7 +735,7 @@ static struct platform_device bq24022 = { * StrataFlash */ -static void hx4700_set_vpp(struct map_info *map, int vpp) +static void hx4700_set_vpp(struct platform_device *pdev, int vpp) { gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp); } diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h index 7f68724dcc27..07734f37f8fd 100644 --- a/arch/arm/mach-pxa/include/mach/memory.h +++ b/arch/arm/mach-pxa/include/mach/memory.h @@ -17,14 +17,8 @@ */ #define PLAT_PHYS_OFFSET UL(0xa0000000) -#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) -void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(size, holes) \ - cmx2xx_pci_adjust_zones(size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M) +#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) +#define ARM_DMA_ZONE_SIZE SZ_64M #endif #endif diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 6251e3f5c62c..32ed551bf9c5 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <linux/irq.h> @@ -183,7 +183,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; -static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) +static int pxa_irq_suspend(void) { int i; @@ -202,7 +202,7 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int pxa_irq_resume(struct sys_device *dev) +static void pxa_irq_resume(void) { int i; @@ -218,22 +218,13 @@ static int pxa_irq_resume(struct sys_device *dev) __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); __raw_writel(1, IRQ_BASE + ICCR); - return 0; } #else #define pxa_irq_suspend NULL #define pxa_irq_resume NULL #endif -struct sysdev_class pxa_irq_sysclass = { - .name = "irq", +struct syscore_ops pxa_irq_syscore_ops = { .suspend = pxa_irq_suspend, .resume = pxa_irq_resume, }; - -static int __init pxa_irq_init(void) -{ - return sysdev_class_register(&pxa_irq_sysclass); -} - -core_initcall(pxa_irq_init); diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index f5de541725b1..6cf8180bf5bd 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/bitops.h> @@ -159,30 +159,22 @@ static void __init lpd270_init_irq(void) #ifdef CONFIG_PM -static int lpd270_irq_resume(struct sys_device *dev) +static void lpd270_irq_resume(void) { __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK); - return 0; } -static struct sysdev_class lpd270_irq_sysclass = { - .name = "cpld_irq", +static struct syscore_ops lpd270_irq_syscore_ops = { .resume = lpd270_irq_resume, }; -static struct sys_device lpd270_irq_device = { - .cls = &lpd270_irq_sysclass, -}; - static int __init lpd270_irq_device_init(void) { - int ret = -ENODEV; if (machine_is_logicpd_pxa270()) { - ret = sysdev_class_register(&lpd270_irq_sysclass); - if (ret == 0) - ret = sysdev_register(&lpd270_irq_device); + register_syscore_ops(&lpd270_irq_syscore_ops); + return 0; } - return ret; + return -ENODEV; } device_initcall(lpd270_irq_device_init); diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 3ede978c83d9..e10ddb827147 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -15,7 +15,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/major.h> #include <linux/fb.h> #include <linux/interrupt.h> @@ -176,31 +176,22 @@ static void __init lubbock_init_irq(void) #ifdef CONFIG_PM -static int lubbock_irq_resume(struct sys_device *dev) +static void lubbock_irq_resume(void) { LUB_IRQ_MASK_EN = lubbock_irq_enabled; - return 0; } -static struct sysdev_class lubbock_irq_sysclass = { - .name = "cpld_irq", +static struct syscore_ops lubbock_irq_syscore_ops = { .resume = lubbock_irq_resume, }; -static struct sys_device lubbock_irq_device = { - .cls = &lubbock_irq_sysclass, -}; - static int __init lubbock_irq_device_init(void) { - int ret = -ENODEV; - if (machine_is_lubbock()) { - ret = sysdev_class_register(&lubbock_irq_sysclass); - if (ret == 0) - ret = sysdev_register(&lubbock_irq_device); + register_syscore_ops(&lubbock_irq_syscore_ops); + return 0; } - return ret; + return -ENODEV; } device_initcall(lubbock_irq_device_init); diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 9984ef70bd79..e1920572948a 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -662,7 +662,7 @@ static struct pxaohci_platform_data magician_ohci_info = { * StrataFlash */ -static void magician_set_vpp(struct map_info *map, int vpp) +static void magician_set_vpp(struct platform_device *pdev, int vpp) { gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); } diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 95163baca29e..3479e2b3b511 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/bitops.h> @@ -185,31 +185,21 @@ static void __init mainstone_init_irq(void) #ifdef CONFIG_PM -static int mainstone_irq_resume(struct sys_device *dev) +static void mainstone_irq_resume(void) { MST_INTMSKENA = mainstone_irq_enabled; - return 0; } -static struct sysdev_class mainstone_irq_sysclass = { - .name = "cpld_irq", +static struct syscore_ops mainstone_irq_syscore_ops = { .resume = mainstone_irq_resume, }; -static struct sys_device mainstone_irq_device = { - .cls = &mainstone_irq_sysclass, -}; - static int __init mainstone_irq_device_init(void) { - int ret = -ENODEV; + if (machine_is_mainstone()) + register_syscore_ops(&mainstone_irq_syscore_ops); - if (machine_is_mainstone()) { - ret = sysdev_class_register(&mainstone_irq_sysclass); - if (ret == 0) - ret = sysdev_register(&mainstone_irq_device); - } - return ret; + return 0; } device_initcall(mainstone_irq_device_init); diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 1d1419b73457..87ae3129f4f7 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c @@ -16,7 +16,7 @@ #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/gpio.h> #include <mach/pxa2xx-regs.h> @@ -338,7 +338,7 @@ static unsigned long saved_gafr[2][4]; static unsigned long saved_gpdr[4]; static unsigned long saved_pgsr[4]; -static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) +static int pxa2xx_mfp_suspend(void) { int i; @@ -365,7 +365,7 @@ static int pxa2xx_mfp_suspend(struct sys_device *d, pm_message_t state) return 0; } -static int pxa2xx_mfp_resume(struct sys_device *d) +static void pxa2xx_mfp_resume(void) { int i; @@ -376,15 +376,13 @@ static int pxa2xx_mfp_resume(struct sys_device *d) PGSR(i) = saved_pgsr[i]; } PSSR = PSSR_RDH | PSSR_PH; - return 0; } #else #define pxa2xx_mfp_suspend NULL #define pxa2xx_mfp_resume NULL #endif -struct sysdev_class pxa2xx_mfp_sysclass = { - .name = "mfp", +struct syscore_ops pxa2xx_mfp_syscore_ops = { .suspend = pxa2xx_mfp_suspend, .resume = pxa2xx_mfp_resume, }; @@ -409,6 +407,6 @@ static int __init pxa2xx_mfp_init(void) for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) gpdr_lpm[i] = GPDR(i * 32); - return sysdev_class_register(&pxa2xx_mfp_sysclass); + return 0; } postcore_initcall(pxa2xx_mfp_init); diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c index 7a270eecd480..89863a01ecd7 100644 --- a/arch/arm/mach-pxa/mfp-pxa3xx.c +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c @@ -17,7 +17,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/hardware.h> #include <mach/mfp-pxa3xx.h> @@ -31,13 +31,13 @@ * a pull-down mode if they're an active low chip select, and we're * just entering standby. */ -static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state) +static int pxa3xx_mfp_suspend(void) { mfp_config_lpm(); return 0; } -static int pxa3xx_mfp_resume(struct sys_device *d) +static void pxa3xx_mfp_resume(void) { mfp_config_run(); @@ -47,24 +47,13 @@ static int pxa3xx_mfp_resume(struct sys_device *d) * preserve them here in case they will be referenced later */ ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); - return 0; } #else #define pxa3xx_mfp_suspend NULL #define pxa3xx_mfp_resume NULL #endif -struct sysdev_class pxa3xx_mfp_sysclass = { - .name = "mfp", +struct syscore_ops pxa3xx_mfp_syscore_ops = { .suspend = pxa3xx_mfp_suspend, - .resume = pxa3xx_mfp_resume, + .resume = pxa3xx_mfp_resume, }; - -static int __init mfp_init_devicefs(void) -{ - if (cpu_is_pxa3xx()) - return sysdev_class_register(&pxa3xx_mfp_sysclass); - - return 0; -} -postcore_initcall(mfp_init_devicefs); diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 23925db8ff74..e3470137c934 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -22,7 +22,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/input.h> #include <linux/delay.h> #include <linux/gpio_keys.h> @@ -488,7 +488,7 @@ static void install_bootstrap(void) } -static int mioa701_sys_suspend(struct sys_device *sysdev, pm_message_t state) +static int mioa701_sys_suspend(void) { int i = 0, is_bt_on; u32 *mem_resume_vector = phys_to_virt(RESUME_VECTOR_ADDR); @@ -514,7 +514,7 @@ static int mioa701_sys_suspend(struct sys_device *sysdev, pm_message_t state) return 0; } -static int mioa701_sys_resume(struct sys_device *sysdev) +static void mioa701_sys_resume(void) { int i = 0; u32 *mem_resume_vector = phys_to_virt(RESUME_VECTOR_ADDR); @@ -527,43 +527,18 @@ static int mioa701_sys_resume(struct sys_device *sysdev) *mem_resume_enabler = save_buffer[i++]; *mem_resume_bt = save_buffer[i++]; *mem_resume_unknown = save_buffer[i++]; - - return 0; } -static struct sysdev_class mioa701_sysclass = { - .name = "mioa701", -}; - -static struct sys_device sysdev_bootstrap = { - .cls = &mioa701_sysclass, -}; - -static struct sysdev_driver driver_bootstrap = { - .suspend = &mioa701_sys_suspend, - .resume = &mioa701_sys_resume, +static struct syscore_ops mioa701_syscore_ops = { + .suspend = mioa701_sys_suspend, + .resume = mioa701_sys_resume, }; static int __init bootstrap_init(void) { - int rc; int save_size = mioa701_bootstrap_lg + (sizeof(u32) * 3); - rc = sysdev_class_register(&mioa701_sysclass); - if (rc) { - printk(KERN_ERR "Failed registering mioa701 sys class\n"); - return -ENODEV; - } - rc = sysdev_register(&sysdev_bootstrap); - if (rc) { - printk(KERN_ERR "Failed registering mioa701 sys device\n"); - return -ENODEV; - } - rc = sysdev_driver_register(&mioa701_sysclass, &driver_bootstrap); - if (rc) { - printk(KERN_ERR "Failed registering PMU sys driver\n"); - return -ENODEV; - } + register_syscore_ops(&mioa701_syscore_ops); save_buffer = kmalloc(save_size, GFP_KERNEL); if (!save_buffer) @@ -576,9 +551,7 @@ static int __init bootstrap_init(void) static void bootstrap_exit(void) { kfree(save_buffer); - sysdev_driver_unregister(&mioa701_sysclass, &driver_bootstrap); - sysdev_unregister(&sysdev_bootstrap); - sysdev_class_unregister(&mioa701_sysclass); + unregister_syscore_ops(&mioa701_syscore_ops); printk(KERN_CRIT "Unregistering mioa701 suspend will hang next" "resume !!!\n"); diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index a6f898cbfac9..4061ecddee70 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -24,7 +24,6 @@ #include <linux/gpio.h> #include <linux/wm97xx.h> #include <linux/power_supply.h> -#include <linux/sysdev.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 8aadad55fbe4..20d1b18b1733 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -25,7 +25,6 @@ #include <linux/pwm_backlight.h> #include <linux/gpio.h> #include <linux/power_supply.h> -#include <linux/sysdev.h> #include <linux/w1-gpio.h> #include <asm/mach-types.h> diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 3b8a4f37dbbe..65f24f0b77e8 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -19,7 +19,7 @@ */ #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/delay.h> #include <linux/irq.h> #include <linux/gpio_keys.h> @@ -233,9 +233,9 @@ static struct palmz72_resume_info palmz72_resume_info = { static unsigned long store_ptr; -/* sys_device for Palm Zire 72 PM */ +/* syscore_ops for Palm Zire 72 PM */ -static int palmz72_pm_suspend(struct sys_device *dev, pm_message_t msg) +static int palmz72_pm_suspend(void) { /* setup the resume_info struct for the original bootloader */ palmz72_resume_info.resume_addr = (u32) cpu_resume; @@ -249,31 +249,23 @@ static int palmz72_pm_suspend(struct sys_device *dev, pm_message_t msg) return 0; } -static int palmz72_pm_resume(struct sys_device *dev) +static void palmz72_pm_resume(void) { *PALMZ72_SAVE_DWORD = store_ptr; - return 0; } -static struct sysdev_class palmz72_pm_sysclass = { - .name = "palmz72_pm", +static struct syscore_ops palmz72_pm_syscore_ops = { .suspend = palmz72_pm_suspend, .resume = palmz72_pm_resume, }; -static struct sys_device palmz72_pm_device = { - .cls = &palmz72_pm_sysclass, -}; - static int __init palmz72_pm_init(void) { - int ret = -ENODEV; if (machine_is_palmz72()) { - ret = sysdev_class_register(&palmz72_pm_sysclass); - if (ret == 0) - ret = sysdev_register(&palmz72_pm_device); + register_syscore_ops(&palmz72_pm_syscore_ops); + return 0; } - return ret; + return -ENODEV; } device_initcall(palmz72_pm_init); diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index a4af8c52d7ee..fed363cec9c6 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -21,7 +21,7 @@ #include <linux/init.h> #include <linux/platform_device.h> #include <linux/suspend.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/irq.h> #include <asm/mach/map.h> @@ -350,21 +350,9 @@ static struct platform_device *pxa25x_devices[] __initdata = { &pxa_device_asoc_platform, }; -static struct sys_device pxa25x_sysdev[] = { - { - .cls = &pxa_irq_sysclass, - }, { - .cls = &pxa2xx_mfp_sysclass, - }, { - .cls = &pxa_gpio_sysclass, - }, { - .cls = &pxa2xx_clock_sysclass, - } -}; - static int __init pxa25x_init(void) { - int i, ret = 0; + int ret = 0; if (cpu_is_pxa25x()) { @@ -377,11 +365,10 @@ static int __init pxa25x_init(void) pxa25x_init_pm(); - for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) { - ret = sysdev_register(&pxa25x_sysdev[i]); - if (ret) - pr_err("failed to register sysdev[%d]\n", i); - } + register_syscore_ops(&pxa_irq_syscore_ops); + register_syscore_ops(&pxa2xx_mfp_syscore_ops); + register_syscore_ops(&pxa_gpio_syscore_ops); + register_syscore_ops(&pxa2xx_clock_syscore_ops); ret = platform_add_devices(pxa25x_devices, ARRAY_SIZE(pxa25x_devices)); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 909756eaf4b7..2fecbec58d88 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -16,7 +16,7 @@ #include <linux/init.h> #include <linux/suspend.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/i2c/pxa-i2c.h> @@ -428,21 +428,9 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_pwm1, }; -static struct sys_device pxa27x_sysdev[] = { - { - .cls = &pxa_irq_sysclass, - }, { - .cls = &pxa2xx_mfp_sysclass, - }, { - .cls = &pxa_gpio_sysclass, - }, { - .cls = &pxa2xx_clock_sysclass, - } -}; - static int __init pxa27x_init(void) { - int i, ret = 0; + int ret = 0; if (cpu_is_pxa27x()) { @@ -455,11 +443,10 @@ static int __init pxa27x_init(void) pxa27x_init_pm(); - for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) { - ret = sysdev_register(&pxa27x_sysdev[i]); - if (ret) - pr_err("failed to register sysdev[%d]\n", i); - } + register_syscore_ops(&pxa_irq_syscore_ops); + register_syscore_ops(&pxa2xx_mfp_syscore_ops); + register_syscore_ops(&pxa_gpio_syscore_ops); + register_syscore_ops(&pxa2xx_clock_syscore_ops); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 8dd107391157..8521d7d6f1da 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -20,7 +20,7 @@ #include <linux/platform_device.h> #include <linux/irq.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/i2c/pxa-i2c.h> #include <asm/mach/map.h> @@ -427,21 +427,9 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_pwm1, }; -static struct sys_device pxa3xx_sysdev[] = { - { - .cls = &pxa_irq_sysclass, - }, { - .cls = &pxa3xx_mfp_sysclass, - }, { - .cls = &pxa_gpio_sysclass, - }, { - .cls = &pxa3xx_clock_sysclass, - } -}; - static int __init pxa3xx_init(void) { - int i, ret = 0; + int ret = 0; if (cpu_is_pxa3xx()) { @@ -462,11 +450,10 @@ static int __init pxa3xx_init(void) pxa3xx_init_pm(); - for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { - ret = sysdev_register(&pxa3xx_sysdev[i]); - if (ret) - pr_err("failed to register sysdev[%d]\n", i); - } + register_syscore_ops(&pxa_irq_syscore_ops); + register_syscore_ops(&pxa3xx_mfp_syscore_ops); + register_syscore_ops(&pxa_gpio_syscore_ops); + register_syscore_ops(&pxa3xx_clock_syscore_ops); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c index 23b229bd06e9..ecc82a330fad 100644 --- a/arch/arm/mach-pxa/pxa95x.c +++ b/arch/arm/mach-pxa/pxa95x.c @@ -18,7 +18,7 @@ #include <linux/i2c/pxa-i2c.h> #include <linux/irq.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/hardware.h> #include <mach/gpio.h> @@ -260,16 +260,6 @@ static struct platform_device *devices[] __initdata = { &pxa27x_device_pwm1, }; -static struct sys_device pxa95x_sysdev[] = { - { - .cls = &pxa_irq_sysclass, - }, { - .cls = &pxa_gpio_sysclass, - }, { - .cls = &pxa3xx_clock_sysclass, - } -}; - static int __init pxa95x_init(void) { int ret = 0, i; @@ -293,11 +283,9 @@ static int __init pxa95x_init(void) if ((ret = pxa_init_dma(IRQ_DMA, 32))) return ret; - for (i = 0; i < ARRAY_SIZE(pxa95x_sysdev); i++) { - ret = sysdev_register(&pxa95x_sysdev[i]); - if (ret) - pr_err("failed to register sysdev[%d]\n", i); - } + register_syscore_ops(&pxa_irq_syscore_ops); + register_syscore_ops(&pxa_gpio_syscore_ops); + register_syscore_ops(&pxa3xx_clock_syscore_ops); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index cd1861351f75..d130f77b6d11 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c @@ -18,7 +18,6 @@ #include <linux/init.h> #include <linux/kernel.h> -#include <linux/sysdev.h> #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/gpio.h> diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index 232b7316ec08..79923058d10f 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c @@ -6,7 +6,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/hardware.h> #include <mach/smemc.h> @@ -16,7 +16,7 @@ static unsigned long msc[2]; static unsigned long sxcnfg, memclkcfg; static unsigned long csadrcfg[4]; -static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) +static int pxa3xx_smemc_suspend(void) { msc[0] = __raw_readl(MSC0); msc[1] = __raw_readl(MSC1); @@ -30,7 +30,7 @@ static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int pxa3xx_smemc_resume(struct sys_device *dev) +static void pxa3xx_smemc_resume(void) { __raw_writel(msc[0], MSC0); __raw_writel(msc[1], MSC1); @@ -40,34 +40,19 @@ static int pxa3xx_smemc_resume(struct sys_device *dev) __raw_writel(csadrcfg[1], CSADRCFG1); __raw_writel(csadrcfg[2], CSADRCFG2); __raw_writel(csadrcfg[3], CSADRCFG3); - - return 0; } -static struct sysdev_class smemc_sysclass = { - .name = "smemc", +static struct syscore_ops smemc_syscore_ops = { .suspend = pxa3xx_smemc_suspend, .resume = pxa3xx_smemc_resume, }; -static struct sys_device smemc_sysdev = { - .id = 0, - .cls = &smemc_sysclass, -}; - static int __init smemc_init(void) { - int ret = 0; + if (cpu_is_pxa3xx()) + register_syscore_ops(&smemc_syscore_ops); - if (cpu_is_pxa3xx()) { - ret = sysdev_class_register(&smemc_sysclass); - if (ret) - return ret; - - ret = sysdev_register(&smemc_sysdev); - } - - return ret; + return 0; } subsys_initcall(smemc_init); #endif diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 428da3ff33a5..de684701449c 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -105,19 +105,6 @@ static struct clock_event_device ckevt_pxa_osmr0 = { .set_mode = pxa_osmr0_set_mode, }; -static cycle_t pxa_read_oscr(struct clocksource *cs) -{ - return OSCR; -} - -static struct clocksource cksrc_pxa_oscr0 = { - .name = "oscr0", - .rating = 200, - .read = pxa_read_oscr, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static struct irqaction pxa_ost0_irq = { .name = "ost0", .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, @@ -134,7 +121,6 @@ static void __init pxa_timer_init(void) init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); - clocksource_calc_mult_shift(&cksrc_pxa_oscr0, clock_tick_rate, 4); clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4); ckevt_pxa_osmr0.max_delta_ns = clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); @@ -144,7 +130,8 @@ static void __init pxa_timer_init(void) setup_irq(IRQ_OST0, &pxa_ost0_irq); - clocksource_register_hz(&cksrc_pxa_oscr0, clock_tick_rate); + clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32, + clocksource_mmio_readl_up); clockevents_register_device(&ckevt_pxa_osmr0); } diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index b9cfbebdfe9c..687417a93698 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -15,7 +15,6 @@ #include <linux/init.h> #include <linux/kernel.h> #include <linux/platform_device.h> -#include <linux/sysdev.h> #include <linux/interrupt.h> #include <linux/sched.h> #include <linux/bitops.h> diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index b523f119e0f0..903218eab56d 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -44,6 +44,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/physmap.h> +#include <linux/syscore_ops.h> #include <mach/pxa25x.h> #include <mach/audio.h> @@ -130,20 +131,19 @@ static u8 viper_hw_version(void) return v1; } -/* CPU sysdev */ -static int viper_cpu_suspend(struct sys_device *sysdev, pm_message_t state) +/* CPU system core operations. */ +static int viper_cpu_suspend(void) { viper_icr_set_bit(VIPER_ICR_R_DIS); return 0; } -static int viper_cpu_resume(struct sys_device *sysdev) +static void viper_cpu_resume(void) { viper_icr_clear_bit(VIPER_ICR_R_DIS); - return 0; } -static struct sysdev_driver viper_cpu_sysdev_driver = { +static struct syscore_ops viper_cpu_syscore_ops = { .suspend = viper_cpu_suspend, .resume = viper_cpu_resume, }; @@ -945,7 +945,7 @@ static void __init viper_init(void) viper_init_vcore_gpios(); viper_init_cpufreq(); - sysdev_driver_register(&cpu_sysdev_class, &viper_cpu_sysdev_driver); + register_syscore_ops(&viper_cpu_syscore_ops); if (version) { pr_info("viper: hardware v%di%d detected. " diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index f71d377c8640..67bd41488bf8 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c @@ -16,7 +16,6 @@ #include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/gpio.h> -#include <linux/sysdev.h> #include <linux/usb/gpio_vbus.h> #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 75dbc8791d05..5c23450d2d1d 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -31,6 +31,7 @@ #include <linux/amba/mmci.h> #include <linux/gfp.h> #include <linux/clkdev.h> +#include <linux/mtd/physmap.h> #include <asm/system.h> #include <mach/hardware.h> @@ -41,7 +42,6 @@ #include <asm/hardware/icst.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irq.h> #include <asm/mach/map.h> @@ -56,48 +56,9 @@ #include "core.h" -#ifdef CONFIG_ZONE_DMA -/* - * Adjust the zones if there are restrictions for DMA access. - */ -void __init realview_adjust_zones(unsigned long *size, unsigned long *hole) -{ - unsigned long dma_size = SZ_256M >> PAGE_SHIFT; - - if (!machine_is_realview_pbx() || size[0] <= dma_size) - return; - - size[ZONE_NORMAL] = size[0] - dma_size; - size[ZONE_DMA] = dma_size; - hole[ZONE_NORMAL] = hole[0]; - hole[ZONE_DMA] = 0; -} -#endif - - #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) -static int realview_flash_init(void) -{ - u32 val; - - val = __raw_readl(REALVIEW_FLASHCTRL); - val &= ~REALVIEW_FLASHPROG_FLVPPEN; - __raw_writel(val, REALVIEW_FLASHCTRL); - - return 0; -} - -static void realview_flash_exit(void) -{ - u32 val; - - val = __raw_readl(REALVIEW_FLASHCTRL); - val &= ~REALVIEW_FLASHPROG_FLVPPEN; - __raw_writel(val, REALVIEW_FLASHCTRL); -} - -static void realview_flash_set_vpp(int on) +static void realview_flash_set_vpp(struct platform_device *pdev, int on) { u32 val; @@ -109,16 +70,13 @@ static void realview_flash_set_vpp(int on) __raw_writel(val, REALVIEW_FLASHCTRL); } -static struct flash_platform_data realview_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data realview_flash_data = { .width = 4, - .init = realview_flash_init, - .exit = realview_flash_exit, .set_vpp = realview_flash_set_vpp, }; struct platform_device realview_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &realview_flash_data, @@ -315,6 +273,10 @@ static struct clk ref24_clk = { .rate = 24000000, }; +static struct clk sp804_clk = { + .rate = 1000000, +}; + static struct clk dummy_apb_pclk; static struct clk_lookup lookups[] = { @@ -357,7 +319,10 @@ static struct clk_lookup lookups[] = { }, { /* SSP */ .dev_id = "dev:ssp0", .clk = &ref24_clk, - } + }, { /* SP804 timers */ + .dev_id = "sp804", + .clk = &sp804_clk, + }, }; void __init realview_init_early(void) @@ -545,8 +510,8 @@ void __init realview_timer_init(unsigned int timer_irq) writel(0, timer2_va_base + TIMER_CTRL); writel(0, timer3_va_base + TIMER_CTRL); - sp804_clocksource_init(timer3_va_base); - sp804_clockevents_init(timer0_va_base, timer_irq); + sp804_clocksource_init(timer3_va_base, "timer3"); + sp804_clockevents_init(timer0_va_base, timer_irq, "timer0"); } /* diff --git a/arch/arm/mach-realview/include/mach/barriers.h b/arch/arm/mach-realview/include/mach/barriers.h index 0c5d749d7b5f..9a732195aa1c 100644 --- a/arch/arm/mach-realview/include/mach/barriers.h +++ b/arch/arm/mach-realview/include/mach/barriers.h @@ -4,5 +4,5 @@ * operation to deadlock the system. */ #define mb() dsb() -#define rmb() dmb() +#define rmb() dsb() #define wmb() mb() diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h index e05fc2c4c080..1759fa673eea 100644 --- a/arch/arm/mach-realview/include/mach/memory.h +++ b/arch/arm/mach-realview/include/mach/memory.h @@ -29,13 +29,8 @@ #define PLAT_PHYS_OFFSET UL(0x00000000) #endif -#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) -extern void realview_adjust_zones(unsigned long *size, unsigned long *hole); -#define arch_adjust_zones(size, hole) \ - realview_adjust_zones(size, hole) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M) +#ifdef CONFIG_ZONE_DMA +#define ARM_DMA_ZONE_SIZE SZ_256M #endif #ifdef CONFIG_SPARSEMEM diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h deleted file mode 100644 index c8221b38ee7c..000000000000 --- a/arch/arm/mach-realview/include/mach/smp.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef ASMARM_ARCH_SMP_H -#define ASMARM_ARCH_SMP_H - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index 23919229e12d..963bf0d8119a 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -14,6 +14,7 @@ #include <linux/io.h> #include <mach/hardware.h> +#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <asm/smp_scu.h> #include <asm/unified.h> @@ -61,6 +62,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 5e2f35332056..2854129f8cc7 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c @@ -23,38 +23,12 @@ #include <linux/module.h> #include <linux/interrupt.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <plat/cpu.h> #include <plat/pm.h> -static int s3c2410_irq_add(struct sys_device *sysdev) -{ - return 0; -} - -static struct sysdev_driver s3c2410_irq_driver = { - .add = s3c2410_irq_add, +struct syscore_ops s3c24xx_irq_syscore_ops = { .suspend = s3c24xx_irq_suspend, .resume = s3c24xx_irq_resume, }; - -static int __init s3c2410_irq_init(void) -{ - return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver); -} - -arch_initcall(s3c2410_irq_init); - -static struct sysdev_driver s3c2410a_irq_driver = { - .add = s3c2410_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, -}; - -static int __init s3c2410a_irq_init(void) -{ - return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_irq_driver); -} - -arch_initcall(s3c2410a_irq_init); diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 2970ea9f7c2b..1e2d536adda9 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -17,7 +17,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/gpio.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/dm9000.h> @@ -214,17 +214,16 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { /* NAND Flash on BAST board */ #ifdef CONFIG_PM -static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) +static int bast_pm_suspend(void) { /* ensure that an nRESET is not generated on resume. */ gpio_direction_output(S3C2410_GPA(21), 1); return 0; } -static int bast_pm_resume(struct sys_device *sd) +static void bast_pm_resume(void) { s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); - return 0; } #else @@ -232,16 +231,11 @@ static int bast_pm_resume(struct sys_device *sd) #define bast_pm_resume NULL #endif -static struct sysdev_class bast_pm_sysclass = { - .name = "mach-bast", +static struct syscore_ops bast_pm_syscore_ops = { .suspend = bast_pm_suspend, .resume = bast_pm_resume, }; -static struct sys_device bast_pm_sysdev = { - .cls = &bast_pm_sysclass, -}; - static int smartmedia_map[] = { 0 }; static int chip0_map[] = { 1 }; static int chip1_map[] = { 2 }; @@ -642,8 +636,7 @@ static void __init bast_map_io(void) static void __init bast_init(void) { - sysdev_class_register(&bast_pm_sysclass); - sysdev_register(&bast_pm_sysdev); + register_syscore_ops(&bast_pm_syscore_ops); s3c_i2c0_set_platdata(&bast_i2c_info); s3c_nand_set_platdata(&bast_nand_info); diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c index 598d130633dc..ad9f750f1e55 100644 --- a/arch/arm/mach-s3c2410/nor-simtec.c +++ b/arch/arm/mach-s3c2410/nor-simtec.c @@ -32,7 +32,7 @@ #include "nor-simtec.h" -static void simtec_nor_vpp(struct map_info *map, int vpp) +static void simtec_nor_vpp(struct platform_device *pdev, int vpp) { unsigned int val; unsigned long flags; diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 725636fc4dc3..4728f9aa7df1 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -25,6 +25,7 @@ #include <linux/errno.h> #include <linux/time.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/gpio.h> #include <linux/io.h> @@ -92,7 +93,7 @@ static void s3c2410_pm_prepare(void) } } -static int s3c2410_pm_resume(struct sys_device *dev) +static void s3c2410_pm_resume(void) { unsigned long tmp; @@ -104,10 +105,12 @@ static int s3c2410_pm_resume(struct sys_device *dev) if ( machine_is_aml_m5900() ) s3c2410_gpio_setpin(S3C2410_GPF(2), 0); - - return 0; } +struct syscore_ops s3c2410_pm_syscore_ops = { + .resume = s3c2410_pm_resume, +}; + static int s3c2410_pm_add(struct sys_device *dev) { pm_cpu_prep = s3c2410_pm_prepare; @@ -119,7 +122,6 @@ static int s3c2410_pm_add(struct sys_device *dev) #if defined(CONFIG_CPU_S3C2410) static struct sysdev_driver s3c2410_pm_driver = { .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, }; /* register ourselves */ @@ -133,7 +135,6 @@ arch_initcall(s3c2410_pm_drvinit); static struct sysdev_driver s3c2410a_pm_driver = { .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, }; static int __init s3c2410a_pm_drvinit(void) @@ -147,7 +148,6 @@ arch_initcall(s3c2410a_pm_drvinit); #if defined(CONFIG_CPU_S3C2440) static struct sysdev_driver s3c2440_pm_driver = { .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, }; static int __init s3c2440_pm_drvinit(void) @@ -161,7 +161,6 @@ arch_initcall(s3c2440_pm_drvinit); #if defined(CONFIG_CPU_S3C2442) static struct sysdev_driver s3c2442_pm_driver = { .add = s3c2410_pm_add, - .resume = s3c2410_pm_resume, }; static int __init s3c2442_pm_drvinit(void) diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index adc90a3c5890..f1d3bd8f6f17 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -19,6 +19,7 @@ #include <linux/gpio.h> #include <linux/clk.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -40,6 +41,7 @@ #include <plat/devs.h> #include <plat/clock.h> #include <plat/pll.h> +#include <plat/pm.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> @@ -168,6 +170,9 @@ int __init s3c2410_init(void) { printk("S3C2410: Initialising architecture\n"); + register_syscore_ops(&s3c2410_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + return sysdev_register(&s3c2410_sysdev); } diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index f3355d2ec634..1a1aa220972b 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c @@ -202,8 +202,6 @@ static int s3c2412_irq_add(struct sys_device *sysdev) static struct sysdev_driver s3c2412_irq_driver = { .add = s3c2412_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, }; static int s3c2412_irq_init(void) diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index 923e01bdf017..85dcaeb9e62f 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c @@ -17,7 +17,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/gpio.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/i2c.h> @@ -486,7 +486,7 @@ static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = { /* Jive power management device */ #ifdef CONFIG_PM -static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) +static int jive_pm_suspend(void) { /* Write the magic value u-boot uses to check for resume into * the INFORM0 register, and ensure INFORM1 is set to the @@ -498,10 +498,9 @@ static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) return 0; } -static int jive_pm_resume(struct sys_device *sd) +static void jive_pm_resume(void) { __raw_writel(0x0, S3C2412_INFORM0); - return 0; } #else @@ -509,16 +508,11 @@ static int jive_pm_resume(struct sys_device *sd) #define jive_pm_resume NULL #endif -static struct sysdev_class jive_pm_sysclass = { - .name = "jive-pm", +static struct syscore_ops jive_pm_syscore_ops = { .suspend = jive_pm_suspend, .resume = jive_pm_resume, }; -static struct sys_device jive_pm_sysdev = { - .cls = &jive_pm_sysclass, -}; - static void __init jive_map_io(void) { s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); @@ -536,10 +530,9 @@ static void jive_power_off(void) static void __init jive_machine_init(void) { - /* register system devices for managing low level suspend */ + /* register system core operations for managing low level suspend */ - sysdev_class_register(&jive_pm_sysclass); - sysdev_register(&jive_pm_sysdev); + register_syscore_ops(&jive_pm_syscore_ops); /* write our sleep configurations for the IO. Pull down all unused * IO, ensure that we have turned off all peripherals we do not diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c index a7417c479ffe..752b13a7b3db 100644 --- a/arch/arm/mach-s3c2412/pm.c +++ b/arch/arm/mach-s3c2412/pm.c @@ -17,6 +17,7 @@ #include <linux/timer.h> #include <linux/init.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -86,13 +87,24 @@ static struct sleep_save s3c2412_sleep[] = { SAVE_ITEM(S3C2413_GPJSLPCON), }; -static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state) +static struct sysdev_driver s3c2412_pm_driver = { + .add = s3c2412_pm_add, +}; + +static __init int s3c2412_pm_init(void) +{ + return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver); +} + +arch_initcall(s3c2412_pm_init); + +static int s3c2412_pm_suspend(void) { s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); return 0; } -static int s3c2412_pm_resume(struct sys_device *dev) +static void s3c2412_pm_resume(void) { unsigned long tmp; @@ -102,18 +114,9 @@ static int s3c2412_pm_resume(struct sys_device *dev) __raw_writel(tmp, S3C2412_PWRCFG); s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); - return 0; } -static struct sysdev_driver s3c2412_pm_driver = { - .add = s3c2412_pm_add, +struct syscore_ops s3c2412_pm_syscore_ops = { .suspend = s3c2412_pm_suspend, .resume = s3c2412_pm_resume, }; - -static __init int s3c2412_pm_init(void) -{ - return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver); -} - -arch_initcall(s3c2412_pm_init); diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 4c6df51ddf33..ef0958d3e5c6 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -19,6 +19,7 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/io.h> @@ -244,5 +245,8 @@ int __init s3c2412_init(void) { printk("S3C2412: Initialising architecture\n"); + register_syscore_ops(&s3c2412_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + return sysdev_register(&s3c2412_sysdev); } diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c index 77b38f2381c1..28ad20d42445 100644 --- a/arch/arm/mach-s3c2416/irq.c +++ b/arch/arm/mach-s3c2416/irq.c @@ -236,8 +236,6 @@ static int __init s3c2416_irq_add(struct sys_device *sysdev) static struct sysdev_driver s3c2416_irq_driver = { .add = s3c2416_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, }; static int __init s3c2416_irq_init(void) diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c index 4a04205b04d5..41db2b21e213 100644 --- a/arch/arm/mach-s3c2416/pm.c +++ b/arch/arm/mach-s3c2416/pm.c @@ -11,6 +11,7 @@ */ #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <asm/cacheflush.h> @@ -55,30 +56,26 @@ static int s3c2416_pm_add(struct sys_device *sysdev) return 0; } -static int s3c2416_pm_suspend(struct sys_device *dev, pm_message_t state) +static struct sysdev_driver s3c2416_pm_driver = { + .add = s3c2416_pm_add, +}; + +static __init int s3c2416_pm_init(void) { - return 0; + return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver); } -static int s3c2416_pm_resume(struct sys_device *dev) +arch_initcall(s3c2416_pm_init); + + +static void s3c2416_pm_resume(void) { /* unset the return-from-sleep amd inform flags */ __raw_writel(0x0, S3C2443_PWRMODE); __raw_writel(0x0, S3C2412_INFORM0); __raw_writel(0x0, S3C2412_INFORM1); - - return 0; } -static struct sysdev_driver s3c2416_pm_driver = { - .add = s3c2416_pm_add, - .suspend = s3c2416_pm_suspend, +struct syscore_ops s3c2416_pm_syscore_ops = { .resume = s3c2416_pm_resume, }; - -static __init int s3c2416_pm_init(void) -{ - return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver); -} - -arch_initcall(s3c2416_pm_init); diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index ba7fd8737434..494ce913dc95 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -32,6 +32,7 @@ #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/clk.h> #include <linux/io.h> @@ -54,6 +55,7 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/sdhci.h> +#include <plat/pm.h> #include <plat/iic-core.h> #include <plat/fb-core.h> @@ -95,6 +97,9 @@ int __init s3c2416_init(void) s3c_fb_setname("s3c2443-fb"); + register_syscore_ops(&s3c2416_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + return sysdev_register(&s3c2416_sysdev); } diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 14dc67897757..d88536393310 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -17,7 +17,7 @@ #include <linux/init.h> #include <linux/gpio.h> #include <linux/device.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/serial_core.h> #include <linux/clk.h> #include <linux/i2c.h> @@ -284,7 +284,7 @@ static struct platform_device osiris_pcmcia = { #ifdef CONFIG_PM static unsigned char pm_osiris_ctrl0; -static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state) +static int osiris_pm_suspend(void) { unsigned int tmp; @@ -304,7 +304,7 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state) return 0; } -static int osiris_pm_resume(struct sys_device *sd) +static void osiris_pm_resume(void) { if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8) __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1); @@ -312,8 +312,6 @@ static int osiris_pm_resume(struct sys_device *sd) __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0); s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); - - return 0; } #else @@ -321,16 +319,11 @@ static int osiris_pm_resume(struct sys_device *sd) #define osiris_pm_resume NULL #endif -static struct sysdev_class osiris_pm_sysclass = { - .name = "mach-osiris", +static struct syscore_ops osiris_pm_syscore_ops = { .suspend = osiris_pm_suspend, .resume = osiris_pm_resume, }; -static struct sys_device osiris_pm_sysdev = { - .cls = &osiris_pm_sysclass, -}; - /* Link for DVS driver to TPS65011 */ static void osiris_tps_release(struct device *dev) @@ -439,8 +432,7 @@ static void __init osiris_map_io(void) static void __init osiris_init(void) { - sysdev_class_register(&osiris_pm_sysclass); - sysdev_register(&osiris_pm_sysdev); + register_syscore_ops(&osiris_pm_syscore_ops); s3c_i2c0_set_platdata(NULL); s3c_nand_set_platdata(&osiris_nand_info); diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c index f7663f731ea0..ce99ff72838d 100644 --- a/arch/arm/mach-s3c2440/s3c2440.c +++ b/arch/arm/mach-s3c2440/s3c2440.c @@ -19,6 +19,7 @@ #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/gpio.h> #include <linux/clk.h> #include <linux/io.h> @@ -33,6 +34,7 @@ #include <plat/devs.h> #include <plat/cpu.h> #include <plat/s3c244x.h> +#include <plat/pm.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> @@ -51,6 +53,12 @@ int __init s3c2440_init(void) s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT; s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT; + /* register suspend/resume handlers */ + + register_syscore_ops(&s3c2410_pm_syscore_ops); + register_syscore_ops(&s3c244x_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + /* register our system device for everything else */ return sysdev_register(&s3c2440_sysdev); diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c index ecf813546554..6224bad4d604 100644 --- a/arch/arm/mach-s3c2440/s3c2442.c +++ b/arch/arm/mach-s3c2440/s3c2442.c @@ -29,6 +29,7 @@ #include <linux/err.h> #include <linux/device.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/mutex.h> @@ -45,6 +46,7 @@ #include <plat/clock.h> #include <plat/cpu.h> #include <plat/s3c244x.h> +#include <plat/pm.h> #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> @@ -167,6 +169,10 @@ int __init s3c2442_init(void) { printk("S3C2442: Initialising architecture\n"); + register_syscore_ops(&s3c2410_pm_syscore_ops); + register_syscore_ops(&s3c244x_pm_syscore_ops); + register_syscore_ops(&s3c24xx_irq_syscore_ops); + return sysdev_register(&s3c2442_sysdev); } diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c index de07c2feaa32..c63e8f26d901 100644 --- a/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/arch/arm/mach-s3c2440/s3c244x-irq.c @@ -116,8 +116,6 @@ static int s3c244x_irq_add(struct sys_device *sysdev) static struct sysdev_driver s3c2440_irq_driver = { .add = s3c244x_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, }; static int s3c2440_irq_init(void) @@ -129,8 +127,6 @@ arch_initcall(s3c2440_irq_init); static struct sysdev_driver s3c2442_irq_driver = { .add = s3c244x_irq_add, - .suspend = s3c24xx_irq_suspend, - .resume = s3c24xx_irq_resume, }; diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c index 90c1707b9c95..7e8a23d2098a 100644 --- a/arch/arm/mach-s3c2440/s3c244x.c +++ b/arch/arm/mach-s3c2440/s3c244x.c @@ -19,6 +19,7 @@ #include <linux/serial_core.h> #include <linux/platform_device.h> #include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/clk.h> #include <linux/io.h> @@ -134,45 +135,14 @@ void __init s3c244x_init_clocks(int xtal) s3c2410_baseclk_add(); } -#ifdef CONFIG_PM - -static struct sleep_save s3c244x_sleep[] = { - SAVE_ITEM(S3C2440_DSC0), - SAVE_ITEM(S3C2440_DSC1), - SAVE_ITEM(S3C2440_GPJDAT), - SAVE_ITEM(S3C2440_GPJCON), - SAVE_ITEM(S3C2440_GPJUP) -}; - -static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) -{ - s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); - return 0; -} - -static int s3c244x_resume(struct sys_device *dev) -{ - s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); - return 0; -} - -#else -#define s3c244x_suspend NULL -#define s3c244x_resume NULL -#endif - /* Since the S3C2442 and S3C2440 share items, put both sysclasses here */ struct sysdev_class s3c2440_sysclass = { .name = "s3c2440-core", - .suspend = s3c244x_suspend, - .resume = s3c244x_resume }; struct sysdev_class s3c2442_sysclass = { .name = "s3c2442-core", - .suspend = s3c244x_suspend, - .resume = s3c244x_resume }; /* need to register class before we actually register the device, and @@ -194,3 +164,33 @@ static int __init s3c2442_core_init(void) } core_initcall(s3c2442_core_init); + + +#ifdef CONFIG_PM +static struct sleep_save s3c244x_sleep[] = { + SAVE_ITEM(S3C2440_DSC0), + SAVE_ITEM(S3C2440_DSC1), + SAVE_ITEM(S3C2440_GPJDAT), + SAVE_ITEM(S3C2440_GPJCON), + SAVE_ITEM(S3C2440_GPJUP) +}; + +static int s3c244x_suspend(void) +{ + s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); + return 0; +} + +static void s3c244x_resume(void) +{ + s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); +} +#else +#define s3c244x_suspend NULL +#define s3c244x_resume NULL +#endif + +struct syscore_ops s3c244x_pm_syscore_ops = { + .suspend = s3c244x_suspend, + .resume = s3c244x_resume, +}; diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c index da1bec64b9da..8bec61e242c7 100644 --- a/arch/arm/mach-s3c64xx/irq-pm.c +++ b/arch/arm/mach-s3c64xx/irq-pm.c @@ -13,7 +13,7 @@ */ #include <linux/kernel.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/interrupt.h> #include <linux/serial_core.h> #include <linux/irq.h> @@ -54,7 +54,7 @@ static struct irq_grp_save { static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; -static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state) +static int s3c64xx_irq_pm_suspend(void) { struct irq_grp_save *grp = eint_grp_save; int i; @@ -75,7 +75,7 @@ static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int s3c64xx_irq_pm_resume(struct sys_device *dev) +static void s3c64xx_irq_pm_resume(void) { struct irq_grp_save *grp = eint_grp_save; int i; @@ -94,18 +94,18 @@ static int s3c64xx_irq_pm_resume(struct sys_device *dev) } S3C_PMDBG("%s: IRQ configuration restored\n", __func__); - return 0; } -static struct sysdev_driver s3c64xx_irq_driver = { +struct syscore_ops s3c64xx_irq_syscore_ops = { .suspend = s3c64xx_irq_pm_suspend, .resume = s3c64xx_irq_pm_resume, }; -static int __init s3c64xx_irq_pm_init(void) +static __init int s3c64xx_syscore_init(void) { - return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver); -} + register_syscore_ops(&s3c64xx_irq_syscore_ops); -arch_initcall(s3c64xx_irq_pm_init); + return 0; +} +core_initcall(s3c64xx_syscore_init); diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index 549d7924fd4c..24febae3d4c0 100644 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/suspend.h> +#include <linux/syscore_ops.h> #include <linux/io.h> #include <plat/cpu.h> @@ -140,7 +141,17 @@ static int s5pv210_pm_add(struct sys_device *sysdev) return 0; } -static int s5pv210_pm_resume(struct sys_device *dev) +static struct sysdev_driver s5pv210_pm_driver = { + .add = s5pv210_pm_add, +}; + +static __init int s5pv210_pm_drvinit(void) +{ + return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver); +} +arch_initcall(s5pv210_pm_drvinit); + +static void s5pv210_pm_resume(void) { u32 tmp; @@ -150,17 +161,15 @@ static int s5pv210_pm_resume(struct sys_device *dev) __raw_writel(tmp , S5P_OTHERS); s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); - - return 0; } -static struct sysdev_driver s5pv210_pm_driver = { - .add = s5pv210_pm_add, +static struct syscore_ops s5pv210_pm_syscore_ops = { .resume = s5pv210_pm_resume, }; -static __init int s5pv210_pm_drvinit(void) +static __init int s5pv210_pm_syscore_init(void) { - return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver); + register_syscore_ops(&s5pv210_pm_syscore_ops); + return 0; } -arch_initcall(s5pv210_pm_drvinit); +arch_initcall(s5pv210_pm_syscore_init); diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index a44da6a2916c..cff31ee246b7 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -14,18 +14,8 @@ */ #define PLAT_PHYS_OFFSET UL(0xc0000000) -#ifndef __ASSEMBLY__ - #ifdef CONFIG_SA1111 -void sa1111_adjust_zones(unsigned long *size, unsigned long *holes); - -#define arch_adjust_zones(size, holes) \ - sa1111_adjust_zones(size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M) - -#endif +#define ARM_DMA_ZONE_SIZE SZ_1M #endif /* diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 423ddb3d65e9..dfbf824a69fa 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -14,7 +14,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/ioport.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <mach/hardware.h> #include <asm/mach/irq.h> @@ -234,7 +234,7 @@ static struct sa1100irq_state { unsigned int iccr; } sa1100irq_state; -static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state) +static int sa1100irq_suspend(void) { struct sa1100irq_state *st = &sa1100irq_state; @@ -264,7 +264,7 @@ static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int sa1100irq_resume(struct sys_device *dev) +static void sa1100irq_resume(void) { struct sa1100irq_state *st = &sa1100irq_state; @@ -277,24 +277,17 @@ static int sa1100irq_resume(struct sys_device *dev) ICMR = st->icmr; } - return 0; } -static struct sysdev_class sa1100irq_sysclass = { - .name = "sa11x0-irq", +static struct syscore_ops sa1100irq_syscore_ops = { .suspend = sa1100irq_suspend, .resume = sa1100irq_resume, }; -static struct sys_device sa1100irq_device = { - .id = 0, - .cls = &sa1100irq_sysclass, -}; - static int __init sa1100irq_init_devicefs(void) { - sysdev_class_register(&sa1100irq_sysclass); - return sysdev_register(&sa1100irq_device); + register_syscore_ops(&sa1100irq_syscore_ops); + return 0; } device_initcall(sa1100irq_init_devicefs); diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index ae4f3d80416f..fa6602491d54 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -92,25 +92,11 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) static struct clock_event_device ckevt_sa1100_osmr0 = { .name = "osmr0", .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, .rating = 200, .set_next_event = sa1100_osmr0_set_next_event, .set_mode = sa1100_osmr0_set_mode, }; -static cycle_t sa1100_read_oscr(struct clocksource *s) -{ - return OSCR; -} - -static struct clocksource cksrc_sa1100_oscr = { - .name = "oscr", - .rating = 200, - .read = sa1100_read_oscr, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static struct irqaction sa1100_timer_irq = { .name = "ost0", .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, @@ -120,14 +106,13 @@ static struct irqaction sa1100_timer_irq = { static void __init sa1100_timer_init(void) { - OIER = 0; /* disable any timer interrupts */ - OSSR = 0xf; /* clear status on all timers */ + OIER = 0; + OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32, 3686400, SC_MULT, SC_SHIFT); - ckevt_sa1100_osmr0.mult = - div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift); + clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4); ckevt_sa1100_osmr0.max_delta_ns = clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0); ckevt_sa1100_osmr0.min_delta_ns = @@ -136,7 +121,8 @@ static void __init sa1100_timer_init(void) setup_irq(IRQ_OST0, &sa1100_timer_irq); - clocksource_register_hz(&cksrc_sa1100_oscr, CLOCK_TICK_RATE); + clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, + clocksource_mmio_readl_up); clockevents_register_device(&ckevt_sa1100_osmr0); } diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index 9afb17000008..4c0831f83b0c 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h @@ -17,25 +17,7 @@ */ #define PLAT_PHYS_OFFSET UL(0x08000000) -#ifndef __ASSEMBLY__ - -static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size) -{ - /* Only the first 4 MB (=1024 Pages) are usable for DMA */ - /* See dev / -> .properties in OpenFirmware. */ - zone_size[1] = zone_size[0] - 1024; - zone_size[0] = 1024; - zhole_size[1] = zhole_size[0]; - zhole_size[0] = 0; -} - -#define arch_adjust_zones(size, holes) \ - __arch_adjust_zones(size, holes) - -#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1) -#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M) - -#endif +#define ARM_DMA_ZONE_SIZE SZ_4M /* * Cache flushing area diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h deleted file mode 100644 index 50db94e927ad..000000000000 --- a/arch/arm/mach-shmobile/include/mach/smp.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __MACH_SMP_H -#define __MACH_SMP_H - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ -#if defined(CONFIG_ARM_GIC) - gic_raise_softirq(mask, ipi); -#endif -} - -#endif diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index 65e879bab4dc..f3888feb1c68 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c @@ -16,6 +16,7 @@ #include <linux/device.h> #include <linux/smp.h> #include <linux/io.h> +#include <asm/hardware/gic.h> #include <asm/localtimer.h> #include <asm/mach-types.h> #include <mach/common.h> @@ -57,6 +58,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-shmobile/pm_runtime.c b/arch/arm/mach-shmobile/pm_runtime.c index 94912d3944d3..2d1b67a59e4a 100644 --- a/arch/arm/mach-shmobile/pm_runtime.c +++ b/arch/arm/mach-shmobile/pm_runtime.c @@ -18,152 +18,41 @@ #include <linux/clk.h> #include <linux/sh_clk.h> #include <linux/bitmap.h> +#include <linux/slab.h> #ifdef CONFIG_PM_RUNTIME -#define BIT_ONCE 0 -#define BIT_ACTIVE 1 -#define BIT_CLK_ENABLED 2 -struct pm_runtime_data { - unsigned long flags; - struct clk *clk; -}; - -static void __devres_release(struct device *dev, void *res) -{ - struct pm_runtime_data *prd = res; - - dev_dbg(dev, "__devres_release()\n"); - - if (test_bit(BIT_CLK_ENABLED, &prd->flags)) - clk_disable(prd->clk); - - if (test_bit(BIT_ACTIVE, &prd->flags)) - clk_put(prd->clk); -} - -static struct pm_runtime_data *__to_prd(struct device *dev) -{ - return devres_find(dev, __devres_release, NULL, NULL); -} - -static void platform_pm_runtime_init(struct device *dev, - struct pm_runtime_data *prd) -{ - if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags)) { - prd->clk = clk_get(dev, NULL); - if (!IS_ERR(prd->clk)) { - set_bit(BIT_ACTIVE, &prd->flags); - dev_info(dev, "clocks managed by runtime pm\n"); - } - } -} - -static void platform_pm_runtime_bug(struct device *dev, - struct pm_runtime_data *prd) -{ - if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags)) - dev_err(dev, "runtime pm suspend before resume\n"); -} - -int platform_pm_runtime_suspend(struct device *dev) -{ - struct pm_runtime_data *prd = __to_prd(dev); - - dev_dbg(dev, "platform_pm_runtime_suspend()\n"); - - platform_pm_runtime_bug(dev, prd); - - if (prd && test_bit(BIT_ACTIVE, &prd->flags)) { - clk_disable(prd->clk); - clear_bit(BIT_CLK_ENABLED, &prd->flags); - } - - return 0; -} - -int platform_pm_runtime_resume(struct device *dev) -{ - struct pm_runtime_data *prd = __to_prd(dev); - - dev_dbg(dev, "platform_pm_runtime_resume()\n"); - - platform_pm_runtime_init(dev, prd); - - if (prd && test_bit(BIT_ACTIVE, &prd->flags)) { - clk_enable(prd->clk); - set_bit(BIT_CLK_ENABLED, &prd->flags); - } - - return 0; -} - -int platform_pm_runtime_idle(struct device *dev) +static int default_platform_runtime_idle(struct device *dev) { /* suspend synchronously to disable clocks immediately */ return pm_runtime_suspend(dev); } -static int platform_bus_notify(struct notifier_block *nb, - unsigned long action, void *data) -{ - struct device *dev = data; - struct pm_runtime_data *prd; - - dev_dbg(dev, "platform_bus_notify() %ld !\n", action); - - if (action == BUS_NOTIFY_BIND_DRIVER) { - prd = devres_alloc(__devres_release, sizeof(*prd), GFP_KERNEL); - if (prd) - devres_add(dev, prd); - else - dev_err(dev, "unable to alloc memory for runtime pm\n"); - } - - return 0; -} - -#else /* CONFIG_PM_RUNTIME */ - -static int platform_bus_notify(struct notifier_block *nb, - unsigned long action, void *data) -{ - struct device *dev = data; - struct clk *clk; +static struct dev_power_domain default_power_domain = { + .ops = { + .runtime_suspend = pm_runtime_clk_suspend, + .runtime_resume = pm_runtime_clk_resume, + .runtime_idle = default_platform_runtime_idle, + USE_PLATFORM_PM_SLEEP_OPS + }, +}; - dev_dbg(dev, "platform_bus_notify() %ld !\n", action); +#define DEFAULT_PWR_DOMAIN_PTR (&default_power_domain) - switch (action) { - case BUS_NOTIFY_BIND_DRIVER: - clk = clk_get(dev, NULL); - if (!IS_ERR(clk)) { - clk_enable(clk); - clk_put(clk); - dev_info(dev, "runtime pm disabled, clock forced on\n"); - } - break; - case BUS_NOTIFY_UNBOUND_DRIVER: - clk = clk_get(dev, NULL); - if (!IS_ERR(clk)) { - clk_disable(clk); - clk_put(clk); - dev_info(dev, "runtime pm disabled, clock forced off\n"); - } - break; - } +#else - return 0; -} +#define DEFAULT_PWR_DOMAIN_PTR NULL #endif /* CONFIG_PM_RUNTIME */ -static struct notifier_block platform_bus_notifier = { - .notifier_call = platform_bus_notify +static struct pm_clk_notifier_block platform_bus_notifier = { + .pwr_domain = DEFAULT_PWR_DOMAIN_PTR, + .con_ids = { NULL, }, }; static int __init sh_pm_runtime_init(void) { - bus_register_notifier(&platform_bus_type, &platform_bus_notifier); + pm_runtime_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); return 0; } core_initcall(sh_pm_runtime_init); diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig index 20d1317cc486..2cee6b0de371 100644 --- a/arch/arm/mach-spear3xx/Kconfig +++ b/arch/arm/mach-spear3xx/Kconfig @@ -4,9 +4,26 @@ if ARCH_SPEAR3XX -choice - prompt "SPEAr3XX Family" - default MACH_SPEAR300 +menu "SPEAr3xx Implementations" +config BOARD_SPEAR300_EVB + bool "SPEAr300 Evaluation Board" + select MACH_SPEAR300 + help + Supports ST SPEAr300 Evaluation Board + +config BOARD_SPEAR310_EVB + bool "SPEAr310 Evaluation Board" + select MACH_SPEAR310 + help + Supports ST SPEAr310 Evaluation Board + +config BOARD_SPEAR320_EVB + bool "SPEAr320 Evaluation Board" + select MACH_SPEAR320 + help + Supports ST SPEAr320 Evaluation Board + +endmenu config MACH_SPEAR300 bool "SPEAr300" @@ -23,11 +40,4 @@ config MACH_SPEAR320 help Supports ST SPEAr320 Machine -endchoice - -# Adding SPEAr3XX machine specific configuration files -source "arch/arm/mach-spear3xx/Kconfig300" -source "arch/arm/mach-spear3xx/Kconfig310" -source "arch/arm/mach-spear3xx/Kconfig320" - endif #ARCH_SPEAR3XX diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300 deleted file mode 100644 index c519a05b4ab4..000000000000 --- a/arch/arm/mach-spear3xx/Kconfig300 +++ /dev/null @@ -1,17 +0,0 @@ -# -# SPEAr300 machine configuration file -# - -if MACH_SPEAR300 - -choice - prompt "SPEAr300 Boards" - default BOARD_SPEAR300_EVB - -config BOARD_SPEAR300_EVB - bool "SPEAr300 Evaluation Board" - help - Supports ST SPEAr300 Evaluation Board -endchoice - -endif #MACH_SPEAR300 diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310 deleted file mode 100644 index 60e7442d75bd..000000000000 --- a/arch/arm/mach-spear3xx/Kconfig310 +++ /dev/null @@ -1,17 +0,0 @@ -# -# SPEAr310 machine configuration file -# - -if MACH_SPEAR310 - -choice - prompt "SPEAr310 Boards" - default BOARD_SPEAR310_EVB - -config BOARD_SPEAR310_EVB - bool "SPEAr310 Evaluation Board" - help - Supports ST SPEAr310 Evaluation Board -endchoice - -endif #MACH_SPEAR310 diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320 deleted file mode 100644 index 1c1d438399b8..000000000000 --- a/arch/arm/mach-spear3xx/Kconfig320 +++ /dev/null @@ -1,17 +0,0 @@ -# -# SPEAr320 machine configuration file -# - -if MACH_SPEAR320 - -choice - prompt "SPEAr320 Boards" - default BOARD_SPEAR320_EVB - -config BOARD_SPEAR320_EVB - bool "SPEAr320 Evaluation Board" - help - Supports ST SPEAr320 Evaluation Board -endchoice - -endif #MACH_SPEAR320 diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c index 98bc7edc95a6..f67860cd649f 100644 --- a/arch/arm/mach-spear3xx/clock.c +++ b/arch/arm/mach-spear3xx/clock.c @@ -13,6 +13,7 @@ #include <linux/init.h> #include <linux/kernel.h> +#include <asm/mach-types.h> #include <plat/clock.h> #include <mach/misc_regs.h> @@ -688,56 +689,71 @@ static struct clk_lookup spear_clk_lookups[] = { { .dev_id = "adc", .clk = &adc_clk}, { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, { .dev_id = "gpio", .clk = &gpio_clk}, -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) - { .dev_id = "physmap-flash", .clk = &emi_clk}, -#endif -#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \ - defined(CONFIG_MACH_SPEAR320) - { .con_id = "fsmc", .clk = &fsmc_clk}, -#endif - -/* common clocks to spear310 and spear320 */ -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) - { .dev_id = "uart1", .clk = &uart1_clk}, - { .dev_id = "uart2", .clk = &uart2_clk}, -#endif - - /* common clock to spear300 and spear320 */ -#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320) - { .dev_id = "clcd", .clk = &clcd_clk}, - { .dev_id = "sdhci", .clk = &sdhci_clk}, -#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */ +}; - /* spear300 machine specific clock structures */ +/* array of all spear 300 clock lookups */ #ifdef CONFIG_MACH_SPEAR300 +static struct clk_lookup spear300_clk_lookups[] = { + { .dev_id = "clcd", .clk = &clcd_clk}, + { .con_id = "fsmc", .clk = &fsmc_clk}, { .dev_id = "gpio1", .clk = &gpio1_clk}, { .dev_id = "keyboard", .clk = &kbd_clk}, + { .dev_id = "sdhci", .clk = &sdhci_clk}, +}; #endif - /* spear310 machine specific clock structures */ +/* array of all spear 310 clock lookups */ #ifdef CONFIG_MACH_SPEAR310 +static struct clk_lookup spear310_clk_lookups[] = { + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .con_id = "emi", .clk = &emi_clk}, + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "uart2", .clk = &uart2_clk}, { .dev_id = "uart3", .clk = &uart3_clk}, { .dev_id = "uart4", .clk = &uart4_clk}, { .dev_id = "uart5", .clk = &uart5_clk}, - +}; #endif - /* spear320 machine specific clock structures */ + +/* array of all spear 320 clock lookups */ #ifdef CONFIG_MACH_SPEAR320 +static struct clk_lookup spear320_clk_lookups[] = { + { .dev_id = "clcd", .clk = &clcd_clk}, + { .con_id = "fsmc", .clk = &fsmc_clk}, + { .dev_id = "i2c_designware.1", .clk = &i2c1_clk}, + { .con_id = "emi", .clk = &emi_clk}, + { .dev_id = "pwm", .clk = &pwm_clk}, + { .dev_id = "sdhci", .clk = &sdhci_clk}, { .dev_id = "c_can_platform.0", .clk = &can0_clk}, { .dev_id = "c_can_platform.1", .clk = &can1_clk}, - { .dev_id = "i2c_designware.1", .clk = &i2c1_clk}, { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, - { .dev_id = "pwm", .clk = &pwm_clk}, -#endif + { .dev_id = "uart1", .clk = &uart1_clk}, + { .dev_id = "uart2", .clk = &uart2_clk}, }; +#endif -void __init clk_init(void) +void __init spear3xx_clk_init(void) { - int i; + int i, cnt; + struct clk_lookup *lookups; + + if (machine_is_spear300()) { + cnt = ARRAY_SIZE(spear300_clk_lookups); + lookups = spear300_clk_lookups; + } else if (machine_is_spear310()) { + cnt = ARRAY_SIZE(spear310_clk_lookups); + lookups = spear310_clk_lookups; + } else { + cnt = ARRAY_SIZE(spear320_clk_lookups); + lookups = spear320_clk_lookups; + } for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) clk_register(&spear_clk_lookups[i]); - recalc_root_clocks(); + for (i = 0; i < cnt; i++) + clk_register(&lookups[i]); + + clk_init(); } diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index 8e30636909ef..b8f31c3935f7 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -27,16 +27,16 @@ * Following GPT channels will be used as clock source and clockevent */ #define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE -#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 -#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 +#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1 +#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 /* Add spear3xx family device structure declarations here */ -extern struct amba_device gpio_device; -extern struct amba_device uart_device; +extern struct amba_device spear3xx_gpio_device; +extern struct amba_device spear3xx_uart_device; extern struct sys_timer spear3xx_timer; /* Add spear3xx family function declarations here */ -void __init clk_init(void); +void __init spear3xx_clk_init(void); void __init spear_setup_timer(void); void __init spear3xx_map_io(void); void __init spear3xx_init_irq(void); @@ -60,81 +60,80 @@ void __init spear3xx_init(void); #define PMX_TIMER_1_2_MASK (1 << 0) /* pad mux devices */ -extern struct pmx_dev pmx_firda; -extern struct pmx_dev pmx_i2c; -extern struct pmx_dev pmx_ssp_cs; -extern struct pmx_dev pmx_ssp; -extern struct pmx_dev pmx_mii; -extern struct pmx_dev pmx_gpio_pin0; -extern struct pmx_dev pmx_gpio_pin1; -extern struct pmx_dev pmx_gpio_pin2; -extern struct pmx_dev pmx_gpio_pin3; -extern struct pmx_dev pmx_gpio_pin4; -extern struct pmx_dev pmx_gpio_pin5; -extern struct pmx_dev pmx_uart0_modem; -extern struct pmx_dev pmx_uart0; -extern struct pmx_dev pmx_timer_3_4; -extern struct pmx_dev pmx_timer_1_2; +extern struct pmx_dev spear3xx_pmx_firda; +extern struct pmx_dev spear3xx_pmx_i2c; +extern struct pmx_dev spear3xx_pmx_ssp_cs; +extern struct pmx_dev spear3xx_pmx_ssp; +extern struct pmx_dev spear3xx_pmx_mii; +extern struct pmx_dev spear3xx_pmx_gpio_pin0; +extern struct pmx_dev spear3xx_pmx_gpio_pin1; +extern struct pmx_dev spear3xx_pmx_gpio_pin2; +extern struct pmx_dev spear3xx_pmx_gpio_pin3; +extern struct pmx_dev spear3xx_pmx_gpio_pin4; +extern struct pmx_dev spear3xx_pmx_gpio_pin5; +extern struct pmx_dev spear3xx_pmx_uart0_modem; +extern struct pmx_dev spear3xx_pmx_uart0; +extern struct pmx_dev spear3xx_pmx_timer_3_4; +extern struct pmx_dev spear3xx_pmx_timer_1_2; #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) /* padmux plgpio devices */ -extern struct pmx_dev pmx_plgpio_0_1; -extern struct pmx_dev pmx_plgpio_2_3; -extern struct pmx_dev pmx_plgpio_4_5; -extern struct pmx_dev pmx_plgpio_6_9; -extern struct pmx_dev pmx_plgpio_10_27; -extern struct pmx_dev pmx_plgpio_28; -extern struct pmx_dev pmx_plgpio_29; -extern struct pmx_dev pmx_plgpio_30; -extern struct pmx_dev pmx_plgpio_31; -extern struct pmx_dev pmx_plgpio_32; -extern struct pmx_dev pmx_plgpio_33; -extern struct pmx_dev pmx_plgpio_34_36; -extern struct pmx_dev pmx_plgpio_37_42; -extern struct pmx_dev pmx_plgpio_43_44_47_48; -extern struct pmx_dev pmx_plgpio_45_46_49_50; +extern struct pmx_dev spear3xx_pmx_plgpio_0_1; +extern struct pmx_dev spear3xx_pmx_plgpio_2_3; +extern struct pmx_dev spear3xx_pmx_plgpio_4_5; +extern struct pmx_dev spear3xx_pmx_plgpio_6_9; +extern struct pmx_dev spear3xx_pmx_plgpio_10_27; +extern struct pmx_dev spear3xx_pmx_plgpio_28; +extern struct pmx_dev spear3xx_pmx_plgpio_29; +extern struct pmx_dev spear3xx_pmx_plgpio_30; +extern struct pmx_dev spear3xx_pmx_plgpio_31; +extern struct pmx_dev spear3xx_pmx_plgpio_32; +extern struct pmx_dev spear3xx_pmx_plgpio_33; +extern struct pmx_dev spear3xx_pmx_plgpio_34_36; +extern struct pmx_dev spear3xx_pmx_plgpio_37_42; +extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48; +extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50; #endif -extern struct pmx_driver pmx_driver; - /* spear300 declarations */ #ifdef CONFIG_MACH_SPEAR300 /* Add spear300 machine device structure declarations here */ -extern struct amba_device gpio1_device; +extern struct amba_device spear300_gpio1_device; /* pad mux modes */ -extern struct pmx_mode nand_mode; -extern struct pmx_mode nor_mode; -extern struct pmx_mode photo_frame_mode; -extern struct pmx_mode lend_ip_phone_mode; -extern struct pmx_mode hend_ip_phone_mode; -extern struct pmx_mode lend_wifi_phone_mode; -extern struct pmx_mode hend_wifi_phone_mode; -extern struct pmx_mode ata_pabx_wi2s_mode; -extern struct pmx_mode ata_pabx_i2s_mode; -extern struct pmx_mode caml_lcdw_mode; -extern struct pmx_mode camu_lcd_mode; -extern struct pmx_mode camu_wlcd_mode; -extern struct pmx_mode caml_lcd_mode; +extern struct pmx_mode spear300_nand_mode; +extern struct pmx_mode spear300_nor_mode; +extern struct pmx_mode spear300_photo_frame_mode; +extern struct pmx_mode spear300_lend_ip_phone_mode; +extern struct pmx_mode spear300_hend_ip_phone_mode; +extern struct pmx_mode spear300_lend_wifi_phone_mode; +extern struct pmx_mode spear300_hend_wifi_phone_mode; +extern struct pmx_mode spear300_ata_pabx_wi2s_mode; +extern struct pmx_mode spear300_ata_pabx_i2s_mode; +extern struct pmx_mode spear300_caml_lcdw_mode; +extern struct pmx_mode spear300_camu_lcd_mode; +extern struct pmx_mode spear300_camu_wlcd_mode; +extern struct pmx_mode spear300_caml_lcd_mode; /* pad mux devices */ -extern struct pmx_dev pmx_fsmc_2_chips; -extern struct pmx_dev pmx_fsmc_4_chips; -extern struct pmx_dev pmx_keyboard; -extern struct pmx_dev pmx_clcd; -extern struct pmx_dev pmx_telecom_gpio; -extern struct pmx_dev pmx_telecom_tdm; -extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk; -extern struct pmx_dev pmx_telecom_camera; -extern struct pmx_dev pmx_telecom_dac; -extern struct pmx_dev pmx_telecom_i2s; -extern struct pmx_dev pmx_telecom_boot_pins; -extern struct pmx_dev pmx_telecom_sdhci_4bit; -extern struct pmx_dev pmx_telecom_sdhci_8bit; -extern struct pmx_dev pmx_gpio1; +extern struct pmx_dev spear300_pmx_fsmc_2_chips; +extern struct pmx_dev spear300_pmx_fsmc_4_chips; +extern struct pmx_dev spear300_pmx_keyboard; +extern struct pmx_dev spear300_pmx_clcd; +extern struct pmx_dev spear300_pmx_telecom_gpio; +extern struct pmx_dev spear300_pmx_telecom_tdm; +extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk; +extern struct pmx_dev spear300_pmx_telecom_camera; +extern struct pmx_dev spear300_pmx_telecom_dac; +extern struct pmx_dev spear300_pmx_telecom_i2s; +extern struct pmx_dev spear300_pmx_telecom_boot_pins; +extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit; +extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit; +extern struct pmx_dev spear300_pmx_gpio1; /* Add spear300 machine function declarations here */ -void __init spear300_init(void); +void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR300 */ @@ -143,17 +142,18 @@ void __init spear300_init(void); /* Add spear310 machine device structure declarations here */ /* pad mux devices */ -extern struct pmx_dev pmx_emi_cs_0_1_4_5; -extern struct pmx_dev pmx_emi_cs_2_3; -extern struct pmx_dev pmx_uart1; -extern struct pmx_dev pmx_uart2; -extern struct pmx_dev pmx_uart3_4_5; -extern struct pmx_dev pmx_fsmc; -extern struct pmx_dev pmx_rs485_0_1; -extern struct pmx_dev pmx_tdm0; +extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5; +extern struct pmx_dev spear310_pmx_emi_cs_2_3; +extern struct pmx_dev spear310_pmx_uart1; +extern struct pmx_dev spear310_pmx_uart2; +extern struct pmx_dev spear310_pmx_uart3_4_5; +extern struct pmx_dev spear310_pmx_fsmc; +extern struct pmx_dev spear310_pmx_rs485_0_1; +extern struct pmx_dev spear310_pmx_tdm0; /* Add spear310 machine function declarations here */ -void __init spear310_init(void); +void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR310 */ @@ -162,37 +162,38 @@ void __init spear310_init(void); /* Add spear320 machine device structure declarations here */ /* pad mux modes */ -extern struct pmx_mode auto_net_smii_mode; -extern struct pmx_mode auto_net_mii_mode; -extern struct pmx_mode auto_exp_mode; -extern struct pmx_mode small_printers_mode; +extern struct pmx_mode spear320_auto_net_smii_mode; +extern struct pmx_mode spear320_auto_net_mii_mode; +extern struct pmx_mode spear320_auto_exp_mode; +extern struct pmx_mode spear320_small_printers_mode; /* pad mux devices */ -extern struct pmx_dev pmx_clcd; -extern struct pmx_dev pmx_emi; -extern struct pmx_dev pmx_fsmc; -extern struct pmx_dev pmx_spp; -extern struct pmx_dev pmx_sdhci; -extern struct pmx_dev pmx_i2s; -extern struct pmx_dev pmx_uart1; -extern struct pmx_dev pmx_uart1_modem; -extern struct pmx_dev pmx_uart2; -extern struct pmx_dev pmx_touchscreen; -extern struct pmx_dev pmx_can; -extern struct pmx_dev pmx_sdhci_led; -extern struct pmx_dev pmx_pwm0; -extern struct pmx_dev pmx_pwm1; -extern struct pmx_dev pmx_pwm2; -extern struct pmx_dev pmx_pwm3; -extern struct pmx_dev pmx_ssp1; -extern struct pmx_dev pmx_ssp2; -extern struct pmx_dev pmx_mii1; -extern struct pmx_dev pmx_smii0; -extern struct pmx_dev pmx_smii1; -extern struct pmx_dev pmx_i2c1; +extern struct pmx_dev spear320_pmx_clcd; +extern struct pmx_dev spear320_pmx_emi; +extern struct pmx_dev spear320_pmx_fsmc; +extern struct pmx_dev spear320_pmx_spp; +extern struct pmx_dev spear320_pmx_sdhci; +extern struct pmx_dev spear320_pmx_i2s; +extern struct pmx_dev spear320_pmx_uart1; +extern struct pmx_dev spear320_pmx_uart1_modem; +extern struct pmx_dev spear320_pmx_uart2; +extern struct pmx_dev spear320_pmx_touchscreen; +extern struct pmx_dev spear320_pmx_can; +extern struct pmx_dev spear320_pmx_sdhci_led; +extern struct pmx_dev spear320_pmx_pwm0; +extern struct pmx_dev spear320_pmx_pwm1; +extern struct pmx_dev spear320_pmx_pwm2; +extern struct pmx_dev spear320_pmx_pwm3; +extern struct pmx_dev spear320_pmx_ssp1; +extern struct pmx_dev spear320_pmx_ssp2; +extern struct pmx_dev spear320_pmx_mii1; +extern struct pmx_dev spear320_pmx_smii0; +extern struct pmx_dev spear320_pmx_smii1; +extern struct pmx_dev spear320_pmx_i2c1; /* Add spear320 machine function declarations here */ -void __init spear320_init(void); +void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count); #endif /* CONFIG_MACH_SPEAR320 */ diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h index a1a7f481866d..6e265442808e 100644 --- a/arch/arm/mach-spear3xx/include/mach/irqs.h +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -15,138 +15,140 @@ #define __MACH_IRQS_H /* SPEAr3xx IRQ definitions */ -#define IRQ_HW_ACCEL_MOD_0 0 -#define IRQ_INTRCOMM_RAS_ARM 1 -#define IRQ_CPU_GPT1_1 2 -#define IRQ_CPU_GPT1_2 3 -#define IRQ_BASIC_GPT1_1 4 -#define IRQ_BASIC_GPT1_2 5 -#define IRQ_BASIC_GPT2_1 6 -#define IRQ_BASIC_GPT2_2 7 -#define IRQ_BASIC_DMA 8 -#define IRQ_BASIC_SMI 9 -#define IRQ_BASIC_RTC 10 -#define IRQ_BASIC_GPIO 11 -#define IRQ_BASIC_WDT 12 -#define IRQ_DDR_CONTROLLER 13 -#define IRQ_SYS_ERROR 14 -#define IRQ_WAKEUP_RCV 15 -#define IRQ_JPEG 16 -#define IRQ_IRDA 17 -#define IRQ_ADC 18 -#define IRQ_UART 19 -#define IRQ_SSP 20 -#define IRQ_I2C 21 -#define IRQ_MAC_1 22 -#define IRQ_MAC_2 23 -#define IRQ_USB_DEV 24 -#define IRQ_USB_H_OHCI_0 25 -#define IRQ_USB_H_EHCI_0 26 -#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0 -#define IRQ_USB_H_OHCI_1 27 -#define IRQ_GEN_RAS_1 28 -#define IRQ_GEN_RAS_2 29 -#define IRQ_GEN_RAS_3 30 -#define IRQ_HW_ACCEL_MOD_1 31 -#define IRQ_VIC_END 32 - -#define VIRQ_START IRQ_VIC_END +#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0 +#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 +#define SPEAR3XX_IRQ_CPU_GPT1_1 2 +#define SPEAR3XX_IRQ_CPU_GPT1_2 3 +#define SPEAR3XX_IRQ_BASIC_GPT1_1 4 +#define SPEAR3XX_IRQ_BASIC_GPT1_2 5 +#define SPEAR3XX_IRQ_BASIC_GPT2_1 6 +#define SPEAR3XX_IRQ_BASIC_GPT2_2 7 +#define SPEAR3XX_IRQ_BASIC_DMA 8 +#define SPEAR3XX_IRQ_BASIC_SMI 9 +#define SPEAR3XX_IRQ_BASIC_RTC 10 +#define SPEAR3XX_IRQ_BASIC_GPIO 11 +#define SPEAR3XX_IRQ_BASIC_WDT 12 +#define SPEAR3XX_IRQ_DDR_CONTROLLER 13 +#define SPEAR3XX_IRQ_SYS_ERROR 14 +#define SPEAR3XX_IRQ_WAKEUP_RCV 15 +#define SPEAR3XX_IRQ_JPEG 16 +#define SPEAR3XX_IRQ_IRDA 17 +#define SPEAR3XX_IRQ_ADC 18 +#define SPEAR3XX_IRQ_UART 19 +#define SPEAR3XX_IRQ_SSP 20 +#define SPEAR3XX_IRQ_I2C 21 +#define SPEAR3XX_IRQ_MAC_1 22 +#define SPEAR3XX_IRQ_MAC_2 23 +#define SPEAR3XX_IRQ_USB_DEV 24 +#define SPEAR3XX_IRQ_USB_H_OHCI_0 25 +#define SPEAR3XX_IRQ_USB_H_EHCI_0 26 +#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0 +#define SPEAR3XX_IRQ_USB_H_OHCI_1 27 +#define SPEAR3XX_IRQ_GEN_RAS_1 28 +#define SPEAR3XX_IRQ_GEN_RAS_2 29 +#define SPEAR3XX_IRQ_GEN_RAS_3 30 +#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31 +#define SPEAR3XX_IRQ_VIC_END 32 + +#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END /* SPEAr300 Virtual irq definitions */ -#ifdef CONFIG_MACH_SPEAR300 /* IRQs sharing IRQ_GEN_RAS_1 */ -#define VIRQ_IT_PERS_S (VIRQ_START + 0) -#define VIRQ_IT_CHANGE_S (VIRQ_START + 1) -#define VIRQ_I2S (VIRQ_START + 2) -#define VIRQ_TDM (VIRQ_START + 3) -#define VIRQ_CAMERA_L (VIRQ_START + 4) -#define VIRQ_CAMERA_F (VIRQ_START + 5) -#define VIRQ_CAMERA_V (VIRQ_START + 6) -#define VIRQ_KEYBOARD (VIRQ_START + 7) -#define VIRQ_GPIO1 (VIRQ_START + 8) +#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) +#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) +#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) +#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) +#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) +#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) +#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) +#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) +#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) /* IRQs sharing IRQ_GEN_RAS_3 */ -#define IRQ_CLCD IRQ_GEN_RAS_3 +#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM - -/* GPIO pins virtual irqs */ -#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9) -#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8) -#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8) +#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM /* SPEAr310 Virtual irq definitions */ -#elif defined(CONFIG_MACH_SPEAR310) /* IRQs sharing IRQ_GEN_RAS_1 */ -#define VIRQ_SMII0 (VIRQ_START + 0) -#define VIRQ_SMII1 (VIRQ_START + 1) -#define VIRQ_SMII2 (VIRQ_START + 2) -#define VIRQ_SMII3 (VIRQ_START + 3) -#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 4) -#define VIRQ_WAKEUP_SMII1 (VIRQ_START + 5) -#define VIRQ_WAKEUP_SMII2 (VIRQ_START + 6) -#define VIRQ_WAKEUP_SMII3 (VIRQ_START + 7) +#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) +#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) +#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) +#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) +#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) +#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) +#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) +#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) /* IRQs sharing IRQ_GEN_RAS_2 */ -#define VIRQ_UART1 (VIRQ_START + 8) -#define VIRQ_UART2 (VIRQ_START + 9) -#define VIRQ_UART3 (VIRQ_START + 10) -#define VIRQ_UART4 (VIRQ_START + 11) -#define VIRQ_UART5 (VIRQ_START + 12) +#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) /* IRQs sharing IRQ_GEN_RAS_3 */ -#define VIRQ_EMI (VIRQ_START + 13) -#define VIRQ_PLGPIO (VIRQ_START + 14) +#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) +#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define VIRQ_TDM_HDLC (VIRQ_START + 15) -#define VIRQ_RS485_0 (VIRQ_START + 16) -#define VIRQ_RS485_1 (VIRQ_START + 17) - -/* GPIO pins virtual irqs */ -#define SPEAR_GPIO_INT_BASE (VIRQ_START + 18) +#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) +#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) +#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) /* SPEAr320 Virtual irq definitions */ -#else /* IRQs sharing IRQ_GEN_RAS_1 */ -#define VIRQ_EMI (VIRQ_START + 0) -#define VIRQ_CLCD (VIRQ_START + 1) -#define VIRQ_SPP (VIRQ_START + 2) +#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) +#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) +#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) /* IRQs sharing IRQ_GEN_RAS_2 */ -#define IRQ_SDHCI IRQ_GEN_RAS_2 +#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 /* IRQs sharing IRQ_GEN_RAS_3 */ -#define VIRQ_PLGPIO (VIRQ_START + 3) -#define VIRQ_I2S_PLAY (VIRQ_START + 4) -#define VIRQ_I2S_REC (VIRQ_START + 5) +#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) +#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) +#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define VIRQ_CANU (VIRQ_START + 6) -#define VIRQ_CANL (VIRQ_START + 7) -#define VIRQ_UART1 (VIRQ_START + 8) -#define VIRQ_UART2 (VIRQ_START + 9) -#define VIRQ_SSP1 (VIRQ_START + 10) -#define VIRQ_SSP2 (VIRQ_START + 11) -#define VIRQ_SMII0 (VIRQ_START + 12) -#define VIRQ_MII1_SMII1 (VIRQ_START + 13) -#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14) -#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15) -#define VIRQ_I2C (VIRQ_START + 16) - -/* GPIO pins virtual irqs */ -#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17) +#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) +#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) +#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) +#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) +#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) +#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) +#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) +/* + * GPIO pins virtual irqs + * Use the lowest number for the GPIO virtual IRQs base on which subarchs + * we have compiled in + */ +#if defined(CONFIG_MACH_SPEAR310) +#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18) +#elif defined(CONFIG_MACH_SPEAR320) +#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17) +#else +#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9) #endif -/* PLGPIO Virtual IRQs */ +#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) +#define SPEAR3XX_PLGPIO_COUNT 102 + #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) -#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8) -#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + 102) +#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) +#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \ + SPEAR3XX_PLGPIO_COUNT) +#else +#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8) #endif -#define VIRQ_END SPEAR_GPIO_INT_END -#define NR_IRQS VIRQ_END +#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END +#define NR_IRQS SPEAR3XX_VIRQ_END #endif /* __MACH_IRQS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h index c723515f8853..3b6ea0729040 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear300.h +++ b/arch/arm/mach-spear3xx/include/mach/spear300.h @@ -20,19 +20,19 @@ #define SPEAR300_TELECOM_BASE UL(0x50000000) /* Interrupt registers offsets and masks */ -#define INT_ENB_MASK_REG 0x54 -#define INT_STS_MASK_REG 0x58 -#define IT_PERS_S_IRQ_MASK (1 << 0) -#define IT_CHANGE_S_IRQ_MASK (1 << 1) -#define I2S_IRQ_MASK (1 << 2) -#define TDM_IRQ_MASK (1 << 3) -#define CAMERA_L_IRQ_MASK (1 << 4) -#define CAMERA_F_IRQ_MASK (1 << 5) -#define CAMERA_V_IRQ_MASK (1 << 6) -#define KEYBOARD_IRQ_MASK (1 << 7) -#define GPIO1_IRQ_MASK (1 << 8) - -#define SHIRQ_RAS1_MASK 0x1FF +#define SPEAR300_INT_ENB_MASK_REG 0x54 +#define SPEAR300_INT_STS_MASK_REG 0x58 +#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) +#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) +#define SPEAR300_I2S_IRQ_MASK (1 << 2) +#define SPEAR300_TDM_IRQ_MASK (1 << 3) +#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) +#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) +#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) +#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) +#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) + +#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF #define SPEAR300_CLCD_BASE UL(0x60000000) #define SPEAR300_SDHCI_BASE UL(0x70000000) diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h index 1e853479b8cd..1567d0da725f 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h @@ -29,29 +29,29 @@ #define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) /* Interrupt registers offsets and masks */ -#define INT_STS_MASK_REG 0x04 -#define SMII0_IRQ_MASK (1 << 0) -#define SMII1_IRQ_MASK (1 << 1) -#define SMII2_IRQ_MASK (1 << 2) -#define SMII3_IRQ_MASK (1 << 3) -#define WAKEUP_SMII0_IRQ_MASK (1 << 4) -#define WAKEUP_SMII1_IRQ_MASK (1 << 5) -#define WAKEUP_SMII2_IRQ_MASK (1 << 6) -#define WAKEUP_SMII3_IRQ_MASK (1 << 7) -#define UART1_IRQ_MASK (1 << 8) -#define UART2_IRQ_MASK (1 << 9) -#define UART3_IRQ_MASK (1 << 10) -#define UART4_IRQ_MASK (1 << 11) -#define UART5_IRQ_MASK (1 << 12) -#define EMI_IRQ_MASK (1 << 13) -#define TDM_HDLC_IRQ_MASK (1 << 14) -#define RS485_0_IRQ_MASK (1 << 15) -#define RS485_1_IRQ_MASK (1 << 16) +#define SPEAR310_INT_STS_MASK_REG 0x04 +#define SPEAR310_SMII0_IRQ_MASK (1 << 0) +#define SPEAR310_SMII1_IRQ_MASK (1 << 1) +#define SPEAR310_SMII2_IRQ_MASK (1 << 2) +#define SPEAR310_SMII3_IRQ_MASK (1 << 3) +#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) +#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) +#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) +#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) +#define SPEAR310_UART1_IRQ_MASK (1 << 8) +#define SPEAR310_UART2_IRQ_MASK (1 << 9) +#define SPEAR310_UART3_IRQ_MASK (1 << 10) +#define SPEAR310_UART4_IRQ_MASK (1 << 11) +#define SPEAR310_UART5_IRQ_MASK (1 << 12) +#define SPEAR310_EMI_IRQ_MASK (1 << 13) +#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) +#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) +#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) -#define SHIRQ_RAS1_MASK 0x000FF -#define SHIRQ_RAS2_MASK 0x01F00 -#define SHIRQ_RAS3_MASK 0x02000 -#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000 +#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF +#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 +#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 +#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 #endif /* __MACH_SPEAR310_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h index 940f0d85d959..8cfa83fa1296 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -36,31 +36,31 @@ #define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) /* Interrupt registers offsets and masks */ -#define INT_STS_MASK_REG 0x04 -#define INT_CLR_MASK_REG 0x04 -#define INT_ENB_MASK_REG 0x08 -#define GPIO_IRQ_MASK (1 << 0) -#define I2S_PLAY_IRQ_MASK (1 << 1) -#define I2S_REC_IRQ_MASK (1 << 2) -#define EMI_IRQ_MASK (1 << 7) -#define CLCD_IRQ_MASK (1 << 8) -#define SPP_IRQ_MASK (1 << 9) -#define SDHCI_IRQ_MASK (1 << 10) -#define CAN_U_IRQ_MASK (1 << 11) -#define CAN_L_IRQ_MASK (1 << 12) -#define UART1_IRQ_MASK (1 << 13) -#define UART2_IRQ_MASK (1 << 14) -#define SSP1_IRQ_MASK (1 << 15) -#define SSP2_IRQ_MASK (1 << 16) -#define SMII0_IRQ_MASK (1 << 17) -#define MII1_SMII1_IRQ_MASK (1 << 18) -#define WAKEUP_SMII0_IRQ_MASK (1 << 19) -#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) -#define I2C1_IRQ_MASK (1 << 21) +#define SPEAR320_INT_STS_MASK_REG 0x04 +#define SPEAR320_INT_CLR_MASK_REG 0x04 +#define SPEAR320_INT_ENB_MASK_REG 0x08 +#define SPEAR320_GPIO_IRQ_MASK (1 << 0) +#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) +#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) +#define SPEAR320_EMI_IRQ_MASK (1 << 7) +#define SPEAR320_CLCD_IRQ_MASK (1 << 8) +#define SPEAR320_SPP_IRQ_MASK (1 << 9) +#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) +#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) +#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) +#define SPEAR320_UART1_IRQ_MASK (1 << 13) +#define SPEAR320_UART2_IRQ_MASK (1 << 14) +#define SPEAR320_SSP1_IRQ_MASK (1 << 15) +#define SPEAR320_SSP2_IRQ_MASK (1 << 16) +#define SPEAR320_SMII0_IRQ_MASK (1 << 17) +#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) +#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) +#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) +#define SPEAR320_I2C1_IRQ_MASK (1 << 21) -#define SHIRQ_RAS1_MASK 0x000380 -#define SHIRQ_RAS3_MASK 0x000007 -#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 +#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 +#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 +#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 #endif /* __MACH_SPEAR320_H */ diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c index 2697e65adf86..a5e46b4ade20 100644 --- a/arch/arm/mach-spear3xx/spear300.c +++ b/arch/arm/mach-spear3xx/spear300.c @@ -40,86 +40,86 @@ #define CAML_LCD_MODE (1 << 12) #define ALL_MODES 0x1FFF -struct pmx_mode nand_mode = { +struct pmx_mode spear300_nand_mode = { .id = NAND_MODE, .name = "nand mode", .mask = 0x00, }; -struct pmx_mode nor_mode = { +struct pmx_mode spear300_nor_mode = { .id = NOR_MODE, .name = "nor mode", .mask = 0x01, }; -struct pmx_mode photo_frame_mode = { +struct pmx_mode spear300_photo_frame_mode = { .id = PHOTO_FRAME_MODE, .name = "photo frame mode", .mask = 0x02, }; -struct pmx_mode lend_ip_phone_mode = { +struct pmx_mode spear300_lend_ip_phone_mode = { .id = LEND_IP_PHONE_MODE, .name = "lend ip phone mode", .mask = 0x03, }; -struct pmx_mode hend_ip_phone_mode = { +struct pmx_mode spear300_hend_ip_phone_mode = { .id = HEND_IP_PHONE_MODE, .name = "hend ip phone mode", .mask = 0x04, }; -struct pmx_mode lend_wifi_phone_mode = { +struct pmx_mode spear300_lend_wifi_phone_mode = { .id = LEND_WIFI_PHONE_MODE, .name = "lend wifi phone mode", .mask = 0x05, }; -struct pmx_mode hend_wifi_phone_mode = { +struct pmx_mode spear300_hend_wifi_phone_mode = { .id = HEND_WIFI_PHONE_MODE, .name = "hend wifi phone mode", .mask = 0x06, }; -struct pmx_mode ata_pabx_wi2s_mode = { +struct pmx_mode spear300_ata_pabx_wi2s_mode = { .id = ATA_PABX_WI2S_MODE, .name = "ata pabx wi2s mode", .mask = 0x07, }; -struct pmx_mode ata_pabx_i2s_mode = { +struct pmx_mode spear300_ata_pabx_i2s_mode = { .id = ATA_PABX_I2S_MODE, .name = "ata pabx i2s mode", .mask = 0x08, }; -struct pmx_mode caml_lcdw_mode = { +struct pmx_mode spear300_caml_lcdw_mode = { .id = CAML_LCDW_MODE, .name = "caml lcdw mode", .mask = 0x0C, }; -struct pmx_mode camu_lcd_mode = { +struct pmx_mode spear300_camu_lcd_mode = { .id = CAMU_LCD_MODE, .name = "camu lcd mode", .mask = 0x0D, }; -struct pmx_mode camu_wlcd_mode = { +struct pmx_mode spear300_camu_wlcd_mode = { .id = CAMU_WLCD_MODE, .name = "camu wlcd mode", .mask = 0x0E, }; -struct pmx_mode caml_lcd_mode = { +struct pmx_mode spear300_caml_lcd_mode = { .id = CAML_LCD_MODE, .name = "caml lcd mode", .mask = 0x0F, }; /* devices */ -struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { +static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { { .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, @@ -127,14 +127,14 @@ struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { }, }; -struct pmx_dev pmx_fsmc_2_chips = { +struct pmx_dev spear300_pmx_fsmc_2_chips = { .name = "fsmc_2_chips", .modes = pmx_fsmc_2_chips_modes, .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { +static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { { .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, @@ -142,14 +142,14 @@ struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { }, }; -struct pmx_dev pmx_fsmc_4_chips = { +struct pmx_dev spear300_pmx_fsmc_4_chips = { .name = "fsmc_4_chips", .modes = pmx_fsmc_4_chips_modes, .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_keyboard_modes[] = { +static struct pmx_dev_mode pmx_keyboard_modes[] = { { .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | @@ -159,14 +159,14 @@ struct pmx_dev_mode pmx_keyboard_modes[] = { }, }; -struct pmx_dev pmx_keyboard = { +struct pmx_dev spear300_pmx_keyboard = { .name = "keyboard", .modes = pmx_keyboard_modes, .mode_count = ARRAY_SIZE(pmx_keyboard_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_clcd_modes[] = { +static struct pmx_dev_mode pmx_clcd_modes[] = { { .ids = PHOTO_FRAME_MODE, .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK , @@ -177,14 +177,14 @@ struct pmx_dev_mode pmx_clcd_modes[] = { }, }; -struct pmx_dev pmx_clcd = { +struct pmx_dev spear300_pmx_clcd = { .name = "clcd", .modes = pmx_clcd_modes, .mode_count = ARRAY_SIZE(pmx_clcd_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_gpio_modes[] = { +static struct pmx_dev_mode pmx_telecom_gpio_modes[] = { { .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE, .mask = PMX_MII_MASK, @@ -204,14 +204,14 @@ struct pmx_dev_mode pmx_telecom_gpio_modes[] = { }, }; -struct pmx_dev pmx_telecom_gpio = { +struct pmx_dev spear300_pmx_telecom_gpio = { .name = "telecom_gpio", .modes = pmx_telecom_gpio_modes, .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_tdm_modes[] = { +static struct pmx_dev_mode pmx_telecom_tdm_modes[] = { { .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE @@ -222,14 +222,14 @@ struct pmx_dev_mode pmx_telecom_tdm_modes[] = { }, }; -struct pmx_dev pmx_telecom_tdm = { +struct pmx_dev spear300_pmx_telecom_tdm = { .name = "telecom_tdm", .modes = pmx_telecom_tdm_modes, .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { +static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { { .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE @@ -239,14 +239,14 @@ struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { }, }; -struct pmx_dev pmx_telecom_spi_cs_i2c_clk = { +struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = { .name = "telecom_spi_cs_i2c_clk", .modes = pmx_telecom_spi_cs_i2c_clk_modes, .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_camera_modes[] = { +static struct pmx_dev_mode pmx_telecom_camera_modes[] = { { .ids = CAML_LCDW_MODE | CAML_LCD_MODE, .mask = PMX_MII_MASK, @@ -256,14 +256,14 @@ struct pmx_dev_mode pmx_telecom_camera_modes[] = { }, }; -struct pmx_dev pmx_telecom_camera = { +struct pmx_dev spear300_pmx_telecom_camera = { .name = "telecom_camera", .modes = pmx_telecom_camera_modes, .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_dac_modes[] = { +static struct pmx_dev_mode pmx_telecom_dac_modes[] = { { .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE | CAML_LCD_MODE, @@ -271,14 +271,14 @@ struct pmx_dev_mode pmx_telecom_dac_modes[] = { }, }; -struct pmx_dev pmx_telecom_dac = { +struct pmx_dev spear300_pmx_telecom_dac = { .name = "telecom_dac", .modes = pmx_telecom_dac_modes, .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_i2s_modes[] = { +static struct pmx_dev_mode pmx_telecom_i2s_modes[] = { { .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | @@ -288,14 +288,14 @@ struct pmx_dev_mode pmx_telecom_i2s_modes[] = { }, }; -struct pmx_dev pmx_telecom_i2s = { +struct pmx_dev spear300_pmx_telecom_i2s = { .name = "telecom_i2s", .modes = pmx_telecom_i2s_modes, .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { +static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { { .ids = NAND_MODE | NOR_MODE, .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | @@ -303,14 +303,14 @@ struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { }, }; -struct pmx_dev pmx_telecom_boot_pins = { +struct pmx_dev spear300_pmx_telecom_boot_pins = { .name = "telecom_boot_pins", .modes = pmx_telecom_boot_pins_modes, .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { +static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { { .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | @@ -323,14 +323,14 @@ struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { }, }; -struct pmx_dev pmx_telecom_sdhci_4bit = { +struct pmx_dev spear300_pmx_telecom_sdhci_4bit = { .name = "telecom_sdhci_4bit", .modes = pmx_telecom_sdhci_4bit_modes, .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { +static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { { .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | @@ -342,14 +342,14 @@ struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { }, }; -struct pmx_dev pmx_telecom_sdhci_8bit = { +struct pmx_dev spear300_pmx_telecom_sdhci_8bit = { .name = "telecom_sdhci_8bit", .modes = pmx_telecom_sdhci_8bit_modes, .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_gpio1_modes[] = { +static struct pmx_dev_mode pmx_gpio1_modes[] = { { .ids = PHOTO_FRAME_MODE, .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | @@ -357,7 +357,7 @@ struct pmx_dev_mode pmx_gpio1_modes[] = { }, }; -struct pmx_dev pmx_gpio1 = { +struct pmx_dev spear300_pmx_gpio1 = { .name = "arm gpio1", .modes = pmx_gpio1_modes, .mode_count = ARRAY_SIZE(pmx_gpio1_modes), @@ -365,60 +365,60 @@ struct pmx_dev pmx_gpio1 = { }; /* pmx driver structure */ -struct pmx_driver pmx_driver = { +static struct pmx_driver pmx_driver = { .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f}, .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, }; /* spear3xx shared irq */ -struct shirq_dev_config shirq_ras1_config[] = { +static struct shirq_dev_config shirq_ras1_config[] = { { - .virq = VIRQ_IT_PERS_S, - .enb_mask = IT_PERS_S_IRQ_MASK, - .status_mask = IT_PERS_S_IRQ_MASK, + .virq = SPEAR300_VIRQ_IT_PERS_S, + .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK, + .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK, }, { - .virq = VIRQ_IT_CHANGE_S, - .enb_mask = IT_CHANGE_S_IRQ_MASK, - .status_mask = IT_CHANGE_S_IRQ_MASK, + .virq = SPEAR300_VIRQ_IT_CHANGE_S, + .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK, + .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK, }, { - .virq = VIRQ_I2S, - .enb_mask = I2S_IRQ_MASK, - .status_mask = I2S_IRQ_MASK, + .virq = SPEAR300_VIRQ_I2S, + .enb_mask = SPEAR300_I2S_IRQ_MASK, + .status_mask = SPEAR300_I2S_IRQ_MASK, }, { - .virq = VIRQ_TDM, - .enb_mask = TDM_IRQ_MASK, - .status_mask = TDM_IRQ_MASK, + .virq = SPEAR300_VIRQ_TDM, + .enb_mask = SPEAR300_TDM_IRQ_MASK, + .status_mask = SPEAR300_TDM_IRQ_MASK, }, { - .virq = VIRQ_CAMERA_L, - .enb_mask = CAMERA_L_IRQ_MASK, - .status_mask = CAMERA_L_IRQ_MASK, + .virq = SPEAR300_VIRQ_CAMERA_L, + .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK, + .status_mask = SPEAR300_CAMERA_L_IRQ_MASK, }, { - .virq = VIRQ_CAMERA_F, - .enb_mask = CAMERA_F_IRQ_MASK, - .status_mask = CAMERA_F_IRQ_MASK, + .virq = SPEAR300_VIRQ_CAMERA_F, + .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK, + .status_mask = SPEAR300_CAMERA_F_IRQ_MASK, }, { - .virq = VIRQ_CAMERA_V, - .enb_mask = CAMERA_V_IRQ_MASK, - .status_mask = CAMERA_V_IRQ_MASK, + .virq = SPEAR300_VIRQ_CAMERA_V, + .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK, + .status_mask = SPEAR300_CAMERA_V_IRQ_MASK, }, { - .virq = VIRQ_KEYBOARD, - .enb_mask = KEYBOARD_IRQ_MASK, - .status_mask = KEYBOARD_IRQ_MASK, + .virq = SPEAR300_VIRQ_KEYBOARD, + .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK, + .status_mask = SPEAR300_KEYBOARD_IRQ_MASK, }, { - .virq = VIRQ_GPIO1, - .enb_mask = GPIO1_IRQ_MASK, - .status_mask = GPIO1_IRQ_MASK, + .virq = SPEAR300_VIRQ_GPIO1, + .enb_mask = SPEAR300_GPIO1_IRQ_MASK, + .status_mask = SPEAR300_GPIO1_IRQ_MASK, }, }; -struct spear_shirq shirq_ras1 = { - .irq = IRQ_GEN_RAS_1, +static struct spear_shirq shirq_ras1 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_1, .dev_config = shirq_ras1_config, .dev_count = ARRAY_SIZE(shirq_ras1_config), .regs = { - .enb_reg = INT_ENB_MASK_REG, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS1_MASK, + .enb_reg = SPEAR300_INT_ENB_MASK_REG, + .status_reg = SPEAR300_INT_STS_MASK_REG, + .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK, .clear_reg = -1, }, }; @@ -427,10 +427,10 @@ struct spear_shirq shirq_ras1 = { /* arm gpio1 device registration */ static struct pl061_platform_data gpio1_plat_data = { .gpio_base = 8, - .irq_base = SPEAR_GPIO1_INT_BASE, + .irq_base = SPEAR300_GPIO1_INT_BASE, }; -struct amba_device gpio1_device = { +struct amba_device spear300_gpio1_device = { .dev = { .init_name = "gpio1", .platform_data = &gpio1_plat_data, @@ -440,11 +440,12 @@ struct amba_device gpio1_device = { .end = SPEAR300_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, - .irq = {VIRQ_GPIO1, NO_IRQ}, + .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ}, }; /* spear300 routines */ -void __init spear300_init(void) +void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { int ret = 0; @@ -460,6 +461,10 @@ void __init spear300_init(void) } /* pmx initialization */ + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; + pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); if (pmx_driver.base) { ret = pmx_register(&pmx_driver); diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c index 42d2253ef540..69006f694220 100644 --- a/arch/arm/mach-spear3xx/spear300_evb.c +++ b/arch/arm/mach-spear3xx/spear300_evb.c @@ -19,26 +19,26 @@ /* padmux devices to enable */ static struct pmx_dev *pmx_devs[] = { /* spear3xx specific devices */ - &pmx_i2c, - &pmx_ssp_cs, - &pmx_ssp, - &pmx_mii, - &pmx_uart0, + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp_cs, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, /* spear300 specific devices */ - &pmx_fsmc_2_chips, - &pmx_clcd, - &pmx_telecom_sdhci_4bit, - &pmx_gpio1, + &spear300_pmx_fsmc_2_chips, + &spear300_pmx_clcd, + &spear300_pmx_telecom_sdhci_4bit, + &spear300_pmx_gpio1, }; static struct amba_device *amba_devs[] __initdata = { /* spear3xx specific devices */ - &gpio_device, - &uart_device, + &spear3xx_gpio_device, + &spear3xx_uart_device, /* spear300 specific devices */ - &gpio1_device, + &spear300_gpio1_device, }; static struct platform_device *plat_devs[] __initdata = { @@ -51,13 +51,9 @@ static void __init spear300_evb_init(void) { unsigned int i; - /* padmux initialization, must be done before spear300_init */ - pmx_driver.mode = &photo_frame_mode; - pmx_driver.devs = pmx_devs; - pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); - /* call spear300 machine init function */ - spear300_init(); + spear300_init(&spear300_photo_frame_mode, pmx_devs, + ARRAY_SIZE(pmx_devs)); /* Add Platform Devices */ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c index 5c0a67b60c2a..9004cf9f01bf 100644 --- a/arch/arm/mach-spear3xx/spear310.c +++ b/arch/arm/mach-spear3xx/spear310.c @@ -22,112 +22,112 @@ #define PAD_MUX_CONFIG_REG 0x08 /* devices */ -struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { +static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_emi_cs_0_1_4_5 = { +struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { .name = "emi_cs_0_1_4_5", .modes = pmx_emi_cs_0_1_4_5_modes, .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { +static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_emi_cs_2_3 = { +struct pmx_dev spear310_pmx_emi_cs_2_3 = { .name = "emi_cs_2_3", .modes = pmx_emi_cs_2_3_modes, .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart1_modes[] = { +static struct pmx_dev_mode pmx_uart1_modes[] = { { .ids = 0x00, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_uart1 = { +struct pmx_dev spear310_pmx_uart1 = { .name = "uart1", .modes = pmx_uart1_modes, .mode_count = ARRAY_SIZE(pmx_uart1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart2_modes[] = { +static struct pmx_dev_mode pmx_uart2_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_uart2 = { +struct pmx_dev spear310_pmx_uart2 = { .name = "uart2", .modes = pmx_uart2_modes, .mode_count = ARRAY_SIZE(pmx_uart2_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart3_4_5_modes[] = { +static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { { .ids = 0x00, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_uart3_4_5 = { +struct pmx_dev spear310_pmx_uart3_4_5 = { .name = "uart3_4_5", .modes = pmx_uart3_4_5_modes, .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_fsmc_modes[] = { +static struct pmx_dev_mode pmx_fsmc_modes[] = { { .ids = 0x00, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_fsmc = { +struct pmx_dev spear310_pmx_fsmc = { .name = "fsmc", .modes = pmx_fsmc_modes, .mode_count = ARRAY_SIZE(pmx_fsmc_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_rs485_0_1_modes[] = { +static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { { .ids = 0x00, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_rs485_0_1 = { +struct pmx_dev spear310_pmx_rs485_0_1 = { .name = "rs485_0_1", .modes = pmx_rs485_0_1_modes, .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_tdm0_modes[] = { +static struct pmx_dev_mode pmx_tdm0_modes[] = { { .ids = 0x00, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_tdm0 = { +struct pmx_dev spear310_pmx_tdm0 = { .name = "tdm0", .modes = pmx_tdm0_modes, .mode_count = ARRAY_SIZE(pmx_tdm0_modes), @@ -135,122 +135,122 @@ struct pmx_dev pmx_tdm0 = { }; /* pmx driver structure */ -struct pmx_driver pmx_driver = { +static struct pmx_driver pmx_driver = { .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, }; /* spear3xx shared irq */ -struct shirq_dev_config shirq_ras1_config[] = { +static struct shirq_dev_config shirq_ras1_config[] = { { - .virq = VIRQ_SMII0, - .status_mask = SMII0_IRQ_MASK, + .virq = SPEAR310_VIRQ_SMII0, + .status_mask = SPEAR310_SMII0_IRQ_MASK, }, { - .virq = VIRQ_SMII1, - .status_mask = SMII1_IRQ_MASK, + .virq = SPEAR310_VIRQ_SMII1, + .status_mask = SPEAR310_SMII1_IRQ_MASK, }, { - .virq = VIRQ_SMII2, - .status_mask = SMII2_IRQ_MASK, + .virq = SPEAR310_VIRQ_SMII2, + .status_mask = SPEAR310_SMII2_IRQ_MASK, }, { - .virq = VIRQ_SMII3, - .status_mask = SMII3_IRQ_MASK, + .virq = SPEAR310_VIRQ_SMII3, + .status_mask = SPEAR310_SMII3_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII0, - .status_mask = WAKEUP_SMII0_IRQ_MASK, + .virq = SPEAR310_VIRQ_WAKEUP_SMII0, + .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII1, - .status_mask = WAKEUP_SMII1_IRQ_MASK, + .virq = SPEAR310_VIRQ_WAKEUP_SMII1, + .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII2, - .status_mask = WAKEUP_SMII2_IRQ_MASK, + .virq = SPEAR310_VIRQ_WAKEUP_SMII2, + .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII3, - .status_mask = WAKEUP_SMII3_IRQ_MASK, + .virq = SPEAR310_VIRQ_WAKEUP_SMII3, + .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK, }, }; -struct spear_shirq shirq_ras1 = { - .irq = IRQ_GEN_RAS_1, +static struct spear_shirq shirq_ras1 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_1, .dev_config = shirq_ras1_config, .dev_count = ARRAY_SIZE(shirq_ras1_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS1_MASK, + .status_reg = SPEAR310_INT_STS_MASK_REG, + .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK, .clear_reg = -1, }, }; -struct shirq_dev_config shirq_ras2_config[] = { +static struct shirq_dev_config shirq_ras2_config[] = { { - .virq = VIRQ_UART1, - .status_mask = UART1_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART1, + .status_mask = SPEAR310_UART1_IRQ_MASK, }, { - .virq = VIRQ_UART2, - .status_mask = UART2_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART2, + .status_mask = SPEAR310_UART2_IRQ_MASK, }, { - .virq = VIRQ_UART3, - .status_mask = UART3_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART3, + .status_mask = SPEAR310_UART3_IRQ_MASK, }, { - .virq = VIRQ_UART4, - .status_mask = UART4_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART4, + .status_mask = SPEAR310_UART4_IRQ_MASK, }, { - .virq = VIRQ_UART5, - .status_mask = UART5_IRQ_MASK, + .virq = SPEAR310_VIRQ_UART5, + .status_mask = SPEAR310_UART5_IRQ_MASK, }, }; -struct spear_shirq shirq_ras2 = { - .irq = IRQ_GEN_RAS_2, +static struct spear_shirq shirq_ras2 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_2, .dev_config = shirq_ras2_config, .dev_count = ARRAY_SIZE(shirq_ras2_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS2_MASK, + .status_reg = SPEAR310_INT_STS_MASK_REG, + .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK, .clear_reg = -1, }, }; -struct shirq_dev_config shirq_ras3_config[] = { +static struct shirq_dev_config shirq_ras3_config[] = { { - .virq = VIRQ_EMI, - .status_mask = EMI_IRQ_MASK, + .virq = SPEAR310_VIRQ_EMI, + .status_mask = SPEAR310_EMI_IRQ_MASK, }, }; -struct spear_shirq shirq_ras3 = { - .irq = IRQ_GEN_RAS_3, +static struct spear_shirq shirq_ras3 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_3, .dev_config = shirq_ras3_config, .dev_count = ARRAY_SIZE(shirq_ras3_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS3_MASK, + .status_reg = SPEAR310_INT_STS_MASK_REG, + .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK, .clear_reg = -1, }, }; -struct shirq_dev_config shirq_intrcomm_ras_config[] = { +static struct shirq_dev_config shirq_intrcomm_ras_config[] = { { - .virq = VIRQ_TDM_HDLC, - .status_mask = TDM_HDLC_IRQ_MASK, + .virq = SPEAR310_VIRQ_TDM_HDLC, + .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK, }, { - .virq = VIRQ_RS485_0, - .status_mask = RS485_0_IRQ_MASK, + .virq = SPEAR310_VIRQ_RS485_0, + .status_mask = SPEAR310_RS485_0_IRQ_MASK, }, { - .virq = VIRQ_RS485_1, - .status_mask = RS485_1_IRQ_MASK, + .virq = SPEAR310_VIRQ_RS485_1, + .status_mask = SPEAR310_RS485_1_IRQ_MASK, }, }; -struct spear_shirq shirq_intrcomm_ras = { - .irq = IRQ_INTRCOMM_RAS_ARM, +static struct spear_shirq shirq_intrcomm_ras = { + .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, .dev_config = shirq_intrcomm_ras_config, .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, + .status_reg = SPEAR310_INT_STS_MASK_REG, + .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK, .clear_reg = -1, }, }; @@ -258,7 +258,8 @@ struct spear_shirq shirq_intrcomm_ras = { /* Add spear310 specific devices here */ /* spear310 routines */ -void __init spear310_init(void) +void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { void __iomem *base; int ret = 0; @@ -296,6 +297,10 @@ void __init spear310_init(void) /* pmx initialization */ pmx_driver.base = base; + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; + ret = pmx_register(&pmx_driver); if (ret) printk(KERN_ERR "padmux: registeration failed. err no: %d\n", diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c index 2d7f333bd67b..c8684ce1f9b3 100644 --- a/arch/arm/mach-spear3xx/spear310_evb.c +++ b/arch/arm/mach-spear3xx/spear310_evb.c @@ -19,31 +19,31 @@ /* padmux devices to enable */ static struct pmx_dev *pmx_devs[] = { /* spear3xx specific devices */ - &pmx_i2c, - &pmx_ssp, - &pmx_gpio_pin0, - &pmx_gpio_pin1, - &pmx_gpio_pin2, - &pmx_gpio_pin3, - &pmx_gpio_pin4, - &pmx_gpio_pin5, - &pmx_uart0, + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_gpio_pin0, + &spear3xx_pmx_gpio_pin1, + &spear3xx_pmx_gpio_pin2, + &spear3xx_pmx_gpio_pin3, + &spear3xx_pmx_gpio_pin4, + &spear3xx_pmx_gpio_pin5, + &spear3xx_pmx_uart0, /* spear310 specific devices */ - &pmx_emi_cs_0_1_4_5, - &pmx_emi_cs_2_3, - &pmx_uart1, - &pmx_uart2, - &pmx_uart3_4_5, - &pmx_fsmc, - &pmx_rs485_0_1, - &pmx_tdm0, + &spear310_pmx_emi_cs_0_1_4_5, + &spear310_pmx_emi_cs_2_3, + &spear310_pmx_uart1, + &spear310_pmx_uart2, + &spear310_pmx_uart3_4_5, + &spear310_pmx_fsmc, + &spear310_pmx_rs485_0_1, + &spear310_pmx_tdm0, }; static struct amba_device *amba_devs[] __initdata = { /* spear3xx specific devices */ - &gpio_device, - &uart_device, + &spear3xx_gpio_device, + &spear3xx_uart_device, /* spear310 specific devices */ }; @@ -58,13 +58,8 @@ static void __init spear310_evb_init(void) { unsigned int i; - /* padmux initialization, must be done before spear310_init */ - pmx_driver.mode = NULL; - pmx_driver.devs = pmx_devs; - pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); - /* call spear310 machine init function */ - spear310_init(); + spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs)); /* Add Platform Devices */ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c index 741c1f414cbd..ee29bef43074 100644 --- a/arch/arm/mach-spear3xx/spear320.c +++ b/arch/arm/mach-spear3xx/spear320.c @@ -29,88 +29,88 @@ #define SMALL_PRINTERS_MODE (1 << 3) #define ALL_MODES 0xF -struct pmx_mode auto_net_smii_mode = { +struct pmx_mode spear320_auto_net_smii_mode = { .id = AUTO_NET_SMII_MODE, .name = "Automation Networking SMII Mode", .mask = 0x00, }; -struct pmx_mode auto_net_mii_mode = { +struct pmx_mode spear320_auto_net_mii_mode = { .id = AUTO_NET_MII_MODE, .name = "Automation Networking MII Mode", .mask = 0x01, }; -struct pmx_mode auto_exp_mode = { +struct pmx_mode spear320_auto_exp_mode = { .id = AUTO_EXP_MODE, .name = "Automation Expanded Mode", .mask = 0x02, }; -struct pmx_mode small_printers_mode = { +struct pmx_mode spear320_small_printers_mode = { .id = SMALL_PRINTERS_MODE, .name = "Small Printers Mode", .mask = 0x03, }; /* devices */ -struct pmx_dev_mode pmx_clcd_modes[] = { +static struct pmx_dev_mode pmx_clcd_modes[] = { { .ids = AUTO_NET_SMII_MODE, .mask = 0x0, }, }; -struct pmx_dev pmx_clcd = { +struct pmx_dev spear320_pmx_clcd = { .name = "clcd", .modes = pmx_clcd_modes, .mode_count = ARRAY_SIZE(pmx_clcd_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_emi_modes[] = { +static struct pmx_dev_mode pmx_emi_modes[] = { { .ids = AUTO_EXP_MODE, .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_emi = { +struct pmx_dev spear320_pmx_emi = { .name = "emi", .modes = pmx_emi_modes, .mode_count = ARRAY_SIZE(pmx_emi_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_fsmc_modes[] = { +static struct pmx_dev_mode pmx_fsmc_modes[] = { { .ids = ALL_MODES, .mask = 0x0, }, }; -struct pmx_dev pmx_fsmc = { +struct pmx_dev spear320_pmx_fsmc = { .name = "fsmc", .modes = pmx_fsmc_modes, .mode_count = ARRAY_SIZE(pmx_fsmc_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_spp_modes[] = { +static struct pmx_dev_mode pmx_spp_modes[] = { { .ids = SMALL_PRINTERS_MODE, .mask = 0x0, }, }; -struct pmx_dev pmx_spp = { +struct pmx_dev spear320_pmx_spp = { .name = "spp", .modes = pmx_spp_modes, .mode_count = ARRAY_SIZE(pmx_spp_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_sdhci_modes[] = { +static struct pmx_dev_mode pmx_sdhci_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | SMALL_PRINTERS_MODE, @@ -118,42 +118,42 @@ struct pmx_dev_mode pmx_sdhci_modes[] = { }, }; -struct pmx_dev pmx_sdhci = { +struct pmx_dev spear320_pmx_sdhci = { .name = "sdhci", .modes = pmx_sdhci_modes, .mode_count = ARRAY_SIZE(pmx_sdhci_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_i2s_modes[] = { +static struct pmx_dev_mode pmx_i2s_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_i2s = { +struct pmx_dev spear320_pmx_i2s = { .name = "i2s", .modes = pmx_i2s_modes, .mode_count = ARRAY_SIZE(pmx_i2s_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart1_modes[] = { +static struct pmx_dev_mode pmx_uart1_modes[] = { { .ids = ALL_MODES, .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, }, }; -struct pmx_dev pmx_uart1 = { +struct pmx_dev spear320_pmx_uart1 = { .name = "uart1", .modes = pmx_uart1_modes, .mode_count = ARRAY_SIZE(pmx_uart1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart1_modem_modes[] = { +static struct pmx_dev_mode pmx_uart1_modem_modes[] = { { .ids = AUTO_EXP_MODE, .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | @@ -165,42 +165,42 @@ struct pmx_dev_mode pmx_uart1_modem_modes[] = { }, }; -struct pmx_dev pmx_uart1_modem = { +struct pmx_dev spear320_pmx_uart1_modem = { .name = "uart1_modem", .modes = pmx_uart1_modem_modes, .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_uart2_modes[] = { +static struct pmx_dev_mode pmx_uart2_modes[] = { { .ids = ALL_MODES, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_uart2 = { +struct pmx_dev spear320_pmx_uart2 = { .name = "uart2", .modes = pmx_uart2_modes, .mode_count = ARRAY_SIZE(pmx_uart2_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_touchscreen_modes[] = { +static struct pmx_dev_mode pmx_touchscreen_modes[] = { { .ids = AUTO_NET_SMII_MODE, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_touchscreen = { +struct pmx_dev spear320_pmx_touchscreen = { .name = "touchscreen", .modes = pmx_touchscreen_modes, .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_can_modes[] = { +static struct pmx_dev_mode pmx_can_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | @@ -208,28 +208,28 @@ struct pmx_dev_mode pmx_can_modes[] = { }, }; -struct pmx_dev pmx_can = { +struct pmx_dev spear320_pmx_can = { .name = "can", .modes = pmx_can_modes, .mode_count = ARRAY_SIZE(pmx_can_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_sdhci_led_modes[] = { +static struct pmx_dev_mode pmx_sdhci_led_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_sdhci_led = { +struct pmx_dev spear320_pmx_sdhci_led = { .name = "sdhci_led", .modes = pmx_sdhci_led_modes, .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_pwm0_modes[] = { +static struct pmx_dev_mode pmx_pwm0_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_UART0_MODEM_MASK, @@ -239,14 +239,14 @@ struct pmx_dev_mode pmx_pwm0_modes[] = { }, }; -struct pmx_dev pmx_pwm0 = { +struct pmx_dev spear320_pmx_pwm0 = { .name = "pwm0", .modes = pmx_pwm0_modes, .mode_count = ARRAY_SIZE(pmx_pwm0_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_pwm1_modes[] = { +static struct pmx_dev_mode pmx_pwm1_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_UART0_MODEM_MASK, @@ -256,14 +256,14 @@ struct pmx_dev_mode pmx_pwm1_modes[] = { }, }; -struct pmx_dev pmx_pwm1 = { +struct pmx_dev spear320_pmx_pwm1 = { .name = "pwm1", .modes = pmx_pwm1_modes, .mode_count = ARRAY_SIZE(pmx_pwm1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_pwm2_modes[] = { +static struct pmx_dev_mode pmx_pwm2_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, .mask = PMX_SSP_CS_MASK, @@ -273,105 +273,105 @@ struct pmx_dev_mode pmx_pwm2_modes[] = { }, }; -struct pmx_dev pmx_pwm2 = { +struct pmx_dev spear320_pmx_pwm2 = { .name = "pwm2", .modes = pmx_pwm2_modes, .mode_count = ARRAY_SIZE(pmx_pwm2_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_pwm3_modes[] = { +static struct pmx_dev_mode pmx_pwm3_modes[] = { { .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_pwm3 = { +struct pmx_dev spear320_pmx_pwm3 = { .name = "pwm3", .modes = pmx_pwm3_modes, .mode_count = ARRAY_SIZE(pmx_pwm3_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_ssp1_modes[] = { +static struct pmx_dev_mode pmx_ssp1_modes[] = { { .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_ssp1 = { +struct pmx_dev spear320_pmx_ssp1 = { .name = "ssp1", .modes = pmx_ssp1_modes, .mode_count = ARRAY_SIZE(pmx_ssp1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_ssp2_modes[] = { +static struct pmx_dev_mode pmx_ssp2_modes[] = { { .ids = AUTO_NET_SMII_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_ssp2 = { +struct pmx_dev spear320_pmx_ssp2 = { .name = "ssp2", .modes = pmx_ssp2_modes, .mode_count = ARRAY_SIZE(pmx_ssp2_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_mii1_modes[] = { +static struct pmx_dev_mode pmx_mii1_modes[] = { { .ids = AUTO_NET_MII_MODE, .mask = 0x0, }, }; -struct pmx_dev pmx_mii1 = { +struct pmx_dev spear320_pmx_mii1 = { .name = "mii1", .modes = pmx_mii1_modes, .mode_count = ARRAY_SIZE(pmx_mii1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_smii0_modes[] = { +static struct pmx_dev_mode pmx_smii0_modes[] = { { .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_smii0 = { +struct pmx_dev spear320_pmx_smii0 = { .name = "smii0", .modes = pmx_smii0_modes, .mode_count = ARRAY_SIZE(pmx_smii0_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_smii1_modes[] = { +static struct pmx_dev_mode pmx_smii1_modes[] = { { .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_smii1 = { +struct pmx_dev spear320_pmx_smii1 = { .name = "smii1", .modes = pmx_smii1_modes, .mode_count = ARRAY_SIZE(pmx_smii1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_i2c1_modes[] = { +static struct pmx_dev_mode pmx_i2c1_modes[] = { { .ids = AUTO_EXP_MODE, .mask = 0x0, }, }; -struct pmx_dev pmx_i2c1 = { +struct pmx_dev spear320_pmx_i2c1 = { .name = "i2c1", .modes = pmx_i2c1_modes, .mode_count = ARRAY_SIZE(pmx_i2c1_modes), @@ -379,131 +379,131 @@ struct pmx_dev pmx_i2c1 = { }; /* pmx driver structure */ -struct pmx_driver pmx_driver = { +static struct pmx_driver pmx_driver = { .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, }; /* spear3xx shared irq */ -struct shirq_dev_config shirq_ras1_config[] = { +static struct shirq_dev_config shirq_ras1_config[] = { { - .virq = VIRQ_EMI, - .status_mask = EMI_IRQ_MASK, - .clear_mask = EMI_IRQ_MASK, + .virq = SPEAR320_VIRQ_EMI, + .status_mask = SPEAR320_EMI_IRQ_MASK, + .clear_mask = SPEAR320_EMI_IRQ_MASK, }, { - .virq = VIRQ_CLCD, - .status_mask = CLCD_IRQ_MASK, - .clear_mask = CLCD_IRQ_MASK, + .virq = SPEAR320_VIRQ_CLCD, + .status_mask = SPEAR320_CLCD_IRQ_MASK, + .clear_mask = SPEAR320_CLCD_IRQ_MASK, }, { - .virq = VIRQ_SPP, - .status_mask = SPP_IRQ_MASK, - .clear_mask = SPP_IRQ_MASK, + .virq = SPEAR320_VIRQ_SPP, + .status_mask = SPEAR320_SPP_IRQ_MASK, + .clear_mask = SPEAR320_SPP_IRQ_MASK, }, }; -struct spear_shirq shirq_ras1 = { - .irq = IRQ_GEN_RAS_1, +static struct spear_shirq shirq_ras1 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_1, .dev_config = shirq_ras1_config, .dev_count = ARRAY_SIZE(shirq_ras1_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS1_MASK, - .clear_reg = INT_CLR_MASK_REG, + .status_reg = SPEAR320_INT_STS_MASK_REG, + .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK, + .clear_reg = SPEAR320_INT_CLR_MASK_REG, .reset_to_clear = 1, }, }; -struct shirq_dev_config shirq_ras3_config[] = { +static struct shirq_dev_config shirq_ras3_config[] = { { - .virq = VIRQ_PLGPIO, - .enb_mask = GPIO_IRQ_MASK, - .status_mask = GPIO_IRQ_MASK, - .clear_mask = GPIO_IRQ_MASK, + .virq = SPEAR320_VIRQ_PLGPIO, + .enb_mask = SPEAR320_GPIO_IRQ_MASK, + .status_mask = SPEAR320_GPIO_IRQ_MASK, + .clear_mask = SPEAR320_GPIO_IRQ_MASK, }, { - .virq = VIRQ_I2S_PLAY, - .enb_mask = I2S_PLAY_IRQ_MASK, - .status_mask = I2S_PLAY_IRQ_MASK, - .clear_mask = I2S_PLAY_IRQ_MASK, + .virq = SPEAR320_VIRQ_I2S_PLAY, + .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK, + .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK, + .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK, }, { - .virq = VIRQ_I2S_REC, - .enb_mask = I2S_REC_IRQ_MASK, - .status_mask = I2S_REC_IRQ_MASK, - .clear_mask = I2S_REC_IRQ_MASK, + .virq = SPEAR320_VIRQ_I2S_REC, + .enb_mask = SPEAR320_I2S_REC_IRQ_MASK, + .status_mask = SPEAR320_I2S_REC_IRQ_MASK, + .clear_mask = SPEAR320_I2S_REC_IRQ_MASK, }, }; -struct spear_shirq shirq_ras3 = { - .irq = IRQ_GEN_RAS_3, +static struct spear_shirq shirq_ras3 = { + .irq = SPEAR3XX_IRQ_GEN_RAS_3, .dev_config = shirq_ras3_config, .dev_count = ARRAY_SIZE(shirq_ras3_config), .regs = { - .enb_reg = INT_ENB_MASK_REG, + .enb_reg = SPEAR320_INT_ENB_MASK_REG, .reset_to_enb = 1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_RAS3_MASK, - .clear_reg = INT_CLR_MASK_REG, + .status_reg = SPEAR320_INT_STS_MASK_REG, + .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK, + .clear_reg = SPEAR320_INT_CLR_MASK_REG, .reset_to_clear = 1, }, }; -struct shirq_dev_config shirq_intrcomm_ras_config[] = { +static struct shirq_dev_config shirq_intrcomm_ras_config[] = { { - .virq = VIRQ_CANU, - .status_mask = CAN_U_IRQ_MASK, - .clear_mask = CAN_U_IRQ_MASK, + .virq = SPEAR320_VIRQ_CANU, + .status_mask = SPEAR320_CAN_U_IRQ_MASK, + .clear_mask = SPEAR320_CAN_U_IRQ_MASK, }, { - .virq = VIRQ_CANL, - .status_mask = CAN_L_IRQ_MASK, - .clear_mask = CAN_L_IRQ_MASK, + .virq = SPEAR320_VIRQ_CANL, + .status_mask = SPEAR320_CAN_L_IRQ_MASK, + .clear_mask = SPEAR320_CAN_L_IRQ_MASK, }, { - .virq = VIRQ_UART1, - .status_mask = UART1_IRQ_MASK, - .clear_mask = UART1_IRQ_MASK, + .virq = SPEAR320_VIRQ_UART1, + .status_mask = SPEAR320_UART1_IRQ_MASK, + .clear_mask = SPEAR320_UART1_IRQ_MASK, }, { - .virq = VIRQ_UART2, - .status_mask = UART2_IRQ_MASK, - .clear_mask = UART2_IRQ_MASK, + .virq = SPEAR320_VIRQ_UART2, + .status_mask = SPEAR320_UART2_IRQ_MASK, + .clear_mask = SPEAR320_UART2_IRQ_MASK, }, { - .virq = VIRQ_SSP1, - .status_mask = SSP1_IRQ_MASK, - .clear_mask = SSP1_IRQ_MASK, + .virq = SPEAR320_VIRQ_SSP1, + .status_mask = SPEAR320_SSP1_IRQ_MASK, + .clear_mask = SPEAR320_SSP1_IRQ_MASK, }, { - .virq = VIRQ_SSP2, - .status_mask = SSP2_IRQ_MASK, - .clear_mask = SSP2_IRQ_MASK, + .virq = SPEAR320_VIRQ_SSP2, + .status_mask = SPEAR320_SSP2_IRQ_MASK, + .clear_mask = SPEAR320_SSP2_IRQ_MASK, }, { - .virq = VIRQ_SMII0, - .status_mask = SMII0_IRQ_MASK, - .clear_mask = SMII0_IRQ_MASK, + .virq = SPEAR320_VIRQ_SMII0, + .status_mask = SPEAR320_SMII0_IRQ_MASK, + .clear_mask = SPEAR320_SMII0_IRQ_MASK, }, { - .virq = VIRQ_MII1_SMII1, - .status_mask = MII1_SMII1_IRQ_MASK, - .clear_mask = MII1_SMII1_IRQ_MASK, + .virq = SPEAR320_VIRQ_MII1_SMII1, + .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK, + .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_SMII0, - .status_mask = WAKEUP_SMII0_IRQ_MASK, - .clear_mask = WAKEUP_SMII0_IRQ_MASK, + .virq = SPEAR320_VIRQ_WAKEUP_SMII0, + .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, + .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK, }, { - .virq = VIRQ_WAKEUP_MII1_SMII1, - .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK, - .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK, + .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1, + .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, + .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK, }, { - .virq = VIRQ_I2C, - .status_mask = I2C1_IRQ_MASK, - .clear_mask = I2C1_IRQ_MASK, + .virq = SPEAR320_VIRQ_I2C1, + .status_mask = SPEAR320_I2C1_IRQ_MASK, + .clear_mask = SPEAR320_I2C1_IRQ_MASK, }, }; -struct spear_shirq shirq_intrcomm_ras = { - .irq = IRQ_INTRCOMM_RAS_ARM, +static struct spear_shirq shirq_intrcomm_ras = { + .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, .dev_config = shirq_intrcomm_ras_config, .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), .regs = { .enb_reg = -1, - .status_reg = INT_STS_MASK_REG, - .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, - .clear_reg = INT_CLR_MASK_REG, + .status_reg = SPEAR320_INT_STS_MASK_REG, + .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK, + .clear_reg = SPEAR320_INT_CLR_MASK_REG, .reset_to_clear = 1, }, }; @@ -511,7 +511,8 @@ struct spear_shirq shirq_intrcomm_ras = { /* Add spear320 specific devices here */ /* spear320 routines */ -void __init spear320_init(void) +void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, + u8 pmx_dev_count) { void __iomem *base; int ret = 0; @@ -543,6 +544,10 @@ void __init spear320_init(void) /* pmx initialization */ pmx_driver.base = base; + pmx_driver.mode = pmx_mode; + pmx_driver.devs = pmx_devs; + pmx_driver.devs_count = pmx_dev_count; + ret = pmx_register(&pmx_driver); if (ret) printk(KERN_ERR "padmux: registeration failed. err no: %d\n", diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c index 8213e4b66c14..a12b353940d6 100644 --- a/arch/arm/mach-spear3xx/spear320_evb.c +++ b/arch/arm/mach-spear3xx/spear320_evb.c @@ -19,28 +19,28 @@ /* padmux devices to enable */ static struct pmx_dev *pmx_devs[] = { /* spear3xx specific devices */ - &pmx_i2c, - &pmx_ssp, - &pmx_mii, - &pmx_uart0, + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, /* spear320 specific devices */ - &pmx_fsmc, - &pmx_sdhci, - &pmx_i2s, - &pmx_uart1, - &pmx_uart2, - &pmx_can, - &pmx_pwm0, - &pmx_pwm1, - &pmx_pwm2, - &pmx_mii1, + &spear320_pmx_fsmc, + &spear320_pmx_sdhci, + &spear320_pmx_i2s, + &spear320_pmx_uart1, + &spear320_pmx_uart2, + &spear320_pmx_can, + &spear320_pmx_pwm0, + &spear320_pmx_pwm1, + &spear320_pmx_pwm2, + &spear320_pmx_mii1, }; static struct amba_device *amba_devs[] __initdata = { /* spear3xx specific devices */ - &gpio_device, - &uart_device, + &spear3xx_gpio_device, + &spear3xx_uart_device, /* spear320 specific devices */ }; @@ -55,13 +55,9 @@ static void __init spear320_evb_init(void) { unsigned int i; - /* padmux initialization, must be done before spear320_init */ - pmx_driver.mode = &auto_net_mii_mode; - pmx_driver.devs = pmx_devs; - pmx_driver.devs_count = ARRAY_SIZE(pmx_devs); - /* call spear320 machine init function */ - spear320_init(); + spear320_init(&spear320_auto_net_mii_mode, pmx_devs, + ARRAY_SIZE(pmx_devs)); /* Add Platform Devices */ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index d3ba8ca1bc59..10af45da86a0 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -25,10 +25,10 @@ /* gpio device registration */ static struct pl061_platform_data gpio_plat_data = { .gpio_base = 0, - .irq_base = SPEAR_GPIO_INT_BASE, + .irq_base = SPEAR3XX_GPIO_INT_BASE, }; -struct amba_device gpio_device = { +struct amba_device spear3xx_gpio_device = { .dev = { .init_name = "gpio", .platform_data = &gpio_plat_data, @@ -38,11 +38,11 @@ struct amba_device gpio_device = { .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, - .irq = {IRQ_BASIC_GPIO, NO_IRQ}, + .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ}, }; /* uart device registration */ -struct amba_device uart_device = { +struct amba_device spear3xx_uart_device = { .dev = { .init_name = "uart", }, @@ -51,7 +51,7 @@ struct amba_device uart_device = { .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, - .irq = {IRQ_UART, NO_IRQ}, + .irq = {SPEAR3XX_IRQ_UART, NO_IRQ}, }; /* Do spear3xx familiy common initialization part here */ @@ -97,215 +97,215 @@ void __init spear3xx_map_io(void) iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); /* This will initialize clock framework */ - clk_init(); + spear3xx_clk_init(); } /* pad multiplexing support */ /* devices */ -struct pmx_dev_mode pmx_firda_modes[] = { +static struct pmx_dev_mode pmx_firda_modes[] = { { .ids = 0xffffffff, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_firda = { +struct pmx_dev spear3xx_pmx_firda = { .name = "firda", .modes = pmx_firda_modes, .mode_count = ARRAY_SIZE(pmx_firda_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_i2c_modes[] = { +static struct pmx_dev_mode pmx_i2c_modes[] = { { .ids = 0xffffffff, .mask = PMX_I2C_MASK, }, }; -struct pmx_dev pmx_i2c = { +struct pmx_dev spear3xx_pmx_i2c = { .name = "i2c", .modes = pmx_i2c_modes, .mode_count = ARRAY_SIZE(pmx_i2c_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_ssp_cs_modes[] = { +static struct pmx_dev_mode pmx_ssp_cs_modes[] = { { .ids = 0xffffffff, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_ssp_cs = { +struct pmx_dev spear3xx_pmx_ssp_cs = { .name = "ssp_chip_selects", .modes = pmx_ssp_cs_modes, .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_ssp_modes[] = { +static struct pmx_dev_mode pmx_ssp_modes[] = { { .ids = 0xffffffff, .mask = PMX_SSP_MASK, }, }; -struct pmx_dev pmx_ssp = { +struct pmx_dev spear3xx_pmx_ssp = { .name = "ssp", .modes = pmx_ssp_modes, .mode_count = ARRAY_SIZE(pmx_ssp_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_mii_modes[] = { +static struct pmx_dev_mode pmx_mii_modes[] = { { .ids = 0xffffffff, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_mii = { +struct pmx_dev spear3xx_pmx_mii = { .name = "mii", .modes = pmx_mii_modes, .mode_count = ARRAY_SIZE(pmx_mii_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin0_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN0_MASK, }, }; -struct pmx_dev pmx_gpio_pin0 = { +struct pmx_dev spear3xx_pmx_gpio_pin0 = { .name = "gpio_pin0", .modes = pmx_gpio_pin0_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin1_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN1_MASK, }, }; -struct pmx_dev pmx_gpio_pin1 = { +struct pmx_dev spear3xx_pmx_gpio_pin1 = { .name = "gpio_pin1", .modes = pmx_gpio_pin1_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin2_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN2_MASK, }, }; -struct pmx_dev pmx_gpio_pin2 = { +struct pmx_dev spear3xx_pmx_gpio_pin2 = { .name = "gpio_pin2", .modes = pmx_gpio_pin2_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin3_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN3_MASK, }, }; -struct pmx_dev pmx_gpio_pin3 = { +struct pmx_dev spear3xx_pmx_gpio_pin3 = { .name = "gpio_pin3", .modes = pmx_gpio_pin3_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin4_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN4_MASK, }, }; -struct pmx_dev pmx_gpio_pin4 = { +struct pmx_dev spear3xx_pmx_gpio_pin4 = { .name = "gpio_pin4", .modes = pmx_gpio_pin4_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_gpio_pin5_modes[] = { +static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { { .ids = 0xffffffff, .mask = PMX_GPIO_PIN5_MASK, }, }; -struct pmx_dev pmx_gpio_pin5 = { +struct pmx_dev spear3xx_pmx_gpio_pin5 = { .name = "gpio_pin5", .modes = pmx_gpio_pin5_modes, .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_uart0_modem_modes[] = { +static struct pmx_dev_mode pmx_uart0_modem_modes[] = { { .ids = 0xffffffff, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_uart0_modem = { +struct pmx_dev spear3xx_pmx_uart0_modem = { .name = "uart0_modem", .modes = pmx_uart0_modem_modes, .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_uart0_modes[] = { +static struct pmx_dev_mode pmx_uart0_modes[] = { { .ids = 0xffffffff, .mask = PMX_UART0_MASK, }, }; -struct pmx_dev pmx_uart0 = { +struct pmx_dev spear3xx_pmx_uart0 = { .name = "uart0", .modes = pmx_uart0_modes, .mode_count = ARRAY_SIZE(pmx_uart0_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_timer_3_4_modes[] = { +static struct pmx_dev_mode pmx_timer_3_4_modes[] = { { .ids = 0xffffffff, .mask = PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_timer_3_4 = { +struct pmx_dev spear3xx_pmx_timer_3_4 = { .name = "timer_3_4", .modes = pmx_timer_3_4_modes, .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), .enb_on_reset = 0, }; -struct pmx_dev_mode pmx_timer_1_2_modes[] = { +static struct pmx_dev_mode pmx_timer_1_2_modes[] = { { .ids = 0xffffffff, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_timer_1_2 = { +struct pmx_dev spear3xx_pmx_timer_1_2 = { .name = "timer_1_2", .modes = pmx_timer_1_2_modes, .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), @@ -314,210 +314,210 @@ struct pmx_dev pmx_timer_1_2 = { #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) /* plgpios devices */ -struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { +static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { { .ids = 0x00, .mask = PMX_FIRDA_MASK, }, }; -struct pmx_dev pmx_plgpio_0_1 = { +struct pmx_dev spear3xx_pmx_plgpio_0_1 = { .name = "plgpio 0 and 1", .modes = pmx_plgpio_0_1_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { +static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { { .ids = 0x00, .mask = PMX_UART0_MASK, }, }; -struct pmx_dev pmx_plgpio_2_3 = { +struct pmx_dev spear3xx_pmx_plgpio_2_3 = { .name = "plgpio 2 and 3", .modes = pmx_plgpio_2_3_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { +static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { { .ids = 0x00, .mask = PMX_I2C_MASK, }, }; -struct pmx_dev pmx_plgpio_4_5 = { +struct pmx_dev spear3xx_pmx_plgpio_4_5 = { .name = "plgpio 4 and 5", .modes = pmx_plgpio_4_5_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { +static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { { .ids = 0x00, .mask = PMX_SSP_MASK, }, }; -struct pmx_dev pmx_plgpio_6_9 = { +struct pmx_dev spear3xx_pmx_plgpio_6_9 = { .name = "plgpio 6 to 9", .modes = pmx_plgpio_6_9_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { +static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { { .ids = 0x00, .mask = PMX_MII_MASK, }, }; -struct pmx_dev pmx_plgpio_10_27 = { +struct pmx_dev spear3xx_pmx_plgpio_10_27 = { .name = "plgpio 10 to 27", .modes = pmx_plgpio_10_27_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_28_modes[] = { +static struct pmx_dev_mode pmx_plgpio_28_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN0_MASK, }, }; -struct pmx_dev pmx_plgpio_28 = { +struct pmx_dev spear3xx_pmx_plgpio_28 = { .name = "plgpio 28", .modes = pmx_plgpio_28_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_29_modes[] = { +static struct pmx_dev_mode pmx_plgpio_29_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN1_MASK, }, }; -struct pmx_dev pmx_plgpio_29 = { +struct pmx_dev spear3xx_pmx_plgpio_29 = { .name = "plgpio 29", .modes = pmx_plgpio_29_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_30_modes[] = { +static struct pmx_dev_mode pmx_plgpio_30_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN2_MASK, }, }; -struct pmx_dev pmx_plgpio_30 = { +struct pmx_dev spear3xx_pmx_plgpio_30 = { .name = "plgpio 30", .modes = pmx_plgpio_30_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_31_modes[] = { +static struct pmx_dev_mode pmx_plgpio_31_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN3_MASK, }, }; -struct pmx_dev pmx_plgpio_31 = { +struct pmx_dev spear3xx_pmx_plgpio_31 = { .name = "plgpio 31", .modes = pmx_plgpio_31_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_32_modes[] = { +static struct pmx_dev_mode pmx_plgpio_32_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN4_MASK, }, }; -struct pmx_dev pmx_plgpio_32 = { +struct pmx_dev spear3xx_pmx_plgpio_32 = { .name = "plgpio 32", .modes = pmx_plgpio_32_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_33_modes[] = { +static struct pmx_dev_mode pmx_plgpio_33_modes[] = { { .ids = 0x00, .mask = PMX_GPIO_PIN5_MASK, }, }; -struct pmx_dev pmx_plgpio_33 = { +struct pmx_dev spear3xx_pmx_plgpio_33 = { .name = "plgpio 33", .modes = pmx_plgpio_33_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { +static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { { .ids = 0x00, .mask = PMX_SSP_CS_MASK, }, }; -struct pmx_dev pmx_plgpio_34_36 = { +struct pmx_dev spear3xx_pmx_plgpio_34_36 = { .name = "plgpio 34 to 36", .modes = pmx_plgpio_34_36_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { +static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { { .ids = 0x00, .mask = PMX_UART0_MODEM_MASK, }, }; -struct pmx_dev pmx_plgpio_37_42 = { +struct pmx_dev spear3xx_pmx_plgpio_37_42 = { .name = "plgpio 37 to 42", .modes = pmx_plgpio_37_42_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { +static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_1_2_MASK, }, }; -struct pmx_dev pmx_plgpio_43_44_47_48 = { +struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { .name = "plgpio 43, 44, 47 and 48", .modes = pmx_plgpio_43_44_47_48_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), .enb_on_reset = 1, }; -struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { +static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { { .ids = 0x00, .mask = PMX_TIMER_3_4_MASK, }, }; -struct pmx_dev pmx_plgpio_45_46_49_50 = { +struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { .name = "plgpio 45, 46, 49 and 50", .modes = pmx_plgpio_45_46_49_50_modes, .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig index bddba034f862..ff4ae5ba00f1 100644 --- a/arch/arm/mach-spear6xx/Kconfig +++ b/arch/arm/mach-spear6xx/Kconfig @@ -4,17 +4,18 @@ if ARCH_SPEAR6XX -choice - prompt "SPEAr6XX Family" - default MACH_SPEAR600 +menu "SPEAr6xx Implementations" +config BOARD_SPEAR600_EVB + bool "SPEAr600 Evaluation Board" + select MACH_SPEAR600 + help + Supports ST SPEAr600 Evaluation Board + +endmenu config MACH_SPEAR600 bool "SPEAr600" help Supports ST SPEAr600 Machine -endchoice - -# Adding SPEAr6XX machine specific configuration files -source "arch/arm/mach-spear6xx/Kconfig600" endif #ARCH_SPEAR6XX diff --git a/arch/arm/mach-spear6xx/Kconfig600 b/arch/arm/mach-spear6xx/Kconfig600 deleted file mode 100644 index 9e19f65eb78e..000000000000 --- a/arch/arm/mach-spear6xx/Kconfig600 +++ /dev/null @@ -1,17 +0,0 @@ -# -# SPEAr600 machine configuration file -# - -if MACH_SPEAR600 - -choice - prompt "SPEAr600 Boards" - default BOARD_SPEAR600_EVB - -config BOARD_SPEAR600_EVB - bool "SPEAr600 Evaluation Board" - help - Supports ST SPEAr600 Evaluation Board -endchoice - -endif #MACH_SPEAR600 diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c index 88b748b5be80..ac70e0d88fef 100644 --- a/arch/arm/mach-spear6xx/clock.c +++ b/arch/arm/mach-spear6xx/clock.c @@ -671,12 +671,12 @@ static struct clk_lookup spear_clk_lookups[] = { { .dev_id = "gpio2", .clk = &gpio2_clk}, }; -void __init clk_init(void) +void __init spear6xx_clk_init(void) { int i; for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) clk_register(&spear_clk_lookups[i]); - recalc_root_clocks(); + clk_init(); } diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h index 94cf4a648b57..183f0238c5e2 100644 --- a/arch/arm/mach-spear6xx/include/mach/generic.h +++ b/arch/arm/mach-spear6xx/include/mach/generic.h @@ -39,7 +39,7 @@ void __init spear6xx_map_io(void); void __init spear6xx_init_irq(void); void __init spear6xx_init(void); void __init spear600_init(void); -void __init clk_init(void); +void __init spear6xx_clk_init(void); /* Add spear600 machine device structure declarations here */ diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 981812961ac7..e0f6628c8b2c 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -148,7 +148,7 @@ void __init spear6xx_map_io(void) iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); /* This will initialize clock framework */ - clk_init(); + spear6xx_clk_init(); } static void __init spear6xx_timer_init(void) diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile deleted file mode 100644 index d156f76b379f..000000000000 --- a/arch/arm/mach-stmp378x/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o -obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot deleted file mode 100644 index 1568ad404d59..000000000000 --- a/arch/arm/mach-stmp378x/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x40008000 -params_phys-y := 0x40000100 -initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S deleted file mode 100644 index 731a92286da2..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/entry-macro.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Low-level IRQ helper macros for Freescale STMP378X - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #0xf0000000 @ vm address of IRQ controller - ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT - cmp \irqnr, #0x7f - moveqs \irqnr, #0 @ Zero flag set for no IRQ - - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h deleted file mode 100644 index cc59673becdd..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/irqs.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Freescale STMP378X interrupts - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#define IRQ_DEBUG_UART 0 -#define IRQ_COMMS_RX 1 -#define IRQ_COMMS_TX 1 -#define IRQ_SSP2_ERROR 2 -#define IRQ_VDD5V 3 -#define IRQ_HEADPHONE_SHORT 4 -#define IRQ_DAC_DMA 5 -#define IRQ_DAC_ERROR 6 -#define IRQ_ADC_DMA 7 -#define IRQ_ADC_ERROR 8 -#define IRQ_SPDIF_DMA 9 -#define IRQ_SAIF2_DMA 9 -#define IRQ_SPDIF_ERROR 10 -#define IRQ_SAIF1_IRQ 10 -#define IRQ_SAIF2_IRQ 10 -#define IRQ_USB_CTRL 11 -#define IRQ_USB_WAKEUP 12 -#define IRQ_GPMI_DMA 13 -#define IRQ_SSP1_DMA 14 -#define IRQ_SSP_ERROR 15 -#define IRQ_GPIO0 16 -#define IRQ_GPIO1 17 -#define IRQ_GPIO2 18 -#define IRQ_SAIF1_DMA 19 -#define IRQ_SSP2_DMA 20 -#define IRQ_ECC8_IRQ 21 -#define IRQ_RTC_ALARM 22 -#define IRQ_UARTAPP_TX_DMA 23 -#define IRQ_UARTAPP_INTERNAL 24 -#define IRQ_UARTAPP_RX_DMA 25 -#define IRQ_I2C_DMA 26 -#define IRQ_I2C_ERROR 27 -#define IRQ_TIMER0 28 -#define IRQ_TIMER1 29 -#define IRQ_TIMER2 30 -#define IRQ_TIMER3 31 -#define IRQ_BATT_BRNOUT 32 -#define IRQ_VDDD_BRNOUT 33 -#define IRQ_VDDIO_BRNOUT 34 -#define IRQ_VDD18_BRNOUT 35 -#define IRQ_TOUCH_DETECT 36 -#define IRQ_LRADC_CH0 37 -#define IRQ_LRADC_CH1 38 -#define IRQ_LRADC_CH2 39 -#define IRQ_LRADC_CH3 40 -#define IRQ_LRADC_CH4 41 -#define IRQ_LRADC_CH5 42 -#define IRQ_LRADC_CH6 43 -#define IRQ_LRADC_CH7 44 -#define IRQ_LCDIF_DMA 45 -#define IRQ_LCDIF_ERROR 46 -#define IRQ_DIGCTL_DEBUG_TRAP 47 -#define IRQ_RTC_1MSEC 48 -#define IRQ_DRI_DMA 49 -#define IRQ_DRI_ATTENTION 50 -#define IRQ_GPMI_ATTENTION 51 -#define IRQ_IR 52 -#define IRQ_DCP_VMI 53 -#define IRQ_DCP 54 -#define IRQ_BCH 56 -#define IRQ_PXP 57 -#define IRQ_UARTAPP2_TX_DMA 58 -#define IRQ_UARTAPP2_INTERNAL 59 -#define IRQ_UARTAPP2_RX_DMA 60 -#define IRQ_VDAC_DETECT 61 -#define IRQ_VDD5V_DROOP 64 -#define IRQ_DCDC4P2_BO 65 - - -#define NR_REAL_IRQS 128 -#define NR_IRQS (NR_REAL_IRQS + 32 * 3) - -/* All interrupts are FIQ capable */ -#define FIQ_START IRQ_DEBUG_UART - -/* Hard disk IRQ is a GPMI attention IRQ */ -#define IRQ_HARDDISK IRQ_GPMI_ATTENTION diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h deleted file mode 100644 index 93f952d35969..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/pins.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Freescale STMP378X SoC pin multiplexing - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_PINS_H -#define __ASM_ARCH_PINS_H - -/* - * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware - * interface this pin belongs to. - */ - -/* Bank 0 */ -#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) -#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) -#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) -#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) -#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) -#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) -#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) -#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) -#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) -#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) -#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) -#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) -#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) -#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) -#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) -#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) -#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16) -#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17) -#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18) -#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) -#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20) -#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21) -#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22) -#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23) -#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) -#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) -#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26) -#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27) -#define PINID_AUART1_RX STMP3XXX_PINID(0, 28) -#define PINID_AUART1_TX STMP3XXX_PINID(0, 29) -#define PINID_I2C_SCL STMP3XXX_PINID(0, 30) -#define PINID_I2C_SDA STMP3XXX_PINID(0, 31) - -/* Bank 1 */ -#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) -#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) -#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) -#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) -#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) -#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) -#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) -#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) -#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) -#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) -#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) -#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) -#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) -#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) -#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) -#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) -#define PINID_LCD_D16 STMP3XXX_PINID(1, 16) -#define PINID_LCD_D17 STMP3XXX_PINID(1, 17) -#define PINID_LCD_RESET STMP3XXX_PINID(1, 18) -#define PINID_LCD_RS STMP3XXX_PINID(1, 19) -#define PINID_LCD_WR STMP3XXX_PINID(1, 20) -#define PINID_LCD_CS STMP3XXX_PINID(1, 21) -#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22) -#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23) -#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24) -#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25) -#define PINID_PWM0 STMP3XXX_PINID(1, 26) -#define PINID_PWM1 STMP3XXX_PINID(1, 27) -#define PINID_PWM2 STMP3XXX_PINID(1, 28) -#define PINID_PWM3 STMP3XXX_PINID(1, 29) -#define PINID_PWM4 STMP3XXX_PINID(1, 30) - -/* Bank 2 */ -#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0) -#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1) -#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2) -#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3) -#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4) -#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5) -#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6) -#define PINID_ROTARYA STMP3XXX_PINID(2, 7) -#define PINID_ROTARYB STMP3XXX_PINID(2, 8) -#define PINID_EMI_A00 STMP3XXX_PINID(2, 9) -#define PINID_EMI_A01 STMP3XXX_PINID(2, 10) -#define PINID_EMI_A02 STMP3XXX_PINID(2, 11) -#define PINID_EMI_A03 STMP3XXX_PINID(2, 12) -#define PINID_EMI_A04 STMP3XXX_PINID(2, 13) -#define PINID_EMI_A05 STMP3XXX_PINID(2, 14) -#define PINID_EMI_A06 STMP3XXX_PINID(2, 15) -#define PINID_EMI_A07 STMP3XXX_PINID(2, 16) -#define PINID_EMI_A08 STMP3XXX_PINID(2, 17) -#define PINID_EMI_A09 STMP3XXX_PINID(2, 18) -#define PINID_EMI_A10 STMP3XXX_PINID(2, 19) -#define PINID_EMI_A11 STMP3XXX_PINID(2, 20) -#define PINID_EMI_A12 STMP3XXX_PINID(2, 21) -#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22) -#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23) -#define PINID_EMI_CASN STMP3XXX_PINID(2, 24) -#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25) -#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26) -#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27) -#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28) -#define PINID_EMI_CKE STMP3XXX_PINID(2, 29) -#define PINID_EMI_RASN STMP3XXX_PINID(2, 30) -#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) - -/* Bank 3 */ -#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) -#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) -#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) -#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) -#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) -#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) -#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) -#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) -#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) -#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) -#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) -#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) -#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) -#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) -#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) -#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) -#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16) -#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17) -#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18) -#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19) -#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) -#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) - -#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h deleted file mode 100644 index dbcf85b6ac2a..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * stmp378x: APBH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBH -#define _MACH_REGS_APBH - -#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) -#define REGS_APBH_PHYS 0x80004000 -#define REGS_APBH_SIZE 0x2000 - -#define HW_APBH_CTRL0 0x0 -#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBH_CTRL0_RESET_CHANNEL 16 -#define BM_APBH_CTRL0_CLKGATE 0x40000000 -#define BM_APBH_CTRL0_SFTRST 0x80000000 - -#define HW_APBH_CTRL1 0x10 -#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 -#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 - -#define HW_APBH_CTRL2 0x20 - -#define HW_APBH_DEVSEL 0x30 - -#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBH_CHn_NXTCMDAR 0x50 - -#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBH_CHn_CMD_COMMAND 0x00000003 -#define BP_APBH_CHn_CMD_COMMAND 0 -#define BM_APBH_CHn_CMD_CHAIN 0x00000004 -#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 -#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 -#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBH_CHn_CMD_CMDWORDS 12 -#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBH_CHn_CMD_XFER_COUNT 16 - -#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBH_CHn_SEMA 0x80 -#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBH_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h deleted file mode 100644 index 3b934a4d27f0..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * stmp378x: APBX register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBX -#define _MACH_REGS_APBX - -#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) -#define REGS_APBX_PHYS 0x80024000 -#define REGS_APBX_SIZE 0x2000 - -#define HW_APBX_CTRL0 0x0 -#define BM_APBX_CTRL0_CLKGATE 0x40000000 -#define BM_APBX_CTRL0_SFTRST 0x80000000 - -#define HW_APBX_CTRL1 0x10 - -#define HW_APBX_CTRL2 0x20 - -#define HW_APBX_CHANNEL_CTRL 0x30 -#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 -#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 - -#define HW_APBX_DEVSEL 0x40 - -#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70) -#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70) -#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70) -#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70) -#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70) -#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70) -#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70) -#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70) -#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70) -#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70) -#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70) -#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70) -#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70) -#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70) -#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70) -#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70) - -#define HW_APBX_CHn_NXTCMDAR 0x110 -#define BM_APBX_CHn_CMD_COMMAND 0x00000003 -#define BP_APBX_CHn_CMD_COMMAND 0 -#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBX_CHn_CMD_CHAIN 0x00000004 -#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 -#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBX_CHn_CMD_CMDWORDS 12 -#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBX_CHn_CMD_XFER_COUNT 16 - -#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70) -#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70) -#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70) -#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70) -#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70) -#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70) -#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70) -#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70) -#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70) -#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70) -#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70) -#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70) -#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70) -#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70) -#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70) -#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70) - -#define HW_APBX_CHn_BAR 0x130 - -#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70) -#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70) -#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70) -#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70) -#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70) -#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70) -#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70) -#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70) -#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70) -#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70) -#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70) -#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70) -#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70) -#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70) -#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70) -#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70) - -#define HW_APBX_CHn_SEMA 0x140 -#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBX_CHn_SEMA_PHORE 16 - -#endif - diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h deleted file mode 100644 index 641ac6126f83..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp378x: AUDIOIN register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000) -#define REGS_AUDIOIN_PHYS 0x8004C000 -#define REGS_AUDIOIN_SIZE 0x2000 - -#define HW_AUDIOIN_CTRL 0x0 -#define BM_AUDIOIN_CTRL_RUN 0x00000001 -#define BP_AUDIOIN_CTRL_RUN 0 -#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 -#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOIN_STAT 0x10 - -#define HW_AUDIOIN_ADCSRR 0x20 - -#define HW_AUDIOIN_ADCVOLUME 0x30 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF -#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 -#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 - -#define HW_AUDIOIN_ADCDEBUG 0x40 - -#define HW_AUDIOIN_ADCVOL 0x50 -#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F -#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 -#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 -#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 -#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 -#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 -#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 -#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 -#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 - -#define HW_AUDIOIN_MICLINE 0x60 - -#define HW_AUDIOIN_ANACLKCTRL 0x70 -#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOIN_DATA 0x80 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h deleted file mode 100644 index f533e23694a0..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * stmp378x: AUDIOOUT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) -#define REGS_AUDIOOUT_PHYS 0x80048000 -#define REGS_AUDIOOUT_SIZE 0x2000 - -#define HW_AUDIOOUT_CTRL 0x0 -#define BM_AUDIOOUT_CTRL_RUN 0x00000001 -#define BP_AUDIOOUT_CTRL_RUN 0 -#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 -#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOOUT_STAT 0x10 - -#define HW_AUDIOOUT_DACSRR 0x20 -#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF -#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 -#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 -#define BP_AUDIOOUT_DACSRR_SRC_INT 16 -#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 -#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 -#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 -#define BP_AUDIOOUT_DACSRR_BASEMULT 28 - -#define HW_AUDIOOUT_DACVOLUME 0x30 -#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 -#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 -#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_DACDEBUG 0x40 - -#define HW_AUDIOOUT_HPVOL 0x50 -#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 -#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 - -#define HW_AUDIOOUT_PWRDN 0x70 -#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 -#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 -#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 -#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 -#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 -#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 -#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000 - -#define HW_AUDIOOUT_REFCTRL 0x80 -#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 -#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 -#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 -#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 -#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 -#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 -#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 -#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 -#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 -#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 -#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 -#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 -#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 - -#define HW_AUDIOOUT_ANACTRL 0x90 -#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 -#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 - -#define HW_AUDIOOUT_TEST 0xA0 -#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 -#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 - -#define HW_AUDIOOUT_BISTCTRL 0xB0 - -#define HW_AUDIOOUT_BISTSTAT0 0xC0 - -#define HW_AUDIOOUT_BISTSTAT1 0xD0 - -#define HW_AUDIOOUT_ANACLKCTRL 0xE0 -#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOOUT_DATA 0xF0 - -#define HW_AUDIOOUT_SPEAKERCTRL 0x100 -#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000 - -#define HW_AUDIOOUT_VERSION 0x200 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h deleted file mode 100644 index 532d24650717..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-bch.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * stmp378x: BCH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000) -#define REGS_BCH_PHYS 0x8000A000 -#define REGS_BCH_SIZE 0x2000 - -#define HW_BCH_CTRL 0x0 -#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_BCH_CTRL_COMPLETE_IRQ 0 -#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 - -#define HW_BCH_STATUS0 0x10 -#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_BCH_STATUS0_CORRECTED 0x00000008 -#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 -#define BP_BCH_STATUS0_STATUS_BLK0 8 -#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_BCH_STATUS0_COMPLETED_CE 16 - -#define HW_BCH_LAYOUTSELECT 0x70 - -#define HW_BCH_FLASH0LAYOUT0 0x80 -#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 -#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 -#define BP_BCH_FLASH0LAYOUT0_ECC0 12 -#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 -#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 -#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 -#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 -#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 -#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 -#define BP_BCH_FLASH0LAYOUT1_ECCN 12 -#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 -#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 - -#define HW_BCH_BLOCKNAME 0x150 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h deleted file mode 100644 index 7c546afd57a3..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * stmp378x: CLKCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_CLKCTRL -#define _MACH_REGS_CLKCTRL - -#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) -#define REGS_CLKCTRL_PHYS 0x80040000 -#define REGS_CLKCTRL_SIZE 0x2000 - -#define HW_CLKCTRL_PLLCTRL0 0x0 -#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 - -#define HW_CLKCTRL_CPU 0x20 -#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F -#define BP_CLKCTRL_CPU_DIV_CPU 0 - -#define HW_CLKCTRL_HBUS 0x30 -#define BM_CLKCTRL_HBUS_DIV 0x0000001F -#define BP_CLKCTRL_HBUS_DIV 0 -#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 - -#define HW_CLKCTRL_XBUS 0x40 - -#define HW_CLKCTRL_XTAL 0x50 -#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 - -#define HW_CLKCTRL_PIX 0x60 -#define BM_CLKCTRL_PIX_DIV 0x00000FFF -#define BP_CLKCTRL_PIX_DIV 0 -#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 - -#define HW_CLKCTRL_SSP 0x70 - -#define HW_CLKCTRL_GPMI 0x80 - -#define HW_CLKCTRL_SPDIF 0x90 - -#define HW_CLKCTRL_EMI 0xA0 -#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F -#define BP_CLKCTRL_EMI_DIV_EMI 0 -#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 -#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 -#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 -#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 - -#define HW_CLKCTRL_IR 0xB0 - -#define HW_CLKCTRL_SAIF 0xC0 - -#define HW_CLKCTRL_TV 0xD0 - -#define HW_CLKCTRL_ETM 0xE0 - -#define HW_CLKCTRL_FRAC 0xF0 -#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 -#define BP_CLKCTRL_FRAC_EMIFRAC 8 -#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 -#define BP_CLKCTRL_FRAC_PIXFRAC 16 -#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 - -#define HW_CLKCTRL_FRAC1 0x100 - -#define HW_CLKCTRL_CLKSEQ 0x110 -#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 - -#define HW_CLKCTRL_RESET 0x120 -#define BM_CLKCTRL_RESET_DIG 0x00000001 -#define BP_CLKCTRL_RESET_DIG 0 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h deleted file mode 100644 index fdedd00c0e28..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * stmp378x: DCP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000) -#define REGS_DCP_PHYS 0x80028000 -#define REGS_DCP_SIZE 0x2000 - -#define HW_DCP_CTRL 0x0 -#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF -#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 -#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000 -#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000 -#define BM_DCP_CTRL_CLKGATE 0x40000000 -#define BM_DCP_CTRL_SFTRST 0x80000000 - -#define HW_DCP_STAT 0x10 -#define BM_DCP_STAT_IRQ 0x0000000F -#define BP_DCP_STAT_IRQ 0 - -#define HW_DCP_CHANNELCTRL 0x20 -#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF -#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 - -#define HW_DCP_CONTEXT 0x50 -#define BM_DCP_PACKET1_INTERRUPT 0x00000001 -#define BP_DCP_PACKET1_INTERRUPT 0 -#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002 -#define BM_DCP_PACKET1_CHAIN 0x00000004 -#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008 -#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020 -#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040 -#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100 -#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200 -#define BM_DCP_PACKET1_OTP_KEY 0x00000400 -#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800 -#define BM_DCP_PACKET1_HASH_INIT 0x00001000 -#define BM_DCP_PACKET1_HASH_TERM 0x00002000 -#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F -#define BP_DCP_PACKET2_CIPHER_SELECT 0 -#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0 -#define BP_DCP_PACKET2_CIPHER_MODE 4 -#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00 -#define BP_DCP_PACKET2_KEY_SELECT 8 -#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000 -#define BP_DCP_PACKET2_HASH_SELECT 16 -#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000 -#define BP_DCP_PACKET2_CIPHER_CFG 24 - -#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40) -#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40) -#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40) -#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40) - -#define HW_DCP_CHnCMDPTR 0x100 - -#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40) -#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40) -#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40) -#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40) - -#define HW_DCP_CHnSEMA 0x110 -#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF -#define BP_DCP_CHnSEMA_INCREMENT 0 - -#define HW_DCP_CH0STAT (0x120 + 0 * 0x40) -#define HW_DCP_CH1STAT (0x120 + 1 * 0x40) -#define HW_DCP_CH2STAT (0x120 + 2 * 0x40) -#define HW_DCP_CH3STAT (0x120 + 3 * 0x40) - -#define HW_DCP_CHnSTAT 0x120 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h deleted file mode 100644 index 5293005523b3..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * stmp378x: DIGCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000) -#define REGS_DIGCTL_PHYS 0x8001C000 -#define REGS_DIGCTL_SIZE 0x2000 - -#define HW_DIGCTL_CTRL 0x0 -#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 - -#define HW_DIGCTL_ARMCACHE 0x2B0 -#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 -#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 -#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 -#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 -#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 -#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 -#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 -#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 -#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 -#define BP_DIGCTL_ARMCACHE_VALID_SS 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h deleted file mode 100644 index 02851431677c..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dram.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * stmp378x: DRAM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000) -#define REGS_DRAM_PHYS 0x800E0000 -#define REGS_DRAM_SIZE 0x2000 - -#define HW_DRAM_CTL06 0x18 - -#define HW_DRAM_CTL08 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h deleted file mode 100644 index da25f7e397e5..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-dri.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * stmp378x: DRI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000) -#define REGS_DRI_PHYS 0x80074000 -#define REGS_DRI_SIZE 0x2000 - -#define HW_DRI_CTRL 0x0 -#define BM_DRI_CTRL_RUN 0x00000001 -#define BP_DRI_CTRL_RUN 0 -#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004 -#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008 -#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400 -#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800 -#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000 -#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000 -#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000 -#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 -#define BM_DRI_CTRL_CLKGATE 0x40000000 -#define BM_DRI_CTRL_SFTRST 0x80000000 - -#define HW_DRI_TIMING 0x10 -#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF -#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 -#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000 -#define BP_DRI_TIMING_PILOT_REP_RATE 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h deleted file mode 100644 index cc353bec331b..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * stmp378x: ECC8 register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) -#define REGS_ECC8_PHYS 0x80008000 -#define REGS_ECC8_SIZE 0x2000 - -#define HW_ECC8_CTRL 0x0 -#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_ECC8_CTRL_COMPLETE_IRQ 0 -#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 -#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 - -#define HW_ECC8_STATUS0 0x10 -#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_ECC8_STATUS0_CORRECTED 0x00000008 -#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 -#define BP_ECC8_STATUS0_STATUS_AUX 8 -#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_ECC8_STATUS0_COMPLETED_CE 16 - -#define HW_ECC8_STATUS1 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h deleted file mode 100644 index 98773fc33d7b..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * stmp378x: EMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000) -#define REGS_EMI_PHYS 0x80020000 -#define REGS_EMI_SIZE 0x2000 - -#define HW_EMI_STAT 0x10 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h deleted file mode 100644 index 2cc8bbe91687..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * stmp378x: GPMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000) -#define REGS_GPMI_PHYS 0x8000C000 -#define REGS_GPMI_SIZE 0x2000 - -#define HW_GPMI_CTRL0 0x0 -#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_GPMI_CTRL0_XFER_COUNT 0 -#define BM_GPMI_CTRL0_CS 0x00300000 -#define BP_GPMI_CTRL0_CS 20 -#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 -#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 -#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 -#define BP_GPMI_CTRL0_ADDRESS 17 -#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 -#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 -#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 -#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 -#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 -#define BP_GPMI_CTRL0_COMMAND_MODE 24 -#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 -#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 -#define BM_GPMI_CTRL0_RUN 0x20000000 -#define BM_GPMI_CTRL0_CLKGATE 0x40000000 -#define BM_GPMI_CTRL0_SFTRST 0x80000000 -#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF -#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 -#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 -#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 -#define BP_GPMI_ECCCTRL_ECC_CMD 13 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3 - -#define HW_GPMI_CTRL1 0x60 -#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 -#define BP_GPMI_CTRL1_GPMI_MODE 0 -#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 -#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 -#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 -#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 -#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 -#define BP_GPMI_CTRL1_RDN_DELAY 12 -#define BM_GPMI_CTRL1_BCH_MODE 0x00040000 - -#define HW_GPMI_TIMING0 0x70 -#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF -#define BP_GPMI_TIMING0_DATA_SETUP 0 -#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 -#define BP_GPMI_TIMING0_DATA_HOLD 8 -#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 -#define BP_GPMI_TIMING0_ADDRESS_SETUP 16 - -#define HW_GPMI_TIMING1 0x80 -#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 -#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h deleted file mode 100644 index 13a234c99433..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * stmp378x: I2C register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000) -#define REGS_I2C_PHYS 0x80058000 -#define REGS_I2C_SIZE 0x2000 - -#define HW_I2C_CTRL0 0x0 -#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_I2C_CTRL0_XFER_COUNT 0 -#define BM_I2C_CTRL0_DIRECTION 0x00010000 -#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 -#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 -#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 -#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 -#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 -#define BM_I2C_CTRL0_CLKGATE 0x40000000 -#define BM_I2C_CTRL0_SFTRST 0x80000000 - -#define HW_I2C_TIMING0 0x10 - -#define HW_I2C_TIMING1 0x20 - -#define HW_I2C_TIMING2 0x30 - -#define HW_I2C_CTRL1 0x40 -#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 -#define BP_I2C_CTRL1_SLAVE_IRQ 0 -#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 -#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 -#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 -#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 -#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 -#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 -#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 -#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 - -#define HW_I2C_VERSION 0x90 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h deleted file mode 100644 index f996e80f40e7..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * stmp378x: ICOLL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_ICOLL -#define _MACH_REGS_ICOLL - -#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) -#define REGS_ICOLL_PHYS 0x80000000 -#define REGS_ICOLL_SIZE 0x2000 - -#define HW_ICOLL_VECTOR 0x0 - -#define HW_ICOLL_LEVELACK 0x10 -#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F -#define BP_ICOLL_LEVELACK_IRQLEVELACK 0 - -#define HW_ICOLL_CTRL 0x20 -#define BM_ICOLL_CTRL_CLKGATE 0x40000000 -#define BM_ICOLL_CTRL_SFTRST 0x80000000 - -#define HW_ICOLL_STAT 0x70 - -#define HW_ICOLL_INTERRUPTn 0x120 - -#define HW_ICOLL_INTERRUPTn 0x120 -#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h deleted file mode 100644 index a5b4ef10fab8..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ir.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * stmp378x: IR register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000) -#define REGS_IR_PHYS 0x80078000 -#define REGS_IR_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h deleted file mode 100644 index 9cdbef4badc3..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * stmp378x: LCDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) -#define REGS_LCDIF_PHYS 0x80030000 -#define REGS_LCDIF_SIZE 0x2000 - -#define HW_LCDIF_CTRL 0x0 -#define BM_LCDIF_CTRL_RUN 0x00000001 -#define BP_LCDIF_CTRL_RUN 0 -#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 -#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 -#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 -#define BP_LCDIF_CTRL_WORD_LENGTH 8 -#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 -#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 -#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 -#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 -#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 -#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 -#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 -#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 -#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 -#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 -#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 -#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 -#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 -#define BM_LCDIF_CTRL_CLKGATE 0x40000000 -#define BM_LCDIF_CTRL_SFTRST 0x80000000 - -#define HW_LCDIF_CTRL1 0x10 -#define BM_LCDIF_CTRL1_RESET 0x00000001 -#define BP_LCDIF_CTRL1_RESET 0 -#define BM_LCDIF_CTRL1_MODE86 0x00000002 -#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 -#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 -#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 -#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 -#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 -#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 -#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 -#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 - -#define HW_LCDIF_TRANSFER_COUNT 0x20 -#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF -#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 -#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 -#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 - -#define HW_LCDIF_CUR_BUF 0x30 - -#define HW_LCDIF_NEXT_BUF 0x40 - -#define HW_LCDIF_TIMING 0x60 - -#define HW_LCDIF_VDCTRL0 0x70 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF -#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 -#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 -#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 -#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 -#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 -#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 -#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 -#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 - -#define HW_LCDIF_VDCTRL1 0x80 -#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF -#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 - -#define HW_LCDIF_VDCTRL2 0x90 -#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF -#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 -#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000 -#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24 - -#define HW_LCDIF_VDCTRL3 0xA0 -#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF -#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 -#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 -#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 - -#define HW_LCDIF_VDCTRL4 0xB0 -#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF -#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 - -#define HW_LCDIF_DVICTRL0 0xC0 -#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF -#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 -#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00 -#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 -#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000 -#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 - -#define HW_LCDIF_DVICTRL1 0xD0 -#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF -#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 -#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 -#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 -#define BP_LCDIF_DVICTRL1_F1_START_LINE 20 - -#define HW_LCDIF_DVICTRL2 0xE0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 -#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 -#define BP_LCDIF_DVICTRL2_F2_END_LINE 20 - -#define HW_LCDIF_DVICTRL3 0xF0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000 -#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 - -#define HW_LCDIF_DVICTRL4 0x100 -#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF -#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 -#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 -#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 -#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 -#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 -#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 -#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 - -#define HW_LCDIF_CSC_COEFF0 0x110 -#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 -#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 -#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 -#define BP_LCDIF_CSC_COEFF0_C0 16 - -#define HW_LCDIF_CSC_COEFF1 0x120 -#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF -#define BP_LCDIF_CSC_COEFF1_C1 0 -#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 -#define BP_LCDIF_CSC_COEFF1_C2 16 - -#define HW_LCDIF_CSC_COEFF2 0x130 -#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF -#define BP_LCDIF_CSC_COEFF2_C3 0 -#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 -#define BP_LCDIF_CSC_COEFF2_C4 16 - -#define HW_LCDIF_CSC_COEFF3 0x140 -#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF -#define BP_LCDIF_CSC_COEFF3_C5 0 -#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 -#define BP_LCDIF_CSC_COEFF3_C6 16 - -#define HW_LCDIF_CSC_COEFF4 0x150 -#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF -#define BP_LCDIF_CSC_COEFF4_C7 0 -#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 -#define BP_LCDIF_CSC_COEFF4_C8 16 - -#define HW_LCDIF_CSC_OFFSET 0x160 -#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF -#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 -#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 -#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 - -#define HW_LCDIF_CSC_LIMIT 0x170 -#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF -#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 -#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 -#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 -#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 -#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 -#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 -#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 - -#define HW_LCDIF_STAT 0x1D0 -#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h deleted file mode 100644 index cb8cb06f8277..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * stmp378x: LRADC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000) -#define REGS_LRADC_PHYS 0x80050000 -#define REGS_LRADC_SIZE 0x2000 - -#define HW_LRADC_CTRL0 0x0 -#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF -#define BP_LRADC_CTRL0_SCHEDULE 0 -#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 -#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 -#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 -#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 -#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 -#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 -#define BM_LRADC_CTRL0_CLKGATE 0x40000000 -#define BM_LRADC_CTRL0_SFTRST 0x80000000 - -#define HW_LRADC_CTRL1 0x10 -#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 -#define BP_LRADC_CTRL1_LRADC0_IRQ 0 -#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 -#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 -#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 -#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 - -#define HW_LRADC_CTRL2 0x20 -#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 -#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 -#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 -#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 -#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 -#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 - -#define HW_LRADC_CTRL3 0x30 -#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 -#define BP_LRADC_CTRL3_CYCLE_TIME 8 - -#define HW_LRADC_STATUS 0x40 -#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 -#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 - -#define HW_LRADC_CH0 (0x50 + 0 * 0x10) -#define HW_LRADC_CH1 (0x50 + 1 * 0x10) -#define HW_LRADC_CH2 (0x50 + 2 * 0x10) -#define HW_LRADC_CH3 (0x50 + 3 * 0x10) -#define HW_LRADC_CH4 (0x50 + 4 * 0x10) -#define HW_LRADC_CH5 (0x50 + 5 * 0x10) -#define HW_LRADC_CH6 (0x50 + 6 * 0x10) -#define HW_LRADC_CH7 (0x50 + 7 * 0x10) - -#define HW_LRADC_CHn 0x50 -#define BM_LRADC_CHn_VALUE 0x0003FFFF -#define BP_LRADC_CHn_VALUE 0 -#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 -#define BP_LRADC_CHn_NUM_SAMPLES 24 -#define BM_LRADC_CHn_ACCUMULATE 0x20000000 - -#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10) -#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10) -#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10) -#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10) - -#define HW_LRADC_DELAYn 0xD0 -#define BM_LRADC_DELAYn_DELAY 0x000007FF -#define BP_LRADC_DELAYn_DELAY 0 -#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 -#define BP_LRADC_DELAYn_LOOP_COUNT 11 -#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 -#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 -#define BM_LRADC_DELAYn_KICK 0x00100000 -#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 -#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 - -#define HW_LRADC_CTRL4 0x140 -#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 -#define BP_LRADC_CTRL4_LRADC6SELECT 24 -#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 -#define BP_LRADC_CTRL4_LRADC7SELECT 28 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h deleted file mode 100644 index f0af64d9937e..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * stmp378x: OCOTP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000) -#define REGS_OCOTP_PHYS 0x8002C000 -#define REGS_OCOTP_SIZE 0x2000 - -#define HW_OCOTP_CTRL 0x0 -#define BM_OCOTP_CTRL_BUSY 0x00000100 -#define BM_OCOTP_CTRL_ERROR 0x00000200 -#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 -#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 -#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 -#define BP_OCOTP_CTRL_WR_UNLOCK 16 - -#define HW_OCOTP_DATA 0x10 - -#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10) -#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10) -#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10) -#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10) - -#define HW_OCOTP_CUSTn 0x20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h deleted file mode 100644 index 50d90ea1b136..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * stmp378x: PINCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_PINCTRL -#define _MACH_REGS_PINCTRL - -#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) -#define REGS_PINCTRL_PHYS 0x80018000 -#define REGS_PINCTRL_SIZE 0x2000 - -#define HW_PINCTRL_MUXSEL0 0x100 -#define HW_PINCTRL_MUXSEL1 0x110 -#define HW_PINCTRL_MUXSEL2 0x120 -#define HW_PINCTRL_MUXSEL3 0x130 -#define HW_PINCTRL_MUXSEL4 0x140 -#define HW_PINCTRL_MUXSEL5 0x150 -#define HW_PINCTRL_MUXSEL6 0x160 -#define HW_PINCTRL_MUXSEL7 0x170 - -#define HW_PINCTRL_DRIVE0 0x200 -#define HW_PINCTRL_DRIVE1 0x210 -#define HW_PINCTRL_DRIVE2 0x220 -#define HW_PINCTRL_DRIVE3 0x230 -#define HW_PINCTRL_DRIVE4 0x240 -#define HW_PINCTRL_DRIVE5 0x250 -#define HW_PINCTRL_DRIVE6 0x260 -#define HW_PINCTRL_DRIVE7 0x270 -#define HW_PINCTRL_DRIVE8 0x280 -#define HW_PINCTRL_DRIVE9 0x290 -#define HW_PINCTRL_DRIVE10 0x2A0 -#define HW_PINCTRL_DRIVE11 0x2B0 -#define HW_PINCTRL_DRIVE12 0x2C0 -#define HW_PINCTRL_DRIVE13 0x2D0 -#define HW_PINCTRL_DRIVE14 0x2E0 - -#define HW_PINCTRL_PULL0 0x400 -#define HW_PINCTRL_PULL1 0x410 -#define HW_PINCTRL_PULL2 0x420 -#define HW_PINCTRL_PULL3 0x430 - -#define HW_PINCTRL_DOUT0 0x500 -#define HW_PINCTRL_DOUT1 0x510 -#define HW_PINCTRL_DOUT2 0x520 - -#define HW_PINCTRL_DIN0 0x600 -#define HW_PINCTRL_DIN1 0x610 -#define HW_PINCTRL_DIN2 0x620 - -#define HW_PINCTRL_DOE0 0x700 -#define HW_PINCTRL_DOE1 0x710 -#define HW_PINCTRL_DOE2 0x720 - -#define HW_PINCTRL_PIN2IRQ0 0x800 -#define HW_PINCTRL_PIN2IRQ1 0x810 -#define HW_PINCTRL_PIN2IRQ2 0x820 - -#define HW_PINCTRL_IRQEN0 0x900 -#define HW_PINCTRL_IRQEN1 0x910 -#define HW_PINCTRL_IRQEN2 0x920 - -#define HW_PINCTRL_IRQLEVEL0 0xA00 -#define HW_PINCTRL_IRQLEVEL1 0xA10 -#define HW_PINCTRL_IRQLEVEL2 0xA20 - -#define HW_PINCTRL_IRQPOL0 0xB00 -#define HW_PINCTRL_IRQPOL1 0xB10 -#define HW_PINCTRL_IRQPOL2 0xB20 - -#define HW_PINCTRL_IRQSTAT0 0xC00 -#define HW_PINCTRL_IRQSTAT1 0xC10 -#define HW_PINCTRL_IRQSTAT2 0xC20 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h deleted file mode 100644 index e454c830f076..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-power.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp378x: POWER register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_POWER -#define _MACH_REGS_POWER - -#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) -#define REGS_POWER_PHYS 0x80044000 -#define REGS_POWER_SIZE 0x2000 - -#define HW_POWER_CTRL 0x0 -#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 -#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 -#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 -#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 -#define BM_POWER_CTRL_CLKGATE 0x40000000 - -#define HW_POWER_5VCTRL 0x10 -#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 - -#define HW_POWER_MINPWR 0x20 - -#define HW_POWER_CHARGE 0x30 - -#define HW_POWER_VDDDCTRL 0x40 - -#define HW_POWER_VDDACTRL 0x50 - -#define HW_POWER_VDDIOCTRL 0x60 -#define BM_POWER_VDDIOCTRL_TRG 0x0000001F -#define BP_POWER_VDDIOCTRL_TRG 0 - -#define HW_POWER_STS 0xC0 -#define BM_POWER_STS_VBUSVALID 0x00000002 -#define BM_POWER_STS_BVALID 0x00000004 -#define BM_POWER_STS_AVALID 0x00000008 -#define BM_POWER_STS_DC_OK 0x00000200 - -#define HW_POWER_RESET 0x100 - -#define HW_POWER_DEBUG 0x110 -#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 -#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 -#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h deleted file mode 100644 index 0d0f9e56ec77..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * stmp378x: PWM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000) -#define REGS_PWM_PHYS 0x80064000 -#define REGS_PWM_SIZE 0x2000 - -#define HW_PWM_CTRL 0x0 -#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 -#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 - -#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20) -#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20) -#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20) -#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20) - -#define HW_PWM_ACTIVEn 0x10 -#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF -#define BP_PWM_ACTIVEn_ACTIVE 0 -#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 -#define BP_PWM_ACTIVEn_INACTIVE 16 - -#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20) -#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20) -#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20) -#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20) - -#define HW_PWM_PERIODn 0x20 -#define BM_PWM_PERIODn_PERIOD 0x0000FFFF -#define BP_PWM_PERIODn_PERIOD 0 -#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 -#define BP_PWM_PERIODn_ACTIVE_STATE 16 -#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 -#define BP_PWM_PERIODn_INACTIVE_STATE 18 -#define BM_PWM_PERIODn_CDIV 0x00700000 -#define BP_PWM_PERIODn_CDIV 20 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h deleted file mode 100644 index 54d297896de8..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * stmp378x: PXP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000) -#define REGS_PXP_PHYS 0x8002A000 -#define REGS_PXP_SIZE 0x2000 - -#define HW_PXP_CTRL 0x0 -#define BM_PXP_CTRL_ENABLE 0x00000001 -#define BP_PXP_CTRL_ENABLE 0 -#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 -#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0 -#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4 -#define BM_PXP_CTRL_ROTATE 0x00000300 -#define BP_PXP_CTRL_ROTATE 8 -#define BM_PXP_CTRL_HFLIP 0x00000400 -#define BM_PXP_CTRL_VFLIP 0x00000800 -#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 -#define BP_PXP_CTRL_S0_FORMAT 12 -#define BM_PXP_CTRL_SCALE 0x00040000 -#define BM_PXP_CTRL_CROP 0x00080000 - -#define HW_PXP_STAT 0x10 -#define BM_PXP_STAT_IRQ 0x00000001 -#define BP_PXP_STAT_IRQ 0 - -#define HW_PXP_RGBBUF 0x20 - -#define HW_PXP_RGBSIZE 0x40 -#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF -#define BP_PXP_RGBSIZE_HEIGHT 0 -#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000 -#define BP_PXP_RGBSIZE_WIDTH 12 - -#define HW_PXP_S0BUF 0x50 - -#define HW_PXP_S0UBUF 0x60 - -#define HW_PXP_S0VBUF 0x70 - -#define HW_PXP_S0PARAM 0x80 -#define BM_PXP_S0PARAM_HEIGHT 0x000000FF -#define BP_PXP_S0PARAM_HEIGHT 0 -#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 -#define BP_PXP_S0PARAM_WIDTH 8 -#define BM_PXP_S0PARAM_YBASE 0x00FF0000 -#define BP_PXP_S0PARAM_YBASE 16 -#define BM_PXP_S0PARAM_XBASE 0xFF000000 -#define BP_PXP_S0PARAM_XBASE 24 - -#define HW_PXP_S0BACKGROUND 0x90 - -#define HW_PXP_S0CROP 0xA0 -#define BM_PXP_S0CROP_HEIGHT 0x000000FF -#define BP_PXP_S0CROP_HEIGHT 0 -#define BM_PXP_S0CROP_WIDTH 0x0000FF00 -#define BP_PXP_S0CROP_WIDTH 8 -#define BM_PXP_S0CROP_YBASE 0x00FF0000 -#define BP_PXP_S0CROP_YBASE 16 -#define BM_PXP_S0CROP_XBASE 0xFF000000 -#define BP_PXP_S0CROP_XBASE 24 - -#define HW_PXP_S0SCALE 0xB0 -#define BM_PXP_S0SCALE_XSCALE 0x00003FFF -#define BP_PXP_S0SCALE_XSCALE 0 -#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000 -#define BP_PXP_S0SCALE_YSCALE 16 - -#define HW_PXP_CSCCOEFF0 0xD0 - -#define HW_PXP_CSCCOEFF1 0xE0 - -#define HW_PXP_CSCCOEFF2 0xF0 - -#define HW_PXP_S0COLORKEYLOW 0x180 - -#define HW_PXP_S0COLORKEYHIGH 0x190 - -#define HW_PXP_OL0 (0x200 + 0 * 0x40) -#define HW_PXP_OL1 (0x200 + 1 * 0x40) -#define HW_PXP_OL2 (0x200 + 2 * 0x40) -#define HW_PXP_OL3 (0x200 + 3 * 0x40) -#define HW_PXP_OL4 (0x200 + 4 * 0x40) -#define HW_PXP_OL5 (0x200 + 5 * 0x40) -#define HW_PXP_OL6 (0x200 + 6 * 0x40) -#define HW_PXP_OL7 (0x200 + 7 * 0x40) - -#define HW_PXP_OLn 0x200 - -#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40) -#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40) -#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40) -#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40) -#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40) -#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40) -#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40) -#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40) - -#define HW_PXP_OLnSIZE 0x210 -#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF -#define BP_PXP_OLnSIZE_HEIGHT 0 -#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 -#define BP_PXP_OLnSIZE_WIDTH 8 - -#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40) -#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40) -#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40) -#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40) -#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40) -#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40) -#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40) -#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40) - -#define HW_PXP_OLnPARAM 0x220 -#define BM_PXP_OLnPARAM_ENABLE 0x00000001 -#define BP_PXP_OLnPARAM_ENABLE 0 -#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 -#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 -#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 -#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 -#define BP_PXP_OLnPARAM_FORMAT 4 -#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 -#define BP_PXP_OLnPARAM_ALPHA 8 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h deleted file mode 100644 index b8dbd6742d98..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * stmp378x: RTC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000) -#define REGS_RTC_PHYS 0x8005C000 -#define REGS_RTC_SIZE 0x2000 - -#define HW_RTC_CTRL 0x0 -#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 -#define BP_RTC_CTRL_ALARM_IRQ_EN 0 -#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 -#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 -#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 -#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 - -#define HW_RTC_STAT 0x10 -#define BM_RTC_STAT_NEW_REGS 0x0000FF00 -#define BP_RTC_STAT_NEW_REGS 8 -#define BM_RTC_STAT_STALE_REGS 0x00FF0000 -#define BP_RTC_STAT_STALE_REGS 16 -#define BM_RTC_STAT_RTC_PRESENT 0x80000000 - -#define HW_RTC_SECONDS 0x30 - -#define HW_RTC_ALARM 0x40 - -#define HW_RTC_WATCHDOG 0x50 - -#define HW_RTC_PERSISTENT0 0x60 -#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 -#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 -#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 -#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 -#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 -#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 -#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 - -#define HW_RTC_PERSISTENT1 0x70 -#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF -#define BP_RTC_PERSISTENT1_GENERAL 0 - -#define HW_RTC_VERSION 0xD0 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h deleted file mode 100644 index 6df41762c2a3..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * stmp378x: SAIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SAIF_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h deleted file mode 100644 index 801539848c28..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * stmp378x: SPDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000) -#define REGS_SPDIF_PHYS 0x80054000 -#define REGS_SPDIF_SIZE 0x2000 - -#define HW_SPDIF_CTRL 0x0 -#define BM_SPDIF_CTRL_RUN 0x00000001 -#define BP_SPDIF_CTRL_RUN 0 -#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010 -#define BM_SPDIF_CTRL_CLKGATE 0x40000000 -#define BM_SPDIF_CTRL_SFTRST 0x80000000 - -#define HW_SPDIF_STAT 0x10 - -#define HW_SPDIF_FRAMECTRL 0x20 - -#define HW_SPDIF_SRR 0x30 -#define BM_SPDIF_SRR_RATE 0x000FFFFF -#define BP_SPDIF_SRR_RATE 0 -#define BM_SPDIF_SRR_BASEMULT 0x70000000 -#define BP_SPDIF_SRR_BASEMULT 28 - -#define HW_SPDIF_DEBUG 0x40 - -#define HW_SPDIF_DATA 0x50 - -#define HW_SPDIF_VERSION 0x60 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h deleted file mode 100644 index 28aacf0f58ed..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * stmp378x: SSP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000) -#define REGS_SSP1_PHYS 0x80010000 -#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000) -#define REGS_SSP2_PHYS 0x80034000 -#define REGS_SSP_SIZE 0x2000 - -#define HW_SSP_CTRL0 0x0 -#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_SSP_CTRL0_XFER_COUNT 0 -#define BM_SSP_CTRL0_ENABLE 0x00010000 -#define BM_SSP_CTRL0_GET_RESP 0x00020000 -#define BM_SSP_CTRL0_LONG_RESP 0x00080000 -#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 -#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 -#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 -#define BP_SSP_CTRL0_BUS_WIDTH 22 -#define BM_SSP_CTRL0_DATA_XFER 0x01000000 -#define BM_SSP_CTRL0_READ 0x02000000 -#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 -#define BM_SSP_CTRL0_LOCK_CS 0x08000000 -#define BM_SSP_CTRL0_RUN 0x20000000 -#define BM_SSP_CTRL0_CLKGATE 0x40000000 -#define BM_SSP_CTRL0_SFTRST 0x80000000 - -#define HW_SSP_CMD0 0x10 -#define BM_SSP_CMD0_CMD 0x000000FF -#define BP_SSP_CMD0_CMD 0 -#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 -#define BP_SSP_CMD0_BLOCK_COUNT 8 -#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 -#define BP_SSP_CMD0_BLOCK_SIZE 16 -#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 -#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF -#define BP_SSP_CMD1_CMD_ARG 0 - -#define HW_SSP_TIMING 0x50 -#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF -#define BP_SSP_TIMING_CLOCK_RATE 0 -#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 -#define BP_SSP_TIMING_CLOCK_DIVIDE 8 -#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 -#define BP_SSP_TIMING_TIMEOUT 16 - -#define HW_SSP_CTRL1 0x60 -#define BM_SSP_CTRL1_SSP_MODE 0x0000000F -#define BP_SSP_CTRL1_SSP_MODE 0 -#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 -#define BP_SSP_CTRL1_WORD_LENGTH 4 -#define BM_SSP_CTRL1_POLARITY 0x00000200 -#define BM_SSP_CTRL1_PHASE 0x00000400 -#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 -#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 -#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 -#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 - -#define HW_SSP_DATA 0x70 - -#define HW_SSP_SDRESP0 0x80 - -#define HW_SSP_SDRESP1 0x90 - -#define HW_SSP_SDRESP2 0xA0 - -#define HW_SSP_SDRESP3 0xB0 - -#define HW_SSP_STATUS 0xC0 -#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 -#define BM_SSP_STATUS_TIMEOUT 0x00001000 -#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 -#define BM_SSP_STATUS_RESP_ERR 0x00008000 -#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 -#define BM_SSP_STATUS_CARD_DETECT 0x10000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h deleted file mode 100644 index 08343a8b5566..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * stmp378x: SYDMA register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000) -#define REGS_SYDMA_PHYS 0x80026000 -#define REGS_SYDMA_SIZE 0x2000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h deleted file mode 100644 index b5527957c67f..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * stmp378x: TIMROT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_TIMROT -#define _MACH_REGS_TIMROT - -#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) -#define REGS_TIMROT_PHYS 0x80068000 -#define REGS_TIMROT_SIZE 0x2000 - -#define HW_TIMROT_ROTCTRL 0x0 -#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 -#define BP_TIMROT_ROTCTRL_SELECT_A 0 -#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 -#define BP_TIMROT_ROTCTRL_SELECT_B 4 -#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 -#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 -#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 -#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 -#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 -#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 -#define BP_TIMROT_ROTCTRL_DIVIDER 16 -#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 -#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 -#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 - -#define HW_TIMROT_ROTCOUNT 0x10 -#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF -#define BP_TIMROT_ROTCOUNT_UPDOWN 0 - -#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20) -#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20) -#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20) - -#define HW_TIMROT_TIMCTRLn 0x20 -#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F -#define BP_TIMROT_TIMCTRLn_SELECT 0 -#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 -#define BP_TIMROT_TIMCTRLn_PRESCALE 4 -#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 -#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 -#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 -#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 - -#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20) -#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20) -#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20) - -#define HW_TIMROT_TIMCOUNTn 0x30 - -#endif diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h deleted file mode 100644 index 7f895cb34350..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * stmp378x: TVENC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000) -#define REGS_TVENC_PHYS 0x80038000 -#define REGS_TVENC_SIZE 0x2000 - -#define HW_TVENC_CTRL 0x0 -#define BM_TVENC_CTRL_CLKGATE 0x40000000 -#define BM_TVENC_CTRL_SFTRST 0x80000000 - -#define HW_TVENC_CONFIG 0x10 -#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007 -#define BP_TVENC_CONFIG_ENCD_MODE 0 -#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070 -#define BP_TVENC_CONFIG_SYNC_MODE 4 -#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200 -#define BM_TVENC_CONFIG_CGAIN 0x0000C000 -#define BP_TVENC_CONFIG_CGAIN 14 -#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000 -#define BP_TVENC_CONFIG_YGAIN_SEL 16 -#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000 - -#define HW_TVENC_SYNCOFFSET 0x30 - -#define HW_TVENC_COLORSUB0 0xC0 - -#define HW_TVENC_COLORBURST 0x140 -#define BM_TVENC_COLORBURST_PBA 0x00FF0000 -#define BP_TVENC_COLORBURST_PBA 16 -#define BM_TVENC_COLORBURST_NBA 0xFF000000 -#define BP_TVENC_COLORBURST_NBA 24 - -#define HW_TVENC_MACROVISION0 0x150 - -#define HW_TVENC_MACROVISION1 0x160 - -#define HW_TVENC_MACROVISION2 0x170 - -#define HW_TVENC_MACROVISION3 0x180 - -#define HW_TVENC_MACROVISION4 0x190 - -#define HW_TVENC_DACCTRL 0x1A0 -#define BM_TVENC_DACCTRL_RVAL 0x00000070 -#define BP_TVENC_DACCTRL_RVAL 4 -#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100 -#define BM_TVENC_DACCTRL_PWRUP1 0x00001000 -#define BM_TVENC_DACCTRL_GAINUP 0x00040000 -#define BM_TVENC_DACCTRL_GAINDN 0x00080000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h deleted file mode 100644 index a251e68bb3a1..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * stmp378x: UARTAPP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000) -#define REGS_UARTAPP1_PHYS 0x8006C000 -#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000) -#define REGS_UARTAPP2_PHYS 0x8006E000 -#define REGS_UARTAPP_SIZE 0x2000 - -#define HW_UARTAPP_CTRL0 0x0 -#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL0_XFER_COUNT 0 -#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 -#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 -#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 -#define BM_UARTAPP_CTRL0_RUN 0x20000000 -#define BM_UARTAPP_CTRL0_SFTRST 0x80000000 -#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL1_XFER_COUNT 0 -#define BM_UARTAPP_CTRL1_RUN 0x10000000 - -#define HW_UARTAPP_CTRL2 0x20 -#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 -#define BP_UARTAPP_CTRL2_UARTEN 0 -#define BM_UARTAPP_CTRL2_TXE 0x00000100 -#define BM_UARTAPP_CTRL2_RXE 0x00000200 -#define BM_UARTAPP_CTRL2_RTS 0x00000800 -#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 -#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 -#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 -#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 -#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000 - -#define HW_UARTAPP_LINECTRL 0x30 -#define BM_UARTAPP_LINECTRL_BRK 0x00000001 -#define BP_UARTAPP_LINECTRL_BRK 0 -#define BM_UARTAPP_LINECTRL_PEN 0x00000002 -#define BM_UARTAPP_LINECTRL_EPS 0x00000004 -#define BM_UARTAPP_LINECTRL_STP2 0x00000008 -#define BM_UARTAPP_LINECTRL_FEN 0x00000010 -#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 -#define BP_UARTAPP_LINECTRL_WLEN 5 -#define BM_UARTAPP_LINECTRL_SPS 0x00000080 -#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 -#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 -#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 -#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 - -#define HW_UARTAPP_INTR 0x50 -#define BM_UARTAPP_INTR_CTSMIS 0x00000002 -#define BM_UARTAPP_INTR_RTIS 0x00000040 -#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 -#define BM_UARTAPP_INTR_RXIEN 0x00100000 -#define BM_UARTAPP_INTR_RTIEN 0x00400000 - -#define HW_UARTAPP_DATA 0x60 - -#define HW_UARTAPP_STAT 0x70 -#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF -#define BP_UARTAPP_STAT_RXCOUNT 0 -#define BM_UARTAPP_STAT_FERR 0x00010000 -#define BM_UARTAPP_STAT_PERR 0x00020000 -#define BM_UARTAPP_STAT_BERR 0x00040000 -#define BM_UARTAPP_STAT_OERR 0x00080000 -#define BM_UARTAPP_STAT_RXFE 0x01000000 -#define BM_UARTAPP_STAT_TXFF 0x02000000 -#define BM_UARTAPP_STAT_TXFE 0x08000000 -#define BM_UARTAPP_STAT_CTS 0x10000000 - -#define HW_UARTAPP_VERSION 0x90 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h deleted file mode 100644 index b810deb552a9..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * stmp378x: UARTDBG register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000) -#define REGS_UARTDBG_PHYS 0x80070000 -#define REGS_UARTDBG_SIZE 0x2000 - -#define HW_UARTDBGDR 0x00000000 -#define BP_UARTDBGDR_UNAVAILABLE 16 -#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) -#define BP_UARTDBGDR_RESERVED 12 -#define BM_UARTDBGDR_RESERVED 0x0000F000 -#define BF_UARTDBGDR_RESERVED(v) \ - (((v) << 12) & BM_UARTDBGDR_RESERVED) -#define BM_UARTDBGDR_OE 0x00000800 -#define BM_UARTDBGDR_BE 0x00000400 -#define BM_UARTDBGDR_PE 0x00000200 -#define BM_UARTDBGDR_FE 0x00000100 -#define BP_UARTDBGDR_DATA 0 -#define BM_UARTDBGDR_DATA 0x000000FF -#define BF_UARTDBGDR_DATA(v) \ - (((v) << 0) & BM_UARTDBGDR_DATA) -#define HW_UARTDBGRSR_ECR 0x00000004 -#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 -#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) -#define BP_UARTDBGRSR_ECR_EC 4 -#define BM_UARTDBGRSR_ECR_EC 0x000000F0 -#define BF_UARTDBGRSR_ECR_EC(v) \ - (((v) << 4) & BM_UARTDBGRSR_ECR_EC) -#define BM_UARTDBGRSR_ECR_OE 0x00000008 -#define BM_UARTDBGRSR_ECR_BE 0x00000004 -#define BM_UARTDBGRSR_ECR_PE 0x00000002 -#define BM_UARTDBGRSR_ECR_FE 0x00000001 -#define HW_UARTDBGFR 0x00000018 -#define BP_UARTDBGFR_UNAVAILABLE 16 -#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGFR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) -#define BP_UARTDBGFR_RESERVED 9 -#define BM_UARTDBGFR_RESERVED 0x0000FE00 -#define BF_UARTDBGFR_RESERVED(v) \ - (((v) << 9) & BM_UARTDBGFR_RESERVED) -#define BM_UARTDBGFR_RI 0x00000100 -#define BM_UARTDBGFR_TXFE 0x00000080 -#define BM_UARTDBGFR_RXFF 0x00000040 -#define BM_UARTDBGFR_TXFF 0x00000020 -#define BM_UARTDBGFR_RXFE 0x00000010 -#define BM_UARTDBGFR_BUSY 0x00000008 -#define BM_UARTDBGFR_DCD 0x00000004 -#define BM_UARTDBGFR_DSR 0x00000002 -#define BM_UARTDBGFR_CTS 0x00000001 -#define HW_UARTDBGILPR 0x00000020 -#define BP_UARTDBGILPR_UNAVAILABLE 8 -#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGILPR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) -#define BP_UARTDBGILPR_ILPDVSR 0 -#define BM_UARTDBGILPR_ILPDVSR 0x000000FF -#define BF_UARTDBGILPR_ILPDVSR(v) \ - (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) -#define HW_UARTDBGIBRD 0x00000024 -#define BP_UARTDBGIBRD_UNAVAILABLE 16 -#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIBRD_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) -#define BP_UARTDBGIBRD_BAUD_DIVINT 0 -#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF -#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ - (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) -#define HW_UARTDBGFBRD 0x00000028 -#define BP_UARTDBGFBRD_UNAVAILABLE 8 -#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGFBRD_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) -#define BP_UARTDBGFBRD_RESERVED 6 -#define BM_UARTDBGFBRD_RESERVED 0x000000C0 -#define BF_UARTDBGFBRD_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGFBRD_RESERVED) -#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 -#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F -#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ - (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) -#define HW_UARTDBGLCR_H 0x0000002c -#define BP_UARTDBGLCR_H_UNAVAILABLE 16 -#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) -#define BP_UARTDBGLCR_H_RESERVED 8 -#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 -#define BF_UARTDBGLCR_H_RESERVED(v) \ - (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) -#define BM_UARTDBGLCR_H_SPS 0x00000080 -#define BP_UARTDBGLCR_H_WLEN 5 -#define BM_UARTDBGLCR_H_WLEN 0x00000060 -#define BF_UARTDBGLCR_H_WLEN(v) \ - (((v) << 5) & BM_UARTDBGLCR_H_WLEN) -#define BM_UARTDBGLCR_H_FEN 0x00000010 -#define BM_UARTDBGLCR_H_STP2 0x00000008 -#define BM_UARTDBGLCR_H_EPS 0x00000004 -#define BM_UARTDBGLCR_H_PEN 0x00000002 -#define BM_UARTDBGLCR_H_BRK 0x00000001 -#define HW_UARTDBGCR 0x00000030 -#define BP_UARTDBGCR_UNAVAILABLE 16 -#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGCR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) -#define BM_UARTDBGCR_CTSEN 0x00008000 -#define BM_UARTDBGCR_RTSEN 0x00004000 -#define BM_UARTDBGCR_OUT2 0x00002000 -#define BM_UARTDBGCR_OUT1 0x00001000 -#define BM_UARTDBGCR_RTS 0x00000800 -#define BM_UARTDBGCR_DTR 0x00000400 -#define BM_UARTDBGCR_RXE 0x00000200 -#define BM_UARTDBGCR_TXE 0x00000100 -#define BM_UARTDBGCR_LBE 0x00000080 -#define BP_UARTDBGCR_RESERVED 3 -#define BM_UARTDBGCR_RESERVED 0x00000078 -#define BF_UARTDBGCR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGCR_RESERVED) -#define BM_UARTDBGCR_SIRLP 0x00000004 -#define BM_UARTDBGCR_SIREN 0x00000002 -#define BM_UARTDBGCR_UARTEN 0x00000001 -#define HW_UARTDBGIFLS 0x00000034 -#define BP_UARTDBGIFLS_UNAVAILABLE 16 -#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIFLS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) -#define BP_UARTDBGIFLS_RESERVED 6 -#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 -#define BF_UARTDBGIFLS_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGIFLS_RESERVED) -#define BP_UARTDBGIFLS_RXIFLSEL 3 -#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 -#define BF_UARTDBGIFLS_RXIFLSEL(v) \ - (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) -#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 -#define BP_UARTDBGIFLS_TXIFLSEL 0 -#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 -#define BF_UARTDBGIFLS_TXIFLSEL(v) \ - (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) -#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 -#define HW_UARTDBGIMSC 0x00000038 -#define BP_UARTDBGIMSC_UNAVAILABLE 16 -#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIMSC_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) -#define BP_UARTDBGIMSC_RESERVED 11 -#define BM_UARTDBGIMSC_RESERVED 0x0000F800 -#define BF_UARTDBGIMSC_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGIMSC_RESERVED) -#define BM_UARTDBGIMSC_OEIM 0x00000400 -#define BM_UARTDBGIMSC_BEIM 0x00000200 -#define BM_UARTDBGIMSC_PEIM 0x00000100 -#define BM_UARTDBGIMSC_FEIM 0x00000080 -#define BM_UARTDBGIMSC_RTIM 0x00000040 -#define BM_UARTDBGIMSC_TXIM 0x00000020 -#define BM_UARTDBGIMSC_RXIM 0x00000010 -#define BM_UARTDBGIMSC_DSRMIM 0x00000008 -#define BM_UARTDBGIMSC_DCDMIM 0x00000004 -#define BM_UARTDBGIMSC_CTSMIM 0x00000002 -#define BM_UARTDBGIMSC_RIMIM 0x00000001 -#define HW_UARTDBGRIS 0x0000003c -#define BP_UARTDBGRIS_UNAVAILABLE 16 -#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGRIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) -#define BP_UARTDBGRIS_RESERVED 11 -#define BM_UARTDBGRIS_RESERVED 0x0000F800 -#define BF_UARTDBGRIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGRIS_RESERVED) -#define BM_UARTDBGRIS_OERIS 0x00000400 -#define BM_UARTDBGRIS_BERIS 0x00000200 -#define BM_UARTDBGRIS_PERIS 0x00000100 -#define BM_UARTDBGRIS_FERIS 0x00000080 -#define BM_UARTDBGRIS_RTRIS 0x00000040 -#define BM_UARTDBGRIS_TXRIS 0x00000020 -#define BM_UARTDBGRIS_RXRIS 0x00000010 -#define BM_UARTDBGRIS_DSRRMIS 0x00000008 -#define BM_UARTDBGRIS_DCDRMIS 0x00000004 -#define BM_UARTDBGRIS_CTSRMIS 0x00000002 -#define BM_UARTDBGRIS_RIRMIS 0x00000001 -#define HW_UARTDBGMIS 0x00000040 -#define BP_UARTDBGMIS_UNAVAILABLE 16 -#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGMIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) -#define BP_UARTDBGMIS_RESERVED 11 -#define BM_UARTDBGMIS_RESERVED 0x0000F800 -#define BF_UARTDBGMIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGMIS_RESERVED) -#define BM_UARTDBGMIS_OEMIS 0x00000400 -#define BM_UARTDBGMIS_BEMIS 0x00000200 -#define BM_UARTDBGMIS_PEMIS 0x00000100 -#define BM_UARTDBGMIS_FEMIS 0x00000080 -#define BM_UARTDBGMIS_RTMIS 0x00000040 -#define BM_UARTDBGMIS_TXMIS 0x00000020 -#define BM_UARTDBGMIS_RXMIS 0x00000010 -#define BM_UARTDBGMIS_DSRMMIS 0x00000008 -#define BM_UARTDBGMIS_DCDMMIS 0x00000004 -#define BM_UARTDBGMIS_CTSMMIS 0x00000002 -#define BM_UARTDBGMIS_RIMMIS 0x00000001 -#define HW_UARTDBGICR 0x00000044 -#define BP_UARTDBGICR_UNAVAILABLE 16 -#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGICR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) -#define BP_UARTDBGICR_RESERVED 11 -#define BM_UARTDBGICR_RESERVED 0x0000F800 -#define BF_UARTDBGICR_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGICR_RESERVED) -#define BM_UARTDBGICR_OEIC 0x00000400 -#define BM_UARTDBGICR_BEIC 0x00000200 -#define BM_UARTDBGICR_PEIC 0x00000100 -#define BM_UARTDBGICR_FEIC 0x00000080 -#define BM_UARTDBGICR_RTIC 0x00000040 -#define BM_UARTDBGICR_TXIC 0x00000020 -#define BM_UARTDBGICR_RXIC 0x00000010 -#define BM_UARTDBGICR_DSRMIC 0x00000008 -#define BM_UARTDBGICR_DCDMIC 0x00000004 -#define BM_UARTDBGICR_CTSMIC 0x00000002 -#define BM_UARTDBGICR_RIMIC 0x00000001 -#define HW_UARTDBGDMACR 0x00000048 -#define BP_UARTDBGDMACR_UNAVAILABLE 16 -#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDMACR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) -#define BP_UARTDBGDMACR_RESERVED 3 -#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 -#define BF_UARTDBGDMACR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGDMACR_RESERVED) -#define BM_UARTDBGDMACR_DMAONERR 0x00000004 -#define BM_UARTDBGDMACR_TXDMAE 0x00000002 -#define BM_UARTDBGDMACR_RXDMAE 0x00000001 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h deleted file mode 100644 index 25112c1aa608..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * stmp378x: USBCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTRL_PHYS 0x80080000 -#define REGS_USBCTRL_SIZE 0x2000 - -#define HW_USBCTRL_USBCMD 0x140 -#define BM_USBCTRL_USBCMD_RS 0x00000001 -#define BP_USBCTRL_USBCMD_RS 0 -#define BM_USBCTRL_USBCMD_RST 0x00000002 - -#define HW_USBCTRL_USBINTR 0x148 -#define BM_USBCTRL_USBINTR_UE 0x00000001 -#define BP_USBCTRL_USBINTR_UE 0 - -#define HW_USBCTRL_PORTSC1 0x184 -#define BM_USBCTRL_PORTSC1_PHCD 0x00800000 - -#define HW_USBCTRL_OTGSC 0x1A4 -#define BM_USBCTRL_OTGSC_ID 0x00000100 -#define BM_USBCTRL_OTGSC_IDIS 0x00010000 -#define BM_USBCTRL_OTGSC_IDIE 0x01000000 diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h deleted file mode 100644 index 11f3b732dc92..000000000000 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp378x: USBPHY register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000) -#define REGS_USBPHY_PHYS 0x8007C000 -#define REGS_USBPHY_SIZE 0x2000 - -#define HW_USBPHY_PWD 0x0 - -#define HW_USBPHY_CTRL 0x30 -#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 -#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 -#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 -#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 -#define BM_USBPHY_CTRL_CLKGATE 0x40000000 -#define BM_USBPHY_CTRL_SFTRST 0x80000000 - -#define HW_USBPHY_STATUS 0x40 -#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 -#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c deleted file mode 100644 index c2f9fe04c112..000000000000 --- a/arch/arm/mach-stmp378x/stmp378x.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Freescale STMP378X platform support - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/irq.h> -#include <linux/dma-mapping.h> - -#include <asm/dma.h> -#include <asm/setup.h> -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> - -#include <mach/pins.h> -#include <mach/pinmux.h> -#include <mach/dma.h> -#include <mach/hardware.h> -#include <mach/system.h> -#include <mach/platform.h> -#include <mach/stmp3xxx.h> -#include <mach/regs-icoll.h> -#include <mach/regs-apbh.h> -#include <mach/regs-apbx.h> -#include <mach/regs-pxp.h> -#include <mach/regs-i2c.h> - -#include "stmp378x.h" -/* - * IRQ handling - */ -static void stmp378x_ack_irq(struct irq_data *d) -{ - /* Tell ICOLL to release IRQ line */ - __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR); - - /* ACK current interrupt */ - __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */, - REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); - - /* Barrier */ - (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); -} - -static void stmp378x_mask_irq(struct irq_data *d) -{ - /* IRQ disable */ - stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE, - REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10); -} - -static void stmp378x_unmask_irq(struct irq_data *d) -{ - /* IRQ enable */ - stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE, - REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10); -} - -static struct irq_chip stmp378x_chip = { - .irq_ack = stmp378x_ack_irq, - .irq_mask = stmp378x_mask_irq, - .irq_unmask = stmp378x_unmask_irq, -}; - -void __init stmp378x_init_irq(void) -{ - stmp3xxx_init_irq(&stmp378x_chip); -} - -/* - * DMA interrupt handling - */ -void stmp3xxx_arch_dma_enable_interrupt(int channel) -{ - void __iomem *c1, *c2; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c1 = REGS_APBH_BASE + HW_APBH_CTRL1; - c2 = REGS_APBH_BASE + HW_APBH_CTRL2; - break; - - case STMP3XXX_BUS_APBX: - c1 = REGS_APBX_BASE + HW_APBX_CTRL1; - c2 = REGS_APBX_BASE + HW_APBX_CTRL2; - break; - - default: - return; - } - stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1); - stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2); -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); - -void stmp3xxx_arch_dma_clear_interrupt(int channel) -{ - void __iomem *c1, *c2; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c1 = REGS_APBH_BASE + HW_APBH_CTRL1; - c2 = REGS_APBH_BASE + HW_APBH_CTRL2; - break; - - case STMP3XXX_BUS_APBX: - c1 = REGS_APBX_BASE + HW_APBX_CTRL1; - c2 = REGS_APBX_BASE + HW_APBX_CTRL2; - break; - - default: - return; - } - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1); - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2); -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); - -int stmp3xxx_arch_dma_is_interrupt(int channel) -{ - int r = 0; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - - case STMP3XXX_BUS_APBX: - r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - } - return r; -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); - -void stmp3xxx_arch_dma_reset_channel(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - void __iomem *c0; - u32 mask; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c0 = REGS_APBH_BASE + HW_APBH_CTRL0; - mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL; - break; - case STMP3XXX_BUS_APBX: - c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL; - mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL; - break; - default: - return; - } - - /* Reset channel and wait for it to complete */ - stmp3xxx_setl(mask, c0); - while (__raw_readl(c0) & mask) - cpu_relax(); -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); - -void stmp3xxx_arch_dma_freeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - u32 mask = 1 << chbit; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze); - -void stmp3xxx_arch_dma_unfreeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - u32 mask = 1 << chbit; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze); - -/* - * The registers are all very closely mapped, so we might as well map them all - * with a single mapping - * - * Logical Physical - * f0000000 80000000 On-chip registers - * f1000000 00000000 32k on-chip SRAM - */ - -static struct map_desc stmp378x_io_desc[] __initdata = { - { - .virtual = (u32)STMP3XXX_REGS_BASE, - .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE), - .length = STMP3XXX_REGS_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (u32)STMP3XXX_OCRAM_BASE, - .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE), - .length = STMP3XXX_OCRAM_SIZE, - .type = MT_DEVICE, - }, -}; - - -static u64 common_dmamask = DMA_BIT_MASK(32); - -/* - * devices that are present only on stmp378x, not on all 3xxx boards: - * PxP - * I2C - */ -static struct resource pxp_resource[] = { - { - .flags = IORESOURCE_MEM, - .start = REGS_PXP_PHYS, - .end = REGS_PXP_PHYS + REGS_PXP_SIZE, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_PXP, - .end = IRQ_PXP, - }, -}; - -struct platform_device stmp378x_pxp = { - .name = "stmp3xxx-pxp", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(pxp_resource), - .resource = pxp_resource, -}; - -static struct resource i2c_resources[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_I2C_ERROR, - .end = IRQ_I2C_ERROR, - }, { - .flags = IORESOURCE_MEM, - .start = REGS_I2C_PHYS, - .end = REGS_I2C_PHYS + REGS_I2C_SIZE, - }, { - .flags = IORESOURCE_DMA, - .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX), - .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX), - }, -}; - -struct platform_device stmp378x_i2c = { - .name = "i2c_stmp3xxx", - .id = 0, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = i2c_resources, - .num_resources = ARRAY_SIZE(i2c_resources), -}; - -void __init stmp378x_map_io(void) -{ - iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc)); -} diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h deleted file mode 100644 index 0dc15b3c891f..000000000000 --- a/arch/arm/mach-stmp378x/stmp378x.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X internal functions and data declarations - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __MACH_STMP378X_H -#define __MACH_STMP378X_H - -void stmp378x_map_io(void); -void stmp378x_init_irq(void); - -extern struct platform_device stmp378x_pxp, stmp378x_i2c; -#endif /* __MACH_STMP378X_COMMON_H */ diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c deleted file mode 100644 index 06158848afd9..000000000000 --- a/arch/arm/mach-stmp378x/stmp378x_devb.c +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Freescale STMP378X development board support - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/spi/spi.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/pins.h> -#include <mach/pinmux.h> -#include <mach/platform.h> -#include <mach/stmp3xxx.h> -#include <mach/mmc.h> -#include <mach/gpmi.h> - -#include "stmp378x.h" - -static struct platform_device *devices[] = { - &stmp3xxx_dbguart, - &stmp3xxx_appuart, - &stmp3xxx_watchdog, - &stmp3xxx_touchscreen, - &stmp3xxx_rtc, - &stmp3xxx_keyboard, - &stmp3xxx_framebuffer, - &stmp3xxx_backlight, - &stmp3xxx_rotdec, - &stmp3xxx_persistent, - &stmp3xxx_dcp_bootstream, - &stmp3xxx_dcp, - &stmp3xxx_battery, - &stmp378x_pxp, - &stmp378x_i2c, -}; - -static struct pin_desc i2c_pins_desc[] = { - { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, -}; - -static struct pin_group i2c_pins = { - .pins = i2c_pins_desc, - .nr_pins = ARRAY_SIZE(i2c_pins_desc), -}; - -static struct pin_desc dbguart_pins_0[] = { - { PINID_PWM0, PIN_FUN3, }, - { PINID_PWM1, PIN_FUN3, }, -}; - -static struct pin_group dbguart_pins[] = { - [0] = { - .pins = dbguart_pins_0, - .nr_pins = ARRAY_SIZE(dbguart_pins_0), - }, -}; - -static int dbguart_pins_control(int id, int request) -{ - int r = 0; - - if (request) - r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart"); - else - stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart"); - return r; -} - -static struct pin_desc appuart_pins_0[] = { - { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, -}; - -static struct pin_desc appuart_pins_1[] = { -#if 0 /* enable these when second appuart will be connected */ - { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, -#endif -}; - -static struct pin_desc mmc_pins_desc[] = { - { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 }, - { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 }, - { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 }, -}; - -static struct pin_group mmc_pins = { - .pins = mmc_pins_desc, - .nr_pins = ARRAY_SIZE(mmc_pins_desc), -}; - -static int stmp3xxxmmc_get_wp(void) -{ - return gpio_get_value(PINID_PWM4); -} - -static int stmp3xxxmmc_hw_init_ssp1(void) -{ - int ret; - - ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc"); - if (ret) - goto out; - - /* Configure write protect GPIO pin */ - ret = gpio_request(PINID_PWM4, "mmc wp"); - if (ret) - goto out_wp; - - gpio_direction_input(PINID_PWM4); - - /* Configure POWER pin as gpio to drive power to MMC slot */ - ret = gpio_request(PINID_PWM3, "mmc power"); - if (ret) - goto out_power; - - gpio_direction_output(PINID_PWM3, 0); - mdelay(100); - - return 0; - -out_power: - gpio_free(PINID_PWM4); -out_wp: - stmp3xxx_release_pin_group(&mmc_pins, "mmc"); -out: - return ret; -} - -static void stmp3xxxmmc_hw_release_ssp1(void) -{ - gpio_free(PINID_PWM3); - gpio_free(PINID_PWM4); - stmp3xxx_release_pin_group(&mmc_pins, "mmc"); -} - -static void stmp3xxxmmc_cmd_pullup_ssp1(int enable) -{ - stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc"); -} - -static unsigned long -stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz) -{ - struct clk *ssp, *parent; - char *p; - long r; - - ssp = clk_get(NULL, "ssp"); - - /* using SSP1, no timeout, clock rate 1 */ - writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) | - BF(0xFFFF, SSP_TIMING_TIMEOUT), - base + HW_SSP_TIMING); - - p = (hz > 1000000) ? "io" : "osc_24M"; - parent = clk_get(NULL, p); - clk_set_parent(ssp, parent); - r = clk_set_rate(ssp, 2 * hz / 1000); - clk_put(parent); - clk_put(ssp); - - return hz; -} - -static struct stmp3xxxmmc_platform_data mmc_data = { - .hw_init = stmp3xxxmmc_hw_init_ssp1, - .hw_release = stmp3xxxmmc_hw_release_ssp1, - .get_wp = stmp3xxxmmc_get_wp, - .cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1, - .setclock = stmp3xxxmmc_setclock_ssp1, -}; - - -static struct pin_group appuart_pins[] = { - [0] = { - .pins = appuart_pins_0, - .nr_pins = ARRAY_SIZE(appuart_pins_0), - }, - [1] = { - .pins = appuart_pins_1, - .nr_pins = ARRAY_SIZE(appuart_pins_1), - }, -}; - -static struct pin_desc ssp1_pins_desc[] = { - { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, }, - { PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, - { PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, - { PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, }, -}; - -static struct pin_desc ssp2_pins_desc[] = { - { PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, }, - { PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, - { PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, - { PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, }, -}; - -static struct pin_group ssp1_pins = { - .pins = ssp1_pins_desc, - .nr_pins = ARRAY_SIZE(ssp1_pins_desc), -}; - -static struct pin_group ssp2_pins = { - .pins = ssp1_pins_desc, - .nr_pins = ARRAY_SIZE(ssp2_pins_desc), -}; - -static struct pin_desc gpmi_pins_desc[] = { - { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 }, - { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, - { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 }, -}; - -static struct pin_group gpmi_pins = { - .pins = gpmi_pins_desc, - .nr_pins = ARRAY_SIZE(gpmi_pins_desc), -}; - -static struct mtd_partition gpmi_partitions[] = { - [0] = { - .name = "boot", - .size = 10 * SZ_1M, - .offset = 0, - }, - [1] = { - .name = "data", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct gpmi_platform_data gpmi_data = { - .pins = &gpmi_pins, - .nr_parts = ARRAY_SIZE(gpmi_partitions), - .parts = gpmi_partitions, - .part_types = { "cmdline", NULL }, -}; - -static struct spi_board_info spi_board_info[] __initdata = { -#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) - { - .modalias = "enc28j60", - .max_speed_hz = 6 * 1000 * 1000, - .bus_num = 1, - .chip_select = 0, - .platform_data = NULL, - }, -#endif -}; - -static void __init stmp378x_devb_init(void) -{ - stmp3xxx_pinmux_init(NR_REAL_IRQS); - - /* init stmp3xxx platform */ - stmp3xxx_init(); - - stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; - stmp3xxx_appuart.dev.platform_data = appuart_pins; - stmp3xxx_mmc.dev.platform_data = &mmc_data; - stmp3xxx_gpmi.dev.platform_data = &gpmi_data; - stmp3xxx_spi1.dev.platform_data = &ssp1_pins; - stmp3xxx_spi2.dev.platform_data = &ssp2_pins; - stmp378x_i2c.dev.platform_data = &i2c_pins; - - /* register spi devices */ - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - - /* add board's devices */ - platform_add_devices(devices, ARRAY_SIZE(devices)); - - /* add devices selected by command line ssp1= and ssp2= options */ - stmp3xxx_ssp1_device_register(); - stmp3xxx_ssp2_device_register(); -} - -MACHINE_START(STMP378X, "STMP378X") - .boot_params = 0x40000100, - .map_io = stmp378x_map_io, - .init_irq = stmp378x_init_irq, - .timer = &stmp3xxx_timer, - .init_machine = stmp378x_devb_init, -MACHINE_END diff --git a/arch/arm/mach-stmp37xx/Makefile b/arch/arm/mach-stmp37xx/Makefile deleted file mode 100644 index 57deffd09fbf..000000000000 --- a/arch/arm/mach-stmp37xx/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o -obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o diff --git a/arch/arm/mach-stmp37xx/Makefile.boot b/arch/arm/mach-stmp37xx/Makefile.boot deleted file mode 100644 index 1568ad404d59..000000000000 --- a/arch/arm/mach-stmp37xx/Makefile.boot +++ /dev/null @@ -1,3 +0,0 @@ - zreladdr-y := 0x40008000 -params_phys-y := 0x40000100 -initrd_phys-y := 0x40800000 diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S deleted file mode 100644 index fed2787b6c34..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Low-level IRQ helper macros for Freescale STMP37XX - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro disable_fiq - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - mov \base, #0xf0000000 @ vm address of IRQ controller - ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT - cmp \irqnr, #0x3f - movne \irqstat, #0 @ Ack this IRQ - strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR - moveqs \irqnr, #0 @ Zero flag set for no IRQ - - .endm - - .macro get_irqnr_preamble, base, tmp - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h deleted file mode 100644 index 98f12938550d..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/irqs.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Freescale STMP37XX interrupts - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef _ASM_ARCH_IRQS_H -#define _ASM_ARCH_IRQS_H - -#define IRQ_DEBUG_UART 0 -#define IRQ_COMMS_RX 1 -#define IRQ_COMMS_TX 1 -#define IRQ_SSP2_ERROR 2 -#define IRQ_VDD5V 3 -#define IRQ_HEADPHONE_SHORT 4 -#define IRQ_DAC_DMA 5 -#define IRQ_DAC_ERROR 6 -#define IRQ_ADC_DMA 7 -#define IRQ_ADC_ERROR 8 -#define IRQ_SPDIF_DMA 9 -#define IRQ_SAIF2_DMA 9 -#define IRQ_SPDIF_ERROR 10 -#define IRQ_SAIF1_IRQ 10 -#define IRQ_SAIF2_IRQ 10 -#define IRQ_USB_CTRL 11 -#define IRQ_USB_WAKEUP 12 -#define IRQ_GPMI_DMA 13 -#define IRQ_SSP1_DMA 14 -#define IRQ_SSP_ERROR 15 -#define IRQ_GPIO0 16 -#define IRQ_GPIO1 17 -#define IRQ_GPIO2 18 -#define IRQ_SAIF1_DMA 19 -#define IRQ_SSP2_DMA 20 -#define IRQ_ECC8_IRQ 21 -#define IRQ_RTC_ALARM 22 -#define IRQ_UARTAPP_TX_DMA 23 -#define IRQ_UARTAPP_INTERNAL 24 -#define IRQ_UARTAPP_RX_DMA 25 -#define IRQ_I2C_DMA 26 -#define IRQ_I2C_ERROR 27 -#define IRQ_TIMER0 28 -#define IRQ_TIMER1 29 -#define IRQ_TIMER2 30 -#define IRQ_TIMER3 31 -#define IRQ_BATT_BRNOUT 32 -#define IRQ_VDDD_BRNOUT 33 -#define IRQ_VDDIO_BRNOUT 34 -#define IRQ_VDD18_BRNOUT 35 -#define IRQ_TOUCH_DETECT 36 -#define IRQ_LRADC_CH0 37 -#define IRQ_LRADC_CH1 38 -#define IRQ_LRADC_CH2 39 -#define IRQ_LRADC_CH3 40 -#define IRQ_LRADC_CH4 41 -#define IRQ_LRADC_CH5 42 -#define IRQ_LRADC_CH6 43 -#define IRQ_LRADC_CH7 44 -#define IRQ_LCDIF_DMA 45 -#define IRQ_LCDIF_ERROR 46 -#define IRQ_DIGCTL_DEBUG_TRAP 47 -#define IRQ_RTC_1MSEC 48 -#define IRQ_DRI_DMA 49 -#define IRQ_DRI_ATTENTION 50 -#define IRQ_GPMI_ATTENTION 51 -#define IRQ_IR 52 -#define IRQ_DCP_VMI 53 -#define IRQ_DCP 54 -#define IRQ_RESERVED_55 55 -#define IRQ_RESERVED_56 56 -#define IRQ_RESERVED_57 57 -#define IRQ_RESERVED_58 58 -#define IRQ_RESERVED_59 59 -#define SW_IRQ_60 60 -#define SW_IRQ_61 61 -#define SW_IRQ_62 62 -#define SW_IRQ_63 63 - -#define NR_REAL_IRQS 64 -#define NR_IRQS (NR_REAL_IRQS + 32 * 3) - -/* TIMER and BRNOUT are FIQ capable */ -#define FIQ_START IRQ_TIMER0 - -/* Hard disk IRQ is a GPMI attention IRQ */ -#define IRQ_HARDDISK IRQ_GPMI_ATTENTION - -#endif /* _ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h deleted file mode 100644 index d56de0c471d8..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/pins.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Freescale STMP37XX SoC pin multiplexing - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_PINS_H -#define __ASM_ARCH_PINS_H - -/* - * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware - * interface this pin belongs to. - */ - -/* Bank 0 */ -#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0) -#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1) -#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2) -#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3) -#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4) -#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5) -#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6) -#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7) -#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8) -#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9) -#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10) -#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11) -#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12) -#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13) -#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14) -#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15) -#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16) -#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17) -#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18) -#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19) -#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20) -#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21) -#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22) -#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23) -#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24) -#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25) -#define PINID_UART2_CTS STMP3XXX_PINID(0, 26) -#define PINID_UART2_RTS STMP3XXX_PINID(0, 27) -#define PINID_UART2_RX STMP3XXX_PINID(0, 28) -#define PINID_UART2_TX STMP3XXX_PINID(0, 29) - -/* Bank 1 */ -#define PINID_LCD_D00 STMP3XXX_PINID(1, 0) -#define PINID_LCD_D01 STMP3XXX_PINID(1, 1) -#define PINID_LCD_D02 STMP3XXX_PINID(1, 2) -#define PINID_LCD_D03 STMP3XXX_PINID(1, 3) -#define PINID_LCD_D04 STMP3XXX_PINID(1, 4) -#define PINID_LCD_D05 STMP3XXX_PINID(1, 5) -#define PINID_LCD_D06 STMP3XXX_PINID(1, 6) -#define PINID_LCD_D07 STMP3XXX_PINID(1, 7) -#define PINID_LCD_D08 STMP3XXX_PINID(1, 8) -#define PINID_LCD_D09 STMP3XXX_PINID(1, 9) -#define PINID_LCD_D10 STMP3XXX_PINID(1, 10) -#define PINID_LCD_D11 STMP3XXX_PINID(1, 11) -#define PINID_LCD_D12 STMP3XXX_PINID(1, 12) -#define PINID_LCD_D13 STMP3XXX_PINID(1, 13) -#define PINID_LCD_D14 STMP3XXX_PINID(1, 14) -#define PINID_LCD_D15 STMP3XXX_PINID(1, 15) -#define PINID_LCD_RESET STMP3XXX_PINID(1, 16) -#define PINID_LCD_RS STMP3XXX_PINID(1, 17) -#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18) -#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19) -#define PINID_LCD_CS STMP3XXX_PINID(1, 20) -#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21) -#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22) -#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23) -#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24) -#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25) -#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26) -#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27) -#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28) - -/* Bank 2 */ -#define PINID_PWM0 STMP3XXX_PINID(2, 0) -#define PINID_PWM1 STMP3XXX_PINID(2, 1) -#define PINID_PWM2 STMP3XXX_PINID(2, 2) -#define PINID_PWM3 STMP3XXX_PINID(2, 3) -#define PINID_PWM4 STMP3XXX_PINID(2, 4) -#define PINID_I2C_SCL STMP3XXX_PINID(2, 5) -#define PINID_I2C_SDA STMP3XXX_PINID(2, 6) -#define PINID_ROTTARYA STMP3XXX_PINID(2, 7) -#define PINID_ROTTARYB STMP3XXX_PINID(2, 8) -#define PINID_EMI_CKE STMP3XXX_PINID(2, 9) -#define PINID_EMI_RASN STMP3XXX_PINID(2, 10) -#define PINID_EMI_CASN STMP3XXX_PINID(2, 11) -#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12) -#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13) -#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14) -#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15) -#define PINID_EMI_A00 STMP3XXX_PINID(2, 16) -#define PINID_EMI_A01 STMP3XXX_PINID(2, 17) -#define PINID_EMI_A02 STMP3XXX_PINID(2, 18) -#define PINID_EMI_A03 STMP3XXX_PINID(2, 19) -#define PINID_EMI_A04 STMP3XXX_PINID(2, 20) -#define PINID_EMI_A05 STMP3XXX_PINID(2, 21) -#define PINID_EMI_A06 STMP3XXX_PINID(2, 22) -#define PINID_EMI_A07 STMP3XXX_PINID(2, 23) -#define PINID_EMI_A08 STMP3XXX_PINID(2, 24) -#define PINID_EMI_A09 STMP3XXX_PINID(2, 25) -#define PINID_EMI_A10 STMP3XXX_PINID(2, 26) -#define PINID_EMI_A11 STMP3XXX_PINID(2, 27) -#define PINID_EMI_A12 STMP3XXX_PINID(2, 28) -#define PINID_EMI_A13 STMP3XXX_PINID(2, 29) -#define PINID_EMI_A14 STMP3XXX_PINID(2, 30) -#define PINID_EMI_WEN STMP3XXX_PINID(2, 31) - -/* Bank 3 */ -#define PINID_EMI_D00 STMP3XXX_PINID(3, 0) -#define PINID_EMI_D01 STMP3XXX_PINID(3, 1) -#define PINID_EMI_D02 STMP3XXX_PINID(3, 2) -#define PINID_EMI_D03 STMP3XXX_PINID(3, 3) -#define PINID_EMI_D04 STMP3XXX_PINID(3, 4) -#define PINID_EMI_D05 STMP3XXX_PINID(3, 5) -#define PINID_EMI_D06 STMP3XXX_PINID(3, 6) -#define PINID_EMI_D07 STMP3XXX_PINID(3, 7) -#define PINID_EMI_D08 STMP3XXX_PINID(3, 8) -#define PINID_EMI_D09 STMP3XXX_PINID(3, 9) -#define PINID_EMI_D10 STMP3XXX_PINID(3, 10) -#define PINID_EMI_D11 STMP3XXX_PINID(3, 11) -#define PINID_EMI_D12 STMP3XXX_PINID(3, 12) -#define PINID_EMI_D13 STMP3XXX_PINID(3, 13) -#define PINID_EMI_D14 STMP3XXX_PINID(3, 14) -#define PINID_EMI_D15 STMP3XXX_PINID(3, 15) -#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16) -#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17) -#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18) -#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19) -#define PINID_EMI_CLK STMP3XXX_PINID(3, 20) -#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21) - -#endif /* __ASM_ARCH_PINS_H */ diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h deleted file mode 100644 index a323aa9a21f2..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * stmp37xx: APBH register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBH -#define _MACH_REGS_APBH - -#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) - -#define HW_APBH_CTRL0 0x0 -#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBH_CTRL0_RESET_CHANNEL 16 -#define BM_APBH_CTRL0_CLKGATE 0x40000000 -#define BM_APBH_CTRL0_SFTRST 0x80000000 - -#define HW_APBH_CTRL1 0x10 -#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 -#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 - -#define HW_APBH_DEVSEL 0x20 - -#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBH_CHn_NXTCMDAR 0x50 - -#define BM_APBH_CHn_CMD_MODE 0x00000003 -#define BP_APBH_CHn_CMD_MODE 0x00000001 -#define BV_APBH_CHn_CMD_MODE_NOOP 0 -#define BV_APBH_CHn_CMD_MODE_WRITE 1 -#define BV_APBH_CHn_CMD_MODE_READ 2 -#define BV_APBH_CHn_CMD_MODE_SENSE 3 -#define BM_APBH_CHn_CMD_CHAIN 0x00000004 -#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 -#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 -#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBH_CHn_CMD_CMDWORDS 12 -#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBH_CHn_CMD_XFER_COUNT 16 - -#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBH_CHn_SEMA 0x80 -#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBH_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h deleted file mode 100644 index 6d080cd5b702..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * stmp37xx: APBX register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_APBX -#define _MACH_REGS_APBX - -#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) - -#define HW_APBX_CTRL0 0x0 -#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBX_CTRL0_RESET_CHANNEL 16 -#define BM_APBX_CTRL0_CLKGATE 0x40000000 -#define BM_APBX_CTRL0_SFTRST 0x80000000 - -#define HW_APBX_CTRL1 0x10 - -#define HW_APBX_DEVSEL 0x20 - -#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBX_CHn_NXTCMDAR 0x50 -#define BM_APBX_CHn_CMD_MODE 0x00000003 -#define BP_APBX_CHn_CMD_MODE 0x00000001 -#define BV_APBX_CHn_CMD_MODE_NOOP 0 -#define BV_APBX_CHn_CMD_MODE_WRITE 1 -#define BV_APBX_CHn_CMD_MODE_READ 2 -#define BV_APBX_CHn_CMD_MODE_SENSE 3 -#define BM_APBX_CHn_CMD_COMMAND 0x00000003 -#define BP_APBX_CHn_CMD_COMMAND 0 -#define BM_APBX_CHn_CMD_CHAIN 0x00000004 -#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBX_CHn_CMD_CMDWORDS 12 -#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 -#define BP_APBX_CHn_CMD_XFER_COUNT 16 - -#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70) -#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70) -#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70) -#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70) -#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70) -#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70) -#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70) -#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70) -#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70) -#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70) -#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70) -#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70) -#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70) -#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70) -#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70) -#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70) - -#define HW_APBX_CHn_BAR 0x70 - -#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBX_CHn_SEMA 0x80 -#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 -#define BP_APBX_CHn_SEMA_PHORE 16 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h deleted file mode 100644 index 3b511f947a53..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * stmp37xx: AUDIOIN register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000) - -#define HW_AUDIOIN_CTRL 0x0 -#define BM_AUDIOIN_CTRL_RUN 0x00000001 -#define BP_AUDIOIN_CTRL_RUN 0 -#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 -#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOIN_STAT 0x10 - -#define HW_AUDIOIN_ADCSRR 0x20 - -#define HW_AUDIOIN_ADCVOLUME 0x30 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF -#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 -#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 - -#define HW_AUDIOIN_ADCDEBUG 0x40 - -#define HW_AUDIOIN_ADCVOL 0x50 -#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F -#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 -#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 -#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 -#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 -#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 -#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 -#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 -#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 - -#define HW_AUDIOIN_MICLINE 0x60 - -#define HW_AUDIOIN_ANACLKCTRL 0x70 -#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOIN_DATA 0x80 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h deleted file mode 100644 index ca1942b8a3e9..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * stmp37xx: AUDIOOUT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) - -#define HW_AUDIOOUT_CTRL 0x0 -#define BM_AUDIOOUT_CTRL_RUN 0x00000001 -#define BP_AUDIOOUT_CTRL_RUN 0 -#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 -#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 -#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 - -#define HW_AUDIOOUT_STAT 0x10 - -#define HW_AUDIOOUT_DACSRR 0x20 -#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF -#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 -#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 -#define BP_AUDIOOUT_DACSRR_SRC_INT 16 -#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 -#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 -#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 -#define BP_AUDIOOUT_DACSRR_BASEMULT 28 - -#define HW_AUDIOOUT_DACVOLUME 0x30 -#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 -#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 -#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_DACDEBUG 0x40 - -#define HW_AUDIOOUT_HPVOL 0x50 -#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 -#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 - -#define HW_AUDIOOUT_PWRDN 0x70 -#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 -#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 -#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 -#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 -#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 -#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 -#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000 - -#define HW_AUDIOOUT_REFCTRL 0x80 -#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 -#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 -#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 -#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 -#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 -#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 -#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 -#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 -#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 -#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 -#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 -#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 -#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 - -#define HW_AUDIOOUT_ANACTRL 0x90 -#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 -#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 - -#define HW_AUDIOOUT_TEST 0xA0 -#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 -#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 - -#define HW_AUDIOOUT_BISTCTRL 0xB0 - -#define HW_AUDIOOUT_BISTSTAT0 0xC0 - -#define HW_AUDIOOUT_BISTSTAT1 0xD0 - -#define HW_AUDIOOUT_ANACLKCTRL 0xE0 -#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 - -#define HW_AUDIOOUT_DATA 0xF0 - -#define HW_AUDIOOUT_LINEOUTCTRL 0x100 -#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F -#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0 -#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00 -#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8 -#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000 -#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12 -#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000 -#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20 -#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000 -#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000 - -#define HW_AUDIOOUT_VERSION 0x200 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h deleted file mode 100644 index 47f5c92fdaf6..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * stmp37xx: CLKCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_CLKCTRL -#define _MACH_REGS_CLKCTRL - -#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) - -#define HW_CLKCTRL_PLLCTRL0 0x0 -#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 - -#define HW_CLKCTRL_CPU 0x20 -#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F -#define BP_CLKCTRL_CPU_DIV_CPU 0 - -#define HW_CLKCTRL_HBUS 0x30 -#define BM_CLKCTRL_HBUS_DIV 0x0000001F -#define BP_CLKCTRL_HBUS_DIV 0 - -#define HW_CLKCTRL_XBUS 0x40 - -#define HW_CLKCTRL_XTAL 0x50 - -#define HW_CLKCTRL_PIX 0x60 -#define BM_CLKCTRL_PIX_DIV 0x00007FFF -#define BP_CLKCTRL_PIX_DIV 0 -#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 - -#define HW_CLKCTRL_SSP 0x70 - -#define HW_CLKCTRL_GPMI 0x80 - -#define HW_CLKCTRL_SPDIF 0x90 - -#define HW_CLKCTRL_EMI 0xA0 - -#define HW_CLKCTRL_IR 0xB0 - -#define HW_CLKCTRL_SAIF 0xC0 - -#define HW_CLKCTRL_FRAC 0xD0 -#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 -#define BP_CLKCTRL_FRAC_EMIFRAC 8 -#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 -#define BP_CLKCTRL_FRAC_PIXFRAC 16 -#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 - -#define HW_CLKCTRL_CLKSEQ 0xE0 -#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 - -#define HW_CLKCTRL_RESET 0xF0 -#define BM_CLKCTRL_RESET_DIG 0x00000001 -#define BP_CLKCTRL_RESET_DIG 0 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h deleted file mode 100644 index ba1bbe265c20..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * stmp37xx: DIGCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000) - -#define HW_DIGCTL_CTRL 0x0 -#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h deleted file mode 100644 index 3b6d990a3af5..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp37xx: ECC8 register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) - -#define HW_ECC8_CTRL 0x0 -#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_ECC8_CTRL_COMPLETE_IRQ 0 -#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 -#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 - -#define HW_ECC8_STATUS0 0x10 -#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_ECC8_STATUS0_CORRECTED 0x00000008 -#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 -#define BP_ECC8_STATUS0_STATUS_AUX 8 -#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 -#define BP_ECC8_STATUS0_COMPLETED_CE 16 - -#define HW_ECC8_STATUS1 0x20 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h deleted file mode 100644 index f2b304f54490..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * stmp37xx: GPMI register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000) -#define REGS_GPMI_PHYS 0x8000C000 -#define REGS_GPMI_SIZE 0x2000 - -#define HW_GPMI_CTRL0 0x0 -#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_GPMI_CTRL0_XFER_COUNT 0 -#define BM_GPMI_CTRL0_CS 0x00300000 -#define BP_GPMI_CTRL0_CS 20 -#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 -#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 -#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 -#define BP_GPMI_CTRL0_COMMAND_MODE 24 -#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 -#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 -#define BM_GPMI_CTRL0_RUN 0x20000000 -#define BM_GPMI_CTRL0_CLKGATE 0x40000000 -#define BM_GPMI_CTRL0_SFTRST 0x80000000 -#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 -#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 -#define BP_GPMI_ECCCTRL_ECC_CMD 13 - -#define HW_GPMI_CTRL1 0x60 -#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003 -#define BP_GPMI_CTRL1_GPMI_MODE 0 -#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 -#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 -#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 -#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 -#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000 -#define BP_GPMI_CTRL1_DSAMPLE_TIME 12 - -#define HW_GPMI_TIMING0 0x70 -#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF -#define BP_GPMI_TIMING0_DATA_SETUP 0 -#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 -#define BP_GPMI_TIMING0_DATA_HOLD 8 - -#define HW_GPMI_TIMING1 0x80 -#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 -#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h deleted file mode 100644 index 35882a9b8bc5..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * stmp37xx: I2C register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000) -#define REGS_I2C_PHYS 0x80058000 -#define REGS_I2C_SIZE 0x2000 - -#define HW_I2C_CTRL0 0x0 -#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_I2C_CTRL0_XFER_COUNT 0 -#define BM_I2C_CTRL0_DIRECTION 0x00010000 -#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 -#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 -#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 -#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 -#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 -#define BM_I2C_CTRL0_CLKGATE 0x40000000 -#define BM_I2C_CTRL0_SFTRST 0x80000000 - -#define HW_I2C_TIMING0 0x10 - -#define HW_I2C_TIMING1 0x20 - -#define HW_I2C_TIMING2 0x30 - -#define HW_I2C_CTRL1 0x40 -#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 -#define BP_I2C_CTRL1_SLAVE_IRQ 0 -#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 -#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 -#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 -#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 -#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 -#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 -#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 -#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 - -#define HW_I2C_VERSION 0x90 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h deleted file mode 100644 index 3b7c92239e20..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * stmp37xx: ICOLL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_ICOLL -#define _MACH_REGS_ICOLL - -#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) - -#define HW_ICOLL_VECTOR 0x0 - -#define HW_ICOLL_LEVELACK 0x10 - -#define HW_ICOLL_CTRL 0x20 -#define BM_ICOLL_CTRL_CLKGATE 0x40000000 -#define BM_ICOLL_CTRL_SFTRST 0x80000000 - -#define HW_ICOLL_STAT 0x30 - -#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10) -#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10) -#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10) -#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10) - -#define HW_ICOLL_PRIORITYn 0x60 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h deleted file mode 100644 index 72514e8b0737..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * stmp37xx: LCDIF register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) -#define REGS_LCDIF_PHYS 0x80030000 -#define REGS_LCDIF_SIZE 0x2000 - -#define HW_LCDIF_CTRL 0x0 -#define BM_LCDIF_CTRL_COUNT 0x0000FFFF -#define BP_LCDIF_CTRL_COUNT 0 -#define BM_LCDIF_CTRL_RUN 0x00010000 -#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000 -#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000 -#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000 -#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000 -#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000 -#define BP_LCDIF_CTRL_DATA_SWIZZLE 21 -#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000 -#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000 -#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25 -#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000 -#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000 -#define BM_LCDIF_CTRL_CLKGATE 0x40000000 -#define BM_LCDIF_CTRL_SFTRST 0x80000000 - -#define HW_LCDIF_CTRL1 0x10 -#define BM_LCDIF_CTRL1_RESET 0x00000001 -#define BP_LCDIF_CTRL1_RESET 0 -#define BM_LCDIF_CTRL1_MODE86 0x00000002 -#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 -#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 -#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 -#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 -#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 -#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 - -#define HW_LCDIF_TIMING 0x20 - -#define HW_LCDIF_VDCTRL0 0x30 -#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF -#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 -#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 -#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 -#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 -#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 -#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 -#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 -#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 - -#define HW_LCDIF_VDCTRL1 0x40 -#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF -#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 -#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000 -#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20 - -#define HW_LCDIF_VDCTRL2 0x50 -#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF -#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0 -#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800 -#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11 -#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000 -#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23 - -#define HW_LCDIF_VDCTRL3 0x60 -#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF -#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 -#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000 -#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12 -#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h deleted file mode 100644 index cc7b4702d1cd..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * stmp37xx: LRADC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000) - -#define HW_LRADC_CTRL0 0x0 -#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF -#define BP_LRADC_CTRL0_SCHEDULE 0 -#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 -#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 -#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 -#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 -#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 -#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 -#define BM_LRADC_CTRL0_CLKGATE 0x40000000 -#define BM_LRADC_CTRL0_SFTRST 0x80000000 - -#define HW_LRADC_CTRL1 0x10 -#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 -#define BP_LRADC_CTRL1_LRADC0_IRQ 0 -#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 -#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 -#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 -#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 - -#define HW_LRADC_CTRL2 0x20 -#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 -#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 -#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 -#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 -#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 -#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 - -#define HW_LRADC_CTRL3 0x30 -#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 -#define BP_LRADC_CTRL3_CYCLE_TIME 8 - -#define HW_LRADC_STATUS 0x40 -#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 -#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 - -#define HW_LRADC_CH0 (0x50 + 0 * 0x10) -#define HW_LRADC_CH1 (0x50 + 1 * 0x10) -#define HW_LRADC_CH2 (0x50 + 2 * 0x10) -#define HW_LRADC_CH3 (0x50 + 3 * 0x10) -#define HW_LRADC_CH4 (0x50 + 4 * 0x10) -#define HW_LRADC_CH5 (0x50 + 5 * 0x10) -#define HW_LRADC_CH6 (0x50 + 6 * 0x10) -#define HW_LRADC_CH7 (0x50 + 7 * 0x10) - -#define HW_LRADC_CHn 0x50 -#define BM_LRADC_CHn_VALUE 0x0003FFFF -#define BP_LRADC_CHn_VALUE 0 -#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 -#define BP_LRADC_CHn_NUM_SAMPLES 24 -#define BM_LRADC_CHn_ACCUMULATE 0x20000000 - -#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10) -#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10) -#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10) -#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10) - -#define HW_LRADC_DELAYn 0xD0 -#define BM_LRADC_DELAYn_DELAY 0x000007FF -#define BP_LRADC_DELAYn_DELAY 0 -#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 -#define BP_LRADC_DELAYn_LOOP_COUNT 11 -#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 -#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 -#define BM_LRADC_DELAYn_KICK 0x00100000 -#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 -#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 - -#define HW_LRADC_CTRL4 0x140 -#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 -#define BP_LRADC_CTRL4_LRADC6SELECT 24 -#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 -#define BP_LRADC_CTRL4_LRADC7SELECT 28 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h deleted file mode 100644 index d5efce2388c7..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * stmp37xx: PINCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_PINCTRL -#define _MACH_REGS_PINCTRL - -#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) - -#define HW_PINCTRL_MUXSEL0 0x100 -#define HW_PINCTRL_MUXSEL1 0x110 -#define HW_PINCTRL_MUXSEL2 0x120 -#define HW_PINCTRL_MUXSEL3 0x130 -#define HW_PINCTRL_MUXSEL4 0x140 -#define HW_PINCTRL_MUXSEL5 0x150 -#define HW_PINCTRL_MUXSEL6 0x160 -#define HW_PINCTRL_MUXSEL7 0x170 - -#define HW_PINCTRL_DRIVE0 0x200 -#define HW_PINCTRL_DRIVE1 0x210 -#define HW_PINCTRL_DRIVE2 0x220 -#define HW_PINCTRL_DRIVE3 0x230 -#define HW_PINCTRL_DRIVE4 0x240 -#define HW_PINCTRL_DRIVE5 0x250 -#define HW_PINCTRL_DRIVE6 0x260 -#define HW_PINCTRL_DRIVE7 0x270 -#define HW_PINCTRL_DRIVE8 0x280 -#define HW_PINCTRL_DRIVE9 0x290 -#define HW_PINCTRL_DRIVE10 0x2A0 -#define HW_PINCTRL_DRIVE11 0x2B0 -#define HW_PINCTRL_DRIVE12 0x2C0 -#define HW_PINCTRL_DRIVE13 0x2D0 -#define HW_PINCTRL_DRIVE14 0x2E0 - -#define HW_PINCTRL_PULL0 0x300 -#define HW_PINCTRL_PULL1 0x310 -#define HW_PINCTRL_PULL2 0x320 -#define HW_PINCTRL_PULL3 0x330 - -#define HW_PINCTRL_DOUT0 0x400 -#define HW_PINCTRL_DOUT1 0x410 -#define HW_PINCTRL_DOUT2 0x420 - -#define HW_PINCTRL_DIN0 0x500 -#define HW_PINCTRL_DIN1 0x510 -#define HW_PINCTRL_DIN2 0x520 - -#define HW_PINCTRL_DOE0 0x600 -#define HW_PINCTRL_DOE1 0x610 -#define HW_PINCTRL_DOE2 0x620 - -#define HW_PINCTRL_PIN2IRQ0 0x700 -#define HW_PINCTRL_PIN2IRQ1 0x710 -#define HW_PINCTRL_PIN2IRQ2 0x720 - -#define HW_PINCTRL_IRQEN0 0x800 -#define HW_PINCTRL_IRQEN1 0x810 -#define HW_PINCTRL_IRQEN2 0x820 - -#define HW_PINCTRL_IRQLEVEL0 0x900 -#define HW_PINCTRL_IRQLEVEL1 0x910 -#define HW_PINCTRL_IRQLEVEL2 0x920 - -#define HW_PINCTRL_IRQPOL0 0xA00 -#define HW_PINCTRL_IRQPOL1 0xA10 -#define HW_PINCTRL_IRQPOL2 0xA20 - -#define HW_PINCTRL_IRQSTAT0 0xB00 -#define HW_PINCTRL_IRQSTAT1 0xB10 -#define HW_PINCTRL_IRQSTAT2 0xB20 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h deleted file mode 100644 index 0e733d74a229..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-power.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * stmp37xx: POWER register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_POWER -#define _MACH_REGS_POWER - -#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) - -#define HW_POWER_CTRL 0x0 -#define BM_POWER_CTRL_CLKGATE 0x40000000 - -#define HW_POWER_5VCTRL 0x10 - -#define HW_POWER_MINPWR 0x20 - -#define HW_POWER_CHARGE 0x30 - -#define HW_POWER_VDDDCTRL 0x40 - -#define HW_POWER_VDDACTRL 0x50 - -#define HW_POWER_VDDIOCTRL 0x60 -#define BM_POWER_VDDIOCTRL_TRG 0x0000001F -#define BP_POWER_VDDIOCTRL_TRG 0 - -#define HW_POWER_STS 0xB0 -#define BM_POWER_STS_VBUSVALID 0x00000002 -#define BM_POWER_STS_BVALID 0x00000004 -#define BM_POWER_STS_AVALID 0x00000008 -#define BM_POWER_STS_DC_OK 0x00000100 - -#define HW_POWER_RESET 0xE0 - -#define HW_POWER_DEBUG 0xF0 -#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 -#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 -#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 - -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h deleted file mode 100644 index 15966a1b62e0..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * stmp37xx: PWM register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000) - -#define HW_PWM_CTRL 0x0 -#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 -#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 - -#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20) -#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20) -#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20) -#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20) - -#define HW_PWM_ACTIVEn 0x10 -#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF -#define BP_PWM_ACTIVEn_ACTIVE 0 -#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 -#define BP_PWM_ACTIVEn_INACTIVE 16 - -#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20) -#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20) -#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20) -#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20) - -#define HW_PWM_PERIODn 0x20 -#define BM_PWM_PERIODn_PERIOD 0x0000FFFF -#define BP_PWM_PERIODn_PERIOD 0 -#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 -#define BP_PWM_PERIODn_ACTIVE_STATE 16 -#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 -#define BP_PWM_PERIODn_INACTIVE_STATE 18 -#define BM_PWM_PERIODn_CDIV 0x00700000 -#define BP_PWM_PERIODn_CDIV 20 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h deleted file mode 100644 index fac40edc38a1..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * stmp37xx: RTC register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000) -#define REGS_RTC_PHYS 0x8005C000 -#define REGS_RTC_SIZE 0x2000 - -#define HW_RTC_CTRL 0x0 -#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 -#define BP_RTC_CTRL_ALARM_IRQ_EN 0 -#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 -#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 -#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 -#define BM_RTC_CTRL_WATCHDOGEN 0x00000010 - -#define HW_RTC_STAT 0x10 -#define BM_RTC_STAT_NEW_REGS 0x0000FF00 -#define BP_RTC_STAT_NEW_REGS 8 -#define BM_RTC_STAT_STALE_REGS 0x00FF0000 -#define BP_RTC_STAT_STALE_REGS 16 -#define BM_RTC_STAT_RTC_PRESENT 0x80000000 - -#define HW_RTC_SECONDS 0x30 - -#define HW_RTC_ALARM 0x40 - -#define HW_RTC_WATCHDOG 0x50 - -#define HW_RTC_PERSISTENT0 0x60 -#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 -#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 -#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 -#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 -#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 -#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 -#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 - -#define HW_RTC_PERSISTENT1 0x70 - -#define HW_RTC_VERSION 0xD0 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h deleted file mode 100644 index cbde891a06c2..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * stmp37xx: SSP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000) -#define REGS_SSP1_PHYS 0x80010000 -#define REGS_SSP2_PHYS 0x80034000 -#define REGS_SSP_SIZE 0x2000 - -#define HW_SSP_CTRL0 0x0 -#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_SSP_CTRL0_XFER_COUNT 0 -#define BM_SSP_CTRL0_ENABLE 0x00010000 -#define BM_SSP_CTRL0_GET_RESP 0x00020000 -#define BM_SSP_CTRL0_LONG_RESP 0x00080000 -#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 -#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 -#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 -#define BP_SSP_CTRL0_BUS_WIDTH 22 -#define BM_SSP_CTRL0_DATA_XFER 0x01000000 -#define BM_SSP_CTRL0_READ 0x02000000 -#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 -#define BM_SSP_CTRL0_LOCK_CS 0x08000000 -#define BM_SSP_CTRL0_RUN 0x20000000 -#define BM_SSP_CTRL0_CLKGATE 0x40000000 -#define BM_SSP_CTRL0_SFTRST 0x80000000 - -#define HW_SSP_CMD0 0x10 -#define BM_SSP_CMD0_CMD 0x000000FF -#define BP_SSP_CMD0_CMD 0 -#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 -#define BP_SSP_CMD0_BLOCK_COUNT 8 -#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 -#define BP_SSP_CMD0_BLOCK_SIZE 16 -#define BM_SSP_CMD0_APPEND_8CYC 0x00100000 -#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF -#define BP_SSP_CMD1_CMD_ARG 0 - -#define HW_SSP_TIMING 0x50 -#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF -#define BP_SSP_TIMING_CLOCK_RATE 0 -#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 -#define BP_SSP_TIMING_CLOCK_DIVIDE 8 -#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 -#define BP_SSP_TIMING_TIMEOUT 16 - -#define HW_SSP_CTRL1 0x60 -#define BM_SSP_CTRL1_SSP_MODE 0x0000000F -#define BP_SSP_CTRL1_SSP_MODE 0 -#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 -#define BP_SSP_CTRL1_WORD_LENGTH 4 -#define BM_SSP_CTRL1_POLARITY 0x00000200 -#define BM_SSP_CTRL1_PHASE 0x00000400 -#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 -#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 -#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 -#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 - -#define HW_SSP_DATA 0x70 - -#define HW_SSP_SDRESP0 0x80 - -#define HW_SSP_SDRESP1 0x90 - -#define HW_SSP_SDRESP2 0xA0 - -#define HW_SSP_SDRESP3 0xB0 - -#define HW_SSP_STATUS 0xC0 -#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 -#define BM_SSP_STATUS_TIMEOUT 0x00001000 -#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 -#define BM_SSP_STATUS_RESP_ERR 0x00008000 -#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 -#define BM_SSP_STATUS_CARD_DETECT 0x10000000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h deleted file mode 100644 index 4af0f6edfa78..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * stmp37xx: TIMROT register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef _MACH_REGS_TIMROT -#define _MACH_REGS_TIMROT - -#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) - -#define HW_TIMROT_ROTCTRL 0x0 -#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 -#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 - -#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20) -#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20) -#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20) - -#define HW_TIMROT_TIMCTRLn 0x20 -#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F -#define BP_TIMROT_TIMCTRLn_SELECT 0 -#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 -#define BP_TIMROT_TIMCTRLn_PRESCALE 4 -#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 -#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 -#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 -#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 - -#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20) -#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20) -#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20) - -#define HW_TIMROT_TIMCOUNTn 0x30 -#endif diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h deleted file mode 100644 index 0594275d860c..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * stmp37xx: UARTAPP register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000) -#define REGS_UARTAPP1_PHYS 0x8006C000 -#define REGS_UARTAPP_SIZE 0x2000 - -#define HW_UARTAPP_CTRL0 0x0 -#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL0_XFER_COUNT 0 -#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 -#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 -#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 -#define BM_UARTAPP_CTRL0_RUN 0x20000000 -#define BM_UARTAPP_CTRL0_SFTRST 0x80000000 -#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL1_XFER_COUNT 0 -#define BM_UARTAPP_CTRL1_RUN 0x10000000 - -#define HW_UARTAPP_CTRL2 0x20 -#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 -#define BP_UARTAPP_CTRL2_UARTEN 0 -#define BM_UARTAPP_CTRL2_TXE 0x00000100 -#define BM_UARTAPP_CTRL2_RXE 0x00000200 -#define BM_UARTAPP_CTRL2_RTS 0x00000800 -#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 -#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 -#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 -#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 -#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000 - -#define HW_UARTAPP_LINECTRL 0x30 -#define BM_UARTAPP_LINECTRL_BRK 0x00000001 -#define BP_UARTAPP_LINECTRL_BRK 0 -#define BM_UARTAPP_LINECTRL_PEN 0x00000002 -#define BM_UARTAPP_LINECTRL_EPS 0x00000004 -#define BM_UARTAPP_LINECTRL_STP2 0x00000008 -#define BM_UARTAPP_LINECTRL_FEN 0x00000010 -#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 -#define BP_UARTAPP_LINECTRL_WLEN 5 -#define BM_UARTAPP_LINECTRL_SPS 0x00000080 -#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 -#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 -#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 -#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 - -#define HW_UARTAPP_INTR 0x50 -#define BM_UARTAPP_INTR_CTSMIS 0x00000002 -#define BM_UARTAPP_INTR_RTIS 0x00000040 -#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 -#define BM_UARTAPP_INTR_RXIEN 0x00100000 -#define BM_UARTAPP_INTR_RTIEN 0x00400000 - -#define HW_UARTAPP_DATA 0x60 - -#define HW_UARTAPP_STAT 0x70 -#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF -#define BP_UARTAPP_STAT_RXCOUNT 0 -#define BM_UARTAPP_STAT_FERR 0x00010000 -#define BM_UARTAPP_STAT_PERR 0x00020000 -#define BM_UARTAPP_STAT_BERR 0x00040000 -#define BM_UARTAPP_STAT_OERR 0x00080000 -#define BM_UARTAPP_STAT_RXFE 0x01000000 -#define BM_UARTAPP_STAT_TXFF 0x02000000 -#define BM_UARTAPP_STAT_TXFE 0x08000000 -#define BM_UARTAPP_STAT_CTS 0x10000000 - -#define HW_UARTAPP_VERSION 0x90 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h deleted file mode 100644 index b810deb552a9..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * stmp378x: UARTDBG register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000) -#define REGS_UARTDBG_PHYS 0x80070000 -#define REGS_UARTDBG_SIZE 0x2000 - -#define HW_UARTDBGDR 0x00000000 -#define BP_UARTDBGDR_UNAVAILABLE 16 -#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) -#define BP_UARTDBGDR_RESERVED 12 -#define BM_UARTDBGDR_RESERVED 0x0000F000 -#define BF_UARTDBGDR_RESERVED(v) \ - (((v) << 12) & BM_UARTDBGDR_RESERVED) -#define BM_UARTDBGDR_OE 0x00000800 -#define BM_UARTDBGDR_BE 0x00000400 -#define BM_UARTDBGDR_PE 0x00000200 -#define BM_UARTDBGDR_FE 0x00000100 -#define BP_UARTDBGDR_DATA 0 -#define BM_UARTDBGDR_DATA 0x000000FF -#define BF_UARTDBGDR_DATA(v) \ - (((v) << 0) & BM_UARTDBGDR_DATA) -#define HW_UARTDBGRSR_ECR 0x00000004 -#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 -#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) -#define BP_UARTDBGRSR_ECR_EC 4 -#define BM_UARTDBGRSR_ECR_EC 0x000000F0 -#define BF_UARTDBGRSR_ECR_EC(v) \ - (((v) << 4) & BM_UARTDBGRSR_ECR_EC) -#define BM_UARTDBGRSR_ECR_OE 0x00000008 -#define BM_UARTDBGRSR_ECR_BE 0x00000004 -#define BM_UARTDBGRSR_ECR_PE 0x00000002 -#define BM_UARTDBGRSR_ECR_FE 0x00000001 -#define HW_UARTDBGFR 0x00000018 -#define BP_UARTDBGFR_UNAVAILABLE 16 -#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGFR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) -#define BP_UARTDBGFR_RESERVED 9 -#define BM_UARTDBGFR_RESERVED 0x0000FE00 -#define BF_UARTDBGFR_RESERVED(v) \ - (((v) << 9) & BM_UARTDBGFR_RESERVED) -#define BM_UARTDBGFR_RI 0x00000100 -#define BM_UARTDBGFR_TXFE 0x00000080 -#define BM_UARTDBGFR_RXFF 0x00000040 -#define BM_UARTDBGFR_TXFF 0x00000020 -#define BM_UARTDBGFR_RXFE 0x00000010 -#define BM_UARTDBGFR_BUSY 0x00000008 -#define BM_UARTDBGFR_DCD 0x00000004 -#define BM_UARTDBGFR_DSR 0x00000002 -#define BM_UARTDBGFR_CTS 0x00000001 -#define HW_UARTDBGILPR 0x00000020 -#define BP_UARTDBGILPR_UNAVAILABLE 8 -#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGILPR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) -#define BP_UARTDBGILPR_ILPDVSR 0 -#define BM_UARTDBGILPR_ILPDVSR 0x000000FF -#define BF_UARTDBGILPR_ILPDVSR(v) \ - (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) -#define HW_UARTDBGIBRD 0x00000024 -#define BP_UARTDBGIBRD_UNAVAILABLE 16 -#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIBRD_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) -#define BP_UARTDBGIBRD_BAUD_DIVINT 0 -#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF -#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ - (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) -#define HW_UARTDBGFBRD 0x00000028 -#define BP_UARTDBGFBRD_UNAVAILABLE 8 -#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 -#define BF_UARTDBGFBRD_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) -#define BP_UARTDBGFBRD_RESERVED 6 -#define BM_UARTDBGFBRD_RESERVED 0x000000C0 -#define BF_UARTDBGFBRD_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGFBRD_RESERVED) -#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 -#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F -#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ - (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) -#define HW_UARTDBGLCR_H 0x0000002c -#define BP_UARTDBGLCR_H_UNAVAILABLE 16 -#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) -#define BP_UARTDBGLCR_H_RESERVED 8 -#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 -#define BF_UARTDBGLCR_H_RESERVED(v) \ - (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) -#define BM_UARTDBGLCR_H_SPS 0x00000080 -#define BP_UARTDBGLCR_H_WLEN 5 -#define BM_UARTDBGLCR_H_WLEN 0x00000060 -#define BF_UARTDBGLCR_H_WLEN(v) \ - (((v) << 5) & BM_UARTDBGLCR_H_WLEN) -#define BM_UARTDBGLCR_H_FEN 0x00000010 -#define BM_UARTDBGLCR_H_STP2 0x00000008 -#define BM_UARTDBGLCR_H_EPS 0x00000004 -#define BM_UARTDBGLCR_H_PEN 0x00000002 -#define BM_UARTDBGLCR_H_BRK 0x00000001 -#define HW_UARTDBGCR 0x00000030 -#define BP_UARTDBGCR_UNAVAILABLE 16 -#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGCR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) -#define BM_UARTDBGCR_CTSEN 0x00008000 -#define BM_UARTDBGCR_RTSEN 0x00004000 -#define BM_UARTDBGCR_OUT2 0x00002000 -#define BM_UARTDBGCR_OUT1 0x00001000 -#define BM_UARTDBGCR_RTS 0x00000800 -#define BM_UARTDBGCR_DTR 0x00000400 -#define BM_UARTDBGCR_RXE 0x00000200 -#define BM_UARTDBGCR_TXE 0x00000100 -#define BM_UARTDBGCR_LBE 0x00000080 -#define BP_UARTDBGCR_RESERVED 3 -#define BM_UARTDBGCR_RESERVED 0x00000078 -#define BF_UARTDBGCR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGCR_RESERVED) -#define BM_UARTDBGCR_SIRLP 0x00000004 -#define BM_UARTDBGCR_SIREN 0x00000002 -#define BM_UARTDBGCR_UARTEN 0x00000001 -#define HW_UARTDBGIFLS 0x00000034 -#define BP_UARTDBGIFLS_UNAVAILABLE 16 -#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIFLS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) -#define BP_UARTDBGIFLS_RESERVED 6 -#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 -#define BF_UARTDBGIFLS_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGIFLS_RESERVED) -#define BP_UARTDBGIFLS_RXIFLSEL 3 -#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 -#define BF_UARTDBGIFLS_RXIFLSEL(v) \ - (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) -#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 -#define BP_UARTDBGIFLS_TXIFLSEL 0 -#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 -#define BF_UARTDBGIFLS_TXIFLSEL(v) \ - (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) -#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 -#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 -#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 -#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 -#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 -#define HW_UARTDBGIMSC 0x00000038 -#define BP_UARTDBGIMSC_UNAVAILABLE 16 -#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGIMSC_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) -#define BP_UARTDBGIMSC_RESERVED 11 -#define BM_UARTDBGIMSC_RESERVED 0x0000F800 -#define BF_UARTDBGIMSC_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGIMSC_RESERVED) -#define BM_UARTDBGIMSC_OEIM 0x00000400 -#define BM_UARTDBGIMSC_BEIM 0x00000200 -#define BM_UARTDBGIMSC_PEIM 0x00000100 -#define BM_UARTDBGIMSC_FEIM 0x00000080 -#define BM_UARTDBGIMSC_RTIM 0x00000040 -#define BM_UARTDBGIMSC_TXIM 0x00000020 -#define BM_UARTDBGIMSC_RXIM 0x00000010 -#define BM_UARTDBGIMSC_DSRMIM 0x00000008 -#define BM_UARTDBGIMSC_DCDMIM 0x00000004 -#define BM_UARTDBGIMSC_CTSMIM 0x00000002 -#define BM_UARTDBGIMSC_RIMIM 0x00000001 -#define HW_UARTDBGRIS 0x0000003c -#define BP_UARTDBGRIS_UNAVAILABLE 16 -#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGRIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) -#define BP_UARTDBGRIS_RESERVED 11 -#define BM_UARTDBGRIS_RESERVED 0x0000F800 -#define BF_UARTDBGRIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGRIS_RESERVED) -#define BM_UARTDBGRIS_OERIS 0x00000400 -#define BM_UARTDBGRIS_BERIS 0x00000200 -#define BM_UARTDBGRIS_PERIS 0x00000100 -#define BM_UARTDBGRIS_FERIS 0x00000080 -#define BM_UARTDBGRIS_RTRIS 0x00000040 -#define BM_UARTDBGRIS_TXRIS 0x00000020 -#define BM_UARTDBGRIS_RXRIS 0x00000010 -#define BM_UARTDBGRIS_DSRRMIS 0x00000008 -#define BM_UARTDBGRIS_DCDRMIS 0x00000004 -#define BM_UARTDBGRIS_CTSRMIS 0x00000002 -#define BM_UARTDBGRIS_RIRMIS 0x00000001 -#define HW_UARTDBGMIS 0x00000040 -#define BP_UARTDBGMIS_UNAVAILABLE 16 -#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGMIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) -#define BP_UARTDBGMIS_RESERVED 11 -#define BM_UARTDBGMIS_RESERVED 0x0000F800 -#define BF_UARTDBGMIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGMIS_RESERVED) -#define BM_UARTDBGMIS_OEMIS 0x00000400 -#define BM_UARTDBGMIS_BEMIS 0x00000200 -#define BM_UARTDBGMIS_PEMIS 0x00000100 -#define BM_UARTDBGMIS_FEMIS 0x00000080 -#define BM_UARTDBGMIS_RTMIS 0x00000040 -#define BM_UARTDBGMIS_TXMIS 0x00000020 -#define BM_UARTDBGMIS_RXMIS 0x00000010 -#define BM_UARTDBGMIS_DSRMMIS 0x00000008 -#define BM_UARTDBGMIS_DCDMMIS 0x00000004 -#define BM_UARTDBGMIS_CTSMMIS 0x00000002 -#define BM_UARTDBGMIS_RIMMIS 0x00000001 -#define HW_UARTDBGICR 0x00000044 -#define BP_UARTDBGICR_UNAVAILABLE 16 -#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGICR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) -#define BP_UARTDBGICR_RESERVED 11 -#define BM_UARTDBGICR_RESERVED 0x0000F800 -#define BF_UARTDBGICR_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGICR_RESERVED) -#define BM_UARTDBGICR_OEIC 0x00000400 -#define BM_UARTDBGICR_BEIC 0x00000200 -#define BM_UARTDBGICR_PEIC 0x00000100 -#define BM_UARTDBGICR_FEIC 0x00000080 -#define BM_UARTDBGICR_RTIC 0x00000040 -#define BM_UARTDBGICR_TXIC 0x00000020 -#define BM_UARTDBGICR_RXIC 0x00000010 -#define BM_UARTDBGICR_DSRMIC 0x00000008 -#define BM_UARTDBGICR_DCDMIC 0x00000004 -#define BM_UARTDBGICR_CTSMIC 0x00000002 -#define BM_UARTDBGICR_RIMIC 0x00000001 -#define HW_UARTDBGDMACR 0x00000048 -#define BP_UARTDBGDMACR_UNAVAILABLE 16 -#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 -#define BF_UARTDBGDMACR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) -#define BP_UARTDBGDMACR_RESERVED 3 -#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 -#define BF_UARTDBGDMACR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGDMACR_RESERVED) -#define BM_UARTDBGDMACR_DMAONERR 0x00000004 -#define BM_UARTDBGDMACR_TXDMAE 0x00000002 -#define BM_UARTDBGDMACR_RXDMAE 0x00000001 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h deleted file mode 100644 index 9145e22df32c..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * stmp37xx: USBCTL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTL_PHYS 0x80000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h deleted file mode 100644 index 1a2ae9cbdfed..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * stmp37xx: USBCTRL register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTRL_PHYS 0x80080000 diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h deleted file mode 100644 index b7fce0fbc560..000000000000 --- a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * stmp37xx: USBPHY register definitions - * - * Copyright (c) 2008 Freescale Semiconductor - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000) - -#define HW_USBPHY_PWD 0x0 - -#define HW_USBPHY_CTRL 0x30 -#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001 -#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0 -#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 -#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 -#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 -#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 -#define BM_USBPHY_CTRL_CLKGATE 0x40000000 -#define BM_USBPHY_CTRL_SFTRST 0x80000000 - -#define HW_USBPHY_STATUS 0x40 -#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 -#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c deleted file mode 100644 index a9aed06ff376..000000000000 --- a/arch/arm/mach-stmp37xx/stmp37xx.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Freescale STMP37XX platform support - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/irq.h> -#include <linux/io.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> - -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> - -#include <mach/stmp3xxx.h> -#include <mach/dma.h> - -#include <mach/platform.h> -#include <mach/regs-icoll.h> -#include <mach/regs-apbh.h> -#include <mach/regs-apbx.h> -#include "stmp37xx.h" - -/* - * IRQ handling - */ -static void stmp37xx_ack_irq(struct irq_data *d) -{ - /* Disable IRQ */ - stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); - - /* ACK current interrupt */ - __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); - - /* Barrier */ - (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); -} - -static void stmp37xx_mask_irq(struct irq_data *d) -{ - /* IRQ disable */ - stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); -} - -static void stmp37xx_unmask_irq(struct irq_data *d) -{ - /* IRQ enable */ - stmp3xxx_setl(0x04 << ((d->irq % 4) * 8), - REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10); -} - -static struct irq_chip stmp37xx_chip = { - .irq_ack = stmp37xx_ack_irq, - .irq_mask = stmp37xx_mask_irq, - .irq_unmask = stmp37xx_unmask_irq, -}; - -void __init stmp37xx_init_irq(void) -{ - stmp3xxx_init_irq(&stmp37xx_chip); -} - -/* - * DMA interrupt handling - */ -void stmp3xxx_arch_dma_enable_interrupt(int channel) -{ - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)), - REGS_APBH_BASE + HW_APBH_CTRL1); - break; - - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)), - REGS_APBX_BASE + HW_APBX_CTRL1); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt); - -void stmp3xxx_arch_dma_clear_interrupt(int channel) -{ - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), - REGS_APBH_BASE + HW_APBH_CTRL1); - break; - - case STMP3XXX_BUS_APBX: - stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), - REGS_APBX_BASE + HW_APBX_CTRL1); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt); - -int stmp3xxx_arch_dma_is_interrupt(int channel) -{ - int r = 0; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - - case STMP3XXX_BUS_APBX: - r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) & - (1 << STMP3XXX_DMA_CHANNEL(channel)); - break; - } - return r; -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt); - -void stmp3xxx_arch_dma_reset_channel(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - /* Reset channel and wait for it to complete */ - stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL, - REGS_APBH_BASE + HW_APBH_CTRL0); - while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) & - (chbit << BP_APBH_CTRL0_RESET_CHANNEL)) - cpu_relax(); - break; - - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL, - REGS_APBX_BASE + HW_APBX_CTRL0); - while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) & - (chbit << BP_APBX_CTRL0_RESET_CHANNEL)) - cpu_relax(); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel); - -void stmp3xxx_arch_dma_freeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze); - -void stmp3xxx_arch_dma_unfreeze(int channel) -{ - unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - case STMP3XXX_BUS_APBX: - stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0); - break; - } -} -EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze); - -/* - * The registers are all very closely mapped, so we might as well map them all - * with a single mapping - * - * Logical Physical - * f0000000 80000000 On-chip registers - * f1000000 00000000 32k on-chip SRAM - */ -static struct map_desc stmp37xx_io_desc[] __initdata = { - { - .virtual = (u32)STMP3XXX_REGS_BASE, - .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE), - .length = SZ_1M, - .type = MT_DEVICE - }, - { - .virtual = (u32)STMP3XXX_OCRAM_BASE, - .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE), - .length = STMP3XXX_OCRAM_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init stmp37xx_map_io(void) -{ - iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc)); -} diff --git a/arch/arm/mach-stmp37xx/stmp37xx.h b/arch/arm/mach-stmp37xx/stmp37xx.h deleted file mode 100644 index 0b75fb796a64..000000000000 --- a/arch/arm/mach-stmp37xx/stmp37xx.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X internal functions and data declarations - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __MACH_STMP37XX_H -#define __MACH_STMP37XX_H - -void stmp37xx_map_io(void); -void stmp37xx_init_irq(void); - -#endif /* __MACH_STMP37XX_H */ diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c deleted file mode 100644 index 311d8552d362..000000000000 --- a/arch/arm/mach-stmp37xx/stmp37xx_devb.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Freescale STMP37XX development board support - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include <mach/stmp3xxx.h> -#include <mach/pins.h> -#include <mach/pinmux.h> -#include "stmp37xx.h" - -/* - * List of STMP37xx development board specific devices - */ -static struct platform_device *stmp37xx_devb_devices[] = { - &stmp3xxx_dbguart, - &stmp3xxx_appuart, -}; - -static struct pin_desc dbguart_pins_0[] = { - { PINID_PWM0, PIN_FUN3, }, - { PINID_PWM1, PIN_FUN3, }, -}; - -struct pin_desc appuart_pins_0[] = { - { PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, - { PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, }, -}; - -static struct pin_group appuart_pins[] = { - [0] = { - .pins = appuart_pins_0, - .nr_pins = ARRAY_SIZE(appuart_pins_0), - }, - /* 37xx has the only app uart */ -}; - -static struct pin_group dbguart_pins[] = { - [0] = { - .pins = dbguart_pins_0, - .nr_pins = ARRAY_SIZE(dbguart_pins_0), - }, -}; - -static int dbguart_pins_control(int id, int request) -{ - int r = 0; - - if (request) - r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart"); - else - stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart"); - return r; -} - - -static void __init stmp37xx_devb_init(void) -{ - stmp3xxx_pinmux_init(NR_REAL_IRQS); - - /* Init STMP3xxx platform */ - stmp3xxx_init(); - - stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control; - stmp3xxx_appuart.dev.platform_data = appuart_pins; - - /* Add STMP37xx development board devices */ - platform_add_devices(stmp37xx_devb_devices, - ARRAY_SIZE(stmp37xx_devb_devices)); -} - -MACHINE_START(STMP37XX, "STMP37XX") - .boot_params = 0x40000100, - .map_io = stmp37xx_map_io, - .init_irq = stmp37xx_init_irq, - .timer = &stmp3xxx_timer, - .init_machine = stmp37xx_devb_init, -MACHINE_END diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c index e0a8d609afe1..a96babe83771 100644 --- a/arch/arm/mach-tcc8k/time.c +++ b/arch/arm/mach-tcc8k/time.c @@ -25,19 +25,6 @@ static void __iomem *timer_base; -static cycle_t tcc_get_cycles(struct clocksource *cs) -{ - return __raw_readl(timer_base + TC32MCNT_OFFS); -} - -static struct clocksource clocksource_tcc = { - .name = "tcc_tc32", - .rating = 200, - .read = tcc_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static int tcc_set_next_event(unsigned long evt, struct clock_event_device *unused) { @@ -102,7 +89,8 @@ static int __init tcc_clockevent_init(struct clk *clock) { unsigned int c = clk_get_rate(clock); - clocksource_register_hz(&clocksource_tcc, c); + clocksource_mmio_init(timer_base + TC32MCNT_OFFS, "tcc_tc32", c, + 200, 32, clocksource_mmio_readl_up); clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC, clockevent_tcc.shift); diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h index cc115174899b..425b42e91ef6 100644 --- a/arch/arm/mach-tegra/include/mach/barriers.h +++ b/arch/arm/mach-tegra/include/mach/barriers.h @@ -23,7 +23,7 @@ #include <asm/outercache.h> -#define rmb() dmb() +#define rmb() dsb() #define wmb() do { dsb(); outer_sync(); } while (0) #define mb() wmb() diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h deleted file mode 100644 index c8221b38ee7c..000000000000 --- a/arch/arm/mach-tegra/include/mach/smp.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef ASMARM_ARCH_SMP_H -#define ASMARM_ARCH_SMP_H - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index ec1f68924edf..b8ae3c978dee 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -20,6 +20,7 @@ #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> #include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/smp_scu.h> @@ -122,6 +123,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) cpu_set(i, cpu_possible_map); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 0fcb1eb4214d..90350420c4e9 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -98,11 +98,6 @@ static void tegra_timer_set_mode(enum clock_event_mode mode, } } -static cycle_t tegra_clocksource_read(struct clocksource *cs) -{ - return timer_readl(TIMERUS_CNTR_1US); -} - static struct clock_event_device tegra_clockevent = { .name = "timer0", .rating = 300, @@ -111,14 +106,6 @@ static struct clock_event_device tegra_clockevent = { .set_mode = tegra_timer_set_mode, }; -static struct clocksource tegra_clocksource = { - .name = "timer_us", - .rating = 300, - .read = tegra_clocksource_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static DEFINE_CLOCK_DATA(cd); /* @@ -234,7 +221,8 @@ static void __init tegra_init_timer(void) init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32, 1000000, SC_MULT, SC_SHIFT); - if (clocksource_register_hz(&tegra_clocksource, 1000000)) { + if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { printk(KERN_ERR "Failed to register clocksource\n"); BUG(); } diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 3ec58bd2d6e4..891cf44591e0 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -333,20 +333,6 @@ static struct irqaction u300_timer_irq = { .handler = u300_timer_interrupt, }; -/* Use general purpose timer 2 as clock source */ -static cycle_t u300_get_cycles(struct clocksource *cs) -{ - return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); -} - -static struct clocksource clocksource_u300_1mhz = { - .name = "GPT2", - .rating = 300, /* Reasonably fast and accurate clock source */ - .read = u300_get_cycles, - .mask = CLOCKSOURCE_MASK(32), /* 32 bits */ - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - /* * Override the global weak sched_clock symbol with this * local implementation which uses the clocksource to get some @@ -422,7 +408,9 @@ static void __init u300_timer_init(void) writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); - if (clocksource_register_hz(&clocksource_u300_1mhz, rate)) + /* Use general purpose timer 2 as clock source */ + if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC, + "GPT2", rate, 300, 32, clocksource_mmio_readl_up)) printk(KERN_ERR "timer: failed to initialize clock " "source %s\n", clocksource_u300_1mhz.name); diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h deleted file mode 100644 index ca2b15b1b3b1..000000000000 --- a/arch/arm/mach-ux500/include/mach/smp.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is based ARM realview platform. - * Copyright (C) ARM Limited. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#ifndef ASMARM_ARCH_SMP_H -#define ASMARM_ARCH_SMP_H - -#include <asm/hardware/gic.h> - -/* This is required to wakeup the secondary core */ -extern void u8500_secondary_startup(void); - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} -#endif diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 4fff4d408417..0c527fe2cebb 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -18,10 +18,14 @@ #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> #include <asm/smp_scu.h> #include <mach/hardware.h> #include <mach/setup.h> +/* This is called from headsmp.S to wakeup the secondary core */ +extern void u8500_secondary_startup(void); + /* * control for which core is the next to come out of the secondary * boot "holding pen" @@ -94,7 +98,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) */ write_pen_release(cpu); - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { @@ -162,6 +166,8 @@ void __init smp_init_cpus(void) for (i = 0; i < ncores; i++) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } void __init platform_smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index eb7ffa0ee8b5..0c99cf076c63 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -32,6 +32,7 @@ #include <linux/io.h> #include <linux/gfp.h> #include <linux/clkdev.h> +#include <linux/mtd/physmap.h> #include <asm/system.h> #include <asm/irq.h> @@ -42,7 +43,6 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/irq.h> #include <asm/mach/time.h> #include <asm/mach/map.h> @@ -190,27 +190,7 @@ void __init versatile_map_io(void) #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET) -static int versatile_flash_init(void) -{ - u32 val; - - val = __raw_readl(VERSATILE_FLASHCTRL); - val &= ~VERSATILE_FLASHPROG_FLVPPEN; - __raw_writel(val, VERSATILE_FLASHCTRL); - - return 0; -} - -static void versatile_flash_exit(void) -{ - u32 val; - - val = __raw_readl(VERSATILE_FLASHCTRL); - val &= ~VERSATILE_FLASHPROG_FLVPPEN; - __raw_writel(val, VERSATILE_FLASHCTRL); -} - -static void versatile_flash_set_vpp(int on) +static void versatile_flash_set_vpp(struct platform_device *pdev, int on) { u32 val; @@ -222,11 +202,8 @@ static void versatile_flash_set_vpp(int on) __raw_writel(val, VERSATILE_FLASHCTRL); } -static struct flash_platform_data versatile_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data versatile_flash_data = { .width = 4, - .init = versatile_flash_init, - .exit = versatile_flash_exit, .set_vpp = versatile_flash_set_vpp, }; @@ -237,7 +214,7 @@ static struct resource versatile_flash_resource = { }; static struct platform_device versatile_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = 0, .dev = { .platform_data = &versatile_flash_data, @@ -375,6 +352,10 @@ static struct clk ref24_clk = { .rate = 24000000, }; +static struct clk sp804_clk = { + .rate = 1000000, +}; + static struct clk dummy_apb_pclk; static struct clk_lookup lookups[] = { @@ -411,7 +392,10 @@ static struct clk_lookup lookups[] = { }, { /* CLCD */ .dev_id = "dev:20", .clk = &osc4_clk, - } + }, { /* SP804 timers */ + .dev_id = "sp804", + .clk = &sp804_clk, + }, }; /* @@ -764,8 +748,8 @@ static void __init versatile_timer_init(void) writel(0, TIMER2_VA_BASE + TIMER_CTRL); writel(0, TIMER3_VA_BASE + TIMER_CTRL); - sp804_clocksource_init(TIMER3_VA_BASE); - sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1); + sp804_clocksource_init(TIMER3_VA_BASE, "timer3"); + sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0"); } struct sys_timer versatile_timer = { diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index ebc22e759325..765a71ff7f3b 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -71,8 +71,9 @@ static void __init ct_ca9x4_timer_init(void) writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL); writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL); - sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1)); - sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0); + sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1"); + sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0, + "ct-timer0"); } static struct sys_timer ct_ca9x4_timer = { @@ -141,10 +142,22 @@ static struct clk osc1_clk = { .rate = 24000000, }; +static struct clk ct_sp804_clk = { + .rate = 1000000, +}; + static struct clk_lookup lookups[] = { { /* CLCD */ .dev_id = "ct:clcd", .clk = &osc1_clk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .con_id = "ct-timer0", + .clk = &ct_sp804_clk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .con_id = "ct-timer1", + .clk = &ct_sp804_clk, }, }; @@ -210,6 +223,8 @@ static void ct_ca9x4_init_cpu_map(void) for (i = 0; i < ncores; ++i) set_cpu_possible(i, true); + + set_smp_cross_call(gic_raise_softirq); } static void ct_ca9x4_smp_enable(unsigned int max_cpus) diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h deleted file mode 100644 index 4c05e4a9713a..000000000000 --- a/arch/arm/mach-vexpress/include/mach/smp.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __MACH_SMP_H -#define __MACH_SMP_H - -#include <asm/hardware/gic.h> - -/* - * We use IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} -#endif diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index ba46e8e07437..285edcd2da2a 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -13,11 +13,11 @@ #include <linux/sysdev.h> #include <linux/usb/isp1760.h> #include <linux/clkdev.h> +#include <linux/mtd/physmap.h> #include <asm/mach-types.h> #include <asm/sizes.h> #include <asm/mach/arch.h> -#include <asm/mach/flash.h> #include <asm/mach/map.h> #include <asm/mach/time.h> #include <asm/hardware/arm_timer.h> @@ -65,8 +65,9 @@ static void __init v2m_timer_init(void) writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL); writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL); - sp804_clocksource_init(MMIO_P2V(V2M_TIMER1)); - sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0); + sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1"); + sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0, + "v2m-timer0"); } static struct sys_timer v2m_timer = { @@ -206,27 +207,13 @@ static struct platform_device v2m_usb_device = { .dev.platform_data = &v2m_usb_config, }; -static int v2m_flash_init(void) -{ - writel(0, MMIO_P2V(V2M_SYS_FLASH)); - return 0; -} - -static void v2m_flash_exit(void) -{ - writel(0, MMIO_P2V(V2M_SYS_FLASH)); -} - -static void v2m_flash_set_vpp(int on) +static void v2m_flash_set_vpp(struct platform_device *pdev, int on) { writel(on != 0, MMIO_P2V(V2M_SYS_FLASH)); } -static struct flash_platform_data v2m_flash_data = { - .map_name = "cfi_probe", +static struct physmap_flash_data v2m_flash_data = { .width = 4, - .init = v2m_flash_init, - .exit = v2m_flash_exit, .set_vpp = v2m_flash_set_vpp, }; @@ -243,7 +230,7 @@ static struct resource v2m_flash_resources[] = { }; static struct platform_device v2m_flash_device = { - .name = "armflash", + .name = "physmap-flash", .id = -1, .resource = v2m_flash_resources, .num_resources = ARRAY_SIZE(v2m_flash_resources), @@ -333,6 +320,10 @@ static struct clk osc2_clk = { .rate = 24000000, }; +static struct clk v2m_sp804_clk = { + .rate = 1000000, +}; + static struct clk dummy_apb_pclk; static struct clk_lookup v2m_lookups[] = { @@ -363,6 +354,14 @@ static struct clk_lookup v2m_lookups[] = { }, { /* CLCD */ .dev_id = "mb:clcd", .clk = &osc1_clk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .con_id = "v2m-timer0", + .clk = &v2m_sp804_clk, + }, { /* SP804 timers */ + .dev_id = "sp804", + .con_id = "v2m-timer1", + .clk = &v2m_sp804_clk, }, }; diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c index 4b089cb930dc..a2c4e2d0a0d4 100644 --- a/arch/arm/mach-w90x900/time.c +++ b/arch/arm/mach-w90x900/time.c @@ -43,7 +43,6 @@ #define PRESCALE 0x63 /* Divider = prescale + 1 */ #define TDR_SHIFT 24 -#define TDR_MASK ((1 << TDR_SHIFT) - 1) static unsigned int timer0_load; @@ -143,19 +142,6 @@ static void __init nuc900_clockevents_init(void) clockevents_register_device(&nuc900_clockevent_device); } -static cycle_t nuc900_get_cycles(struct clocksource *cs) -{ - return (~__raw_readl(REG_TDR1)) & TDR_MASK; -} - -static struct clocksource clocksource_nuc900 = { - .name = "nuc900-timer1", - .rating = 200, - .read = nuc900_get_cycles, - .mask = CLOCKSOURCE_MASK(TDR_SHIFT), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static void __init nuc900_clocksource_init(void) { unsigned int val; @@ -175,7 +161,8 @@ static void __init nuc900_clocksource_init(void) val |= (COUNTEN | PERIOD | PRESCALE); __raw_writel(val, REG_TCSR1); - clocksource_register_hz(&clocksource_nuc900, rate); + clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200, + TDR_SHIFT, clocksource_mmio_readl_down); } static void __init nuc900_timer_init(void) diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index f1b799802858..1a8d4aa821be 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -275,7 +275,8 @@ void __sync_icache_dcache(pte_t pteval) * kernel cache lines for later. Otherwise, we assume we have * aliasing mappings. * - * Note that we disable the lazy flush for SMP. + * Note that we disable the lazy flush for SMP configurations where + * the cache maintenance operations are not automatically broadcasted. */ void flush_dcache_page(struct page *page) { diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index e5f6fc428348..76f82ae44efb 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -201,6 +201,20 @@ static void __init arm_bootmem_init(unsigned long start_pfn, } } +#ifdef CONFIG_ZONE_DMA +static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole, + unsigned long dma_size) +{ + if (size[0] <= dma_size) + return; + + size[ZONE_NORMAL] = size[0] - dma_size; + size[ZONE_DMA] = dma_size; + hole[ZONE_NORMAL] = hole[0]; + hole[ZONE_DMA] = 0; +} +#endif + static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, unsigned long max_high) { @@ -243,11 +257,18 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, #endif } +#ifdef ARM_DMA_ZONE_SIZE +#ifndef CONFIG_ZONE_DMA +#error ARM_DMA_ZONE_SIZE set but no DMA zone to limit allocations +#endif + /* * Adjust the sizes according to any special requirements for * this machine type. */ - arch_adjust_zones(zone_size, zhole_size); + arm_adjust_dma_zone(zone_size, zhole_size, + ARM_DMA_ZONE_SIZE >> PAGE_SHIFT); +#endif free_area_init_node(0, zone_size, min, zhole_size); } @@ -392,7 +413,7 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn) * Convert start_pfn/end_pfn to a struct page pointer. */ start_pg = pfn_to_page(start_pfn - 1) + 1; - end_pg = pfn_to_page(end_pfn); + end_pg = pfn_to_page(end_pfn - 1) + 1; /* * Convert to physical addresses, and @@ -426,6 +447,14 @@ static void __init free_unused_memmap(struct meminfo *mi) bank_start = bank_pfn_start(bank); +#ifdef CONFIG_SPARSEMEM + /* + * Take care not to free memmap entries that don't exist + * due to SPARSEMEM sections which aren't present. + */ + bank_start = min(bank_start, + ALIGN(prev_bank_end, PAGES_PER_SECTION)); +#endif /* * If we had a previous bank, and there is a space * between the current bank and the previous, free it. @@ -440,6 +469,12 @@ static void __init free_unused_memmap(struct meminfo *mi) */ prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES); } + +#ifdef CONFIG_SPARSEMEM + if (!IS_ALIGNED(prev_bank_end, PAGES_PER_SECTION)) + free_memmap(prev_bank_end, + ALIGN(prev_bank_end, PAGES_PER_SECTION)); +#endif } static void __init free_highpages(void) diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c index d69d343ff61f..d3467f818c33 100644 --- a/arch/arm/plat-mxc/epit.c +++ b/arch/arm/plat-mxc/epit.c @@ -83,26 +83,12 @@ static void epit_irq_acknowledge(void) __raw_writel(EPITSR_OCIF, timer_base + EPITSR); } -static cycle_t epit_read(struct clocksource *cs) -{ - return 0 - __raw_readl(timer_base + EPITCNR); -} - -static struct clocksource clocksource_epit = { - .name = "epit", - .rating = 200, - .read = epit_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static int __init epit_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - clocksource_register_hz(&clocksource_epit, c); - - return 0; + return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32, + clocksource_mmio_readl_down); } /* clock event */ diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 2237ff8b434f..e4ac94a86832 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -106,56 +106,32 @@ static void gpt_irq_acknowledge(void) __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); } -static cycle_t dummy_get_cycles(struct clocksource *cs) -{ - return 0; -} - -static cycle_t mx1_2_get_cycles(struct clocksource *cs) -{ - return __raw_readl(timer_base + MX1_2_TCN); -} - -static cycle_t v2_get_cycles(struct clocksource *cs) -{ - return __raw_readl(timer_base + V2_TCN); -} - -static struct clocksource clocksource_mxc = { - .name = "mxc_timer1", - .rating = 200, - .read = dummy_get_cycles, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; +static void __iomem *sched_clock_reg; static DEFINE_CLOCK_DATA(cd); unsigned long long notrace sched_clock(void) { - cycle_t cyc = clocksource_mxc.read(&clocksource_mxc); + cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; return cyc_to_sched_clock(&cd, cyc, (u32)~0); } static void notrace mxc_update_sched_clock(void) { - cycle_t cyc = clocksource_mxc.read(&clocksource_mxc); + cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; update_sched_clock(&cd, cyc, (u32)~0); } static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); + void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); - if (timer_is_v2()) - clocksource_mxc.read = v2_get_cycles; - else - clocksource_mxc.read = mx1_2_get_cycles; + sched_clock_reg = reg; init_sched_clock(&cd, mxc_update_sched_clock, 32, c); - clocksource_register_hz(&clocksource_mxc, c); - - return 0; + return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, + clocksource_mmio_readl_up); } /* clock event */ diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig index 187f4e84bb22..18296ee68802 100644 --- a/arch/arm/plat-nomadik/Kconfig +++ b/arch/arm/plat-nomadik/Kconfig @@ -5,6 +5,7 @@ config PLAT_NOMADIK bool depends on ARCH_NOMADIK || ARCH_U8500 + select CLKSRC_MMIO default y help Common platform code for Nomadik and other ST-Ericsson diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c index 41723402006b..ef74e157a9d5 100644 --- a/arch/arm/plat-nomadik/timer.c +++ b/arch/arm/plat-nomadik/timer.c @@ -26,29 +26,6 @@ void __iomem *mtu_base; /* Assigned by machine code */ /* - * Kernel assumes that sched_clock can be called early - * but the MTU may not yet be initialized. - */ -static cycle_t nmdk_read_timer_dummy(struct clocksource *cs) -{ - return 0; -} - -/* clocksource: MTU decrements, so we negate the value being read. */ -static cycle_t nmdk_read_timer(struct clocksource *cs) -{ - return -readl(mtu_base + MTU_VAL(0)); -} - -static struct clocksource nmdk_clksrc = { - .name = "mtu_0", - .rating = 200, - .read = nmdk_read_timer_dummy, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/* * Override the global weak sched_clock symbol with this * local implementation which uses the clocksource to get some * better resolution when scheduling the kernel. @@ -172,12 +149,10 @@ void __init nmdk_timer_init(void) writel(0, mtu_base + MTU_BGLR(0)); writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); - /* Now the clock source is ready */ - nmdk_clksrc.read = nmdk_read_timer; - - if (clocksource_register_hz(&nmdk_clksrc, rate)) + if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0", + rate, 200, 32, clocksource_mmio_readl_down)) pr_err("timer: failed to initialize clock source %s\n", - nmdk_clksrc.name); + "mtu_0"); init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate); diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index cd5f993612fd..e9c0efc5d4af 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -12,6 +12,7 @@ choice config ARCH_OMAP1 bool "TI OMAP1" select CLKDEV_LOOKUP + select CLKSRC_MMIO help "Systems based on omap7xx, omap15xx or omap16xx" diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index d2adcdda23cf..bd9e32187eab 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -17,7 +17,7 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/err.h> #include <linux/clk.h> #include <linux/io.h> @@ -1372,9 +1372,7 @@ static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { .resume_noirq = omap_mpuio_resume_noirq, }; -/* use platform_driver for this, now that there's no longer any - * point to sys_device (other than not disturbing old code). - */ +/* use platform_driver for this. */ static struct platform_driver omap_mpuio_driver = { .driver = { .name = "mpuio", @@ -1745,7 +1743,7 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev) } #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) -static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) +static int omap_gpio_suspend(void) { int i; @@ -1795,12 +1793,12 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) return 0; } -static int omap_gpio_resume(struct sys_device *dev) +static void omap_gpio_resume(void) { int i; if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) - return 0; + return; for (i = 0; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; @@ -1836,21 +1834,13 @@ static int omap_gpio_resume(struct sys_device *dev) __raw_writel(bank->saved_wakeup, wake_set); spin_unlock_irqrestore(&bank->lock, flags); } - - return 0; } -static struct sysdev_class omap_gpio_sysclass = { - .name = "gpio", +static struct syscore_ops omap_gpio_syscore_ops = { .suspend = omap_gpio_suspend, .resume = omap_gpio_resume, }; -static struct sys_device omap_gpio_device = { - .id = 0, - .cls = &omap_gpio_sysclass, -}; - #endif #ifdef CONFIG_ARCH_OMAP2PLUS @@ -2108,21 +2098,14 @@ postcore_initcall(omap_gpio_drv_reg); static int __init omap_gpio_sysinit(void) { - int ret = 0; - mpuio_init(); #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) - if (cpu_is_omap16xx() || cpu_class_is_omap2()) { - if (ret == 0) { - ret = sysdev_class_register(&omap_gpio_sysclass); - if (ret == 0) - ret = sysdev_register(&omap_gpio_device); - } - } + if (cpu_is_omap16xx() || cpu_class_is_omap2()) + register_syscore_ops(&omap_gpio_syscore_ops); #endif - return ret; + return 0; } arch_initcall(omap_gpio_sysinit); diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h index 3e6327016b40..3083195123ea 100644 --- a/arch/arm/plat-omap/include/plat/flash.h +++ b/arch/arm/plat-omap/include/plat/flash.h @@ -11,6 +11,6 @@ #include <linux/mtd/map.h> -extern void omap1_set_vpp(struct map_info *map, int enable); +extern void omap1_set_vpp(struct platform_device *pdev, int enable); #endif diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h deleted file mode 100644 index 7a10257909ef..000000000000 --- a/arch/arm/plat-omap/include/plat/smp.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * OMAP4 machine specific smp.h - * - * Copyright (C) 2009 Texas Instruments, Inc. - * - * Author: - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * - * Interface functions needed for the SMP. This file is based on arm - * realview smp platform. - * Copyright (c) 2003 ARM Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef OMAP_ARCH_SMP_H -#define OMAP_ARCH_SMP_H - -#include <asm/hardware/gic.h> - -/* Needed for secondary core boot */ -extern void omap_secondary_startup(void); -extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); -extern void omap_auxcoreboot_addr(u32 cpu_addr); -extern u32 omap_read_auxcoreboot0(void); - -/* - * We use Soft IRQ1 as the IPI - */ -static inline void smp_cross_call(const struct cpumask *mask, int ipi) -{ - gic_raise_softirq(mask, ipi); -} - -#endif diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 8a51fd58f656..34fc31ee9081 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -793,6 +793,8 @@ static irqreturn_t iommu_fault_handler(int irq, void *data) clk_enable(obj->clk); errs = iommu_report_fault(obj, &da); clk_disable(obj->clk); + if (errs == 0) + return IRQ_HANDLED; /* Fault callback or TLB/PTE Dynamic loading */ if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index 9bbda9acb73b..a37b8eb65b76 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -536,6 +536,28 @@ int omap_early_device_register(struct omap_device *od) return 0; } +static int _od_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + + return omap_device_idle(pdev); +} + +static int _od_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + + return omap_device_enable(pdev); +} + +static struct dev_power_domain omap_device_power_domain = { + .ops = { + .runtime_suspend = _od_runtime_suspend, + .runtime_resume = _od_runtime_resume, + USE_PLATFORM_PM_SLEEP_OPS + } +}; + /** * omap_device_register - register an omap_device with one omap_hwmod * @od: struct omap_device * to register @@ -549,6 +571,7 @@ int omap_device_register(struct omap_device *od) pr_debug("omap_device: %s: registering\n", od->pdev.name); od->pdev.dev.parent = &omap_device_parent; + od->pdev.dev.pwr_domain = &omap_device_power_domain; return platform_device_register(&od->pdev); } diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 742b0323c57b..69a61367e4b8 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -81,24 +81,6 @@ static void __init setup_sched_clock(unsigned long tclk) } /* - * Clocksource handling. - */ -static cycle_t orion_clksrc_read(struct clocksource *cs) -{ - return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF); -} - -static struct clocksource orion_clksrc = { - .name = "orion_clocksource", - .rating = 300, - .read = orion_clksrc_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - - - -/* * Clockevent handling. */ static int @@ -247,7 +229,8 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF); u = readl(timer_base + TIMER_CTRL_OFF); writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF); - clocksource_register_hz(&orion_clksrc, tclk); + clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource", + tclk, 300, 32, clocksource_mmio_readl_down); /* * Setup clockevent timer (interrupt-driven). diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c index dce088f45678..48ebb9479b61 100644 --- a/arch/arm/plat-pxa/gpio.c +++ b/arch/arm/plat-pxa/gpio.c @@ -15,7 +15,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/io.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/slab.h> #include <mach/gpio.h> @@ -295,7 +295,7 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) } #ifdef CONFIG_PM -static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) +static int pxa_gpio_suspend(void) { struct pxa_gpio_chip *c; int gpio; @@ -312,7 +312,7 @@ static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int pxa_gpio_resume(struct sys_device *dev) +static void pxa_gpio_resume(void) { struct pxa_gpio_chip *c; int gpio; @@ -326,22 +326,13 @@ static int pxa_gpio_resume(struct sys_device *dev) __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET); __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET); } - return 0; } #else #define pxa_gpio_suspend NULL #define pxa_gpio_resume NULL #endif -struct sysdev_class pxa_gpio_sysclass = { - .name = "gpio", +struct syscore_ops pxa_gpio_syscore_ops = { .suspend = pxa_gpio_suspend, .resume = pxa_gpio_resume, }; - -static int __init pxa_gpio_init(void) -{ - return sysdev_class_register(&pxa_gpio_sysclass); -} - -core_initcall(pxa_gpio_init); diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c index a9aa5ad3f4eb..be12eadcce20 100644 --- a/arch/arm/plat-pxa/mfp.c +++ b/arch/arm/plat-pxa/mfp.c @@ -17,7 +17,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/sysdev.h> #include <plat/mfp.h> diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 27ea852e3370..c10d10c56e2e 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c @@ -22,7 +22,7 @@ #include <linux/sched.h> #include <linux/spinlock.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> #include <linux/slab.h> #include <linux/errno.h> #include <linux/io.h> @@ -1195,19 +1195,12 @@ int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *d EXPORT_SYMBOL(s3c2410_dma_getposition); -static inline struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev) -{ - return container_of(dev, struct s3c2410_dma_chan, dev); -} - -/* system device class */ +/* system core operations */ #ifdef CONFIG_PM -static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) +static void s3c2410_dma_suspend_chan(s3c2410_dma_chan *cp) { - struct s3c2410_dma_chan *cp = to_dma_chan(dev); - printk(KERN_DEBUG "suspending dma channel %d\n", cp->number); if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) { @@ -1222,13 +1215,21 @@ static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) s3c2410_dma_dostop(cp); } +} + +static int s3c2410_dma_suspend(void) +{ + struct s3c2410_dma_chan *cp = s3c2410_chans; + int channel; + + for (channel = 0; channel < dma_channels; cp++, channel++) + s3c2410_dma_suspend_chan(cp); return 0; } -static int s3c2410_dma_resume(struct sys_device *dev) +static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp) { - struct s3c2410_dma_chan *cp = to_dma_chan(dev); unsigned int no = cp->number | DMACH_LOW_LEVEL; /* restore channel's hardware configuration */ @@ -1249,13 +1250,21 @@ static int s3c2410_dma_resume(struct sys_device *dev) return 0; } +static void s3c2410_dma_resume(void) +{ + struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1; + int channel; + + for (channel = dma_channels - 1; channel >= 0; cp++, channel--) + s3c2410_dma_resume_chan(cp); +} + #else #define s3c2410_dma_suspend NULL #define s3c2410_dma_resume NULL #endif /* CONFIG_PM */ -struct sysdev_class dma_sysclass = { - .name = "s3c24xx-dma", +struct syscore_ops dma_syscore_ops = { .suspend = s3c2410_dma_suspend, .resume = s3c2410_dma_resume, }; @@ -1269,39 +1278,14 @@ static void s3c2410_dma_cache_ctor(void *p) /* initialisation code */ -static int __init s3c24xx_dma_sysclass_init(void) +static int __init s3c24xx_dma_syscore_init(void) { - int ret = sysdev_class_register(&dma_sysclass); - - if (ret != 0) - printk(KERN_ERR "dma sysclass registration failed\n"); - - return ret; -} - -core_initcall(s3c24xx_dma_sysclass_init); - -static int __init s3c24xx_dma_sysdev_register(void) -{ - struct s3c2410_dma_chan *cp = s3c2410_chans; - int channel, ret; - - for (channel = 0; channel < dma_channels; cp++, channel++) { - cp->dev.cls = &dma_sysclass; - cp->dev.id = channel; - ret = sysdev_register(&cp->dev); - - if (ret) { - printk(KERN_ERR "error registering dev for dma %d\n", - channel); - return ret; - } - } + register_syscore_ops(&dma_syscore_ops); return 0; } -late_initcall(s3c24xx_dma_sysdev_register); +late_initcall(s3c24xx_dma_syscore_init); int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq, unsigned int stride) diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c index c3624d898630..0efb2e2848c8 100644 --- a/arch/arm/plat-s3c24xx/irq-pm.c +++ b/arch/arm/plat-s3c24xx/irq-pm.c @@ -14,7 +14,6 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> #include <linux/irq.h> #include <plat/cpu.h> @@ -65,7 +64,7 @@ static unsigned long save_extint[3]; static unsigned long save_eintflt[4]; static unsigned long save_eintmask; -int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) +int s3c24xx_irq_suspend(void) { unsigned int i; @@ -81,7 +80,7 @@ int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) return 0; } -int s3c24xx_irq_resume(struct sys_device *dev) +void s3c24xx_irq_resume(void) { unsigned int i; @@ -93,6 +92,4 @@ int s3c24xx_irq_resume(struct sys_device *dev) s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); __raw_writel(save_eintmask, S3C24XX_EINTMASK); - - return 0; } diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c index 5259ad458bc8..327acb3a4464 100644 --- a/arch/arm/plat-s5p/irq-pm.c +++ b/arch/arm/plat-s5p/irq-pm.c @@ -16,7 +16,6 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/interrupt.h> -#include <linux/sysdev.h> #include <plat/cpu.h> #include <plat/irqs.h> @@ -77,17 +76,15 @@ static struct sleep_save eint_save[] = { SAVE_ITEM(S5P_EINT_MASK(3)), }; -int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) +int s3c24xx_irq_suspend(void) { s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save)); return 0; } -int s3c24xx_irq_resume(struct sys_device *dev) +void s3c24xx_irq_resume(void) { s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save)); - - return 0; } diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c index 8090403eec0f..899a8cc011ff 100644 --- a/arch/arm/plat-s5p/s5p-time.c +++ b/arch/arm/plat-s5p/s5p-time.c @@ -290,7 +290,7 @@ static void __init s5p_clockevent_init(void) setup_irq(irq_number, &s5p_clock_event_irq); } -static cycle_t s5p_timer_read(struct clocksource *cs) +static void __iomem *s5p_timer_reg(void) { unsigned long offset = 0; @@ -308,10 +308,17 @@ static cycle_t s5p_timer_read(struct clocksource *cs) default: printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id); - return 0; + return NULL; } - return (cycle_t) ~__raw_readl(S3C_TIMERREG(offset)); + return S3C_TIMERREG(offset); +} + +static cycle_t s5p_timer_read(struct clocksource *cs) +{ + void __iomem *reg = s5p_timer_reg(); + + return (cycle_t) (reg ? ~__raw_readl(reg) : 0); } /* @@ -325,53 +332,22 @@ static DEFINE_CLOCK_DATA(cd); unsigned long long notrace sched_clock(void) { - u32 cyc; - unsigned long offset = 0; - - switch (timer_source.source_id) { - case S5P_PWM0: - case S5P_PWM1: - case S5P_PWM2: - case S5P_PWM3: - offset = (timer_source.source_id * 0x0c) + 0x14; - break; - - case S5P_PWM4: - offset = 0x40; - break; + void __iomem *reg = s5p_timer_reg(); - default: - printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id); + if (!reg) return 0; - } - cyc = ~__raw_readl(S3C_TIMERREG(offset)); - return cyc_to_sched_clock(&cd, cyc, (u32)~0); + return cyc_to_sched_clock(&cd, ~__raw_readl(reg), (u32)~0); } static void notrace s5p_update_sched_clock(void) { - u32 cyc; - unsigned long offset = 0; + void __iomem *reg = s5p_timer_reg(); - switch (timer_source.source_id) { - case S5P_PWM0: - case S5P_PWM1: - case S5P_PWM2: - case S5P_PWM3: - offset = (timer_source.source_id * 0x0c) + 0x14; - break; - - case S5P_PWM4: - offset = 0x40; - break; - - default: - printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id); - } + if (!reg) + return; - cyc = ~__raw_readl(S3C_TIMERREG(offset)); - update_sched_clock(&cd, cyc, (u32)~0); + update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0); } struct clocksource time_clocksource = { diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index cedfff51c82b..3aedac0034ba 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -68,6 +68,12 @@ extern void s3c24xx_init_uartdevs(char *name, struct sys_timer; extern struct sys_timer s3c24xx_timer; +extern struct syscore_ops s3c2410_pm_syscore_ops; +extern struct syscore_ops s3c2412_pm_syscore_ops; +extern struct syscore_ops s3c2416_pm_syscore_ops; +extern struct syscore_ops s3c244x_pm_syscore_ops; +extern struct syscore_ops s3c64xx_irq_syscore_ops; + /* system device classes */ extern struct sysdev_class s3c2410_sysclass; diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 937cc2ace517..7fb6f6be8c81 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -103,14 +103,16 @@ extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); #ifdef CONFIG_PM extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); -extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); -extern int s3c24xx_irq_resume(struct sys_device *dev); +extern int s3c24xx_irq_suspend(void); +extern void s3c24xx_irq_resume(void); #else #define s3c_irqext_wake NULL #define s3c24xx_irq_suspend NULL #define s3c24xx_irq_resume NULL #endif +extern struct syscore_ops s3c24xx_irq_syscore_ops; + /* PM debug functions */ #ifdef CONFIG_SAMSUNG_PM_DEBUG diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c index bdbd7ec9cb6b..6fa474cb398e 100644 --- a/arch/arm/plat-spear/clock.c +++ b/arch/arm/plat-spear/clock.c @@ -903,6 +903,11 @@ void recalc_root_clocks(void) spin_unlock_irqrestore(&clocks_lock, flags); } +void __init clk_init(void) +{ + recalc_root_clocks(); +} + #ifdef CONFIG_DEBUG_FS /* * debugfs support to trace clock tree hierarchy and attributes diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h index fcc0d0ad4a1f..0062bafef12d 100644 --- a/arch/arm/plat-spear/include/plat/clock.h +++ b/arch/arm/plat-spear/include/plat/clock.h @@ -224,6 +224,7 @@ struct clcd_rate_tbl { }; /* platform specific clock functions */ +void __init clk_init(void); void clk_register(struct clk_lookup *cl); void recalc_root_clocks(void); diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c index dbb6e4fff79d..0c77e4298675 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/plat-spear/time.c @@ -70,19 +70,6 @@ static void clockevent_set_mode(enum clock_event_mode mode, static int clockevent_next_event(unsigned long evt, struct clock_event_device *clk_event_dev); -static cycle_t clocksource_read_cycles(struct clocksource *cs) -{ - return (cycle_t) readw(gpt_base + COUNT(CLKSRC)); -} - -static struct clocksource clksrc = { - .name = "tmr1", - .rating = 200, /* its a pretty decent clock */ - .read = clocksource_read_cycles, - .mask = 0xFFFF, /* 16 bits */ - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - static void spear_clocksource_init(void) { u32 tick_rate; @@ -103,7 +90,8 @@ static void spear_clocksource_init(void) writew(val, gpt_base + CR(CLKSRC)); /* register the clocksource */ - clocksource_register_hz(&clksrc, tick_rate); + clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate, + 200, 16, clocksource_mmio_readw_up); } static struct clock_event_device clkevt = { diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig deleted file mode 100644 index 2cf37c35951b..000000000000 --- a/arch/arm/plat-stmp3xxx/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -if ARCH_STMP3XXX - -menu "Freescale STMP3xxx implementations" - -choice - prompt "Select STMP3xxx chip family" - -config ARCH_STMP37XX - bool "Freescale SMTP37xx" - select CPU_ARM926T - ---help--- - STMP37xx refers to 3700 through 3769 chips - -config ARCH_STMP378X - bool "Freescale STMP378x" - select CPU_ARM926T - ---help--- - STMP378x refers to 3780 through 3789 chips - -endchoice - -choice - prompt "Select STMP3xxx board type" - -config MACH_STMP37XX - depends on ARCH_STMP37XX - bool "Freescale STMP37xx development board" - -config MACH_STMP378X - depends on ARCH_STMP378X - bool "Freescale STMP378x development board" - -endchoice - -endmenu - -endif diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile deleted file mode 100644 index 31dd518f37a5..000000000000 --- a/arch/arm/plat-stmp3xxx/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the linux kernel. -# -# Object file lists. -obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c deleted file mode 100644 index 2e712e17ce72..000000000000 --- a/arch/arm/plat-stmp3xxx/clock.c +++ /dev/null @@ -1,1134 +0,0 @@ -/* - * Clock manipulation routines for Freescale STMP37XX/STMP378X - * - * Author: Vitaly Wool <vital@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#define DEBUG -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/spinlock.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/clkdev.h> - -#include <asm/mach-types.h> -#include <mach/platform.h> -#include <mach/regs-clkctrl.h> - -#include "clock.h" - -static DEFINE_SPINLOCK(clocks_lock); - -static struct clk osc_24M; -static struct clk pll_clk; -static struct clk cpu_clk; -static struct clk hclk; - -static int propagate_rate(struct clk *); - -static inline int clk_is_busy(struct clk *clk) -{ - return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit); -} - -static inline int clk_good(struct clk *clk) -{ - return clk && !IS_ERR(clk) && clk->ops; -} - -static int std_clk_enable(struct clk *clk) -{ - if (clk->enable_reg) { - u32 clk_reg = __raw_readl(clk->enable_reg); - if (clk->enable_negate) - clk_reg &= ~(1 << clk->enable_shift); - else - clk_reg |= (1 << clk->enable_shift); - __raw_writel(clk_reg, clk->enable_reg); - if (clk->enable_wait) - udelay(clk->enable_wait); - return 0; - } else - return -EINVAL; -} - -static int std_clk_disable(struct clk *clk) -{ - if (clk->enable_reg) { - u32 clk_reg = __raw_readl(clk->enable_reg); - if (clk->enable_negate) - clk_reg |= (1 << clk->enable_shift); - else - clk_reg &= ~(1 << clk->enable_shift); - __raw_writel(clk_reg, clk->enable_reg); - return 0; - } else - return -EINVAL; -} - -static int io_set_rate(struct clk *clk, u32 rate) -{ - u32 reg_frac, clkctrl_frac; - int i, ret = 0, mask = 0x1f; - - clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate; - - if (clkctrl_frac < 18 || clkctrl_frac > 35) { - ret = -EINVAL; - goto out; - } - - reg_frac = __raw_readl(clk->scale_reg); - reg_frac &= ~(mask << clk->scale_shift); - __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift), - clk->scale_reg); - if (clk->busy_reg) { - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) - ret = -ETIMEDOUT; - else - ret = 0; - } -out: - return ret; -} - -static long io_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate * 18; - int mask = 0x1f; - - rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; - clk->rate = rate; - - return rate; -} - -static long per_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - long div; - const int mask = 0xff; - - if (clk->enable_reg && - !(__raw_readl(clk->enable_reg) & clk->enable_shift)) - clk->rate = 0; - else { - div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; - if (div) - rate /= div; - clk->rate = rate; - } - - return clk->rate; -} - -static int per_set_rate(struct clk *clk, u32 rate) -{ - int ret = -EINVAL; - int div = (clk->parent->rate + rate - 1) / rate; - u32 reg_frac; - const int mask = 0xff; - int try = 10; - int i = -1; - - if (div == 0 || div > mask) - goto out; - - reg_frac = __raw_readl(clk->scale_reg); - reg_frac &= ~(mask << clk->scale_shift); - - while (try--) { - __raw_writel(reg_frac | (div << clk->scale_shift), - clk->scale_reg); - - if (clk->busy_reg) { - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - } - if (i) - break; - } - - if (!i) - ret = -ETIMEDOUT; - else - ret = 0; - -out: - if (ret != 0) - printk(KERN_ERR "%s: error %d\n", __func__, ret); - return ret; -} - -static long lcdif_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - long div; - const int mask = 0xff; - - div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask; - if (div) { - rate /= div; - div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) & - BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC; - rate /= div; - } - clk->rate = rate; - - return rate; -} - -static int lcdif_set_rate(struct clk *clk, u32 rate) -{ - int ret = 0; - /* - * On 3700, we can get most timings exact by modifying ref_pix - * and the divider, but keeping the phase timings at 1 (2 - * phases per cycle). - * - * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz, - * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns. - * - * ns_cycle >= 2*18e3/(18*480) = 25/6 - * ns_cycle <= 2*35e3/(18*480) = 875/108 - * - * Multiply the ns_cycle by 'div' to lengthen it until it fits the - * bounds. This is the divider we'll use after ref_pix. - * - * 6 * ns_cycle >= 25 * div - * 108 * ns_cycle <= 875 * div - */ - u32 ns_cycle = 1000000 / rate; - u32 div, reg_val; - u32 lowest_result = (u32) -1; - u32 lowest_div = 0, lowest_fracdiv = 0; - - for (div = 1; div < 256; ++div) { - u32 fracdiv; - u32 ps_result; - int lower_bound = 6 * ns_cycle >= 25 * div; - int upper_bound = 108 * ns_cycle <= 875 * div; - if (!lower_bound) - break; - if (!upper_bound) - continue; - /* - * Found a matching div. Calculate fractional divider needed, - * rounded up. - */ - fracdiv = ((clk->parent->rate / 1000 * 18 / 2) * - ns_cycle + 1000 * div - 1) / - (1000 * div); - if (fracdiv < 18 || fracdiv > 35) { - ret = -EINVAL; - goto out; - } - /* Calculate the actual cycle time this results in */ - ps_result = 6250 * div * fracdiv / 27; - - /* Use the fastest result that doesn't break ns_cycle */ - if (ps_result <= lowest_result) { - lowest_result = ps_result; - lowest_div = div; - lowest_fracdiv = fracdiv; - } - } - - if (div >= 256 || lowest_result == (u32) -1) { - ret = -EINVAL; - goto out; - } - pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz " - "PIXCLK=%uMHz cycle=%u.%03uns\n", - lowest_fracdiv, lowest_div, - 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div, - lowest_result / 1000, lowest_result % 1000); - - /* Program ref_pix phase fractional divider */ - reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); - reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC; - reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC); - __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); - - /* Ungate PFD */ - stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX, - REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC); - - /* Program pix divider */ - reg_val = __raw_readl(clk->scale_reg); - reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); - reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV); - __raw_writel(reg_val, clk->scale_reg); - - /* Wait for divider update */ - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - ret = -ETIMEDOUT; - goto out; - } - } - - /* Switch to ref_pix source */ - reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); - reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX; - __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); - -out: - return ret; -} - - -static int cpu_set_rate(struct clk *clk, u32 rate) -{ - u32 reg_val; - - if (rate < 24000) - return -EINVAL; - else if (rate == 24000) { - /* switch to the 24M source */ - clk_set_parent(clk, &osc_24M); - } else { - int i; - u32 clkctrl_cpu = 1; - u32 c = clkctrl_cpu; - u32 clkctrl_frac = 1; - u32 val; - for ( ; c < 0x40; c++) { - u32 f = (pll_clk.rate*18/c + rate/2) / rate; - int s1, s2; - - if (f < 18 || f > 35) - continue; - s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate; - s2 = pll_clk.rate*18/c/f - rate; - pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2); - if (abs(s1) > abs(s2)) { - clkctrl_cpu = c; - clkctrl_frac = f; - } - if (s2 == 0) - break; - }; - pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__, - clkctrl_cpu, clkctrl_frac); - if (c == 0x40) { - int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - - rate; - if (abs(d) > 100 || - clkctrl_frac < 18 || clkctrl_frac > 35) - return -EINVAL; - } - - /* 4.6.2 */ - val = __raw_readl(clk->scale_reg); - val &= ~(0x3f << clk->scale_shift); - val |= clkctrl_frac; - clk_set_parent(clk, &osc_24M); - udelay(10); - __raw_writel(val, clk->scale_reg); - /* ungate */ - __raw_writel(1<<7, clk->scale_reg + 8); - /* write clkctrl_cpu */ - clk->saved_div = clkctrl_cpu; - - reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - reg_val &= ~0x3F; - reg_val |= clkctrl_cpu; - __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up CPU divisor\n"); - return -ETIMEDOUT; - } - clk_set_parent(clk, &pll_clk); - clk->saved_div = 0; - udelay(10); - } - return 0; -} - -static long cpu_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate * 18; - - rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; - rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f; - rate = ((rate + 9) / 10) * 10; - clk->rate = rate; - - return rate; -} - -static long cpu_round_rate(struct clk *clk, u32 rate) -{ - unsigned long r = 0; - - if (rate <= 24000) - r = 24000; - else { - u32 clkctrl_cpu = 1; - u32 clkctrl_frac; - do { - clkctrl_frac = - (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate; - if (clkctrl_frac > 35) - continue; - if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 == - rate / 10) - break; - } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate); - if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate) - clkctrl_cpu--; - pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__, - clkctrl_cpu, clkctrl_frac); - if (clkctrl_frac < 18) - clkctrl_frac = 18; - if (clkctrl_frac > 35) - clkctrl_frac = 35; - - r = pll_clk.rate * 18; - r /= clkctrl_frac; - r /= clkctrl_cpu; - r = 10 * ((r + 9) / 10); - } - return r; -} - -static long emi_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate * 18; - - rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f; - rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f; - clk->rate = rate; - - return rate; -} - -static int clkseq_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = -EINVAL; - int shift = 8; - - /* bypass? */ - if (parent == &osc_24M) - shift = 4; - - if (clk->bypass_reg) { -#ifdef CONFIG_ARCH_STMP378X - u32 hbus_val, cpu_val; - - if (clk == &cpu_clk && shift == 4) { - hbus_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_HBUS); - cpu_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_CPU); - - hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | - BM_CLKCTRL_HBUS_DIV); - clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU; - cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; - cpu_val |= 1; - - if (machine_is_stmp378x()) { - __raw_writel(hbus_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); - __raw_writel(cpu_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - hclk.rate = 0; - } - } else if (clk == &cpu_clk && shift == 8) { - hbus_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_HBUS); - cpu_val = __raw_readl(REGS_CLKCTRL_BASE + - HW_CLKCTRL_CPU); - hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | - BM_CLKCTRL_HBUS_DIV); - hbus_val |= 2; - cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; - if (clk->saved_div) - cpu_val |= clk->saved_div; - else - cpu_val |= 2; - - if (machine_is_stmp378x()) { - __raw_writel(hbus_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); - __raw_writel(cpu_val, - REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU); - hclk.rate = 0; - } - } -#endif - __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift); - - ret = 0; - } - - return ret; -} - -static int hbus_set_rate(struct clk *clk, u32 rate) -{ - u8 div = 0; - int is_frac = 0; - u32 clkctrl_hbus; - struct clk *parent = clk->parent; - - pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, - parent->rate); - - if (rate > parent->rate) - return -EINVAL; - - if (((parent->rate + rate/2) / rate) * rate != parent->rate && - parent->rate / rate < 32) { - pr_debug("%s: switching to fractional mode\n", __func__); - is_frac = 1; - } - - if (is_frac) - div = (32 * rate + parent->rate / 2) / parent->rate; - else - div = (parent->rate + rate - 1) / rate; - pr_debug("%s: div calculated is %d\n", __func__, div); - if (!div || div > 0x1f) - return -EINVAL; - - clk_set_parent(&cpu_clk, &osc_24M); - udelay(10); - clkctrl_hbus = __raw_readl(clk->scale_reg); - clkctrl_hbus &= ~0x3f; - clkctrl_hbus |= div; - clkctrl_hbus |= (is_frac << 5); - - __raw_writel(clkctrl_hbus, clk->scale_reg); - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up CPU divisor\n"); - return -ETIMEDOUT; - } - } - clk_set_parent(&cpu_clk, &pll_clk); - __raw_writel(clkctrl_hbus, clk->scale_reg); - udelay(10); - return 0; -} - -static long hbus_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - - if (__raw_readl(clk->scale_reg) & 0x20) { - rate *= __raw_readl(clk->scale_reg) & 0x1f; - rate /= 32; - } else - rate /= __raw_readl(clk->scale_reg) & 0x1f; - clk->rate = rate; - - return rate; -} - -static int xbus_set_rate(struct clk *clk, u32 rate) -{ - u16 div = 0; - u32 clkctrl_xbus; - - pr_debug("%s: rate %d, parent rate %d\n", __func__, rate, - clk->parent->rate); - - div = (clk->parent->rate + rate - 1) / rate; - pr_debug("%s: div calculated is %d\n", __func__, div); - if (!div || div > 0x3ff) - return -EINVAL; - - clkctrl_xbus = __raw_readl(clk->scale_reg); - clkctrl_xbus &= ~0x3ff; - clkctrl_xbus |= div; - __raw_writel(clkctrl_xbus, clk->scale_reg); - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up xbus divisor\n"); - return -ETIMEDOUT; - } - } - return 0; -} - -static long xbus_get_rate(struct clk *clk) -{ - long rate = clk->parent->rate; - - rate /= __raw_readl(clk->scale_reg) & 0x3ff; - clk->rate = rate; - - return rate; -} - - -/* Clock ops */ - -static struct clk_ops std_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = per_get_rate, - .set_rate = per_set_rate, - .set_parent = clkseq_set_parent, -}; - -static struct clk_ops min_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, -}; - -static struct clk_ops cpu_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = cpu_get_rate, - .set_rate = cpu_set_rate, - .round_rate = cpu_round_rate, - .set_parent = clkseq_set_parent, -}; - -static struct clk_ops io_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = io_get_rate, - .set_rate = io_set_rate, -}; - -static struct clk_ops hbus_ops = { - .get_rate = hbus_get_rate, - .set_rate = hbus_set_rate, -}; - -static struct clk_ops xbus_ops = { - .get_rate = xbus_get_rate, - .set_rate = xbus_set_rate, -}; - -static struct clk_ops lcdif_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .get_rate = lcdif_get_rate, - .set_rate = lcdif_set_rate, - .set_parent = clkseq_set_parent, -}; - -static struct clk_ops emi_ops = { - .get_rate = emi_get_rate, -}; - -/* List of on-chip clocks */ - -static struct clk osc_24M = { - .flags = FIXED_RATE | ENABLED, - .rate = 24000, -}; - -static struct clk pll_clk = { - .parent = &osc_24M, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, - .enable_shift = 16, - .enable_wait = 10, - .flags = FIXED_RATE | ENABLED, - .rate = 480000, - .ops = &min_ops, -}; - -static struct clk cpu_clk = { - .parent = &pll_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .scale_shift = 0, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 7, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU, - .busy_bit = 28, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &cpu_ops, -}; - -static struct clk io_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .enable_shift = 31, - .enable_negate = 1, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .scale_shift = 24, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &io_ops, -}; - -static struct clk hclk = { - .parent = &cpu_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 7, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS, - .busy_bit = 29, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &hbus_ops, -}; - -static struct clk xclk = { - .parent = &osc_24M, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS, - .busy_bit = 31, - .flags = RATE_PROPAGATES | ENABLED, - .ops = &xbus_ops, -}; - -static struct clk uart_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 31, - .enable_negate = 1, - .flags = ENABLED, - .ops = &min_ops, -}; - -static struct clk audio_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 30, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk pwm_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 29, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk dri_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 28, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk digctl_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 27, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk timer_clk = { - .parent = &xclk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL, - .enable_shift = 26, - .enable_negate = 1, - .flags = ENABLED, - .ops = &min_ops, -}; - -static struct clk lcdif_clk = { - .parent = &pll_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 1, - .flags = NEEDS_SET_PARENT, - .ops = &lcdif_ops, -}; - -static struct clk ssp_clk = { - .parent = &io_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP, - .enable_shift = 31, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 5, - .enable_negate = 1, - .flags = NEEDS_SET_PARENT, - .ops = &std_ops, -}; - -static struct clk gpmi_clk = { - .parent = &io_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 4, - .flags = NEEDS_SET_PARENT, - .ops = &std_ops, -}; - -static struct clk spdif_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF, - .enable_shift = 31, - .enable_negate = 1, - .ops = &min_ops, -}; - -static struct clk emi_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, - .enable_shift = 31, - .enable_negate = 1, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC, - .scale_shift = 8, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI, - .busy_bit = 28, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 6, - .flags = ENABLED, - .ops = &emi_ops, -}; - -static struct clk ir_clk = { - .parent = &io_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 3, - .ops = &min_ops, -}; - -static struct clk saif_clk = { - .parent = &pll_clk, - .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, - .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, - .busy_bit = 29, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF, - .enable_shift = 31, - .enable_negate = 1, - .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ, - .bypass_shift = 0, - .ops = &std_ops, -}; - -static struct clk usb_clk = { - .parent = &pll_clk, - .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0, - .enable_shift = 18, - .enable_negate = 1, - .ops = &min_ops, -}; - -/* list of all the clocks */ -static struct clk_lookup onchip_clks[] = { - { - .con_id = "osc_24M", - .clk = &osc_24M, - }, { - .con_id = "pll", - .clk = &pll_clk, - }, { - .con_id = "cpu", - .clk = &cpu_clk, - }, { - .con_id = "hclk", - .clk = &hclk, - }, { - .con_id = "xclk", - .clk = &xclk, - }, { - .con_id = "io", - .clk = &io_clk, - }, { - .con_id = "uart", - .clk = &uart_clk, - }, { - .con_id = "audio", - .clk = &audio_clk, - }, { - .con_id = "pwm", - .clk = &pwm_clk, - }, { - .con_id = "dri", - .clk = &dri_clk, - }, { - .con_id = "digctl", - .clk = &digctl_clk, - }, { - .con_id = "timer", - .clk = &timer_clk, - }, { - .con_id = "lcdif", - .clk = &lcdif_clk, - }, { - .con_id = "ssp", - .clk = &ssp_clk, - }, { - .con_id = "gpmi", - .clk = &gpmi_clk, - }, { - .con_id = "spdif", - .clk = &spdif_clk, - }, { - .con_id = "emi", - .clk = &emi_clk, - }, { - .con_id = "ir", - .clk = &ir_clk, - }, { - .con_id = "saif", - .clk = &saif_clk, - }, { - .con_id = "usb", - .clk = &usb_clk, - }, -}; - -static int __init propagate_rate(struct clk *clk) -{ - struct clk_lookup *cl; - - for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks); - cl++) { - if (unlikely(!clk_good(cl->clk))) - continue; - if (cl->clk->parent == clk && cl->clk->ops->get_rate) { - cl->clk->ops->get_rate(cl->clk); - if (cl->clk->flags & RATE_PROPAGATES) - propagate_rate(cl->clk); - } - } - - return 0; -} - -/* Exported API */ -unsigned long clk_get_rate(struct clk *clk) -{ - if (unlikely(!clk_good(clk))) - return 0; - - if (clk->rate != 0) - return clk->rate; - - if (clk->ops->get_rate != NULL) - return clk->ops->get_rate(clk); - - return clk_get_rate(clk->parent); -} -EXPORT_SYMBOL(clk_get_rate); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (unlikely(!clk_good(clk))) - return 0; - - if (clk->ops->round_rate) - return clk->ops->round_rate(clk, rate); - - return 0; -} -EXPORT_SYMBOL(clk_round_rate); - -static inline int close_enough(long rate1, long rate2) -{ - return rate1 && !((rate2 - rate1) * 1000 / rate1); -} - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - int ret = -EINVAL; - - if (unlikely(!clk_good(clk))) - goto out; - - if (clk->flags & FIXED_RATE || !clk->ops->set_rate) - goto out; - - else if (!close_enough(clk->rate, rate)) { - ret = clk->ops->set_rate(clk, rate); - if (ret < 0) - goto out; - clk->rate = rate; - if (clk->flags & RATE_PROPAGATES) - propagate_rate(clk); - } else - ret = 0; - -out: - return ret; -} -EXPORT_SYMBOL(clk_set_rate); - -int clk_enable(struct clk *clk) -{ - unsigned long clocks_flags; - - if (unlikely(!clk_good(clk))) - return -EINVAL; - - if (clk->parent) - clk_enable(clk->parent); - - spin_lock_irqsave(&clocks_lock, clocks_flags); - - clk->usage++; - if (clk->ops && clk->ops->enable) - clk->ops->enable(clk); - - spin_unlock_irqrestore(&clocks_lock, clocks_flags); - return 0; -} -EXPORT_SYMBOL(clk_enable); - -static void local_clk_disable(struct clk *clk) -{ - if (unlikely(!clk_good(clk))) - return; - - if (clk->usage == 0 && clk->ops->disable) - clk->ops->disable(clk); - - if (clk->parent) - local_clk_disable(clk->parent); -} - -void clk_disable(struct clk *clk) -{ - unsigned long clocks_flags; - - if (unlikely(!clk_good(clk))) - return; - - spin_lock_irqsave(&clocks_lock, clocks_flags); - - if ((--clk->usage) == 0 && clk->ops->disable) - clk->ops->disable(clk); - - spin_unlock_irqrestore(&clocks_lock, clocks_flags); - if (clk->parent) - clk_disable(clk->parent); -} -EXPORT_SYMBOL(clk_disable); - -/* Some additional API */ -int clk_set_parent(struct clk *clk, struct clk *parent) -{ - int ret = -ENODEV; - unsigned long clocks_flags; - - if (unlikely(!clk_good(clk))) - goto out; - - if (!clk->ops->set_parent) - goto out; - - spin_lock_irqsave(&clocks_lock, clocks_flags); - - ret = clk->ops->set_parent(clk, parent); - if (!ret) { - /* disable if usage count is 0 */ - local_clk_disable(parent); - - parent->usage += clk->usage; - clk->parent->usage -= clk->usage; - - /* disable if new usage count is 0 */ - local_clk_disable(clk->parent); - - clk->parent = parent; - } - spin_unlock_irqrestore(&clocks_lock, clocks_flags); - -out: - return ret; -} -EXPORT_SYMBOL(clk_set_parent); - -struct clk *clk_get_parent(struct clk *clk) -{ - if (unlikely(!clk_good(clk))) - return NULL; - return clk->parent; -} -EXPORT_SYMBOL(clk_get_parent); - -static int __init clk_init(void) -{ - struct clk_lookup *cl; - struct clk_ops *ops; - - spin_lock_init(&clocks_lock); - - for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks); - cl++) { - if (cl->clk->flags & ENABLED) - clk_enable(cl->clk); - else - local_clk_disable(cl->clk); - - ops = cl->clk->ops; - - if ((cl->clk->flags & NEEDS_INITIALIZATION) && - ops && ops->set_rate) - ops->set_rate(cl->clk, cl->clk->rate); - - if (cl->clk->flags & FIXED_RATE) { - if (cl->clk->flags & RATE_PROPAGATES) - propagate_rate(cl->clk); - } else { - if (ops && ops->get_rate) - ops->get_rate(cl->clk); - } - - if (cl->clk->flags & NEEDS_SET_PARENT) { - if (ops && ops->set_parent) - ops->set_parent(cl->clk, cl->clk->parent); - } - } - clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks)); - return 0; -} - -arch_initcall(clk_init); diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h deleted file mode 100644 index a6611e1a3510..000000000000 --- a/arch/arm/plat-stmp3xxx/clock.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Clock control driver for Freescale STMP37XX/STMP378X - internal header file - * - * Author: Vitaly Wool <vital@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__ -#define __ARCH_ARM_STMX3XXX_CLOCK_H__ - -#ifndef __ASSEMBLER__ - -struct clk_ops { - int (*enable) (struct clk *); - int (*disable) (struct clk *); - long (*get_rate) (struct clk *); - long (*round_rate) (struct clk *, u32); - int (*set_rate) (struct clk *, u32); - int (*set_parent) (struct clk *, struct clk *); -}; - -struct clk { - struct clk *parent; - u32 rate; - u32 flags; - u8 scale_shift; - u8 enable_shift; - u8 bypass_shift; - u8 busy_bit; - s8 usage; - int enable_wait; - int enable_negate; - u32 saved_div; - void __iomem *enable_reg; - void __iomem *scale_reg; - void __iomem *bypass_reg; - void __iomem *busy_reg; - struct clk_ops *ops; -}; - -#endif /* __ASSEMBLER__ */ - -/* Flags */ -#define RATE_PROPAGATES (1<<0) -#define NEEDS_INITIALIZATION (1<<1) -#define PARENT_SET_RATE (1<<2) -#define FIXED_RATE (1<<3) -#define ENABLED (1<<4) -#define NEEDS_SET_PARENT (1<<5) - -#endif diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c deleted file mode 100644 index 37b8a09148a4..000000000000 --- a/arch/arm/plat-stmp3xxx/core.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X core routines - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> - -#include <mach/stmp3xxx.h> -#include <mach/platform.h> -#include <mach/dma.h> -#include <mach/regs-clkctrl.h> - -static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable) -{ - u32 c; - int timeout; - - /* the process of software reset of IP block is done - in several steps: - - - clear SFTRST and wait for block is enabled; - - clear clock gating (CLKGATE bit); - - set the SFTRST again and wait for block is in reset; - - clear SFTRST and wait for reset completion. - */ - c = __raw_readl(hwreg); - c &= ~(1<<31); /* clear SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1<<31)) == 0) - break; - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when enabling\n", - __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1<<30); /* clear CLKGATE */ - __raw_writel(c, hwreg); - - if (!just_enable) { - c = __raw_readl(hwreg); - c |= (1<<31); /* now again set SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* poll until CLKGATE set */ - if (__raw_readl(hwreg) & (1<<30)) - break; - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when resetting\n", - __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1<<31); /* clear SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1<<31)) == 0) - break; - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when enabling " - "after reset\n", __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1<<30); /* clear CLKGATE */ - __raw_writel(c, hwreg); - } - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1<<30)) == 0) - break; - - if (timeout <= 0) { - printk(KERN_ERR"%s(%p): timeout when unclockgating\n", - __func__, hwreg); - return -ETIME; - } - - return 0; -} - -int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable) -{ - int try = 10; - int r; - - while (try--) { - r = __stmp3xxx_reset_block(hwreg, just_enable); - if (!r) - break; - pr_debug("%s: try %d failed\n", __func__, 10 - try); - } - return r; -} -EXPORT_SYMBOL(stmp3xxx_reset_block); - -struct platform_device stmp3xxx_dbguart = { - .name = "stmp3xxx-dbguart", - .id = -1, -}; - -void __init stmp3xxx_init(void) -{ - /* Turn off auto-slow and other tricks */ - stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS); - - stmp3xxx_dma_init(); -} diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c deleted file mode 100644 index 68fed4b8746a..000000000000 --- a/arch/arm/plat-stmp3xxx/devices.c +++ /dev/null @@ -1,389 +0,0 @@ -/* -* Freescale STMP37XX/STMP378X platform devices -* -* Embedded Alley Solutions, Inc <source@embeddedalley.com> -* -* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. -* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. -*/ - -/* -* The code contained herein is licensed under the GNU General Public -* License. You may obtain a copy of the GNU General Public License -* Version 2 or later at the following locations: -* -* http://www.opensource.org/licenses/gpl-license.html -* http://www.gnu.org/copyleft/gpl.html -*/ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> - -#include <mach/dma.h> -#include <mach/platform.h> -#include <mach/stmp3xxx.h> -#include <mach/regs-lcdif.h> -#include <mach/regs-uartapp.h> -#include <mach/regs-gpmi.h> -#include <mach/regs-usbctrl.h> -#include <mach/regs-ssp.h> -#include <mach/regs-rtc.h> - -static u64 common_dmamask = DMA_BIT_MASK(32); - -static struct resource appuart_resources[] = { - { - .start = IRQ_UARTAPP_INTERNAL, - .end = IRQ_UARTAPP_INTERNAL, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_UARTAPP_RX_DMA, - .end = IRQ_UARTAPP_RX_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_UARTAPP_TX_DMA, - .end = IRQ_UARTAPP_TX_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = REGS_UARTAPP1_PHYS, - .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE, - .flags = IORESOURCE_MEM, - }, { - /* Rx DMA channel */ - .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX), - .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX), - .flags = IORESOURCE_DMA, - }, { - /* Tx DMA channel */ - .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX), - .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX), - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device stmp3xxx_appuart = { - .name = "stmp3xxx-appuart", - .id = 0, - .resource = appuart_resources, - .num_resources = ARRAY_SIZE(appuart_resources), - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device stmp3xxx_watchdog = { - .name = "stmp3xxx_wdt", - .id = -1, -}; - -static struct resource ts_resource[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_TOUCH_DETECT, - .end = IRQ_TOUCH_DETECT, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_LRADC_CH5, - .end = IRQ_LRADC_CH5, - }, -}; - -struct platform_device stmp3xxx_touchscreen = { - .name = "stmp3xxx_ts", - .id = -1, - .resource = ts_resource, - .num_resources = ARRAY_SIZE(ts_resource), -}; - -/* -* Keypad device -*/ -struct platform_device stmp3xxx_keyboard = { - .name = "stmp3xxx-keyboard", - .id = -1, -}; - -static struct resource gpmi_resources[] = { - { - .flags = IORESOURCE_MEM, - .start = REGS_GPMI_PHYS, - .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_GPMI_DMA, - .end = IRQ_GPMI_DMA, - }, { - .flags = IORESOURCE_DMA, - .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH), - }, -}; - -struct platform_device stmp3xxx_gpmi = { - .name = "gpmi", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = gpmi_resources, - .num_resources = ARRAY_SIZE(gpmi_resources), -}; - -static struct resource mmc1_resource[] = { - { - .flags = IORESOURCE_MEM, - .start = REGS_SSP1_PHYS, - .end = REGS_SSP1_PHYS + REGS_SSP_SIZE, - }, { - .flags = IORESOURCE_DMA, - .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_SSP1_DMA, - .end = IRQ_SSP1_DMA, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_SSP_ERROR, - .end = IRQ_SSP_ERROR, - }, -}; - -struct platform_device stmp3xxx_mmc = { - .name = "stmp3xxx-mmc", - .id = 1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = mmc1_resource, - .num_resources = ARRAY_SIZE(mmc1_resource), -}; - -static struct resource usb_resources[] = { - { - .start = REGS_USBCTRL_PHYS, - .end = REGS_USBCTRL_PHYS + SZ_4K, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_USB_CTRL, - .end = IRQ_USB_CTRL, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device stmp3xxx_udc = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = usb_resources, - .num_resources = ARRAY_SIZE(usb_resources), -}; - -struct platform_device stmp3xxx_ehci = { - .name = "fsl-ehci", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = usb_resources, - .num_resources = ARRAY_SIZE(usb_resources), -}; - -static struct resource rtc_resources[] = { - { - .start = REGS_RTC_PHYS, - .end = REGS_RTC_PHYS + REGS_RTC_SIZE, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_RTC_ALARM, - .end = IRQ_RTC_ALARM, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_RTC_1MSEC, - .end = IRQ_RTC_1MSEC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device stmp3xxx_rtc = { - .name = "stmp3xxx-rtc", - .id = -1, - .resource = rtc_resources, - .num_resources = ARRAY_SIZE(rtc_resources), -}; - -static struct resource ssp1_resources[] = { - { - .start = REGS_SSP1_PHYS, - .end = REGS_SSP1_PHYS + REGS_SSP_SIZE, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_SSP1_DMA, - .end = IRQ_SSP1_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH), - .flags = IORESOURCE_DMA, - }, -}; - -static struct resource ssp2_resources[] = { - { - .start = REGS_SSP2_PHYS, - .end = REGS_SSP2_PHYS + REGS_SSP_SIZE, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_SSP2_DMA, - .end = IRQ_SSP2_DMA, - .flags = IORESOURCE_IRQ, - }, { - .start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH), - .end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH), - .flags = IORESOURCE_DMA, - }, -}; - -struct platform_device stmp3xxx_spi1 = { - .name = "stmp3xxx_ssp", - .id = 1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = ssp1_resources, - .num_resources = ARRAY_SIZE(ssp1_resources), -}; - -struct platform_device stmp3xxx_spi2 = { - .name = "stmp3xxx_ssp", - .id = 2, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = ssp2_resources, - .num_resources = ARRAY_SIZE(ssp2_resources), -}; - -static struct resource fb_resource[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_LCDIF_DMA, - .end = IRQ_LCDIF_DMA, - }, { - .flags = IORESOURCE_IRQ, - .start = IRQ_LCDIF_ERROR, - .end = IRQ_LCDIF_ERROR, - }, { - .flags = IORESOURCE_MEM, - .start = REGS_LCDIF_PHYS, - .end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE, - }, -}; - -struct platform_device stmp3xxx_framebuffer = { - .name = "stmp3xxx-fb", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(fb_resource), - .resource = fb_resource, -}; - -#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \ - static char *cmdline_device_##name; \ - static int cmdline_device_##name##_setup(char *dev) \ - { \ - cmdline_device_##name = dev + 1; \ - return 0; \ - } \ - __setup(#name, cmdline_device_##name##_setup); \ - int stmp3xxx_##name##_device_register(void) \ - { \ - struct platform_device *d = NULL; \ - if (!cmdline_device_##name || \ - !strcmp(cmdline_device_##name, #dev1)) \ - d = &stmp3xxx_##dev1; \ - else if (!strcmp(cmdline_device_##name, #dev2)) \ - d = &stmp3xxx_##dev2; \ - else \ - printk(KERN_ERR"Unknown %s assignment '%s'.\n", \ - #name, cmdline_device_##name); \ - return d ? platform_device_register(d) : -ENOENT; \ - } - -CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1) -CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2) - -struct platform_device stmp3xxx_backlight = { - .name = "stmp3xxx-bl", - .id = -1, -}; - -struct platform_device stmp3xxx_rotdec = { - .name = "stmp3xxx-rotdec", - .id = -1, -}; - -struct platform_device stmp3xxx_persistent = { - .name = "stmp3xxx-persistent", - .id = -1, -}; - -struct platform_device stmp3xxx_dcp_bootstream = { - .name = "stmp3xxx-dcpboot", - .id = -1, - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource dcp_resources[] = { - { - .start = IRQ_DCP_VMI, - .end = IRQ_DCP_VMI, - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_DCP, - .end = IRQ_DCP, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device stmp3xxx_dcp = { - .name = "stmp3xxx-dcp", - .id = -1, - .resource = dcp_resources, - .num_resources = ARRAY_SIZE(dcp_resources), - .dev = { - .dma_mask = &common_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource battery_resource[] = { - { - .flags = IORESOURCE_IRQ, - .start = IRQ_VDD5V, - .end = IRQ_VDD5V, - }, -}; - -struct platform_device stmp3xxx_battery = { - .name = "stmp3xxx-battery", - .resource = battery_resource, - .num_resources = ARRAY_SIZE(battery_resource), -}; diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c deleted file mode 100644 index b4dcf8c0477d..000000000000 --- a/arch/arm/plat-stmp3xxx/dma.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * DMA helper routines for Freescale STMP37XX/STMP378X - * - * Author: dmitry pervushin <dpervushin@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/device.h> -#include <linux/dmapool.h> -#include <linux/sysdev.h> -#include <linux/cpufreq.h> - -#include <asm/page.h> - -#include <mach/platform.h> -#include <mach/dma.h> -#include <mach/regs-apbx.h> -#include <mach/regs-apbh.h> - -static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command); -static const size_t pool_alignment = 8; -static struct stmp3xxx_dma_user { - void *pool; - int inuse; - const char *name; -} channels[MAX_DMA_CHANNELS]; - -#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS) -#define IS_USED(ch) (channels[ch].inuse) - -int stmp3xxx_dma_request(int ch, struct device *dev, const char *name) -{ - struct stmp3xxx_dma_user *user; - int err = 0; - - user = channels + ch; - if (!IS_VALID_CHANNEL(ch)) { - err = -ENODEV; - goto out; - } - if (IS_USED(ch)) { - err = -EBUSY; - goto out; - } - /* Create a pool to allocate dma commands from */ - user->pool = dma_pool_create(name, dev, pool_item_size, - pool_alignment, PAGE_SIZE); - if (user->pool == NULL) { - err = -ENOMEM; - goto out; - } - user->name = name; - user->inuse++; -out: - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_request); - -int stmp3xxx_dma_release(int ch) -{ - struct stmp3xxx_dma_user *user = channels + ch; - int err = 0; - - if (!IS_VALID_CHANNEL(ch)) { - err = -ENODEV; - goto out; - } - if (!IS_USED(ch)) { - err = -EBUSY; - goto out; - } - BUG_ON(user->pool == NULL); - dma_pool_destroy(user->pool); - user->inuse--; -out: - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_release); - -int stmp3xxx_dma_read_semaphore(int channel) -{ - int sem = -1; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + - STMP3XXX_DMA_CHANNEL(channel) * 0x70); - sem &= BM_APBH_CHn_SEMA_PHORE; - sem >>= BP_APBH_CHn_SEMA_PHORE; - break; - - case STMP3XXX_BUS_APBX: - sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + - STMP3XXX_DMA_CHANNEL(channel) * 0x70); - sem &= BM_APBX_CHn_SEMA_PHORE; - sem >>= BP_APBX_CHn_SEMA_PHORE; - break; - default: - BUG(); - } - return sem; -} -EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore); - -int stmp3xxx_dma_allocate_command(int channel, - struct stmp3xxx_dma_descriptor *descriptor) -{ - struct stmp3xxx_dma_user *user = channels + channel; - int err = 0; - - if (!IS_VALID_CHANNEL(channel)) { - err = -ENODEV; - goto out; - } - if (!IS_USED(channel)) { - err = -EBUSY; - goto out; - } - if (descriptor == NULL) { - err = -EINVAL; - goto out; - } - - /* Allocate memory for a command from the buffer */ - descriptor->command = - dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle); - - /* Check it worked */ - if (!descriptor->command) { - err = -ENOMEM; - goto out; - } - - memset(descriptor->command, 0, pool_item_size); -out: - WARN_ON(err); - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_allocate_command); - -int stmp3xxx_dma_free_command(int channel, - struct stmp3xxx_dma_descriptor *descriptor) -{ - int err = 0; - - if (!IS_VALID_CHANNEL(channel)) { - err = -ENODEV; - goto out; - } - if (!IS_USED(channel)) { - err = -EBUSY; - goto out; - } - - /* Return the command memory to the pool */ - dma_pool_free(channels[channel].pool, descriptor->command, - descriptor->handle); - - /* Initialise descriptor so we're not tempted to use it */ - descriptor->command = NULL; - descriptor->handle = 0; - descriptor->virtual_buf_ptr = NULL; - descriptor->next_descr = NULL; - - WARN_ON(err); -out: - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_free_command); - -void stmp3xxx_dma_go(int channel, - struct stmp3xxx_dma_descriptor *head, u32 semaphore) -{ - int ch = STMP3XXX_DMA_CHANNEL(channel); - void __iomem *c, *s; - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch; - s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch; - break; - - case STMP3XXX_BUS_APBX: - c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch; - s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch; - break; - - default: - return; - } - - /* Set next command */ - __raw_writel(head->handle, c); - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - __raw_writel(semaphore, s); -} -EXPORT_SYMBOL(stmp3xxx_dma_go); - -int stmp3xxx_dma_running(int channel) -{ - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA + - 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & - BM_APBH_CHn_SEMA_PHORE; - - case STMP3XXX_BUS_APBX: - return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA + - 0x70 * STMP3XXX_DMA_CHANNEL(channel))) & - BM_APBX_CHn_SEMA_PHORE; - default: - BUG(); - return 0; - } -} -EXPORT_SYMBOL(stmp3xxx_dma_running); - -/* - * Circular dma chain management - */ -void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain) -{ - int i; - - for (i = 0; i < chain->total_count; i++) - stmp3xxx_dma_free_command( - STMP3XXX_DMA(chain->channel, chain->bus), - &chain->chain[i]); -} -EXPORT_SYMBOL(stmp3xxx_dma_free_chain); - -int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, - struct stmp3xxx_dma_descriptor descriptors[], - unsigned items) -{ - int i; - int err = 0; - - if (items == 0) - return err; - - for (i = 0; i < items; i++) { - err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]); - if (err) { - WARN_ON(err); - /* - * Couldn't allocate the whole chain. - * deallocate what has been allocated - */ - if (i) { - do { - stmp3xxx_dma_free_command(ch, - &descriptors - [i]); - } while (i-- > 0); - } - return err; - } - - /* link them! */ - if (i > 0) { - descriptors[i - 1].next_descr = &descriptors[i]; - descriptors[i - 1].command->next = - descriptors[i].handle; - } - } - - /* make list circular */ - descriptors[items - 1].next_descr = &descriptors[0]; - descriptors[items - 1].command->next = descriptors[0].handle; - - chain->total_count = items; - chain->chain = descriptors; - chain->free_index = 0; - chain->active_index = 0; - chain->cooked_index = 0; - chain->free_count = items; - chain->active_count = 0; - chain->cooked_count = 0; - chain->bus = STMP3XXX_DMA_BUS(ch); - chain->channel = STMP3XXX_DMA_CHANNEL(ch); - return err; -} -EXPORT_SYMBOL(stmp3xxx_dma_make_chain); - -void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain) -{ - BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus))); - chain->free_index = 0; - chain->active_index = 0; - chain->cooked_index = 0; - chain->free_count = chain->total_count; - chain->active_count = 0; - chain->cooked_count = 0; -} -EXPORT_SYMBOL(stmp37xx_circ_clear_chain); - -void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain, - unsigned count) -{ - BUG_ON(chain->cooked_count < count); - - chain->cooked_count -= count; - chain->cooked_index += count; - chain->cooked_index %= chain->total_count; - chain->free_count += count; -} -EXPORT_SYMBOL(stmp37xx_circ_advance_free); - -void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, - unsigned count) -{ - void __iomem *c; - u32 mask_clr, mask; - BUG_ON(chain->free_count < count); - - chain->free_count -= count; - chain->free_index += count; - chain->free_index %= chain->total_count; - chain->active_count += count; - - switch (chain->bus) { - case STMP3XXX_BUS_APBH: - c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel; - mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA; - mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA); - break; - case STMP3XXX_BUS_APBX: - c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel; - mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA; - mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA); - break; - default: - BUG(); - return; - } - - /* Set counting semaphore (kicks off transfer). Assumes - peripheral has been set up correctly */ - stmp3xxx_clearl(mask_clr, c); - stmp3xxx_setl(mask, c); -} -EXPORT_SYMBOL(stmp37xx_circ_advance_active); - -unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain) -{ - unsigned cooked; - - cooked = chain->active_count - - stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus)); - - chain->active_count -= cooked; - chain->active_index += cooked; - chain->active_index %= chain->total_count; - - chain->cooked_count += cooked; - - return cooked; -} -EXPORT_SYMBOL(stmp37xx_circ_advance_cooked); - -void stmp3xxx_dma_set_alt_target(int channel, int function) -{ -#if defined(CONFIG_ARCH_STMP37XX) - unsigned bits = 4; -#elif defined(CONFIG_ARCH_STMP378X) - unsigned bits = 2; -#else -#error wrong arch -#endif - int shift = STMP3XXX_DMA_CHANNEL(channel) * bits; - unsigned mask = (1<<bits) - 1; - void __iomem *c; - - BUG_ON(function < 0 || function >= (1<<bits)); - pr_debug("%s: channel = %d, using mask %x, " - "shift = %d\n", __func__, channel, mask, shift); - - switch (STMP3XXX_DMA_BUS(channel)) { - case STMP3XXX_BUS_APBH: - c = REGS_APBH_BASE + HW_APBH_DEVSEL; - break; - case STMP3XXX_BUS_APBX: - c = REGS_APBX_BASE + HW_APBX_DEVSEL; - break; - default: - BUG(); - } - stmp3xxx_clearl(mask << shift, c); - stmp3xxx_setl(mask << shift, c); -} -EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target); - -void stmp3xxx_dma_suspend(void) -{ - stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0); - stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0); -} - -void stmp3xxx_dma_resume(void) -{ - stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST, - REGS_APBH_BASE + HW_APBH_CTRL0); - stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST, - REGS_APBX_BASE + HW_APBX_CTRL0); -} - -#ifdef CONFIG_CPU_FREQ - -struct dma_notifier_block { - struct notifier_block nb; - void *data; -}; - -static int dma_cpufreq_notifier(struct notifier_block *self, - unsigned long phase, void *p) -{ - switch (phase) { - case CPUFREQ_POSTCHANGE: - stmp3xxx_dma_resume(); - break; - - case CPUFREQ_PRECHANGE: - stmp3xxx_dma_suspend(); - break; - - default: - break; - } - - return NOTIFY_DONE; -} - -static struct dma_notifier_block dma_cpufreq_nb = { - .nb = { - .notifier_call = dma_cpufreq_notifier, - }, -}; -#endif /* CONFIG_CPU_FREQ */ - -void __init stmp3xxx_dma_init(void) -{ - stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST, - REGS_APBH_BASE + HW_APBH_CTRL0); - stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST, - REGS_APBX_BASE + HW_APBX_CTRL0); -#ifdef CONFIG_CPU_FREQ - cpufreq_register_notifier(&dma_cpufreq_nb.nb, - CPUFREQ_TRANSITION_NOTIFIER); -#endif /* CONFIG_CPU_FREQ */ -} diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h deleted file mode 100644 index f9c39772d7c5..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_MACH_CLKDEV_H -#define __ASM_MACH_CLKDEV_H - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do { } while (0) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h deleted file mode 100644 index b4e205b95f2c..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/cputype.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X CPU type detection - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_CPU_H -#define __ASM_PLAT_CPU_H - -#ifdef CONFIG_ARCH_STMP37XX -#define cpu_is_stmp37xx() (1) -#else -#define cpu_is_stmp37xx() (0) -#endif - -#ifdef CONFIG_ARCH_STMP378X -#define cpu_is_stmp378x() (1) -#else -#define cpu_is_stmp378x() (0) -#endif - -#endif /* __ASM_PLAT_CPU_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S deleted file mode 100644 index d3a0985c9681..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Debugging macro include header - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - - .macro addruart, rp, rv - mov \rp, #0x00070000 - add \rv, \rp, #0xf0000000 @ virtual base - add \rp, \rp, #0x80000000 @ physical base - .endm - - .macro senduart,rd,rx - strb \rd, [\rx, #0] @ data register at 0 - .endm - - .macro waituart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full - bne 1001b - .endm - - .macro busyuart,rd,rx -1001: ldr \rd, [\rx, #0x18] @ UARTFLG - tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy - bne 1001b - .endm diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h deleted file mode 100644 index 7c58557c6766..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/dma.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X DMA helper interface - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_STMP3XXX_DMA_H -#define __ASM_PLAT_STMP3XXX_DMA_H - -#include <linux/platform_device.h> -#include <linux/dmapool.h> - -#if !defined(MAX_PIO_WORDS) -#define MAX_PIO_WORDS (15) -#endif - -#define STMP3XXX_BUS_APBH 0 -#define STMP3XXX_BUS_APBX 1 -#define STMP3XXX_DMA_MAX_CHANNEL 16 -#define STMP3XXX_DMA_BUS(dma) ((dma) / 16) -#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16) -#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel)) -#define MAX_DMA_ADDRESS 0xffffffff -#define MAX_DMA_CHANNELS 32 - -struct stmp3xxx_dma_command { - u32 next; - u32 cmd; - union { - u32 buf_ptr; - u32 alternate; - }; - u32 pio_words[MAX_PIO_WORDS]; -}; - -struct stmp3xxx_dma_descriptor { - struct stmp3xxx_dma_command *command; - dma_addr_t handle; - - /* The virtual address of the buffer pointer */ - void *virtual_buf_ptr; - /* The next descriptor in a the DMA chain (optional) */ - struct stmp3xxx_dma_descriptor *next_descr; -}; - -struct stmp37xx_circ_dma_chain { - unsigned total_count; - struct stmp3xxx_dma_descriptor *chain; - - unsigned free_index; - unsigned free_count; - unsigned active_index; - unsigned active_count; - unsigned cooked_index; - unsigned cooked_count; - - int bus; - unsigned channel; -}; - -static inline struct stmp3xxx_dma_descriptor - *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain) -{ - return &(chain->chain[chain->free_index]); -} - -static inline struct stmp3xxx_dma_descriptor - *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain) -{ - return &(chain->chain[chain->cooked_index]); -} - -int stmp3xxx_dma_request(int ch, struct device *dev, const char *name); -int stmp3xxx_dma_release(int ch); -int stmp3xxx_dma_allocate_command(int ch, - struct stmp3xxx_dma_descriptor *descriptor); -int stmp3xxx_dma_free_command(int ch, - struct stmp3xxx_dma_descriptor *descriptor); -void stmp3xxx_dma_continue(int channel, u32 semaphore); -void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head, - u32 semaphore); -int stmp3xxx_dma_running(int ch); -int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain, - struct stmp3xxx_dma_descriptor descriptors[], - unsigned items); -void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain); -void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain); -void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain, - unsigned count); -void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain, - unsigned count); -unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain); -int stmp3xxx_dma_read_semaphore(int ch); -void stmp3xxx_dma_init(void); -void stmp3xxx_dma_set_alt_target(int ch, int target); -void stmp3xxx_dma_suspend(void); -void stmp3xxx_dma_resume(void); - -/* - * STMP37xx and STMP378x have different DMA control - * registers layout - */ - -void stmp3xxx_arch_dma_freeze(int ch); -void stmp3xxx_arch_dma_unfreeze(int ch); -void stmp3xxx_arch_dma_reset_channel(int ch); -void stmp3xxx_arch_dma_enable_interrupt(int ch); -void stmp3xxx_arch_dma_clear_interrupt(int ch); -int stmp3xxx_arch_dma_is_interrupt(int ch); - -static inline void stmp3xxx_dma_reset_channel(int ch) -{ - stmp3xxx_arch_dma_reset_channel(ch); -} - - -static inline void stmp3xxx_dma_freeze(int ch) -{ - stmp3xxx_arch_dma_freeze(ch); -} - -static inline void stmp3xxx_dma_unfreeze(int ch) -{ - stmp3xxx_arch_dma_unfreeze(ch); -} - -static inline void stmp3xxx_dma_enable_interrupt(int ch) -{ - stmp3xxx_arch_dma_enable_interrupt(ch); -} - -static inline void stmp3xxx_dma_clear_interrupt(int ch) -{ - stmp3xxx_arch_dma_clear_interrupt(ch); -} - -static inline int stmp3xxx_dma_is_interrupt(int ch) -{ - return stmp3xxx_arch_dma_is_interrupt(ch); -} - -#endif /* __ASM_PLAT_STMP3XXX_DMA_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h deleted file mode 100644 index a8b579256170..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X GPIO interface - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_GPIO_H -#define __ASM_PLAT_GPIO_H - -#define ARCH_NR_GPIOS (32 * 3) -#define gpio_to_irq(gpio) __gpio_to_irq(gpio) -#define gpio_get_value(gpio) __gpio_get_value(gpio) -#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value) - -#include <asm-generic/gpio.h> - -#endif /* __ASM_PLAT_GPIO_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h deleted file mode 100644 index e166432910ad..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __MACH_GPMI_H - -#include <linux/mtd/partitions.h> -#include <mach/regs-gpmi.h> - -struct gpmi_platform_data { - void *pins; - int nr_parts; - struct mtd_partition *parts; - const char *part_types[]; -}; -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h deleted file mode 100644 index 47b8978405bc..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/hardware.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file contains the hardware definitions of the Freescale STMP3XXX - * - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* - * Where in virtual memory the IO devices (timers, system controllers - * and so on) - */ -#define IO_BASE 0xF0000000 /* VA of IO */ -#define IO_SIZE 0x00100000 /* How much? */ -#define IO_START 0x80000000 /* PA of IO */ - -/* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h deleted file mode 100644 index d08b1b7f3d1c..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/io.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xffffffff - -#define __io(a) __typesafe_io(a) -#define __mem_pci(a) (a) -#define __mem_isa(a) (a) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h deleted file mode 100644 index 61fa54882e12..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/memory.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - -/* - * Physical DRAM offset. - */ -#define PLAT_PHYS_OFFSET UL(0x40000000) - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h deleted file mode 100644 index ba81e1543761..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/mmc.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _MACH_MMC_H -#define _MACH_MMC_H - -#include <mach/regs-ssp.h> - -struct stmp3xxxmmc_platform_data { - int (*get_wp)(void); - unsigned long (*setclock)(void __iomem *base, unsigned long); - void (*cmd_pullup)(int); - int (*hw_init)(void); - void (*hw_release)(void); -}; - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h deleted file mode 100644 index cc5af82279ad..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X Pin Multiplexing - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __PINMUX_H -#define __PINMUX_H - -#include <linux/spinlock.h> -#include <linux/types.h> -#include <linux/gpio.h> -#include <asm-generic/gpio.h> - -/* Pin definitions */ -#include "pins.h" -#include <mach/pins.h> - -/* - * Each pin may be routed up to four different HW interfaces - * including GPIO - */ -enum pin_fun { - PIN_FUN1 = 0, - PIN_FUN2, - PIN_FUN3, - PIN_GPIO, -}; - -/* - * Each pin may have different output drive strength in range from - * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths. - */ -enum pin_strength { - PIN_4MA = 0, - PIN_8MA, - PIN_12MA, - PIN_16MA, - PIN_20MA, -}; - -/* - * Each pin can be programmed for 1.8V or 3.3V - */ -enum pin_voltage { - PIN_1_8V = 0, - PIN_3_3V, -}; - -/* - * Structure to define a group of pins and their parameters - */ -struct pin_desc { - unsigned id; - enum pin_fun fun; - enum pin_strength strength; - enum pin_voltage voltage; - unsigned pullup:1; -}; - -struct pin_group { - struct pin_desc *pins; - int nr_pins; -}; - -/* Set pin drive strength */ -void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength, - const char *label); - -/* Set pin voltage */ -void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, - const char *label); - -/* Enable pull-up resistor for a pin */ -void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label); - -/* - * Request a pin ownership, only one module (identified by @label) - * may own a pin. - */ -int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label); - -/* Release pin */ -void stmp3xxx_release_pin(unsigned id, const char *label); - -void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun); - -/* - * Each bank is associated with a number of registers to control - * pin function, drive strength, voltage and pull-up reigster. The - * number of registers of a given type depends on the number of bits - * describin particular pin. - */ -#define HW_MUXSEL_NUM 2 /* registers per bank */ -#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */ -#define HW_MUXSEL_PIN_NUM 16 /* pins per register */ -#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */ -#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */ - -#define HW_DRIVE_NUM 4 /* registers per bank */ -#define HW_DRIVE_PIN_LEN 4 /* bits per pin */ -#define HW_DRIVE_PIN_NUM 8 /* pins per register */ -#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */ -#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */ -#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */ - - -struct stmp3xxx_pinmux_bank { - struct gpio_chip chip; - - /* Pins allocation map */ - unsigned long pin_map; - - /* Pin owner names */ - const char *pin_labels[32]; - - /* Bank registers */ - void __iomem *hw_muxsel[HW_MUXSEL_NUM]; - void __iomem *hw_drive[HW_DRIVE_NUM]; - void __iomem *hw_pull; - - void __iomem *pin2irq, - *irqlevel, - *irqpolarity, - *irqen, - *irqstat; - - /* HW MUXSEL register function bit values */ - u8 functions[HW_MUXSEL_PINFUN_NUM]; - - /* - * HW DRIVE register strength bit values: - * 0xff - requested strength is not supported for this bank - */ - u8 strengths[HW_DRIVE_PINDRV_NUM]; - - /* GPIO things */ - void __iomem *hw_gpio_in, - *hw_gpio_out, - *hw_gpio_doe; - int irq, virq; -}; - -int __init stmp3xxx_pinmux_init(int virtual_irq_start); - -#endif /* __PINMUX_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h deleted file mode 100644 index c573318e1caa..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/pins.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_PINS_H -#define __ASM_PLAT_PINS_H - -#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin) -#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32) -#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32) - -/* - * Special invalid pin identificator to show a pin doesn't exist - */ -#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF) - -#endif /* __ASM_PLAT_PINS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h deleted file mode 100644 index 7007ddaa91eb..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/platform.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_PLATFORM_H -#define __ASM_PLAT_PLATFORM_H - -#ifndef __ASSEMBLER__ -#include <linux/io.h> -#endif -#include <asm/sizes.h> - -/* Virtual address where registers are mapped */ -#define STMP3XXX_REGS_PHBASE 0x80000000 -#ifdef __ASSEMBLER__ -#define STMP3XXX_REGS_BASE 0xF0000000 -#else -#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000 -#endif -#define STMP3XXX_REGS_SIZE SZ_1M - -/* Virtual address where OCRAM is mapped */ -#define STMP3XXX_OCRAM_PHBASE 0x00000000 -#ifdef __ASSEMBLER__ -#define STMP3XXX_OCRAM_BASE 0xf1000000 -#else -#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000 -#endif -#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K) - -#ifdef CONFIG_ARCH_STMP37XX -#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD -#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR -#endif - -#ifdef CONFIG_ARCH_STMP378X -#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD -#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR -#endif - -#define HW_STMP3XXX_SET 0x04 -#define HW_STMP3XXX_CLR 0x08 -#define HW_STMP3XXX_TOG 0x0c - -#ifndef __ASSEMBLER__ -static inline void stmp3xxx_clearl(u32 v, void __iomem *r) -{ - __raw_writel(v, r + HW_STMP3XXX_CLR); -} - -static inline void stmp3xxx_setl(u32 v, void __iomem *r) -{ - __raw_writel(v, r + HW_STMP3XXX_SET); -} -#endif - -#define BF(value, field) (((value) << BP_##field) & BM_##field) - -#endif /* __ASM_ARCH_PLATFORM_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h deleted file mode 100644 index 2e300feaa4cf..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X core structure and function declarations - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_STMP3XXX_H -#define __ASM_PLAT_STMP3XXX_H - -#include <linux/irq.h> - -extern struct sys_timer stmp3xxx_timer; - -void stmp3xxx_init_irq(struct irq_chip *chip); -void stmp3xxx_init(void); -int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable); -extern struct platform_device stmp3xxx_dbguart, - stmp3xxx_appuart, - stmp3xxx_watchdog, - stmp3xxx_touchscreen, - stmp3xxx_keyboard, - stmp3xxx_gpmi, - stmp3xxx_mmc, - stmp3xxx_udc, - stmp3xxx_ehci, - stmp3xxx_rtc, - stmp3xxx_spi1, - stmp3xxx_spi2, - stmp3xxx_backlight, - stmp3xxx_rotdec, - stmp3xxx_dcp, - stmp3xxx_dcp_bootstream, - stmp3xxx_persistent, - stmp3xxx_framebuffer, - stmp3xxx_battery; -int stmp3xxx_ssp1_device_register(void); -int stmp3xxx_ssp2_device_register(void); - -struct pin_group; -void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label); -int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label); - -#endif /* __ASM_PLAT_STMP3XXX_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h deleted file mode 100644 index 28a988889319..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/system.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2005 Sigmatel Inc - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_ARCH_SYSTEM_H -#define __ASM_ARCH_SYSTEM_H - -#include <asm/proc-fns.h> -#include <mach/platform.h> -#include <mach/regs-clkctrl.h> -#include <mach/regs-power.h> - -static inline void arch_idle(void) -{ - /* - * This should do all the clock switching - * and wait for interrupt tricks - */ - - cpu_do_idle(); -} - -static inline void arch_reset(char mode, const char *cmd) -{ - /* Set BATTCHRG to default value */ - __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE); - - /* Set MINPWR to default value */ - __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR); - - /* Reset digital side of chip (but not power or RTC) */ - __raw_writel(BM_CLKCTRL_RESET_DIG, - REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET); - - /* Should not return */ -} - -#endif diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h deleted file mode 100644 index 3373985d7a8e..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/timex.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 1999 ARM Limited - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/* - * System time clock is sourced from the 32k clock - */ -#define CLOCK_TICK_RATE (32768) diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h deleted file mode 100644 index f79f5ee56cd4..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ASM_PLAT_UNCOMPRESS_H -#define __ASM_PLAT_UNCOMPRESS_H - -/* - * Register includes are for when the MMU enabled; we need to define our - * own stuff here for pre-MMU use - */ -#define UARTDBG_BASE 0x80070000 -#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c]) - -/* - * This does not append a newline - */ -static void putc(char c) -{ - /* Wait for TX fifo empty */ - while ((UART(6) & (1<<7)) == 0) - continue; - - /* Write byte */ - UART(0) = c; - - /* Wait for last bit to exit the UART */ - while (UART(6) & (1<<3)) - continue; -} - -static void flush(void) -{ -} - -/* - * nothing to do - */ -#define arch_decomp_setup() - -#define arch_decomp_wdog() - -#endif /* __ASM_PLAT_UNCOMPRESS_H */ diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h deleted file mode 100644 index 943c1a29d641..000000000000 --- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#define VMALLOC_END 0xf0000000UL diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c deleted file mode 100644 index 6fdf9acf82ed..000000000000 --- a/arch/arm/plat-stmp3xxx/irq.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Freescale STMP37XX/STMP378X common interrupt handling code - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/irq.h> -#include <linux/sysdev.h> - -#include <mach/stmp3xxx.h> -#include <mach/platform.h> -#include <mach/regs-icoll.h> - -void __init stmp3xxx_init_irq(struct irq_chip *chip) -{ - unsigned int i, lv; - - /* Reset the interrupt controller */ - stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true); - - /* Disable all interrupts initially */ - for (i = 0; i < NR_REAL_IRQS; i++) { - chip->irq_mask(irq_get_irq_data(i)); - irq_set_chip_and_handler(i, chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - } - - /* Ensure vector is cleared */ - for (lv = 0; lv < 4; lv++) - __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK); - __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR); - - /* Barrier */ - (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT); -} - diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c deleted file mode 100644 index 3def03b3217d..000000000000 --- a/arch/arm/plat-stmp3xxx/pinmux.c +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Freescale STMP378X/STMP378X Pin Multiplexing - * - * Author: Vladislav Buzov <vbuzov@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#define DEBUG -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/sysdev.h> -#include <linux/string.h> -#include <linux/bitops.h> -#include <linux/irq.h> - -#include <mach/hardware.h> -#include <mach/platform.h> -#include <mach/regs-pinctrl.h> -#include <mach/pins.h> -#include <mach/pinmux.h> - -#define NR_BANKS ARRAY_SIZE(pinmux_banks) -static struct stmp3xxx_pinmux_bank pinmux_banks[] = { - [0] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0, - .functions = { 0x0, 0x1, 0x2, 0x3 }, - .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, - - .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0, - .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0, - .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0, - .irq = IRQ_GPIO0, - - .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0, - .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0, - .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0, - .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0, - .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0, - }, - [1] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1, - .functions = { 0x0, 0x1, 0x2, 0x3 }, - .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff }, - - .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1, - .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1, - .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1, - .irq = IRQ_GPIO1, - - .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1, - .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1, - .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1, - .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1, - .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1, - }, - [2] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2, - .functions = { 0x0, 0x1, 0x2, 0x3 }, - .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 }, - - .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2, - .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2, - .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2, - .irq = IRQ_GPIO2, - - .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2, - .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2, - .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2, - .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2, - .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2, - }, - [3] = { - .hw_muxsel = { - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6, - REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7, - }, - .hw_drive = { - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13, - REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14, - NULL, - }, - .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3, - .functions = {0x0, 0x1, 0x2, 0x3}, - .strengths = {0x0, 0x1, 0x2, 0x3, 0xff}, - }, -}; - -static inline struct stmp3xxx_pinmux_bank * -stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin) -{ - unsigned b, p; - - b = STMP3XXX_PINID_TO_BANK(id); - p = STMP3XXX_PINID_TO_PINNUM(id); - BUG_ON(b >= NR_BANKS); - if (bank) - *bank = b; - if (pin) - *pin = p; - return &pinmux_banks[b]; -} - -/* Check if requested pin is owned by caller */ -static int stmp3xxx_check_pin(unsigned id, const char *label) -{ - unsigned pin; - struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin); - - if (!test_bit(pin, &pm->pin_map)) { - printk(KERN_WARNING - "%s: Accessing free pin %x, caller %s\n", - __func__, id, label); - - return -EINVAL; - } - - if (label && pm->pin_labels[pin] && - strcmp(label, pm->pin_labels[pin])) { - printk(KERN_WARNING - "%s: Wrong pin owner %x, caller %s owner %s\n", - __func__, id, label, pm->pin_labels[pin]); - - return -EINVAL; - } - return 0; -} - -void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength, - const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwdrive; - u32 shift, val; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label, - bank, pin, strength); - - hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM]; - shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN; - val = pbank->strengths[strength]; - if (val == 0xff) { - printk(KERN_WARNING - "%s: strength is not supported for bank %d, caller %s", - __func__, bank, label); - return; - } - - if (stmp3xxx_check_pin(id, label)) - return; - - pr_debug("%s: writing 0x%x to 0x%p register\n", __func__, - val << shift, hwdrive); - stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive); - stmp3xxx_setl(val << shift, hwdrive); -} - -void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage, - const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwdrive; - u32 shift; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label, - bank, pin, voltage); - - hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM]; - shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN; - - if (stmp3xxx_check_pin(id, label)) - return; - - pr_debug("%s: changing 0x%x bit in 0x%p register\n", - __func__, HW_DRIVE_PINV_MASK << shift, hwdrive); - if (voltage == PIN_1_8V) - stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive); - else - stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive); -} - -void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwpull; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label, - bank, pin, enable); - - hwpull = pbank->hw_pull; - - if (stmp3xxx_check_pin(id, label)) - return; - - pr_debug("%s: changing 0x%x bit in 0x%p register\n", - __func__, 1 << pin, hwpull); - if (enable) - stmp3xxx_setl(1 << pin, hwpull); - else - stmp3xxx_clearl(1 << pin, hwpull); -} - -int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - u32 bank, pin; - int ret = 0; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label, - bank, pin, fun); - - if (test_bit(pin, &pbank->pin_map)) { - printk(KERN_WARNING - "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n", - __func__, bank, pin, label, pbank->pin_labels[pin]); - return -EBUSY; - } - - set_bit(pin, &pbank->pin_map); - pbank->pin_labels[pin] = label; - - stmp3xxx_set_pin_type(id, fun); - - return ret; -} - -void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun) -{ - struct stmp3xxx_pinmux_bank *pbank; - void __iomem *hwmux; - u32 shift, val; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - - hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM]; - shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; - - val = pbank->functions[fun]; - shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN; - pr_debug("%s: writing 0x%x to 0x%p register\n", - __func__, val << shift, hwmux); - stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux); - stmp3xxx_setl(val << shift, hwmux); -} - -void stmp3xxx_release_pin(unsigned id, const char *label) -{ - struct stmp3xxx_pinmux_bank *pbank; - u32 bank, pin; - - pbank = stmp3xxx_pinmux_bank(id, &bank, &pin); - pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin); - - if (stmp3xxx_check_pin(id, label)) - return; - - clear_bit(pin, &pbank->pin_map); - pbank->pin_labels[pin] = NULL; -} - -int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label) -{ - struct pin_desc *pin; - int p; - int err = 0; - - /* Allocate and configure pins */ - for (p = 0; p < pin_group->nr_pins; p++) { - pr_debug("%s: #%d\n", __func__, p); - pin = &pin_group->pins[p]; - - err = stmp3xxx_request_pin(pin->id, pin->fun, label); - if (err) - goto out_err; - - stmp3xxx_pin_strength(pin->id, pin->strength, label); - stmp3xxx_pin_voltage(pin->id, pin->voltage, label); - stmp3xxx_pin_pullup(pin->id, pin->pullup, label); - } - - return 0; - -out_err: - /* Release allocated pins in case of error */ - while (--p >= 0) { - pr_debug("%s: releasing #%d\n", __func__, p); - stmp3xxx_release_pin(pin_group->pins[p].id, label); - } - return err; -} -EXPORT_SYMBOL(stmp3xxx_request_pin_group); - -void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label) -{ - struct pin_desc *pin; - int p; - - for (p = 0; p < pin_group->nr_pins; p++) { - pin = &pin_group->pins[p]; - stmp3xxx_release_pin(pin->id, label); - } -} -EXPORT_SYMBOL(stmp3xxx_release_pin_group); - -static int stmp3xxx_irq_data_to_gpio(struct irq_data *d, - struct stmp3xxx_pinmux_bank **bank, unsigned *gpio) -{ - struct stmp3xxx_pinmux_bank *pm; - - for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++) - if (pm->virq <= d->irq && d->irq < pm->virq + 32) { - *bank = pm; - *gpio = d->irq - pm->virq; - return 0; - } - return -ENOENT; -} - -static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type) -{ - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - int l, p; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - switch (type) { - case IRQ_TYPE_EDGE_RISING: - l = 0; p = 1; break; - case IRQ_TYPE_EDGE_FALLING: - l = 0; p = 0; break; - case IRQ_TYPE_LEVEL_HIGH: - l = 1; p = 1; break; - case IRQ_TYPE_LEVEL_LOW: - l = 1; p = 0; break; - default: - pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n", - __func__, type); - return -ENXIO; - } - - if (l) - stmp3xxx_setl(1 << gpio, pm->irqlevel); - else - stmp3xxx_clearl(1 << gpio, pm->irqlevel); - if (p) - stmp3xxx_setl(1 << gpio, pm->irqpolarity); - else - stmp3xxx_clearl(1 << gpio, pm->irqpolarity); - return 0; -} - -static void stmp3xxx_pin_ack_irq(struct irq_data *d) -{ - u32 stat; - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - stat = __raw_readl(pm->irqstat) & (1 << gpio); - stmp3xxx_clearl(stat, pm->irqstat); -} - -static void stmp3xxx_pin_mask_irq(struct irq_data *d) -{ - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - stmp3xxx_clearl(1 << gpio, pm->irqen); - stmp3xxx_clearl(1 << gpio, pm->pin2irq); -} - -static void stmp3xxx_pin_unmask_irq(struct irq_data *d) -{ - struct stmp3xxx_pinmux_bank *pm; - unsigned gpio; - - stmp3xxx_irq_data_to_gpio(d, &pm, &gpio); - stmp3xxx_setl(1 << gpio, pm->irqen); - stmp3xxx_setl(1 << gpio, pm->pin2irq); -} - -static inline -struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip) -{ - return container_of(chip, struct stmp3xxx_pinmux_bank, chip); -} - -static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - return pm->virq + offset; -} - -static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - unsigned v; - - v = __raw_readl(pm->hw_gpio_in) & (1 << offset); - return v ? 1 : 0; -} - -static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - - if (v) - stmp3xxx_setl(1 << offset, pm->hw_gpio_out); - else - stmp3xxx_clearl(1 << offset, pm->hw_gpio_out); -} - -static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - - stmp3xxx_setl(1 << offset, pm->hw_gpio_doe); - stmp3xxx_gpio_set(chip, offset, v); - return 0; -} - -static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset) -{ - struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip); - - stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe); - return 0; -} - -static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio"); -} - -static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - stmp3xxx_release_pin(chip->base + offset, "gpio"); -} - -static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) -{ - struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq); - int gpio_irq = pm->virq; - u32 stat = __raw_readl(pm->irqstat); - - while (stat) { - if (stat & 1) - generic_handle_irq(gpio_irq); - gpio_irq++; - stat >>= 1; - } -} - -static struct irq_chip gpio_irq_chip = { - .irq_ack = stmp3xxx_pin_ack_irq, - .irq_mask = stmp3xxx_pin_mask_irq, - .irq_unmask = stmp3xxx_pin_unmask_irq, - .irq_set_type = stmp3xxx_set_irqtype, -}; - -int __init stmp3xxx_pinmux_init(int virtual_irq_start) -{ - int b, r = 0; - struct stmp3xxx_pinmux_bank *pm; - int virq; - - for (b = 0; b < 3; b++) { - /* only banks 0,1,2 are allowed to GPIO */ - pm = pinmux_banks + b; - pm->chip.base = 32 * b; - pm->chip.ngpio = 32; - pm->chip.owner = THIS_MODULE; - pm->chip.can_sleep = 1; - pm->chip.exported = 1; - pm->chip.to_irq = stmp3xxx_gpio_to_irq; - pm->chip.direction_input = stmp3xxx_gpio_input; - pm->chip.direction_output = stmp3xxx_gpio_output; - pm->chip.get = stmp3xxx_gpio_get; - pm->chip.set = stmp3xxx_gpio_set; - pm->chip.request = stmp3xxx_gpio_request; - pm->chip.free = stmp3xxx_gpio_free; - pm->virq = virtual_irq_start + b * 32; - - for (virq = pm->virq; virq < pm->virq; virq++) { - gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); - irq_set_chip_and_handler(virq, &gpio_irq_chip, - handle_level_irq); - set_irq_flags(virq, IRQF_VALID); - } - r = gpiochip_add(&pm->chip); - if (r < 0) - break; - irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq); - irq_set_handler_data(pm->irq, pm); - } - return r; -} - -MODULE_AUTHOR("Vladislav Buzov"); -MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c deleted file mode 100644 index c395630a6edc..000000000000 --- a/arch/arm/plat-stmp3xxx/timer.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * System timer for Freescale STMP37XX/STMP378X - * - * Embedded Alley Solutions, Inc <source@embeddedalley.com> - * - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. - */ - -/* - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/spinlock.h> -#include <linux/clocksource.h> -#include <linux/clockchips.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/interrupt.h> - -#include <asm/mach/time.h> -#include <mach/stmp3xxx.h> -#include <mach/platform.h> -#include <mach/regs-timrot.h> - -static irqreturn_t -stmp3xxx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *c = dev_id; - - /* timer 0 */ - if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) & - BM_TIMROT_TIMCTRLn_IRQ) { - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - c->event_handler(c); - } - - /* timer 1 */ - else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1) - & BM_TIMROT_TIMCTRLn_IRQ) { - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); - } - - return IRQ_HANDLED; -} - -static cycle_t stmp3xxx_clock_read(struct clocksource *cs) -{ - return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1) - & 0xFFFF0000) >> 16); -} - -static int -stmp3xxx_timrot_set_next_event(unsigned long delta, - struct clock_event_device *dev) -{ - /* reload the timer */ - __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - return 0; -} - -static void -stmp3xxx_timrot_set_mode(enum clock_event_mode mode, - struct clock_event_device *dev) -{ -} - -static struct clock_event_device ckevt_timrot = { - .name = "timrot", - .features = CLOCK_EVT_FEAT_ONESHOT, - .shift = 32, - .set_next_event = stmp3xxx_timrot_set_next_event, - .set_mode = stmp3xxx_timrot_set_mode, -}; - -static struct clocksource cksrc_stmp3xxx = { - .name = "cksrc_stmp3xxx", - .rating = 250, - .read = stmp3xxx_clock_read, - .mask = CLOCKSOURCE_MASK(16), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static struct irqaction stmp3xxx_timer_irq = { - .name = "stmp3xxx_timer", - .flags = IRQF_DISABLED | IRQF_TIMER, - .handler = stmp3xxx_timer_interrupt, - .dev_id = &ckevt_timrot, -}; - - -/* - * Set up timer interrupt, and return the current time in seconds. - */ -static void __init stmp3xxx_init_timer(void) -{ - ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, - ckevt_timrot.shift); - ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); - ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); - ckevt_timrot.cpumask = cpumask_of(0); - - stmp3xxx_reset_block(REGS_TIMROT_BASE, false); - - /* clear two timers */ - __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); - - /* configure them */ - __raw_writel( - (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - __raw_writel( - (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - - __raw_writel(CLOCK_TICK_RATE / HZ - 1, - REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); - - setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq); - - clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE); - clockevents_register_device(&ckevt_timrot); -} - -#ifdef CONFIG_PM - -void stmp3xxx_suspend_timer(void) -{ - stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE, - REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL); -} - -void stmp3xxx_resume_timer(void) -{ - stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE, - REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL); - __raw_writel( - 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); - __raw_writel( - 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */ - BM_TIMROT_TIMCTRLn_RELOAD | - BM_TIMROT_TIMCTRLn_UPDATE | - BM_TIMROT_TIMCTRLn_IRQ_EN, - REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); - __raw_writel(CLOCK_TICK_RATE / HZ - 1, - REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); - __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); -} - -#else - -#define stmp3xxx_suspend_timer NULL -#define stmp3xxx_resume_timer NULL - -#endif /* CONFIG_PM */ - -struct sys_timer stmp3xxx_timer = { - .init = stmp3xxx_init_timer, - .suspend = stmp3xxx_suspend_timer, - .resume = stmp3xxx_resume_timer, -}; diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c index ba3d471d4bcf..51ecfea09b27 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/plat-versatile/platsmp.c @@ -16,6 +16,7 @@ #include <linux/smp.h> #include <asm/cacheflush.h> +#include <asm/hardware/gic.h> /* * control for which core is the next to come out of the secondary @@ -83,7 +84,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * the boot monitor to read the system wide flags register, * and branch to the address found there. */ - smp_cross_call(cpumask_of(cpu), 1); + gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index f74695075e64..f25e7ec89416 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -398,9 +398,9 @@ static void vfp_enable(void *unused) } #ifdef CONFIG_PM -#include <linux/sysdev.h> +#include <linux/syscore_ops.h> -static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state) +static int vfp_pm_suspend(void) { struct thread_info *ti = current_thread_info(); u32 fpexc = fmrx(FPEXC); @@ -420,34 +420,25 @@ static int vfp_pm_suspend(struct sys_device *dev, pm_message_t state) return 0; } -static int vfp_pm_resume(struct sys_device *dev) +static void vfp_pm_resume(void) { /* ensure we have access to the vfp */ vfp_enable(NULL); /* and disable it to ensure the next usage restores the state */ fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); - - return 0; } -static struct sysdev_class vfp_pm_sysclass = { - .name = "vfp", +static struct syscore_ops vfp_pm_syscore_ops = { .suspend = vfp_pm_suspend, .resume = vfp_pm_resume, }; -static struct sys_device vfp_pm_sysdev = { - .cls = &vfp_pm_sysclass, -}; - static void vfp_pm_init(void) { - sysdev_class_register(&vfp_pm_sysclass); - sysdev_register(&vfp_pm_sysdev); + register_syscore_ops(&vfp_pm_syscore_ops); } - #else static inline void vfp_pm_init(void) { } #endif /* CONFIG_PM */ |