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Diffstat (limited to 'arch/mips/ath79/setup.c')
-rw-r--r--arch/mips/ath79/setup.c78
1 files changed, 12 insertions, 66 deletions
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 9728abcb18fa..4a70c5de8c92 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -19,6 +19,7 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_fdt.h>
+#include <linux/irqchip.h>
#include <asm/bootinfo.h>
#include <asm/idle.h>
@@ -31,8 +32,6 @@
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
-#include "dev-common.h"
-#include "machtypes.h"
#define ATH79_SYS_TYPE_LEN 64
@@ -235,25 +234,21 @@ void __init plat_mem_setup(void)
else if (fw_passed_dtb)
__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
- if (mips_machtype != ATH79_MACH_GENERIC_OF) {
- ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
- AR71XX_RESET_SIZE);
- ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
- AR71XX_PLL_SIZE);
- ath79_detect_sys_type();
- ath79_ddr_ctrl_init();
+ ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
+ AR71XX_RESET_SIZE);
+ ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
+ AR71XX_PLL_SIZE);
+ ath79_detect_sys_type();
+ ath79_ddr_ctrl_init();
- detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
-
- /* OF machines should use the reset driver */
- _machine_restart = ath79_restart;
- }
+ detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
+ _machine_restart = ath79_restart;
_machine_halt = ath79_halt;
pm_power_off = ath79_halt;
}
-static void __init ath79_of_plat_time_init(void)
+void __init plat_time_init(void)
{
struct device_node *np;
struct clk *clk;
@@ -283,61 +278,12 @@ static void __init ath79_of_plat_time_init(void)
clk_put(clk);
}
-void __init plat_time_init(void)
-{
- unsigned long cpu_clk_rate;
- unsigned long ahb_clk_rate;
- unsigned long ddr_clk_rate;
- unsigned long ref_clk_rate;
-
- if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
- ath79_of_plat_time_init();
- return;
- }
-
- ath79_clocks_init();
-
- cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
- ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
- ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
- ref_clk_rate = ath79_get_sys_clk_rate("ref");
-
- pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
- cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
- ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
- ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
- ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
-
- mips_hpt_frequency = cpu_clk_rate / 2;
-}
-
-static int __init ath79_setup(void)
+void __init arch_init_irq(void)
{
- if (mips_machtype == ATH79_MACH_GENERIC_OF)
- return 0;
-
- ath79_gpio_init();
- ath79_register_uart();
- ath79_register_wdt();
-
- mips_machine_setup();
-
- return 0;
+ irqchip_init();
}
-arch_initcall(ath79_setup);
-
void __init device_tree_init(void)
{
unflatten_and_copy_device_tree();
}
-
-MIPS_MACHINE(ATH79_MACH_GENERIC,
- "Generic",
- "Generic AR71XX/AR724X/AR913X based board",
- NULL);
-
-MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
- "DTB",
- "Generic AR71XX/AR724X/AR913X based board (DT)",
- NULL);