diff options
Diffstat (limited to 'arch/mips/include/asm/mach-ralink/rt305x.h')
| -rw-r--r-- | arch/mips/include/asm/mach-ralink/rt305x.h | 48 |
1 files changed, 2 insertions, 46 deletions
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h index b54619dc4b88..4fc5c279cd75 100644 --- a/arch/mips/include/asm/mach-ralink/rt305x.h +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -43,7 +43,8 @@ static inline int soc_is_rt5350(void) return ralink_soc == RT305X_SOC_RT5350; } -#define RT305X_SYSC_BASE 0x10000000 +#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) +#define RT305X_SYSC_BASE IOMEM(0x10000000) #define SYSC_REG_CHIP_NAME0 0x00 #define SYSC_REG_CHIP_NAME1 0x04 @@ -66,26 +67,9 @@ static inline int soc_is_rt5350(void) #define CHIP_ID_ID_SHIFT 8 #define CHIP_ID_REV_MASK 0xff -#define RT305X_SYSCFG_CPUCLK_SHIFT 18 -#define RT305X_SYSCFG_CPUCLK_MASK 0x1 -#define RT305X_SYSCFG_CPUCLK_LOW 0x0 -#define RT305X_SYSCFG_CPUCLK_HIGH 0x1 - #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 -#define RT305X_SYSCFG_CPUCLK_MASK 0x1 #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1 -#define RT3352_SYSCFG0_CPUCLK_SHIFT 8 -#define RT3352_SYSCFG0_CPUCLK_MASK 0x1 -#define RT3352_SYSCFG0_CPUCLK_LOW 0x0 -#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 - -#define RT5350_SYSCFG0_CPUCLK_SHIFT 8 -#define RT5350_SYSCFG0_CPUCLK_MASK 0x3 -#define RT5350_SYSCFG0_CPUCLK_360 0x0 -#define RT5350_SYSCFG0_CPUCLK_320 0x2 -#define RT5350_SYSCFG0_CPUCLK_300 0x3 - #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 #define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 #define RT5350_SYSCFG0_DRAM_SIZE_2M 0 @@ -114,39 +98,11 @@ static inline int soc_is_rt5350(void) #define RT305X_GPIO_GE0_TXD0 40 #define RT305X_GPIO_GE0_RXCLK 51 -#define RT305X_GPIO_MODE_UART0_SHIFT 2 -#define RT305X_GPIO_MODE_UART0_MASK 0x7 -#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) -#define RT305X_GPIO_MODE_UARTF 0 -#define RT305X_GPIO_MODE_PCM_UARTF 1 -#define RT305X_GPIO_MODE_PCM_I2S 2 -#define RT305X_GPIO_MODE_I2S_UARTF 3 -#define RT305X_GPIO_MODE_PCM_GPIO 4 -#define RT305X_GPIO_MODE_GPIO_UARTF 5 -#define RT305X_GPIO_MODE_GPIO_I2S 6 -#define RT305X_GPIO_MODE_GPIO 7 - -#define RT305X_GPIO_MODE_I2C 0 -#define RT305X_GPIO_MODE_SPI 1 -#define RT305X_GPIO_MODE_UART1 5 -#define RT305X_GPIO_MODE_JTAG 6 -#define RT305X_GPIO_MODE_MDIO 7 -#define RT305X_GPIO_MODE_SDRAM 8 -#define RT305X_GPIO_MODE_RGMII 9 -#define RT5350_GPIO_MODE_PHY_LED 14 -#define RT5350_GPIO_MODE_SPI_CS1 21 -#define RT3352_GPIO_MODE_LNA 18 -#define RT3352_GPIO_MODE_PA 20 - #define RT3352_SYSC_REG_SYSCFG0 0x010 #define RT3352_SYSC_REG_SYSCFG1 0x014 -#define RT3352_SYSC_REG_CLKCFG1 0x030 #define RT3352_SYSC_REG_RSTCTRL 0x034 #define RT3352_SYSC_REG_USB_PS 0x05c -#define RT3352_CLKCFG0_XTAL_SEL BIT(20) -#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) -#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) #define RT3352_RSTCTRL_UHST BIT(22) #define RT3352_RSTCTRL_UDEV BIT(25) #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) |