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-rw-r--r--arch/mips/include/asm/sync.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h
index aabd097933fe..44c04a82d0b7 100644
--- a/arch/mips/include/asm/sync.h
+++ b/arch/mips/include/asm/sync.h
@@ -19,7 +19,7 @@
*
* Ordering barriers can be more efficient than completion barriers, since:
*
- * a) Ordering barriers only require memory access instructions which preceed
+ * a) Ordering barriers only require memory access instructions which precede
* them in program order (older instructions) to reach a point in the
* load/store datapath beyond which reordering is not possible before
* allowing memory access instructions which follow them (younger