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Diffstat (limited to 'arch/mips/include/asm/txx9/smsc_fdc37m81x.h')
-rw-r--r--arch/mips/include/asm/txx9/smsc_fdc37m81x.h54
1 files changed, 27 insertions, 27 deletions
diff --git a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
index d1d6332b4ca6..926d08f18463 100644
--- a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
+++ b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
@@ -18,43 +18,43 @@
/* Common Registers */
#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
#define SMSC_FDC37M81X_CONFIG_DATA 0x01
-#define SMSC_FDC37M81X_CONF 0x02
-#define SMSC_FDC37M81X_INDEX 0x03
-#define SMSC_FDC37M81X_DNUM 0x07
-#define SMSC_FDC37M81X_DID 0x20
-#define SMSC_FDC37M81X_DREV 0x21
-#define SMSC_FDC37M81X_PCNT 0x22
-#define SMSC_FDC37M81X_PMGT 0x23
-#define SMSC_FDC37M81X_OSC 0x24
-#define SMSC_FDC37M81X_CONFPA0 0x26
-#define SMSC_FDC37M81X_CONFPA1 0x27
-#define SMSC_FDC37M81X_TEST4 0x2B
-#define SMSC_FDC37M81X_TEST5 0x2C
-#define SMSC_FDC37M81X_TEST1 0x2D
-#define SMSC_FDC37M81X_TEST2 0x2E
-#define SMSC_FDC37M81X_TEST3 0x2F
+#define SMSC_FDC37M81X_CONF 0x02
+#define SMSC_FDC37M81X_INDEX 0x03
+#define SMSC_FDC37M81X_DNUM 0x07
+#define SMSC_FDC37M81X_DID 0x20
+#define SMSC_FDC37M81X_DREV 0x21
+#define SMSC_FDC37M81X_PCNT 0x22
+#define SMSC_FDC37M81X_PMGT 0x23
+#define SMSC_FDC37M81X_OSC 0x24
+#define SMSC_FDC37M81X_CONFPA0 0x26
+#define SMSC_FDC37M81X_CONFPA1 0x27
+#define SMSC_FDC37M81X_TEST4 0x2B
+#define SMSC_FDC37M81X_TEST5 0x2C
+#define SMSC_FDC37M81X_TEST1 0x2D
+#define SMSC_FDC37M81X_TEST2 0x2E
+#define SMSC_FDC37M81X_TEST3 0x2F
/* Logical device numbers */
-#define SMSC_FDC37M81X_FDD 0x00
-#define SMSC_FDC37M81X_PARALLEL 0x03
-#define SMSC_FDC37M81X_SERIAL1 0x04
-#define SMSC_FDC37M81X_SERIAL2 0x05
-#define SMSC_FDC37M81X_KBD 0x07
-#define SMSC_FDC37M81X_AUXIO 0x08
-#define SMSC_FDC37M81X_NONE 0xff
+#define SMSC_FDC37M81X_FDD 0x00
+#define SMSC_FDC37M81X_PARALLEL 0x03
+#define SMSC_FDC37M81X_SERIAL1 0x04
+#define SMSC_FDC37M81X_SERIAL2 0x05
+#define SMSC_FDC37M81X_KBD 0x07
+#define SMSC_FDC37M81X_AUXIO 0x08
+#define SMSC_FDC37M81X_NONE 0xff
/* Logical device Config Registers */
-#define SMSC_FDC37M81X_ACTIVE 0x30
+#define SMSC_FDC37M81X_ACTIVE 0x30
#define SMSC_FDC37M81X_BASEADDR0 0x60
#define SMSC_FDC37M81X_BASEADDR1 0x61
-#define SMSC_FDC37M81X_INT 0x70
-#define SMSC_FDC37M81X_INT2 0x72
-#define SMSC_FDC37M81X_LDCR_F0 0xF0
+#define SMSC_FDC37M81X_INT 0x70
+#define SMSC_FDC37M81X_INT2 0x72
+#define SMSC_FDC37M81X_LDCR_F0 0xF0
/* Chip Config Values */
#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
-#define SMSC_FDC37M81X_CHIP_ID 0x4d
+#define SMSC_FDC37M81X_CHIP_ID 0x4d
unsigned long smsc_fdc37m81x_init(unsigned long port);