diff options
Diffstat (limited to 'arch/mips/include/asm/txx9')
| -rw-r--r-- | arch/mips/include/asm/txx9/boards.h | 9 | ||||
| -rw-r--r-- | arch/mips/include/asm/txx9/jmr3927.h | 179 | ||||
| -rw-r--r-- | arch/mips/include/asm/txx9/rbtx4938.h | 145 | ||||
| -rw-r--r-- | arch/mips/include/asm/txx9/rbtx4939.h | 142 | ||||
| -rw-r--r-- | arch/mips/include/asm/txx9/spi.h | 34 | ||||
| -rw-r--r-- | arch/mips/include/asm/txx9/tx3927.h | 341 | ||||
| -rw-r--r-- | arch/mips/include/asm/txx9/tx4939.h | 525 |
7 files changed, 0 insertions, 1375 deletions
diff --git a/arch/mips/include/asm/txx9/boards.h b/arch/mips/include/asm/txx9/boards.h index d45237befd3e..6897ca4366d5 100644 --- a/arch/mips/include/asm/txx9/boards.h +++ b/arch/mips/include/asm/txx9/boards.h @@ -1,14 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifdef CONFIG_TOSHIBA_JMR3927 -BOARD_VEC(jmr3927_vec) -#endif #ifdef CONFIG_TOSHIBA_RBTX4927 BOARD_VEC(rbtx4927_vec) BOARD_VEC(rbtx4937_vec) #endif -#ifdef CONFIG_TOSHIBA_RBTX4938 -BOARD_VEC(rbtx4938_vec) -#endif -#ifdef CONFIG_TOSHIBA_RBTX4939 -BOARD_VEC(rbtx4939_vec) -#endif diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h deleted file mode 100644 index aab959dc30ba..000000000000 --- a/arch/mips/include/asm/txx9/jmr3927.h +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Defines for the TJSYS JMR-TX3927 - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000-2001 Toshiba Corporation - */ -#ifndef __ASM_TXX9_JMR3927_H -#define __ASM_TXX9_JMR3927_H - -#include <asm/txx9/tx3927.h> -#include <asm/addrspace.h> -#include <asm/txx9irq.h> - -/* CS */ -#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ -#define JMR3927_ROMCE1 0x1e000000 /* 4M */ -#define JMR3927_ROMCE2 0x14000000 /* 16M */ -#define JMR3927_ROMCE3 0x10000000 /* 64M */ -#define JMR3927_ROMCE5 0x1d000000 /* 4M */ -#define JMR3927_SDCS0 0x00000000 /* 32M */ -#define JMR3927_SDCS1 0x02000000 /* 32M */ -/* PCI Direct Mappings */ - -#define JMR3927_PCIMEM 0x08000000 -#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */ -#define JMR3927_PCIIO 0x15000000 -#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */ - -#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */ -#define JMR3927_PORT_BASE KSEG1 - -/* Address map (virtual address) */ -#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0) -#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1) -#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2) -#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM) -#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO) - -#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000) -#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000) -#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000) -#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000) -#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000) -#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000) -#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000) -#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000) -#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000) -#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000) -#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000) - -/* Flash ROM */ -#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE) -#define JMR3927_FLASH_SIZE 0x00400000 - -/* bits for IOC_REV/IOC_BREV (high byte) */ -#define JMR3927_IDT_MASK 0xfc -#define JMR3927_REV_MASK 0x03 -#define JMR3927_IOC_IDT 0xe0 - -/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */ -#define JMR3927_IOC_INTB_PCIA 0 -#define JMR3927_IOC_INTB_PCIB 1 -#define JMR3927_IOC_INTB_PCIC 2 -#define JMR3927_IOC_INTB_PCID 3 -#define JMR3927_IOC_INTB_MODEM 4 -#define JMR3927_IOC_INTB_INT6 5 -#define JMR3927_IOC_INTB_INT7 6 -#define JMR3927_IOC_INTB_SOFT 7 -#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA) -#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB) -#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC) -#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID) -#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM) -#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6) -#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7) -#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT) - -/* bits for IOC_RESET (high byte) */ -#define JMR3927_IOC_RESET_CPU 1 -#define JMR3927_IOC_RESET_PCI 2 - -#if defined(__BIG_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a)) -#elif defined(__LITTLE_ENDIAN) -#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d)) -#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1)) -#else -#error "No Endian" -#endif - -/* LED macro */ -#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) - -#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR) - -/* DIPSW4 macro */ -#define jmr3927_dipsw1() (gpio_get_value(11) == 0) -#define jmr3927_dipsw2() (gpio_get_value(10) == 0) -#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0) -#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0) - -/* - * IRQ mappings - */ - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an JMR machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ -#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ - -#define JMR3927_IRQ_IRC TXX9_IRQ_BASE -#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) -#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) - -#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0) -#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1) -#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2) -#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3) -#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4) -#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5) -#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0) -#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1) -#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch)) -#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) -#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) -#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) -#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) -#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) -#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) -#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) -#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID) -#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM) -#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6) -#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7) -#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT) - -/* IOC (PCI, MODEM) */ -#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 -/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ -#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 - -/* Clocks */ -#define JMR3927_CORECLK 132710400 /* 132.7MHz */ - -/* - * TX3927 Pin Configuration: - * - * PCFG bits Avail Dead - * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3] - * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4] - * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF, - * GDBGE* PIO[2:1] - * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12] - * SELTMR[2:0]:000 TIMER[1:0] - * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6], - * DMAREQ[1],DMAACK[1] - * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8] - * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14] - * SELDONE:1 DMADONE PIO[7] - * - * Usable pins are: - * RXD[1;0],TXD[1:0],CTS[0],RTS[0], - * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11] - * INT[3:0] - */ - -void jmr3927_prom_init(void); -void jmr3927_irq_setup(void); -struct pci_dev; -int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); - -#endif /* __ASM_TXX9_JMR3927_H */ diff --git a/arch/mips/include/asm/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h deleted file mode 100644 index 9c969dd3c6eb..000000000000 --- a/arch/mips/include/asm/txx9/rbtx4938.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Definitions for TX4937/TX4938 - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TXX9_RBTX4938_H -#define __ASM_TXX9_RBTX4938_H - -#include <asm/addrspace.h> -#include <asm/txx9irq.h> -#include <asm/txx9/tx4938.h> - -/* Address map */ -#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000) -#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002) -#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004) -#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006) -#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008) -#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000) -#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002) -#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004) -#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000) -#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002) -#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004) -#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006) -#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008) -#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a) -#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c) -#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000) -#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000) -#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002) -#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008) -#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a) -#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000) -#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002) -#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004) -#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000) - -/* Ethernet port address (Jumperless Mode (W12:Open)) */ -#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280) - -/* bits for ISTAT/IMASK/IMSTAT */ -#define RBTX4938_INTB_PCID 0 -#define RBTX4938_INTB_PCIC 1 -#define RBTX4938_INTB_PCIB 2 -#define RBTX4938_INTB_PCIA 3 -#define RBTX4938_INTB_RTC 4 -#define RBTX4938_INTB_ATA 5 -#define RBTX4938_INTB_MODEM 6 -#define RBTX4938_INTB_SWINT 7 -#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID) -#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC) -#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB) -#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA) -#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC) -#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA) -#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM) -#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT) - -#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR) -#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR) -#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR) -#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR) -#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR) -#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR) -#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR) -#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR) -#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR) -#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR) -#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR) -#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR) -#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR) -#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR) -#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR) -#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR) -#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR) -#define rbtx4938_softresetlock_addr \ - ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR) -#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR) - -/* - * IRQ mappings - */ - -#define RBTX4938_SOFT_INT0 0 /* not used */ -#define RBTX4938_SOFT_INT1 1 /* not used */ -#define RBTX4938_IRC_INT 2 -#define RBTX4938_TIMER_INT 7 - -/* These are the virtual IRQ numbers, we divide all IRQ's into - * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new - * IRQ hardware is supported. - */ -#define RBTX4938_NR_IRQ_IOC 8 - -#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE -#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR) -#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) - -#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) -#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) -#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) -#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n)) -#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n)) -#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO) -#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC) -#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC) -#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n)) -#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC) -#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR) -#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME) -#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC) -#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME) -#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1) -#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI) -#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID) -#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC) -#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB) -#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA) -#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC) -#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA) -#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM) -#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT) - - -/* IOC (PCI, etc) */ -#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0)) -/* Onboard 10M Ether */ -#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1)) - -#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) -#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) - -void rbtx4938_prom_init(void); -void rbtx4938_irq_setup(void); -struct pci_dev; -int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); - -#endif /* __ASM_TXX9_RBTX4938_H */ diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h deleted file mode 100644 index 6157bfd90848..000000000000 --- a/arch/mips/include/asm/txx9/rbtx4939.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Definitions for RBTX4939 - * - * (C) Copyright TOSHIBA CORPORATION 2005-2006 - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_TXX9_RBTX4939_H -#define __ASM_TXX9_RBTX4939_H - -#include <asm/addrspace.h> -#include <asm/txx9irq.h> -#include <asm/txx9/generic.h> -#include <asm/txx9/tx4939.h> - -/* Address map */ -#define RBTX4939_IOC_REG_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) -#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000) -#define RBTX4939_IOC_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000002) -#define RBTX4939_CONFIG1_ADDR (IO_BASE + TXX9_CE(1) + 0x00000004) -#define RBTX4939_CONFIG2_ADDR (IO_BASE + TXX9_CE(1) + 0x00000006) -#define RBTX4939_CONFIG3_ADDR (IO_BASE + TXX9_CE(1) + 0x00000008) -#define RBTX4939_CONFIG4_ADDR (IO_BASE + TXX9_CE(1) + 0x0000000a) -#define RBTX4939_USTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00001000) -#define RBTX4939_UDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001002) -#define RBTX4939_BDIPSW_ADDR (IO_BASE + TXX9_CE(1) + 0x00001004) -#define RBTX4939_IEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00002000) -#define RBTX4939_IPOL_ADDR (IO_BASE + TXX9_CE(1) + 0x00002002) -#define RBTX4939_IFAC1_ADDR (IO_BASE + TXX9_CE(1) + 0x00002004) -#define RBTX4939_IFAC2_ADDR (IO_BASE + TXX9_CE(1) + 0x00002006) -#define RBTX4939_SOFTINT_ADDR (IO_BASE + TXX9_CE(1) + 0x00003000) -#define RBTX4939_ISASTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004000) -#define RBTX4939_PCISTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00004002) -#define RBTX4939_ROME_ADDR (IO_BASE + TXX9_CE(1) + 0x00004004) -#define RBTX4939_SPICS_ADDR (IO_BASE + TXX9_CE(1) + 0x00004006) -#define RBTX4939_AUDI_ADDR (IO_BASE + TXX9_CE(1) + 0x00004008) -#define RBTX4939_ISAGPIO_ADDR (IO_BASE + TXX9_CE(1) + 0x0000400a) -#define RBTX4939_PE1_ADDR (IO_BASE + TXX9_CE(1) + 0x00005000) -#define RBTX4939_PE2_ADDR (IO_BASE + TXX9_CE(1) + 0x00005002) -#define RBTX4939_PE3_ADDR (IO_BASE + TXX9_CE(1) + 0x00005004) -#define RBTX4939_VP_ADDR (IO_BASE + TXX9_CE(1) + 0x00005006) -#define RBTX4939_VPRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00005008) -#define RBTX4939_VPSOUT_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500a) -#define RBTX4939_VPSIN_ADDR (IO_BASE + TXX9_CE(1) + 0x0000500c) -#define RBTX4939_7SEG_ADDR(s, ch) \ - (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2) -#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000) -#define RBTX4939_RESETEN_ADDR (IO_BASE + TXX9_CE(1) + 0x00007002) -#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004) -#define RBTX4939_ETHER_BASE (IO_BASE + TXX9_CE(1) + 0x00020000) - -/* Ethernet port address */ -#define RBTX4939_ETHER_ADDR (RBTX4939_ETHER_BASE + 0x300) - -/* bits for IEN/IPOL/IFAC */ -#define RBTX4938_INTB_ISA0 0 -#define RBTX4938_INTB_ISA11 1 -#define RBTX4938_INTB_ISA12 2 -#define RBTX4938_INTB_ISA15 3 -#define RBTX4938_INTB_I2S 4 -#define RBTX4938_INTB_SW 5 -#define RBTX4938_INTF_ISA0 (1 << RBTX4938_INTB_ISA0) -#define RBTX4938_INTF_ISA11 (1 << RBTX4938_INTB_ISA11) -#define RBTX4938_INTF_ISA12 (1 << RBTX4938_INTB_ISA12) -#define RBTX4938_INTF_ISA15 (1 << RBTX4938_INTB_ISA15) -#define RBTX4938_INTF_I2S (1 << RBTX4938_INTB_I2S) -#define RBTX4938_INTF_SW (1 << RBTX4938_INTB_SW) - -/* bits for PE1,PE2,PE3 */ -#define RBTX4939_PE1_ATA(ch) (0x01 << (ch)) -#define RBTX4939_PE1_RMII(ch) (0x04 << (ch)) -#define RBTX4939_PE2_SIO0 0x01 -#define RBTX4939_PE2_SIO2 0x02 -#define RBTX4939_PE2_SIO3 0x04 -#define RBTX4939_PE2_CIR 0x08 -#define RBTX4939_PE2_SPI 0x10 -#define RBTX4939_PE2_GPIO 0x20 -#define RBTX4939_PE3_VP 0x01 -#define RBTX4939_PE3_VP_P 0x02 -#define RBTX4939_PE3_VP_S 0x04 - -#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR) -#define rbtx4939_ioc_rev_addr ((u8 __iomem *)RBTX4939_IOC_REV_ADDR) -#define rbtx4939_config1_addr ((u8 __iomem *)RBTX4939_CONFIG1_ADDR) -#define rbtx4939_config2_addr ((u8 __iomem *)RBTX4939_CONFIG2_ADDR) -#define rbtx4939_config3_addr ((u8 __iomem *)RBTX4939_CONFIG3_ADDR) -#define rbtx4939_config4_addr ((u8 __iomem *)RBTX4939_CONFIG4_ADDR) -#define rbtx4939_ustat_addr ((u8 __iomem *)RBTX4939_USTAT_ADDR) -#define rbtx4939_udipsw_addr ((u8 __iomem *)RBTX4939_UDIPSW_ADDR) -#define rbtx4939_bdipsw_addr ((u8 __iomem *)RBTX4939_BDIPSW_ADDR) -#define rbtx4939_ien_addr ((u8 __iomem *)RBTX4939_IEN_ADDR) -#define rbtx4939_ipol_addr ((u8 __iomem *)RBTX4939_IPOL_ADDR) -#define rbtx4939_ifac1_addr ((u8 __iomem *)RBTX4939_IFAC1_ADDR) -#define rbtx4939_ifac2_addr ((u8 __iomem *)RBTX4939_IFAC2_ADDR) -#define rbtx4939_softint_addr ((u8 __iomem *)RBTX4939_SOFTINT_ADDR) -#define rbtx4939_isastat_addr ((u8 __iomem *)RBTX4939_ISASTAT_ADDR) -#define rbtx4939_pcistat_addr ((u8 __iomem *)RBTX4939_PCISTAT_ADDR) -#define rbtx4939_rome_addr ((u8 __iomem *)RBTX4939_ROME_ADDR) -#define rbtx4939_spics_addr ((u8 __iomem *)RBTX4939_SPICS_ADDR) -#define rbtx4939_audi_addr ((u8 __iomem *)RBTX4939_AUDI_ADDR) -#define rbtx4939_isagpio_addr ((u8 __iomem *)RBTX4939_ISAGPIO_ADDR) -#define rbtx4939_pe1_addr ((u8 __iomem *)RBTX4939_PE1_ADDR) -#define rbtx4939_pe2_addr ((u8 __iomem *)RBTX4939_PE2_ADDR) -#define rbtx4939_pe3_addr ((u8 __iomem *)RBTX4939_PE3_ADDR) -#define rbtx4939_vp_addr ((u8 __iomem *)RBTX4939_VP_ADDR) -#define rbtx4939_vpreset_addr ((u8 __iomem *)RBTX4939_VPRESET_ADDR) -#define rbtx4939_vpsout_addr ((u8 __iomem *)RBTX4939_VPSOUT_ADDR) -#define rbtx4939_vpsin_addr ((u8 __iomem *)RBTX4939_VPSIN_ADDR) -#define rbtx4939_7seg_addr(s, ch) \ - ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch)) -#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR) -#define rbtx4939_reseten_addr ((u8 __iomem *)RBTX4939_RESETEN_ADDR) -#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR) - -/* - * IRQ mappings - */ -#define RBTX4939_NR_IRQ_IOC 8 - -#define RBTX4939_IRQ_IOC (TXX9_IRQ_BASE + TX4939_NUM_IR) -#define RBTX4939_IRQ_END (RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC) - -/* IOC (ISA, etc) */ -#define RBTX4939_IRQ_IOCINT (TXX9_IRQ_BASE + TX4939_IR_INT(0)) -/* Onboard 10M Ether */ -#define RBTX4939_IRQ_ETHER (TXX9_IRQ_BASE + TX4939_IR_INT(1)) - -void rbtx4939_prom_init(void); -void rbtx4939_irq_setup(void); - -struct mtd_partition; -struct map_info; -struct rbtx4939_flash_data { - unsigned int width; - unsigned int nr_parts; - struct mtd_partition *parts; - void (*map_init)(struct map_info *map); -}; - -#endif /* __ASM_TXX9_RBTX4939_H */ diff --git a/arch/mips/include/asm/txx9/spi.h b/arch/mips/include/asm/txx9/spi.h deleted file mode 100644 index 0d727f354557..000000000000 --- a/arch/mips/include/asm/txx9/spi.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Definitions for TX4937/TX4938 SPI - * - * Copyright (C) 2000-2001 Toshiba Corporation - * - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - * - * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) - */ -#ifndef __ASM_TXX9_SPI_H -#define __ASM_TXX9_SPI_H - -#include <linux/errno.h> - -#ifdef CONFIG_SPI -int spi_eeprom_register(int busid, int chipid, int size); -int spi_eeprom_read(int busid, int chipid, - int address, unsigned char *buf, int len); -#else -static inline int spi_eeprom_register(int busid, int chipid, int size) -{ - return -ENODEV; -} -static inline int spi_eeprom_read(int busid, int chipid, - int address, unsigned char *buf, int len) -{ - return -ENODEV; -} -#endif - -#endif /* __ASM_TXX9_SPI_H */ diff --git a/arch/mips/include/asm/txx9/tx3927.h b/arch/mips/include/asm/txx9/tx3927.h deleted file mode 100644 index 149fab4f8327..000000000000 --- a/arch/mips/include/asm/txx9/tx3927.h +++ /dev/null @@ -1,341 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Toshiba Corporation - */ -#ifndef __ASM_TXX9_TX3927_H -#define __ASM_TXX9_TX3927_H - -#define TX3927_REG_BASE 0xfffe0000UL -#define TX3927_REG_SIZE 0x00010000 -#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000) -#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000) -#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000) -#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000) -#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000) -#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000) -#define TX3927_NR_TMR 3 -#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100) -#define TX3927_NR_SIO 2 -#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100) -#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500) - -struct tx3927_sdramc_reg { - volatile unsigned long cr[8]; - volatile unsigned long tr[3]; - volatile unsigned long cmd; - volatile unsigned long smrs[2]; -}; - -struct tx3927_romc_reg { - volatile unsigned long cr[8]; -}; - -struct tx3927_dma_reg { - struct tx3927_dma_ch_reg { - volatile unsigned long cha; - volatile unsigned long sar; - volatile unsigned long dar; - volatile unsigned long cntr; - volatile unsigned long sair; - volatile unsigned long dair; - volatile unsigned long ccr; - volatile unsigned long csr; - } ch[4]; - volatile unsigned long dbr[8]; - volatile unsigned long tdhr; - volatile unsigned long mcr; - volatile unsigned long unused0; -}; - -#include <asm/byteorder.h> - -#ifdef __BIG_ENDIAN -#define endian_def_s2(e1, e2) \ - volatile unsigned short e1, e2 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned short e1;volatile unsigned char e2, e3 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned char e1, e2;volatile unsigned short e3 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e1, e2, e3, e4 -#else -#define endian_def_s2(e1, e2) \ - volatile unsigned short e2, e1 -#define endian_def_sb2(e1, e2, e3) \ - volatile unsigned char e3, e2;volatile unsigned short e1 -#define endian_def_b2s(e1, e2, e3) \ - volatile unsigned short e3;volatile unsigned char e2, e1 -#define endian_def_b4(e1, e2, e3, e4) \ - volatile unsigned char e4, e3, e2, e1 -#endif - -struct tx3927_pcic_reg { - endian_def_s2(did, vid); - endian_def_s2(pcistat, pcicmd); - endian_def_b4(cc, scc, rpli, rid); - endian_def_b4(unused0, ht, mlt, cls); - volatile unsigned long ioba; /* +10 */ - volatile unsigned long mba; - volatile unsigned long unused1[5]; - endian_def_s2(svid, ssvid); - volatile unsigned long unused2; /* +30 */ - endian_def_sb2(unused3, unused4, capptr); - volatile unsigned long unused5; - endian_def_b4(ml, mg, ip, il); - volatile unsigned long unused6; /* +40 */ - volatile unsigned long istat; - volatile unsigned long iim; - volatile unsigned long rrt; - volatile unsigned long unused7[3]; /* +50 */ - volatile unsigned long ipbmma; - volatile unsigned long ipbioma; /* +60 */ - volatile unsigned long ilbmma; - volatile unsigned long ilbioma; - volatile unsigned long unused8[9]; - volatile unsigned long tc; /* +90 */ - volatile unsigned long tstat; - volatile unsigned long tim; - volatile unsigned long tccmd; - volatile unsigned long pcirrt; /* +a0 */ - volatile unsigned long pcirrt_cmd; - volatile unsigned long pcirrdt; - volatile unsigned long unused9[3]; - volatile unsigned long tlboap; - volatile unsigned long tlbiap; - volatile unsigned long tlbmma; /* +c0 */ - volatile unsigned long tlbioma; - volatile unsigned long sc_msg; - volatile unsigned long sc_be; - volatile unsigned long tbl; /* +d0 */ - volatile unsigned long unused10[3]; - volatile unsigned long pwmng; /* +e0 */ - volatile unsigned long pwmngs; - volatile unsigned long unused11[6]; - volatile unsigned long req_trace; /* +100 */ - volatile unsigned long pbapmc; - volatile unsigned long pbapms; - volatile unsigned long pbapmim; - volatile unsigned long bm; /* +110 */ - volatile unsigned long cpcibrs; - volatile unsigned long cpcibgs; - volatile unsigned long pbacs; - volatile unsigned long iobas; /* +120 */ - volatile unsigned long mbas; - volatile unsigned long lbc; - volatile unsigned long lbstat; - volatile unsigned long lbim; /* +130 */ - volatile unsigned long pcistatim; - volatile unsigned long ica; - volatile unsigned long icd; - volatile unsigned long iiadp; /* +140 */ - volatile unsigned long iscdp; - volatile unsigned long mmas; - volatile unsigned long iomas; - volatile unsigned long ipciaddr; /* +150 */ - volatile unsigned long ipcidata; - volatile unsigned long ipcibe; -}; - -struct tx3927_ccfg_reg { - volatile unsigned long ccfg; - volatile unsigned long crir; - volatile unsigned long pcfg; - volatile unsigned long tear; - volatile unsigned long pdcr; -}; - -/* - * SDRAMC - */ - -/* - * ROMC - */ - -/* - * DMA - */ -/* bits for MCR */ -#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch)) -#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch)) -#define TX3927_DMA_MCR_RSFIF 0x00000080 -#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch)) -#define TX3927_DMA_MCR_LE 0x00000004 -#define TX3927_DMA_MCR_RPRT 0x00000002 -#define TX3927_DMA_MCR_MSTEN 0x00000001 - -/* bits for CCRn */ -#define TX3927_DMA_CCR_DBINH 0x04000000 -#define TX3927_DMA_CCR_SBINH 0x02000000 -#define TX3927_DMA_CCR_CHRST 0x01000000 -#define TX3927_DMA_CCR_RVBYTE 0x00800000 -#define TX3927_DMA_CCR_ACKPOL 0x00400000 -#define TX3927_DMA_CCR_REQPL 0x00200000 -#define TX3927_DMA_CCR_EGREQ 0x00100000 -#define TX3927_DMA_CCR_CHDN 0x00080000 -#define TX3927_DMA_CCR_DNCTL 0x00060000 -#define TX3927_DMA_CCR_EXTRQ 0x00010000 -#define TX3927_DMA_CCR_INTRQD 0x0000e000 -#define TX3927_DMA_CCR_INTENE 0x00001000 -#define TX3927_DMA_CCR_INTENC 0x00000800 -#define TX3927_DMA_CCR_INTENT 0x00000400 -#define TX3927_DMA_CCR_CHNEN 0x00000200 -#define TX3927_DMA_CCR_XFACT 0x00000100 -#define TX3927_DMA_CCR_SNOP 0x00000080 -#define TX3927_DMA_CCR_DSTINC 0x00000040 -#define TX3927_DMA_CCR_SRCINC 0x00000020 -#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c) -#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2) -#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4) -#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5) -#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6) -#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7) -#define TX3927_DMA_CCR_MEMIO 0x00000002 -#define TX3927_DMA_CCR_ONEAD 0x00000001 - -/* bits for CSRn */ -#define TX3927_DMA_CSR_CHNACT 0x00000100 -#define TX3927_DMA_CSR_ABCHC 0x00000080 -#define TX3927_DMA_CSR_NCHNC 0x00000040 -#define TX3927_DMA_CSR_NTRNFC 0x00000020 -#define TX3927_DMA_CSR_EXTDN 0x00000010 -#define TX3927_DMA_CSR_CFERR 0x00000008 -#define TX3927_DMA_CSR_CHERR 0x00000004 -#define TX3927_DMA_CSR_DESERR 0x00000002 -#define TX3927_DMA_CSR_SORERR 0x00000001 - -/* - * IRC - */ -#define TX3927_IR_INT0 0 -#define TX3927_IR_INT1 1 -#define TX3927_IR_INT2 2 -#define TX3927_IR_INT3 3 -#define TX3927_IR_INT4 4 -#define TX3927_IR_INT5 5 -#define TX3927_IR_SIO0 6 -#define TX3927_IR_SIO1 7 -#define TX3927_IR_SIO(ch) (6 + (ch)) -#define TX3927_IR_DMA 8 -#define TX3927_IR_PIO 9 -#define TX3927_IR_PCI 10 -#define TX3927_IR_TMR(ch) (13 + (ch)) -#define TX3927_NUM_IR 16 - -/* - * PCIC - */ -/* bits for PCICMD */ -/* see PCI_COMMAND_XXX in linux/pci.h */ - -/* bits for PCISTAT */ -/* see PCI_STATUS_XXX in linux/pci.h */ -#define PCI_STATUS_NEW_CAP 0x0010 - -/* bits for ISTAT/IIM */ -#define TX3927_PCIC_IIM_ALL 0x00001600 - -/* bits for TC */ -#define TX3927_PCIC_TC_OF16E 0x00000020 -#define TX3927_PCIC_TC_IF8E 0x00000010 -#define TX3927_PCIC_TC_OF8E 0x00000008 - -/* bits for TSTAT/TIM */ -#define TX3927_PCIC_TIM_ALL 0x0003ffff - -/* bits for IOBA/MBA */ -/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */ - -/* bits for PBAPMC */ -#define TX3927_PCIC_PBAPMC_RPBA 0x00000004 -#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002 -#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001 - -/* bits for LBSTAT/LBIM */ -#define TX3927_PCIC_LBIM_ALL 0x0000003e - -/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */ -#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900 - -/* bits for LBC */ -#define TX3927_PCIC_LBC_IBSE 0x00004000 -#define TX3927_PCIC_LBC_TIBSE 0x00002000 -#define TX3927_PCIC_LBC_TMFBSE 0x00001000 -#define TX3927_PCIC_LBC_HRST 0x00000800 -#define TX3927_PCIC_LBC_SRST 0x00000400 -#define TX3927_PCIC_LBC_EPCAD 0x00000200 -#define TX3927_PCIC_LBC_MSDSE 0x00000100 -#define TX3927_PCIC_LBC_CRR 0x00000080 -#define TX3927_PCIC_LBC_ILMDE 0x00000040 -#define TX3927_PCIC_LBC_ILIDE 0x00000020 - -#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) -#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32) - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX3927_CCFG_TLBOFF 0x00020000 -#define TX3927_CCFG_BEOW 0x00010000 -#define TX3927_CCFG_WR 0x00008000 -#define TX3927_CCFG_TOE 0x00004000 -#define TX3927_CCFG_PCIXARB 0x00002000 -#define TX3927_CCFG_PCI3 0x00001000 -#define TX3927_CCFG_PSNP 0x00000800 -#define TX3927_CCFG_PPRI 0x00000400 -#define TX3927_CCFG_PLLM 0x00000030 -#define TX3927_CCFG_ENDIAN 0x00000004 -#define TX3927_CCFG_HALT 0x00000002 -#define TX3927_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX3927_PCFG_SYSCLKEN 0x08000000 -#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000 -#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch)) -#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000 -#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch)) -#define TX3927_PCFG_SELALL 0x0003ffff -#define TX3927_PCFG_SELCS 0x00020000 -#define TX3927_PCFG_SELDSF 0x00010000 -#define TX3927_PCFG_SELSIOC_ALL 0x0000c000 -#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch)) -#define TX3927_PCFG_SELSIO_ALL 0x00003000 -#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch)) -#define TX3927_PCFG_SELTMR_ALL 0x00000e00 -#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch)) -#define TX3927_PCFG_SELDONE 0x00000100 -#define TX3927_PCFG_INTDMA_ALL 0x000000f0 -#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch)) -#define TX3927_PCFG_SELDMA_ALL 0x0000000f -#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch)) - -#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) -#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) -#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) -#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) -#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) -#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) -#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) - -#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16) -#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000) -#define TX3927_ROMC_SIZE(ch) \ - (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf)) -#define TX3927_ROMC_WIDTH(ch) (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1)) - -void tx3927_wdt_init(void); -void tx3927_setup(void); -void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr); -void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask); -struct pci_controller; -void tx3927_pcic_setup(struct pci_controller *channel, - unsigned long sdram_size, int extarb); -void tx3927_setup_pcierr_irq(void); -void tx3927_irq_init(void); -void tx3927_mtd_init(int ch); - -#endif /* __ASM_TXX9_TX3927_H */ diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h deleted file mode 100644 index 00805ac6e9fc..000000000000 --- a/arch/mips/include/asm/txx9/tx4939.h +++ /dev/null @@ -1,525 +0,0 @@ -/* - * Definitions for TX4939 - * - * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation - * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. - */ -#ifndef __ASM_TXX9_TX4939_H -#define __ASM_TXX9_TX4939_H - -/* some controllers are compatible with 4927/4938 */ -#include <asm/txx9/tx4938.h> - -#ifdef CONFIG_64BIT -#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */ -#else -#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */ -#endif -#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */ - -#define TX4939_ATA_REG(ch) (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000) -#define TX4939_NDFMC_REG (TX4939_REG_BASE + 0x5000) -#define TX4939_SRAMC_REG (TX4939_REG_BASE + 0x6000) -#define TX4939_CRYPTO_REG (TX4939_REG_BASE + 0x6800) -#define TX4939_PCIC1_REG (TX4939_REG_BASE + 0x7000) -#define TX4939_DDRC_REG (TX4939_REG_BASE + 0x8000) -#define TX4939_EBUSC_REG (TX4939_REG_BASE + 0x9000) -#define TX4939_VPC_REG (TX4939_REG_BASE + 0xa000) -#define TX4939_DMA_REG(ch) (TX4939_REG_BASE + 0xb000 + (ch) * 0x800) -#define TX4939_PCIC_REG (TX4939_REG_BASE + 0xd000) -#define TX4939_CCFG_REG (TX4939_REG_BASE + 0xe000) -#define TX4939_IRC_REG (TX4939_REG_BASE + 0xe800) -#define TX4939_NR_TMR 6 /* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */ -#define TX4939_TMR_REG(ch) \ - (TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100) -#define TX4939_NR_SIO 4 /* 0xf300, 0xf400, 0xf380, 0xf480 */ -#define TX4939_SIO_REG(ch) \ - (TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6)) -#define TX4939_ACLC_REG (TX4939_REG_BASE + 0xf700) -#define TX4939_SPI_REG (TX4939_REG_BASE + 0xf800) -#define TX4939_I2C_REG (TX4939_REG_BASE + 0xf900) -#define TX4939_I2S_REG (TX4939_REG_BASE + 0xfa00) -#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00) -#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00) - -#define TX4939_RNG_REG (TX4939_CRYPTO_REG + 0xb0) - -struct tx4939_le_reg { - __u32 r; - __u32 unused; -}; - -struct tx4939_ddrc_reg { - struct tx4939_le_reg ctl[47]; - __u64 unused0[17]; - __u64 winen; - __u64 win[4]; -}; - -struct tx4939_ccfg_reg { - __u64 ccfg; - __u64 crir; - __u64 pcfg; - __u64 toea; - __u64 clkctr; - __u64 unused0; - __u64 garbc; - __u64 unused1[2]; - __u64 ramp; - __u64 unused2[2]; - __u64 dskwctrl; - __u64 mclkosc; - __u64 mclkctl; - __u64 unused3[17]; - struct { - __u64 mr; - __u64 dr; - } gpio[2]; -}; - -struct tx4939_irc_reg { - struct tx4939_le_reg den; - struct tx4939_le_reg scipb; - struct tx4939_le_reg dm[2]; - struct tx4939_le_reg lvl[16]; - struct tx4939_le_reg msk; - struct tx4939_le_reg edc; - struct tx4939_le_reg pnd0; - struct tx4939_le_reg cs; - struct tx4939_le_reg pnd1; - struct tx4939_le_reg dm2[2]; - struct tx4939_le_reg dbr[2]; - struct tx4939_le_reg dben; - struct tx4939_le_reg unused0[2]; - struct tx4939_le_reg flag[2]; - struct tx4939_le_reg pol; - struct tx4939_le_reg cnt; - struct tx4939_le_reg maskint; - struct tx4939_le_reg maskext; -}; - -struct tx4939_crypto_reg { - struct tx4939_le_reg csr; - struct tx4939_le_reg idesptr; - struct tx4939_le_reg cdesptr; - struct tx4939_le_reg buserr; - struct tx4939_le_reg cip_tout; - struct tx4939_le_reg cir; - union { - struct { - struct tx4939_le_reg data[8]; - struct tx4939_le_reg ctrl; - } gen; - struct { - struct { - struct tx4939_le_reg l; - struct tx4939_le_reg u; - } key[3], ini; - struct tx4939_le_reg ctrl; - } des; - struct { - struct tx4939_le_reg key[4]; - struct tx4939_le_reg ini[4]; - struct tx4939_le_reg ctrl; - } aes; - struct { - struct { - struct tx4939_le_reg l; - struct tx4939_le_reg u; - } cnt; - struct tx4939_le_reg ini[5]; - struct tx4939_le_reg unused; - struct tx4939_le_reg ctrl; - } hash; - } cdr; - struct tx4939_le_reg unused0[7]; - struct tx4939_le_reg rcsr; - struct tx4939_le_reg rpr; - __u64 rdr; - __u64 ror[3]; - struct tx4939_le_reg unused1[2]; - struct tx4939_le_reg xorslr; - struct tx4939_le_reg xorsur; -}; - -struct tx4939_crypto_desc { - __u32 src; - __u32 dst; - __u32 next; - __u32 ctrl; - __u32 index; - __u32 xor; -}; - -struct tx4939_vpc_reg { - struct tx4939_le_reg csr; - struct { - struct tx4939_le_reg ctrlA; - struct tx4939_le_reg ctrlB; - struct tx4939_le_reg idesptr; - struct tx4939_le_reg cdesptr; - } port[3]; - struct tx4939_le_reg buserr; -}; - -struct tx4939_vpc_desc { - __u32 src; - __u32 next; - __u32 ctrl1; - __u32 ctrl2; -}; - -/* - * IRC - */ -#define TX4939_IR_NONE 0 -#define TX4939_IR_DDR 1 -#define TX4939_IR_WTOERR 2 -#define TX4939_NUM_IR_INT 3 -#define TX4939_IR_INT(n) (3 + (n)) -#define TX4939_NUM_IR_ETH 2 -#define TX4939_IR_ETH(n) ((n) ? 43 : 6) -#define TX4939_IR_VIDEO 7 -#define TX4939_IR_CIR 8 -#define TX4939_NUM_IR_SIO 4 -#define TX4939_IR_SIO(n) ((n) ? 43 + (n) : 9) /* 9,44-46 */ -#define TX4939_NUM_IR_DMA 4 -#define TX4939_IR_DMA(ch, n) (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */ -#define TX4939_IR_IRC 14 -#define TX4939_IR_PDMAC 15 -#define TX4939_NUM_IR_TMR 6 -#define TX4939_IR_TMR(n) (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */ -#define TX4939_NUM_IR_ATA 2 -#define TX4939_IR_ATA(n) (19 + (n)) -#define TX4939_IR_ACLC 21 -#define TX4939_IR_CIPHER 26 -#define TX4939_IR_INTA 27 -#define TX4939_IR_INTB 28 -#define TX4939_IR_INTC 29 -#define TX4939_IR_INTD 30 -#define TX4939_IR_I2C 33 -#define TX4939_IR_SPI 34 -#define TX4939_IR_PCIC 35 -#define TX4939_IR_PCIC1 36 -#define TX4939_IR_PCIERR 37 -#define TX4939_IR_PCIPME 38 -#define TX4939_IR_NDFMC 39 -#define TX4939_IR_ACLCPME 40 -#define TX4939_IR_RTC 41 -#define TX4939_IR_RND 42 -#define TX4939_IR_I2S 47 -#define TX4939_NUM_IR 64 - -#define TX4939_IRC_INT 2 /* IP[2] in Status register */ - -/* - * CCFG - */ -/* CCFG : Chip Configuration */ -#define TX4939_CCFG_PCIBOOT 0x0000040000000000ULL -#define TX4939_CCFG_WDRST 0x0000020000000000ULL -#define TX4939_CCFG_WDREXEN 0x0000010000000000ULL -#define TX4939_CCFG_BCFG_MASK 0x000000ff00000000ULL -#define TX4939_CCFG_GTOT_MASK 0x06000000 -#define TX4939_CCFG_GTOT_4096 0x06000000 -#define TX4939_CCFG_GTOT_2048 0x04000000 -#define TX4939_CCFG_GTOT_1024 0x02000000 -#define TX4939_CCFG_GTOT_512 0x00000000 -#define TX4939_CCFG_TINTDIS 0x01000000 -#define TX4939_CCFG_PCI66 0x00800000 -#define TX4939_CCFG_PCIMODE 0x00400000 -#define TX4939_CCFG_SSCG 0x00100000 -#define TX4939_CCFG_MULCLK_MASK 0x000e0000 -#define TX4939_CCFG_MULCLK_8 (0x7 << 17) -#define TX4939_CCFG_MULCLK_9 (0x0 << 17) -#define TX4939_CCFG_MULCLK_10 (0x1 << 17) -#define TX4939_CCFG_MULCLK_11 (0x2 << 17) -#define TX4939_CCFG_MULCLK_12 (0x3 << 17) -#define TX4939_CCFG_MULCLK_13 (0x4 << 17) -#define TX4939_CCFG_MULCLK_14 (0x5 << 17) -#define TX4939_CCFG_MULCLK_15 (0x6 << 17) -#define TX4939_CCFG_BEOW 0x00010000 -#define TX4939_CCFG_WR 0x00008000 -#define TX4939_CCFG_TOE 0x00004000 -#define TX4939_CCFG_PCIARB 0x00002000 -#define TX4939_CCFG_YDIVMODE_MASK 0x00001c00 -#define TX4939_CCFG_YDIVMODE_2 (0x0 << 10) -#define TX4939_CCFG_YDIVMODE_3 (0x1 << 10) -#define TX4939_CCFG_YDIVMODE_5 (0x6 << 10) -#define TX4939_CCFG_YDIVMODE_6 (0x7 << 10) -#define TX4939_CCFG_PTSEL 0x00000200 -#define TX4939_CCFG_BESEL 0x00000100 -#define TX4939_CCFG_SYSSP_MASK 0x000000c0 -#define TX4939_CCFG_ACKSEL 0x00000020 -#define TX4939_CCFG_ROMW 0x00000010 -#define TX4939_CCFG_ENDIAN 0x00000004 -#define TX4939_CCFG_ARMODE 0x00000002 -#define TX4939_CCFG_ACEHOLD 0x00000001 - -/* PCFG : Pin Configuration */ -#define TX4939_PCFG_SIO2MODE_MASK 0xc000000000000000ULL -#define TX4939_PCFG_SIO2MODE_GPIO 0x8000000000000000ULL -#define TX4939_PCFG_SIO2MODE_SIO2 0x4000000000000000ULL -#define TX4939_PCFG_SIO2MODE_SIO0 0x0000000000000000ULL -#define TX4939_PCFG_SPIMODE 0x2000000000000000ULL -#define TX4939_PCFG_I2CMODE 0x1000000000000000ULL -#define TX4939_PCFG_I2SMODE_MASK 0x0c00000000000000ULL -#define TX4939_PCFG_I2SMODE_GPIO 0x0c00000000000000ULL -#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL -#define TX4939_PCFG_I2SMODE_I2S_ALT 0x0400000000000000ULL -#define TX4939_PCFG_I2SMODE_ACLC 0x0000000000000000ULL -#define TX4939_PCFG_SIO3MODE 0x0200000000000000ULL -#define TX4939_PCFG_DMASEL3 0x0004000000000000ULL -#define TX4939_PCFG_DMASEL3_SIO0 0x0004000000000000ULL -#define TX4939_PCFG_DMASEL3_NDFC 0x0000000000000000ULL -#define TX4939_PCFG_VSSMODE 0x0000200000000000ULL -#define TX4939_PCFG_VPSMODE 0x0000100000000000ULL -#define TX4939_PCFG_ET1MODE 0x0000080000000000ULL -#define TX4939_PCFG_ET0MODE 0x0000040000000000ULL -#define TX4939_PCFG_ATA1MODE 0x0000020000000000ULL -#define TX4939_PCFG_ATA0MODE 0x0000010000000000ULL -#define TX4939_PCFG_BP_PLL 0x0000000100000000ULL - -#define TX4939_PCFG_SYSCLKEN 0x08000000 -#define TX4939_PCFG_PCICLKEN_ALL 0x000f0000 -#define TX4939_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) -#define TX4939_PCFG_SPEED1 0x00002000 -#define TX4939_PCFG_SPEED0 0x00001000 -#define TX4939_PCFG_ITMODE 0x00000300 -#define TX4939_PCFG_DMASEL_ALL (0x00000007 | TX4939_PCFG_DMASEL3) -#define TX4939_PCFG_DMASEL2 0x00000004 -#define TX4939_PCFG_DMASEL2_DRQ2 0x00000000 -#define TX4939_PCFG_DMASEL2_SIO0 0x00000004 -#define TX4939_PCFG_DMASEL1 0x00000002 -#define TX4939_PCFG_DMASEL1_DRQ1 0x00000000 -#define TX4939_PCFG_DMASEL0 0x00000001 -#define TX4939_PCFG_DMASEL0_DRQ0 0x00000000 - -/* CLKCTR : Clock Control */ -#define TX4939_CLKCTR_IOSCKD 0x8000000000000000ULL -#define TX4939_CLKCTR_SYSCKD 0x4000000000000000ULL -#define TX4939_CLKCTR_TM5CKD 0x2000000000000000ULL -#define TX4939_CLKCTR_TM4CKD 0x1000000000000000ULL -#define TX4939_CLKCTR_TM3CKD 0x0800000000000000ULL -#define TX4939_CLKCTR_CIRCKD 0x0400000000000000ULL -#define TX4939_CLKCTR_SIO3CKD 0x0200000000000000ULL -#define TX4939_CLKCTR_SIO2CKD 0x0100000000000000ULL -#define TX4939_CLKCTR_SIO1CKD 0x0080000000000000ULL -#define TX4939_CLKCTR_VPCCKD 0x0040000000000000ULL -#define TX4939_CLKCTR_EPCICKD 0x0020000000000000ULL -#define TX4939_CLKCTR_ETH1CKD 0x0008000000000000ULL -#define TX4939_CLKCTR_ATA1CKD 0x0004000000000000ULL -#define TX4939_CLKCTR_BROMCKD 0x0002000000000000ULL -#define TX4939_CLKCTR_NDCCKD 0x0001000000000000ULL -#define TX4939_CLKCTR_I2CCKD 0x0000800000000000ULL -#define TX4939_CLKCTR_ETH0CKD 0x0000400000000000ULL -#define TX4939_CLKCTR_SPICKD 0x0000200000000000ULL -#define TX4939_CLKCTR_SRAMCKD 0x0000100000000000ULL -#define TX4939_CLKCTR_PCI1CKD 0x0000080000000000ULL -#define TX4939_CLKCTR_DMA1CKD 0x0000040000000000ULL -#define TX4939_CLKCTR_ACLCKD 0x0000020000000000ULL -#define TX4939_CLKCTR_ATA0CKD 0x0000010000000000ULL -#define TX4939_CLKCTR_DMA0CKD 0x0000008000000000ULL -#define TX4939_CLKCTR_PCICCKD 0x0000004000000000ULL -#define TX4939_CLKCTR_I2SCKD 0x0000002000000000ULL -#define TX4939_CLKCTR_TM0CKD 0x0000001000000000ULL -#define TX4939_CLKCTR_TM1CKD 0x0000000800000000ULL -#define TX4939_CLKCTR_TM2CKD 0x0000000400000000ULL -#define TX4939_CLKCTR_SIO0CKD 0x0000000200000000ULL -#define TX4939_CLKCTR_CYPCKD 0x0000000100000000ULL -#define TX4939_CLKCTR_IOSRST 0x80000000 -#define TX4939_CLKCTR_SYSRST 0x40000000 -#define TX4939_CLKCTR_TM5RST 0x20000000 -#define TX4939_CLKCTR_TM4RST 0x10000000 -#define TX4939_CLKCTR_TM3RST 0x08000000 -#define TX4939_CLKCTR_CIRRST 0x04000000 -#define TX4939_CLKCTR_SIO3RST 0x02000000 -#define TX4939_CLKCTR_SIO2RST 0x01000000 -#define TX4939_CLKCTR_SIO1RST 0x00800000 -#define TX4939_CLKCTR_VPCRST 0x00400000 -#define TX4939_CLKCTR_EPCIRST 0x00200000 -#define TX4939_CLKCTR_ETH1RST 0x00080000 -#define TX4939_CLKCTR_ATA1RST 0x00040000 -#define TX4939_CLKCTR_BROMRST 0x00020000 -#define TX4939_CLKCTR_NDCRST 0x00010000 -#define TX4939_CLKCTR_I2CRST 0x00008000 -#define TX4939_CLKCTR_ETH0RST 0x00004000 -#define TX4939_CLKCTR_SPIRST 0x00002000 -#define TX4939_CLKCTR_SRAMRST 0x00001000 -#define TX4939_CLKCTR_PCI1RST 0x00000800 -#define TX4939_CLKCTR_DMA1RST 0x00000400 -#define TX4939_CLKCTR_ACLRST 0x00000200 -#define TX4939_CLKCTR_ATA0RST 0x00000100 -#define TX4939_CLKCTR_DMA0RST 0x00000080 -#define TX4939_CLKCTR_PCICRST 0x00000040 -#define TX4939_CLKCTR_I2SRST 0x00000020 -#define TX4939_CLKCTR_TM0RST 0x00000010 -#define TX4939_CLKCTR_TM1RST 0x00000008 -#define TX4939_CLKCTR_TM2RST 0x00000004 -#define TX4939_CLKCTR_SIO0RST 0x00000002 -#define TX4939_CLKCTR_CYPRST 0x00000001 - -/* - * CRYPTO - */ -#define TX4939_CRYPTO_CSR_SAESO 0x08000000 -#define TX4939_CRYPTO_CSR_SAESI 0x04000000 -#define TX4939_CRYPTO_CSR_SDESO 0x02000000 -#define TX4939_CRYPTO_CSR_SDESI 0x01000000 -#define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000 -#define TX4939_CRYPTO_CSR_INDXBST(n) ((n) << 20) -#define TX4939_CRYPTO_CSR_TOINT 0x00080000 -#define TX4939_CRYPTO_CSR_DCINT 0x00040000 -#define TX4939_CRYPTO_CSR_GBINT 0x00010000 -#define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000 -#define TX4939_CRYPTO_CSR_INDXAST(n) ((n) << 13) -#define TX4939_CRYPTO_CSR_CSWAP_MASK 0x00001800 -#define TX4939_CRYPTO_CSR_CSWAP_NONE 0x00000000 -#define TX4939_CRYPTO_CSR_CSWAP_IN 0x00000800 -#define TX4939_CRYPTO_CSR_CSWAP_OUT 0x00001000 -#define TX4939_CRYPTO_CSR_CSWAP_BOTH 0x00001800 -#define TX4939_CRYPTO_CSR_CDIV_MASK 0x00000600 -#define TX4939_CRYPTO_CSR_CDIV_DIV2 0x00000000 -#define TX4939_CRYPTO_CSR_CDIV_DIV1 0x00000200 -#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT 0x00000400 -#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT 0x00000600 -#define TX4939_CRYPTO_CSR_PDINT_MASK 0x000000c0 -#define TX4939_CRYPTO_CSR_PDINT_ALL 0x00000000 -#define TX4939_CRYPTO_CSR_PDINT_END 0x00000040 -#define TX4939_CRYPTO_CSR_PDINT_NEXT 0x00000080 -#define TX4939_CRYPTO_CSR_PDINT_NONE 0x000000c0 -#define TX4939_CRYPTO_CSR_GINTE 0x00000008 -#define TX4939_CRYPTO_CSR_RSTD 0x00000004 -#define TX4939_CRYPTO_CSR_RSTC 0x00000002 -#define TX4939_CRYPTO_CSR_ENCR 0x00000001 - -/* bits for tx4939_crypto_reg.cdr.gen.ctrl */ -#define TX4939_CRYPTO_CTX_ENGINE_MASK 0x00000003 -#define TX4939_CRYPTO_CTX_ENGINE_DES 0x00000000 -#define TX4939_CRYPTO_CTX_ENGINE_AES 0x00000001 -#define TX4939_CRYPTO_CTX_ENGINE_MD5 0x00000002 -#define TX4939_CRYPTO_CTX_ENGINE_SHA1 0x00000003 -#define TX4939_CRYPTO_CTX_TDMS 0x00000010 -#define TX4939_CRYPTO_CTX_CMS 0x00000020 -#define TX4939_CRYPTO_CTX_DMS 0x00000040 -#define TX4939_CRYPTO_CTX_UPDATE 0x00000080 - -/* bits for tx4939_crypto_desc.ctrl */ -#define TX4939_CRYPTO_DESC_OB_CNT_MASK 0xffe00000 -#define TX4939_CRYPTO_DESC_OB_CNT(cnt) ((cnt) << 21) -#define TX4939_CRYPTO_DESC_IB_CNT_MASK 0x001ffc00 -#define TX4939_CRYPTO_DESC_IB_CNT(cnt) ((cnt) << 10) -#define TX4939_CRYPTO_DESC_START 0x00000200 -#define TX4939_CRYPTO_DESC_END 0x00000100 -#define TX4939_CRYPTO_DESC_XOR 0x00000010 -#define TX4939_CRYPTO_DESC_LAST 0x00000008 -#define TX4939_CRYPTO_DESC_ERR_MASK 0x00000006 -#define TX4939_CRYPTO_DESC_ERR_NONE 0x00000000 -#define TX4939_CRYPTO_DESC_ERR_TOUT 0x00000002 -#define TX4939_CRYPTO_DESC_ERR_DIGEST 0x00000004 -#define TX4939_CRYPTO_DESC_OWN 0x00000001 - -/* bits for tx4939_crypto_desc.index */ -#define TX4939_CRYPTO_DESC_HASH_IDX_MASK 0x00000070 -#define TX4939_CRYPTO_DESC_HASH_IDX(idx) ((idx) << 4) -#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK 0x00000007 -#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx) ((idx) << 0) - -#define TX4939_CRYPTO_NR_SET 6 - -#define TX4939_CRYPTO_RCSR_INTE 0x00000008 -#define TX4939_CRYPTO_RCSR_RST 0x00000004 -#define TX4939_CRYPTO_RCSR_FIN 0x00000002 -#define TX4939_CRYPTO_RCSR_ST 0x00000001 - -/* - * VPC - */ -#define TX4939_VPC_CSR_GBINT 0x00010000 -#define TX4939_VPC_CSR_SWAPO 0x00000020 -#define TX4939_VPC_CSR_SWAPI 0x00000010 -#define TX4939_VPC_CSR_GINTE 0x00000008 -#define TX4939_VPC_CSR_RSTD 0x00000004 -#define TX4939_VPC_CSR_RSTVPC 0x00000002 - -#define TX4939_VPC_CTRLA_VDPSN 0x00000200 -#define TX4939_VPC_CTRLA_PBUSY 0x00000100 -#define TX4939_VPC_CTRLA_DCINT 0x00000080 -#define TX4939_VPC_CTRLA_UOINT 0x00000040 -#define TX4939_VPC_CTRLA_PDINT_MASK 0x00000030 -#define TX4939_VPC_CTRLA_PDINT_ALL 0x00000000 -#define TX4939_VPC_CTRLA_PDINT_NEXT 0x00000010 -#define TX4939_VPC_CTRLA_PDINT_NONE 0x00000030 -#define TX4939_VPC_CTRLA_VDVLDP 0x00000008 -#define TX4939_VPC_CTRLA_VDMODE 0x00000004 -#define TX4939_VPC_CTRLA_VDFOR 0x00000002 -#define TX4939_VPC_CTRLA_ENVPC 0x00000001 - -/* bits for tx4939_vpc_desc.ctrl1 */ -#define TX4939_VPC_DESC_CTRL1_ERR_MASK 0x00000006 -#define TX4939_VPC_DESC_CTRL1_OWN 0x00000001 - -#define tx4939_ddrcptr ((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG) -#define tx4939_ebuscptr tx4938_ebuscptr -#define tx4939_ircptr \ - ((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG) -#define tx4939_pcicptr tx4938_pcicptr -#define tx4939_pcic1ptr tx4938_pcic1ptr -#define tx4939_ccfgptr \ - ((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG) -#define tx4939_sramcptr tx4938_sramcptr -#define tx4939_cryptoptr \ - ((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG) -#define tx4939_vpcptr ((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG) - -#define TX4939_REV_MAJ_MIN() \ - ((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff) -#define TX4939_REV_PCODE() \ - ((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16) -#define TX4939_CCFG_BCFG() \ - ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \ - >> 32)) - -#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits) -#define tx4939_ccfg_set(bits) tx4938_ccfg_set(bits) -#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new) - -#define TX4939_EBUSC_CR(ch) TX4927_EBUSC_CR(ch) -#define TX4939_EBUSC_BA(ch) TX4927_EBUSC_BA(ch) -#define TX4939_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch) -#define TX4939_EBUSC_WIDTH(ch) \ - (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1)) - -/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2 (14.745MHz for MST 20MHz) */ -#define TX4939_SCLK0(mst) \ - ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2) - -void tx4939_wdt_init(void); -void tx4939_add_memory_regions(void); -void tx4939_setup(void); -void tx4939_time_init(unsigned int tmrnr); -void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask); -void tx4939_spi_init(int busid); -void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1); -int tx4939_report_pciclk(void); -void tx4939_report_pci1clk(void); -struct pci_dev; -int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot); -int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -void tx4939_setup_pcierr_irq(void); -void tx4939_irq_init(void); -int tx4939_irq(void); -void tx4939_mtd_init(int ch); -void tx4939_ata_init(void); -void tx4939_rtc_init(void); -void tx4939_ndfmc_init(unsigned int hold, unsigned int spw, - unsigned char ch_mask, unsigned char wide_mask); -void tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1); -void tx4939_aclc_init(void); -void tx4939_sramc_init(void); -void tx4939_rng_init(void); - -#endif /* __ASM_TXX9_TX4939_H */ |