18 files changed, 40 insertions, 490 deletions

diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 5d1addac5e28..853a43ee4b44 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -58,16 +58,13 @@ obj-$(CONFIG_CPU_BMIPS)		+= smp-bmips.o bmips_vec.o bmips_5xxx_init.o
 obj-$(CONFIG_MIPS_MT)		+= mips-mt.o
 obj-$(CONFIG_MIPS_MT_FPAFF)	+= mips-mt-fpaff.o
 obj-$(CONFIG_MIPS_MT_SMP)	+= smp-mt.o
-obj-$(CONFIG_MIPS_CMP)		+= smp-cmp.o
 obj-$(CONFIG_MIPS_CPS)		+= smp-cps.o cps-vec.o
 obj-$(CONFIG_MIPS_CPS_NS16550)	+= cps-vec-ns16550.o
 obj-$(CONFIG_MIPS_SPRAM)	+= spram.o
 
 obj-$(CONFIG_MIPS_VPE_LOADER)	+= vpe.o
-obj-$(CONFIG_MIPS_VPE_LOADER_CMP) += vpe-cmp.o
 obj-$(CONFIG_MIPS_VPE_LOADER_MT) += vpe-mt.o
 obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
-obj-$(CONFIG_MIPS_VPE_APSP_API_CMP) += rtlx-cmp.o
 obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o
 
 obj-$(CONFIG_MIPS_MSC)		+= irq-msc01.o
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index c4501897b870..40fd4051bb3d 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -306,7 +306,10 @@ void output_octeon_cop2_state_defines(void)
 	OFFSET(OCTEON_CP2_HSH_IVW,	octeon_cop2_state, cop2_hsh_ivw);
 	OFFSET(OCTEON_CP2_SHA3,		octeon_cop2_state, cop2_sha3);
 	OFFSET(THREAD_CP2,	task_struct, thread.cp2);
+#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
+    CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
 	OFFSET(THREAD_CVMSEG,	task_struct, thread.cvmseg.cvmseg);
+#endif
 	BLANK();
 }
 #endif
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 8ef492da827f..64ecfdac6580 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -116,6 +116,8 @@ not_nmi:
 	li	t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
 	mtc0	t0, CP0_STATUS
 
+	/* We don't know how to do coherence setup on earlier ISA */
+#if MIPS_ISA_REV > 0
 	/* Skip cache & coherence setup if we're already coherent */
 	lw	s7, GCR_CL_COHERENCE_OFS(s1)
 	bnez	s7, 1f
@@ -129,6 +131,7 @@ not_nmi:
 	li	t0, 0xff
 	sw	t0, GCR_CL_COHERENCE_OFS(s1)
 	ehb
+#endif /* MIPS_ISA_REV > 0 */
 
 	/* Set Kseg0 CCA to that in s0 */
 1:	mfc0	t0, CP0_CONFIG
@@ -515,6 +518,7 @@ LEAF(mips_cps_boot_vpes)
 	 nop
 	END(mips_cps_boot_vpes)
 
+#if MIPS_ISA_REV > 0
 LEAF(mips_cps_cache_init)
 	/*
 	 * Clear the bits used to index the caches. Note that the architecture
@@ -588,6 +592,7 @@ dcache_done:
 	jr	ra
 	 nop
 	END(mips_cps_cache_init)
+#endif /* MIPS_ISA_REV > 0 */
 
 #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
 
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 7ddf07f255f3..6d15a398d389 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1602,6 +1602,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);
+	/* Octeon has different cache interface */
+	c->options &= ~MIPS_CPU_4K_CACHE;
 	switch (c->processor_id & PRID_IMP_MASK) {
 	case PRID_IMP_CAVIUM_CN38XX:
 	case PRID_IMP_CAVIUM_CN31XX:
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index b4f7d950c846..3f00788b0871 100644
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -181,11 +181,16 @@ static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);
 
 phys_addr_t __mips_cm_phys_base(void)
 {
-	u32 config3 = read_c0_config3();
 	unsigned long cmgcr;
 
 	/* Check the CMGCRBase register is implemented */
-	if (!(config3 & MIPS_CONF3_CMGCR))
+	if (!(read_c0_config() & MIPS_CONF_M))
+		return 0;
+
+	if (!(read_c0_config2() & MIPS_CONF_M))
+		return 0;
+
+	if (!(read_c0_config3() & MIPS_CONF3_CMGCR))
 		return 0;
 
 	/* Read the address from CMGCRBase */
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index dc023a979803..f88b7919f11f 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -234,7 +234,7 @@ static int __init mips_mt_init(void)
 {
 	struct class *mtc;
 
-	mtc = class_create(THIS_MODULE, "mt");
+	mtc = class_create("mt");
 	if (IS_ERR(mtc))
 		return PTR_ERR(mtc);
 
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 896080b445c2..9b7c8ab6f08c 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -428,7 +428,6 @@ done_restore:
 	jr	ra
 	 nop
 	.space 30 * 4, 0
-octeon_mult_save_end:
 	EXPORT(octeon_mult_save_end)
 	END(octeon_mult_save)
 
@@ -448,7 +447,6 @@ octeon_mult_save_end:
 	sd	k0, PT_MPL+8(sp)      /* PT_MPL+8  has MPL1 */
 	jr	ra
 	 sd	k1, PT_MPL+16(sp)     /* PT_MPL+16 has MPL2 */
-octeon_mult_save2_end:
 	EXPORT(octeon_mult_save2_end)
 	END(octeon_mult_save2)
 
@@ -480,7 +478,6 @@ octeon_mult_save2_end:
 	sd	$10, PT_MPL+(4*8)(sp)	/* store MPL4 */
 	jr	ra
 	 sd	$11, PT_MPL+(5*8)(sp)	/* store MPL5 */
-octeon_mult_save3_end:
 	EXPORT(octeon_mult_save3_end)
 	END(octeon_mult_save3)
 	.set pop
@@ -498,7 +495,6 @@ octeon_mult_save3_end:
 	jr	ra
 	 nop
 	.space 30 * 4, 0
-octeon_mult_restore_end:
 	EXPORT(octeon_mult_restore_end)
 	END(octeon_mult_restore)
 
@@ -517,7 +513,6 @@ octeon_mult_restore_end:
 	mtp1	v0			/* P1 */
 	jr	ra
 	 mtp0	v1			/* P0 */
-octeon_mult_restore2_end:
 	EXPORT(octeon_mult_restore2_end)
 	END(octeon_mult_restore2)
 
@@ -548,7 +543,6 @@ octeon_mult_restore2_end:
 	.word	0x714b000b
 	/* mtp2	$10, $11		   restore P2 and P5 */
 
-octeon_mult_restore3_end:
 	EXPORT(octeon_mult_restore3_end)
 	END(octeon_mult_restore3)
 	.set pop
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 093dbbd6b843..a3225912c862 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -40,7 +40,7 @@
 #include <asm/stacktrace.h>
 
 #ifdef CONFIG_HOTPLUG_CPU
-void arch_cpu_idle_dead(void)
+void __noreturn arch_cpu_idle_dead(void)
 {
 	play_dead();
 }
diff --git a/arch/mips/kernel/rtlx-cmp.c b/arch/mips/kernel/rtlx-cmp.c
deleted file mode 100644
index d26dcc4b46e7..000000000000
--- a/arch/mips/kernel/rtlx-cmp.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- * Copyright (C) 2013 Imagination Technologies Ltd.
- */
-#include <linux/device.h>
-#include <linux/fs.h>
-#include <linux/err.h>
-#include <linux/wait.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-
-#include <asm/mips_mt.h>
-#include <asm/vpe.h>
-#include <asm/rtlx.h>
-
-static int major;
-
-static void rtlx_interrupt(void)
-{
-	int i;
-	struct rtlx_info *info;
-	struct rtlx_info **p = vpe_get_shared(aprp_cpu_index());
-
-	if (p == NULL || *p == NULL)
-		return;
-
-	info = *p;
-
-	if (info->ap_int_pending == 1 && smp_processor_id() == 0) {
-		for (i = 0; i < RTLX_CHANNELS; i++) {
-			wake_up(&channel_wqs[i].lx_queue);
-			wake_up(&channel_wqs[i].rt_queue);
-		}
-		info->ap_int_pending = 0;
-	}
-}
-
-void _interrupt_sp(void)
-{
-	smp_send_reschedule(aprp_cpu_index());
-}
-
-int __init rtlx_module_init(void)
-{
-	struct device *dev;
-	int i, err;
-
-	if (!cpu_has_mipsmt) {
-		pr_warn("VPE loader: not a MIPS MT capable processor\n");
-		return -ENODEV;
-	}
-
-	if (num_possible_cpus() - aprp_cpu_index() < 1) {
-		pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n"
-			"Pass maxcpus=<n> argument as kernel argument\n");
-
-		return -ENODEV;
-	}
-
-	major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops);
-	if (major < 0) {
-		pr_err("rtlx_module_init: unable to register device\n");
-		return major;
-	}
-
-	/* initialise the wait queues */
-	for (i = 0; i < RTLX_CHANNELS; i++) {
-		init_waitqueue_head(&channel_wqs[i].rt_queue);
-		init_waitqueue_head(&channel_wqs[i].lx_queue);
-		atomic_set(&channel_wqs[i].in_open, 0);
-		mutex_init(&channel_wqs[i].mutex);
-
-		dev = device_create(mt_class, NULL, MKDEV(major, i), NULL,
-				    "%s%d", RTLX_MODULE_NAME, i);
-		if (IS_ERR(dev)) {
-			while (i--)
-				device_destroy(mt_class, MKDEV(major, i));
-
-			err = PTR_ERR(dev);
-			goto out_chrdev;
-		}
-	}
-
-	/* set up notifiers */
-	rtlx_notify.start = rtlx_starting;
-	rtlx_notify.stop = rtlx_stopping;
-	vpe_notify(aprp_cpu_index(), &rtlx_notify);
-
-	if (cpu_has_vint) {
-		aprp_hook = rtlx_interrupt;
-	} else {
-		pr_err("APRP RTLX init on non-vectored-interrupt processor\n");
-		err = -ENODEV;
-		goto out_class;
-	}
-
-	return 0;
-
-out_class:
-	for (i = 0; i < RTLX_CHANNELS; i++)
-		device_destroy(mt_class, MKDEV(major, i));
-out_chrdev:
-	unregister_chrdev(major, RTLX_MODULE_NAME);
-
-	return err;
-}
-
-void __exit rtlx_module_exit(void)
-{
-	int i;
-
-	for (i = 0; i < RTLX_CHANNELS; i++)
-		device_destroy(mt_class, MKDEV(major, i));
-
-	unregister_chrdev(major, RTLX_MODULE_NAME);
-
-	aprp_hook = NULL;
-}
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index f1c88f8a1dc5..febdc5564638 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -786,7 +786,8 @@ void __init setup_arch(char **cmdline_p)
 	setup_early_printk();
 #endif
 	cpu_report();
-	check_bugs_early();
+	if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64))
+		check_bugs64_early();
 
 #if defined(CONFIG_VT)
 #if defined(CONFIG_VGA_CONSOLE)
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index f5d7bfa3472a..15466d4cf4a0 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -54,6 +54,8 @@ static void bmips_set_reset_vec(int cpu, u32 val);
 
 #ifdef CONFIG_SMP
 
+#include <asm/smp.h>
+
 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
 unsigned long bmips_smp_boot_sp;
 unsigned long bmips_smp_boot_gp;
@@ -413,6 +415,8 @@ void __ref play_dead(void)
 	"	wait\n"
 	"	j	bmips_secondary_reentry\n"
 	: : : "memory");
+
+	BUG();
 }
 
 #endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
deleted file mode 100644
index 76f5824cdb00..000000000000
--- a/arch/mips/kernel/smp-cmp.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- *
- * Copyright (C) 2007 MIPS Technologies, Inc.
- *    Chris Dearman (chris@mips.com)
- */
-
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/sched/task_stack.h>
-#include <linux/smp.h>
-#include <linux/cpumask.h>
-#include <linux/interrupt.h>
-#include <linux/compiler.h>
-
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-#include <asm/cpu.h>
-#include <asm/processor.h>
-#include <asm/hardirq.h>
-#include <asm/mmu_context.h>
-#include <asm/smp.h>
-#include <asm/time.h>
-#include <asm/mipsregs.h>
-#include <asm/mipsmtregs.h>
-#include <asm/mips_mt.h>
-#include <asm/amon.h>
-
-static void cmp_init_secondary(void)
-{
-	struct cpuinfo_mips *c __maybe_unused = &current_cpu_data;
-
-	/* Assume GIC is present */
-	change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
-				 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
-
-	/* Enable per-cpu interrupts: platform specific */
-
-#ifdef CONFIG_MIPS_MT_SMP
-	if (cpu_has_mipsmt)
-		cpu_set_vpe_id(c, (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
-				  TCBIND_CURVPE);
-#endif
-}
-
-static void cmp_smp_finish(void)
-{
-	pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
-
-	/* CDFIXME: remove this? */
-	write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
-
-#ifdef CONFIG_MIPS_MT_FPAFF
-	/* If we have an FPU, enroll ourselves in the FPU-full mask */
-	if (cpu_has_fpu)
-		cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
-#endif /* CONFIG_MIPS_MT_FPAFF */
-
-	local_irq_enable();
-}
-
-/*
- * Setup the PC, SP, and GP of a secondary processor and start it running
- * smp_bootstrap is the place to resume from
- * __KSTK_TOS(idle) is apparently the stack pointer
- * (unsigned long)idle->thread_info the gp
- */
-static int cmp_boot_secondary(int cpu, struct task_struct *idle)
-{
-	struct thread_info *gp = task_thread_info(idle);
-	unsigned long sp = __KSTK_TOS(idle);
-	unsigned long pc = (unsigned long)&smp_bootstrap;
-	unsigned long a0 = 0;
-
-	pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(),
-		__func__, cpu);
-
-#if 0
-	/* Needed? */
-	flush_icache_range((unsigned long)gp,
-			   (unsigned long)(gp + sizeof(struct thread_info)));
-#endif
-
-	amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
-	return 0;
-}
-
-/*
- * Common setup before any secondaries are started
- */
-void __init cmp_smp_setup(void)
-{
-	int i;
-	int ncpu = 0;
-
-	pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__);
-
-#ifdef CONFIG_MIPS_MT_FPAFF
-	/* If we have an FPU, enroll ourselves in the FPU-full mask */
-	if (cpu_has_fpu)
-		cpumask_set_cpu(0, &mt_fpu_cpumask);
-#endif /* CONFIG_MIPS_MT_FPAFF */
-
-	for (i = 1; i < NR_CPUS; i++) {
-		if (amon_cpu_avail(i)) {
-			set_cpu_possible(i, true);
-			__cpu_number_map[i]	= ++ncpu;
-			__cpu_logical_map[ncpu] = i;
-		}
-	}
-
-	if (cpu_has_mipsmt) {
-		unsigned int nvpe = 1;
-#ifdef CONFIG_MIPS_MT_SMP
-		unsigned int mvpconf0 = read_c0_mvpconf0();
-
-		nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
-#endif
-		smp_num_siblings = nvpe;
-	}
-	pr_info("Detected %i available secondary CPU(s)\n", ncpu);
-}
-
-void __init cmp_prepare_cpus(unsigned int max_cpus)
-{
-	pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n",
-		 smp_processor_id(), __func__, max_cpus);
-
-#ifdef CONFIG_MIPS_MT
-	/*
-	 * FIXME: some of these options are per-system, some per-core and
-	 * some per-cpu
-	 */
-	mips_mt_set_cpuoptions();
-#endif
-
-}
-
-const struct plat_smp_ops cmp_smp_ops = {
-	.send_ipi_single	= mips_smp_send_ipi_single,
-	.send_ipi_mask		= mips_smp_send_ipi_mask,
-	.init_secondary		= cmp_init_secondary,
-	.smp_finish		= cmp_smp_finish,
-	.boot_secondary		= cmp_boot_secondary,
-	.smp_setup		= cmp_smp_setup,
-	.prepare_cpus		= cmp_prepare_cpus,
-};
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 4fc288bb85b9..62f677b2306f 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -20,6 +20,7 @@
 #include <asm/mipsregs.h>
 #include <asm/pm-cps.h>
 #include <asm/r4kcache.h>
+#include <asm/smp.h>
 #include <asm/smp-cps.h>
 #include <asm/time.h>
 #include <asm/uasm.h>
@@ -361,6 +362,8 @@ out:
 
 static void cps_init_secondary(void)
 {
+	int core = cpu_core(&current_cpu_data);
+
 	/* Disable MT - we only want to run 1 TC per VPE */
 	if (cpu_has_mipsmt)
 		dmt();
@@ -376,6 +379,9 @@ static void cps_init_secondary(void)
 		BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
 	}
 
+	if (core > 0 && !read_gcr_cl_coherence())
+		pr_warn("Core %u is not in coherent domain\n", core);
+
 	if (cpu_has_veic)
 		clear_c0_status(ST0_IM);
 	else
diff --git a/arch/mips/kernel/uprobes.c b/arch/mips/kernel/uprobes.c
index 6c063aa188e6..401b148f8917 100644
--- a/arch/mips/kernel/uprobes.c
+++ b/arch/mips/kernel/uprobes.c
@@ -191,6 +191,7 @@ void arch_uprobe_abort_xol(struct arch_uprobe *aup,
 {
 	struct uprobe_task *utask = current->utask;
 
+	current->thread.trap_nr = utask->autask.saved_trap_nr;
 	instruction_pointer_set(regs, utask->vaddr);
 }
 
@@ -207,24 +208,6 @@ unsigned long arch_uretprobe_hijack_return_addr(
 	return ra;
 }
 
-/**
- * set_swbp - store breakpoint at a given address.
- * @auprobe: arch specific probepoint information.
- * @mm: the probed process address space.
- * @vaddr: the virtual address to insert the opcode.
- *
- * For mm @mm, store the breakpoint instruction at @vaddr.
- * Return 0 (success) or a negative errno.
- *
- * This version overrides the weak version in kernel/events/uprobes.c.
- * It is required to handle MIPS16 and microMIPS.
- */
-int __weak set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm,
-	unsigned long vaddr)
-{
-	return uprobe_write_opcode(auprobe, mm, vaddr, UPROBE_SWBP_INSN);
-}
-
 void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
 				  void *src, unsigned long len)
 {
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 52cbde60edf5..9ff55cb80a64 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -15,6 +15,8 @@
 #define EMITS_PT_NOTE
 #endif
 
+#define RUNTIME_DISCARD_EXIT
+
 #include <asm-generic/vmlinux.lds.h>
 
 #undef mips
diff --git a/arch/mips/kernel/vpe-cmp.c b/arch/mips/kernel/vpe-cmp.c
deleted file mode 100644
index 92140edb3ce3..000000000000
--- a/arch/mips/kernel/vpe-cmp.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
- * Copyright (C) 2013 Imagination Technologies Ltd.
- */
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/fs.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-
-#include <asm/vpe.h>
-
-static int major;
-
-void cleanup_tc(struct tc *tc)
-{
-
-}
-
-static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
-			  const char *buf, size_t len)
-{
-	struct vpe *vpe = get_vpe(aprp_cpu_index());
-	struct vpe_notifications *notifier;
-
-	list_for_each_entry(notifier, &vpe->notify, list)
-		notifier->stop(aprp_cpu_index());
-
-	release_progmem(vpe->load_addr);
-	vpe->state = VPE_STATE_UNUSED;
-
-	return len;
-}
-static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill);
-
-static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr,
-			 char *buf)
-{
-	struct vpe *vpe = get_vpe(aprp_cpu_index());
-
-	return sprintf(buf, "%d\n", vpe->ntcs);
-}
-
-static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr,
-			  const char *buf, size_t len)
-{
-	struct vpe *vpe = get_vpe(aprp_cpu_index());
-	unsigned long new;
-	int ret;
-
-	ret = kstrtoul(buf, 0, &new);
-	if (ret < 0)
-		return ret;
-
-	/* APRP can only reserve one TC in a VPE and no more. */
-	if (new != 1)
-		return -EINVAL;
-
-	vpe->ntcs = new;
-
-	return len;
-}
-static DEVICE_ATTR_RW(ntcs);
-
-static struct attribute *vpe_attrs[] = {
-	&dev_attr_kill.attr,
-	&dev_attr_ntcs.attr,
-	NULL,
-};
-ATTRIBUTE_GROUPS(vpe);
-
-static void vpe_device_release(struct device *cd)
-{
-}
-
-static struct class vpe_class = {
-	.name = "vpe",
-	.owner = THIS_MODULE,
-	.dev_release = vpe_device_release,
-	.dev_groups = vpe_groups,
-};
-
-static struct device vpe_device;
-
-int __init vpe_module_init(void)
-{
-	struct vpe *v = NULL;
-	struct tc *t;
-	int err;
-
-	if (!cpu_has_mipsmt) {
-		pr_warn("VPE loader: not a MIPS MT capable processor\n");
-		return -ENODEV;
-	}
-
-	if (num_possible_cpus() - aprp_cpu_index() < 1) {
-		pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n"
-			"Pass maxcpus=<n> argument as kernel argument\n");
-		return -ENODEV;
-	}
-
-	major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops);
-	if (major < 0) {
-		pr_warn("VPE loader: unable to register character device\n");
-		return major;
-	}
-
-	err = class_register(&vpe_class);
-	if (err) {
-		pr_err("vpe_class registration failed\n");
-		goto out_chrdev;
-	}
-
-	device_initialize(&vpe_device);
-	vpe_device.class	= &vpe_class;
-	vpe_device.parent	= NULL;
-	dev_set_name(&vpe_device, "vpe_sp");
-	vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR);
-	err = device_add(&vpe_device);
-	if (err) {
-		pr_err("Adding vpe_device failed\n");
-		goto out_class;
-	}
-
-	t = alloc_tc(aprp_cpu_index());
-	if (!t) {
-		pr_warn("VPE: unable to allocate TC\n");
-		err = -ENOMEM;
-		goto out_dev;
-	}
-
-	/* VPE */
-	v = alloc_vpe(aprp_cpu_index());
-	if (v == NULL) {
-		pr_warn("VPE: unable to allocate VPE\n");
-		kfree(t);
-		err = -ENOMEM;
-		goto out_dev;
-	}
-
-	v->ntcs = 1;
-
-	/* add the tc to the list of this vpe's tc's. */
-	list_add(&t->tc, &v->tc);
-
-	/* TC */
-	t->pvpe = v;	/* set the parent vpe */
-
-	return 0;
-
-out_dev:
-	device_del(&vpe_device);
-
-out_class:
-	put_device(&vpe_device);
-	class_unregister(&vpe_class);
-
-out_chrdev:
-	unregister_chrdev(major, VPE_MODULE_NAME);
-
-	return err;
-}
-
-void __exit vpe_module_exit(void)
-{
-	struct vpe *v, *n;
-
-	device_unregister(&vpe_device);
-	class_unregister(&vpe_class);
-	unregister_chrdev(major, VPE_MODULE_NAME);
-
-	/* No locking needed here */
-	list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list)
-		if (v->state != VPE_STATE_UNUSED)
-			release_vpe(v);
-}
diff --git a/arch/mips/kernel/vpe-mt.c b/arch/mips/kernel/vpe-mt.c
index 223d6274f2e5..667bc75f6420 100644
--- a/arch/mips/kernel/vpe-mt.c
+++ b/arch/mips/kernel/vpe-mt.c
@@ -316,7 +316,6 @@ static void vpe_device_release(struct device *cd)
 
 static struct class vpe_class = {
 	.name = "vpe",
-	.owner = THIS_MODULE,
 	.dev_release = vpe_device_release,
 	.dev_groups = vpe_groups,
 };
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 13294972707b..e9a0cfd02ae2 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -199,18 +199,17 @@ static void layout_sections(struct module *mod, const Elf_Ehdr *hdr,
 	for (m = 0; m < ARRAY_SIZE(masks); ++m) {
 		for (i = 0; i < hdr->e_shnum; ++i) {
 			Elf_Shdr *s = &sechdrs[i];
+			struct module_memory *mod_mem;
+
+			mod_mem = &mod->mem[MOD_TEXT];
 
 			if ((s->sh_flags & masks[m][0]) != masks[m][0]
 			    || (s->sh_flags & masks[m][1])
 			    || s->sh_entsize != ~0UL)
 				continue;
 			s->sh_entsize =
-				get_offset((unsigned long *)&mod->core_layout.size, s);
+				get_offset((unsigned long *)&mod_mem->size, s);
 		}
-
-		if (m == 0)
-			mod->core_layout.text_size = mod->core_layout.size;
-
 	}
 }
 
@@ -641,7 +640,7 @@ static int vpe_elfload(struct vpe *v)
 		layout_sections(&mod, hdr, sechdrs, secstrings);
 	}
 
-	v->load_addr = alloc_progmem(mod.core_layout.size);
+	v->load_addr = alloc_progmem(mod.mem[MOD_TEXT].size);
 	if (!v->load_addr)
 		return -ENOMEM;
 
@@ -795,7 +794,7 @@ static int vpe_open(struct inode *inode, struct file *filp)
 
 static int vpe_release(struct inode *inode, struct file *filp)
 {
-#if defined(CONFIG_MIPS_VPE_LOADER_MT) || defined(CONFIG_MIPS_VPE_LOADER_CMP)
+#ifdef CONFIG_MIPS_VPE_LOADER_MT
 	struct vpe *v;
 	Elf_Ehdr *hdr;
 	int ret = 0;