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-rw-r--r--arch/mips/mm/c-r4k.c2
-rw-r--r--arch/mips/mm/cache.c2
-rw-r--r--arch/mips/mm/dma-default.c46
-rw-r--r--arch/mips/mm/init.c1
-rw-r--r--arch/mips/mm/mmap.c1
-rw-r--r--arch/mips/mm/sc-mips.c47
-rw-r--r--arch/mips/mm/tlbex-fault.S7
-rw-r--r--arch/mips/mm/tlbex.c5
8 files changed, 32 insertions, 79 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 81d6a15c93d0..6f534b209971 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -37,7 +37,7 @@
#include <asm/cacheflush.h> /* for run_uncached() */
#include <asm/traps.h>
#include <asm/dma-coherence.h>
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
/*
* Bits describing what cache ops an SMP callback function may perform.
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 899e46279902..44ac64d51827 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -20,6 +20,7 @@
#include <asm/processor.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
+#include <asm/setup.h>
/* Cache operations. */
void (*flush_cache_all)(void);
@@ -44,7 +45,6 @@ void (*__flush_cache_vunmap)(void);
void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
-void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size);
/* MIPS specific cache operations */
void (*flush_cache_sigtramp)(unsigned long addr);
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 8e78251eccc2..c01bd20d0208 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -127,23 +127,6 @@ static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
return gfp | dma_flag;
}
-static void *mips_dma_alloc_noncoherent(struct device *dev, size_t size,
- dma_addr_t * dma_handle, gfp_t gfp)
-{
- void *ret;
-
- gfp = massage_gfp_flags(dev, gfp);
-
- ret = (void *) __get_free_pages(gfp, get_order(size));
-
- if (ret != NULL) {
- memset(ret, 0, size);
- *dma_handle = plat_map_dma_mem(dev, ret, size);
- }
-
- return ret;
-}
-
static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
{
@@ -151,13 +134,6 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
struct page *page = NULL;
unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
- /*
- * XXX: seems like the coherent and non-coherent implementations could
- * be consolidated.
- */
- if (attrs & DMA_ATTR_NON_CONSISTENT)
- return mips_dma_alloc_noncoherent(dev, size, dma_handle, gfp);
-
gfp = massage_gfp_flags(dev, gfp);
if (IS_ENABLED(CONFIG_DMA_CMA) && gfpflags_allow_blocking(gfp))
@@ -172,7 +148,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
ret = page_address(page);
memset(ret, 0, size);
*dma_handle = plat_map_dma_mem(dev, ret, size);
- if (!plat_device_is_coherent(dev)) {
+ if (!(attrs & DMA_ATTR_NON_CONSISTENT) &&
+ !plat_device_is_coherent(dev)) {
dma_cache_wback_inv((unsigned long) ret, size);
ret = UNCAC_ADDR(ret);
}
@@ -180,14 +157,6 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
return ret;
}
-
-static void mips_dma_free_noncoherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle)
-{
- plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
- free_pages((unsigned long) vaddr, get_order(size));
-}
-
static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle, unsigned long attrs)
{
@@ -195,14 +164,9 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
struct page *page = NULL;
- if (attrs & DMA_ATTR_NON_CONSISTENT) {
- mips_dma_free_noncoherent(dev, size, vaddr, dma_handle);
- return;
- }
-
plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
- if (!plat_device_is_coherent(dev))
+ if (!(attrs & DMA_ATTR_NON_CONSISTENT) && !plat_device_is_coherent(dev))
addr = CAC_ADDR(addr);
page = virt_to_page((void *) addr);
@@ -409,12 +373,12 @@ static void mips_dma_sync_sg_for_device(struct device *dev,
}
}
-int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+static int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
return 0;
}
-int mips_dma_supported(struct device *dev, u64 mask)
+static int mips_dma_supported(struct device *dev, u64 mask)
{
return plat_dma_supported(dev, mask);
}
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 8ce2983a7015..5f6ea7d746de 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -31,6 +31,7 @@
#include <linux/gfp.h>
#include <linux/kcore.h>
#include <linux/export.h>
+#include <linux/initrd.h>
#include <asm/asm-offsets.h>
#include <asm/bootinfo.h>
diff --git a/arch/mips/mm/mmap.c b/arch/mips/mm/mmap.c
index 28adeabe851f..33d3251ecd37 100644
--- a/arch/mips/mm/mmap.c
+++ b/arch/mips/mm/mmap.c
@@ -7,6 +7,7 @@
* written by Ralf Baechle <ralf@linux-mips.org>
*/
#include <linux/compiler.h>
+#include <linux/elf-randomize.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/mman.h>
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index c909c3342729..acfb89273dad 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -14,7 +14,7 @@
#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/r4kcache.h>
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
/*
* MIPS32/MIPS64 L2 cache handling
@@ -63,34 +63,25 @@ static void mips_sc_prefetch_enable(void)
* prefetching for both code & data, for all ports.
*/
pftctl = read_gcr_l2_pft_control();
- if (pftctl & CM_GCR_L2_PFT_CONTROL_NPFT_MSK) {
- pftctl &= ~CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK;
- pftctl |= PAGE_MASK & CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK;
- pftctl |= CM_GCR_L2_PFT_CONTROL_PFTEN_MSK;
+ if (pftctl & CM_GCR_L2_PFT_CONTROL_NPFT) {
+ pftctl &= ~CM_GCR_L2_PFT_CONTROL_PAGEMASK;
+ pftctl |= PAGE_MASK & CM_GCR_L2_PFT_CONTROL_PAGEMASK;
+ pftctl |= CM_GCR_L2_PFT_CONTROL_PFTEN;
write_gcr_l2_pft_control(pftctl);
- pftctl = read_gcr_l2_pft_control_b();
- pftctl |= CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK;
- pftctl |= CM_GCR_L2_PFT_CONTROL_B_CEN_MSK;
- write_gcr_l2_pft_control_b(pftctl);
+ set_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
+ CM_GCR_L2_PFT_CONTROL_B_CEN);
}
}
static void mips_sc_prefetch_disable(void)
{
- unsigned long pftctl;
-
if (mips_cm_revision() < CM_REV_CM2_5)
return;
- pftctl = read_gcr_l2_pft_control();
- pftctl &= ~CM_GCR_L2_PFT_CONTROL_PFTEN_MSK;
- write_gcr_l2_pft_control(pftctl);
-
- pftctl = read_gcr_l2_pft_control_b();
- pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK;
- pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_CEN_MSK;
- write_gcr_l2_pft_control_b(pftctl);
+ clear_gcr_l2_pft_control(CM_GCR_L2_PFT_CONTROL_PFTEN);
+ clear_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
+ CM_GCR_L2_PFT_CONTROL_B_CEN);
}
static bool mips_sc_prefetch_is_enabled(void)
@@ -101,9 +92,9 @@ static bool mips_sc_prefetch_is_enabled(void)
return false;
pftctl = read_gcr_l2_pft_control();
- if (!(pftctl & CM_GCR_L2_PFT_CONTROL_NPFT_MSK))
+ if (!(pftctl & CM_GCR_L2_PFT_CONTROL_NPFT))
return false;
- return !!(pftctl & CM_GCR_L2_PFT_CONTROL_PFTEN_MSK);
+ return !!(pftctl & CM_GCR_L2_PFT_CONTROL_PFTEN);
}
static struct bcache_ops mips_sc_ops = {
@@ -160,21 +151,21 @@ static int __init mips_sc_probe_cm3(void)
unsigned long cfg = read_gcr_l2_config();
unsigned long sets, line_sz, assoc;
- if (cfg & CM_GCR_L2_CONFIG_BYPASS_MSK)
+ if (cfg & CM_GCR_L2_CONFIG_BYPASS)
return 0;
- sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK;
- sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF;
+ sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE;
+ sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE);
if (sets)
c->scache.sets = 64 << sets;
- line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
- line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
+ line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE;
+ line_sz >>= __ffs(CM_GCR_L2_CONFIG_LINE_SIZE);
if (line_sz)
c->scache.linesz = 2 << line_sz;
- assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
- assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
+ assoc = cfg & CM_GCR_L2_CONFIG_ASSOC;
+ assoc >>= __ffs(CM_GCR_L2_CONFIG_ASSOC);
c->scache.ways = assoc + 1;
c->scache.waysize = c->scache.sets * c->scache.linesz;
c->scache.waybit = __ffs(c->scache.waysize);
diff --git a/arch/mips/mm/tlbex-fault.S b/arch/mips/mm/tlbex-fault.S
index 318855eb5f80..77db401fc620 100644
--- a/arch/mips/mm/tlbex-fault.S
+++ b/arch/mips/mm/tlbex-fault.S
@@ -12,14 +12,15 @@
.macro tlb_do_page_fault, write
NESTED(tlb_do_page_fault_\write, PT_SIZE, sp)
- SAVE_ALL
+ .cfi_signal_frame
+ SAVE_ALL docfi=1
MFC0 a2, CP0_BADVADDR
KMODE
move a0, sp
REG_S a2, PT_BVADDR(sp)
li a1, \write
- PTR_LA ra, ret_from_exception
- j do_page_fault
+ jal do_page_fault
+ j ret_from_exception
END(tlb_do_page_fault_\write)
.endm
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 5aadc69c8ce3..79b9f2ad3ff5 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2634,11 +2634,6 @@ void build_tlb_refill_handler(void)
#endif
break;
- case CPU_R6000:
- case CPU_R6000A:
- panic("No R6000 TLB refill handler yet");
- break;
-
case CPU_R8000:
panic("No R8000 TLB refill handler yet");
break;
generated by cgit (git 2.34.1) at 2024-05-22 06:31:43 +0000