diff options
Diffstat (limited to 'arch/mips')
136 files changed, 4811 insertions, 15466 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 584081df89c2..2c57994b5217 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -19,7 +19,6 @@ platform-$(CONFIG_MACH_LOONGSON32) += loongson32/ platform-$(CONFIG_MACH_LOONGSON64) += loongson64/ platform-$(CONFIG_MIPS_MALTA) += mti-malta/ platform-$(CONFIG_MACH_NINTENDO64) += n64/ -platform-$(CONFIG_NLM_COMMON) += netlogic/ platform-$(CONFIG_PIC32MZDA) += pic32/ platform-$(CONFIG_RALINK) += ralink/ platform-$(CONFIG_MIKROTIK_RB532) += rb532/ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 771ca53af06d..86510741d49d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -47,7 +47,6 @@ config MIPS select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT - select HANDLE_DOMAIN_IRQ select HAVE_ARCH_COMPILER_H select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT @@ -57,7 +56,6 @@ config MIPS select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES select HAVE_ASM_MODVERSIONS - select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS select HAVE_CONTEXT_TRACKING select HAVE_TIF_NOHZ select HAVE_C_RECORDMCOUNT @@ -65,7 +63,10 @@ config MIPS select HAVE_DEBUG_STACKOVERFLOW select HAVE_DMA_CONTIGUOUS select HAVE_DYNAMIC_FTRACE - select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2 + select HAVE_EBPF_JIT if !CPU_MICROMIPS && \ + !CPU_DADDI_WORKAROUNDS && \ + !CPU_R4000_WORKAROUNDS && \ + !CPU_R4400_WORKAROUNDS select HAVE_EXIT_THREAD select HAVE_FAST_GUP select HAVE_FTRACE_MCOUNT_RECORD @@ -994,60 +995,6 @@ config CAVIUM_OCTEON_SOC Hikari Say Y here for most Octeon reference boards. -config NLM_XLR_BOARD - bool "Netlogic XLR/XLS based systems" - select BOOT_ELF32 - select NLM_COMMON - select SYS_HAS_CPU_XLR - select SYS_SUPPORTS_SMP - select HAVE_PCI - select SWAP_IO_SPACE - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select PHYS_ADDR_T_64BIT - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select NR_CPUS_DEFAULT_32 - select CEVT_R4K - select CSRC_R4K - select IRQ_MIPS_CPU - select ZONE_DMA32 if 64BIT - select SYNC_R4K - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_ZBOOT - select SYS_SUPPORTS_ZBOOT_UART16550 - help - Support for systems based on Netlogic XLR and XLS processors. - Say Y here if you have a XLR or XLS based board. - -config NLM_XLP_BOARD - bool "Netlogic XLP based systems" - select BOOT_ELF32 - select NLM_COMMON - select SYS_HAS_CPU_XLP - select SYS_SUPPORTS_SMP - select HAVE_PCI - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select PHYS_ADDR_T_64BIT - select GPIOLIB - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select NR_CPUS_DEFAULT_32 - select CEVT_R4K - select CSRC_R4K - select IRQ_MIPS_CPU - select ZONE_DMA32 if 64BIT - select SYNC_R4K - select SYS_HAS_EARLY_PRINTK - select USE_OF - select SYS_SUPPORTS_ZBOOT - select SYS_SUPPORTS_ZBOOT_UART16550 - help - This board is based on Netlogic XLP Processor. - Say Y here if you have a XLP based board. - endchoice source "arch/mips/alchemy/Kconfig" @@ -1070,7 +1017,6 @@ source "arch/mips/cavium-octeon/Kconfig" source "arch/mips/loongson2ef/Kconfig" source "arch/mips/loongson32/Kconfig" source "arch/mips/loongson64/Kconfig" -source "arch/mips/netlogic/Kconfig" endmenu @@ -1212,15 +1158,6 @@ config SYS_SUPPORTS_RELOCATABLE The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF to allow access to command line and entropy sources. -config MIPS_CBPF_JIT - def_bool y - depends on BPF_JIT && HAVE_CBPF_JIT - -config MIPS_EBPF_JIT - def_bool y - depends on BPF_JIT && HAVE_EBPF_JIT - - # # Endianness selection. Sufficiently obscure so many users don't know what to # answer,so we try hard to limit the available choices. Also the use of a @@ -1379,6 +1316,7 @@ config CPU_LOONGSON64 select MIPS_ASID_BITS_VARIABLE select MIPS_PGD_C0_CONTEXT select MIPS_L1_CACHE_SHIFT_6 + select MIPS_FP_SUPPORT select GPIOLIB select SWIOTLB select HAVE_KVM @@ -1782,35 +1720,10 @@ config CPU_BMIPS select CPU_HAS_PREFETCH select CPU_SUPPORTS_CPUFREQ select MIPS_EXTERNAL_TIMER + select GENERIC_IRQ_MIGRATION if HOTPLUG_CPU help Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors. -config CPU_XLR - bool "Netlogic XLR SoC" - depends on SYS_HAS_CPU_XLR - select CPU_SUPPORTS_32BIT_KERNEL - select CPU_SUPPORTS_64BIT_KERNEL - select CPU_SUPPORTS_HIGHMEM - select CPU_SUPPORTS_HUGEPAGES - select WEAK_ORDERING - select WEAK_REORDERING_BEYOND_LLSC - help - Netlogic Microsystems XLR/XLS processors. - -config CPU_XLP - bool "Netlogic XLP SoC" - depends on SYS_HAS_CPU_XLP - select CPU_SUPPORTS_32BIT_KERNEL - select CPU_SUPPORTS_64BIT_KERNEL - select CPU_SUPPORTS_HIGHMEM - select WEAK_ORDERING - select WEAK_REORDERING_BEYOND_LLSC - select CPU_HAS_PREFETCH - select CPU_MIPSR2 - select CPU_SUPPORTS_HUGEPAGES - select MIPS_ASID_BITS_VARIABLE - help - Netlogic Microsystems XLP processors. endchoice config CPU_MIPS32_3_5_FEATURES @@ -2057,12 +1970,6 @@ config SYS_HAS_CPU_BMIPS5000 select SYS_HAS_CPU_BMIPS select ARCH_HAS_SYNC_DMA_FOR_CPU -config SYS_HAS_CPU_XLR - bool - -config SYS_HAS_CPU_XLP - bool - # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC @@ -2157,7 +2064,7 @@ config CPU_SUPPORTS_HUGEPAGES config MIPS_PGD_C0_CONTEXT bool depends on 64BIT - default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP + default y if (CPU_MIPSR2 || CPU_MIPSR6) # # Set to y for ptrace access to watch registers. @@ -2840,7 +2747,7 @@ config NODES_SHIFT config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON64) + depends on PERF_EVENTS && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_LOONGSON64) default y help Enable hardware performance counter support for perf events. If @@ -3316,8 +3223,6 @@ source "drivers/cpuidle/Kconfig" endmenu -source "drivers/firmware/Kconfig" - source "arch/mips/kvm/Kconfig" source "arch/mips/vdso/Kconfig" diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c index 752b93d91ac9..fd91d9c9a252 100644 --- a/arch/mips/alchemy/devboards/db1550.c +++ b/arch/mips/alchemy/devboards/db1550.c @@ -66,6 +66,7 @@ int __init db1550_board_setup(void) case BCSR_WHOAMI_PB1550_DDR: bcsr_init(PB1550_BCSR_PHYS_ADDR, PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); + break; case BCSR_WHOAMI_DB1550: break; default: diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c index c18d7f72d9d9..96d28f211121 100644 --- a/arch/mips/boot/compressed/uart-16550.c +++ b/arch/mips/boot/compressed/uart-16550.c @@ -23,18 +23,6 @@ #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset)) #endif -#ifdef CONFIG_CPU_XLR -#define UART0_BASE 0x1EF14000 -#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) -#define IOTYPE unsigned int -#endif - -#ifdef CONFIG_CPU_XLP -#define UART0_BASE 0x18030100 -#define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) -#define IOTYPE unsigned int -#endif - #ifndef IOTYPE #define IOTYPE char #endif diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index be96d35eb582..928f38a79dff 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -9,7 +9,6 @@ subdir-$(CONFIG_MACH_LOONGSON64) += loongson subdir-$(CONFIG_SOC_VCOREIII) += mscc subdir-$(CONFIG_MIPS_MALTA) += mti subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti -subdir-$(CONFIG_NLM_XLP_BOARD) += netlogic subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni subdir-$(CONFIG_MACH_PIC32) += pic32 subdir-$(CONFIG_ATH79) += qca diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index a688809beebc..b249a4f0f6b6 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -113,9 +113,12 @@ * Use the 32.768 kHz oscillator as the parent of the RTC for a higher * precision. */ - assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>; - assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>; - assigned-clock-rates = <48000000>; + assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>, + <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>; + assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>, + <&cgu JZ4780_CLK_MPLL>, + <&cgu JZ4780_CLK_SSIPLL>; + assigned-clock-rates = <48000000>, <0>, <54000000>; }; &tcu { diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index 9e34f433b9b5..28adc3d93975 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -255,22 +255,23 @@ }; }; - spi_gpio { - compatible = "spi-gpio"; + spi0: spi@10043000 { + compatible = "ingenic,jz4780-spi"; + reg = <0x10043000 0x1c>; #address-cells = <1>; #size-cells = <0>; - num-chipselects = <2>; - gpio-miso = <&gpe 14 0>; - gpio-sck = <&gpe 15 0>; - gpio-mosi = <&gpe 17 0>; - cs-gpios = <&gpe 16 0>, <&gpe 18 0>; + interrupt-parent = <&intc>; + interrupts = <8>; - spidev@0 { - compatible = "spidev"; - reg = <0>; - spi-max-frequency = <1000000>; - }; + clocks = <&cgu JZ4780_CLK_SSI0>; + clock-names = "spi"; + + dmas = <&dma JZ4780_DMA_SSI0_RX 0xffffffff>, + <&dma JZ4780_DMA_SSI0_TX 0xffffffff>; + dma-names = "rx", "tx"; + + status = "disabled"; }; uart0: serial@10030000 { @@ -338,6 +339,25 @@ status = "disabled"; }; + spi1: spi@10044000 { + compatible = "ingenic,jz4780-spi"; + reg = <0x10044000 0x1c>; + #address-cells = <1>; + #size-sells = <0>; + + interrupt-parent = <&intc>; + interrupts = <7>; + + clocks = <&cgu JZ4780_CLK_SSI1>; + clock-names = "spi"; + + dmas = <&dma JZ4780_DMA_SSI1_RX 0xffffffff>, + <&dma JZ4780_DMA_SSI1_TX 0xffffffff>; + dma-names = "rx", "tx"; + + status = "disabled"; + }; + i2c0: i2c@10050000 { compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c"; #address-cells = <1>; diff --git a/arch/mips/boot/dts/netlogic/Makefile b/arch/mips/boot/dts/netlogic/Makefile deleted file mode 100644 index 45af4224494f..000000000000 --- a/arch/mips/boot/dts/netlogic/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_DT_XLP_EVP) += xlp_evp.dtb -dtb-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb -dtb-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb -dtb-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb -dtb-$(CONFIG_DT_XLP_RVP) += xlp_rvp.dtb - -obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/netlogic/xlp_evp.dts b/arch/mips/boot/dts/netlogic/xlp_evp.dts deleted file mode 100644 index e63e55926e04..000000000000 --- a/arch/mips/boot/dts/netlogic/xlp_evp.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * XLP8XX Device Tree Source for EVP boards - */ - -/dts-v1/; -/ { - model = "netlogic,XLP-EVP"; - compatible = "netlogic,xlp"; - #address-cells = <2>; - #size-cells = <2>; - - soc { - #address-cells = <2>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x02000000>; // GBU chipselects - - serial0: serial@30000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x30100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - serial1: serial@31000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x31100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <18>; - }; - i2c0: ocores@32000 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x32100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <30>; - }; - i2c1: ocores@33000 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x33100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <31>; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; - - dtt@4c { - compatible = "national,lm90"; - reg = <0x4c>; - }; - }; - pic: pic@4000 { - compatible = "netlogic,xlp-pic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0 0x4000 0x200>; - interrupt-controller; - }; - - nor_flash@1,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - reg = <1 0 0x1000000>; - - partition@0 { - label = "x-loader"; - reg = <0x0 0x100000>; /* 1M */ - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x100000 0x100000>; /* 1M */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; /* 5M */ - }; - - partition@700000 { - label = "rootfs"; - reg = <0x700000 0x800000>; /* 8M */ - }; - - partition@f00000 { - label = "env"; - reg = <0xf00000 0x100000>; /* 1M */ - read-only; - }; - }; - - gpio: xlp_gpio@34100 { - compatible = "netlogic,xlp832-gpio"; - reg = <0 0x34100 0x1000>; - #gpio-cells = <2>; - gpio-controller; - - #interrupt-cells = <2>; - interrupt-parent = <&pic>; - interrupts = <39>; - interrupt-controller; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; - }; -}; diff --git a/arch/mips/boot/dts/netlogic/xlp_fvp.dts b/arch/mips/boot/dts/netlogic/xlp_fvp.dts deleted file mode 100644 index d05abf13fb7d..000000000000 --- a/arch/mips/boot/dts/netlogic/xlp_fvp.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * XLP2XX Device Tree Source for FVP boards - */ - -/dts-v1/; -/ { - model = "netlogic,XLP-FVP"; - compatible = "netlogic,xlp"; - #address-cells = <2>; - #size-cells = <2>; - - soc { - #address-cells = <2>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x02000000>; // GBU chipselects - - serial0: serial@30000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x30100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - serial1: serial@31000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x31100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <18>; - }; - i2c0: ocores@37100 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x37100 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <30>; - }; - i2c1: ocores@37120 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x37120 0x20>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <31>; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; - - dtt@4c { - compatible = "national,lm90"; - reg = <0x4c>; - }; - }; - pic: pic@4000 { - compatible = "netlogic,xlp-pic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0 0x4000 0x200>; - interrupt-controller; - }; - - nor_flash@1,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - reg = <1 0 0x1000000>; - - partition@0 { - label = "x-loader"; - reg = <0x0 0x100000>; /* 1M */ - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x100000 0x100000>; /* 1M */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; /* 5M */ - }; - - partition@700000 { - label = "rootfs"; - reg = <0x700000 0x800000>; /* 8M */ - }; - - partition@f00000 { - label = "env"; - reg = <0xf00000 0x100000>; /* 1M */ - read-only; - }; - }; - - gpio: xlp_gpio@34100 { - compatible = "netlogic,xlp208-gpio"; - reg = <0 0x34100 0x1000>; - #gpio-cells = <2>; - gpio-controller; - - #interrupt-cells = <2>; - interrupt-parent = <&pic>; - interrupts = <39>; - interrupt-controller; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; - }; -}; diff --git a/arch/mips/boot/dts/netlogic/xlp_gvp.dts b/arch/mips/boot/dts/netlogic/xlp_gvp.dts deleted file mode 100644 index d47de4851786..000000000000 --- a/arch/mips/boot/dts/netlogic/xlp_gvp.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * XLP9XX Device Tree Source for GVP boards - */ - -/dts-v1/; -/ { - model = "netlogic,XLP-GVP"; - compatible = "netlogic,xlp"; - #address-cells = <2>; - #size-cells = <2>; - - soc { - #address-cells = <2>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x02000000>; // GBU chipselects - - serial0: serial@30000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x112100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <125000000>; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - pic: pic@110000 { - compatible = "netlogic,xlp-pic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0 0x110000 0x200>; - interrupt-controller; - }; - - nor_flash@1,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - reg = <1 0 0x1000000>; - - partition@0 { - label = "x-loader"; - reg = <0x0 0x100000>; /* 1M */ - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x100000 0x100000>; /* 1M */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; /* 5M */ - }; - - partition@700000 { - label = "rootfs"; - reg = <0x700000 0x800000>; /* 8M */ - }; - - partition@f00000 { - label = "env"; - reg = <0xf00000 0x100000>; /* 1M */ - read-only; - }; - }; - - gpio: xlp_gpio@114100 { - compatible = "netlogic,xlp980-gpio"; - reg = <0 0x114100 0x1000>; - #gpio-cells = <2>; - gpio-controller; - - #interrupt-cells = <2>; - interrupt-parent = <&pic>; - interrupts = <39>; - interrupt-controller; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; - }; -}; diff --git a/arch/mips/boot/dts/netlogic/xlp_rvp.dts b/arch/mips/boot/dts/netlogic/xlp_rvp.dts deleted file mode 100644 index aa0faee194ec..000000000000 --- a/arch/mips/boot/dts/netlogic/xlp_rvp.dts +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * XLP5XX Device Tree Source for RVP boards - */ - -/dts-v1/; -/ { - model = "netlogic,XLP-RVP"; - compatible = "netlogic,xlp"; - #address-cells = <2>; - #size-cells = <2>; - - soc { - #address-cells = <2>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x02000000>; // GBU chipselects - - serial0: serial@30000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x112100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <125000000>; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - pic: pic@110000 { - compatible = "netlogic,xlp-pic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0 0x110000 0x200>; - interrupt-controller; - }; - - nor_flash@1,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - reg = <1 0 0x1000000>; - - partition@0 { - label = "x-loader"; - reg = <0x0 0x100000>; /* 1M */ - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x100000 0x100000>; /* 1M */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; /* 5M */ - }; - - partition@700000 { - label = "rootfs"; - reg = <0x700000 0x800000>; /* 8M */ - }; - - partition@f00000 { - label = "env"; - reg = <0xf00000 0x100000>; /* 1M */ - read-only; - }; - }; - - gpio: xlp_gpio@114100 { - compatible = "netlogic,xlp532-gpio"; - reg = <0 0x114100 0x1000>; - #gpio-cells = <2>; - gpio-controller; - - #interrupt-cells = <2>; - interrupt-parent = <&pic>; - interrupts = <39>; - interrupt-controller; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; - }; -}; diff --git a/arch/mips/boot/dts/netlogic/xlp_svp.dts b/arch/mips/boot/dts/netlogic/xlp_svp.dts deleted file mode 100644 index 3bb0b2e08e4a..000000000000 --- a/arch/mips/boot/dts/netlogic/xlp_svp.dts +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * XLP3XX Device Tree Source for SVP boards - */ - -/dts-v1/; -/ { - model = "netlogic,XLP-SVP"; - compatible = "netlogic,xlp"; - #address-cells = <2>; - #size-cells = <2>; - - soc { - #address-cells = <2>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG - 1 0 0 0x16000000 0x02000000>; // GBU chipselects - - serial0: serial@30000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x30100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - serial1: serial@31000 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0 0x31100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <133333333>; - interrupt-parent = <&pic>; - interrupts = <18>; - }; - i2c0: ocores@32000 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x32100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <30>; - }; - i2c1: ocores@33000 { - compatible = "opencores,i2c-ocores"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x33100 0xa00>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <32000000>; - interrupt-parent = <&pic>; - interrupts = <31>; - - rtc@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; - - dtt@4c { - compatible = "national,lm90"; - reg = <0x4c>; - }; - }; - pic: pic@4000 { - compatible = "netlogic,xlp-pic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0 0x4000 0x200>; - interrupt-controller; - }; - - nor_flash@1,0 { - compatible = "cfi-flash"; - #address-cells = <1>; - #size-cells = <1>; - bank-width = <2>; - reg = <1 0 0x1000000>; - - partition@0 { - label = "x-loader"; - reg = <0x0 0x100000>; /* 1M */ - read-only; - }; - - partition@100000 { - label = "u-boot"; - reg = <0x100000 0x100000>; /* 1M */ - }; - - partition@200000 { - label = "kernel"; - reg = <0x200000 0x500000>; /* 5M */ - }; - - partition@700000 { - label = "rootfs"; - reg = <0x700000 0x800000>; /* 8M */ - }; - - partition@f00000 { - label = "env"; - reg = <0xf00000 0x100000>; /* 1M */ - read-only; - }; - }; - - gpio: xlp_gpio@34100 { - compatible = "netlogic,xlp316-gpio"; - reg = <0 0x34100 0x1000>; - #gpio-cells = <2>; - gpio-controller; - - #interrupt-cells = <2>; - interrupt-parent = <&pic>; - interrupts = <39>; - interrupt-controller; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; - }; -}; diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c index 6044ff471002..b22f664e2d29 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -1056,16 +1056,6 @@ int cvmx_helper_initialize_packet_io_global(void) EXPORT_SYMBOL_GPL(cvmx_helper_initialize_packet_io_global); /** - * Does core local initialization for packet io - * - * Returns Zero on success, non-zero on failure - */ -int cvmx_helper_initialize_packet_io_local(void) -{ - return cvmx_pko_initialize_local(); -} - -/** * Return the link state of an IPD/PKO port as returned by * auto negotiation. The result of this function may not match * Octeon's link config if auto negotiation has changed since diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c index 7c4879e74318..ae8806e7bce2 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-pko.c +++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c @@ -230,20 +230,6 @@ void cvmx_pko_initialize_global(void) } /* - * This function does per-core initialization required by the PKO routines. - * This must be called on all cores that will do packet output, and must - * be called after the FPA has been initialized and filled with pages. - * - * Returns 0 on success - * !0 on failure - */ -int cvmx_pko_initialize_local(void) -{ - /* Nothing to do */ - return 0; -} - -/* * Enables the packet output hardware. It must already be * configured. */ diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index be5d4afcd30f..844f882096e6 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -2609,7 +2609,10 @@ static void octeon_irq_ciu3_ip2(void) else hw = intsn; - ret = handle_domain_irq(domain, hw, NULL); + irq_enter(); + ret = generic_handle_domain_irq(domain, hw); + irq_exit(); + if (ret < 0) { union cvmx_ciu3_iscx_w1c isc_w1c; u64 isc_w1c_addr = ciu3_addr + CIU3_ISC_W1C(intsn); diff --git a/arch/mips/configs/loongson3_defconfig b/arch/mips/configs/loongson3_defconfig index f02101ff04b3..25ecd15bc952 100644 --- a/arch/mips/configs/loongson3_defconfig +++ b/arch/mips/configs/loongson3_defconfig @@ -282,6 +282,7 @@ CONFIG_DRM=y CONFIG_DRM_RADEON=m CONFIG_DRM_QXL=y CONFIG_DRM_VIRTIO_GPU=y +CONFIG_FB=y CONFIG_FB_RADEON=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=m diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig deleted file mode 100644 index 32c290611723..000000000000 --- a/arch/mips/configs/nlm_xlp_defconfig +++ /dev/null @@ -1,557 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_CGROUPS=y -CONFIG_NAMESPACES=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -CONFIG_EMBEDDED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_NLM_XLP_BOARD=y -CONFIG_64BIT=y -CONFIG_PAGE_SIZE_16KB=y -# CONFIG_HW_PERF_EVENTS is not set -CONFIG_SMP=y -# CONFIG_SECCOMP is not set -CONFIG_PCI=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_STUB=y -CONFIG_MIPS32_O32=y -CONFIG_MIPS32_N32=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_ACORN_PARTITION=y -CONFIG_ACORN_PARTITION_ICS=y -CONFIG_ACORN_PARTITION_RISCIX=y -CONFIG_OSF_PARTITION=y -CONFIG_AMIGA_PARTITION=y -CONFIG_ATARI_PARTITION=y -CONFIG_MAC_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_SGI_PARTITION=y -CONFIG_ULTRIX_PARTITION=y -CONFIG_SUN_PARTITION=y -CONFIG_KARMA_PARTITION=y -CONFIG_SYSV68_PARTITION=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_BINFMT_MISC=y -CONFIG_KSM=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=m -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_NET_IPIP=m -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_MD5SIG=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OSF=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_SECURITY=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_SECURITY=m -CONFIG_DECNET_NF_GRABULATOR=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_IP6=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_IP_DCCP=m -CONFIG_RDS=m -CONFIG_RDS_TCP=m -CONFIG_TIPC=m -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_DECNET=m -CONFIG_LLC2=m -CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=m -CONFIG_IPDDP=m -CONFIG_IPDDP_ENCAP=y -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_PHONET=m -CONFIG_IEEE802154=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_IPT=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_DCB=y -CONFIG_NET_PKTGEN=m -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_STANDALONE is not set -CONFIG_CONNECTOR=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_LE_BYTE_SWAP=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_OF=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_CDROM_PKTCDVD=y -CONFIG_RAID_ATTRS=m -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_SAS_LIBSAS=m -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_ISCSI_TCP=m -CONFIG_SCSI_DEBUG=m -CONFIG_SCSI_DH=y -CONFIG_SCSI_DH_RDAC=m -CONFIG_SCSI_DH_HP_SW=m -CONFIG_SCSI_DH_EMC=m -CONFIG_SCSI_DH_ALUA=m -CONFIG_SCSI_OSD_INITIATOR=m -CONFIG_SCSI_OSD_ULD=m -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_SIL24=y -# CONFIG_ATA_SFF is not set -CONFIG_NETDEVICES=y -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_ADAPTEC is not set -# CONFIG_NET_VENDOR_ALTEON is not set -# CONFIG_NET_VENDOR_AMD is not set -# CONFIG_NET_VENDOR_ATHEROS is not set -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_BROCADE is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_DEC is not set -# CONFIG_NET_VENDOR_DLINK is not set -# CONFIG_NET_VENDOR_EMULEX is not set -# CONFIG_NET_VENDOR_HP is not set -# CONFIG_NET_VENDOR_I825XX is not set -CONFIG_E1000E=y -CONFIG_SKY2=y -# CONFIG_NET_VENDOR_MELLANOX is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MYRI is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_NVIDIA is not set -# CONFIG_NET_VENDOR_OKI is not set -# CONFIG_NET_VENDOR_QLOGIC is not set -# CONFIG_NET_VENDOR_RDC is not set -# CONFIG_NET_VENDOR_REALTEK is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SILAN is not set -# CONFIG_NET_VENDOR_SIS is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_NET_VENDOR_SUN is not set -# CONFIG_NET_VENDOR_TEHUTI is not set -# CONFIG_NET_VENDOR_TI is not set -# CONFIG_NET_VENDOR_TOSHIBA is not set -# CONFIG_NET_VENDOR_VIA is not set -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIO_SERPORT=m -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=m -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_LEGACY_PTY_COUNT=0 -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_N_HDLC=m -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=48 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_TIMERIOMEM=m -CONFIG_RAW_DRIVER=m -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OCORES=y -CONFIG_SENSORS_LM90=y -CONFIG_THERMAL=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1374=y -CONFIG_UIO=y -CONFIG_UIO_PDRV_GENIRQ=m -# CONFIG_IOMMU_SUPPORT is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_GFS2_FS=m -CONFIG_BTRFS_FS=m -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_NILFS2_FS=m -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=y -CONFIG_CUSE=m -CONFIG_FSCACHE=m -CONFIG_FSCACHE_STATS=y -CONFIG_FSCACHE_HISTOGRAM=y -CONFIG_CACHEFILES=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_NTFS_FS=m -CONFIG_PROC_KCORE=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_ADFS_FS=m -CONFIG_AFFS_FS=m -CONFIG_ECRYPT_FS=y -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=m -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -CONFIG_EXOFS_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=m -CONFIG_NFS_FSCACHE=y -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y -CONFIG_CIFS_UPCALL=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_DFS_UPCALL=y -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="cp437" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_SECURITY=y -CONFIG_LSM_MMAP_MIN_ADDR=0 -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SELINUX_BOOTPARAM=y -CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 -CONFIG_SECURITY_SELINUX_DISABLE=y -CONFIG_SECURITY_SMACK=y -CONFIG_SECURITY_TOMOYO=y -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_VMAC=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_LZO=m -CONFIG_CRC7=m -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_FRAME_WARN=1024 -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_KGDB=y diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig deleted file mode 100644 index bf9b9244929e..000000000000 --- a/arch/mips/configs/nlm_xlr_defconfig +++ /dev/null @@ -1,508 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_NAMESPACES=y -CONFIG_SCHED_AUTOGROUP=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -CONFIG_KALLSYMS_ALL=y -# CONFIG_PERF_EVENTS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_NLM_XLR_BOARD=y -CONFIG_HIGHMEM=y -CONFIG_SMP=y -CONFIG_KEXEC=y -CONFIG_PCI=y -CONFIG_PCI_MSI=y -CONFIG_PCI_DEBUG=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_ACORN_PARTITION=y -CONFIG_ACORN_PARTITION_ICS=y -CONFIG_ACORN_PARTITION_RISCIX=y -CONFIG_OSF_PARTITION=y -CONFIG_AMIGA_PARTITION=y -CONFIG_ATARI_PARTITION=y -CONFIG_MAC_PARTITION=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_SGI_PARTITION=y -CONFIG_ULTRIX_PARTITION=y -CONFIG_SUN_PARTITION=y -CONFIG_KARMA_PARTITION=y -CONFIG_SYSV68_PARTITION=y -CONFIG_BINFMT_MISC=m -CONFIG_KSM=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=m -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_NET_IPIP=m -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_MD5SIG=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OSF=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_SECURITY=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_SECURITY=m -CONFIG_DECNET_NF_GRABULATOR=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_IP6=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_IP_DCCP=m -CONFIG_RDS=m -CONFIG_RDS_TCP=m -CONFIG_TIPC=m -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_DECNET=m -CONFIG_LLC2=m -CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=m -CONFIG_IPDDP=m -CONFIG_IPDDP_ENCAP=y -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_PHONET=m -CONFIG_IEEE802154=m -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_IPT=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_DCB=y -CONFIG_NET_PKTGEN=m -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_STANDALONE is not set -CONFIG_CONNECTOR=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_CDROM_PKTCDVD=y -CONFIG_RAID_ATTRS=m -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_SAS_LIBSAS=m -CONFIG_SCSI_SRP_ATTRS=m -CONFIG_ISCSI_TCP=m -CONFIG_SCSI_DEBUG=m -CONFIG_SCSI_DH=y -CONFIG_SCSI_DH_RDAC=m -CONFIG_SCSI_DH_HP_SW=m -CONFIG_SCSI_DH_EMC=m -CONFIG_SCSI_DH_ALUA=m -CONFIG_SCSI_OSD_INITIATOR=m -CONFIG_SCSI_OSD_ULD=m -CONFIG_NETDEVICES=y -CONFIG_E1000E=y -CONFIG_SKY2=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIO_SERPORT=m -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_RAW=m -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_LEGACY_PTY_COUNT=0 -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_N_HDLC=m -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=48 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_TIMERIOMEM=m -CONFIG_RAW_DRIVER=m -CONFIG_I2C=y -CONFIG_I2C_XLR=y -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1374=y -CONFIG_UIO=y -CONFIG_UIO_PDRV_GENIRQ=m -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_GFS2_FS=m -CONFIG_OCFS2_FS=m -CONFIG_BTRFS_FS=m -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_NILFS2_FS=m -CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V1=m -CONFIG_QFMT_V2=m -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=y -CONFIG_CUSE=m -CONFIG_FSCACHE=m -CONFIG_FSCACHE_STATS=y -CONFIG_FSCACHE_HISTOGRAM=y -CONFIG_CACHEFILES=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_NTFS_FS=m -CONFIG_PROC_KCORE=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CONFIGFS_FS=y -CONFIG_ADFS_FS=m -CONFIG_AFFS_FS=m -CONFIG_ECRYPT_FS=y -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=m -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_ROMFS_FS=m -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -CONFIG_EXOFS_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=m -CONFIG_NFS_FSCACHE=y -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_CIFS=m -CONFIG_CIFS_WEAK_PW_HASH=y -CONFIG_CIFS_UPCALL=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_DFS_UPCALL=y -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="cp437" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_SECURITY=y -CONFIG_LSM_MMAP_MIN_ADDR=0 -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SELINUX_BOOTPARAM=y -CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 -CONFIG_SECURITY_SELINUX_DISABLE=y -CONFIG_SECURITY_SMACK=y -CONFIG_SECURITY_TOMOYO=y -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_VMAC=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_LZO=m -CONFIG_CRC7=m -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_KGDB=y diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h index b3dc9c589442..f207388541d5 100644 --- a/arch/mips/include/asm/cacheflush.h +++ b/arch/mips/include/asm/cacheflush.h @@ -61,6 +61,8 @@ static inline void flush_dcache_page(struct page *page) SetPageDcacheDirty(page); } +void flush_dcache_folio(struct folio *folio); + #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index 0b983800f48b..66a8b293fd80 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -249,6 +249,7 @@ static inline unsigned long __cmpxchg64(volatile void *ptr, /* Load 64 bits from ptr */ " " __SYNC(full, loongson3_war) " \n" "1: lld %L0, %3 # __cmpxchg64 \n" + " .set pop \n" /* * Split the 64 bit value we loaded into the 2 registers that hold the * ret variable. @@ -276,12 +277,14 @@ static inline unsigned long __cmpxchg64(volatile void *ptr, " or %L1, %L1, $at \n" " .set at \n" # endif + " .set push \n" + " .set " MIPS_ISA_ARCH_LEVEL " \n" /* Attempt to store new at ptr */ " scd %L1, %2 \n" /* If we failed, loop! */ "\t" __SC_BEQZ "%L1, 1b \n" - " .set pop \n" "2: " __SYNC(full, loongson3_war) " \n" + " .set pop \n" : "=&r"(ret), "=&r"(tmp), "=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr) diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h index 6b7396a6a115..01b05be23a5d 100644 --- a/arch/mips/include/asm/cop2.h +++ b/arch/mips/include/asm/cop2.h @@ -22,17 +22,6 @@ extern void octeon_cop2_restore(struct octeon_cop2_state *); #define cop2_present 1 #define cop2_lazy_restore 1 -#elif defined(CONFIG_CPU_XLP) - -extern void nlm_cop2_save(struct nlm_cop2_state *); -extern void nlm_cop2_restore(struct nlm_cop2_state *); - -#define cop2_save(r) nlm_cop2_save(&(r)->thread.cp2) -#define cop2_restore(r) nlm_cop2_restore(&(r)->thread.cp2) - -#define cop2_present 1 -#define cop2_lazy_restore 0 - #elif defined(CONFIG_CPU_LOONGSON64) #define cop2_present 1 diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h index 2be5d7b5de68..5efe8c8b854e 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -195,14 +195,6 @@ static inline int __pure __get_cpu_type(const int cpu_type) #ifdef CONFIG_SYS_HAS_CPU_BMIPS5000 case CPU_BMIPS5000: #endif - -#ifdef CONFIG_SYS_HAS_CPU_XLP - case CPU_XLP: -#endif - -#ifdef CONFIG_SYS_HAS_CPU_XLR - case CPU_XLR: -#endif break; default: unreachable(); diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index d45a52f65b7a..5c2f8d9cb7cf 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -328,7 +328,7 @@ enum cpu_type_enum { */ CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF, CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, - CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500, + CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_I6500, CPU_QEMU_GENERIC, diff --git a/arch/mips/include/asm/ginvt.h b/arch/mips/include/asm/ginvt.h index 6eb7c2b94dc7..87b2974ffc53 100644 --- a/arch/mips/include/asm/ginvt.h +++ b/arch/mips/include/asm/ginvt.h @@ -12,11 +12,13 @@ enum ginvt_type { #ifdef TOOLCHAIN_SUPPORTS_GINV # define _ASM_SET_GINV ".set ginv\n" +# define _ASM_UNSET_GINV #else -_ASM_MACRO_1R1I(ginvt, rs, type, - _ASM_INSN_IF_MIPS(0x7c0000bd | (__rs << 21) | (\\type << 8)) - _ASM_INSN32_IF_MM(0x0000717c | (__rs << 16) | (\\type << 9))); -# define _ASM_SET_GINV +# define _ASM_SET_GINV \ + _ASM_MACRO_1R1I(ginvt, rs, type, \ + _ASM_INSN_IF_MIPS(0x7c0000bd | (__rs << 21) | (\\type << 8)) \ + _ASM_INSN32_IF_MM(0x0000717c | (__rs << 16) | (\\type << 9))) +# define _ASM_UNSET_GINV ".purgem ginvt\n" #endif static __always_inline void ginvt(unsigned long addr, enum ginvt_type type) @@ -25,6 +27,7 @@ static __always_inline void ginvt(unsigned long addr, enum ginvt_type type) ".set push\n" _ASM_SET_GINV " ginvt %0, %1\n" + _ASM_UNSET_GINV ".set pop" : /* no outputs */ : "r"(addr), "i"(type) diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index f855478d12fa..cb16be93b048 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -160,7 +160,7 @@ do { \ #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \ - defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR) + defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h index 8218a1356bd8..31ca9151b539 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h @@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma_channel *ch); extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch); extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch); extern void ltq_dma_free(struct ltq_dma_channel *ch); -extern void ltq_dma_init_port(int p); +extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst); #endif diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h index 165993514762..b5be7511f6cd 100644 --- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h +++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h @@ -21,8 +21,10 @@ static inline u32 read_cpucfg(u32 reg) u32 __res; __asm__ __volatile__( + _ASM_SET_PARSE_R "parse_r __res,%0\n\t" "parse_r reg,%1\n\t" + _ASM_UNSET_PARSE_R ".insn \n\t" ".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t" :"=r"(__res) @@ -143,8 +145,10 @@ static inline u32 csr_readl(u32 reg) /* RDCSR reg, val */ __asm__ __volatile__( + _ASM_SET_PARSE_R "parse_r __res,%0\n\t" "parse_r reg,%1\n\t" + _ASM_UNSET_PARSE_R ".insn \n\t" ".word (0xc8000118 | (reg << 21) | (__res << 11))\n\t" :"=r"(__res) @@ -160,8 +164,10 @@ static inline u64 csr_readq(u32 reg) /* DRDCSR reg, val */ __asm__ __volatile__( + _ASM_SET_PARSE_R "parse_r __res,%0\n\t" "parse_r reg,%1\n\t" + _ASM_UNSET_PARSE_R ".insn \n\t" ".word (0xc8020118 | (reg << 21) | (__res << 11))\n\t" :"=r"(__res) @@ -175,8 +181,10 @@ static inline void csr_writel(u32 val, u32 reg) { /* WRCSR reg, val */ __asm__ __volatile__( + _ASM_SET_PARSE_R "parse_r reg,%0\n\t" "parse_r val,%1\n\t" + _ASM_UNSET_PARSE_R ".insn \n\t" ".word (0xc8010118 | (reg << 21) | (val << 11))\n\t" : @@ -189,8 +197,10 @@ static inline void csr_writeq(u64 val, u32 reg) { /* DWRCSR reg, val */ __asm__ __volatile__( + _ASM_SET_PARSE_R "parse_r reg,%0\n\t" "parse_r val,%1\n\t" + _ASM_UNSET_PARSE_R ".insn \n\t" ".word (0xc8030118 | (reg << 21) | (val << 11))\n\t" : @@ -243,8 +253,10 @@ static inline u64 drdtime(void) u64 val = 0; __asm__ __volatile__( + _ASM_SET_PARSE_R "parse_r rID,%0\n\t" "parse_r val,%1\n\t" + _ASM_UNSET_PARSE_R ".insn \n\t" ".word (0xc8090118 | (rID << 21) | (val << 11))\n\t" :"=r"(rID),"=r"(val) diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h deleted file mode 100644 index 0c29ff820bb9..000000000000 --- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2011 Netlogic Microsystems - * Copyright (C) 2003 Ralf Baechle - */ -#ifndef __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H - -#define cpu_has_4kex 1 -#define cpu_has_4k_cache 1 -#define cpu_has_watch 1 -#define cpu_has_mips16 0 -#define cpu_has_mips16e2 0 -#define cpu_has_counter 1 -#define cpu_has_divec 1 -#define cpu_has_vce 0 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_prefetch 1 -#define cpu_has_mcheck 1 -#define cpu_has_ejtag 1 - -#define cpu_has_llsc 1 -#define cpu_has_vtag_icache 0 -#define cpu_has_ic_fills_f_dc 1 -#define cpu_has_dsp 0 -#define cpu_has_dsp2 0 -#define cpu_has_mipsmt 0 -#define cpu_icache_snoops_remote_store 1 - -#define cpu_has_64bits 1 - -#define cpu_has_mips32r1 1 -#define cpu_has_mips64r1 1 - -#define cpu_has_inclusive_pcaches 0 - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 - -#if defined(CONFIG_CPU_XLR) -#define cpu_has_userlocal 0 -#define cpu_has_dc_aliases 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips64r2 0 -#elif defined(CONFIG_CPU_XLP) -#define cpu_has_userlocal 1 -#define cpu_has_mips32r2 1 -#define cpu_has_mips64r2 1 -#else -#error "Unknown Netlogic CPU" -#endif - -#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-netlogic/irq.h b/arch/mips/include/asm/mach-netlogic/irq.h deleted file mode 100644 index c0dbd530cca6..000000000000 --- a/arch/mips/include/asm/mach-netlogic/irq.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2011 Netlogic Microsystems. - */ -#ifndef __ASM_NETLOGIC_IRQ_H -#define __ASM_NETLOGIC_IRQ_H - -#include <asm/mach-netlogic/multi-node.h> -#define NLM_IRQS_PER_NODE 1024 -#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES) - -#define MIPS_CPU_IRQ_BASE 0 - -#endif /* __ASM_NETLOGIC_IRQ_H */ diff --git a/arch/mips/include/asm/mach-netlogic/multi-node.h b/arch/mips/include/asm/mach-netlogic/multi-node.h deleted file mode 100644 index 8bdf47e29145..000000000000 --- a/arch/mips/include/asm/mach-netlogic/multi-node.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _NETLOGIC_MULTI_NODE_H_ -#define _NETLOGIC_MULTI_NODE_H_ - -#ifndef CONFIG_NLM_MULTINODE -#define NLM_NR_NODES 1 -#else -#if defined(CONFIG_NLM_MULTINODE_2) -#define NLM_NR_NODES 2 -#elif defined(CONFIG_NLM_MULTINODE_4) -#define NLM_NR_NODES 4 -#else -#define NLM_NR_NODES 1 -#endif -#endif - -#define NLM_THREADS_PER_CORE 4 - -struct nlm_soc_info { - unsigned long coremask; /* cores enabled on the soc */ - unsigned long ebase; /* not used now */ - uint64_t irqmask; /* EIMR for the node */ - uint64_t sysbase; /* only for XLP - sys block base */ - uint64_t picbase; /* PIC block base */ - spinlock_t piclock; /* lock for PIC access */ - cpumask_t cpumask; /* logical cpu mask for node */ - unsigned int socbus; -}; - -extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; -#define nlm_get_node(i) (&nlm_nodes[i]) -#define nlm_node_present(n) ((n) >= 0 && (n) < NLM_NR_NODES && \ - nlm_get_node(n)->coremask != 0) -#ifdef CONFIG_CPU_XLR -#define nlm_current_node() (&nlm_nodes[0]) -#else -#define nlm_current_node() (&nlm_nodes[nlm_nodeid()]) -#endif -void nlm_node_init(int node); - -#endif diff --git a/arch/mips/include/asm/mach-ralink/spaces.h b/arch/mips/include/asm/mach-ralink/spaces.h index 87d085c9ad61..05d14c21c417 100644 --- a/arch/mips/include/asm/mach-ralink/spaces.h +++ b/arch/mips/include/asm/mach-ralink/spaces.h @@ -2,8 +2,8 @@ #ifndef __ASM_MACH_RALINK_SPACES_H_ #define __ASM_MACH_RALINK_SPACES_H_ -#define PCI_IOBASE _AC(0xa0000000, UL) -#define PCI_IOSIZE SZ_16M +#define PCI_IOBASE mips_io_port_base +#define PCI_IOSIZE SZ_64K #define IO_SPACE_LIMIT (PCI_IOSIZE - 1) #include <asm/mach-generic/spaces.h> diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index aeae2effa123..23c67c0871b1 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -11,6 +11,7 @@ #ifndef __MIPS_ASM_MIPS_CM_H__ #define __MIPS_ASM_MIPS_CM_H__ +#include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/errno.h> @@ -153,8 +154,8 @@ GCR_ACCESSOR_RO(32, 0x030, rev) #define CM_GCR_REV_MINOR GENMASK(7, 0) #define CM_ENCODE_REV(major, minor) \ - (((major) << __ffs(CM_GCR_REV_MAJOR)) | \ - ((minor) << __ffs(CM_GCR_REV_MINOR))) + (FIELD_PREP(CM_GCR_REV_MAJOR, major) | \ + FIELD_PREP(CM_GCR_REV_MINOR, minor)) #define CM_REV_CM2 CM_ENCODE_REV(6, 0) #define CM_REV_CM2_5 CM_ENCODE_REV(7, 0) @@ -362,10 +363,10 @@ static inline int mips_cm_revision(void) static inline unsigned int mips_cm_max_vp_width(void) { extern int smp_num_siblings; - uint32_t cfg; if (mips_cm_revision() >= CM_REV_CM3) - return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW; + return FIELD_GET(CM_GCR_SYS_CONFIG2_MAXVPW, + read_gcr_sys_config2()); if (mips_cm_present()) { /* @@ -373,8 +374,7 @@ static inline unsigned int mips_cm_max_vp_width(void) * number of VP(E)s, and if that ever changes then this will * need revisiting. */ - cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE; - return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1; + return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, read_gcr_cl_config()) + 1; } if (IS_ENABLED(CONFIG_SMP)) diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h index 35fb8ee6dd33..fd43d876892e 100644 --- a/arch/mips/include/asm/mips-cps.h +++ b/arch/mips/include/asm/mips-cps.h @@ -10,8 +10,6 @@ #include <linux/io.h> #include <linux/types.h> -#include <asm/mips-boards/launch.h> - extern unsigned long __cps_access_bad_size(void) __compiletime_error("Bad size for CPS accessor"); @@ -167,30 +165,11 @@ static inline uint64_t mips_cps_cluster_config(unsigned int cluster) */ static inline unsigned int mips_cps_numcores(unsigned int cluster) { - unsigned int ncores; - if (!mips_cm_present()) return 0; /* Add one before masking to handle 0xff indicating no cores */ - ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; - - if (IS_ENABLED(CONFIG_SOC_MT7621)) { - struct cpulaunch *launch; - - /* - * Ralink MT7621S SoC is single core, but the GCR_CONFIG method - * always reports 2 cores. Check the second core's LAUNCH_FREADY - * flag to detect if the second core is missing. This method - * only works before the core has been started. - */ - launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); - launch += 2; /* MT7621 has 2 VPEs per core */ - if (!(launch->flags & LAUNCH_FREADY)) - ncores = 1; - } - - return ncores; + return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; } /** diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index acdf8c69220b..2616353b940c 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1297,22 +1297,22 @@ static inline int mm_insn_16bit(u16 insn) "\\var = " #n "\n\t" \ ".endif\n\t" -__asm__(".macro parse_r var r\n\t" - "\\var = -1\n\t" - _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) - _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) - _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) - _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) - _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) - _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) - _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) - _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) - ".iflt \\var\n\t" - ".error \"Unable to parse register name \\r\"\n\t" - ".endif\n\t" - ".endm"); - -#undef _IFC_REG +#define _ASM_SET_PARSE_R \ + ".macro parse_r var r\n\t" \ + "\\var = -1\n\t" \ + _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3) \ + _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7) \ + _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11) \ + _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15) \ + _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) \ + _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) \ + _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) \ + _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) \ + ".iflt \\var\n\t" \ + ".error \"Unable to parse register name \\r\"\n\t" \ + ".endif\n\t" \ + ".endm\n\t" +#define _ASM_UNSET_PARSE_R ".purgem parse_r\n\t" /* * C macros for generating assembler macros for common instruction formats. @@ -1322,43 +1322,45 @@ __asm__(".macro parse_r var r\n\t" * the ENC encodings. */ -/* Instructions with no operands */ -#define _ASM_MACRO_0(OP, ENC) \ - __asm__(".macro " #OP "\n\t" \ - ENC \ - ".endm") - /* Instructions with 1 register operand & 1 immediate operand */ #define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \ - __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \ + ".macro " #OP " " #R1 ", " #I2 "\n\t" \ + _ASM_SET_PARSE_R \ "parse_r __" #R1 ", \\" #R1 "\n\t" \ ENC \ - ".endm") + _ASM_UNSET_PARSE_R \ + ".endm\n\t" /* Instructions with 2 register operands */ #define _ASM_MACRO_2R(OP, R1, R2, ENC) \ - __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \ + ".macro " #OP " " #R1 ", " #R2 "\n\t" \ + _ASM_SET_PARSE_R \ "parse_r __" #R1 ", \\" #R1 "\n\t" \ "parse_r __" #R2 ", \\" #R2 "\n\t" \ ENC \ - ".endm") + _ASM_UNSET_PARSE_R \ + ".endm\n\t" /* Instructions with 3 register operands */ #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \ - __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \ + ".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \ + _ASM_SET_PARSE_R \ "parse_r __" #R1 ", \\" #R1 "\n\t" \ "parse_r __" #R2 ", \\" #R2 "\n\t" \ "parse_r __" #R3 ", \\" #R3 "\n\t" \ ENC \ - ".endm") + _ASM_UNSET_PARSE_R \ + ".endm\n\t" /* Instructions with 2 register operands and 1 optional select operand */ #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \ - __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \ + ".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \ + _ASM_SET_PARSE_R \ "parse_r __" #R1 ", \\" #R1 "\n\t" \ "parse_r __" #R2 ", \\" #R2 "\n\t" \ ENC \ - ".endm") + _ASM_UNSET_PARSE_R \ + ".endm\n\t" /* * TLB Invalidate Flush @@ -1618,15 +1620,21 @@ do { \ } while (0) #ifndef TOOLCHAIN_SUPPORTS_XPA -_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel, - _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel) - _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11)); -_ASM_MACRO_2R_1S(mthc0, rt, rd, sel, - _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel) - _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11)); -#define _ASM_SET_XPA "" +#define _ASM_SET_MFHC0 \ + _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel, \ + _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11)) +#define _ASM_UNSET_MFHC0 ".purgem mfhc0\n\t" +#define _ASM_SET_MTHC0 \ + _ASM_MACRO_2R_1S(mthc0, rt, rd, sel, \ + _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11)) +#define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t" #else /* !TOOLCHAIN_SUPPORTS_XPA */ -#define _ASM_SET_XPA ".set\txpa\n\t" +#define _ASM_SET_MFHC0 ".set\txpa\n\t" +#define _ASM_SET_MTHC0 ".set\txpa\n\t" +#define _ASM_UNSET_MFHC0 +#define _ASM_UNSET_MTHC0 #endif #define __readx_32bit_c0_register(source, sel) \ @@ -1636,8 +1644,9 @@ _ASM_MACRO_2R_1S(mthc0, rt, rd, sel, __asm__ __volatile__( \ " .set push \n" \ " .set mips32r2 \n" \ - _ASM_SET_XPA \ + _ASM_SET_MFHC0 \ " mfhc0 %0, " #source ", %1 \n" \ + _ASM_UNSET_MFHC0 \ " .set pop \n" \ : "=r" (__res) \ : "i" (sel)); \ @@ -1649,8 +1658,9 @@ do { \ __asm__ __volatile__( \ " .set push \n" \ " .set mips32r2 \n" \ - _ASM_SET_XPA \ + _ASM_SET_MTHC0 \ " mthc0 %z0, " #register ", %1 \n" \ + _ASM_UNSET_MTHC0 \ " .set pop \n" \ : \ : "Jr" (value), "i" (sel)); \ @@ -2046,31 +2056,58 @@ do { \ */ #ifndef TOOLCHAIN_SUPPORTS_VIRT -_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel, - _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) - _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11)); -_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel, - _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel) - _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11)); -_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel, - _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel) - _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11)); -_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel, - _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel) - _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11)); -_ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010) - _ASM_INSN32_IF_MM(0x0000017c)); -_ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009) - _ASM_INSN32_IF_MM(0x0000117c)); -_ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a) - _ASM_INSN32_IF_MM(0x0000217c)); -_ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e) - _ASM_INSN32_IF_MM(0x0000317c)); -_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c) - _ASM_INSN32_IF_MM(0x0000517c)); -#define _ASM_SET_VIRT "" +#define _ASM_SET_MFGC0 \ + _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel, \ + _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11)) +#define _ASM_UNSET_MFGC0 ".purgem mfgc0\n\t" +#define _ASM_SET_DMFGC0 \ + _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel, \ + _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11)) +#define _ASM_UNSET_DMFGC0 ".purgem dmfgc0\n\t" +#define _ASM_SET_MTGC0 \ + _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel, \ + _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11)) +#define _ASM_UNSET_MTGC0 ".purgem mtgc0\n\t" +#define _ASM_SET_DMTGC0 \ + _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel, \ + _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11)) +#define _ASM_UNSET_DMTGC0 ".purgem dmtgc0\n\t" + +#define __tlbgp() \ + _ASM_INSN_IF_MIPS(0x42000010) \ + _ASM_INSN32_IF_MM(0x0000017c) +#define __tlbgr() \ + _ASM_INSN_IF_MIPS(0x42000009) \ + _ASM_INSN32_IF_MM(0x0000117c) +#define __tlbgwi() \ + _ASM_INSN_IF_MIPS(0x4200000a) \ + _ASM_INSN32_IF_MM(0x0000217c) +#define __tlbgwr() \ + _ASM_INSN_IF_MIPS(0x4200000e) \ + _ASM_INSN32_IF_MM(0x0000317c) +#define __tlbginvf() \ + _ASM_INSN_IF_MIPS(0x4200000c) \ + _ASM_INSN32_IF_MM(0x0000517c) #else /* !TOOLCHAIN_SUPPORTS_VIRT */ #define _ASM_SET_VIRT ".set\tvirt\n\t" +#define _ASM_SET_MFGC0 _ASM_SET_VIRT +#define _ASM_SET_DMFGC0 _ASM_SET_VIRT +#define _ASM_SET_MTGC0 _ASM_SET_VIRT +#define _ASM_SET_DMTGC0 _ASM_SET_VIRT +#define _ASM_UNSET_MFGC0 +#define _ASM_UNSET_DMFGC0 +#define _ASM_UNSET_MTGC0 +#define _ASM_UNSET_DMTGC0 + +#define __tlbgp() _ASM_SET_VIRT "tlbgp\n\t" +#define __tlbgr() _ASM_SET_VIRT "tlbgr\n\t" +#define __tlbgwi() _ASM_SET_VIRT "tlbgwi\n\t" +#define __tlbgwr() _ASM_SET_VIRT "tlbgwr\n\t" +#define __tlbginvf() _ASM_SET_VIRT "tlbginvf\n\t" #endif #define __read_32bit_gc0_register(source, sel) \ @@ -2078,8 +2115,9 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c) __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\tmips32r5\n\t" \ - _ASM_SET_VIRT \ + _ASM_SET_MFGC0 \ "mfgc0\t%0, " #source ", %1\n\t" \ + _ASM_UNSET_MFGC0 \ ".set\tpop" \ : "=r" (__res) \ : "i" (sel)); \ @@ -2091,8 +2129,9 @@ _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c) __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\tmips64r5\n\t" \ - _ASM_SET_VIRT \ + _ASM_SET_DMFGC0 \ "dmfgc0\t%0, " #source ", %1\n\t" \ + _ASM_UNSET_DMFGC0 \ ".set\tpop" \ : "=r" (__res) \ : "i" (sel)); \ @@ -2104,8 +2143,9 @@ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\tmips32r5\n\t" \ - _ASM_SET_VIRT \ + _ASM_SET_MTGC0 \ "mtgc0\t%z0, " #register ", %1\n\t" \ + _ASM_UNSET_MTGC0 \ ".set\tpop" \ : : "Jr" ((unsigned int)(value)), \ "i" (sel)); \ @@ -2116,8 +2156,9 @@ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\tmips64r5\n\t" \ - _ASM_SET_VIRT \ + _ASM_SET_DMTGC0 \ "dmtgc0\t%z0, " #register ", %1\n\t" \ + _ASM_UNSET_DMTGC0 \ ".set\tpop" \ : : "Jr" (value), \ "i" (sel)); \ @@ -2788,8 +2829,7 @@ static inline void guest_tlb_probe(void) __asm__ __volatile__( ".set push\n\t" ".set noreorder\n\t" - _ASM_SET_VIRT - "tlbgp\n\t" + __tlbgp() ".set pop"); } @@ -2798,8 +2838,7 @@ static inline void guest_tlb_read(void) __asm__ __volatile__( ".set push\n\t" ".set noreorder\n\t" - _ASM_SET_VIRT - "tlbgr\n\t" + __tlbgr() ".set pop"); } @@ -2808,8 +2847,7 @@ static inline void guest_tlb_write_indexed(void) __asm__ __volatile__( ".set push\n\t" ".set noreorder\n\t" - _ASM_SET_VIRT - "tlbgwi\n\t" + __tlbgwi() ".set pop"); } @@ -2818,8 +2856,7 @@ static inline void guest_tlb_write_random(void) __asm__ __volatile__( ".set push\n\t" ".set noreorder\n\t" - _ASM_SET_VIRT - "tlbgwr\n\t" + __tlbgwr() ".set pop"); } @@ -2831,8 +2868,7 @@ static inline void guest_tlbinvf(void) __asm__ __volatile__( ".set push\n\t" ".set noreorder\n\t" - _ASM_SET_VIRT - "tlbginvf\n\t" + __tlbginvf() ".set pop"); } diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h index e0a3dd52334d..236a49ee2e3e 100644 --- a/arch/mips/include/asm/msa.h +++ b/arch/mips/include/asm/msa.h @@ -162,16 +162,26 @@ static inline void init_msa_upper(void) * to allow compilation with toolchains that do not support MSA. Once all * toolchains in use support MSA these can be removed. */ -_ASM_MACRO_2R(cfcmsa, rd, cs, - _ASM_INSN_IF_MIPS(0x787e0019 | __cs << 11 | __rd << 6) - _ASM_INSN32_IF_MM(0x587e0016 | __cs << 11 | __rd << 6)); -_ASM_MACRO_2R(ctcmsa, cd, rs, - _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6) - _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6)); -#define _ASM_SET_MSA "" + +#define _ASM_SET_CFCMSA \ + _ASM_MACRO_2R(cfcmsa, rd, cs, \ + _ASM_INSN_IF_MIPS(0x787e0019 | __cs << 11 | __rd << 6) \ + _ASM_INSN32_IF_MM(0x587e0016 | __cs << 11 | __rd << 6)) +#define _ASM_UNSET_CFCMSA ".purgem cfcmsa\n\t" +#define _ASM_SET_CTCMSA \ + _ASM_MACRO_2R(ctcmsa, cd, rs, \ + _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6) \ + _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6)) +#define _ASM_UNSET_CTCMSA ".purgem ctcmsa\n\t" #else /* TOOLCHAIN_SUPPORTS_MSA */ -#define _ASM_SET_MSA ".set\tfp=64\n\t" \ - ".set\tmsa\n\t" +#define _ASM_SET_CFCMSA \ + ".set\tfp=64\n\t" \ + ".set\tmsa\n\t" +#define _ASM_UNSET_CFCMSA +#define _ASM_SET_CTCMSA \ + ".set\tfp=64\n\t" \ + ".set\tmsa\n\t" +#define _ASM_UNSET_CTCMSA #endif #define __BUILD_MSA_CTL_REG(name, cs) \ @@ -180,8 +190,9 @@ static inline unsigned int read_msa_##name(void) \ unsigned int reg; \ __asm__ __volatile__( \ " .set push\n" \ - _ASM_SET_MSA \ + _ASM_SET_CFCMSA \ " cfcmsa %0, $" #cs "\n" \ + _ASM_UNSET_CFCMSA \ " .set pop\n" \ : "=r"(reg)); \ return reg; \ @@ -191,8 +202,9 @@ static inline void write_msa_##name(unsigned int val) \ { \ __asm__ __volatile__( \ " .set push\n" \ - _ASM_SET_MSA \ + _ASM_SET_CTCMSA \ " ctcmsa $" #cs ", %0\n" \ + _ASM_UNSET_CTCMSA \ " .set pop\n" \ : : "r"(val)); \ } diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h deleted file mode 100644 index 57616649b4f3..000000000000 --- a/arch/mips/include/asm/netlogic/common.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _NETLOGIC_COMMON_H_ -#define _NETLOGIC_COMMON_H_ - -/* - * Common SMP definitions - */ -#define RESET_VEC_PHYS 0x1fc00000 -#define RESET_VEC_SIZE 8192 /* 8KB reset code and data */ -#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) - -/* Offsets of parameters in the RESET_DATA_PHYS area */ -#define BOOT_THREAD_MODE 0 -#define BOOT_NMI_LOCK 4 -#define BOOT_NMI_HANDLER 8 - -/* CPU ready flags for each CPU */ -#define BOOT_CPU_READY 2048 - -#ifndef __ASSEMBLY__ -#include <linux/cpumask.h> -#include <linux/spinlock.h> -#include <asm/irq.h> -#include <asm/mach-netlogic/multi-node.h> - -struct irq_desc; -void nlm_smp_function_ipi_handler(struct irq_desc *desc); -void nlm_smp_resched_ipi_handler(struct irq_desc *desc); -void nlm_smp_irq_init(int hwcpuid); -void nlm_boot_secondary_cpus(void); -int nlm_wakeup_secondary_cpus(void); -void nlm_rmiboot_preboot(void); -void nlm_percpu_init(int hwcpuid); - -static inline void * -nlm_get_boot_data(int offset) -{ - return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset); -} - -static inline void -nlm_set_nmi_handler(void *handler) -{ - void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER); - - *(int64_t *)nmih = (long)handler; -} - -/* - * Misc. - */ -void nlm_init_boot_cpu(void); -unsigned int nlm_get_cpu_frequency(void); -extern const struct plat_smp_ops nlm_smp_ops; -extern char nlm_reset_entry[], nlm_reset_entry_end[]; - -extern unsigned int nlm_threads_per_core; -extern cpumask_t nlm_cpumask; - -struct irq_data; -uint64_t nlm_pci_irqmask(int node); -void nlm_setup_pic_irq(int node, int picirq, int irq, int irt); -void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *)); - -#ifdef CONFIG_PCI_MSI -void nlm_dispatch_msi(int node, int lirq); -void nlm_dispatch_msix(int node, int msixirq); -#endif - -/* - * The NR_IRQs is divided between nodes, each of them has a separate irq space - */ -static inline int nlm_irq_to_xirq(int node, int irq) -{ - return node * NR_IRQS / NLM_NR_NODES + irq; -} - -#ifdef CONFIG_CPU_XLR -#define nlm_cores_per_node() 8 -#else -static inline int nlm_cores_per_node(void) -{ - return ((read_c0_prid() & PRID_IMP_MASK) - == PRID_IMP_NETLOGIC_XLP9XX) ? 32 : 8; -} -#endif -static inline int nlm_threads_per_node(void) -{ - return nlm_cores_per_node() * NLM_THREADS_PER_CORE; -} - -static inline int nlm_hwtid_to_node(int hwtid) -{ - return hwtid / nlm_threads_per_node(); -} - -extern int nlm_cpu_ready[]; -#endif /* __ASSEMBLY__ */ -#endif /* _NETLOGIC_COMMON_H_ */ diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h deleted file mode 100644 index 79c7cccdc22c..000000000000 --- a/arch/mips/include/asm/netlogic/haldefs.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __NLM_HAL_HALDEFS_H__ -#define __NLM_HAL_HALDEFS_H__ - -#include <linux/irqflags.h> /* for local_irq_disable */ - -/* - * This file contains platform specific memory mapped IO implementation - * and will provide a way to read 32/64 bit memory mapped registers in - * all ABIs - */ -static inline uint32_t -nlm_read_reg(uint64_t base, uint32_t reg) -{ - volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; - - return *addr; -} - -static inline void -nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) -{ - volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; - - *addr = val; -} - -/* - * For o32 compilation, we have to disable interrupts to access 64 bit - * registers - * - * We need to disable interrupts because we save just the lower 32 bits of - * registers in interrupt handling. So if we get hit by an interrupt while - * using the upper 32 bits of a register, we lose. - */ - -static inline uint64_t -nlm_read_reg64(uint64_t base, uint32_t reg) -{ - uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); - volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; - uint64_t val; - - if (sizeof(unsigned long) == 4) { - unsigned long flags; - - local_irq_save(flags); - __asm__ __volatile__( - ".set push" "\n\t" - ".set mips64" "\n\t" - "ld %L0, %1" "\n\t" - "dsra32 %M0, %L0, 0" "\n\t" - "sll %L0, %L0, 0" "\n\t" - ".set pop" "\n" - : "=r" (val) - : "m" (*ptr)); - local_irq_restore(flags); - } else - val = *ptr; - - return val; -} - -static inline void -nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) -{ - uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); - volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; - - if (sizeof(unsigned long) == 4) { - unsigned long flags; - uint64_t tmp; - - local_irq_save(flags); - __asm__ __volatile__( - ".set push" "\n\t" - ".set mips64" "\n\t" - "dsll32 %L0, %L0, 0" "\n\t" - "dsrl32 %L0, %L0, 0" "\n\t" - "dsll32 %M0, %M0, 0" "\n\t" - "or %L0, %L0, %M0" "\n\t" - "sd %L0, %2" "\n\t" - ".set pop" "\n" - : "=r" (tmp) - : "0" (val), "m" (*ptr)); - local_irq_restore(flags); - } else - *ptr = val; -} - -/* - * Routines to store 32/64 bit values to 64 bit addresses, - * used when going thru XKPHYS to access registers - */ -static inline uint32_t -nlm_read_reg_xkphys(uint64_t base, uint32_t reg) -{ - return nlm_read_reg(base, reg); -} - -static inline void -nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) -{ - nlm_write_reg(base, reg, val); -} - -static inline uint64_t -nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) -{ - return nlm_read_reg64(base, reg); -} - -static inline void -nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) -{ - nlm_write_reg64(base, reg, val); -} - -/* Location where IO base is mapped */ -extern uint64_t nlm_io_base; - -#if defined(CONFIG_CPU_XLP) -static inline uint64_t -nlm_pcicfg_base(uint32_t devoffset) -{ - return nlm_io_base + devoffset; -} - -#elif defined(CONFIG_CPU_XLR) - -static inline uint64_t -nlm_mmio_base(uint32_t devoffset) -{ - return nlm_io_base + devoffset; -} -#endif - -#endif diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h deleted file mode 100644 index ed5993d9b7b8..000000000000 --- a/arch/mips/include/asm/netlogic/interrupt.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _ASM_NLM_INTERRUPT_H -#define _ASM_NLM_INTERRUPT_H - -/* Defines for the IRQ numbers */ - -#define IRQ_IPI_SMP_FUNCTION 3 -#define IRQ_IPI_SMP_RESCHEDULE 4 -#define IRQ_FMN 5 -#define IRQ_TIMER 7 - -#endif diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h deleted file mode 100644 index 788baf399e69..000000000000 --- a/arch/mips/include/asm/netlogic/mips-extns.h +++ /dev/null @@ -1,301 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _ASM_NLM_MIPS_EXTS_H -#define _ASM_NLM_MIPS_EXTS_H - -/* - * XLR and XLP interrupt request and interrupt mask registers - */ -/* - * NOTE: Do not save/restore flags around write_c0_eimr(). - * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS - * register. Restoring flags will overwrite the lower 8 bits of EIMR. - * - * Call with interrupts disabled. - */ -#define write_c0_eimr(val) \ -do { \ - if (sizeof(unsigned long) == 4) { \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, $9, 7\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - } else \ - __write_64bit_c0_register($9, 7, (val)); \ -} while (0) - -/* - * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with - * standard functions will be very inefficient. This provides - * optimized functions for the normal operations on the registers. - * - * Call with interrupts disabled. - */ -static inline void ack_c0_eirr(int irq) -{ - __asm__ __volatile__( - ".set push\n\t" - ".set mips64\n\t" - ".set noat\n\t" - "li $1, 1\n\t" - "dsllv $1, $1, %0\n\t" - "dmtc0 $1, $9, 6\n\t" - ".set pop" - : : "r" (irq)); -} - -static inline void set_c0_eimr(int irq) -{ - __asm__ __volatile__( - ".set push\n\t" - ".set mips64\n\t" - ".set noat\n\t" - "li $1, 1\n\t" - "dsllv %0, $1, %0\n\t" - "dmfc0 $1, $9, 7\n\t" - "or $1, %0\n\t" - "dmtc0 $1, $9, 7\n\t" - ".set pop" - : "+r" (irq)); -} - -static inline void clear_c0_eimr(int irq) -{ - __asm__ __volatile__( - ".set push\n\t" - ".set mips64\n\t" - ".set noat\n\t" - "li $1, 1\n\t" - "dsllv %0, $1, %0\n\t" - "dmfc0 $1, $9, 7\n\t" - "or $1, %0\n\t" - "xor $1, %0\n\t" - "dmtc0 $1, $9, 7\n\t" - ".set pop" - : "+r" (irq)); -} - -/* - * Read c0 eimr and c0 eirr, do AND of the two values, the result is - * the interrupts which are raised and are not masked. - */ -static inline uint64_t read_c0_eirr_and_eimr(void) -{ - uint64_t val; - -#ifdef CONFIG_64BIT - val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7); -#else - __asm__ __volatile__( - ".set push\n\t" - ".set mips64\n\t" - ".set noat\n\t" - "dmfc0 %M0, $9, 6\n\t" - "dmfc0 %L0, $9, 7\n\t" - "and %M0, %L0\n\t" - "dsll %L0, %M0, 32\n\t" - "dsra %M0, %M0, 32\n\t" - "dsra %L0, %L0, 32\n\t" - ".set pop" - : "=r" (val)); -#endif - return val; -} - -static inline int hard_smp_processor_id(void) -{ - return __read_32bit_c0_register($15, 1) & 0x3ff; -} - -static inline int nlm_nodeid(void) -{ - uint32_t prid = read_c0_prid() & PRID_IMP_MASK; - - if ((prid == PRID_IMP_NETLOGIC_XLP9XX) || - (prid == PRID_IMP_NETLOGIC_XLP5XX)) - return (__read_32bit_c0_register($15, 1) >> 7) & 0x7; - else - return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; -} - -static inline unsigned int nlm_core_id(void) -{ - uint32_t prid = read_c0_prid() & PRID_IMP_MASK; - - if ((prid == PRID_IMP_NETLOGIC_XLP9XX) || - (prid == PRID_IMP_NETLOGIC_XLP5XX)) - return (read_c0_ebase() & 0x7c) >> 2; - else - return (read_c0_ebase() & 0x1c) >> 2; -} - -static inline unsigned int nlm_thread_id(void) -{ - return read_c0_ebase() & 0x3; -} - -#define __read_64bit_c2_split(source, sel) \ -({ \ - unsigned long long __val; \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc2\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsra\t%M0, %M0, 32\n\t" \ - "dsra\t%L0, %L0, 32\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc2\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsra\t%M0, %M0, 32\n\t" \ - "dsra\t%L0, %L0, 32\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__val)); \ - local_irq_restore(__flags); \ - \ - __val; \ -}) - -#define __write_64bit_c2_split(source, sel, val) \ -do { \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc2\t%L0, " #source "\n\t" \ - ".set\tmips0\n\t" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc2\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : : "r" (val)); \ - local_irq_restore(__flags); \ -} while (0) - -#define __read_32bit_c2_register(source, sel) \ -({ uint32_t __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc2\t%0, " #source "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc2\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __read_64bit_c2_register(source, sel) \ -({ unsigned long long __res; \ - if (sizeof(unsigned long) == 4) \ - __res = __read_64bit_c2_split(source, sel); \ - else if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc2\t%0, " #source "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc2\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_64bit_c2_register(register, sel, value) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_64bit_c2_split(register, sel, value); \ - else if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc2\t%z0, " #register "\n\t" \ - ".set\tmips0\n\t" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc2\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : : "Jr" (value)); \ -} while (0) - -#define __write_32bit_c2_register(reg, sel, value) \ -({ \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc2\t%z0, " #reg "\n\t" \ - ".set\tmips0\n\t" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc2\t%z0, " #reg ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : : "Jr" (value)); \ -}) - -#endif /*_ASM_NLM_MIPS_EXTS_H */ diff --git a/arch/mips/include/asm/netlogic/psb-bootinfo.h b/arch/mips/include/asm/netlogic/psb-bootinfo.h deleted file mode 100644 index c716e9397113..000000000000 --- a/arch/mips/include/asm/netlogic/psb-bootinfo.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _ASM_NETLOGIC_BOOTINFO_H -#define _ASM_NETLOGIC_BOOTINFO_H - -struct psb_info { - uint64_t boot_level; - uint64_t io_base; - uint64_t output_device; - uint64_t uart_print; - uint64_t led_output; - uint64_t init; - uint64_t exit; - uint64_t warm_reset; - uint64_t wakeup; - uint64_t online_cpu_map; - uint64_t master_reentry_sp; - uint64_t master_reentry_gp; - uint64_t master_reentry_fn; - uint64_t slave_reentry_fn; - uint64_t magic_dword; - uint64_t uart_putchar; - uint64_t size; - uint64_t uart_getchar; - uint64_t nmi_handler; - uint64_t psb_version; - uint64_t mac_addr; - uint64_t cpu_frequency; - uint64_t board_version; - uint64_t malloc; - uint64_t free; - uint64_t global_shmem_addr; - uint64_t global_shmem_size; - uint64_t psb_os_cpu_map; - uint64_t userapp_cpu_map; - uint64_t wakeup_os; - uint64_t psb_mem_map; - uint64_t board_major_version; - uint64_t board_minor_version; - uint64_t board_manf_revision; - uint64_t board_serial_number; - uint64_t psb_physaddr_map; - uint64_t xlr_loaderip_config; - uint64_t bldr_envp; - uint64_t avail_mem_map; -}; - -/* This is what netlboot passes and linux boot_mem_map is subtly different */ -#define NLM_BOOT_MEM_MAP_MAX 32 -struct nlm_boot_mem_map { - int nr_map; - struct nlm_boot_mem_map_entry { - uint64_t addr; /* start of memory segment */ - uint64_t size; /* size of memory segment */ - uint32_t type; /* type of memory segment */ - } map[NLM_BOOT_MEM_MAP_MAX]; -}; -#define NLM_BOOT_MEM_RAM 1 - -/* Pointer to saved boot loader info */ -extern struct psb_info nlm_prom_info; - -#endif diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h deleted file mode 100644 index 3067f983495d..000000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __NLM_HAL_BRIDGE_H__ -#define __NLM_HAL_BRIDGE_H__ - -/** -* @file_name mio.h -* @author Netlogic Microsystems -* @brief Basic definitions of XLP memory and io subsystem -*/ - -/* - * BRIDGE specific registers - * - * These registers start after the PCIe header, which has 0x40 - * standard entries - */ -#define BRIDGE_MODE 0x00 -#define BRIDGE_PCI_CFG_BASE 0x01 -#define BRIDGE_PCI_CFG_LIMIT 0x02 -#define BRIDGE_PCIE_CFG_BASE 0x03 -#define BRIDGE_PCIE_CFG_LIMIT 0x04 -#define BRIDGE_BUSNUM_BAR0 0x05 -#define BRIDGE_BUSNUM_BAR1 0x06 -#define BRIDGE_BUSNUM_BAR2 0x07 -#define BRIDGE_BUSNUM_BAR3 0x08 -#define BRIDGE_BUSNUM_BAR4 0x09 -#define BRIDGE_BUSNUM_BAR5 0x0a -#define BRIDGE_BUSNUM_BAR6 0x0b -#define BRIDGE_FLASH_BAR0 0x0c -#define BRIDGE_FLASH_BAR1 0x0d -#define BRIDGE_FLASH_BAR2 0x0e -#define BRIDGE_FLASH_BAR3 0x0f -#define BRIDGE_FLASH_LIMIT0 0x10 -#define BRIDGE_FLASH_LIMIT1 0x11 -#define BRIDGE_FLASH_LIMIT2 0x12 -#define BRIDGE_FLASH_LIMIT3 0x13 - -#define BRIDGE_DRAM_BAR(i) (0x14 + (i)) -#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) -#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i)) -#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i)) - -#define BRIDGE_PCIEMEM_BASE0 0x34 -#define BRIDGE_PCIEMEM_BASE1 0x35 -#define BRIDGE_PCIEMEM_BASE2 0x36 -#define BRIDGE_PCIEMEM_BASE3 0x37 -#define BRIDGE_PCIEMEM_LIMIT0 0x38 -#define BRIDGE_PCIEMEM_LIMIT1 0x39 -#define BRIDGE_PCIEMEM_LIMIT2 0x3a -#define BRIDGE_PCIEMEM_LIMIT3 0x3b -#define BRIDGE_PCIEIO_BASE0 0x3c -#define BRIDGE_PCIEIO_BASE1 0x3d -#define BRIDGE_PCIEIO_BASE2 0x3e -#define BRIDGE_PCIEIO_BASE3 0x3f -#define BRIDGE_PCIEIO_LIMIT0 0x40 -#define BRIDGE_PCIEIO_LIMIT1 0x41 -#define BRIDGE_PCIEIO_LIMIT2 0x42 -#define BRIDGE_PCIEIO_LIMIT3 0x43 -#define BRIDGE_PCIEMEM_BASE4 0x44 -#define BRIDGE_PCIEMEM_BASE5 0x45 -#define BRIDGE_PCIEMEM_BASE6 0x46 -#define BRIDGE_PCIEMEM_LIMIT4 0x47 -#define BRIDGE_PCIEMEM_LIMIT5 0x48 -#define BRIDGE_PCIEMEM_LIMIT6 0x49 -#define BRIDGE_PCIEIO_BASE4 0x4a -#define BRIDGE_PCIEIO_BASE5 0x4b -#define BRIDGE_PCIEIO_BASE6 0x4c -#define BRIDGE_PCIEIO_LIMIT4 0x4d -#define BRIDGE_PCIEIO_LIMIT5 0x4e -#define BRIDGE_PCIEIO_LIMIT6 0x4f -#define BRIDGE_NBU_EVENT_CNT_CTL 0x50 -#define BRIDGE_EVNTCTR1_LOW 0x51 -#define BRIDGE_EVNTCTR1_HI 0x52 -#define BRIDGE_EVNT_CNT_CTL2 0x53 -#define BRIDGE_EVNTCTR2_LOW 0x54 -#define BRIDGE_EVNTCTR2_HI 0x55 -#define BRIDGE_TRACEBUF_MATCH0 0x56 -#define BRIDGE_TRACEBUF_MATCH1 0x57 -#define BRIDGE_TRACEBUF_MATCH_LOW 0x58 -#define BRIDGE_TRACEBUF_MATCH_HI 0x59 -#define BRIDGE_TRACEBUF_CTRL 0x5a -#define BRIDGE_TRACEBUF_INIT 0x5b -#define BRIDGE_TRACEBUF_ACCESS 0x5c -#define BRIDGE_TRACEBUF_READ_DATA0 0x5d -#define BRIDGE_TRACEBUF_READ_DATA1 0x5d -#define BRIDGE_TRACEBUF_READ_DATA2 0x5f -#define BRIDGE_TRACEBUF_READ_DATA3 0x60 -#define BRIDGE_TRACEBUF_STATUS 0x61 -#define BRIDGE_ADDRESS_ERROR0 0x62 -#define BRIDGE_ADDRESS_ERROR1 0x63 -#define BRIDGE_ADDRESS_ERROR2 0x64 -#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65 -#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66 -#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67 -#define BRIDGE_LINE_FLUSH0 0x68 -#define BRIDGE_LINE_FLUSH1 0x69 -#define BRIDGE_NODE_ID 0x6a -#define BRIDGE_ERROR_INTERRUPT_EN 0x6b -#define BRIDGE_PCIE0_WEIGHT 0x2c0 -#define BRIDGE_PCIE1_WEIGHT 0x2c1 -#define BRIDGE_PCIE2_WEIGHT 0x2c2 -#define BRIDGE_PCIE3_WEIGHT 0x2c3 -#define BRIDGE_USB_WEIGHT 0x2c4 -#define BRIDGE_NET_WEIGHT 0x2c5 -#define BRIDGE_POE_WEIGHT 0x2c6 -#define BRIDGE_CMS_WEIGHT 0x2c7 -#define BRIDGE_DMAENG_WEIGHT 0x2c8 -#define BRIDGE_SEC_WEIGHT 0x2c9 -#define BRIDGE_COMP_WEIGHT 0x2ca -#define BRIDGE_GIO_WEIGHT 0x2cb -#define BRIDGE_FLASH_WEIGHT 0x2cc - -/* FIXME verify */ -#define BRIDGE_9XX_FLASH_BAR(i) (0x11 + (i)) -#define BRIDGE_9XX_FLASH_BAR_LIMIT(i) (0x15 + (i)) - -#define BRIDGE_9XX_DRAM_BAR(i) (0x19 + (i)) -#define BRIDGE_9XX_DRAM_LIMIT(i) (0x29 + (i)) -#define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i)) -#define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i)) - -#define BRIDGE_9XX_ADDRESS_ERROR0 0x9d -#define BRIDGE_9XX_ADDRESS_ERROR1 0x9e -#define BRIDGE_9XX_ADDRESS_ERROR2 0x9f - -#define BRIDGE_9XX_PCIEMEM_BASE0 0x59 -#define BRIDGE_9XX_PCIEMEM_BASE1 0x5a -#define BRIDGE_9XX_PCIEMEM_BASE2 0x5b -#define BRIDGE_9XX_PCIEMEM_BASE3 0x5c -#define BRIDGE_9XX_PCIEMEM_LIMIT0 0x5d -#define BRIDGE_9XX_PCIEMEM_LIMIT1 0x5e -#define BRIDGE_9XX_PCIEMEM_LIMIT2 0x5f -#define BRIDGE_9XX_PCIEMEM_LIMIT3 0x60 -#define BRIDGE_9XX_PCIEIO_BASE0 0x61 -#define BRIDGE_9XX_PCIEIO_BASE1 0x62 -#define BRIDGE_9XX_PCIEIO_BASE2 0x63 -#define BRIDGE_9XX_PCIEIO_BASE3 0x64 -#define BRIDGE_9XX_PCIEIO_LIMIT0 0x65 -#define BRIDGE_9XX_PCIEIO_LIMIT1 0x66 -#define BRIDGE_9XX_PCIEIO_LIMIT2 0x67 -#define BRIDGE_9XX_PCIEIO_LIMIT3 0x68 - -#ifndef __ASSEMBLY__ - -#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_bridge_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ - XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node)) -#define nlm_get_bridge_regbase(node) \ - (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) - -#endif /* __ASSEMBLY__ */ -#endif /* __NLM_HAL_BRIDGE_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h deleted file mode 100644 index a06b59292153..000000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __NLM_HAL_CPUCONTROL_H__ -#define __NLM_HAL_CPUCONTROL_H__ - -#define CPU_BLOCKID_IFU 0 -#define CPU_BLOCKID_ICU 1 -#define CPU_BLOCKID_IEU 2 -#define CPU_BLOCKID_LSU 3 -#define CPU_BLOCKID_MMU 4 -#define CPU_BLOCKID_PRF 5 -#define CPU_BLOCKID_SCH 7 -#define CPU_BLOCKID_SCU 8 -#define CPU_BLOCKID_FPU 9 -#define CPU_BLOCKID_MAP 10 - -#define IFU_BRUB_RESERVE 0x007 - -#define ICU_DEFEATURE 0x100 - -#define LSU_DEFEATURE 0x304 -#define LSU_DEBUG_ADDR 0x305 -#define LSU_DEBUG_DATA0 0x306 -#define LSU_CERRLOG_REGID 0x309 -#define SCHED_DEFEATURE 0x700 - -/* Offsets of interest from the 'MAP' Block */ -#define MAP_THREADMODE 0x00 -#define MAP_EXT_EBASE_ENABLE 0x04 -#define MAP_CCDI_CONFIG 0x08 -#define MAP_THRD0_CCDI_STATUS 0x0c -#define MAP_THRD1_CCDI_STATUS 0x10 -#define MAP_THRD2_CCDI_STATUS 0x14 -#define MAP_THRD3_CCDI_STATUS 0x18 -#define MAP_THRD0_DEBUG_MODE 0x1c -#define MAP_THRD1_DEBUG_MODE 0x20 -#define MAP_THRD2_DEBUG_MODE 0x24 -#define MAP_THRD3_DEBUG_MODE 0x28 -#define MAP_MISC_STATE 0x60 -#define MAP_DEBUG_READ_CTL 0x64 -#define MAP_DEBUG_READ_REG0 0x68 -#define MAP_DEBUG_READ_REG1 0x6c - -#define MMU_SETUP 0x400 -#define MMU_LFSRSEED 0x401 -#define MMU_HPW_NUM_PAGE_LVL 0x410 -#define MMU_PGWKR_PGDBASE 0x411 -#define MMU_PGWKR_PGDSHFT 0x412 -#define MMU_PGWKR_PGDMASK 0x413 -#define MMU_PGWKR_PUDSHFT 0x414 -#define MMU_PGWKR_PUDMASK 0x415 -#define MMU_PGWKR_PMDSHFT 0x416 -#define MMU_PGWKR_PMDMASK 0x417 -#define MMU_PGWKR_PTESHFT 0x418 -#define MMU_PGWKR_PTEMASK 0x419 - -#endif /* __NLM_CPUCONTROL_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h deleted file mode 100644 index 805bfd21f33e..000000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __NLM_HAL_IOMAP_H__ -#define __NLM_HAL_IOMAP_H__ - -#define XLP_DEFAULT_IO_BASE 0x18000000 -#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE -#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000 - -#define NMI_BASE 0xbfc00000 -#define XLP_IO_CLK 133333333 - -#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */ -#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE) -#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE) -#define XLP_IO_SIZE (64 << 20) /* ECFG space size */ -#define XLP_IO_PCI_HDRSZ 0x100 -#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) -#define XLP_IO_PCI_OFFSET(b, d, f) (((b) << 20) | ((d) << 15) | ((f) << 12)) - -#define XLP_HDR_OFFSET(node, bus, dev, fn) \ - XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn) - -#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) -/* coherent inter chip */ -#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1) -#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2) -#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3) -#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4) - -#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i) -#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0) -#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1) -#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2) -#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3) - -#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i) -#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0) -#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1) -#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2) -#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3) -#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) -#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) - -#define XLP_IO_SATA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 2) - -/* XLP2xx has an updated USB block */ -#define XLP2XX_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 4, i) -#define XLP2XX_IO_USB_XHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 1) -#define XLP2XX_IO_USB_XHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 2) -#define XLP2XX_IO_USB_XHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 3) - -#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) -#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) - -#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0) - -#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1) -#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2) -#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3) - -#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i) -#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0) -#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1) -#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i) -#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) -#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) -#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) -/* on 2XX, all I2C busses are on the same block */ -#define XLP2XX_IO_I2C_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 7) - -/* system management */ -#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) -#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) - -/* Flash */ -#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0) -#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) -#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) -#define XLP_IO_MMC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) - -/* Things have changed drastically in XLP 9XX */ -#define XLP9XX_HDR_OFFSET(n, d, f) \ - XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f) - -#define XLP9XX_IO_BRIDGE_OFFSET(node) XLP_IO_PCI_OFFSET(0, 0, node) -#define XLP9XX_IO_PIC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 0) -#define XLP9XX_IO_UART_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 2) -#define XLP9XX_IO_SYS_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 0) -#define XLP9XX_IO_FUSE_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 1) -#define XLP9XX_IO_CLOCK_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 2) -#define XLP9XX_IO_POWER_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 3) -#define XLP9XX_IO_JTAG_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 4) - -#define XLP9XX_IO_PCIE_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 1, i) -#define XLP9XX_IO_PCIE0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 0) -#define XLP9XX_IO_PCIE2_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 2) -#define XLP9XX_IO_PCIE3_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 3) - -/* XLP9xx USB block */ -#define XLP9XX_IO_USB_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 4, i) -#define XLP9XX_IO_USB_XHCI0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 1) -#define XLP9XX_IO_USB_XHCI1_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 2) - -/* XLP9XX on-chip SATA controller */ -#define XLP9XX_IO_SATA_OFFSET(node) XLP9XX_HDR_OFFSET(node, 3, 2) - -/* Flash */ -#define XLP9XX_IO_NOR_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 0) -#define XLP9XX_IO_NAND_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 1) -#define XLP9XX_IO_SPI_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 2) -#define XLP9XX_IO_MMC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 3) - -/* PCI config header register id's */ -#define XLP_PCI_CFGREG0 0x00 -#define XLP_PCI_CFGREG1 0x01 -#define XLP_PCI_CFGREG2 0x02 -#define XLP_PCI_CFGREG3 0x03 -#define XLP_PCI_CFGREG4 0x04 -#define XLP_PCI_CFGREG5 0x05 -#define XLP_PCI_DEVINFO_REG0 0x30 -#define XLP_PCI_DEVINFO_REG1 0x31 -#define XLP_PCI_DEVINFO_REG2 0x32 -#define XLP_PCI_DEVINFO_REG3 0x33 -#define XLP_PCI_DEVINFO_REG4 0x34 -#define XLP_PCI_DEVINFO_REG5 0x35 -#define XLP_PCI_DEVINFO_REG6 0x36 -#define XLP_PCI_DEVINFO_REG7 0x37 -#define XLP_PCI_DEVSCRATCH_REG0 0x38 -#define XLP_PCI_DEVSCRATCH_REG1 0x39 -#define XLP_PCI_DEVSCRATCH_REG2 0x3a -#define XLP_PCI_DEVSCRATCH_REG3 0x3b -#define XLP_PCI_MSGSTN_REG 0x3c -#define XLP_PCI_IRTINFO_REG 0x3d -#define XLP_PCI_UCODEINFO_REG 0x3e -#define XLP_PCI_SBB_WT_REG 0x3f - -/* PCI IDs for SoC device */ -#define PCI_VENDOR_NETLOGIC 0x184e - -#define PCI_DEVICE_ID_NLM_ROOT 0x1001 -#define PCI_DEVICE_ID_NLM_ICI 0x1002 -#define PCI_DEVICE_ID_NLM_PIC 0x1003 -#define PCI_DEVICE_ID_NLM_PCIE 0x1004 -#define PCI_DEVICE_ID_NLM_EHCI 0x1007 -#define PCI_DEVICE_ID_NLM_OHCI 0x1008 -#define PCI_DEVICE_ID_NLM_NAE 0x1009 -#define PCI_DEVICE_ID_NLM_POE 0x100A -#define PCI_DEVICE_ID_NLM_FMN 0x100B -#define PCI_DEVICE_ID_NLM_RAID 0x100D -#define PCI_DEVICE_ID_NLM_SAE 0x100D -#define PCI_DEVICE_ID_NLM_RSA 0x100E -#define PCI_DEVICE_ID_NLM_CMP 0x100F -#define PCI_DEVICE_ID_NLM_UART 0x1010 -#define PCI_DEVICE_ID_NLM_I2C 0x1011 -#define PCI_DEVICE_ID_NLM_NOR 0x1015 -#define PCI_DEVICE_ID_NLM_NAND 0x1016 -#define PCI_DEVICE_ID_NLM_MMC 0x1018 -#define PCI_DEVICE_ID_NLM_SATA 0x101A -#define PCI_DEVICE_ID_NLM_XHCI 0x101D - -#define PCI_DEVICE_ID_XLP9XX_MMC 0x9018 -#define PCI_DEVICE_ID_XLP9XX_SATA 0x901A -#define PCI_DEVICE_ID_XLP9XX_XHCI 0x901D - -#ifndef __ASSEMBLY__ - -#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) - -static inline int xlp9xx_get_socbus(int node) -{ - uint64_t socbridge; - - if (node == 0) - return 1; - socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node)); - return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff; -} -#endif /* !__ASSEMBLY */ - -#endif /* __NLM_HAL_IOMAP_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h deleted file mode 100644 index 91540f41e1e4..000000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __NLM_HAL_PCIBUS_H__ -#define __NLM_HAL_PCIBUS_H__ - -/* PCIE Memory and IO regions */ -#define PCIE_MEM_BASE 0xd0000000ULL -#define PCIE_MEM_LIMIT 0xdfffffffULL -#define PCIE_IO_BASE 0x14000000ULL -#define PCIE_IO_LIMIT 0x15ffffffULL - -#define PCIE_BRIDGE_CMD 0x1 -#define PCIE_BRIDGE_MSI_CAP 0x14 -#define PCIE_BRIDGE_MSI_ADDRL 0x15 -#define PCIE_BRIDGE_MSI_ADDRH 0x16 -#define PCIE_BRIDGE_MSI_DATA 0x17 - -/* XLP Global PCIE configuration space registers */ -#define PCIE_BYTE_SWAP_MEM_BASE 0x247 -#define PCIE_BYTE_SWAP_MEM_LIM 0x248 -#define PCIE_BYTE_SWAP_IO_BASE 0x249 -#define PCIE_BYTE_SWAP_IO_LIM 0x24A - -#define PCIE_BRIDGE_MSIX_ADDR_BASE 0x24F -#define PCIE_BRIDGE_MSIX_ADDR_LIMIT 0x250 -#define PCIE_MSI_STATUS 0x25A -#define PCIE_MSI_EN 0x25B -#define PCIE_MSIX_STATUS 0x25D -#define PCIE_INT_STATUS0 0x25F -#define PCIE_INT_STATUS1 0x260 -#define PCIE_INT_EN0 0x261 -#define PCIE_INT_EN1 0x262 - -/* XLP9XX has basic changes */ -#define PCIE_9XX_BYTE_SWAP_MEM_BASE 0x25c -#define PCIE_9XX_BYTE_SWAP_MEM_LIM 0x25d -#define PCIE_9XX_BYTE_SWAP_IO_BASE 0x25e -#define PCIE_9XX_BYTE_SWAP_IO_LIM 0x25f - -#define PCIE_9XX_BRIDGE_MSIX_ADDR_BASE 0x264 -#define PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT 0x265 -#define PCIE_9XX_MSI_STATUS 0x283 -#define PCIE_9XX_MSI_EN 0x284 -/* 128 MSIX vectors available in 9xx */ -#define PCIE_9XX_MSIX_STATUS0 0x286 -#define PCIE_9XX_MSIX_STATUSX(n) (n + 0x286) -#define PCIE_9XX_MSIX_VEC 0x296 -#define PCIE_9XX_MSIX_VECX(n) (n + 0x296) -#define PCIE_9XX_INT_STATUS0 0x397 -#define PCIE_9XX_INT_STATUS1 0x398 -#define PCIE_9XX_INT_EN0 0x399 -#define PCIE_9XX_INT_EN1 0x39a - -/* other */ -#define PCIE_NLINKS 4 - -/* MSI addresses */ -#define MSI_ADDR_BASE 0xfffee00000ULL -#define MSI_ADDR_SZ 0x10000 -#define MSI_LINK_ADDR(n, l) (MSI_ADDR_BASE + \ - (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ) -#define MSIX_ADDR_BASE 0xfffef00000ULL -#define MSIX_LINK_ADDR(n, l) (MSIX_ADDR_BASE + \ - (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ) -#ifndef __ASSEMBLY__ - -#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_pcie_base(node, inst) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ - XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst)) - -#ifdef CONFIG_PCI_MSI -void xlp_init_node_msi_irqs(int node, int link); -#else -static inline void xlp_init_node_msi_irqs(int node, int link) {} -#endif - -struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev); - -#endif -#endif /* __NLM_HAL_PCIBUS_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h deleted file mode 100644 index 41cefe94f0c9..000000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _NLM_HAL_PIC_H -#define _NLM_HAL_PIC_H - -/* PIC Specific registers */ -#define PIC_CTRL 0x00 - -/* PIC control register defines */ -#define PIC_CTRL_ITV 32 /* interrupt timeout value */ -#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */ -#define PIC_CTRL_ITE 18 /* interrupt timeout enable */ -#define PIC_CTRL_STE 10 /* system timer interrupt enable */ -#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */ -#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */ -#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */ -#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */ -#define PIC_CTRL_WTE 0 /* watchdog timer enable */ - -/* PIC Status register defines */ -#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */ -#define PIC_ITE_STATUS 32 /* interrupt timeout status */ -#define PIC_STS_STATUS 4 /* System timer interrupt status */ -#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */ -#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */ - -/* PIC IPI control register offsets */ -#define PIC_IPICTRL_NMI 32 -#define PIC_IPICTRL_RIV 20 /* received interrupt vector */ -#define PIC_IPICTRL_IDB 16 /* interrupt destination base */ -#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */ - -/* PIC IRT register offsets */ -#define PIC_IRT_ENABLE 31 -#define PIC_IRT_NMI 29 -#define PIC_IRT_SCH 28 /* Scheduling scheme */ -#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */ -#define PIC_IRT_DT 19 /* Destination type */ -#define PIC_IRT_DB 16 /* Destination base */ -#define PIC_IRT_DTE 0 /* Destination thread enables */ - -#define PIC_BYTESWAP 0x02 -#define PIC_STATUS 0x04 -#define PIC_INTR_TIMEOUT 0x06 -#define PIC_ICI0_INTR_TIMEOUT 0x08 -#define PIC_ICI1_INTR_TIMEOUT 0x0a -#define PIC_ICI2_INTR_TIMEOUT 0x0c -#define PIC_IPI_CTL 0x0e -#define PIC_INT_ACK 0x10 -#define PIC_INT_PENDING0 0x12 -#define PIC_INT_PENDING1 0x14 -#define PIC_INT_PENDING2 0x16 - -#define PIC_WDOG0_MAXVAL 0x18 -#define PIC_WDOG0_COUNT 0x1a -#define PIC_WDOG0_ENABLE0 0x1c -#define PIC_WDOG0_ENABLE1 0x1e -#define PIC_WDOG0_BEATCMD 0x20 -#define PIC_WDOG0_BEAT0 0x22 -#define PIC_WDOG0_BEAT1 0x24 - -#define PIC_WDOG1_MAXVAL 0x26 -#define PIC_WDOG1_COUNT 0x28 -#define PIC_WDOG1_ENABLE0 0x2a -#define PIC_WDOG1_ENABLE1 0x2c -#define PIC_WDOG1_BEATCMD 0x2e -#define PIC_WDOG1_BEAT0 0x30 -#define PIC_WDOG1_BEAT1 0x32 - -#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) -#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) -#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0)) -#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0)) -#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) -#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0)) -#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0)) - -#define PIC_TIMER0_MAXVAL 0x34 -#define PIC_TIMER1_MAXVAL 0x36 -#define PIC_TIMER2_MAXVAL 0x38 -#define PIC_TIMER3_MAXVAL 0x3a -#define PIC_TIMER4_MAXVAL 0x3c -#define PIC_TIMER5_MAXVAL 0x3e -#define PIC_TIMER6_MAXVAL 0x40 -#define PIC_TIMER7_MAXVAL 0x42 -#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2)) - -#define PIC_TIMER0_COUNT 0x44 -#define PIC_TIMER1_COUNT 0x46 -#define PIC_TIMER2_COUNT 0x48 -#define PIC_TIMER3_COUNT 0x4a -#define PIC_TIMER4_COUNT 0x4c -#define PIC_TIMER5_COUNT 0x4e -#define PIC_TIMER6_COUNT 0x50 -#define PIC_TIMER7_COUNT 0x52 -#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2)) - -#define PIC_ITE0_N0_N1 0x54 -#define PIC_ITE1_N0_N1 0x58 -#define PIC_ITE2_N0_N1 0x5c -#define PIC_ITE3_N0_N1 0x60 -#define PIC_ITE4_N0_N1 0x64 -#define PIC_ITE5_N0_N1 0x68 -#define PIC_ITE6_N0_N1 0x6c -#define PIC_ITE7_N0_N1 0x70 -#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4)) - -#define PIC_ITE0_N2_N3 0x56 -#define PIC_ITE1_N2_N3 0x5a -#define PIC_ITE2_N2_N3 0x5e -#define PIC_ITE3_N2_N3 0x62 -#define PIC_ITE4_N2_N3 0x66 -#define PIC_ITE5_N2_N3 0x6a -#define PIC_ITE6_N2_N3 0x6e -#define PIC_ITE7_N2_N3 0x72 -#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4)) - -#define PIC_IRT0 0x74 -#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) - -#define PIC_9XX_PENDING_0 0x6 -#define PIC_9XX_PENDING_1 0x8 -#define PIC_9XX_PENDING_2 0xa -#define PIC_9XX_PENDING_3 0xc - -#define PIC_9XX_IRT0 0x1c0 -#define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2)) - -/* - * IRT Map - */ -#define PIC_NUM_IRTS 160 -#define PIC_9XX_NUM_IRTS 256 - -#define PIC_IRT_WD_0_INDEX 0 -#define PIC_IRT_WD_1_INDEX 1 -#define PIC_IRT_WD_NMI_0_INDEX 2 -#define PIC_IRT_WD_NMI_1_INDEX 3 -#define PIC_IRT_TIMER_0_INDEX 4 -#define PIC_IRT_TIMER_1_INDEX 5 -#define PIC_IRT_TIMER_2_INDEX 6 -#define PIC_IRT_TIMER_3_INDEX 7 -#define PIC_IRT_TIMER_4_INDEX 8 -#define PIC_IRT_TIMER_5_INDEX 9 -#define PIC_IRT_TIMER_6_INDEX 10 -#define PIC_IRT_TIMER_7_INDEX 11 -#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX -#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX) - - -/* 11 and 12 */ -#define PIC_NUM_MSG_Q_IRTS 32 -#define PIC_IRT_MSG_Q0_INDEX 12 -#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX) -/* 12 to 43 */ -#define PIC_IRT_MSG_0_INDEX 44 -#define PIC_IRT_MSG_1_INDEX 45 -/* 44 and 45 */ -#define PIC_NUM_PCIE_MSIX_IRTS 32 -#define PIC_IRT_PCIE_MSIX_0_INDEX 46 -#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX) -/* 46 to 77 */ -#define PIC_NUM_PCIE_LINK_IRTS 4 -#define PIC_IRT_PCIE_LINK_0_INDEX 78 -#define PIC_IRT_PCIE_LINK_1_INDEX 79 -#define PIC_IRT_PCIE_LINK_2_INDEX 80 -#define PIC_IRT_PCIE_LINK_3_INDEX 81 -#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) - -#define PIC_9XX_IRT_PCIE_LINK_0_INDEX 191 -#define PIC_9XX_IRT_PCIE_LINK_INDEX(num) \ - ((num) + PIC_9XX_IRT_PCIE_LINK_0_INDEX) - -#define PIC_CLOCK_TIMER 7 - -#if !defined(LOCORE) && !defined(__ASSEMBLY__) - -/* - * Misc - */ -#define PIC_IRT_VALID 1 -#define PIC_LOCAL_SCHEDULING 1 -#define PIC_GLOBAL_SCHEDULING 0 - -#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) -#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) -#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ - XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node)) -#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) - -/* We use PIC on node 0 as a timer */ -#define pic_timer_freq() nlm_get_pic_frequency(0) - -/* IRT and h/w interrupt routines */ -static inline void -nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, - int sch, int vec, int dt, int db, int cpu) -{ - uint64_t val; - - val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) | - ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) | - ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) | - (cpu & 0x3ff); - - nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val); -} - -static inline void -nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, - int sch, int vec, int dt, int db, int dte) -{ - uint64_t val; - - val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) | - ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) | - ((dt & 0x1) << 19) | ((db & 0x7) << 16) | - (dte & 0xffff); - - nlm_write_pic_reg(base, PIC_IRT(irt_num), val); -} - -static inline void -nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, - int sch, int vec, int cpu) -{ - if (cpu_is_xlp9xx()) - nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec, - 1, 0, cpu); - else - nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, - (cpu >> 4), /* thread group */ - 1 << (cpu & 0xf)); /* thread mask */ -} - -static inline uint64_t -nlm_pic_read_timer(uint64_t base, int timer) -{ - return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); -} - -static inline uint32_t -nlm_pic_read_timer32(uint64_t base, int timer) -{ - return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); -} - -static inline void -nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) -{ - nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value); -} - -static inline void -nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) -{ - uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL); - int en; - - en = (irq > 0); - nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value); - nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer), - en, 0, 0, irq, cpu); - - /* enable the timer */ - pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); - nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl); -} - -static inline void -nlm_pic_enable_irt(uint64_t base, int irt) -{ - uint64_t reg; - - if (cpu_is_xlp9xx()) { - reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); - nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22)); - } else { - reg = nlm_read_pic_reg(base, PIC_IRT(irt)); - nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); - } -} - -static inline void -nlm_pic_disable_irt(uint64_t base, int irt) -{ - uint64_t reg; - - if (cpu_is_xlp9xx()) { - reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); - reg &= ~((uint64_t)1 << 22); - nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg); - } else { - reg = nlm_read_pic_reg(base, PIC_IRT(irt)); - reg &= ~((uint64_t)1 << 31); - nlm_write_pic_reg(base, PIC_IRT(irt), reg); - } -} - -static inline void -nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) -{ - uint64_t ipi; - - if (cpu_is_xlp9xx()) - ipi = (nmi << 23) | (irq << 24) | - (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt; - else - ipi = ((uint64_t)nmi << 31) | (irq << 20) | - ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); - - nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); -} - -static inline void -nlm_pic_ack(uint64_t base, int irt_num) -{ - nlm_write_pic_reg(base, PIC_INT_ACK, irt_num); - - /* Ack the Status register for Watchdog & System timers */ - if (irt_num < 12) - nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num)); -} - -static inline void -nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) -{ - nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt); -} - -int nlm_irq_to_irt(int irq); - -#endif /* __ASSEMBLY__ */ -#endif /* _NLM_HAL_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h deleted file mode 100644 index 6bcf3952e556..000000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __NLM_HAL_SYS_H__ -#define __NLM_HAL_SYS_H__ - -/** -* @file_name sys.h -* @author Netlogic Microsystems -* @brief HAL for System configuration registers -*/ -#define SYS_CHIP_RESET 0x00 -#define SYS_POWER_ON_RESET_CFG 0x01 -#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02 -#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03 -#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04 -#define SYS_EFUSE_DEVICE_CFG3 0x05 -#define SYS_EFUSE_DEVICE_CFG4 0x06 -#define SYS_EFUSE_DEVICE_CFG5 0x07 -#define SYS_EFUSE_DEVICE_CFG6 0x08 -#define SYS_EFUSE_DEVICE_CFG7 0x09 -#define SYS_PLL_CTRL 0x0a -#define SYS_CPU_RESET 0x0b -#define SYS_CPU_NONCOHERENT_MODE 0x0d -#define SYS_CORE_DFS_DIS_CTRL 0x0e -#define SYS_CORE_DFS_RST_CTRL 0x0f -#define SYS_CORE_DFS_BYP_CTRL 0x10 -#define SYS_CORE_DFS_PHA_CTRL 0x11 -#define SYS_CORE_DFS_DIV_INC_CTRL 0x12 -#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13 -#define SYS_CORE_DFS_DIV_VALUE 0x14 -#define SYS_RESET 0x15 -#define SYS_DFS_DIS_CTRL 0x16 -#define SYS_DFS_RST_CTRL 0x17 -#define SYS_DFS_BYP_CTRL 0x18 -#define SYS_DFS_DIV_INC_CTRL 0x19 -#define SYS_DFS_DIV_DEC_CTRL 0x1a -#define SYS_DFS_DIV_VALUE0 0x1b -#define SYS_DFS_DIV_VALUE1 0x1c -#define SYS_SENSE_AMP_DLY 0x1d -#define SYS_SOC_SENSE_AMP_DLY 0x1e -#define SYS_CTRL0 0x1f -#define SYS_CTRL1 0x20 -#define SYS_TIMEOUT_BS1 0x21 -#define SYS_BYTE_SWAP 0x22 -#define SYS_VRM_VID 0x23 -#define SYS_PWR_RAM_CMD 0x24 -#define SYS_PWR_RAM_ADDR 0x25 -#define SYS_PWR_RAM_DATA0 0x26 -#define SYS_PWR_RAM_DATA1 0x27 -#define SYS_PWR_RAM_DATA2 0x28 -#define SYS_PWR_UCODE 0x29 -#define SYS_CPU0_PWR_STATUS 0x2a -#define SYS_CPU1_PWR_STATUS 0x2b -#define SYS_CPU2_PWR_STATUS 0x2c -#define SYS_CPU3_PWR_STATUS 0x2d -#define SYS_CPU4_PWR_STATUS 0x2e -#define SYS_CPU5_PWR_STATUS 0x2f -#define SYS_CPU6_PWR_STATUS 0x30 -#define SYS_CPU7_PWR_STATUS 0x31 -#define SYS_STATUS 0x32 -#define SYS_INT_POL 0x33 -#define SYS_INT_TYPE 0x34 -#define SYS_INT_STATUS 0x35 -#define SYS_INT_MASK0 0x36 -#define SYS_INT_MASK1 0x37 -#define SYS_UCO_S_ECC 0x38 -#define SYS_UCO_M_ECC 0x39 -#define SYS_UCO_ADDR 0x3a -#define SYS_UCO_INSTR 0x3b -#define SYS_MEM_BIST0 0x3c -#define SYS_MEM_BIST1 0x3d -#define SYS_MEM_BIST2 0x3e -#define SYS_MEM_BIST3 0x3f -#define SYS_MEM_BIST4 0x40 -#define SYS_MEM_BIST5 0x41 -#define SYS_MEM_BIST6 0x42 -#define SYS_MEM_BIST7 0x43 -#define SYS_MEM_BIST8 0x44 -#define SYS_MEM_BIST9 0x45 -#define SYS_MEM_BIST10 0x46 -#define SYS_MEM_BIST11 0x47 -#define SYS_MEM_BIST12 0x48 -#define SYS_SCRTCH0 0x49 -#define SYS_SCRTCH1 0x4a -#define SYS_SCRTCH2 0x4b -#define SYS_SCRTCH3 0x4c - -/* PLL registers XLP2XX */ -#define SYS_CPU_PLL_CTRL0(core) (0x1c0 + (core * 4)) -#define SYS_CPU_PLL_CTRL1(core) (0x1c1 + (core * 4)) -#define SYS_CPU_PLL_CTRL2(core) (0x1c2 + (core * 4)) -#define SYS_CPU_PLL_CTRL3(core) (0x1c3 + (core * 4)) -#define SYS_PLL_CTRL0 0x240 -#define SYS_PLL_CTRL1 0x241 -#define SYS_PLL_CTRL2 0x242 -#define SYS_PLL_CTRL3 0x243 -#define SYS_DMC_PLL_CTRL0 0x244 -#define SYS_DMC_PLL_CTRL1 0x245 -#define SYS_DMC_PLL_CTRL2 0x246 -#define SYS_DMC_PLL_CTRL3 0x247 - -#define SYS_PLL_CTRL0_DEVX(x) (0x248 + (x) * 4) -#define SYS_PLL_CTRL1_DEVX(x) (0x249 + (x) * 4) -#define SYS_PLL_CTRL2_DEVX(x) (0x24a + (x) * 4) -#define SYS_PLL_CTRL3_DEVX(x) (0x24b + (x) * 4) - -#define SYS_CPU_PLL_CHG_CTRL 0x288 -#define SYS_PLL_CHG_CTRL 0x289 -#define SYS_CLK_DEV_DIS 0x28a -#define SYS_CLK_DEV_SEL 0x28b -#define SYS_CLK_DEV_DIV 0x28c -#define SYS_CLK_DEV_CHG 0x28d -#define SYS_CLK_DEV_SEL_REG 0x28e -#define SYS_CLK_DEV_DIV_REG 0x28f -#define SYS_CPU_PLL_LOCK 0x29f -#define SYS_SYS_PLL_LOCK 0x2a0 -#define SYS_PLL_MEM_CMD 0x2a1 -#define SYS_CPU_PLL_MEM_REQ 0x2a2 -#define SYS_SYS_PLL_MEM_REQ 0x2a3 -#define SYS_PLL_MEM_STAT 0x2a4 - -/* PLL registers XLP9XX */ -#define SYS_9XX_CPU_PLL_CTRL0(core) (0xc0 + (core * 4)) -#define SYS_9XX_CPU_PLL_CTRL1(core) (0xc1 + (core * 4)) -#define SYS_9XX_CPU_PLL_CTRL2(core) (0xc2 + (core * 4)) -#define SYS_9XX_CPU_PLL_CTRL3(core) (0xc3 + (core * 4)) -#define SYS_9XX_DMC_PLL_CTRL0 0x140 -#define SYS_9XX_DMC_PLL_CTRL1 0x141 -#define SYS_9XX_DMC_PLL_CTRL2 0x142 -#define SYS_9XX_DMC_PLL_CTRL3 0x143 -#define SYS_9XX_PLL_CTRL0 0x144 -#define SYS_9XX_PLL_CTRL1 0x145 -#define SYS_9XX_PLL_CTRL2 0x146 -#define SYS_9XX_PLL_CTRL3 0x147 - -#define SYS_9XX_PLL_CTRL0_DEVX(x) (0x148 + (x) * 4) -#define SYS_9XX_PLL_CTRL1_DEVX(x) (0x149 + (x) * 4) -#define SYS_9XX_PLL_CTRL2_DEVX(x) (0x14a + (x) * 4) -#define SYS_9XX_PLL_CTRL3_DEVX(x) (0x14b + (x) * 4) - -#define SYS_9XX_CPU_PLL_CHG_CTRL 0x188 -#define SYS_9XX_PLL_CHG_CTRL 0x189 -#define SYS_9XX_CLK_DEV_DIS 0x18a -#define SYS_9XX_CLK_DEV_SEL 0x18b -#define SYS_9XX_CLK_DEV_DIV 0x18d -#define SYS_9XX_CLK_DEV_CHG 0x18f - -#define SYS_9XX_CLK_DEV_SEL_REG 0x1a4 -#define SYS_9XX_CLK_DEV_DIV_REG 0x1a6 - -/* Registers changed on 9XX */ -#define SYS_9XX_POWER_ON_RESET_CFG 0x00 -#define SYS_9XX_CHIP_RESET 0x01 -#define SYS_9XX_CPU_RESET 0x02 -#define SYS_9XX_CPU_NONCOHERENT_MODE 0x03 - -/* XLP 9XX fuse block registers */ -#define FUSE_9XX_DEVCFG6 0xc6 - -#ifndef __ASSEMBLY__ - -#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ - XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node)) -#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) - -/* XLP9XX fuse block */ -#define nlm_get_fuse_pcibase(node) \ - nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node)) -#define nlm_get_fuse_regbase(node) \ - (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ) - -#define nlm_get_clock_pcibase(node) \ - nlm_pcicfg_base(XLP9XX_IO_CLOCK_OFFSET(node)) -#define nlm_get_clock_regbase(node) \ - (nlm_get_clock_pcibase(node) + XLP_IO_PCI_HDRSZ) - -unsigned int nlm_get_pic_frequency(int node); -#endif -#endif diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h deleted file mode 100644 index a6c54424dd95..000000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __XLP_HAL_UART_H__ -#define __XLP_HAL_UART_H__ - -/* UART Specific registers */ -#define UART_RX_DATA 0x00 -#define UART_TX_DATA 0x00 - -#define UART_INT_EN 0x01 -#define UART_INT_ID 0x02 -#define UART_FIFO_CTL 0x02 -#define UART_LINE_CTL 0x03 -#define UART_MODEM_CTL 0x04 -#define UART_LINE_STS 0x05 -#define UART_MODEM_STS 0x06 - -#define UART_DIVISOR0 0x00 -#define UART_DIVISOR1 0x01 - -#define BASE_BAUD (XLP_IO_CLK/16) -#define BAUD_DIVISOR(baud) (BASE_BAUD / baud) - -/* LCR mask values */ -#define LCR_5BITS 0x00 -#define LCR_6BITS 0x01 -#define LCR_7BITS 0x02 -#define LCR_8BITS 0x03 -#define LCR_STOPB 0x04 -#define LCR_PENAB 0x08 -#define LCR_PODD 0x00 -#define LCR_PEVEN 0x10 -#define LCR_PONE 0x20 -#define LCR_PZERO 0x30 -#define LCR_SBREAK 0x40 -#define LCR_EFR_ENABLE 0xbf -#define LCR_DLAB 0x80 - -/* MCR mask values */ -#define MCR_DTR 0x01 -#define MCR_RTS 0x02 -#define MCR_DRS 0x04 -#define MCR_IE 0x08 -#define MCR_LOOPBACK 0x10 - -/* FCR mask values */ -#define FCR_RCV_RST 0x02 -#define FCR_XMT_RST 0x04 -#define FCR_RX_LOW 0x00 -#define FCR_RX_MEDL 0x40 -#define FCR_RX_MEDH 0x80 -#define FCR_RX_HIGH 0xc0 - -/* IER mask values */ -#define IER_ERXRDY 0x1 -#define IER_ETXRDY 0x2 -#define IER_ERLS 0x4 -#define IER_EMSC 0x8 - -#if !defined(LOCORE) && !defined(__ASSEMBLY__) - -#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_uart_pcibase(node, inst) \ - nlm_pcicfg_base(cpu_is_xlp9xx() ? XLP9XX_IO_UART_OFFSET(node) : \ - XLP_IO_UART_OFFSET(node, inst)) -#define nlm_get_uart_regbase(node, inst) \ - (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) - -static inline void -nlm_uart_set_baudrate(uint64_t base, int baud) -{ - uint32_t lcr; - - lcr = nlm_read_uart_reg(base, UART_LINE_CTL); - - /* enable divisor register, and write baud values */ - nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7)); - nlm_write_uart_reg(base, UART_DIVISOR0, - (BAUD_DIVISOR(baud) & 0xff)); - nlm_write_uart_reg(base, UART_DIVISOR1, - ((BAUD_DIVISOR(baud) >> 8) & 0xff)); - - /* restore default lcr */ - nlm_write_uart_reg(base, UART_LINE_CTL, lcr); -} - -static inline void -nlm_uart_outbyte(uint64_t base, char c) -{ - uint32_t lsr; - - for (;;) { - lsr = nlm_read_uart_reg(base, UART_LINE_STS); - if (lsr & 0x20) - break; - } - - nlm_write_uart_reg(base, UART_TX_DATA, (int)c); -} - -static inline char -nlm_uart_inbyte(uint64_t base) -{ - int data, lsr; - - for (;;) { - lsr = nlm_read_uart_reg(base, UART_LINE_STS); - if (lsr & 0x80) { /* parity/frame/break-error - push a zero */ - data = 0; - break; - } - if (lsr & 0x01) { /* Rx data */ - data = nlm_read_uart_reg(base, UART_RX_DATA); - break; - } - } - - return (char)data; -} - -static inline int -nlm_uart_init(uint64_t base, int baud, int databits, int stopbits, - int parity, int int_en, int loopback) -{ - uint32_t lcr; - - lcr = 0; - if (databits >= 8) - lcr |= LCR_8BITS; - else if (databits == 7) - lcr |= LCR_7BITS; - else if (databits == 6) - lcr |= LCR_6BITS; - else - lcr |= LCR_5BITS; - - if (stopbits > 1) - lcr |= LCR_STOPB; - - lcr |= parity << 3; - - /* setup default lcr */ - nlm_write_uart_reg(base, UART_LINE_CTL, lcr); - - /* Reset the FIFOs */ - nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST); - - nlm_uart_set_baudrate(base, baud); - - if (loopback) - nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f); - - if (int_en) - nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY); - - return 0; -} -#endif /* !LOCORE && !__ASSEMBLY__ */ -#endif /* __XLP_HAL_UART_H__ */ diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h deleted file mode 100644 index feb6ed807ec6..000000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _NLM_HAL_XLP_H -#define _NLM_HAL_XLP_H - -#define PIC_UART_0_IRQ 17 -#define PIC_UART_1_IRQ 18 - -#define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19 -#define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i)) - -#define PIC_EHCI_0_IRQ 23 -#define PIC_EHCI_1_IRQ 24 -#define PIC_OHCI_0_IRQ 25 -#define PIC_OHCI_1_IRQ 26 -#define PIC_OHCI_2_IRQ 27 -#define PIC_OHCI_3_IRQ 28 -#define PIC_2XX_XHCI_0_IRQ 23 -#define PIC_2XX_XHCI_1_IRQ 24 -#define PIC_2XX_XHCI_2_IRQ 25 -#define PIC_9XX_XHCI_0_IRQ 23 -#define PIC_9XX_XHCI_1_IRQ 24 -#define PIC_9XX_XHCI_2_IRQ 25 - -#define PIC_MMC_IRQ 29 -#define PIC_I2C_0_IRQ 30 -#define PIC_I2C_1_IRQ 31 -#define PIC_I2C_2_IRQ 32 -#define PIC_I2C_3_IRQ 33 -#define PIC_SPI_IRQ 34 -#define PIC_NAND_IRQ 37 -#define PIC_SATA_IRQ 38 -#define PIC_GPIO_IRQ 39 - -#define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */ -#define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i)) - -/* MSI-X with second link-level dispatch */ -#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */ -#define PIC_PCIE_MSIX_IRQ(i) (48 + (i)) - -/* XLP9xx and XLP8xx has 128 and 32 MSIX vectors respectively */ -#define NLM_MSIX_VEC_BASE 96 /* 96 - 223 - MSIX mapped */ -#define NLM_MSI_VEC_BASE 224 /* 224 -351 - MSI mapped */ - -#define NLM_PIC_INDIRECT_VEC_BASE 512 -#define NLM_GPIO_VEC_BASE 768 - -#define PIC_IRQ_BASE 8 -#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE -#define PIC_IRT_LAST_IRQ 63 - -#ifndef __ASSEMBLY__ - -/* SMP support functions */ -void xlp_boot_core0_siblings(void); -void xlp_wakeup_secondary_cpus(void); - -void xlp_mmu_init(void); -void nlm_hal_init(void); -int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries); - -struct pci_dev; -int xlp_socdev_to_node(const struct pci_dev *dev); - -/* Device tree related */ -void xlp_early_init_devtree(void); -void *xlp_dt_init(void *fdtp); - -static inline int cpu_is_xlpii(void) -{ - int chip = read_c0_prid() & PRID_IMP_MASK; - - return chip == PRID_IMP_NETLOGIC_XLP2XX || - chip == PRID_IMP_NETLOGIC_XLP9XX || - chip == PRID_IMP_NETLOGIC_XLP5XX; -} - -static inline int cpu_is_xlp9xx(void) -{ - int chip = read_c0_prid() & PRID_IMP_MASK; - - return chip == PRID_IMP_NETLOGIC_XLP9XX || - chip == PRID_IMP_NETLOGIC_XLP5XX; -} -#endif /* !__ASSEMBLY__ */ -#endif /* _ASM_NLM_XLP_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h deleted file mode 100644 index 2d02428c4f1b..000000000000 --- a/arch/mips/include/asm/netlogic/xlr/bridge.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _ASM_NLM_BRIDGE_H_ -#define _ASM_NLM_BRIDGE_H_ - -#define BRIDGE_DRAM_0_BAR 0 -#define BRIDGE_DRAM_1_BAR 1 -#define BRIDGE_DRAM_2_BAR 2 -#define BRIDGE_DRAM_3_BAR 3 -#define BRIDGE_DRAM_4_BAR 4 -#define BRIDGE_DRAM_5_BAR 5 -#define BRIDGE_DRAM_6_BAR 6 -#define BRIDGE_DRAM_7_BAR 7 -#define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8 -#define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9 -#define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10 -#define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11 -#define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12 -#define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13 -#define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14 -#define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15 -#define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16 -#define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17 -#define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18 -#define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19 -#define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20 -#define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21 -#define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22 -#define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23 -#define BRIDGE_CFG_BAR 24 -#define BRIDGE_PHNX_IO_BAR 25 -#define BRIDGE_FLASH_BAR 26 -#define BRIDGE_SRAM_BAR 27 -#define BRIDGE_HTMEM_BAR 28 -#define BRIDGE_HTINT_BAR 29 -#define BRIDGE_HTPIC_BAR 30 -#define BRIDGE_HTSM_BAR 31 -#define BRIDGE_HTIO_BAR 32 -#define BRIDGE_HTCFG_BAR 33 -#define BRIDGE_PCIXCFG_BAR 34 -#define BRIDGE_PCIXMEM_BAR 35 -#define BRIDGE_PCIXIO_BAR 36 -#define BRIDGE_DEVICE_MASK 37 -#define BRIDGE_AERR_INTR_LOG1 38 -#define BRIDGE_AERR_INTR_LOG2 39 -#define BRIDGE_AERR_INTR_LOG3 40 -#define BRIDGE_AERR_DEV_STAT 41 -#define BRIDGE_AERR1_LOG1 42 -#define BRIDGE_AERR1_LOG2 43 -#define BRIDGE_AERR1_LOG3 44 -#define BRIDGE_AERR1_DEV_STAT 45 -#define BRIDGE_AERR_INTR_EN 46 -#define BRIDGE_AERR_UPG 47 -#define BRIDGE_AERR_CLEAR 48 -#define BRIDGE_AERR1_CLEAR 49 -#define BRIDGE_SBE_COUNTS 50 -#define BRIDGE_DBE_COUNTS 51 -#define BRIDGE_BITERR_INT_EN 52 - -#define BRIDGE_SYS2IO_CREDITS 53 -#define BRIDGE_EVNT_CNT_CTRL1 54 -#define BRIDGE_EVNT_COUNTER1 55 -#define BRIDGE_EVNT_CNT_CTRL2 56 -#define BRIDGE_EVNT_COUNTER2 57 -#define BRIDGE_RESERVED1 58 - -#define BRIDGE_DEFEATURE 59 -#define BRIDGE_SCRATCH0 60 -#define BRIDGE_SCRATCH1 61 -#define BRIDGE_SCRATCH2 62 -#define BRIDGE_SCRATCH3 63 - -#endif diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h deleted file mode 100644 index f8aca5472b6c..000000000000 --- a/arch/mips/include/asm/netlogic/xlr/flash.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _ASM_NLM_FLASH_H_ -#define _ASM_NLM_FLASH_H_ - -#define FLASH_CSBASE_ADDR(cs) (cs) -#define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) -#define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) -#define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) -#define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) - -#define FLASH_INT_MASK 0x50 -#define FLASH_INT_STATUS 0x60 -#define FLASH_ERROR_STATUS 0x70 -#define FLASH_ERROR_ADDR 0x80 - -#define FLASH_NAND_CLE(cs) (0x90 + (cs)) -#define FLASH_NAND_ALE(cs) (0xa0 + (cs)) - -#define FLASH_NAND_CSDEV_PARAM 0x000041e6 -#define FLASH_NAND_CSTIME_PARAMA 0x4f400e22 -#define FLASH_NAND_CSTIME_PARAMB 0x000083cf - -#endif diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h deleted file mode 100644 index d79c68fa78d9..000000000000 --- a/arch/mips/include/asm/netlogic/xlr/fmn.h +++ /dev/null @@ -1,365 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _NLM_FMN_H_ -#define _NLM_FMN_H_ - -#include <asm/netlogic/mips-extns.h> /* for COP2 access */ - -/* Station IDs */ -#define FMN_STNID_CPU0 0x00 -#define FMN_STNID_CPU1 0x08 -#define FMN_STNID_CPU2 0x10 -#define FMN_STNID_CPU3 0x18 -#define FMN_STNID_CPU4 0x20 -#define FMN_STNID_CPU5 0x28 -#define FMN_STNID_CPU6 0x30 -#define FMN_STNID_CPU7 0x38 - -#define FMN_STNID_XGS0_TX 64 -#define FMN_STNID_XMAC0_00_TX 64 -#define FMN_STNID_XMAC0_01_TX 65 -#define FMN_STNID_XMAC0_02_TX 66 -#define FMN_STNID_XMAC0_03_TX 67 -#define FMN_STNID_XMAC0_04_TX 68 -#define FMN_STNID_XMAC0_05_TX 69 -#define FMN_STNID_XMAC0_06_TX 70 -#define FMN_STNID_XMAC0_07_TX 71 -#define FMN_STNID_XMAC0_08_TX 72 -#define FMN_STNID_XMAC0_09_TX 73 -#define FMN_STNID_XMAC0_10_TX 74 -#define FMN_STNID_XMAC0_11_TX 75 -#define FMN_STNID_XMAC0_12_TX 76 -#define FMN_STNID_XMAC0_13_TX 77 -#define FMN_STNID_XMAC0_14_TX 78 -#define FMN_STNID_XMAC0_15_TX 79 - -#define FMN_STNID_XGS1_TX 80 -#define FMN_STNID_XMAC1_00_TX 80 -#define FMN_STNID_XMAC1_01_TX 81 -#define FMN_STNID_XMAC1_02_TX 82 -#define FMN_STNID_XMAC1_03_TX 83 -#define FMN_STNID_XMAC1_04_TX 84 -#define FMN_STNID_XMAC1_05_TX 85 -#define FMN_STNID_XMAC1_06_TX 86 -#define FMN_STNID_XMAC1_07_TX 87 -#define FMN_STNID_XMAC1_08_TX 88 -#define FMN_STNID_XMAC1_09_TX 89 -#define FMN_STNID_XMAC1_10_TX 90 -#define FMN_STNID_XMAC1_11_TX 91 -#define FMN_STNID_XMAC1_12_TX 92 -#define FMN_STNID_XMAC1_13_TX 93 -#define FMN_STNID_XMAC1_14_TX 94 -#define FMN_STNID_XMAC1_15_TX 95 - -#define FMN_STNID_GMAC 96 -#define FMN_STNID_GMACJFR_0 96 -#define FMN_STNID_GMACRFR_0 97 -#define FMN_STNID_GMACTX0 98 -#define FMN_STNID_GMACTX1 99 -#define FMN_STNID_GMACTX2 100 -#define FMN_STNID_GMACTX3 101 -#define FMN_STNID_GMACJFR_1 102 -#define FMN_STNID_GMACRFR_1 103 - -#define FMN_STNID_DMA 104 -#define FMN_STNID_DMA_0 104 -#define FMN_STNID_DMA_1 105 -#define FMN_STNID_DMA_2 106 -#define FMN_STNID_DMA_3 107 - -#define FMN_STNID_XGS0FR 112 -#define FMN_STNID_XMAC0JFR 112 -#define FMN_STNID_XMAC0RFR 113 - -#define FMN_STNID_XGS1FR 114 -#define FMN_STNID_XMAC1JFR 114 -#define FMN_STNID_XMAC1RFR 115 -#define FMN_STNID_SEC 120 -#define FMN_STNID_SEC0 120 -#define FMN_STNID_SEC1 121 -#define FMN_STNID_SEC2 122 -#define FMN_STNID_SEC3 123 -#define FMN_STNID_PK0 124 -#define FMN_STNID_SEC_RSA 124 -#define FMN_STNID_SEC_RSVD0 125 -#define FMN_STNID_SEC_RSVD1 126 -#define FMN_STNID_SEC_RSVD2 127 - -#define FMN_STNID_GMAC1 80 -#define FMN_STNID_GMAC1_FR_0 81 -#define FMN_STNID_GMAC1_TX0 82 -#define FMN_STNID_GMAC1_TX1 83 -#define FMN_STNID_GMAC1_TX2 84 -#define FMN_STNID_GMAC1_TX3 85 -#define FMN_STNID_GMAC1_FR_1 87 -#define FMN_STNID_GMAC0 96 -#define FMN_STNID_GMAC0_FR_0 97 -#define FMN_STNID_GMAC0_TX0 98 -#define FMN_STNID_GMAC0_TX1 99 -#define FMN_STNID_GMAC0_TX2 100 -#define FMN_STNID_GMAC0_TX3 101 -#define FMN_STNID_GMAC0_FR_1 103 -#define FMN_STNID_CMP_0 108 -#define FMN_STNID_CMP_1 109 -#define FMN_STNID_CMP_2 110 -#define FMN_STNID_CMP_3 111 -#define FMN_STNID_PCIE_0 116 -#define FMN_STNID_PCIE_1 117 -#define FMN_STNID_PCIE_2 118 -#define FMN_STNID_PCIE_3 119 -#define FMN_STNID_XLS_PK0 121 - -#define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s) -#define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s) -#define nlm_read_c2_cc2(s) __read_32bit_c2_register($18, s) -#define nlm_read_c2_cc3(s) __read_32bit_c2_register($19, s) -#define nlm_read_c2_cc4(s) __read_32bit_c2_register($20, s) -#define nlm_read_c2_cc5(s) __read_32bit_c2_register($21, s) -#define nlm_read_c2_cc6(s) __read_32bit_c2_register($22, s) -#define nlm_read_c2_cc7(s) __read_32bit_c2_register($23, s) -#define nlm_read_c2_cc8(s) __read_32bit_c2_register($24, s) -#define nlm_read_c2_cc9(s) __read_32bit_c2_register($25, s) -#define nlm_read_c2_cc10(s) __read_32bit_c2_register($26, s) -#define nlm_read_c2_cc11(s) __read_32bit_c2_register($27, s) -#define nlm_read_c2_cc12(s) __read_32bit_c2_register($28, s) -#define nlm_read_c2_cc13(s) __read_32bit_c2_register($29, s) -#define nlm_read_c2_cc14(s) __read_32bit_c2_register($30, s) -#define nlm_read_c2_cc15(s) __read_32bit_c2_register($31, s) - -#define nlm_write_c2_cc0(s, v) __write_32bit_c2_register($16, s, v) -#define nlm_write_c2_cc1(s, v) __write_32bit_c2_register($17, s, v) -#define nlm_write_c2_cc2(s, v) __write_32bit_c2_register($18, s, v) -#define nlm_write_c2_cc3(s, v) __write_32bit_c2_register($19, s, v) -#define nlm_write_c2_cc4(s, v) __write_32bit_c2_register($20, s, v) -#define nlm_write_c2_cc5(s, v) __write_32bit_c2_register($21, s, v) -#define nlm_write_c2_cc6(s, v) __write_32bit_c2_register($22, s, v) -#define nlm_write_c2_cc7(s, v) __write_32bit_c2_register($23, s, v) -#define nlm_write_c2_cc8(s, v) __write_32bit_c2_register($24, s, v) -#define nlm_write_c2_cc9(s, v) __write_32bit_c2_register($25, s, v) -#define nlm_write_c2_cc10(s, v) __write_32bit_c2_register($26, s, v) -#define nlm_write_c2_cc11(s, v) __write_32bit_c2_register($27, s, v) -#define nlm_write_c2_cc12(s, v) __write_32bit_c2_register($28, s, v) -#define nlm_write_c2_cc13(s, v) __write_32bit_c2_register($29, s, v) -#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v) -#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v) - -#define nlm_read_c2_status0() __read_32bit_c2_register($2, 0) -#define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v) -#define nlm_read_c2_status1() __read_32bit_c2_register($2, 1) -#define nlm_write_c2_status1(v) __write_32bit_c2_register($2, 1, v) -#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0) -#define nlm_read_c2_config() __read_32bit_c2_register($3, 0) -#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v) -#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b) -#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v) - -#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0) -#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1) -#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2) -#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3) - -#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v) -#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v) -#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v) -#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v) - -#define FMN_STN_RX_QSIZE 256 -#define FMN_NSTATIONS 128 -#define FMN_CORE_NBUCKETS 8 - -static inline void nlm_msgsnd(unsigned int stid) -{ - __asm__ volatile ( - ".set push\n" - ".set noreorder\n" - ".set noat\n" - "move $1, %0\n" - "c2 0x10001\n" /* msgsnd $1 */ - ".set pop\n" - : : "r" (stid) : "$1" - ); -} - -static inline void nlm_msgld(unsigned int pri) -{ - __asm__ volatile ( - ".set push\n" - ".set noreorder\n" - ".set noat\n" - "move $1, %0\n" - "c2 0x10002\n" /* msgld $1 */ - ".set pop\n" - : : "r" (pri) : "$1" - ); -} - -static inline void nlm_msgwait(unsigned int mask) -{ - __asm__ volatile ( - ".set push\n" - ".set noreorder\n" - ".set noat\n" - "move $8, %0\n" - "c2 0x10003\n" /* msgwait $1 */ - ".set pop\n" - : : "r" (mask) : "$1" - ); -} - -/* - * Disable interrupts and enable COP2 access - */ -static inline uint32_t nlm_cop2_enable_irqsave(void) -{ - uint32_t sr = read_c0_status(); - - write_c0_status((sr & ~ST0_IE) | ST0_CU2); - return sr; -} - -static inline void nlm_cop2_disable_irqrestore(uint32_t sr) -{ - write_c0_status(sr); -} - -static inline void nlm_fmn_setup_intr(int irq, unsigned int tmask) -{ - uint32_t config; - - config = (1 << 24) /* interrupt water mark - 1 msg */ - | (irq << 16) /* irq */ - | (tmask << 8) /* thread mask */ - | 0x2; /* enable watermark intr, disable empty intr */ - nlm_write_c2_config(config); -} - -struct nlm_fmn_msg { - uint64_t msg0; - uint64_t msg1; - uint64_t msg2; - uint64_t msg3; -}; - -static inline int nlm_fmn_send(unsigned int size, unsigned int code, - unsigned int stid, struct nlm_fmn_msg *msg) -{ - unsigned int dest; - uint32_t status; - int i; - - /* - * Make sure that all the writes pending at the cpu are flushed. - * Any writes pending on CPU will not be see by devices. L1/L2 - * caches are coherent with IO, so no cache flush needed. - */ - __asm __volatile("sync"); - - /* Load TX message buffers */ - nlm_write_c2_tx_msg0(msg->msg0); - nlm_write_c2_tx_msg1(msg->msg1); - nlm_write_c2_tx_msg2(msg->msg2); - nlm_write_c2_tx_msg3(msg->msg3); - dest = ((size - 1) << 16) | (code << 8) | stid; - - /* - * Retry a few times on credit fail, this should be a - * transient condition, unless there is a configuration - * failure, or the receiver is stuck. - */ - for (i = 0; i < 8; i++) { - nlm_msgsnd(dest); - status = nlm_read_c2_status0(); - if ((status & 0x4) == 0) - return 0; - } - - /* If there is a credit failure, return error */ - return status & 0x06; -} - -static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid, - struct nlm_fmn_msg *msg) -{ - uint32_t status, tmp; - - nlm_msgld(bucket); - - /* wait for load pending to clear */ - do { - status = nlm_read_c2_status0(); - } while ((status & 0x08) != 0); - - /* receive error bits */ - tmp = status & 0x30; - if (tmp != 0) - return tmp; - - *size = ((status & 0xc0) >> 6) + 1; - *code = (status & 0xff00) >> 8; - *stid = (status & 0x7f0000) >> 16; - msg->msg0 = nlm_read_c2_rx_msg0(); - msg->msg1 = nlm_read_c2_rx_msg1(); - msg->msg2 = nlm_read_c2_rx_msg2(); - msg->msg3 = nlm_read_c2_rx_msg3(); - - return 0; -} - -struct xlr_fmn_info { - int num_buckets; - int start_stn_id; - int end_stn_id; - int credit_config[128]; -}; - -struct xlr_board_fmn_config { - int bucket_size[128]; /* size of buckets for all stations */ - struct xlr_fmn_info cpu[8]; - struct xlr_fmn_info gmac[2]; - struct xlr_fmn_info dma; - struct xlr_fmn_info cmp; - struct xlr_fmn_info sae; - struct xlr_fmn_info xgmac[2]; -}; - -extern int nlm_register_fmn_handler(int start, int end, - void (*fn)(int, int, int, int, struct nlm_fmn_msg *, void *), - void *arg); -extern void xlr_percpu_fmn_init(void); -extern void nlm_setup_fmn_irq(void); -extern void xlr_board_info_setup(void); - -extern struct xlr_board_fmn_config xlr_board_fmn_config; -#endif diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h deleted file mode 100644 index 8492e835b110..000000000000 --- a/arch/mips/include/asm/netlogic/xlr/gpio.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _ASM_NLM_GPIO_H -#define _ASM_NLM_GPIO_H - -#define GPIO_INT_EN_REG 0 -#define GPIO_INPUT_INVERSION_REG 1 -#define GPIO_IO_DIR_REG 2 -#define GPIO_IO_DATA_WR_REG 3 -#define GPIO_IO_DATA_RD_REG 4 - -#define GPIO_SWRESET_REG 8 -#define GPIO_DRAM1_CNTRL_REG 9 -#define GPIO_DRAM1_RATIO_REG 10 -#define GPIO_DRAM1_RESET_REG 11 -#define GPIO_DRAM1_STATUS_REG 12 -#define GPIO_DRAM2_CNTRL_REG 13 -#define GPIO_DRAM2_RATIO_REG 14 -#define GPIO_DRAM2_RESET_REG 15 -#define GPIO_DRAM2_STATUS_REG 16 - -#define GPIO_PWRON_RESET_CFG_REG 21 -#define GPIO_BIST_ALL_GO_STATUS_REG 24 -#define GPIO_BIST_CPU_GO_STATUS_REG 25 -#define GPIO_BIST_DEV_GO_STATUS_REG 26 - -#define GPIO_FUSE_BANK_REG 35 -#define GPIO_CPU_RESET_REG 40 -#define GPIO_RNG_REG 43 - -#define PWRON_RESET_PCMCIA_BOOT 17 - -#define GPIO_LED_BITMAP 0x1700000 -#define GPIO_LED_0_SHIFT 20 -#define GPIO_LED_1_SHIFT 24 - -#define GPIO_LED_OUTPUT_CODE_RESET 0x01 -#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 -#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 -#define GPIO_LED_OUTPUT_CODE_MAIN 0x04 - -#endif diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h deleted file mode 100644 index ff4533d6ee64..000000000000 --- a/arch/mips/include/asm/netlogic/xlr/iomap.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _ASM_NLM_IOMAP_H -#define _ASM_NLM_IOMAP_H - -#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000) -#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000 -#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000 -#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000 -#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000 -#define NETLOGIC_IO_PIC_OFFSET 0x08000 -#define NETLOGIC_IO_UART_0_OFFSET 0x14000 -#define NETLOGIC_IO_UART_1_OFFSET 0x15100 - -#define NETLOGIC_IO_SIZE 0x1000 - -#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000 - -#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000 -#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000 - -#define NETLOGIC_IO_SRAM_OFFSET 0x07000 - -#define NETLOGIC_IO_PCIX_OFFSET 0x09000 -#define NETLOGIC_IO_HT_OFFSET 0x0A000 - -#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000 - -#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000 -#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000 -#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000 -#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000 - -/* XLS devices */ -#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000 -#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000 -#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000 -#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000 - -#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000 -#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000 -#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000 -#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000 - -#define NETLOGIC_IO_USB_0_OFFSET 0x24000 -#define NETLOGIC_IO_USB_1_OFFSET 0x25000 - -#define NETLOGIC_IO_COMP_OFFSET 0x1D000 -/* end XLS devices */ - -/* XLR devices */ -#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000 -#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000 -#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000 -#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000 -/* end XLR devices */ - -#define NETLOGIC_IO_I2C_0_OFFSET 0x16000 -#define NETLOGIC_IO_I2C_1_OFFSET 0x17000 - -#define NETLOGIC_IO_GPIO_OFFSET 0x18000 -#define NETLOGIC_IO_FLASH_OFFSET 0x19000 -#define NETLOGIC_IO_TB_OFFSET 0x1C000 - -#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000) - -/* - * Base Address (Virtual) of the PCI Config address space - * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28) - * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes - * ie 1<<24 = 16M - */ -#define DEFAULT_PCI_CONFIG_BASE 0x18000000 -#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 -#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 - -#endif diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h deleted file mode 100644 index c95d18edf12f..000000000000 --- a/arch/mips/include/asm/netlogic/xlr/msidef.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef ASM_RMI_MSIDEF_H -#define ASM_RMI_MSIDEF_H - -/* - * Constants for Intel APIC based MSI messages. - * Adapted for the RMI XLR using identical defines - */ - -/* - * Shifts for MSI data - */ - -#define MSI_DATA_VECTOR_SHIFT 0 -#define MSI_DATA_VECTOR_MASK 0x000000ff -#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \ - MSI_DATA_VECTOR_MASK) - -#define MSI_DATA_DELIVERY_MODE_SHIFT 8 -#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT) -#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT) - -#define MSI_DATA_LEVEL_SHIFT 14 -#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) -#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) - -#define MSI_DATA_TRIGGER_SHIFT 15 -#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) -#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) - -/* - * Shift/mask fields for msi address - */ - -#define MSI_ADDR_BASE_HI 0 -#define MSI_ADDR_BASE_LO 0xfee00000 - -#define MSI_ADDR_DEST_MODE_SHIFT 2 -#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT) -#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT) - -#define MSI_ADDR_REDIRECTION_SHIFT 3 -#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) -#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) - -#define MSI_ADDR_DEST_ID_SHIFT 12 -#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 -#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \ - MSI_ADDR_DEST_ID_MASK) - -#endif /* ASM_RMI_MSIDEF_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h deleted file mode 100644 index 3c80a75233bd..000000000000 --- a/arch/mips/include/asm/netlogic/xlr/pic.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _ASM_NLM_XLR_PIC_H -#define _ASM_NLM_XLR_PIC_H - -#define PIC_CLK_HZ 66666666 -#define pic_timer_freq() PIC_CLK_HZ - -/* PIC hardware interrupt numbers */ -#define PIC_IRT_WD_INDEX 0 -#define PIC_IRT_TIMER_0_INDEX 1 -#define PIC_IRT_TIMER_INDEX(i) ((i) + PIC_IRT_TIMER_0_INDEX) -#define PIC_IRT_TIMER_1_INDEX 2 -#define PIC_IRT_TIMER_2_INDEX 3 -#define PIC_IRT_TIMER_3_INDEX 4 -#define PIC_IRT_TIMER_4_INDEX 5 -#define PIC_IRT_TIMER_5_INDEX 6 -#define PIC_IRT_TIMER_6_INDEX 7 -#define PIC_IRT_TIMER_7_INDEX 8 -#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX -#define PIC_IRT_UART_0_INDEX 9 -#define PIC_IRT_UART_1_INDEX 10 -#define PIC_IRT_I2C_0_INDEX 11 -#define PIC_IRT_I2C_1_INDEX 12 -#define PIC_IRT_PCMCIA_INDEX 13 -#define PIC_IRT_GPIO_INDEX 14 -#define PIC_IRT_HYPER_INDEX 15 -#define PIC_IRT_PCIX_INDEX 16 -/* XLS */ -#define PIC_IRT_CDE_INDEX 15 -#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16 -/* XLS */ -#define PIC_IRT_GMAC0_INDEX 17 -#define PIC_IRT_GMAC1_INDEX 18 -#define PIC_IRT_GMAC2_INDEX 19 -#define PIC_IRT_GMAC3_INDEX 20 -#define PIC_IRT_XGS0_INDEX 21 -#define PIC_IRT_XGS1_INDEX 22 -#define PIC_IRT_HYPER_FATAL_INDEX 23 -#define PIC_IRT_PCIX_FATAL_INDEX 24 -#define PIC_IRT_BRIDGE_AERR_INDEX 25 -#define PIC_IRT_BRIDGE_BERR_INDEX 26 -#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27 -#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28 -/* XLS */ -#define PIC_IRT_GMAC4_INDEX 21 -#define PIC_IRT_GMAC5_INDEX 22 -#define PIC_IRT_GMAC6_INDEX 23 -#define PIC_IRT_GMAC7_INDEX 24 -#define PIC_IRT_BRIDGE_ERR_INDEX 25 -#define PIC_IRT_PCIE_LINK0_INDEX 26 -#define PIC_IRT_PCIE_LINK1_INDEX 27 -#define PIC_IRT_PCIE_LINK2_INDEX 23 -#define PIC_IRT_PCIE_LINK3_INDEX 24 -#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28 -#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29 -#define PIC_IRT_SRIO_LINK0_INDEX 26 -#define PIC_IRT_SRIO_LINK1_INDEX 27 -#define PIC_IRT_SRIO_LINK2_INDEX 28 -#define PIC_IRT_SRIO_LINK3_INDEX 29 -#define PIC_IRT_PCIE_INT_INDEX 28 -#define PIC_IRT_PCIE_FATAL_INDEX 29 -#define PIC_IRT_GPIO_B_INDEX 30 -#define PIC_IRT_USB_INDEX 31 -/* XLS */ -#define PIC_NUM_IRTS 32 - - -#define PIC_CLOCK_TIMER 7 - -/* PIC Registers */ -#define PIC_CTRL 0x00 -#define PIC_CTRL_STE 8 /* timer enable start bit */ -#define PIC_IPI 0x04 -#define PIC_INT_ACK 0x06 - -#define WD_MAX_VAL_0 0x08 -#define WD_MAX_VAL_1 0x09 -#define WD_MASK_0 0x0a -#define WD_MASK_1 0x0b -#define WD_HEARBEAT_0 0x0c -#define WD_HEARBEAT_1 0x0d - -#define PIC_IRT_0_BASE 0x40 -#define PIC_IRT_1_BASE 0x80 -#define PIC_TIMER_MAXVAL_0_BASE 0x100 -#define PIC_TIMER_MAXVAL_1_BASE 0x110 -#define PIC_TIMER_COUNT_0_BASE 0x120 -#define PIC_TIMER_COUNT_1_BASE 0x130 - -#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) -#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) - -#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) -#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i)) -#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i)) -#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i)) - -/* - * Mapping between hardware interrupt numbers and IRQs on CPU - * we use a simple scheme to map PIC interrupts 0-31 to IRQs - * 8-39. This leaves the IRQ 0-7 for cpu interrupts like - * count/compare and FMN - */ -#define PIC_IRQ_BASE 8 -#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) -#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) - -#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE -#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX) -#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX) -#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX) -#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX) -#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX) -#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX) -#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX) -#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX) -#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX) -#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ) -#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX) -#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX) -#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX) -#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX) -#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX) -#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX) -#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX) -#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX) -/* XLS */ -#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX) -#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX) -/* end XLS */ -#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX) -#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX) -#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX) -#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX) -#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX) -#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX) -#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX) -#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX) -#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX) -#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX) -#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX) -#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX) -/* XLS defines */ -#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX) -#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX) -#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX) -#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX) -#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX) -#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX) -#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX) -#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX) -#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX) -#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX) -#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX) -#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX) -#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX) -#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX) -#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX) -#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX) -#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX) -#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX) -#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX) -#define PIC_IRT_LAST_IRQ PIC_USB_IRQ -/* end XLS */ - -#ifndef __ASSEMBLY__ - -#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ - ((irq) <= PIC_TIMER_7_IRQ)) -#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ - ((irq) <= PIC_IRT_LAST_IRQ)) - -static inline int -nlm_irq_to_irt(int irq) -{ - if (PIC_IRQ_IS_IRT(irq) == 0) - return -1; - - return PIC_IRQ_TO_INTR(irq); -} - -static inline int -nlm_irt_to_irq(int irt) -{ - - return PIC_INTR_TO_IRQ(irt); -} - -static inline void -nlm_pic_enable_irt(uint64_t base, int irt) -{ - uint32_t reg; - - reg = nlm_read_reg(base, PIC_IRT_1(irt)); - nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31)); -} - -static inline void -nlm_pic_disable_irt(uint64_t base, int irt) -{ - uint32_t reg; - - reg = nlm_read_reg(base, PIC_IRT_1(irt)); - nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31)); -} - -static inline void -nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) -{ - unsigned int tid, pid; - - tid = hwt & 0x3; - pid = (hwt >> 2) & 0x07; - nlm_write_reg(base, PIC_IPI, - (pid << 20) | (tid << 16) | (nmi << 8) | irq); -} - -static inline void -nlm_pic_ack(uint64_t base, int irt) -{ - nlm_write_reg(base, PIC_INT_ACK, 1u << irt); -} - -static inline void -nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) -{ - nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); - /* local scheduling, invalid, level by default */ - nlm_write_reg(base, PIC_IRT_1(irt), - (en << 30) | (1 << 6) | irq); -} - -static inline uint64_t -nlm_pic_read_timer(uint64_t base, int timer) -{ - uint32_t up1, up2, low; - - up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); - low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); - up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); - - if (up1 != up2) /* wrapped, get the new low */ - low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); - return ((uint64_t)up2 << 32) | low; - -} - -static inline uint32_t -nlm_pic_read_timer32(uint64_t base, int timer) -{ - return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); -} - -static inline void -nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) -{ - uint32_t up, low; - uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL); - int en; - - en = (irq > 0); - up = value >> 32; - low = value & 0xFFFFFFFF; - nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low); - nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up); - nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0); - - /* enable the timer */ - pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); - nlm_write_reg(base, PIC_CTRL, pic_ctrl); -} -#endif -#endif /* _ASM_NLM_XLR_PIC_H */ diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h deleted file mode 100644 index ceb991ca8436..000000000000 --- a/arch/mips/include/asm/netlogic/xlr/xlr.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _ASM_NLM_XLR_H -#define _ASM_NLM_XLR_H - -/* SMP helpers */ -void xlr_wakeup_secondary_cpus(void); - -/* XLS B silicon "Rook" */ -static inline unsigned int nlm_chip_is_xls_b(void) -{ - uint32_t prid = read_c0_prid(); - - return ((prid & 0xf000) == 0x4000); -} - -/* XLR chip types */ -/* The XLS product line has chip versions 0x[48c]? */ -static inline unsigned int nlm_chip_is_xls(void) -{ - uint32_t prid = read_c0_prid(); - - return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 || - (prid & 0xf000) == 0xc000); -} - -#endif /* _ASM_NLM_XLR_H */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h index c6c99e28eefb..0cddce35291b 100644 --- a/arch/mips/include/asm/octeon/cvmx-helper.h +++ b/arch/mips/include/asm/octeon/cvmx-helper.h @@ -94,13 +94,6 @@ extern int cvmx_helper_ipd_and_packet_input_enable(void); extern int cvmx_helper_initialize_packet_io_global(void); /** - * Does core local initialization for packet io - * - * Returns Zero on success, non-zero on failure - */ -extern int cvmx_helper_initialize_packet_io_local(void); - -/** * Returns the number of ports on the given interface. * The interface must be initialized before the port count * can be returned. diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h index 03fb64b13fba..5fec8476e421 100644 --- a/arch/mips/include/asm/octeon/cvmx-pko.h +++ b/arch/mips/include/asm/octeon/cvmx-pko.h @@ -277,7 +277,6 @@ typedef struct { * output system. */ extern void cvmx_pko_initialize_global(void); -extern int cvmx_pko_initialize_local(void); /** * Enables the packet output hardware. It must already be diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 9ffc8192adae..421231f55935 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -20,6 +20,10 @@ #include <linux/list.h> #include <linux/of.h> +#ifdef CONFIG_PCI_DRIVERS_GENERIC +#define pci_remap_iospace pci_remap_iospace +#endif + #ifdef CONFIG_PCI_DRIVERS_LEGACY /* diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 804889b70965..7b8037f25d9e 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -86,10 +86,9 @@ extern void paging_init(void); */ #define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd)) -#define __pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) -#ifndef CONFIG_TRANSPARENT_HUGEPAGE -#define pmd_page(pmd) __pmd_page(pmd) -#endif /* CONFIG_TRANSPARENT_HUGEPAGE */ +#ifndef CONFIG_MIPS_HUGE_TLB_SUPPORT +#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) +#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ #define pmd_page_vaddr(pmd) pmd_val(pmd) @@ -416,6 +415,25 @@ static inline pte_t pte_mkhuge(pte_t pte) pte_val(pte) |= _PAGE_HUGE; return pte; } + +#define pmd_write pmd_write +static inline int pmd_write(pmd_t pmd) +{ + return !!(pmd_val(pmd) & _PAGE_WRITE); +} + +static inline unsigned long pmd_pfn(pmd_t pmd) +{ + return pmd_val(pmd) >> _PFN_SHIFT; +} + +static inline struct page *pmd_page(pmd_t pmd) +{ + if (pmd_val(pmd) & _PAGE_HUGE) + return pfn_to_page(pmd_pfn(pmd)); + + return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT); +} #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY @@ -591,12 +609,6 @@ static inline pmd_t pmd_mkhuge(pmd_t pmd) extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, pmd_t pmd); -#define pmd_write pmd_write -static inline int pmd_write(pmd_t pmd) -{ - return !!(pmd_val(pmd) & _PAGE_WRITE); -} - static inline pmd_t pmd_wrprotect(pmd_t pmd) { pmd_val(pmd) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); @@ -677,19 +689,6 @@ static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) /* Extern to avoid header file madness */ extern pmd_t mk_pmd(struct page *page, pgprot_t prot); -static inline unsigned long pmd_pfn(pmd_t pmd) -{ - return pmd_val(pmd) >> _PFN_SHIFT; -} - -static inline struct page *pmd_page(pmd_t pmd) -{ - if (pmd_trans_huge(pmd)) - return pfn_to_page(pmd_pfn(pmd)); - - return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT); -} - static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) { pmd_val(pmd) = (pmd_val(pmd) & (_PAGE_CHG_MASK | _PAGE_HUGE)) | diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 0c3550c82b72..4bb24579d12e 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -207,16 +207,6 @@ struct octeon_cvmseg_state { [cpu_dcache_line_size() / sizeof(unsigned long)]; }; -#elif defined(CONFIG_CPU_XLP) -struct nlm_cop2_state { - u64 rx[4]; - u64 tx[4]; - u32 tx_msg_status; - u32 rx_msg_status; -}; - -#define COP2_INIT \ - .cp2 = {{0}, {0}, 0, 0}, #else #define COP2_INIT #endif @@ -275,9 +265,6 @@ struct thread_struct { struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); #endif -#ifdef CONFIG_CPU_XLP - struct nlm_cop2_state cp2; -#endif struct mips_abi *abi; }; @@ -369,7 +356,7 @@ static inline void flush_thread(void) { } -unsigned long get_wchan(struct task_struct *p); +unsigned long __get_wchan(struct task_struct *p); #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \ THREAD_SIZE - 32 - sizeof(struct pt_regs)) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index f7effca791a5..296bcf31abb5 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -145,6 +145,7 @@ Ip_u1(_mtlo); Ip_u3u1u2(_mul); Ip_u1u2(_multu); Ip_u3u1u2(_mulu); +Ip_u3u1u2(_muhu); Ip_u3u1u2(_nor); Ip_u3u1u2(_or); Ip_u2u1u3(_ori); @@ -248,7 +249,11 @@ static inline void uasm_l##lb(struct uasm_label **lab, u32 *addr) \ #define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off) #define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3) #define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b) +#ifdef CONFIG_CPU_NOP_WORKAROUNDS +#define uasm_i_nop(buf) uasm_i_or(buf, 1, 1, 0) +#else #define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0) +#endif #define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1) static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1, diff --git a/arch/mips/include/asm/vermagic.h b/arch/mips/include/asm/vermagic.h index 371c1873df0d..0904de0b5e09 100644 --- a/arch/mips/include/asm/vermagic.h +++ b/arch/mips/include/asm/vermagic.h @@ -54,10 +54,6 @@ #define MODULE_PROC_FAMILY "OCTEON " #elif defined CONFIG_CPU_P5600 #define MODULE_PROC_FAMILY "P5600 " -#elif defined CONFIG_CPU_XLR -#define MODULE_PROC_FAMILY "XLR " -#elif defined CONFIG_CPU_XLP -#define MODULE_PROC_FAMILY "XLP " #else #error MODULE_PROC_FAMILY undefined for your processor configuration #endif diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h index 1eaf6a1ca561..24e0efb360f6 100644 --- a/arch/mips/include/uapi/asm/socket.h +++ b/arch/mips/include/uapi/asm/socket.h @@ -142,6 +142,8 @@ #define SO_BUF_LOCK 72 +#define SO_RESERVE_MEM 73 + #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 630fcb4cb30e..ac0e2cfc6d57 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1886,87 +1886,6 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) } } -static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) -{ - decode_configs(c); - - if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { - c->cputype = CPU_ALCHEMY; - __cpu_name[cpu] = "Au1300"; - /* following stuff is not for Alchemy */ - return; - } - - c->options = (MIPS_CPU_TLB | - MIPS_CPU_4KEX | - MIPS_CPU_COUNTER | - MIPS_CPU_DIVEC | - MIPS_CPU_WATCH | - MIPS_CPU_EJTAG | - MIPS_CPU_LLSC); - - switch (c->processor_id & PRID_IMP_MASK) { - case PRID_IMP_NETLOGIC_XLP2XX: - case PRID_IMP_NETLOGIC_XLP9XX: - case PRID_IMP_NETLOGIC_XLP5XX: - c->cputype = CPU_XLP; - __cpu_name[cpu] = "Broadcom XLPII"; - break; - - case PRID_IMP_NETLOGIC_XLP8XX: - case PRID_IMP_NETLOGIC_XLP3XX: - c->cputype = CPU_XLP; - __cpu_name[cpu] = "Netlogic XLP"; - break; - - case PRID_IMP_NETLOGIC_XLR732: - case PRID_IMP_NETLOGIC_XLR716: - case PRID_IMP_NETLOGIC_XLR532: - case PRID_IMP_NETLOGIC_XLR308: - case PRID_IMP_NETLOGIC_XLR532C: - case PRID_IMP_NETLOGIC_XLR516C: - case PRID_IMP_NETLOGIC_XLR508C: - case PRID_IMP_NETLOGIC_XLR308C: - c->cputype = CPU_XLR; - __cpu_name[cpu] = "Netlogic XLR"; - break; - - case PRID_IMP_NETLOGIC_XLS608: - case PRID_IMP_NETLOGIC_XLS408: - case PRID_IMP_NETLOGIC_XLS404: - case PRID_IMP_NETLOGIC_XLS208: - case PRID_IMP_NETLOGIC_XLS204: - case PRID_IMP_NETLOGIC_XLS108: - case PRID_IMP_NETLOGIC_XLS104: - case PRID_IMP_NETLOGIC_XLS616B: - case PRID_IMP_NETLOGIC_XLS608B: - case PRID_IMP_NETLOGIC_XLS416B: - case PRID_IMP_NETLOGIC_XLS412B: - case PRID_IMP_NETLOGIC_XLS408B: - case PRID_IMP_NETLOGIC_XLS404B: - c->cputype = CPU_XLR; - __cpu_name[cpu] = "Netlogic XLS"; - break; - - default: - pr_info("Unknown Netlogic chip id [%02x]!\n", - c->processor_id); - c->cputype = CPU_XLR; - break; - } - - if (c->cputype == CPU_XLP) { - set_isa(c, MIPS_CPU_ISA_M64R2); - c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); - /* This will be updated again after all threads are woken up */ - c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; - } else { - set_isa(c, MIPS_CPU_ISA_M64R1); - c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; - } - c->kscratch_mask = 0xf; -} - #ifdef CONFIG_64BIT /* For use by uaccess.h */ u64 __ua_limit; @@ -2031,9 +1950,6 @@ void cpu_probe(void) case PRID_COMP_INGENIC_E1: cpu_probe_ingenic(c, cpu); break; - case PRID_COMP_NETLOGIC: - cpu_probe_netlogic(c, cpu); - break; } BUG_ON(!__cpu_name[cpu]); diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 1aca3b4db904..c81b3a039470 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -175,8 +175,6 @@ void __init check_wait(void) case CPU_CAVIUM_OCTEON3: case CPU_XBURST: case CPU_LOONGSON32: - case CPU_XLR: - case CPU_XLP: cpu_wait = r4k_wait; break; case CPU_LOONGSON64: diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index d20e002b3246..5e11582fe308 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -111,15 +111,9 @@ void __irq_entry do_IRQ(unsigned int irq) #ifdef CONFIG_IRQ_DOMAIN void __irq_entry do_domain_IRQ(struct irq_domain *domain, unsigned int hwirq) { - struct irq_desc *desc; - irq_enter(); check_stack_overflow(); - - desc = irq_resolve_mapping(domain, hwirq); - if (likely(desc)) - handle_irq_desc(desc); - + generic_handle_domain_irq(domain, hwirq); irq_exit(); } #endif diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c index 75bff0f77319..6c7f3b143fdc 100644 --- a/arch/mips/kernel/kprobes.c +++ b/arch/mips/kernel/kprobes.c @@ -11,6 +11,8 @@ * Copyright (C) IBM Corporation, 2002, 2004 */ +#define pr_fmt(fmt) "kprobes: " fmt + #include <linux/kprobes.h> #include <linux/preempt.h> #include <linux/uaccess.h> @@ -80,8 +82,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p) insn = p->addr[0]; if (insn_has_ll_or_sc(insn)) { - pr_notice("Kprobes for ll and sc instructions are not" - "supported\n"); + pr_notice("Kprobes for ll and sc instructions are not supported\n"); ret = -EINVAL; goto out; } @@ -219,7 +220,7 @@ static int evaluate_branch_instruction(struct kprobe *p, struct pt_regs *regs, return 0; unaligned: - pr_notice("%s: unaligned epc - sending SIGBUS.\n", current->comm); + pr_notice("Failed to emulate branch instruction because of unaligned epc - sending SIGBUS to %s.\n", current->comm); force_sig(SIGBUS); return -EFAULT; @@ -238,10 +239,8 @@ static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs, regs->cp0_epc = (unsigned long)p->addr; else if (insn_has_delayslot(p->opcode)) { ret = evaluate_branch_instruction(p, regs, kcb); - if (ret < 0) { - pr_notice("Kprobes: Error in evaluating branch\n"); + if (ret < 0) return; - } } regs->cp0_epc = (unsigned long)&p->ainsn.insn[0]; } @@ -461,14 +460,14 @@ static void __used kretprobe_trampoline_holder(void) /* Keep the assembler from reordering and placing JR here. */ ".set noreorder\n\t" "nop\n\t" - ".global kretprobe_trampoline\n" - "kretprobe_trampoline:\n\t" + ".global __kretprobe_trampoline\n" + "__kretprobe_trampoline:\n\t" "nop\n\t" ".set pop" : : : "memory"); } -void kretprobe_trampoline(void); +void __kretprobe_trampoline(void); void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri, struct pt_regs *regs) @@ -477,7 +476,7 @@ void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri, ri->fp = NULL; /* Replace the return addr with trampoline addr */ - regs->regs[31] = (unsigned long)kretprobe_trampoline; + regs->regs[31] = (unsigned long)__kretprobe_trampoline; } /* @@ -486,8 +485,7 @@ void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri, static int __kprobes trampoline_probe_handler(struct kprobe *p, struct pt_regs *regs) { - instruction_pointer(regs) = __kretprobe_trampoline_handler(regs, - kretprobe_trampoline, NULL); + instruction_pointer(regs) = __kretprobe_trampoline_handler(regs, NULL); /* * By returning a non-zero value, we are telling * kprobe_handler() that we don't want the post_handler @@ -498,14 +496,14 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p, int __kprobes arch_trampoline_kprobe(struct kprobe *p) { - if (p->addr == (kprobe_opcode_t *)kretprobe_trampoline) + if (p->addr == (kprobe_opcode_t *)__kretprobe_trampoline) return 1; return 0; } static struct kprobe trampoline_p = { - .addr = (kprobe_opcode_t *)kretprobe_trampoline, + .addr = (kprobe_opcode_t *)__kretprobe_trampoline, .pre_handler = trampoline_probe_handler }; diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 90f1c3df1f0e..b4f7d950c846 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -221,8 +221,7 @@ static void mips_cm_probe_l2sync(void) phys_addr_t addr; /* L2-only sync was introduced with CM major revision 6 */ - major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR) >> - __ffs(CM_GCR_REV_MAJOR); + major_rev = FIELD_GET(CM_GCR_REV_MAJOR, read_gcr_rev()); if (major_rev < 6) return; @@ -306,13 +305,13 @@ void mips_cm_lock_other(unsigned int cluster, unsigned int core, preempt_disable(); if (cm_rev >= CM_REV_CM3) { - val = core << __ffs(CM3_GCR_Cx_OTHER_CORE); - val |= vp << __ffs(CM3_GCR_Cx_OTHER_VP); + val = FIELD_PREP(CM3_GCR_Cx_OTHER_CORE, core) | + FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp); if (cm_rev >= CM_REV_CM3_5) { val |= CM_GCR_Cx_OTHER_CLUSTER_EN; - val |= cluster << __ffs(CM_GCR_Cx_OTHER_CLUSTER); - val |= block << __ffs(CM_GCR_Cx_OTHER_BLOCK); + val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster); + val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block); } else { WARN_ON(cluster != 0); WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL); @@ -342,7 +341,7 @@ void mips_cm_lock_other(unsigned int cluster, unsigned int core, spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core), per_cpu(cm_core_lock_flags, curr_core)); - val = core << __ffs(CM_GCR_Cx_OTHER_CORENUM); + val = FIELD_PREP(CM_GCR_Cx_OTHER_CORENUM, core); } write_gcr_cl_other(val); @@ -386,8 +385,8 @@ void mips_cm_error_report(void) cm_other = read_gcr_error_mult(); if (revision < CM_REV_CM3) { /* CM2 */ - cause = cm_error >> __ffs(CM_GCR_ERROR_CAUSE_ERRTYPE); - ocause = cm_other >> __ffs(CM_GCR_ERROR_MULT_ERR2ND); + cause = FIELD_GET(CM_GCR_ERROR_CAUSE_ERRTYPE, cm_error); + ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other); if (!cause) return; @@ -445,8 +444,8 @@ void mips_cm_error_report(void) ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits; ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit; - cause = cm_error >> __ffs64(CM3_GCR_ERROR_CAUSE_ERRTYPE); - ocause = cm_other >> __ffs(CM_GCR_ERROR_MULT_ERR2ND); + cause = FIELD_GET(CM3_GCR_ERROR_CAUSE_ERRTYPE, cm_error); + ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other); if (!cause) return; diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 22e22c2de1c9..1641d274fe37 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -1002,15 +1002,6 @@ static const struct mips_perf_event bmips5000_event_map [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, }; -static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = { - [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, - [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */ - [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ - [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */ - [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */ -}; - /* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */ static const struct mips_perf_event mipsxxcore_cache_map [PERF_COUNT_HW_CACHE_MAX] @@ -1477,63 +1468,6 @@ static const struct mips_perf_event octeon_cache_map }, }; -static const struct mips_perf_event xlp_cache_map - [PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { -[C(L1D)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */ - [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */ - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */ - [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */ - }, -}, -[C(L1I)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ - [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ - }, -}, -[C(LL)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */ - [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */ - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */ - [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */ - }, -}, -[C(DTLB)] = { - /* - * Only general DTLB misses are counted use the same event for - * read and write. - */ - [C(OP_READ)] = { - [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ - }, - [C(OP_WRITE)] = { - [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ - }, -}, -[C(ITLB)] = { - [C(OP_READ)] = { - [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ - }, - [C(OP_WRITE)] = { - [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ - }, -}, -[C(BPU)] = { - [C(OP_READ)] = { - [C(RESULT_MISS)] = { 0x25, CNTR_ALL }, - }, -}, -}; - static int __hw_perf_event_init(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; @@ -1953,20 +1887,6 @@ static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) return &raw_event; } -static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config) -{ - unsigned int raw_id = config & 0xff; - - /* Only 1-63 are defined */ - if ((raw_id < 0x01) || (raw_id > 0x3f)) - return ERR_PTR(-EOPNOTSUPP); - - raw_event.cntr_mask = CNTR_ALL; - raw_event.event_id = raw_id; - - return &raw_event; -} - static int __init init_hw_perf_events(void) { @@ -2091,12 +2011,6 @@ init_hw_perf_events(void) mipspmu.general_event_map = &bmips5000_event_map; mipspmu.cache_event_map = &bmips5000_cache_map; break; - case CPU_XLP: - mipspmu.name = "xlp"; - mipspmu.general_event_map = &xlp_event_map; - mipspmu.cache_event_map = &xlp_cache_map; - mipspmu.map_raw_event = xlp_pmu_map_raw_event; - break; default: pr_cont("Either hardware does not support performance " "counters, or not yet implemented.\n"); diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 4184d641f05e..376a6e2676e9 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -19,8 +19,8 @@ unsigned int vced_count, vcei_count; /* - * * No lock; only written during early bootup by CPU 0. - * */ + * No lock; only written during early bootup by CPU 0. + */ static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain); int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb) @@ -39,7 +39,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) unsigned long n = (unsigned long) v - 1; unsigned int version = cpu_data[n].processor_id; unsigned int fp_vers = cpu_data[n].fpu_id; - char fmt [64]; + char fmt[64]; int i; #ifdef CONFIG_SMP @@ -78,66 +78,207 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "count: %d, address/irw mask: [", cpu_data[n].watch_reg_count); for (i = 0; i < cpu_data[n].watch_reg_count; i++) - seq_printf(m, "%s0x%04x", i ? ", " : "" , + seq_printf(m, "%s0x%04x", i ? ", " : "", cpu_data[n].watch_reg_masks[i]); - seq_printf(m, "]\n"); + seq_puts(m, "]\n"); } - seq_printf(m, "isa\t\t\t:"); + seq_puts(m, "isa\t\t\t:"); if (cpu_has_mips_1) - seq_printf(m, " mips1"); + seq_puts(m, " mips1"); if (cpu_has_mips_2) - seq_printf(m, "%s", " mips2"); + seq_puts(m, " mips2"); if (cpu_has_mips_3) - seq_printf(m, "%s", " mips3"); + seq_puts(m, " mips3"); if (cpu_has_mips_4) - seq_printf(m, "%s", " mips4"); + seq_puts(m, " mips4"); if (cpu_has_mips_5) - seq_printf(m, "%s", " mips5"); + seq_puts(m, " mips5"); if (cpu_has_mips32r1) - seq_printf(m, "%s", " mips32r1"); + seq_puts(m, " mips32r1"); if (cpu_has_mips32r2) - seq_printf(m, "%s", " mips32r2"); + seq_puts(m, " mips32r2"); if (cpu_has_mips32r5) - seq_printf(m, "%s", " mips32r5"); + seq_puts(m, " mips32r5"); if (cpu_has_mips32r6) - seq_printf(m, "%s", " mips32r6"); + seq_puts(m, " mips32r6"); if (cpu_has_mips64r1) - seq_printf(m, "%s", " mips64r1"); + seq_puts(m, " mips64r1"); if (cpu_has_mips64r2) - seq_printf(m, "%s", " mips64r2"); + seq_puts(m, " mips64r2"); if (cpu_has_mips64r5) - seq_printf(m, "%s", " mips64r5"); + seq_puts(m, " mips64r5"); if (cpu_has_mips64r6) - seq_printf(m, "%s", " mips64r6"); - seq_printf(m, "\n"); - - seq_printf(m, "ASEs implemented\t:"); - if (cpu_has_mips16) seq_printf(m, "%s", " mips16"); - if (cpu_has_mips16e2) seq_printf(m, "%s", " mips16e2"); - if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx"); - if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d"); - if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips"); - if (cpu_has_dsp) seq_printf(m, "%s", " dsp"); - if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); - if (cpu_has_dsp3) seq_printf(m, "%s", " dsp3"); - if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); - if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); - if (cpu_has_vz) seq_printf(m, "%s", " vz"); - if (cpu_has_msa) seq_printf(m, "%s", " msa"); - if (cpu_has_eva) seq_printf(m, "%s", " eva"); - if (cpu_has_htw) seq_printf(m, "%s", " htw"); - if (cpu_has_xpa) seq_printf(m, "%s", " xpa"); - if (cpu_has_loongson_mmi) seq_printf(m, "%s", " loongson-mmi"); - if (cpu_has_loongson_cam) seq_printf(m, "%s", " loongson-cam"); - if (cpu_has_loongson_ext) seq_printf(m, "%s", " loongson-ext"); - if (cpu_has_loongson_ext2) seq_printf(m, "%s", " loongson-ext2"); - seq_printf(m, "\n"); + seq_puts(m, " mips64r6"); + seq_puts(m, "\n"); + + seq_puts(m, "ASEs implemented\t:"); + if (cpu_has_mips16) + seq_puts(m, " mips16"); + if (cpu_has_mips16e2) + seq_puts(m, " mips16e2"); + if (cpu_has_mdmx) + seq_puts(m, " mdmx"); + if (cpu_has_mips3d) + seq_puts(m, " mips3d"); + if (cpu_has_smartmips) + seq_puts(m, " smartmips"); + if (cpu_has_dsp) + seq_puts(m, " dsp"); + if (cpu_has_dsp2) + seq_puts(m, " dsp2"); + if (cpu_has_dsp3) + seq_puts(m, " dsp3"); + if (cpu_has_mipsmt) + seq_puts(m, " mt"); + if (cpu_has_mmips) + seq_puts(m, " micromips"); + if (cpu_has_vz) + seq_puts(m, " vz"); + if (cpu_has_msa) + seq_puts(m, " msa"); + if (cpu_has_eva) + seq_puts(m, " eva"); + if (cpu_has_htw) + seq_puts(m, " htw"); + if (cpu_has_xpa) + seq_puts(m, " xpa"); + if (cpu_has_loongson_mmi) + seq_puts(m, " loongson-mmi"); + if (cpu_has_loongson_cam) + seq_puts(m, " loongson-cam"); + if (cpu_has_loongson_ext) + seq_puts(m, " loongson-ext"); + if (cpu_has_loongson_ext2) + seq_puts(m, " loongson-ext2"); + seq_puts(m, "\n"); if (cpu_has_mmips) { seq_printf(m, "micromips kernel\t: %s\n", (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); } + + seq_puts(m, "Options implemented\t:"); + if (cpu_has_tlb) + seq_puts(m, " tlb"); + if (cpu_has_ftlb) + seq_puts(m, " ftlb"); + if (cpu_has_tlbinv) + seq_puts(m, " tlbinv"); + if (cpu_has_segments) + seq_puts(m, " segments"); + if (cpu_has_rixiex) + seq_puts(m, " rixiex"); + if (cpu_has_ldpte) + seq_puts(m, " ldpte"); + if (cpu_has_maar) + seq_puts(m, " maar"); + if (cpu_has_rw_llb) + seq_puts(m, " rw_llb"); + if (cpu_has_4kex) + seq_puts(m, " 4kex"); + if (cpu_has_3k_cache) + seq_puts(m, " 3k_cache"); + if (cpu_has_4k_cache) + seq_puts(m, " 4k_cache"); + if (cpu_has_tx39_cache) + seq_puts(m, " tx39_cache"); + if (cpu_has_octeon_cache) + seq_puts(m, " octeon_cache"); + if (cpu_has_fpu) + seq_puts(m, " fpu"); + if (cpu_has_32fpr) + seq_puts(m, " 32fpr"); + if (cpu_has_cache_cdex_p) + seq_puts(m, " cache_cdex_p"); + if (cpu_has_cache_cdex_s) + seq_puts(m, " cache_cdex_s"); + if (cpu_has_prefetch) + seq_puts(m, " prefetch"); + if (cpu_has_mcheck) + seq_puts(m, " mcheck"); + if (cpu_has_ejtag) + seq_puts(m, " ejtag"); + if (cpu_has_llsc) + seq_puts(m, " llsc"); + if (cpu_has_guestctl0ext) + seq_puts(m, " guestctl0ext"); + if (cpu_has_guestctl1) + seq_puts(m, " guestctl1"); + if (cpu_has_guestctl2) + seq_puts(m, " guestctl2"); + if (cpu_has_guestid) + seq_puts(m, " guestid"); + if (cpu_has_drg) + seq_puts(m, " drg"); + if (cpu_has_rixi) + seq_puts(m, " rixi"); + if (cpu_has_lpa) + seq_puts(m, " lpa"); + if (cpu_has_mvh) + seq_puts(m, " mvh"); + if (cpu_has_vtag_icache) + seq_puts(m, " vtag_icache"); + if (cpu_has_dc_aliases) + seq_puts(m, " dc_aliases"); + if (cpu_has_ic_fills_f_dc) + seq_puts(m, " ic_fills_f_dc"); + if (cpu_has_pindexed_dcache) + seq_puts(m, " pindexed_dcache"); + if (cpu_has_userlocal) + seq_puts(m, " userlocal"); + if (cpu_has_nofpuex) + seq_puts(m, " nofpuex"); + if (cpu_has_vint) + seq_puts(m, " vint"); + if (cpu_has_veic) + seq_puts(m, " veic"); + if (cpu_has_inclusive_pcaches) + seq_puts(m, " inclusive_pcaches"); + if (cpu_has_perf_cntr_intr_bit) + seq_puts(m, " perf_cntr_intr_bit"); + if (cpu_has_ufr) + seq_puts(m, " ufr"); + if (cpu_has_fre) + seq_puts(m, " fre"); + if (cpu_has_cdmm) + seq_puts(m, " cdmm"); + if (cpu_has_small_pages) + seq_puts(m, " small_pages"); + if (cpu_has_nan_legacy) + seq_puts(m, " nan_legacy"); + if (cpu_has_nan_2008) + seq_puts(m, " nan_2008"); + if (cpu_has_ebase_wg) + seq_puts(m, " ebase_wg"); + if (cpu_has_badinstr) + seq_puts(m, " badinstr"); + if (cpu_has_badinstrp) + seq_puts(m, " badinstrp"); + if (cpu_has_contextconfig) + seq_puts(m, " contextconfig"); + if (cpu_has_perf) + seq_puts(m, " perf"); + if (cpu_has_mac2008_only) + seq_puts(m, " mac2008_only"); + if (cpu_has_ftlbparex) + seq_puts(m, " ftlbparex"); + if (cpu_has_gsexcex) + seq_puts(m, " gsexcex"); + if (cpu_has_shared_ftlb_ram) + seq_puts(m, " shared_ftlb_ram"); + if (cpu_has_shared_ftlb_entries) + seq_puts(m, " shared_ftlb_entries"); + if (cpu_has_mipsmt_pertccounters) + seq_puts(m, " mipsmt_pertccounters"); + if (cpu_has_mmid) + seq_puts(m, " mmid"); + if (cpu_has_mm_sysad) + seq_puts(m, " mm_sysad"); + if (cpu_has_mm_full) + seq_puts(m, " mm_full"); + seq_puts(m, "\n"); + seq_printf(m, "shadow register sets\t: %d\n", cpu_data[n].srsets); seq_printf(m, "kscratch registers\t: %d\n", @@ -163,7 +304,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) raw_notifier_call_chain(&proc_cpuinfo_chain, 0, &proc_cpuinfo_notifier_args); - seq_printf(m, "\n"); + seq_puts(m, "\n"); return 0; } diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index 95aa86fa6077..cbff1b974f88 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -511,7 +511,7 @@ static int __init frame_info_init(void) /* * Without schedule() frame info, result given by - * thread_saved_pc() and get_wchan() are not reliable. + * thread_saved_pc() and __get_wchan() are not reliable. */ if (schedule_mfi.pc_offset < 0) printk("Can't analyze schedule() prologue at %p\n", schedule); @@ -652,9 +652,9 @@ unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, #endif /* - * get_wchan - a maintenance nightmare^W^Wpain in the ass ... + * __get_wchan - a maintenance nightmare^W^Wpain in the ass ... */ -unsigned long get_wchan(struct task_struct *task) +unsigned long __get_wchan(struct task_struct *task) { unsigned long pc = 0; #ifdef CONFIG_KALLSYMS @@ -662,8 +662,6 @@ unsigned long get_wchan(struct task_struct *task) unsigned long ra = 0; #endif - if (!task || task == current || task_is_running(task)) - goto out; if (!task_stack_page(task)) goto out; diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index f1e985109da0..c9b2a75563e1 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -906,10 +906,8 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused, if (thread_info_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL)) do_signal(regs); - if (thread_info_flags & _TIF_NOTIFY_RESUME) { + if (thread_info_flags & _TIF_NOTIFY_RESUME) tracehook_notify_resume(regs); - rseq_handle_notify_resume(NULL, regs); - } user_enter(); } diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index b6ef5f7312cf..f5d7bfa3472a 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -26,6 +26,7 @@ #include <linux/bug.h> #include <linux/kernel.h> #include <linux/kexec.h> +#include <linux/irq.h> #include <asm/time.h> #include <asm/processor.h> @@ -373,7 +374,7 @@ static int bmips_cpu_disable(void) set_cpu_online(cpu, false); calculate_cpu_foreign_map(); - irq_cpu_offline(); + irq_migrate_all_off_this_cpu(); clear_c0_status(IE_IRQ5); local_flush_tlb_all(); diff --git a/arch/mips/kernel/uprobes.c b/arch/mips/kernel/uprobes.c index 9db2a6db5f62..6c063aa188e6 100644 --- a/arch/mips/kernel/uprobes.c +++ b/arch/mips/kernel/uprobes.c @@ -173,6 +173,7 @@ int arch_uprobe_exception_notify(struct notifier_block *self, case DIE_UPROBE_XOL: if (uprobe_post_sstep_notifier(regs)) return NOTIFY_STOP; + break; default: break; } diff --git a/arch/mips/kvm/entry.c b/arch/mips/kvm/entry.c index 8131fb2bdf97..aceed14aa1f7 100644 --- a/arch/mips/kvm/entry.c +++ b/arch/mips/kvm/entry.c @@ -104,13 +104,7 @@ static void *kvm_mips_build_ret_to_host(void *addr); */ static int c0_kscratch(void) { - switch (boot_cpu_type()) { - case CPU_XLP: - case CPU_XLR: - return 22; - default: - return 31; - } + return 31; } /** diff --git a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c index 75c6f264c626..562aa878b266 100644 --- a/arch/mips/kvm/mips.c +++ b/arch/mips/kvm/mips.c @@ -1073,7 +1073,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) r = KVM_MAX_VCPUS; break; case KVM_CAP_MAX_VCPU_ID: - r = KVM_MAX_VCPU_ID; + r = KVM_MAX_VCPU_IDS; break; case KVM_CAP_MIPS_FPU: /* We don't handle systems with inconsistent cpu_has_fpu */ diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index 63dccb2ed08b..f8eedeb15f18 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -11,6 +11,7 @@ #include <linux/export.h> #include <linux/spinlock.h> #include <linux/clk.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/of.h> @@ -30,6 +31,7 @@ #define LTQ_DMA_PCTRL 0x44 #define LTQ_DMA_IRNEN 0xf4 +#define DMA_ID_CHNR GENMASK(26, 20) /* channel number */ #define DMA_DESCPT BIT(3) /* descriptor complete irq */ #define DMA_TX BIT(8) /* TX channel direction */ #define DMA_CHAN_ON BIT(0) /* channel on / off bit */ @@ -39,8 +41,11 @@ #define DMA_IRQ_ACK 0x7e /* IRQ status register */ #define DMA_POLL BIT(31) /* turn on channel polling */ #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ -#define DMA_2W_BURST BIT(1) /* 2 word burst length */ -#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ +#define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */ +#define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */ +#define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */ +#define DMA_TX_BURST_SHIFT 4 /* tx burst shift */ +#define DMA_RX_BURST_SHIFT 2 /* rx burst shift */ #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ @@ -177,7 +182,7 @@ ltq_dma_free(struct ltq_dma_channel *ch) EXPORT_SYMBOL_GPL(ltq_dma_free); void -ltq_dma_init_port(int p) +ltq_dma_init_port(int p, int tx_burst, int rx_burst) { ltq_dma_w32(p, LTQ_DMA_PS); switch (p) { @@ -186,15 +191,44 @@ ltq_dma_init_port(int p) * Tell the DMA engine to swap the endianness of data frames and * drop packets if the channel arbitration fails. */ - ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, + ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN), LTQ_DMA_PCTRL); break; - case DMA_PORT_DEU: - ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2), + default: + break; + } + + switch (rx_burst) { + case 8: + ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT), + LTQ_DMA_PCTRL); + break; + case 4: + ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT), + LTQ_DMA_PCTRL); + break; + case 2: + ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT), LTQ_DMA_PCTRL); break; + default: + break; + } + switch (tx_burst) { + case 8: + ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT), + LTQ_DMA_PCTRL); + break; + case 4: + ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT), + LTQ_DMA_PCTRL); + break; + case 2: + ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT), + LTQ_DMA_PCTRL); + break; default: break; } @@ -206,7 +240,7 @@ ltq_dma_init(struct platform_device *pdev) { struct clk *clk; struct resource *res; - unsigned id; + unsigned int id, nchannels; int i; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -222,21 +256,24 @@ ltq_dma_init(struct platform_device *pdev) clk_enable(clk); ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); + usleep_range(1, 10); + /* disable all interrupts */ ltq_dma_w32(0, LTQ_DMA_IRNEN); /* reset/configure each channel */ - for (i = 0; i < DMA_MAX_CHANNEL; i++) { + id = ltq_dma_r32(LTQ_DMA_ID); + nchannels = ((id & DMA_ID_CHNR) >> 20); + for (i = 0; i < nchannels; i++) { ltq_dma_w32(i, LTQ_DMA_CS); ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL); ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); } - id = ltq_dma_r32(LTQ_DMA_ID); dev_info(&pdev->dev, "Init done - hw rev: %X, ports: %d, channels: %d\n", - id & 0x1f, (id >> 16) & 0xf, id >> 20); + id & 0x1f, (id >> 16) & 0xf, nchannels); return 0; } diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c index 76e0a9636a0e..ee8de1735b7c 100644 --- a/arch/mips/loongson64/init.c +++ b/arch/mips/loongson64/init.c @@ -77,7 +77,9 @@ void __init szmem(unsigned int node) (u32)node_id, mem_type, mem_start, mem_size); pr_info(" start_pfn:0x%llx, end_pfn:0x%llx, num_physpages:0x%lx\n", start_pfn, end_pfn, num_physpages); - memblock_add_node(PFN_PHYS(start_pfn), PFN_PHYS(node_psize), node); + memblock_add_node(PFN_PHYS(start_pfn), + PFN_PHYS(node_psize), node, + MEMBLOCK_NONE); break; case SYSTEM_RAM_RESERVED: pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n", @@ -177,6 +179,7 @@ static __init void reserve_pio_range(void) if (of_range_parser_init(&parser, np)) { pr_info("Failed to parse resources.\n"); + of_node_put(np); break; } diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 09ebe84a17fe..660e1de4412a 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -550,7 +550,6 @@ static int loongson3_cpu_disable(void) set_cpu_online(cpu, false); calculate_cpu_foreign_map(); local_irq_save(flags); - irq_cpu_offline(); clear_c0_status(ST0_IM); local_irq_restore(flags); local_flush_tlb_all(); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 74b09e801c3a..50261fd8eb21 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1410,7 +1410,6 @@ static void probe_pcache(void) case CPU_I6500: case CPU_SB1: case CPU_SB1A: - case CPU_XLR: c->dcache.flags |= MIPS_CACHE_PINDEX; break; @@ -1699,7 +1698,6 @@ static void setup_scache(void) return; case CPU_CAVIUM_OCTEON3: - case CPU_XLP: /* don't need to worry about L2, fully coherent */ return; diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 19347dc6bbf8..325e1552cbea 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -529,7 +529,7 @@ static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, static void __init pcpu_fc_free(void *ptr, size_t size) { - memblock_free_early(__pa(ptr), size); + memblock_free(ptr, size); } void __init setup_per_cpu_areas(void) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 9adad24c2e65..b131e6a77383 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -325,13 +325,7 @@ static unsigned int kscratch_used_mask; static inline int __maybe_unused c0_kscratch(void) { - switch (current_cpu_type()) { - case CPU_XLP: - case CPU_XLR: - return 22; - default: - return 31; - } + return 31; } static int allocate_kscratch(void) @@ -553,7 +547,6 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: - case CPU_XLR: uasm_i_nop(p); tlbw(p); break; diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c index 7154a1d99aad..e15c6700cd08 100644 --- a/arch/mips/mm/uasm-mips.c +++ b/arch/mips/mm/uasm-mips.c @@ -90,7 +90,7 @@ static const struct insn insn_table[insn_invalid] = { RS | RT | RD}, [insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, [insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT}, - [insn_dmulu] = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op), + [insn_dmulu] = {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op), RS | RT | RD}, [insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE}, [insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE}, @@ -150,6 +150,8 @@ static const struct insn insn_table[insn_invalid] = { [insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS}, [insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op), RS | RT | RD}, + [insn_muhu] = {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op), + RS | RT | RD}, #ifndef CONFIG_CPU_MIPSR6 [insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, #else diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 81dd226d6b6b..125140979d62 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -59,7 +59,7 @@ enum opcode { insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0, - insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor, + insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc, insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll, insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, @@ -344,6 +344,7 @@ I_u1(_mtlo) I_u3u1u2(_mul) I_u1u2(_multu) I_u3u1u2(_mulu) +I_u3u1u2(_muhu) I_u3u1u2(_nor) I_u3u1u2(_or) I_u2u1u3(_ori) diff --git a/arch/mips/net/Makefile b/arch/mips/net/Makefile index d55912349039..e3e6ae6514e8 100644 --- a/arch/mips/net/Makefile +++ b/arch/mips/net/Makefile @@ -1,5 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only # MIPS networking code -obj-$(CONFIG_MIPS_CBPF_JIT) += bpf_jit.o bpf_jit_asm.o -obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o +obj-$(CONFIG_BPF_JIT) += bpf_jit_comp.o + +ifeq ($(CONFIG_32BIT),y) + obj-$(CONFIG_BPF_JIT) += bpf_jit_comp32.o +else + obj-$(CONFIG_BPF_JIT) += bpf_jit_comp64.o +endif diff --git a/arch/mips/net/bpf_jit.c b/arch/mips/net/bpf_jit.c deleted file mode 100644 index 0af88622c619..000000000000 --- a/arch/mips/net/bpf_jit.c +++ /dev/null @@ -1,1270 +0,0 @@ -/* - * Just-In-Time compiler for BPF filters on MIPS - * - * Copyright (c) 2014 Imagination Technologies Ltd. - * Author: Markos Chandras <markos.chandras@imgtec.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; version 2 of the License. - */ - -#include <linux/bitops.h> -#include <linux/compiler.h> -#include <linux/errno.h> -#include <linux/filter.h> -#include <linux/if_vlan.h> -#include <linux/moduleloader.h> -#include <linux/netdevice.h> -#include <linux/string.h> -#include <linux/slab.h> -#include <linux/types.h> -#include <asm/asm.h> -#include <asm/bitops.h> -#include <asm/cacheflush.h> -#include <asm/cpu-features.h> -#include <asm/uasm.h> - -#include "bpf_jit.h" - -/* ABI - * r_skb_hl SKB header length - * r_data SKB data pointer - * r_off Offset - * r_A BPF register A - * r_X BPF register X - * r_skb *skb - * r_M *scratch memory - * r_skb_len SKB length - * - * On entry (*bpf_func)(*skb, *filter) - * a0 = MIPS_R_A0 = skb; - * a1 = MIPS_R_A1 = filter; - * - * Stack - * ... - * M[15] - * M[14] - * M[13] - * ... - * M[0] <-- r_M - * saved reg k-1 - * saved reg k-2 - * ... - * saved reg 0 <-- r_sp - * <no argument area> - * - * Packet layout - * - * <--------------------- len ------------------------> - * <--skb-len(r_skb_hl)-->< ----- skb->data_len ------> - * ---------------------------------------------------- - * | skb->data | - * ---------------------------------------------------- - */ - -#define ptr typeof(unsigned long) - -#define SCRATCH_OFF(k) (4 * (k)) - -/* JIT flags */ -#define SEEN_CALL (1 << BPF_MEMWORDS) -#define SEEN_SREG_SFT (BPF_MEMWORDS + 1) -#define SEEN_SREG_BASE (1 << SEEN_SREG_SFT) -#define SEEN_SREG(x) (SEEN_SREG_BASE << (x)) -#define SEEN_OFF SEEN_SREG(2) -#define SEEN_A SEEN_SREG(3) -#define SEEN_X SEEN_SREG(4) -#define SEEN_SKB SEEN_SREG(5) -#define SEEN_MEM SEEN_SREG(6) -/* SEEN_SK_DATA also implies skb_hl an skb_len */ -#define SEEN_SKB_DATA (SEEN_SREG(7) | SEEN_SREG(1) | SEEN_SREG(0)) - -/* Arguments used by JIT */ -#define ARGS_USED_BY_JIT 2 /* only applicable to 64-bit */ - -#define SBIT(x) (1 << (x)) /* Signed version of BIT() */ - -/** - * struct jit_ctx - JIT context - * @skf: The sk_filter - * @prologue_bytes: Number of bytes for prologue - * @idx: Instruction index - * @flags: JIT flags - * @offsets: Instruction offsets - * @target: Memory location for the compiled filter - */ -struct jit_ctx { - const struct bpf_prog *skf; - unsigned int prologue_bytes; - u32 idx; - u32 flags; - u32 *offsets; - u32 *target; -}; - - -static inline int optimize_div(u32 *k) -{ - /* power of 2 divides can be implemented with right shift */ - if (!(*k & (*k-1))) { - *k = ilog2(*k); - return 1; - } - - return 0; -} - -static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx); - -/* Simply emit the instruction if the JIT memory space has been allocated */ -#define emit_instr(ctx, func, ...) \ -do { \ - if ((ctx)->target != NULL) { \ - u32 *p = &(ctx)->target[ctx->idx]; \ - uasm_i_##func(&p, ##__VA_ARGS__); \ - } \ - (ctx)->idx++; \ -} while (0) - -/* - * Similar to emit_instr but it must be used when we need to emit - * 32-bit or 64-bit instructions - */ -#define emit_long_instr(ctx, func, ...) \ -do { \ - if ((ctx)->target != NULL) { \ - u32 *p = &(ctx)->target[ctx->idx]; \ - UASM_i_##func(&p, ##__VA_ARGS__); \ - } \ - (ctx)->idx++; \ -} while (0) - -/* Determine if immediate is within the 16-bit signed range */ -static inline bool is_range16(s32 imm) -{ - return !(imm >= SBIT(15) || imm < -SBIT(15)); -} - -static inline void emit_addu(unsigned int dst, unsigned int src1, - unsigned int src2, struct jit_ctx *ctx) -{ - emit_instr(ctx, addu, dst, src1, src2); -} - -static inline void emit_nop(struct jit_ctx *ctx) -{ - emit_instr(ctx, nop); -} - -/* Load a u32 immediate to a register */ -static inline void emit_load_imm(unsigned int dst, u32 imm, struct jit_ctx *ctx) -{ - if (ctx->target != NULL) { - /* addiu can only handle s16 */ - if (!is_range16(imm)) { - u32 *p = &ctx->target[ctx->idx]; - uasm_i_lui(&p, r_tmp_imm, (s32)imm >> 16); - p = &ctx->target[ctx->idx + 1]; - uasm_i_ori(&p, dst, r_tmp_imm, imm & 0xffff); - } else { - u32 *p = &ctx->target[ctx->idx]; - uasm_i_addiu(&p, dst, r_zero, imm); - } - } - ctx->idx++; - - if (!is_range16(imm)) - ctx->idx++; -} - -static inline void emit_or(unsigned int dst, unsigned int src1, - unsigned int src2, struct jit_ctx *ctx) -{ - emit_instr(ctx, or, dst, src1, src2); -} - -static inline void emit_ori(unsigned int dst, unsigned src, u32 imm, - struct jit_ctx *ctx) -{ - if (imm >= BIT(16)) { - emit_load_imm(r_tmp, imm, ctx); - emit_or(dst, src, r_tmp, ctx); - } else { - emit_instr(ctx, ori, dst, src, imm); - } -} - -static inline void emit_daddiu(unsigned int dst, unsigned int src, - int imm, struct jit_ctx *ctx) -{ - /* - * Only used for stack, so the imm is relatively small - * and it fits in 15-bits - */ - emit_instr(ctx, daddiu, dst, src, imm); -} - -static inline void emit_addiu(unsigned int dst, unsigned int src, - u32 imm, struct jit_ctx *ctx) -{ - if (!is_range16(imm)) { - emit_load_imm(r_tmp, imm, ctx); - emit_addu(dst, r_tmp, src, ctx); - } else { - emit_instr(ctx, addiu, dst, src, imm); - } -} - -static inline void emit_and(unsigned int dst, unsigned int src1, - unsigned int src2, struct jit_ctx *ctx) -{ - emit_instr(ctx, and, dst, src1, src2); -} - -static inline void emit_andi(unsigned int dst, unsigned int src, - u32 imm, struct jit_ctx *ctx) -{ - /* If imm does not fit in u16 then load it to register */ - if (imm >= BIT(16)) { - emit_load_imm(r_tmp, imm, ctx); - emit_and(dst, src, r_tmp, ctx); - } else { - emit_instr(ctx, andi, dst, src, imm); - } -} - -static inline void emit_xor(unsigned int dst, unsigned int src1, - unsigned int src2, struct jit_ctx *ctx) -{ - emit_instr(ctx, xor, dst, src1, src2); -} - -static inline void emit_xori(ptr dst, ptr src, u32 imm, struct jit_ctx *ctx) -{ - /* If imm does not fit in u16 then load it to register */ - if (imm >= BIT(16)) { - emit_load_imm(r_tmp, imm, ctx); - emit_xor(dst, src, r_tmp, ctx); - } else { - emit_instr(ctx, xori, dst, src, imm); - } -} - -static inline void emit_stack_offset(int offset, struct jit_ctx *ctx) -{ - emit_long_instr(ctx, ADDIU, r_sp, r_sp, offset); -} - -static inline void emit_subu(unsigned int dst, unsigned int src1, - unsigned int src2, struct jit_ctx *ctx) -{ - emit_instr(ctx, subu, dst, src1, src2); -} - -static inline void emit_neg(unsigned int reg, struct jit_ctx *ctx) -{ - emit_subu(reg, r_zero, reg, ctx); -} - -static inline void emit_sllv(unsigned int dst, unsigned int src, - unsigned int sa, struct jit_ctx *ctx) -{ - emit_instr(ctx, sllv, dst, src, sa); -} - -static inline void emit_sll(unsigned int dst, unsigned int src, - unsigned int sa, struct jit_ctx *ctx) -{ - /* sa is 5-bits long */ - if (sa >= BIT(5)) - /* Shifting >= 32 results in zero */ - emit_jit_reg_move(dst, r_zero, ctx); - else - emit_instr(ctx, sll, dst, src, sa); -} - -static inline void emit_srlv(unsigned int dst, unsigned int src, - unsigned int sa, struct jit_ctx *ctx) -{ - emit_instr(ctx, srlv, dst, src, sa); -} - -static inline void emit_srl(unsigned int dst, unsigned int src, - unsigned int sa, struct jit_ctx *ctx) -{ - /* sa is 5-bits long */ - if (sa >= BIT(5)) - /* Shifting >= 32 results in zero */ - emit_jit_reg_move(dst, r_zero, ctx); - else - emit_instr(ctx, srl, dst, src, sa); -} - -static inline void emit_slt(unsigned int dst, unsigned int src1, - unsigned int src2, struct jit_ctx *ctx) -{ - emit_instr(ctx, slt, dst, src1, src2); -} - -static inline void emit_sltu(unsigned int dst, unsigned int src1, - unsigned int src2, struct jit_ctx *ctx) -{ - emit_instr(ctx, sltu, dst, src1, src2); -} - -static inline void emit_sltiu(unsigned dst, unsigned int src, - unsigned int imm, struct jit_ctx *ctx) -{ - /* 16 bit immediate */ - if (!is_range16((s32)imm)) { - emit_load_imm(r_tmp, imm, ctx); - emit_sltu(dst, src, r_tmp, ctx); - } else { - emit_instr(ctx, sltiu, dst, src, imm); - } - -} - -/* Store register on the stack */ -static inline void emit_store_stack_reg(ptr reg, ptr base, - unsigned int offset, - struct jit_ctx *ctx) -{ - emit_long_instr(ctx, SW, reg, offset, base); -} - -static inline void emit_store(ptr reg, ptr base, unsigned int offset, - struct jit_ctx *ctx) -{ - emit_instr(ctx, sw, reg, offset, base); -} - -static inline void emit_load_stack_reg(ptr reg, ptr base, - unsigned int offset, - struct jit_ctx *ctx) -{ - emit_long_instr(ctx, LW, reg, offset, base); -} - -static inline void emit_load(unsigned int reg, unsigned int base, - unsigned int offset, struct jit_ctx *ctx) -{ - emit_instr(ctx, lw, reg, offset, base); -} - -static inline void emit_load_byte(unsigned int reg, unsigned int base, - unsigned int offset, struct jit_ctx *ctx) -{ - emit_instr(ctx, lb, reg, offset, base); -} - -static inline void emit_half_load(unsigned int reg, unsigned int base, - unsigned int offset, struct jit_ctx *ctx) -{ - emit_instr(ctx, lh, reg, offset, base); -} - -static inline void emit_half_load_unsigned(unsigned int reg, unsigned int base, - unsigned int offset, struct jit_ctx *ctx) -{ - emit_instr(ctx, lhu, reg, offset, base); -} - -static inline void emit_mul(unsigned int dst, unsigned int src1, - unsigned int src2, struct jit_ctx *ctx) -{ - emit_instr(ctx, mul, dst, src1, src2); -} - -static inline void emit_div(unsigned int dst, unsigned int src, - struct jit_ctx *ctx) -{ - if (ctx->target != NULL) { - u32 *p = &ctx->target[ctx->idx]; - uasm_i_divu(&p, dst, src); - p = &ctx->target[ctx->idx + 1]; - uasm_i_mflo(&p, dst); - } - ctx->idx += 2; /* 2 insts */ -} - -static inline void emit_mod(unsigned int dst, unsigned int src, - struct jit_ctx *ctx) -{ - if (ctx->target != NULL) { - u32 *p = &ctx->target[ctx->idx]; - uasm_i_divu(&p, dst, src); - p = &ctx->target[ctx->idx + 1]; - uasm_i_mfhi(&p, dst); - } - ctx->idx += 2; /* 2 insts */ -} - -static inline void emit_dsll(unsigned int dst, unsigned int src, - unsigned int sa, struct jit_ctx *ctx) -{ - emit_instr(ctx, dsll, dst, src, sa); -} - -static inline void emit_dsrl32(unsigned int dst, unsigned int src, - unsigned int sa, struct jit_ctx *ctx) -{ - emit_instr(ctx, dsrl32, dst, src, sa); -} - -static inline void emit_wsbh(unsigned int dst, unsigned int src, - struct jit_ctx *ctx) -{ - emit_instr(ctx, wsbh, dst, src); -} - -/* load pointer to register */ -static inline void emit_load_ptr(unsigned int dst, unsigned int src, - int imm, struct jit_ctx *ctx) -{ - /* src contains the base addr of the 32/64-pointer */ - emit_long_instr(ctx, LW, dst, imm, src); -} - -/* load a function pointer to register */ -static inline void emit_load_func(unsigned int reg, ptr imm, - struct jit_ctx *ctx) -{ - if (IS_ENABLED(CONFIG_64BIT)) { - /* At this point imm is always 64-bit */ - emit_load_imm(r_tmp, (u64)imm >> 32, ctx); - emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */ - emit_ori(r_tmp, r_tmp_imm, (imm >> 16) & 0xffff, ctx); - emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */ - emit_ori(reg, r_tmp_imm, imm & 0xffff, ctx); - } else { - emit_load_imm(reg, imm, ctx); - } -} - -/* Move to real MIPS register */ -static inline void emit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx) -{ - emit_long_instr(ctx, ADDU, dst, src, r_zero); -} - -/* Move to JIT (32-bit) register */ -static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx) -{ - emit_addu(dst, src, r_zero, ctx); -} - -/* Compute the immediate value for PC-relative branches. */ -static inline u32 b_imm(unsigned int tgt, struct jit_ctx *ctx) -{ - if (ctx->target == NULL) - return 0; - - /* - * We want a pc-relative branch. We only do forward branches - * so tgt is always after pc. tgt is the instruction offset - * we want to jump to. - - * Branch on MIPS: - * I: target_offset <- sign_extend(offset) - * I+1: PC += target_offset (delay slot) - * - * ctx->idx currently points to the branch instruction - * but the offset is added to the delay slot so we need - * to subtract 4. - */ - return ctx->offsets[tgt] - - (ctx->idx * 4 - ctx->prologue_bytes) - 4; -} - -static inline void emit_bcond(int cond, unsigned int reg1, unsigned int reg2, - unsigned int imm, struct jit_ctx *ctx) -{ - if (ctx->target != NULL) { - u32 *p = &ctx->target[ctx->idx]; - - switch (cond) { - case MIPS_COND_EQ: - uasm_i_beq(&p, reg1, reg2, imm); - break; - case MIPS_COND_NE: - uasm_i_bne(&p, reg1, reg2, imm); - break; - case MIPS_COND_ALL: - uasm_i_b(&p, imm); - break; - default: - pr_warn("%s: Unhandled branch conditional: %d\n", - __func__, cond); - } - } - ctx->idx++; -} - -static inline void emit_b(unsigned int imm, struct jit_ctx *ctx) -{ - emit_bcond(MIPS_COND_ALL, r_zero, r_zero, imm, ctx); -} - -static inline void emit_jalr(unsigned int link, unsigned int reg, - struct jit_ctx *ctx) -{ - emit_instr(ctx, jalr, link, reg); -} - -static inline void emit_jr(unsigned int reg, struct jit_ctx *ctx) -{ - emit_instr(ctx, jr, reg); -} - -static inline u16 align_sp(unsigned int num) -{ - /* Double word alignment for 32-bit, quadword for 64-bit */ - unsigned int align = IS_ENABLED(CONFIG_64BIT) ? 16 : 8; - num = (num + (align - 1)) & -align; - return num; -} - -static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset) -{ - int i = 0, real_off = 0; - u32 sflags, tmp_flags; - - /* Adjust the stack pointer */ - if (offset) - emit_stack_offset(-align_sp(offset), ctx); - - tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT; - /* sflags is essentially a bitmap */ - while (tmp_flags) { - if ((sflags >> i) & 0x1) { - emit_store_stack_reg(MIPS_R_S0 + i, r_sp, real_off, - ctx); - real_off += SZREG; - } - i++; - tmp_flags >>= 1; - } - - /* save return address */ - if (ctx->flags & SEEN_CALL) { - emit_store_stack_reg(r_ra, r_sp, real_off, ctx); - real_off += SZREG; - } - - /* Setup r_M leaving the alignment gap if necessary */ - if (ctx->flags & SEEN_MEM) { - if (real_off % (SZREG * 2)) - real_off += SZREG; - emit_long_instr(ctx, ADDIU, r_M, r_sp, real_off); - } -} - -static void restore_bpf_jit_regs(struct jit_ctx *ctx, - unsigned int offset) -{ - int i, real_off = 0; - u32 sflags, tmp_flags; - - tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT; - /* sflags is a bitmap */ - i = 0; - while (tmp_flags) { - if ((sflags >> i) & 0x1) { - emit_load_stack_reg(MIPS_R_S0 + i, r_sp, real_off, - ctx); - real_off += SZREG; - } - i++; - tmp_flags >>= 1; - } - - /* restore return address */ - if (ctx->flags & SEEN_CALL) - emit_load_stack_reg(r_ra, r_sp, real_off, ctx); - - /* Restore the sp and discard the scrach memory */ - if (offset) - emit_stack_offset(align_sp(offset), ctx); -} - -static unsigned int get_stack_depth(struct jit_ctx *ctx) -{ - int sp_off = 0; - - - /* How may s* regs do we need to preserved? */ - sp_off += hweight32(ctx->flags >> SEEN_SREG_SFT) * SZREG; - - if (ctx->flags & SEEN_MEM) - sp_off += 4 * BPF_MEMWORDS; /* BPF_MEMWORDS are 32-bit */ - - if (ctx->flags & SEEN_CALL) - sp_off += SZREG; /* Space for our ra register */ - - return sp_off; -} - -static void build_prologue(struct jit_ctx *ctx) -{ - int sp_off; - - /* Calculate the total offset for the stack pointer */ - sp_off = get_stack_depth(ctx); - save_bpf_jit_regs(ctx, sp_off); - - if (ctx->flags & SEEN_SKB) - emit_reg_move(r_skb, MIPS_R_A0, ctx); - - if (ctx->flags & SEEN_SKB_DATA) { - /* Load packet length */ - emit_load(r_skb_len, r_skb, offsetof(struct sk_buff, len), - ctx); - emit_load(r_tmp, r_skb, offsetof(struct sk_buff, data_len), - ctx); - /* Load the data pointer */ - emit_load_ptr(r_skb_data, r_skb, - offsetof(struct sk_buff, data), ctx); - /* Load the header length */ - emit_subu(r_skb_hl, r_skb_len, r_tmp, ctx); - } - - if (ctx->flags & SEEN_X) - emit_jit_reg_move(r_X, r_zero, ctx); - - /* - * Do not leak kernel data to userspace, we only need to clear - * r_A if it is ever used. In fact if it is never used, we - * will not save/restore it, so clearing it in this case would - * corrupt the state of the caller. - */ - if (bpf_needs_clear_a(&ctx->skf->insns[0]) && - (ctx->flags & SEEN_A)) - emit_jit_reg_move(r_A, r_zero, ctx); -} - -static void build_epilogue(struct jit_ctx *ctx) -{ - unsigned int sp_off; - - /* Calculate the total offset for the stack pointer */ - - sp_off = get_stack_depth(ctx); - restore_bpf_jit_regs(ctx, sp_off); - - /* Return */ - emit_jr(r_ra, ctx); - emit_nop(ctx); -} - -#define CHOOSE_LOAD_FUNC(K, func) \ - ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative : func) : \ - func##_positive) - -static int build_body(struct jit_ctx *ctx) -{ - const struct bpf_prog *prog = ctx->skf; - const struct sock_filter *inst; - unsigned int i, off, condt; - u32 k, b_off __maybe_unused; - u8 (*sk_load_func)(unsigned long *skb, int offset); - - for (i = 0; i < prog->len; i++) { - u16 code; - - inst = &(prog->insns[i]); - pr_debug("%s: code->0x%02x, jt->0x%x, jf->0x%x, k->0x%x\n", - __func__, inst->code, inst->jt, inst->jf, inst->k); - k = inst->k; - code = bpf_anc_helper(inst); - - if (ctx->target == NULL) - ctx->offsets[i] = ctx->idx * 4; - - switch (code) { - case BPF_LD | BPF_IMM: - /* A <- k ==> li r_A, k */ - ctx->flags |= SEEN_A; - emit_load_imm(r_A, k, ctx); - break; - case BPF_LD | BPF_W | BPF_LEN: - BUILD_BUG_ON(sizeof_field(struct sk_buff, len) != 4); - /* A <- len ==> lw r_A, offset(skb) */ - ctx->flags |= SEEN_SKB | SEEN_A; - off = offsetof(struct sk_buff, len); - emit_load(r_A, r_skb, off, ctx); - break; - case BPF_LD | BPF_MEM: - /* A <- M[k] ==> lw r_A, offset(M) */ - ctx->flags |= SEEN_MEM | SEEN_A; - emit_load(r_A, r_M, SCRATCH_OFF(k), ctx); - break; - case BPF_LD | BPF_W | BPF_ABS: - /* A <- P[k:4] */ - sk_load_func = CHOOSE_LOAD_FUNC(k, sk_load_word); - goto load; - case BPF_LD | BPF_H | BPF_ABS: - /* A <- P[k:2] */ - sk_load_func = CHOOSE_LOAD_FUNC(k, sk_load_half); - goto load; - case BPF_LD | BPF_B | BPF_ABS: - /* A <- P[k:1] */ - sk_load_func = CHOOSE_LOAD_FUNC(k, sk_load_byte); -load: - emit_load_imm(r_off, k, ctx); -load_common: - ctx->flags |= SEEN_CALL | SEEN_OFF | - SEEN_SKB | SEEN_A | SEEN_SKB_DATA; - - emit_load_func(r_s0, (ptr)sk_load_func, ctx); - emit_reg_move(MIPS_R_A0, r_skb, ctx); - emit_jalr(MIPS_R_RA, r_s0, ctx); - /* Load second argument to delay slot */ - emit_reg_move(MIPS_R_A1, r_off, ctx); - /* Check the error value */ - emit_bcond(MIPS_COND_EQ, r_ret, 0, b_imm(i + 1, ctx), - ctx); - /* Load return register on DS for failures */ - emit_reg_move(r_ret, r_zero, ctx); - /* Return with error */ - emit_b(b_imm(prog->len, ctx), ctx); - emit_nop(ctx); - break; - case BPF_LD | BPF_W | BPF_IND: - /* A <- P[X + k:4] */ - sk_load_func = sk_load_word; - goto load_ind; - case BPF_LD | BPF_H | BPF_IND: - /* A <- P[X + k:2] */ - sk_load_func = sk_load_half; - goto load_ind; - case BPF_LD | BPF_B | BPF_IND: - /* A <- P[X + k:1] */ - sk_load_func = sk_load_byte; -load_ind: - ctx->flags |= SEEN_OFF | SEEN_X; - emit_addiu(r_off, r_X, k, ctx); - goto load_common; - case BPF_LDX | BPF_IMM: - /* X <- k */ - ctx->flags |= SEEN_X; - emit_load_imm(r_X, k, ctx); - break; - case BPF_LDX | BPF_MEM: - /* X <- M[k] */ - ctx->flags |= SEEN_X | SEEN_MEM; - emit_load(r_X, r_M, SCRATCH_OFF(k), ctx); - break; - case BPF_LDX | BPF_W | BPF_LEN: - /* X <- len */ - ctx->flags |= SEEN_X | SEEN_SKB; - off = offsetof(struct sk_buff, len); - emit_load(r_X, r_skb, off, ctx); - break; - case BPF_LDX | BPF_B | BPF_MSH: - /* X <- 4 * (P[k:1] & 0xf) */ - ctx->flags |= SEEN_X | SEEN_CALL | SEEN_SKB; - /* Load offset to a1 */ - emit_load_func(r_s0, (ptr)sk_load_byte, ctx); - /* - * This may emit two instructions so it may not fit - * in the delay slot. So use a0 in the delay slot. - */ - emit_load_imm(MIPS_R_A1, k, ctx); - emit_jalr(MIPS_R_RA, r_s0, ctx); - emit_reg_move(MIPS_R_A0, r_skb, ctx); /* delay slot */ - /* Check the error value */ - emit_bcond(MIPS_COND_NE, r_ret, 0, - b_imm(prog->len, ctx), ctx); - emit_reg_move(r_ret, r_zero, ctx); - /* We are good */ - /* X <- P[1:K] & 0xf */ - emit_andi(r_X, r_A, 0xf, ctx); - /* X << 2 */ - emit_b(b_imm(i + 1, ctx), ctx); - emit_sll(r_X, r_X, 2, ctx); /* delay slot */ - break; - case BPF_ST: - /* M[k] <- A */ - ctx->flags |= SEEN_MEM | SEEN_A; - emit_store(r_A, r_M, SCRATCH_OFF(k), ctx); - break; - case BPF_STX: - /* M[k] <- X */ - ctx->flags |= SEEN_MEM | SEEN_X; - emit_store(r_X, r_M, SCRATCH_OFF(k), ctx); - break; - case BPF_ALU | BPF_ADD | BPF_K: - /* A += K */ - ctx->flags |= SEEN_A; - emit_addiu(r_A, r_A, k, ctx); - break; - case BPF_ALU | BPF_ADD | BPF_X: - /* A += X */ - ctx->flags |= SEEN_A | SEEN_X; - emit_addu(r_A, r_A, r_X, ctx); - break; - case BPF_ALU | BPF_SUB | BPF_K: - /* A -= K */ - ctx->flags |= SEEN_A; - emit_addiu(r_A, r_A, -k, ctx); - break; - case BPF_ALU | BPF_SUB | BPF_X: - /* A -= X */ - ctx->flags |= SEEN_A | SEEN_X; - emit_subu(r_A, r_A, r_X, ctx); - break; - case BPF_ALU | BPF_MUL | BPF_K: - /* A *= K */ - /* Load K to scratch register before MUL */ - ctx->flags |= SEEN_A; - emit_load_imm(r_s0, k, ctx); - emit_mul(r_A, r_A, r_s0, ctx); - break; - case BPF_ALU | BPF_MUL | BPF_X: - /* A *= X */ - ctx->flags |= SEEN_A | SEEN_X; - emit_mul(r_A, r_A, r_X, ctx); - break; - case BPF_ALU | BPF_DIV | BPF_K: - /* A /= k */ - if (k == 1) - break; - if (optimize_div(&k)) { - ctx->flags |= SEEN_A; - emit_srl(r_A, r_A, k, ctx); - break; - } - ctx->flags |= SEEN_A; - emit_load_imm(r_s0, k, ctx); - emit_div(r_A, r_s0, ctx); - break; - case BPF_ALU | BPF_MOD | BPF_K: - /* A %= k */ - if (k == 1) { - ctx->flags |= SEEN_A; - emit_jit_reg_move(r_A, r_zero, ctx); - } else { - ctx->flags |= SEEN_A; - emit_load_imm(r_s0, k, ctx); - emit_mod(r_A, r_s0, ctx); - } - break; - case BPF_ALU | BPF_DIV | BPF_X: - /* A /= X */ - ctx->flags |= SEEN_X | SEEN_A; - /* Check if r_X is zero */ - emit_bcond(MIPS_COND_EQ, r_X, r_zero, - b_imm(prog->len, ctx), ctx); - emit_load_imm(r_ret, 0, ctx); /* delay slot */ - emit_div(r_A, r_X, ctx); - break; - case BPF_ALU | BPF_MOD | BPF_X: - /* A %= X */ - ctx->flags |= SEEN_X | SEEN_A; - /* Check if r_X is zero */ - emit_bcond(MIPS_COND_EQ, r_X, r_zero, - b_imm(prog->len, ctx), ctx); - emit_load_imm(r_ret, 0, ctx); /* delay slot */ - emit_mod(r_A, r_X, ctx); - break; - case BPF_ALU | BPF_OR | BPF_K: - /* A |= K */ - ctx->flags |= SEEN_A; - emit_ori(r_A, r_A, k, ctx); - break; - case BPF_ALU | BPF_OR | BPF_X: - /* A |= X */ - ctx->flags |= SEEN_A; - emit_ori(r_A, r_A, r_X, ctx); - break; - case BPF_ALU | BPF_XOR | BPF_K: - /* A ^= k */ - ctx->flags |= SEEN_A; - emit_xori(r_A, r_A, k, ctx); - break; - case BPF_ANC | SKF_AD_ALU_XOR_X: - case BPF_ALU | BPF_XOR | BPF_X: - /* A ^= X */ - ctx->flags |= SEEN_A; - emit_xor(r_A, r_A, r_X, ctx); - break; - case BPF_ALU | BPF_AND | BPF_K: - /* A &= K */ - ctx->flags |= SEEN_A; - emit_andi(r_A, r_A, k, ctx); - break; - case BPF_ALU | BPF_AND | BPF_X: - /* A &= X */ - ctx->flags |= SEEN_A | SEEN_X; - emit_and(r_A, r_A, r_X, ctx); - break; - case BPF_ALU | BPF_LSH | BPF_K: - /* A <<= K */ - ctx->flags |= SEEN_A; - emit_sll(r_A, r_A, k, ctx); - break; - case BPF_ALU | BPF_LSH | BPF_X: - /* A <<= X */ - ctx->flags |= SEEN_A | SEEN_X; - emit_sllv(r_A, r_A, r_X, ctx); - break; - case BPF_ALU | BPF_RSH | BPF_K: - /* A >>= K */ - ctx->flags |= SEEN_A; - emit_srl(r_A, r_A, k, ctx); - break; - case BPF_ALU | BPF_RSH | BPF_X: - ctx->flags |= SEEN_A | SEEN_X; - emit_srlv(r_A, r_A, r_X, ctx); - break; - case BPF_ALU | BPF_NEG: - /* A = -A */ - ctx->flags |= SEEN_A; - emit_neg(r_A, ctx); - break; - case BPF_JMP | BPF_JA: - /* pc += K */ - emit_b(b_imm(i + k + 1, ctx), ctx); - emit_nop(ctx); - break; - case BPF_JMP | BPF_JEQ | BPF_K: - /* pc += ( A == K ) ? pc->jt : pc->jf */ - condt = MIPS_COND_EQ | MIPS_COND_K; - goto jmp_cmp; - case BPF_JMP | BPF_JEQ | BPF_X: - ctx->flags |= SEEN_X; - /* pc += ( A == X ) ? pc->jt : pc->jf */ - condt = MIPS_COND_EQ | MIPS_COND_X; - goto jmp_cmp; - case BPF_JMP | BPF_JGE | BPF_K: - /* pc += ( A >= K ) ? pc->jt : pc->jf */ - condt = MIPS_COND_GE | MIPS_COND_K; - goto jmp_cmp; - case BPF_JMP | BPF_JGE | BPF_X: - ctx->flags |= SEEN_X; - /* pc += ( A >= X ) ? pc->jt : pc->jf */ - condt = MIPS_COND_GE | MIPS_COND_X; - goto jmp_cmp; - case BPF_JMP | BPF_JGT | BPF_K: - /* pc += ( A > K ) ? pc->jt : pc->jf */ - condt = MIPS_COND_GT | MIPS_COND_K; - goto jmp_cmp; - case BPF_JMP | BPF_JGT | BPF_X: - ctx->flags |= SEEN_X; - /* pc += ( A > X ) ? pc->jt : pc->jf */ - condt = MIPS_COND_GT | MIPS_COND_X; -jmp_cmp: - /* Greater or Equal */ - if ((condt & MIPS_COND_GE) || - (condt & MIPS_COND_GT)) { - if (condt & MIPS_COND_K) { /* K */ - ctx->flags |= SEEN_A; - emit_sltiu(r_s0, r_A, k, ctx); - } else { /* X */ - ctx->flags |= SEEN_A | - SEEN_X; - emit_sltu(r_s0, r_A, r_X, ctx); - } - /* A < (K|X) ? r_scrach = 1 */ - b_off = b_imm(i + inst->jf + 1, ctx); - emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, - ctx); - emit_nop(ctx); - /* A > (K|X) ? scratch = 0 */ - if (condt & MIPS_COND_GT) { - /* Checking for equality */ - ctx->flags |= SEEN_A | SEEN_X; - if (condt & MIPS_COND_K) - emit_load_imm(r_s0, k, ctx); - else - emit_jit_reg_move(r_s0, r_X, - ctx); - b_off = b_imm(i + inst->jf + 1, ctx); - emit_bcond(MIPS_COND_EQ, r_A, r_s0, - b_off, ctx); - emit_nop(ctx); - /* Finally, A > K|X */ - b_off = b_imm(i + inst->jt + 1, ctx); - emit_b(b_off, ctx); - emit_nop(ctx); - } else { - /* A >= (K|X) so jump */ - b_off = b_imm(i + inst->jt + 1, ctx); - emit_b(b_off, ctx); - emit_nop(ctx); - } - } else { - /* A == K|X */ - if (condt & MIPS_COND_K) { /* K */ - ctx->flags |= SEEN_A; - emit_load_imm(r_s0, k, ctx); - /* jump true */ - b_off = b_imm(i + inst->jt + 1, ctx); - emit_bcond(MIPS_COND_EQ, r_A, r_s0, - b_off, ctx); - emit_nop(ctx); - /* jump false */ - b_off = b_imm(i + inst->jf + 1, - ctx); - emit_bcond(MIPS_COND_NE, r_A, r_s0, - b_off, ctx); - emit_nop(ctx); - } else { /* X */ - /* jump true */ - ctx->flags |= SEEN_A | SEEN_X; - b_off = b_imm(i + inst->jt + 1, - ctx); - emit_bcond(MIPS_COND_EQ, r_A, r_X, - b_off, ctx); - emit_nop(ctx); - /* jump false */ - b_off = b_imm(i + inst->jf + 1, ctx); - emit_bcond(MIPS_COND_NE, r_A, r_X, - b_off, ctx); - emit_nop(ctx); - } - } - break; - case BPF_JMP | BPF_JSET | BPF_K: - ctx->flags |= SEEN_A; - /* pc += (A & K) ? pc -> jt : pc -> jf */ - emit_load_imm(r_s1, k, ctx); - emit_and(r_s0, r_A, r_s1, ctx); - /* jump true */ - b_off = b_imm(i + inst->jt + 1, ctx); - emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx); - emit_nop(ctx); - /* jump false */ - b_off = b_imm(i + inst->jf + 1, ctx); - emit_b(b_off, ctx); - emit_nop(ctx); - break; - case BPF_JMP | BPF_JSET | BPF_X: - ctx->flags |= SEEN_X | SEEN_A; - /* pc += (A & X) ? pc -> jt : pc -> jf */ - emit_and(r_s0, r_A, r_X, ctx); - /* jump true */ - b_off = b_imm(i + inst->jt + 1, ctx); - emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx); - emit_nop(ctx); - /* jump false */ - b_off = b_imm(i + inst->jf + 1, ctx); - emit_b(b_off, ctx); - emit_nop(ctx); - break; - case BPF_RET | BPF_A: - ctx->flags |= SEEN_A; - if (i != prog->len - 1) - /* - * If this is not the last instruction - * then jump to the epilogue - */ - emit_b(b_imm(prog->len, ctx), ctx); - emit_reg_move(r_ret, r_A, ctx); /* delay slot */ - break; - case BPF_RET | BPF_K: - /* - * It can emit two instructions so it does not fit on - * the delay slot. - */ - emit_load_imm(r_ret, k, ctx); - if (i != prog->len - 1) { - /* - * If this is not the last instruction - * then jump to the epilogue - */ - emit_b(b_imm(prog->len, ctx), ctx); - emit_nop(ctx); - } - break; - case BPF_MISC | BPF_TAX: - /* X = A */ - ctx->flags |= SEEN_X | SEEN_A; - emit_jit_reg_move(r_X, r_A, ctx); - break; - case BPF_MISC | BPF_TXA: - /* A = X */ - ctx->flags |= SEEN_A | SEEN_X; - emit_jit_reg_move(r_A, r_X, ctx); - break; - /* AUX */ - case BPF_ANC | SKF_AD_PROTOCOL: - /* A = ntohs(skb->protocol */ - ctx->flags |= SEEN_SKB | SEEN_OFF | SEEN_A; - BUILD_BUG_ON(sizeof_field(struct sk_buff, - protocol) != 2); - off = offsetof(struct sk_buff, protocol); - emit_half_load(r_A, r_skb, off, ctx); -#ifdef CONFIG_CPU_LITTLE_ENDIAN - /* This needs little endian fixup */ - if (cpu_has_wsbh) { - /* R2 and later have the wsbh instruction */ - emit_wsbh(r_A, r_A, ctx); - } else { - /* Get first byte */ - emit_andi(r_tmp_imm, r_A, 0xff, ctx); - /* Shift it */ - emit_sll(r_tmp, r_tmp_imm, 8, ctx); - /* Get second byte */ - emit_srl(r_tmp_imm, r_A, 8, ctx); - emit_andi(r_tmp_imm, r_tmp_imm, 0xff, ctx); - /* Put everyting together in r_A */ - emit_or(r_A, r_tmp, r_tmp_imm, ctx); - } -#endif - break; - case BPF_ANC | SKF_AD_CPU: - ctx->flags |= SEEN_A | SEEN_OFF; - /* A = current_thread_info()->cpu */ - BUILD_BUG_ON(sizeof_field(struct thread_info, - cpu) != 4); - off = offsetof(struct thread_info, cpu); - /* $28/gp points to the thread_info struct */ - emit_load(r_A, 28, off, ctx); - break; - case BPF_ANC | SKF_AD_IFINDEX: - /* A = skb->dev->ifindex */ - case BPF_ANC | SKF_AD_HATYPE: - /* A = skb->dev->type */ - ctx->flags |= SEEN_SKB | SEEN_A; - off = offsetof(struct sk_buff, dev); - /* Load *dev pointer */ - emit_load_ptr(r_s0, r_skb, off, ctx); - /* error (0) in the delay slot */ - emit_bcond(MIPS_COND_EQ, r_s0, r_zero, - b_imm(prog->len, ctx), ctx); - emit_reg_move(r_ret, r_zero, ctx); - if (code == (BPF_ANC | SKF_AD_IFINDEX)) { - BUILD_BUG_ON(sizeof_field(struct net_device, ifindex) != 4); - off = offsetof(struct net_device, ifindex); - emit_load(r_A, r_s0, off, ctx); - } else { /* (code == (BPF_ANC | SKF_AD_HATYPE) */ - BUILD_BUG_ON(sizeof_field(struct net_device, type) != 2); - off = offsetof(struct net_device, type); - emit_half_load_unsigned(r_A, r_s0, off, ctx); - } - break; - case BPF_ANC | SKF_AD_MARK: - ctx->flags |= SEEN_SKB | SEEN_A; - BUILD_BUG_ON(sizeof_field(struct sk_buff, mark) != 4); - off = offsetof(struct sk_buff, mark); - emit_load(r_A, r_skb, off, ctx); - break; - case BPF_ANC | SKF_AD_RXHASH: - ctx->flags |= SEEN_SKB | SEEN_A; - BUILD_BUG_ON(sizeof_field(struct sk_buff, hash) != 4); - off = offsetof(struct sk_buff, hash); - emit_load(r_A, r_skb, off, ctx); - break; - case BPF_ANC | SKF_AD_VLAN_TAG: - ctx->flags |= SEEN_SKB | SEEN_A; - BUILD_BUG_ON(sizeof_field(struct sk_buff, - vlan_tci) != 2); - off = offsetof(struct sk_buff, vlan_tci); - emit_half_load_unsigned(r_A, r_skb, off, ctx); - break; - case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT: - ctx->flags |= SEEN_SKB | SEEN_A; - emit_load_byte(r_A, r_skb, PKT_VLAN_PRESENT_OFFSET(), ctx); - if (PKT_VLAN_PRESENT_BIT) - emit_srl(r_A, r_A, PKT_VLAN_PRESENT_BIT, ctx); - if (PKT_VLAN_PRESENT_BIT < 7) - emit_andi(r_A, r_A, 1, ctx); - break; - case BPF_ANC | SKF_AD_PKTTYPE: - ctx->flags |= SEEN_SKB; - - emit_load_byte(r_tmp, r_skb, PKT_TYPE_OFFSET(), ctx); - /* Keep only the last 3 bits */ - emit_andi(r_A, r_tmp, PKT_TYPE_MAX, ctx); -#ifdef __BIG_ENDIAN_BITFIELD - /* Get the actual packet type to the lower 3 bits */ - emit_srl(r_A, r_A, 5, ctx); -#endif - break; - case BPF_ANC | SKF_AD_QUEUE: - ctx->flags |= SEEN_SKB | SEEN_A; - BUILD_BUG_ON(sizeof_field(struct sk_buff, - queue_mapping) != 2); - BUILD_BUG_ON(offsetof(struct sk_buff, - queue_mapping) > 0xff); - off = offsetof(struct sk_buff, queue_mapping); - emit_half_load_unsigned(r_A, r_skb, off, ctx); - break; - default: - pr_debug("%s: Unhandled opcode: 0x%02x\n", __FILE__, - inst->code); - return -1; - } - } - - /* compute offsets only during the first pass */ - if (ctx->target == NULL) - ctx->offsets[i] = ctx->idx * 4; - - return 0; -} - -void bpf_jit_compile(struct bpf_prog *fp) -{ - struct jit_ctx ctx; - unsigned int alloc_size, tmp_idx; - - if (!bpf_jit_enable) - return; - - memset(&ctx, 0, sizeof(ctx)); - - ctx.offsets = kcalloc(fp->len + 1, sizeof(*ctx.offsets), GFP_KERNEL); - if (ctx.offsets == NULL) - return; - - ctx.skf = fp; - - if (build_body(&ctx)) - goto out; - - tmp_idx = ctx.idx; - build_prologue(&ctx); - ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4; - /* just to complete the ctx.idx count */ - build_epilogue(&ctx); - - alloc_size = 4 * ctx.idx; - ctx.target = module_alloc(alloc_size); - if (ctx.target == NULL) - goto out; - - /* Clean it */ - memset(ctx.target, 0, alloc_size); - - ctx.idx = 0; - - /* Generate the actual JIT code */ - build_prologue(&ctx); - build_body(&ctx); - build_epilogue(&ctx); - - /* Update the icache */ - flush_icache_range((ptr)ctx.target, (ptr)(ctx.target + ctx.idx)); - - if (bpf_jit_enable > 1) - /* Dump JIT code */ - bpf_jit_dump(fp->len, alloc_size, 2, ctx.target); - - fp->bpf_func = (void *)ctx.target; - fp->jited = 1; - -out: - kfree(ctx.offsets); -} - -void bpf_jit_free(struct bpf_prog *fp) -{ - if (fp->jited) - module_memfree(fp->bpf_func); - - bpf_prog_unlock_free(fp); -} diff --git a/arch/mips/net/bpf_jit.h b/arch/mips/net/bpf_jit.h deleted file mode 100644 index 166ca06c9da9..000000000000 --- a/arch/mips/net/bpf_jit.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Just-In-Time compiler for BPF filters on MIPS - * - * Copyright (c) 2014 Imagination Technologies Ltd. - * Author: Markos Chandras <markos.chandras@imgtec.com> - */ - -#ifndef BPF_JIT_MIPS_OP_H -#define BPF_JIT_MIPS_OP_H - -/* Registers used by JIT */ -#define MIPS_R_ZERO 0 -#define MIPS_R_V0 2 -#define MIPS_R_A0 4 -#define MIPS_R_A1 5 -#define MIPS_R_T4 12 -#define MIPS_R_T5 13 -#define MIPS_R_T6 14 -#define MIPS_R_T7 15 -#define MIPS_R_S0 16 -#define MIPS_R_S1 17 -#define MIPS_R_S2 18 -#define MIPS_R_S3 19 -#define MIPS_R_S4 20 -#define MIPS_R_S5 21 -#define MIPS_R_S6 22 -#define MIPS_R_S7 23 -#define MIPS_R_SP 29 -#define MIPS_R_RA 31 - -/* Conditional codes */ -#define MIPS_COND_EQ 0x1 -#define MIPS_COND_GE (0x1 << 1) -#define MIPS_COND_GT (0x1 << 2) -#define MIPS_COND_NE (0x1 << 3) -#define MIPS_COND_ALL (0x1 << 4) -/* Conditionals on X register or K immediate */ -#define MIPS_COND_X (0x1 << 5) -#define MIPS_COND_K (0x1 << 6) - -#define r_ret MIPS_R_V0 - -/* - * Use 2 scratch registers to avoid pipeline interlocks. - * There is no overhead during epilogue and prologue since - * any of the $s0-$s6 registers will only be preserved if - * they are going to actually be used. - */ -#define r_skb_hl MIPS_R_S0 /* skb header length */ -#define r_skb_data MIPS_R_S1 /* skb actual data */ -#define r_off MIPS_R_S2 -#define r_A MIPS_R_S3 -#define r_X MIPS_R_S4 -#define r_skb MIPS_R_S5 -#define r_M MIPS_R_S6 -#define r_skb_len MIPS_R_S7 -#define r_s0 MIPS_R_T4 /* scratch reg 1 */ -#define r_s1 MIPS_R_T5 /* scratch reg 2 */ -#define r_tmp_imm MIPS_R_T6 /* No need to preserve this */ -#define r_tmp MIPS_R_T7 /* No need to preserve this */ -#define r_zero MIPS_R_ZERO -#define r_sp MIPS_R_SP -#define r_ra MIPS_R_RA - -#ifndef __ASSEMBLY__ - -/* Declare ASM helpers */ - -#define DECLARE_LOAD_FUNC(func) \ - extern u8 func(unsigned long *skb, int offset); \ - extern u8 func##_negative(unsigned long *skb, int offset); \ - extern u8 func##_positive(unsigned long *skb, int offset) - -DECLARE_LOAD_FUNC(sk_load_word); -DECLARE_LOAD_FUNC(sk_load_half); -DECLARE_LOAD_FUNC(sk_load_byte); - -#endif - -#endif /* BPF_JIT_MIPS_OP_H */ diff --git a/arch/mips/net/bpf_jit_asm.S b/arch/mips/net/bpf_jit_asm.S deleted file mode 100644 index 57154c5883b6..000000000000 --- a/arch/mips/net/bpf_jit_asm.S +++ /dev/null @@ -1,285 +0,0 @@ -/* - * bpf_jib_asm.S: Packet/header access helper functions for MIPS/MIPS64 BPF - * compiler. - * - * Copyright (C) 2015 Imagination Technologies Ltd. - * Author: Markos Chandras <markos.chandras@imgtec.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; version 2 of the License. - */ - -#include <asm/asm.h> -#include <asm/isa-rev.h> -#include <asm/regdef.h> -#include "bpf_jit.h" - -/* ABI - * - * r_skb_hl skb header length - * r_skb_data skb data - * r_off(a1) offset register - * r_A BPF register A - * r_X PF register X - * r_skb(a0) *skb - * r_M *scratch memory - * r_skb_le skb length - * r_s0 Scratch register 0 - * r_s1 Scratch register 1 - * - * On entry: - * a0: *skb - * a1: offset (imm or imm + X) - * - * All non-BPF-ABI registers are free for use. On return, we only - * care about r_ret. The BPF-ABI registers are assumed to remain - * unmodified during the entire filter operation. - */ - -#define skb a0 -#define offset a1 -#define SKF_LL_OFF (-0x200000) /* Can't include linux/filter.h in assembly */ - - /* We know better :) so prevent assembler reordering etc */ - .set noreorder - -#define is_offset_negative(TYPE) \ - /* If offset is negative we have more work to do */ \ - slti t0, offset, 0; \ - bgtz t0, bpf_slow_path_##TYPE##_neg; \ - /* Be careful what follows in DS. */ - -#define is_offset_in_header(SIZE, TYPE) \ - /* Reading from header? */ \ - addiu $r_s0, $r_skb_hl, -SIZE; \ - slt t0, $r_s0, offset; \ - bgtz t0, bpf_slow_path_##TYPE; \ - -LEAF(sk_load_word) - is_offset_negative(word) -FEXPORT(sk_load_word_positive) - is_offset_in_header(4, word) - /* Offset within header boundaries */ - PTR_ADDU t1, $r_skb_data, offset - .set reorder - lw $r_A, 0(t1) - .set noreorder -#ifdef CONFIG_CPU_LITTLE_ENDIAN -# if MIPS_ISA_REV >= 2 - wsbh t0, $r_A - rotr $r_A, t0, 16 -# else - sll t0, $r_A, 24 - srl t1, $r_A, 24 - srl t2, $r_A, 8 - or t0, t0, t1 - andi t2, t2, 0xff00 - andi t1, $r_A, 0xff00 - or t0, t0, t2 - sll t1, t1, 8 - or $r_A, t0, t1 -# endif -#endif - jr $r_ra - move $r_ret, zero - END(sk_load_word) - -LEAF(sk_load_half) - is_offset_negative(half) -FEXPORT(sk_load_half_positive) - is_offset_in_header(2, half) - /* Offset within header boundaries */ - PTR_ADDU t1, $r_skb_data, offset - lhu $r_A, 0(t1) -#ifdef CONFIG_CPU_LITTLE_ENDIAN -# if MIPS_ISA_REV >= 2 - wsbh $r_A, $r_A -# else - sll t0, $r_A, 8 - srl t1, $r_A, 8 - andi t0, t0, 0xff00 - or $r_A, t0, t1 -# endif -#endif - jr $r_ra - move $r_ret, zero - END(sk_load_half) - -LEAF(sk_load_byte) - is_offset_negative(byte) -FEXPORT(sk_load_byte_positive) - is_offset_in_header(1, byte) - /* Offset within header boundaries */ - PTR_ADDU t1, $r_skb_data, offset - lbu $r_A, 0(t1) - jr $r_ra - move $r_ret, zero - END(sk_load_byte) - -/* - * call skb_copy_bits: - * (prototype in linux/skbuff.h) - * - * int skb_copy_bits(sk_buff *skb, int offset, void *to, int len) - * - * o32 mandates we leave 4 spaces for argument registers in case - * the callee needs to use them. Even though we don't care about - * the argument registers ourselves, we need to allocate that space - * to remain ABI compliant since the callee may want to use that space. - * We also allocate 2 more spaces for $r_ra and our return register (*to). - * - * n64 is a bit different. The *caller* will allocate the space to preserve - * the arguments. So in 64-bit kernels, we allocate the 4-arg space for no - * good reason but it does not matter that much really. - * - * (void *to) is returned in r_s0 - * - */ -#ifdef CONFIG_CPU_LITTLE_ENDIAN -#define DS_OFFSET(SIZE) (4 * SZREG) -#else -#define DS_OFFSET(SIZE) ((4 * SZREG) + (4 - SIZE)) -#endif -#define bpf_slow_path_common(SIZE) \ - /* Quick check. Are we within reasonable boundaries? */ \ - LONG_ADDIU $r_s1, $r_skb_len, -SIZE; \ - sltu $r_s0, offset, $r_s1; \ - beqz $r_s0, fault; \ - /* Load 4th argument in DS */ \ - LONG_ADDIU a3, zero, SIZE; \ - PTR_ADDIU $r_sp, $r_sp, -(6 * SZREG); \ - PTR_LA t0, skb_copy_bits; \ - PTR_S $r_ra, (5 * SZREG)($r_sp); \ - /* Assign low slot to a2 */ \ - PTR_ADDIU a2, $r_sp, DS_OFFSET(SIZE); \ - jalr t0; \ - /* Reset our destination slot (DS but it's ok) */ \ - INT_S zero, (4 * SZREG)($r_sp); \ - /* \ - * skb_copy_bits returns 0 on success and -EFAULT \ - * on error. Our data live in a2. Do not bother with \ - * our data if an error has been returned. \ - */ \ - /* Restore our frame */ \ - PTR_L $r_ra, (5 * SZREG)($r_sp); \ - INT_L $r_s0, (4 * SZREG)($r_sp); \ - bltz v0, fault; \ - PTR_ADDIU $r_sp, $r_sp, 6 * SZREG; \ - move $r_ret, zero; \ - -NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp) - bpf_slow_path_common(4) -#ifdef CONFIG_CPU_LITTLE_ENDIAN -# if MIPS_ISA_REV >= 2 - wsbh t0, $r_s0 - jr $r_ra - rotr $r_A, t0, 16 -# else - sll t0, $r_s0, 24 - srl t1, $r_s0, 24 - srl t2, $r_s0, 8 - or t0, t0, t1 - andi t2, t2, 0xff00 - andi t1, $r_s0, 0xff00 - or t0, t0, t2 - sll t1, t1, 8 - jr $r_ra - or $r_A, t0, t1 -# endif -#else - jr $r_ra - move $r_A, $r_s0 -#endif - - END(bpf_slow_path_word) - -NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp) - bpf_slow_path_common(2) -#ifdef CONFIG_CPU_LITTLE_ENDIAN -# if MIPS_ISA_REV >= 2 - jr $r_ra - wsbh $r_A, $r_s0 -# else - sll t0, $r_s0, 8 - andi t1, $r_s0, 0xff00 - andi t0, t0, 0xff00 - srl t1, t1, 8 - jr $r_ra - or $r_A, t0, t1 -# endif -#else - jr $r_ra - move $r_A, $r_s0 -#endif - - END(bpf_slow_path_half) - -NESTED(bpf_slow_path_byte, (6 * SZREG), $r_sp) - bpf_slow_path_common(1) - jr $r_ra - move $r_A, $r_s0 - - END(bpf_slow_path_byte) - -/* - * Negative entry points - */ - .macro bpf_is_end_of_data - li t0, SKF_LL_OFF - /* Reading link layer data? */ - slt t1, offset, t0 - bgtz t1, fault - /* Be careful what follows in DS. */ - .endm -/* - * call skb_copy_bits: - * (prototype in linux/filter.h) - * - * void *bpf_internal_load_pointer_neg_helper(const struct sk_buff *skb, - * int k, unsigned int size) - * - * see above (bpf_slow_path_common) for ABI restrictions - */ -#define bpf_negative_common(SIZE) \ - PTR_ADDIU $r_sp, $r_sp, -(6 * SZREG); \ - PTR_LA t0, bpf_internal_load_pointer_neg_helper; \ - PTR_S $r_ra, (5 * SZREG)($r_sp); \ - jalr t0; \ - li a2, SIZE; \ - PTR_L $r_ra, (5 * SZREG)($r_sp); \ - /* Check return pointer */ \ - beqz v0, fault; \ - PTR_ADDIU $r_sp, $r_sp, 6 * SZREG; \ - /* Preserve our pointer */ \ - move $r_s0, v0; \ - /* Set return value */ \ - move $r_ret, zero; \ - -bpf_slow_path_word_neg: - bpf_is_end_of_data -NESTED(sk_load_word_negative, (6 * SZREG), $r_sp) - bpf_negative_common(4) - jr $r_ra - lw $r_A, 0($r_s0) - END(sk_load_word_negative) - -bpf_slow_path_half_neg: - bpf_is_end_of_data -NESTED(sk_load_half_negative, (6 * SZREG), $r_sp) - bpf_negative_common(2) - jr $r_ra - lhu $r_A, 0($r_s0) - END(sk_load_half_negative) - -bpf_slow_path_byte_neg: - bpf_is_end_of_data -NESTED(sk_load_byte_negative, (6 * SZREG), $r_sp) - bpf_negative_common(1) - jr $r_ra - lbu $r_A, 0($r_s0) - END(sk_load_byte_negative) - -fault: - jr $r_ra - addiu $r_ret, zero, 1 diff --git a/arch/mips/net/bpf_jit_comp.c b/arch/mips/net/bpf_jit_comp.c new file mode 100644 index 000000000000..b17130d510d4 --- /dev/null +++ b/arch/mips/net/bpf_jit_comp.c @@ -0,0 +1,1034 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Just-In-Time compiler for eBPF bytecode on MIPS. + * Implementation of JIT functions common to 32-bit and 64-bit CPUs. + * + * Copyright (c) 2021 Anyfi Networks AB. + * Author: Johan Almbladh <johan.almbladh@gmail.com> + * + * Based on code and ideas from + * Copyright (c) 2017 Cavium, Inc. + * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com> + * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> + */ + +/* + * Code overview + * ============= + * + * - bpf_jit_comp.h + * Common definitions and utilities. + * + * - bpf_jit_comp.c + * Implementation of JIT top-level logic and exported JIT API functions. + * Implementation of internal operations shared by 32-bit and 64-bit code. + * JMP and ALU JIT control code, register control code, shared ALU and + * JMP/JMP32 JIT operations. + * + * - bpf_jit_comp32.c + * Implementation of functions to JIT prologue, epilogue and a single eBPF + * instruction for 32-bit MIPS CPUs. The functions use shared operations + * where possible, and implement the rest for 32-bit MIPS such as ALU64 + * operations. + * + * - bpf_jit_comp64.c + * Ditto, for 64-bit MIPS CPUs. + * + * Zero and sign extension + * ======================== + * 32-bit MIPS instructions on 64-bit MIPS registers use sign extension, + * but the eBPF instruction set mandates zero extension. We let the verifier + * insert explicit zero-extensions after 32-bit ALU operations, both for + * 32-bit and 64-bit MIPS JITs. Conditional JMP32 operations on 64-bit MIPs + * are JITed with sign extensions inserted when so expected. + * + * ALU operations + * ============== + * ALU operations on 32/64-bit MIPS and ALU64 operations on 64-bit MIPS are + * JITed in the following steps. ALU64 operations on 32-bit MIPS are more + * complicated and therefore only processed by special implementations in + * step (3). + * + * 1) valid_alu_i: + * Determine if an immediate operation can be emitted as such, or if + * we must fall back to the register version. + * + * 2) rewrite_alu_i: + * Convert BPF operation and immediate value to a canonical form for + * JITing. In some degenerate cases this form may be a no-op. + * + * 3) emit_alu_{i,i64,r,64}: + * Emit instructions for an ALU or ALU64 immediate or register operation. + * + * JMP operations + * ============== + * JMP and JMP32 operations require an JIT instruction offset table for + * translating the jump offset. This table is computed by dry-running the + * JIT without actually emitting anything. However, the computed PC-relative + * offset may overflow the 18-bit offset field width of the native MIPS + * branch instruction. In such cases, the long jump is converted into the + * following sequence. + * + * <branch> !<cond> +2 Inverted PC-relative branch + * nop Delay slot + * j <offset> Unconditional absolute long jump + * nop Delay slot + * + * Since this converted sequence alters the offset table, all offsets must + * be re-calculated. This may in turn trigger new branch conversions, so + * the process is repeated until no further changes are made. Normally it + * completes in 1-2 iterations. If JIT_MAX_ITERATIONS should reached, we + * fall back to converting every remaining jump operation. The branch + * conversion is independent of how the JMP or JMP32 condition is JITed. + * + * JMP32 and JMP operations are JITed as follows. + * + * 1) setup_jmp_{i,r}: + * Convert jump conditional and offset into a form that can be JITed. + * This form may be a no-op, a canonical form, or an inverted PC-relative + * jump if branch conversion is necessary. + * + * 2) valid_jmp_i: + * Determine if an immediate operations can be emitted as such, or if + * we must fall back to the register version. Applies to JMP32 for 32-bit + * MIPS, and both JMP and JMP32 for 64-bit MIPS. + * + * 3) emit_jmp_{i,i64,r,r64}: + * Emit instructions for an JMP or JMP32 immediate or register operation. + * + * 4) finish_jmp_{i,r}: + * Emit any instructions needed to finish the jump. This includes a nop + * for the delay slot if a branch was emitted, and a long absolute jump + * if the branch was converted. + */ + +#include <linux/limits.h> +#include <linux/bitops.h> +#include <linux/errno.h> +#include <linux/filter.h> +#include <linux/bpf.h> +#include <linux/slab.h> +#include <asm/bitops.h> +#include <asm/cacheflush.h> +#include <asm/cpu-features.h> +#include <asm/isa-rev.h> +#include <asm/uasm.h> + +#include "bpf_jit_comp.h" + +/* Convenience macros for descriptor access */ +#define CONVERTED(desc) ((desc) & JIT_DESC_CONVERT) +#define INDEX(desc) ((desc) & ~JIT_DESC_CONVERT) + +/* + * Push registers on the stack, starting at a given depth from the stack + * pointer and increasing. The next depth to be written is returned. + */ +int push_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth) +{ + int reg; + + for (reg = 0; reg < BITS_PER_BYTE * sizeof(mask); reg++) + if (mask & BIT(reg)) { + if ((excl & BIT(reg)) == 0) { + if (sizeof(long) == 4) + emit(ctx, sw, reg, depth, MIPS_R_SP); + else /* sizeof(long) == 8 */ + emit(ctx, sd, reg, depth, MIPS_R_SP); + } + depth += sizeof(long); + } + + ctx->stack_used = max((int)ctx->stack_used, depth); + return depth; +} + +/* + * Pop registers from the stack, starting at a given depth from the stack + * pointer and increasing. The next depth to be read is returned. + */ +int pop_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth) +{ + int reg; + + for (reg = 0; reg < BITS_PER_BYTE * sizeof(mask); reg++) + if (mask & BIT(reg)) { + if ((excl & BIT(reg)) == 0) { + if (sizeof(long) == 4) + emit(ctx, lw, reg, depth, MIPS_R_SP); + else /* sizeof(long) == 8 */ + emit(ctx, ld, reg, depth, MIPS_R_SP); + } + depth += sizeof(long); + } + + return depth; +} + +/* Compute the 28-bit jump target address from a BPF program location */ +int get_target(struct jit_context *ctx, u32 loc) +{ + u32 index = INDEX(ctx->descriptors[loc]); + unsigned long pc = (unsigned long)&ctx->target[ctx->jit_index]; + unsigned long addr = (unsigned long)&ctx->target[index]; + + if (!ctx->target) + return 0; + + if ((addr ^ pc) & ~MIPS_JMP_MASK) + return -1; + + return addr & MIPS_JMP_MASK; +} + +/* Compute the PC-relative offset to relative BPF program offset */ +int get_offset(const struct jit_context *ctx, int off) +{ + return (INDEX(ctx->descriptors[ctx->bpf_index + off]) - + ctx->jit_index - 1) * sizeof(u32); +} + +/* dst = imm (register width) */ +void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm) +{ + if (imm >= -0x8000 && imm <= 0x7fff) { + emit(ctx, addiu, dst, MIPS_R_ZERO, imm); + } else { + emit(ctx, lui, dst, (s16)((u32)imm >> 16)); + emit(ctx, ori, dst, dst, (u16)(imm & 0xffff)); + } + clobber_reg(ctx, dst); +} + +/* dst = src (register width) */ +void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src) +{ + emit(ctx, ori, dst, src, 0); + clobber_reg(ctx, dst); +} + +/* Validate ALU immediate range */ +bool valid_alu_i(u8 op, s32 imm) +{ + switch (BPF_OP(op)) { + case BPF_NEG: + case BPF_LSH: + case BPF_RSH: + case BPF_ARSH: + /* All legal eBPF values are valid */ + return true; + case BPF_ADD: + /* imm must be 16 bits */ + return imm >= -0x8000 && imm <= 0x7fff; + case BPF_SUB: + /* -imm must be 16 bits */ + return imm >= -0x7fff && imm <= 0x8000; + case BPF_AND: + case BPF_OR: + case BPF_XOR: + /* imm must be 16 bits unsigned */ + return imm >= 0 && imm <= 0xffff; + case BPF_MUL: + /* imm must be zero or a positive power of two */ + return imm == 0 || (imm > 0 && is_power_of_2(imm)); + case BPF_DIV: + case BPF_MOD: + /* imm must be an 17-bit power of two */ + return (u32)imm <= 0x10000 && is_power_of_2((u32)imm); + } + return false; +} + +/* Rewrite ALU immediate operation */ +bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val) +{ + bool act = true; + + switch (BPF_OP(op)) { + case BPF_LSH: + case BPF_RSH: + case BPF_ARSH: + case BPF_ADD: + case BPF_SUB: + case BPF_OR: + case BPF_XOR: + /* imm == 0 is a no-op */ + act = imm != 0; + break; + case BPF_MUL: + if (imm == 1) { + /* dst * 1 is a no-op */ + act = false; + } else if (imm == 0) { + /* dst * 0 is dst & 0 */ + op = BPF_AND; + } else { + /* dst * (1 << n) is dst << n */ + op = BPF_LSH; + imm = ilog2(abs(imm)); + } + break; + case BPF_DIV: + if (imm == 1) { + /* dst / 1 is a no-op */ + act = false; + } else { + /* dst / (1 << n) is dst >> n */ + op = BPF_RSH; + imm = ilog2(imm); + } + break; + case BPF_MOD: + /* dst % (1 << n) is dst & ((1 << n) - 1) */ + op = BPF_AND; + imm--; + break; + } + + *alu = op; + *val = imm; + return act; +} + +/* ALU immediate operation (32-bit) */ +void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op) +{ + switch (BPF_OP(op)) { + /* dst = -dst */ + case BPF_NEG: + emit(ctx, subu, dst, MIPS_R_ZERO, dst); + break; + /* dst = dst & imm */ + case BPF_AND: + emit(ctx, andi, dst, dst, (u16)imm); + break; + /* dst = dst | imm */ + case BPF_OR: + emit(ctx, ori, dst, dst, (u16)imm); + break; + /* dst = dst ^ imm */ + case BPF_XOR: + emit(ctx, xori, dst, dst, (u16)imm); + break; + /* dst = dst << imm */ + case BPF_LSH: + emit(ctx, sll, dst, dst, imm); + break; + /* dst = dst >> imm */ + case BPF_RSH: + emit(ctx, srl, dst, dst, imm); + break; + /* dst = dst >> imm (arithmetic) */ + case BPF_ARSH: + emit(ctx, sra, dst, dst, imm); + break; + /* dst = dst + imm */ + case BPF_ADD: + emit(ctx, addiu, dst, dst, imm); + break; + /* dst = dst - imm */ + case BPF_SUB: + emit(ctx, addiu, dst, dst, -imm); + break; + } + clobber_reg(ctx, dst); +} + +/* ALU register operation (32-bit) */ +void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op) +{ + switch (BPF_OP(op)) { + /* dst = dst & src */ + case BPF_AND: + emit(ctx, and, dst, dst, src); + break; + /* dst = dst | src */ + case BPF_OR: + emit(ctx, or, dst, dst, src); + break; + /* dst = dst ^ src */ + case BPF_XOR: + emit(ctx, xor, dst, dst, src); + break; + /* dst = dst << src */ + case BPF_LSH: + emit(ctx, sllv, dst, dst, src); + break; + /* dst = dst >> src */ + case BPF_RSH: + emit(ctx, srlv, dst, dst, src); + break; + /* dst = dst >> src (arithmetic) */ + case BPF_ARSH: + emit(ctx, srav, dst, dst, src); + break; + /* dst = dst + src */ + case BPF_ADD: + emit(ctx, addu, dst, dst, src); + break; + /* dst = dst - src */ + case BPF_SUB: + emit(ctx, subu, dst, dst, src); + break; + /* dst = dst * src */ + case BPF_MUL: + if (cpu_has_mips32r1 || cpu_has_mips32r6) { + emit(ctx, mul, dst, dst, src); + } else { + emit(ctx, multu, dst, src); + emit(ctx, mflo, dst); + } + break; + /* dst = dst / src */ + case BPF_DIV: + if (cpu_has_mips32r6) { + emit(ctx, divu_r6, dst, dst, src); + } else { + emit(ctx, divu, dst, src); + emit(ctx, mflo, dst); + } + break; + /* dst = dst % src */ + case BPF_MOD: + if (cpu_has_mips32r6) { + emit(ctx, modu, dst, dst, src); + } else { + emit(ctx, divu, dst, src); + emit(ctx, mfhi, dst); + } + break; + } + clobber_reg(ctx, dst); +} + +/* Atomic read-modify-write (32-bit) */ +void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code) +{ + LLSC_sync(ctx); + emit(ctx, ll, MIPS_R_T9, off, dst); + switch (code) { + case BPF_ADD: + case BPF_ADD | BPF_FETCH: + emit(ctx, addu, MIPS_R_T8, MIPS_R_T9, src); + break; + case BPF_AND: + case BPF_AND | BPF_FETCH: + emit(ctx, and, MIPS_R_T8, MIPS_R_T9, src); + break; + case BPF_OR: + case BPF_OR | BPF_FETCH: + emit(ctx, or, MIPS_R_T8, MIPS_R_T9, src); + break; + case BPF_XOR: + case BPF_XOR | BPF_FETCH: + emit(ctx, xor, MIPS_R_T8, MIPS_R_T9, src); + break; + case BPF_XCHG: + emit(ctx, move, MIPS_R_T8, src); + break; + } + emit(ctx, sc, MIPS_R_T8, off, dst); + emit(ctx, LLSC_beqz, MIPS_R_T8, -16 - LLSC_offset); + emit(ctx, nop); /* Delay slot */ + + if (code & BPF_FETCH) { + emit(ctx, move, src, MIPS_R_T9); + clobber_reg(ctx, src); + } +} + +/* Atomic compare-and-exchange (32-bit) */ +void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off) +{ + LLSC_sync(ctx); + emit(ctx, ll, MIPS_R_T9, off, dst); + emit(ctx, bne, MIPS_R_T9, res, 12); + emit(ctx, move, MIPS_R_T8, src); /* Delay slot */ + emit(ctx, sc, MIPS_R_T8, off, dst); + emit(ctx, LLSC_beqz, MIPS_R_T8, -20 - LLSC_offset); + emit(ctx, move, res, MIPS_R_T9); /* Delay slot */ + clobber_reg(ctx, res); +} + +/* Swap bytes and truncate a register word or half word */ +void emit_bswap_r(struct jit_context *ctx, u8 dst, u32 width) +{ + u8 tmp = MIPS_R_T8; + u8 msk = MIPS_R_T9; + + switch (width) { + /* Swap bytes in a word */ + case 32: + if (cpu_has_mips32r2 || cpu_has_mips32r6) { + emit(ctx, wsbh, dst, dst); + emit(ctx, rotr, dst, dst, 16); + } else { + emit(ctx, sll, tmp, dst, 16); /* tmp = dst << 16 */ + emit(ctx, srl, dst, dst, 16); /* dst = dst >> 16 */ + emit(ctx, or, dst, dst, tmp); /* dst = dst | tmp */ + + emit(ctx, lui, msk, 0xff); /* msk = 0x00ff0000 */ + emit(ctx, ori, msk, msk, 0xff); /* msk = msk | 0xff */ + + emit(ctx, and, tmp, dst, msk); /* tmp = dst & msk */ + emit(ctx, sll, tmp, tmp, 8); /* tmp = tmp << 8 */ + emit(ctx, srl, dst, dst, 8); /* dst = dst >> 8 */ + emit(ctx, and, dst, dst, msk); /* dst = dst & msk */ + emit(ctx, or, dst, dst, tmp); /* reg = dst | tmp */ + } + break; + /* Swap bytes in a half word */ + case 16: + if (cpu_has_mips32r2 || cpu_has_mips32r6) { + emit(ctx, wsbh, dst, dst); + emit(ctx, andi, dst, dst, 0xffff); + } else { + emit(ctx, andi, tmp, dst, 0xff00); /* t = d & 0xff00 */ + emit(ctx, srl, tmp, tmp, 8); /* t = t >> 8 */ + emit(ctx, andi, dst, dst, 0x00ff); /* d = d & 0x00ff */ + emit(ctx, sll, dst, dst, 8); /* d = d << 8 */ + emit(ctx, or, dst, dst, tmp); /* d = d | t */ + } + break; + } + clobber_reg(ctx, dst); +} + +/* Validate jump immediate range */ +bool valid_jmp_i(u8 op, s32 imm) +{ + switch (op) { + case JIT_JNOP: + /* Immediate value not used */ + return true; + case BPF_JEQ: + case BPF_JNE: + /* No immediate operation */ + return false; + case BPF_JSET: + case JIT_JNSET: + /* imm must be 16 bits unsigned */ + return imm >= 0 && imm <= 0xffff; + case BPF_JGE: + case BPF_JLT: + case BPF_JSGE: + case BPF_JSLT: + /* imm must be 16 bits */ + return imm >= -0x8000 && imm <= 0x7fff; + case BPF_JGT: + case BPF_JLE: + case BPF_JSGT: + case BPF_JSLE: + /* imm + 1 must be 16 bits */ + return imm >= -0x8001 && imm <= 0x7ffe; + } + return false; +} + +/* Invert a conditional jump operation */ +static u8 invert_jmp(u8 op) +{ + switch (op) { + case BPF_JA: return JIT_JNOP; + case BPF_JEQ: return BPF_JNE; + case BPF_JNE: return BPF_JEQ; + case BPF_JSET: return JIT_JNSET; + case BPF_JGT: return BPF_JLE; + case BPF_JGE: return BPF_JLT; + case BPF_JLT: return BPF_JGE; + case BPF_JLE: return BPF_JGT; + case BPF_JSGT: return BPF_JSLE; + case BPF_JSGE: return BPF_JSLT; + case BPF_JSLT: return BPF_JSGE; + case BPF_JSLE: return BPF_JSGT; + } + return 0; +} + +/* Prepare a PC-relative jump operation */ +static void setup_jmp(struct jit_context *ctx, u8 bpf_op, + s16 bpf_off, u8 *jit_op, s32 *jit_off) +{ + u32 *descp = &ctx->descriptors[ctx->bpf_index]; + int op = bpf_op; + int offset = 0; + + /* Do not compute offsets on the first pass */ + if (INDEX(*descp) == 0) + goto done; + + /* Skip jumps never taken */ + if (bpf_op == JIT_JNOP) + goto done; + + /* Convert jumps always taken */ + if (bpf_op == BPF_JA) + *descp |= JIT_DESC_CONVERT; + + /* + * Current ctx->jit_index points to the start of the branch preamble. + * Since the preamble differs among different branch conditionals, + * the current index cannot be used to compute the branch offset. + * Instead, we use the offset table value for the next instruction, + * which gives the index immediately after the branch delay slot. + */ + if (!CONVERTED(*descp)) { + int target = ctx->bpf_index + bpf_off + 1; + int origin = ctx->bpf_index + 1; + + offset = (INDEX(ctx->descriptors[target]) - + INDEX(ctx->descriptors[origin]) + 1) * sizeof(u32); + } + + /* + * The PC-relative branch offset field on MIPS is 18 bits signed, + * so if the computed offset is larger than this we generate a an + * absolute jump that we skip with an inverted conditional branch. + */ + if (CONVERTED(*descp) || offset < -0x20000 || offset > 0x1ffff) { + offset = 3 * sizeof(u32); + op = invert_jmp(bpf_op); + ctx->changes += !CONVERTED(*descp); + *descp |= JIT_DESC_CONVERT; + } + +done: + *jit_off = offset; + *jit_op = op; +} + +/* Prepare a PC-relative jump operation with immediate conditional */ +void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width, + u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off) +{ + bool always = false; + bool never = false; + + switch (bpf_op) { + case BPF_JEQ: + case BPF_JNE: + break; + case BPF_JSET: + case BPF_JLT: + never = imm == 0; + break; + case BPF_JGE: + always = imm == 0; + break; + case BPF_JGT: + never = (u32)imm == U32_MAX; + break; + case BPF_JLE: + always = (u32)imm == U32_MAX; + break; + case BPF_JSGT: + never = imm == S32_MAX && width == 32; + break; + case BPF_JSGE: + always = imm == S32_MIN && width == 32; + break; + case BPF_JSLT: + never = imm == S32_MIN && width == 32; + break; + case BPF_JSLE: + always = imm == S32_MAX && width == 32; + break; + } + + if (never) + bpf_op = JIT_JNOP; + if (always) + bpf_op = BPF_JA; + setup_jmp(ctx, bpf_op, bpf_off, jit_op, jit_off); +} + +/* Prepare a PC-relative jump operation with register conditional */ +void setup_jmp_r(struct jit_context *ctx, bool same_reg, + u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off) +{ + switch (bpf_op) { + case BPF_JSET: + break; + case BPF_JEQ: + case BPF_JGE: + case BPF_JLE: + case BPF_JSGE: + case BPF_JSLE: + if (same_reg) + bpf_op = BPF_JA; + break; + case BPF_JNE: + case BPF_JLT: + case BPF_JGT: + case BPF_JSGT: + case BPF_JSLT: + if (same_reg) + bpf_op = JIT_JNOP; + break; + } + setup_jmp(ctx, bpf_op, bpf_off, jit_op, jit_off); +} + +/* Finish a PC-relative jump operation */ +int finish_jmp(struct jit_context *ctx, u8 jit_op, s16 bpf_off) +{ + /* Emit conditional branch delay slot */ + if (jit_op != JIT_JNOP) + emit(ctx, nop); + /* + * Emit an absolute long jump with delay slot, + * if the PC-relative branch was converted. + */ + if (CONVERTED(ctx->descriptors[ctx->bpf_index])) { + int target = get_target(ctx, ctx->bpf_index + bpf_off + 1); + + if (target < 0) + return -1; + emit(ctx, j, target); + emit(ctx, nop); + } + return 0; +} + +/* Jump immediate (32-bit) */ +void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op) +{ + switch (op) { + /* No-op, used internally for branch optimization */ + case JIT_JNOP: + break; + /* PC += off if dst & imm */ + case BPF_JSET: + emit(ctx, andi, MIPS_R_T9, dst, (u16)imm); + emit(ctx, bnez, MIPS_R_T9, off); + break; + /* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */ + case JIT_JNSET: + emit(ctx, andi, MIPS_R_T9, dst, (u16)imm); + emit(ctx, beqz, MIPS_R_T9, off); + break; + /* PC += off if dst > imm */ + case BPF_JGT: + emit(ctx, sltiu, MIPS_R_T9, dst, imm + 1); + emit(ctx, beqz, MIPS_R_T9, off); + break; + /* PC += off if dst >= imm */ + case BPF_JGE: + emit(ctx, sltiu, MIPS_R_T9, dst, imm); + emit(ctx, beqz, MIPS_R_T9, off); + break; + /* PC += off if dst < imm */ + case BPF_JLT: + emit(ctx, sltiu, MIPS_R_T9, dst, imm); + emit(ctx, bnez, MIPS_R_T9, off); + break; + /* PC += off if dst <= imm */ + case BPF_JLE: + emit(ctx, sltiu, MIPS_R_T9, dst, imm + 1); + emit(ctx, bnez, MIPS_R_T9, off); + break; + /* PC += off if dst > imm (signed) */ + case BPF_JSGT: + emit(ctx, slti, MIPS_R_T9, dst, imm + 1); + emit(ctx, beqz, MIPS_R_T9, off); + break; + /* PC += off if dst >= imm (signed) */ + case BPF_JSGE: + emit(ctx, slti, MIPS_R_T9, dst, imm); + emit(ctx, beqz, MIPS_R_T9, off); + break; + /* PC += off if dst < imm (signed) */ + case BPF_JSLT: + emit(ctx, slti, MIPS_R_T9, dst, imm); + emit(ctx, bnez, MIPS_R_T9, off); + break; + /* PC += off if dst <= imm (signed) */ + case BPF_JSLE: + emit(ctx, slti, MIPS_R_T9, dst, imm + 1); + emit(ctx, bnez, MIPS_R_T9, off); + break; + } +} + +/* Jump register (32-bit) */ +void emit_jmp_r(struct jit_context *ctx, u8 dst, u8 src, s32 off, u8 op) +{ + switch (op) { + /* No-op, used internally for branch optimization */ + case JIT_JNOP: + break; + /* PC += off if dst == src */ + case BPF_JEQ: + emit(ctx, beq, dst, src, off); + break; + /* PC += off if dst != src */ + case BPF_JNE: + emit(ctx, bne, dst, src, off); + break; + /* PC += off if dst & src */ + case BPF_JSET: + emit(ctx, and, MIPS_R_T9, dst, src); + emit(ctx, bnez, MIPS_R_T9, off); + break; + /* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */ + case JIT_JNSET: + emit(ctx, and, MIPS_R_T9, dst, src); + emit(ctx, beqz, MIPS_R_T9, off); + break; + /* PC += off if dst > src */ + case BPF_JGT: + emit(ctx, sltu, MIPS_R_T9, src, dst); + emit(ctx, bnez, MIPS_R_T9, off); + break; + /* PC += off if dst >= src */ + case BPF_JGE: + emit(ctx, sltu, MIPS_R_T9, dst, src); + emit(ctx, beqz, MIPS_R_T9, off); + break; + /* PC += off if dst < src */ + case BPF_JLT: + emit(ctx, sltu, MIPS_R_T9, dst, src); + emit(ctx, bnez, MIPS_R_T9, off); + break; + /* PC += off if dst <= src */ + case BPF_JLE: + emit(ctx, sltu, MIPS_R_T9, src, dst); + emit(ctx, beqz, MIPS_R_T9, off); + break; + /* PC += off if dst > src (signed) */ + case BPF_JSGT: + emit(ctx, slt, MIPS_R_T9, src, dst); + emit(ctx, bnez, MIPS_R_T9, off); + break; + /* PC += off if dst >= src (signed) */ + case BPF_JSGE: + emit(ctx, slt, MIPS_R_T9, dst, src); + emit(ctx, beqz, MIPS_R_T9, off); + break; + /* PC += off if dst < src (signed) */ + case BPF_JSLT: + emit(ctx, slt, MIPS_R_T9, dst, src); + emit(ctx, bnez, MIPS_R_T9, off); + break; + /* PC += off if dst <= src (signed) */ + case BPF_JSLE: + emit(ctx, slt, MIPS_R_T9, src, dst); + emit(ctx, beqz, MIPS_R_T9, off); + break; + } +} + +/* Jump always */ +int emit_ja(struct jit_context *ctx, s16 off) +{ + int target = get_target(ctx, ctx->bpf_index + off + 1); + + if (target < 0) + return -1; + emit(ctx, j, target); + emit(ctx, nop); + return 0; +} + +/* Jump to epilogue */ +int emit_exit(struct jit_context *ctx) +{ + int target = get_target(ctx, ctx->program->len); + + if (target < 0) + return -1; + emit(ctx, j, target); + emit(ctx, nop); + return 0; +} + +/* Build the program body from eBPF bytecode */ +static int build_body(struct jit_context *ctx) +{ + const struct bpf_prog *prog = ctx->program; + unsigned int i; + + ctx->stack_used = 0; + for (i = 0; i < prog->len; i++) { + const struct bpf_insn *insn = &prog->insnsi[i]; + u32 *descp = &ctx->descriptors[i]; + int ret; + + access_reg(ctx, insn->src_reg); + access_reg(ctx, insn->dst_reg); + + ctx->bpf_index = i; + if (ctx->target == NULL) { + ctx->changes += INDEX(*descp) != ctx->jit_index; + *descp &= JIT_DESC_CONVERT; + *descp |= ctx->jit_index; + } + + ret = build_insn(insn, ctx); + if (ret < 0) + return ret; + + if (ret > 0) { + i++; + if (ctx->target == NULL) + descp[1] = ctx->jit_index; + } + } + + /* Store the end offset, where the epilogue begins */ + ctx->descriptors[prog->len] = ctx->jit_index; + return 0; +} + +/* Set the branch conversion flag on all instructions */ +static void set_convert_flag(struct jit_context *ctx, bool enable) +{ + const struct bpf_prog *prog = ctx->program; + u32 flag = enable ? JIT_DESC_CONVERT : 0; + unsigned int i; + + for (i = 0; i <= prog->len; i++) + ctx->descriptors[i] = INDEX(ctx->descriptors[i]) | flag; +} + +static void jit_fill_hole(void *area, unsigned int size) +{ + u32 *p; + + /* We are guaranteed to have aligned memory. */ + for (p = area; size >= sizeof(u32); size -= sizeof(u32)) + uasm_i_break(&p, BRK_BUG); /* Increments p */ +} + +bool bpf_jit_needs_zext(void) +{ + return true; +} + +struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) +{ + struct bpf_prog *tmp, *orig_prog = prog; + struct bpf_binary_header *header = NULL; + struct jit_context ctx; + bool tmp_blinded = false; + unsigned int tmp_idx; + unsigned int image_size; + u8 *image_ptr; + int tries; + + /* + * If BPF JIT was not enabled then we must fall back to + * the interpreter. + */ + if (!prog->jit_requested) + return orig_prog; + /* + * If constant blinding was enabled and we failed during blinding + * then we must fall back to the interpreter. Otherwise, we save + * the new JITed code. + */ + tmp = bpf_jit_blind_constants(prog); + if (IS_ERR(tmp)) + return orig_prog; + if (tmp != prog) { + tmp_blinded = true; + prog = tmp; + } + + memset(&ctx, 0, sizeof(ctx)); + ctx.program = prog; + + /* + * Not able to allocate memory for descriptors[], then + * we must fall back to the interpreter + */ + ctx.descriptors = kcalloc(prog->len + 1, sizeof(*ctx.descriptors), + GFP_KERNEL); + if (ctx.descriptors == NULL) + goto out_err; + + /* First pass discovers used resources */ + if (build_body(&ctx) < 0) + goto out_err; + /* + * Second pass computes instruction offsets. + * If any PC-relative branches are out of range, a sequence of + * a PC-relative branch + a jump is generated, and we have to + * try again from the beginning to generate the new offsets. + * This is done until no additional conversions are necessary. + * The last two iterations are done with all branches being + * converted, to guarantee offset table convergence within a + * fixed number of iterations. + */ + ctx.jit_index = 0; + build_prologue(&ctx); + tmp_idx = ctx.jit_index; + + tries = JIT_MAX_ITERATIONS; + do { + ctx.jit_index = tmp_idx; + ctx.changes = 0; + if (tries == 2) + set_convert_flag(&ctx, true); + if (build_body(&ctx) < 0) + goto out_err; + } while (ctx.changes > 0 && --tries > 0); + + if (WARN_ONCE(ctx.changes > 0, "JIT offsets failed to converge")) + goto out_err; + + build_epilogue(&ctx, MIPS_R_RA); + + /* Now we know the size of the structure to make */ + image_size = sizeof(u32) * ctx.jit_index; + header = bpf_jit_binary_alloc(image_size, &image_ptr, + sizeof(u32), jit_fill_hole); + /* + * Not able to allocate memory for the structure then + * we must fall back to the interpretation + */ + if (header == NULL) + goto out_err; + + /* Actual pass to generate final JIT code */ + ctx.target = (u32 *)image_ptr; + ctx.jit_index = 0; + + /* + * If building the JITed code fails somehow, + * we fall back to the interpretation. + */ + build_prologue(&ctx); + if (build_body(&ctx) < 0) + goto out_err; + build_epilogue(&ctx, MIPS_R_RA); + + /* Populate line info meta data */ + set_convert_flag(&ctx, false); + bpf_prog_fill_jited_linfo(prog, &ctx.descriptors[1]); + + /* Set as read-only exec and flush instruction cache */ + bpf_jit_binary_lock_ro(header); + flush_icache_range((unsigned long)header, + (unsigned long)&ctx.target[ctx.jit_index]); + + if (bpf_jit_enable > 1) + bpf_jit_dump(prog->len, image_size, 2, ctx.target); + + prog->bpf_func = (void *)ctx.target; + prog->jited = 1; + prog->jited_len = image_size; + +out: + if (tmp_blinded) + bpf_jit_prog_release_other(prog, prog == orig_prog ? + tmp : orig_prog); + kfree(ctx.descriptors); + return prog; + +out_err: + prog = orig_prog; + if (header) + bpf_jit_binary_free(header); + goto out; +} diff --git a/arch/mips/net/bpf_jit_comp.h b/arch/mips/net/bpf_jit_comp.h new file mode 100644 index 000000000000..6f3a7b07294b --- /dev/null +++ b/arch/mips/net/bpf_jit_comp.h @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Just-In-Time compiler for eBPF bytecode on 32-bit and 64-bit MIPS. + * + * Copyright (c) 2021 Anyfi Networks AB. + * Author: Johan Almbladh <johan.almbladh@gmail.com> + * + * Based on code and ideas from + * Copyright (c) 2017 Cavium, Inc. + * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com> + * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> + */ + +#ifndef _BPF_JIT_COMP_H +#define _BPF_JIT_COMP_H + +/* MIPS registers */ +#define MIPS_R_ZERO 0 /* Const zero */ +#define MIPS_R_AT 1 /* Asm temp */ +#define MIPS_R_V0 2 /* Result */ +#define MIPS_R_V1 3 /* Result */ +#define MIPS_R_A0 4 /* Argument */ +#define MIPS_R_A1 5 /* Argument */ +#define MIPS_R_A2 6 /* Argument */ +#define MIPS_R_A3 7 /* Argument */ +#define MIPS_R_A4 8 /* Arg (n64) */ +#define MIPS_R_A5 9 /* Arg (n64) */ +#define MIPS_R_A6 10 /* Arg (n64) */ +#define MIPS_R_A7 11 /* Arg (n64) */ +#define MIPS_R_T0 8 /* Temp (o32) */ +#define MIPS_R_T1 9 /* Temp (o32) */ +#define MIPS_R_T2 10 /* Temp (o32) */ +#define MIPS_R_T3 11 /* Temp (o32) */ +#define MIPS_R_T4 12 /* Temporary */ +#define MIPS_R_T5 13 /* Temporary */ +#define MIPS_R_T6 14 /* Temporary */ +#define MIPS_R_T7 15 /* Temporary */ +#define MIPS_R_S0 16 /* Saved */ +#define MIPS_R_S1 17 /* Saved */ +#define MIPS_R_S2 18 /* Saved */ +#define MIPS_R_S3 19 /* Saved */ +#define MIPS_R_S4 20 /* Saved */ +#define MIPS_R_S5 21 /* Saved */ +#define MIPS_R_S6 22 /* Saved */ +#define MIPS_R_S7 23 /* Saved */ +#define MIPS_R_T8 24 /* Temporary */ +#define MIPS_R_T9 25 /* Temporary */ +/* MIPS_R_K0 26 Reserved */ +/* MIPS_R_K1 27 Reserved */ +#define MIPS_R_GP 28 /* Global ptr */ +#define MIPS_R_SP 29 /* Stack ptr */ +#define MIPS_R_FP 30 /* Frame ptr */ +#define MIPS_R_RA 31 /* Return */ + +/* + * Jump address mask for immediate jumps. The four most significant bits + * must be equal to PC. + */ +#define MIPS_JMP_MASK 0x0fffffffUL + +/* Maximum number of iterations in offset table computation */ +#define JIT_MAX_ITERATIONS 8 + +/* + * Jump pseudo-instructions used internally + * for branch conversion and branch optimization. + */ +#define JIT_JNSET 0xe0 +#define JIT_JNOP 0xf0 + +/* Descriptor flag for PC-relative branch conversion */ +#define JIT_DESC_CONVERT BIT(31) + +/* JIT context for an eBPF program */ +struct jit_context { + struct bpf_prog *program; /* The eBPF program being JITed */ + u32 *descriptors; /* eBPF to JITed CPU insn descriptors */ + u32 *target; /* JITed code buffer */ + u32 bpf_index; /* Index of current BPF program insn */ + u32 jit_index; /* Index of current JIT target insn */ + u32 changes; /* Number of PC-relative branch conv */ + u32 accessed; /* Bit mask of read eBPF registers */ + u32 clobbered; /* Bit mask of modified CPU registers */ + u32 stack_size; /* Total allocated stack size in bytes */ + u32 saved_size; /* Size of callee-saved registers */ + u32 stack_used; /* Stack size used for function calls */ +}; + +/* Emit the instruction if the JIT memory space has been allocated */ +#define __emit(ctx, func, ...) \ +do { \ + if ((ctx)->target != NULL) { \ + u32 *p = &(ctx)->target[ctx->jit_index]; \ + uasm_i_##func(&p, ##__VA_ARGS__); \ + } \ + (ctx)->jit_index++; \ +} while (0) +#define emit(...) __emit(__VA_ARGS__) + +/* Workaround for R10000 ll/sc errata */ +#ifdef CONFIG_WAR_R10000 +#define LLSC_beqz beqzl +#else +#define LLSC_beqz beqz +#endif + +/* Workaround for Loongson-3 ll/sc errata */ +#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS +#define LLSC_sync(ctx) emit(ctx, sync, 0) +#define LLSC_offset 4 +#else +#define LLSC_sync(ctx) +#define LLSC_offset 0 +#endif + +/* Workaround for Loongson-2F jump errata */ +#ifdef CONFIG_CPU_JUMP_WORKAROUNDS +#define JALR_MASK 0xffffffffcfffffffULL +#else +#define JALR_MASK (~0ULL) +#endif + +/* + * Mark a BPF register as accessed, it needs to be + * initialized by the program if expected, e.g. FP. + */ +static inline void access_reg(struct jit_context *ctx, u8 reg) +{ + ctx->accessed |= BIT(reg); +} + +/* + * Mark a CPU register as clobbered, it needs to be + * saved/restored by the program if callee-saved. + */ +static inline void clobber_reg(struct jit_context *ctx, u8 reg) +{ + ctx->clobbered |= BIT(reg); +} + +/* + * Push registers on the stack, starting at a given depth from the stack + * pointer and increasing. The next depth to be written is returned. + */ +int push_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth); + +/* + * Pop registers from the stack, starting at a given depth from the stack + * pointer and increasing. The next depth to be read is returned. + */ +int pop_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth); + +/* Compute the 28-bit jump target address from a BPF program location */ +int get_target(struct jit_context *ctx, u32 loc); + +/* Compute the PC-relative offset to relative BPF program offset */ +int get_offset(const struct jit_context *ctx, int off); + +/* dst = imm (32-bit) */ +void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm); + +/* dst = src (32-bit) */ +void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src); + +/* Validate ALU/ALU64 immediate range */ +bool valid_alu_i(u8 op, s32 imm); + +/* Rewrite ALU/ALU64 immediate operation */ +bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val); + +/* ALU immediate operation (32-bit) */ +void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op); + +/* ALU register operation (32-bit) */ +void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op); + +/* Atomic read-modify-write (32-bit) */ +void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code); + +/* Atomic compare-and-exchange (32-bit) */ +void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off); + +/* Swap bytes and truncate a register word or half word */ +void emit_bswap_r(struct jit_context *ctx, u8 dst, u32 width); + +/* Validate JMP/JMP32 immediate range */ +bool valid_jmp_i(u8 op, s32 imm); + +/* Prepare a PC-relative jump operation with immediate conditional */ +void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width, + u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off); + +/* Prepare a PC-relative jump operation with register conditional */ +void setup_jmp_r(struct jit_context *ctx, bool same_reg, + u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off); + +/* Finish a PC-relative jump operation */ +int finish_jmp(struct jit_context *ctx, u8 jit_op, s16 bpf_off); + +/* Conditional JMP/JMP32 immediate */ +void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op); + +/* Conditional JMP/JMP32 register */ +void emit_jmp_r(struct jit_context *ctx, u8 dst, u8 src, s32 off, u8 op); + +/* Jump always */ +int emit_ja(struct jit_context *ctx, s16 off); + +/* Jump to epilogue */ +int emit_exit(struct jit_context *ctx); + +/* + * Build program prologue to set up the stack and registers. + * This function is implemented separately for 32-bit and 64-bit JITs. + */ +void build_prologue(struct jit_context *ctx); + +/* + * Build the program epilogue to restore the stack and registers. + * This function is implemented separately for 32-bit and 64-bit JITs. + */ +void build_epilogue(struct jit_context *ctx, int dest_reg); + +/* + * Convert an eBPF instruction to native instruction, i.e + * JITs an eBPF instruction. + * Returns : + * 0 - Successfully JITed an 8-byte eBPF instruction + * >0 - Successfully JITed a 16-byte eBPF instruction + * <0 - Failed to JIT. + * This function is implemented separately for 32-bit and 64-bit JITs. + */ +int build_insn(const struct bpf_insn *insn, struct jit_context *ctx); + +#endif /* _BPF_JIT_COMP_H */ diff --git a/arch/mips/net/bpf_jit_comp32.c b/arch/mips/net/bpf_jit_comp32.c new file mode 100644 index 000000000000..bd996ede12f8 --- /dev/null +++ b/arch/mips/net/bpf_jit_comp32.c @@ -0,0 +1,1899 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Just-In-Time compiler for eBPF bytecode on MIPS. + * Implementation of JIT functions for 32-bit CPUs. + * + * Copyright (c) 2021 Anyfi Networks AB. + * Author: Johan Almbladh <johan.almbladh@gmail.com> + * + * Based on code and ideas from + * Copyright (c) 2017 Cavium, Inc. + * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com> + * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> + */ + +#include <linux/math64.h> +#include <linux/errno.h> +#include <linux/filter.h> +#include <linux/bpf.h> +#include <asm/cpu-features.h> +#include <asm/isa-rev.h> +#include <asm/uasm.h> + +#include "bpf_jit_comp.h" + +/* MIPS a4-a7 are not available in the o32 ABI */ +#undef MIPS_R_A4 +#undef MIPS_R_A5 +#undef MIPS_R_A6 +#undef MIPS_R_A7 + +/* Stack is 8-byte aligned in o32 ABI */ +#define MIPS_STACK_ALIGNMENT 8 + +/* + * The top 16 bytes of a stack frame is reserved for the callee in O32 ABI. + * This corresponds to stack space for register arguments a0-a3. + */ +#define JIT_RESERVED_STACK 16 + +/* Temporary 64-bit register used by JIT */ +#define JIT_REG_TMP MAX_BPF_JIT_REG + +/* + * Number of prologue bytes to skip when doing a tail call. + * Tail call count (TCC) initialization (8 bytes) always, plus + * R0-to-v0 assignment (4 bytes) if big endian. + */ +#ifdef __BIG_ENDIAN +#define JIT_TCALL_SKIP 12 +#else +#define JIT_TCALL_SKIP 8 +#endif + +/* CPU registers holding the callee return value */ +#define JIT_RETURN_REGS \ + (BIT(MIPS_R_V0) | \ + BIT(MIPS_R_V1)) + +/* CPU registers arguments passed to callee directly */ +#define JIT_ARG_REGS \ + (BIT(MIPS_R_A0) | \ + BIT(MIPS_R_A1) | \ + BIT(MIPS_R_A2) | \ + BIT(MIPS_R_A3)) + +/* CPU register arguments passed to callee on stack */ +#define JIT_STACK_REGS \ + (BIT(MIPS_R_T0) | \ + BIT(MIPS_R_T1) | \ + BIT(MIPS_R_T2) | \ + BIT(MIPS_R_T3) | \ + BIT(MIPS_R_T4) | \ + BIT(MIPS_R_T5)) + +/* Caller-saved CPU registers */ +#define JIT_CALLER_REGS \ + (JIT_RETURN_REGS | \ + JIT_ARG_REGS | \ + JIT_STACK_REGS) + +/* Callee-saved CPU registers */ +#define JIT_CALLEE_REGS \ + (BIT(MIPS_R_S0) | \ + BIT(MIPS_R_S1) | \ + BIT(MIPS_R_S2) | \ + BIT(MIPS_R_S3) | \ + BIT(MIPS_R_S4) | \ + BIT(MIPS_R_S5) | \ + BIT(MIPS_R_S6) | \ + BIT(MIPS_R_S7) | \ + BIT(MIPS_R_GP) | \ + BIT(MIPS_R_FP) | \ + BIT(MIPS_R_RA)) + +/* + * Mapping of 64-bit eBPF registers to 32-bit native MIPS registers. + * + * 1) Native register pairs are ordered according to CPU endiannes, following + * the MIPS convention for passing 64-bit arguments and return values. + * 2) The eBPF return value, arguments and callee-saved registers are mapped + * to their native MIPS equivalents. + * 3) Since the 32 highest bits in the eBPF FP register are always zero, + * only one general-purpose register is actually needed for the mapping. + * We use the fp register for this purpose, and map the highest bits to + * the MIPS register r0 (zero). + * 4) We use the MIPS gp and at registers as internal temporary registers + * for constant blinding. The gp register is callee-saved. + * 5) One 64-bit temporary register is mapped for use when sign-extending + * immediate operands. MIPS registers t6-t9 are available to the JIT + * for as temporaries when implementing complex 64-bit operations. + * + * With this scheme all eBPF registers are being mapped to native MIPS + * registers without having to use any stack scratch space. The direct + * register mapping (2) simplifies the handling of function calls. + */ +static const u8 bpf2mips32[][2] = { + /* Return value from in-kernel function, and exit value from eBPF */ + [BPF_REG_0] = {MIPS_R_V1, MIPS_R_V0}, + /* Arguments from eBPF program to in-kernel function */ + [BPF_REG_1] = {MIPS_R_A1, MIPS_R_A0}, + [BPF_REG_2] = {MIPS_R_A3, MIPS_R_A2}, + /* Remaining arguments, to be passed on the stack per O32 ABI */ + [BPF_REG_3] = {MIPS_R_T1, MIPS_R_T0}, + [BPF_REG_4] = {MIPS_R_T3, MIPS_R_T2}, + [BPF_REG_5] = {MIPS_R_T5, MIPS_R_T4}, + /* Callee-saved registers that in-kernel function will preserve */ + [BPF_REG_6] = {MIPS_R_S1, MIPS_R_S0}, + [BPF_REG_7] = {MIPS_R_S3, MIPS_R_S2}, + [BPF_REG_8] = {MIPS_R_S5, MIPS_R_S4}, + [BPF_REG_9] = {MIPS_R_S7, MIPS_R_S6}, + /* Read-only frame pointer to access the eBPF stack */ +#ifdef __BIG_ENDIAN + [BPF_REG_FP] = {MIPS_R_FP, MIPS_R_ZERO}, +#else + [BPF_REG_FP] = {MIPS_R_ZERO, MIPS_R_FP}, +#endif + /* Temporary register for blinding constants */ + [BPF_REG_AX] = {MIPS_R_GP, MIPS_R_AT}, + /* Temporary register for internal JIT use */ + [JIT_REG_TMP] = {MIPS_R_T7, MIPS_R_T6}, +}; + +/* Get low CPU register for a 64-bit eBPF register mapping */ +static inline u8 lo(const u8 reg[]) +{ +#ifdef __BIG_ENDIAN + return reg[0]; +#else + return reg[1]; +#endif +} + +/* Get high CPU register for a 64-bit eBPF register mapping */ +static inline u8 hi(const u8 reg[]) +{ +#ifdef __BIG_ENDIAN + return reg[1]; +#else + return reg[0]; +#endif +} + +/* + * Mark a 64-bit CPU register pair as clobbered, it needs to be + * saved/restored by the program if callee-saved. + */ +static void clobber_reg64(struct jit_context *ctx, const u8 reg[]) +{ + clobber_reg(ctx, reg[0]); + clobber_reg(ctx, reg[1]); +} + +/* dst = imm (sign-extended) */ +static void emit_mov_se_i64(struct jit_context *ctx, const u8 dst[], s32 imm) +{ + emit_mov_i(ctx, lo(dst), imm); + if (imm < 0) + emit(ctx, addiu, hi(dst), MIPS_R_ZERO, -1); + else + emit(ctx, move, hi(dst), MIPS_R_ZERO); + clobber_reg64(ctx, dst); +} + +/* Zero extension, if verifier does not do it for us */ +static void emit_zext_ver(struct jit_context *ctx, const u8 dst[]) +{ + if (!ctx->program->aux->verifier_zext) { + emit(ctx, move, hi(dst), MIPS_R_ZERO); + clobber_reg(ctx, hi(dst)); + } +} + +/* Load delay slot, if ISA mandates it */ +static void emit_load_delay(struct jit_context *ctx) +{ + if (!cpu_has_mips_2_3_4_5_r) + emit(ctx, nop); +} + +/* ALU immediate operation (64-bit) */ +static void emit_alu_i64(struct jit_context *ctx, + const u8 dst[], s32 imm, u8 op) +{ + u8 src = MIPS_R_T6; + + /* + * ADD/SUB with all but the max negative imm can be handled by + * inverting the operation and the imm value, saving one insn. + */ + if (imm > S32_MIN && imm < 0) + switch (op) { + case BPF_ADD: + op = BPF_SUB; + imm = -imm; + break; + case BPF_SUB: + op = BPF_ADD; + imm = -imm; + break; + } + + /* Move immediate to temporary register */ + emit_mov_i(ctx, src, imm); + + switch (op) { + /* dst = dst + imm */ + case BPF_ADD: + emit(ctx, addu, lo(dst), lo(dst), src); + emit(ctx, sltu, MIPS_R_T9, lo(dst), src); + emit(ctx, addu, hi(dst), hi(dst), MIPS_R_T9); + if (imm < 0) + emit(ctx, addiu, hi(dst), hi(dst), -1); + break; + /* dst = dst - imm */ + case BPF_SUB: + emit(ctx, sltu, MIPS_R_T9, lo(dst), src); + emit(ctx, subu, lo(dst), lo(dst), src); + emit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9); + if (imm < 0) + emit(ctx, addiu, hi(dst), hi(dst), 1); + break; + /* dst = dst | imm */ + case BPF_OR: + emit(ctx, or, lo(dst), lo(dst), src); + if (imm < 0) + emit(ctx, addiu, hi(dst), MIPS_R_ZERO, -1); + break; + /* dst = dst & imm */ + case BPF_AND: + emit(ctx, and, lo(dst), lo(dst), src); + if (imm >= 0) + emit(ctx, move, hi(dst), MIPS_R_ZERO); + break; + /* dst = dst ^ imm */ + case BPF_XOR: + emit(ctx, xor, lo(dst), lo(dst), src); + if (imm < 0) { + emit(ctx, subu, hi(dst), MIPS_R_ZERO, hi(dst)); + emit(ctx, addiu, hi(dst), hi(dst), -1); + } + break; + } + clobber_reg64(ctx, dst); +} + +/* ALU register operation (64-bit) */ +static void emit_alu_r64(struct jit_context *ctx, + const u8 dst[], const u8 src[], u8 op) +{ + switch (BPF_OP(op)) { + /* dst = dst + src */ + case BPF_ADD: + if (src == dst) { + emit(ctx, srl, MIPS_R_T9, lo(dst), 31); + emit(ctx, addu, lo(dst), lo(dst), lo(dst)); + } else { + emit(ctx, addu, lo(dst), lo(dst), lo(src)); + emit(ctx, sltu, MIPS_R_T9, lo(dst), lo(src)); + } + emit(ctx, addu, hi(dst), hi(dst), hi(src)); + emit(ctx, addu, hi(dst), hi(dst), MIPS_R_T9); + break; + /* dst = dst - src */ + case BPF_SUB: + emit(ctx, sltu, MIPS_R_T9, lo(dst), lo(src)); + emit(ctx, subu, lo(dst), lo(dst), lo(src)); + emit(ctx, subu, hi(dst), hi(dst), hi(src)); + emit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9); + break; + /* dst = dst | src */ + case BPF_OR: + emit(ctx, or, lo(dst), lo(dst), lo(src)); + emit(ctx, or, hi(dst), hi(dst), hi(src)); + break; + /* dst = dst & src */ + case BPF_AND: + emit(ctx, and, lo(dst), lo(dst), lo(src)); + emit(ctx, and, hi(dst), hi(dst), hi(src)); + break; + /* dst = dst ^ src */ + case BPF_XOR: + emit(ctx, xor, lo(dst), lo(dst), lo(src)); + emit(ctx, xor, hi(dst), hi(dst), hi(src)); + break; + } + clobber_reg64(ctx, dst); +} + +/* ALU invert (64-bit) */ +static void emit_neg_i64(struct jit_context *ctx, const u8 dst[]) +{ + emit(ctx, sltu, MIPS_R_T9, MIPS_R_ZERO, lo(dst)); + emit(ctx, subu, lo(dst), MIPS_R_ZERO, lo(dst)); + emit(ctx, subu, hi(dst), MIPS_R_ZERO, hi(dst)); + emit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9); + + clobber_reg64(ctx, dst); +} + +/* ALU shift immediate (64-bit) */ +static void emit_shift_i64(struct jit_context *ctx, + const u8 dst[], u32 imm, u8 op) +{ + switch (BPF_OP(op)) { + /* dst = dst << imm */ + case BPF_LSH: + if (imm < 32) { + emit(ctx, srl, MIPS_R_T9, lo(dst), 32 - imm); + emit(ctx, sll, lo(dst), lo(dst), imm); + emit(ctx, sll, hi(dst), hi(dst), imm); + emit(ctx, or, hi(dst), hi(dst), MIPS_R_T9); + } else { + emit(ctx, sll, hi(dst), lo(dst), imm - 32); + emit(ctx, move, lo(dst), MIPS_R_ZERO); + } + break; + /* dst = dst >> imm */ + case BPF_RSH: + if (imm < 32) { + emit(ctx, sll, MIPS_R_T9, hi(dst), 32 - imm); + emit(ctx, srl, lo(dst), lo(dst), imm); + emit(ctx, srl, hi(dst), hi(dst), imm); + emit(ctx, or, lo(dst), lo(dst), MIPS_R_T9); + } else { + emit(ctx, srl, lo(dst), hi(dst), imm - 32); + emit(ctx, move, hi(dst), MIPS_R_ZERO); + } + break; + /* dst = dst >> imm (arithmetic) */ + case BPF_ARSH: + if (imm < 32) { + emit(ctx, sll, MIPS_R_T9, hi(dst), 32 - imm); + emit(ctx, srl, lo(dst), lo(dst), imm); + emit(ctx, sra, hi(dst), hi(dst), imm); + emit(ctx, or, lo(dst), lo(dst), MIPS_R_T9); + } else { + emit(ctx, sra, lo(dst), hi(dst), imm - 32); + emit(ctx, sra, hi(dst), hi(dst), 31); + } + break; + } + clobber_reg64(ctx, dst); +} + +/* ALU shift register (64-bit) */ +static void emit_shift_r64(struct jit_context *ctx, + const u8 dst[], u8 src, u8 op) +{ + u8 t1 = MIPS_R_T8; + u8 t2 = MIPS_R_T9; + + emit(ctx, andi, t1, src, 32); /* t1 = src & 32 */ + emit(ctx, beqz, t1, 16); /* PC += 16 if t1 == 0 */ + emit(ctx, nor, t2, src, MIPS_R_ZERO); /* t2 = ~src (delay slot) */ + + switch (BPF_OP(op)) { + /* dst = dst << src */ + case BPF_LSH: + /* Next: shift >= 32 */ + emit(ctx, sllv, hi(dst), lo(dst), src); /* dh = dl << src */ + emit(ctx, move, lo(dst), MIPS_R_ZERO); /* dl = 0 */ + emit(ctx, b, 20); /* PC += 20 */ + /* +16: shift < 32 */ + emit(ctx, srl, t1, lo(dst), 1); /* t1 = dl >> 1 */ + emit(ctx, srlv, t1, t1, t2); /* t1 = t1 >> t2 */ + emit(ctx, sllv, lo(dst), lo(dst), src); /* dl = dl << src */ + emit(ctx, sllv, hi(dst), hi(dst), src); /* dh = dh << src */ + emit(ctx, or, hi(dst), hi(dst), t1); /* dh = dh | t1 */ + break; + /* dst = dst >> src */ + case BPF_RSH: + /* Next: shift >= 32 */ + emit(ctx, srlv, lo(dst), hi(dst), src); /* dl = dh >> src */ + emit(ctx, move, hi(dst), MIPS_R_ZERO); /* dh = 0 */ + emit(ctx, b, 20); /* PC += 20 */ + /* +16: shift < 32 */ + emit(ctx, sll, t1, hi(dst), 1); /* t1 = dl << 1 */ + emit(ctx, sllv, t1, t1, t2); /* t1 = t1 << t2 */ + emit(ctx, srlv, lo(dst), lo(dst), src); /* dl = dl >> src */ + emit(ctx, srlv, hi(dst), hi(dst), src); /* dh = dh >> src */ + emit(ctx, or, lo(dst), lo(dst), t1); /* dl = dl | t1 */ + break; + /* dst = dst >> src (arithmetic) */ + case BPF_ARSH: + /* Next: shift >= 32 */ + emit(ctx, srav, lo(dst), hi(dst), src); /* dl = dh >>a src */ + emit(ctx, sra, hi(dst), hi(dst), 31); /* dh = dh >>a 31 */ + emit(ctx, b, 20); /* PC += 20 */ + /* +16: shift < 32 */ + emit(ctx, sll, t1, hi(dst), 1); /* t1 = dl << 1 */ + emit(ctx, sllv, t1, t1, t2); /* t1 = t1 << t2 */ + emit(ctx, srlv, lo(dst), lo(dst), src); /* dl = dl >>a src */ + emit(ctx, srav, hi(dst), hi(dst), src); /* dh = dh >> src */ + emit(ctx, or, lo(dst), lo(dst), t1); /* dl = dl | t1 */ + break; + } + + /* +20: Done */ + clobber_reg64(ctx, dst); +} + +/* ALU mul immediate (64x32-bit) */ +static void emit_mul_i64(struct jit_context *ctx, const u8 dst[], s32 imm) +{ + u8 src = MIPS_R_T6; + u8 tmp = MIPS_R_T9; + + switch (imm) { + /* dst = dst * 1 is a no-op */ + case 1: + break; + /* dst = dst * -1 */ + case -1: + emit_neg_i64(ctx, dst); + break; + case 0: + emit_mov_r(ctx, lo(dst), MIPS_R_ZERO); + emit_mov_r(ctx, hi(dst), MIPS_R_ZERO); + break; + /* Full 64x32 multiply */ + default: + /* hi(dst) = hi(dst) * src(imm) */ + emit_mov_i(ctx, src, imm); + if (cpu_has_mips32r1 || cpu_has_mips32r6) { + emit(ctx, mul, hi(dst), hi(dst), src); + } else { + emit(ctx, multu, hi(dst), src); + emit(ctx, mflo, hi(dst)); + } + + /* hi(dst) = hi(dst) - lo(dst) */ + if (imm < 0) + emit(ctx, subu, hi(dst), hi(dst), lo(dst)); + + /* tmp = lo(dst) * src(imm) >> 32 */ + /* lo(dst) = lo(dst) * src(imm) */ + if (cpu_has_mips32r6) { + emit(ctx, muhu, tmp, lo(dst), src); + emit(ctx, mulu, lo(dst), lo(dst), src); + } else { + emit(ctx, multu, lo(dst), src); + emit(ctx, mflo, lo(dst)); + emit(ctx, mfhi, tmp); + } + + /* hi(dst) += tmp */ + emit(ctx, addu, hi(dst), hi(dst), tmp); + clobber_reg64(ctx, dst); + break; + } +} + +/* ALU mul register (64x64-bit) */ +static void emit_mul_r64(struct jit_context *ctx, + const u8 dst[], const u8 src[]) +{ + u8 acc = MIPS_R_T8; + u8 tmp = MIPS_R_T9; + + /* acc = hi(dst) * lo(src) */ + if (cpu_has_mips32r1 || cpu_has_mips32r6) { + emit(ctx, mul, acc, hi(dst), lo(src)); + } else { + emit(ctx, multu, hi(dst), lo(src)); + emit(ctx, mflo, acc); + } + + /* tmp = lo(dst) * hi(src) */ + if (cpu_has_mips32r1 || cpu_has_mips32r6) { + emit(ctx, mul, tmp, lo(dst), hi(src)); + } else { + emit(ctx, multu, lo(dst), hi(src)); + emit(ctx, mflo, tmp); + } + + /* acc += tmp */ + emit(ctx, addu, acc, acc, tmp); + + /* tmp = lo(dst) * lo(src) >> 32 */ + /* lo(dst) = lo(dst) * lo(src) */ + if (cpu_has_mips32r6) { + emit(ctx, muhu, tmp, lo(dst), lo(src)); + emit(ctx, mulu, lo(dst), lo(dst), lo(src)); + } else { + emit(ctx, multu, lo(dst), lo(src)); + emit(ctx, mflo, lo(dst)); + emit(ctx, mfhi, tmp); + } + + /* hi(dst) = acc + tmp */ + emit(ctx, addu, hi(dst), acc, tmp); + clobber_reg64(ctx, dst); +} + +/* Helper function for 64-bit modulo */ +static u64 jit_mod64(u64 a, u64 b) +{ + u64 rem; + + div64_u64_rem(a, b, &rem); + return rem; +} + +/* ALU div/mod register (64-bit) */ +static void emit_divmod_r64(struct jit_context *ctx, + const u8 dst[], const u8 src[], u8 op) +{ + const u8 *r0 = bpf2mips32[BPF_REG_0]; /* Mapped to v0-v1 */ + const u8 *r1 = bpf2mips32[BPF_REG_1]; /* Mapped to a0-a1 */ + const u8 *r2 = bpf2mips32[BPF_REG_2]; /* Mapped to a2-a3 */ + int exclude, k; + u32 addr = 0; + + /* Push caller-saved registers on stack */ + push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + 0, JIT_RESERVED_STACK); + + /* Put 64-bit arguments 1 and 2 in registers a0-a3 */ + for (k = 0; k < 2; k++) { + emit(ctx, move, MIPS_R_T9, src[k]); + emit(ctx, move, r1[k], dst[k]); + emit(ctx, move, r2[k], MIPS_R_T9); + } + + /* Emit function call */ + switch (BPF_OP(op)) { + /* dst = dst / src */ + case BPF_DIV: + addr = (u32)&div64_u64; + break; + /* dst = dst % src */ + case BPF_MOD: + addr = (u32)&jit_mod64; + break; + } + emit_mov_i(ctx, MIPS_R_T9, addr); + emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); + emit(ctx, nop); /* Delay slot */ + + /* Store the 64-bit result in dst */ + emit(ctx, move, dst[0], r0[0]); + emit(ctx, move, dst[1], r0[1]); + + /* Restore caller-saved registers, excluding the computed result */ + exclude = BIT(lo(dst)) | BIT(hi(dst)); + pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + exclude, JIT_RESERVED_STACK); + emit_load_delay(ctx); + + clobber_reg64(ctx, dst); + clobber_reg(ctx, MIPS_R_V0); + clobber_reg(ctx, MIPS_R_V1); + clobber_reg(ctx, MIPS_R_RA); +} + +/* Swap bytes in a register word */ +static void emit_swap8_r(struct jit_context *ctx, u8 dst, u8 src, u8 mask) +{ + u8 tmp = MIPS_R_T9; + + emit(ctx, and, tmp, src, mask); /* tmp = src & 0x00ff00ff */ + emit(ctx, sll, tmp, tmp, 8); /* tmp = tmp << 8 */ + emit(ctx, srl, dst, src, 8); /* dst = src >> 8 */ + emit(ctx, and, dst, dst, mask); /* dst = dst & 0x00ff00ff */ + emit(ctx, or, dst, dst, tmp); /* dst = dst | tmp */ +} + +/* Swap half words in a register word */ +static void emit_swap16_r(struct jit_context *ctx, u8 dst, u8 src) +{ + u8 tmp = MIPS_R_T9; + + emit(ctx, sll, tmp, src, 16); /* tmp = src << 16 */ + emit(ctx, srl, dst, src, 16); /* dst = src >> 16 */ + emit(ctx, or, dst, dst, tmp); /* dst = dst | tmp */ +} + +/* Swap bytes and truncate a register double word, word or half word */ +static void emit_bswap_r64(struct jit_context *ctx, const u8 dst[], u32 width) +{ + u8 tmp = MIPS_R_T8; + + switch (width) { + /* Swap bytes in a double word */ + case 64: + if (cpu_has_mips32r2 || cpu_has_mips32r6) { + emit(ctx, rotr, tmp, hi(dst), 16); + emit(ctx, rotr, hi(dst), lo(dst), 16); + emit(ctx, wsbh, lo(dst), tmp); + emit(ctx, wsbh, hi(dst), hi(dst)); + } else { + emit_swap16_r(ctx, tmp, lo(dst)); + emit_swap16_r(ctx, lo(dst), hi(dst)); + emit(ctx, move, hi(dst), tmp); + + emit(ctx, lui, tmp, 0xff); /* tmp = 0x00ff0000 */ + emit(ctx, ori, tmp, tmp, 0xff); /* tmp = 0x00ff00ff */ + emit_swap8_r(ctx, lo(dst), lo(dst), tmp); + emit_swap8_r(ctx, hi(dst), hi(dst), tmp); + } + break; + /* Swap bytes in a word */ + /* Swap bytes in a half word */ + case 32: + case 16: + emit_bswap_r(ctx, lo(dst), width); + emit(ctx, move, hi(dst), MIPS_R_ZERO); + break; + } + clobber_reg64(ctx, dst); +} + +/* Truncate a register double word, word or half word */ +static void emit_trunc_r64(struct jit_context *ctx, const u8 dst[], u32 width) +{ + switch (width) { + case 64: + break; + /* Zero-extend a word */ + case 32: + emit(ctx, move, hi(dst), MIPS_R_ZERO); + clobber_reg(ctx, hi(dst)); + break; + /* Zero-extend a half word */ + case 16: + emit(ctx, move, hi(dst), MIPS_R_ZERO); + emit(ctx, andi, lo(dst), lo(dst), 0xffff); + clobber_reg64(ctx, dst); + break; + } +} + +/* Load operation: dst = *(size*)(src + off) */ +static void emit_ldx(struct jit_context *ctx, + const u8 dst[], u8 src, s16 off, u8 size) +{ + switch (size) { + /* Load a byte */ + case BPF_B: + emit(ctx, lbu, lo(dst), off, src); + emit(ctx, move, hi(dst), MIPS_R_ZERO); + break; + /* Load a half word */ + case BPF_H: + emit(ctx, lhu, lo(dst), off, src); + emit(ctx, move, hi(dst), MIPS_R_ZERO); + break; + /* Load a word */ + case BPF_W: + emit(ctx, lw, lo(dst), off, src); + emit(ctx, move, hi(dst), MIPS_R_ZERO); + break; + /* Load a double word */ + case BPF_DW: + if (dst[1] == src) { + emit(ctx, lw, dst[0], off + 4, src); + emit(ctx, lw, dst[1], off, src); + } else { + emit(ctx, lw, dst[1], off, src); + emit(ctx, lw, dst[0], off + 4, src); + } + emit_load_delay(ctx); + break; + } + clobber_reg64(ctx, dst); +} + +/* Store operation: *(size *)(dst + off) = src */ +static void emit_stx(struct jit_context *ctx, + const u8 dst, const u8 src[], s16 off, u8 size) +{ + switch (size) { + /* Store a byte */ + case BPF_B: + emit(ctx, sb, lo(src), off, dst); + break; + /* Store a half word */ + case BPF_H: + emit(ctx, sh, lo(src), off, dst); + break; + /* Store a word */ + case BPF_W: + emit(ctx, sw, lo(src), off, dst); + break; + /* Store a double word */ + case BPF_DW: + emit(ctx, sw, src[1], off, dst); + emit(ctx, sw, src[0], off + 4, dst); + break; + } +} + +/* Atomic read-modify-write (32-bit, non-ll/sc fallback) */ +static void emit_atomic_r32(struct jit_context *ctx, + u8 dst, u8 src, s16 off, u8 code) +{ + u32 exclude = 0; + u32 addr = 0; + + /* Push caller-saved registers on stack */ + push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + 0, JIT_RESERVED_STACK); + /* + * Argument 1: dst+off if xchg, otherwise src, passed in register a0 + * Argument 2: src if xchg, othersize dst+off, passed in register a1 + */ + emit(ctx, move, MIPS_R_T9, dst); + if (code == BPF_XCHG) { + emit(ctx, move, MIPS_R_A1, src); + emit(ctx, addiu, MIPS_R_A0, MIPS_R_T9, off); + } else { + emit(ctx, move, MIPS_R_A0, src); + emit(ctx, addiu, MIPS_R_A1, MIPS_R_T9, off); + } + + /* Emit function call */ + switch (code) { + case BPF_ADD: + addr = (u32)&atomic_add; + break; + case BPF_ADD | BPF_FETCH: + addr = (u32)&atomic_fetch_add; + break; + case BPF_SUB: + addr = (u32)&atomic_sub; + break; + case BPF_SUB | BPF_FETCH: + addr = (u32)&atomic_fetch_sub; + break; + case BPF_OR: + addr = (u32)&atomic_or; + break; + case BPF_OR | BPF_FETCH: + addr = (u32)&atomic_fetch_or; + break; + case BPF_AND: + addr = (u32)&atomic_and; + break; + case BPF_AND | BPF_FETCH: + addr = (u32)&atomic_fetch_and; + break; + case BPF_XOR: + addr = (u32)&atomic_xor; + break; + case BPF_XOR | BPF_FETCH: + addr = (u32)&atomic_fetch_xor; + break; + case BPF_XCHG: + addr = (u32)&atomic_xchg; + break; + } + emit_mov_i(ctx, MIPS_R_T9, addr); + emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); + emit(ctx, nop); /* Delay slot */ + + /* Update src register with old value, if specified */ + if (code & BPF_FETCH) { + emit(ctx, move, src, MIPS_R_V0); + exclude = BIT(src); + clobber_reg(ctx, src); + } + + /* Restore caller-saved registers, except any fetched value */ + pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + exclude, JIT_RESERVED_STACK); + emit_load_delay(ctx); + clobber_reg(ctx, MIPS_R_RA); +} + +/* Helper function for 64-bit atomic exchange */ +static s64 jit_xchg64(s64 a, atomic64_t *v) +{ + return atomic64_xchg(v, a); +} + +/* Atomic read-modify-write (64-bit) */ +static void emit_atomic_r64(struct jit_context *ctx, + u8 dst, const u8 src[], s16 off, u8 code) +{ + const u8 *r0 = bpf2mips32[BPF_REG_0]; /* Mapped to v0-v1 */ + const u8 *r1 = bpf2mips32[BPF_REG_1]; /* Mapped to a0-a1 */ + u32 exclude = 0; + u32 addr = 0; + + /* Push caller-saved registers on stack */ + push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + 0, JIT_RESERVED_STACK); + /* + * Argument 1: 64-bit src, passed in registers a0-a1 + * Argument 2: 32-bit dst+off, passed in register a2 + */ + emit(ctx, move, MIPS_R_T9, dst); + emit(ctx, move, r1[0], src[0]); + emit(ctx, move, r1[1], src[1]); + emit(ctx, addiu, MIPS_R_A2, MIPS_R_T9, off); + + /* Emit function call */ + switch (code) { + case BPF_ADD: + addr = (u32)&atomic64_add; + break; + case BPF_ADD | BPF_FETCH: + addr = (u32)&atomic64_fetch_add; + break; + case BPF_SUB: + addr = (u32)&atomic64_sub; + break; + case BPF_SUB | BPF_FETCH: + addr = (u32)&atomic64_fetch_sub; + break; + case BPF_OR: + addr = (u32)&atomic64_or; + break; + case BPF_OR | BPF_FETCH: + addr = (u32)&atomic64_fetch_or; + break; + case BPF_AND: + addr = (u32)&atomic64_and; + break; + case BPF_AND | BPF_FETCH: + addr = (u32)&atomic64_fetch_and; + break; + case BPF_XOR: + addr = (u32)&atomic64_xor; + break; + case BPF_XOR | BPF_FETCH: + addr = (u32)&atomic64_fetch_xor; + break; + case BPF_XCHG: + addr = (u32)&jit_xchg64; + break; + } + emit_mov_i(ctx, MIPS_R_T9, addr); + emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); + emit(ctx, nop); /* Delay slot */ + + /* Update src register with old value, if specified */ + if (code & BPF_FETCH) { + emit(ctx, move, lo(src), lo(r0)); + emit(ctx, move, hi(src), hi(r0)); + exclude = BIT(src[0]) | BIT(src[1]); + clobber_reg64(ctx, src); + } + + /* Restore caller-saved registers, except any fetched value */ + pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + exclude, JIT_RESERVED_STACK); + emit_load_delay(ctx); + clobber_reg(ctx, MIPS_R_RA); +} + +/* Atomic compare-and-exchange (32-bit, non-ll/sc fallback) */ +static void emit_cmpxchg_r32(struct jit_context *ctx, u8 dst, u8 src, s16 off) +{ + const u8 *r0 = bpf2mips32[BPF_REG_0]; + + /* Push caller-saved registers on stack */ + push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + JIT_RETURN_REGS, JIT_RESERVED_STACK + 2 * sizeof(u32)); + /* + * Argument 1: 32-bit dst+off, passed in register a0 + * Argument 2: 32-bit r0, passed in register a1 + * Argument 3: 32-bit src, passed in register a2 + */ + emit(ctx, addiu, MIPS_R_T9, dst, off); + emit(ctx, move, MIPS_R_T8, src); + emit(ctx, move, MIPS_R_A1, lo(r0)); + emit(ctx, move, MIPS_R_A0, MIPS_R_T9); + emit(ctx, move, MIPS_R_A2, MIPS_R_T8); + + /* Emit function call */ + emit_mov_i(ctx, MIPS_R_T9, (u32)&atomic_cmpxchg); + emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); + emit(ctx, nop); /* Delay slot */ + +#ifdef __BIG_ENDIAN + emit(ctx, move, lo(r0), MIPS_R_V0); +#endif + /* Restore caller-saved registers, except the return value */ + pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + JIT_RETURN_REGS, JIT_RESERVED_STACK + 2 * sizeof(u32)); + emit_load_delay(ctx); + clobber_reg(ctx, MIPS_R_V0); + clobber_reg(ctx, MIPS_R_V1); + clobber_reg(ctx, MIPS_R_RA); +} + +/* Atomic compare-and-exchange (64-bit) */ +static void emit_cmpxchg_r64(struct jit_context *ctx, + u8 dst, const u8 src[], s16 off) +{ + const u8 *r0 = bpf2mips32[BPF_REG_0]; + const u8 *r2 = bpf2mips32[BPF_REG_2]; + + /* Push caller-saved registers on stack */ + push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + JIT_RETURN_REGS, JIT_RESERVED_STACK + 2 * sizeof(u32)); + /* + * Argument 1: 32-bit dst+off, passed in register a0 (a1 unused) + * Argument 2: 64-bit r0, passed in registers a2-a3 + * Argument 3: 64-bit src, passed on stack + */ + push_regs(ctx, BIT(src[0]) | BIT(src[1]), 0, JIT_RESERVED_STACK); + emit(ctx, addiu, MIPS_R_T9, dst, off); + emit(ctx, move, r2[0], r0[0]); + emit(ctx, move, r2[1], r0[1]); + emit(ctx, move, MIPS_R_A0, MIPS_R_T9); + + /* Emit function call */ + emit_mov_i(ctx, MIPS_R_T9, (u32)&atomic64_cmpxchg); + emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); + emit(ctx, nop); /* Delay slot */ + + /* Restore caller-saved registers, except the return value */ + pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, + JIT_RETURN_REGS, JIT_RESERVED_STACK + 2 * sizeof(u32)); + emit_load_delay(ctx); + clobber_reg(ctx, MIPS_R_V0); + clobber_reg(ctx, MIPS_R_V1); + clobber_reg(ctx, MIPS_R_RA); +} + +/* + * Conditional movz or an emulated equivalent. + * Note that the rs register may be modified. + */ +static void emit_movz_r(struct jit_context *ctx, u8 rd, u8 rs, u8 rt) +{ + if (cpu_has_mips_2) { + emit(ctx, movz, rd, rs, rt); /* rd = rt ? rd : rs */ + } else if (cpu_has_mips32r6) { + if (rs != MIPS_R_ZERO) + emit(ctx, seleqz, rs, rs, rt); /* rs = 0 if rt == 0 */ + emit(ctx, selnez, rd, rd, rt); /* rd = 0 if rt != 0 */ + if (rs != MIPS_R_ZERO) + emit(ctx, or, rd, rd, rs); /* rd = rd | rs */ + } else { + emit(ctx, bnez, rt, 8); /* PC += 8 if rd != 0 */ + emit(ctx, nop); /* +0: delay slot */ + emit(ctx, or, rd, rs, MIPS_R_ZERO); /* +4: rd = rs */ + } + clobber_reg(ctx, rd); + clobber_reg(ctx, rs); +} + +/* + * Conditional movn or an emulated equivalent. + * Note that the rs register may be modified. + */ +static void emit_movn_r(struct jit_context *ctx, u8 rd, u8 rs, u8 rt) +{ + if (cpu_has_mips_2) { + emit(ctx, movn, rd, rs, rt); /* rd = rt ? rs : rd */ + } else if (cpu_has_mips32r6) { + if (rs != MIPS_R_ZERO) + emit(ctx, selnez, rs, rs, rt); /* rs = 0 if rt == 0 */ + emit(ctx, seleqz, rd, rd, rt); /* rd = 0 if rt != 0 */ + if (rs != MIPS_R_ZERO) + emit(ctx, or, rd, rd, rs); /* rd = rd | rs */ + } else { + emit(ctx, beqz, rt, 8); /* PC += 8 if rd == 0 */ + emit(ctx, nop); /* +0: delay slot */ + emit(ctx, or, rd, rs, MIPS_R_ZERO); /* +4: rd = rs */ + } + clobber_reg(ctx, rd); + clobber_reg(ctx, rs); +} + +/* Emulation of 64-bit sltiu rd, rs, imm, where imm may be S32_MAX + 1 */ +static void emit_sltiu_r64(struct jit_context *ctx, u8 rd, + const u8 rs[], s64 imm) +{ + u8 tmp = MIPS_R_T9; + + if (imm < 0) { + emit_mov_i(ctx, rd, imm); /* rd = imm */ + emit(ctx, sltu, rd, lo(rs), rd); /* rd = rsl < rd */ + emit(ctx, sltiu, tmp, hi(rs), -1); /* tmp = rsh < ~0U */ + emit(ctx, or, rd, rd, tmp); /* rd = rd | tmp */ + } else { /* imm >= 0 */ + if (imm > 0x7fff) { + emit_mov_i(ctx, rd, (s32)imm); /* rd = imm */ + emit(ctx, sltu, rd, lo(rs), rd); /* rd = rsl < rd */ + } else { + emit(ctx, sltiu, rd, lo(rs), imm); /* rd = rsl < imm */ + } + emit_movn_r(ctx, rd, MIPS_R_ZERO, hi(rs)); /* rd = 0 if rsh */ + } +} + +/* Emulation of 64-bit sltu rd, rs, rt */ +static void emit_sltu_r64(struct jit_context *ctx, u8 rd, + const u8 rs[], const u8 rt[]) +{ + u8 tmp = MIPS_R_T9; + + emit(ctx, sltu, rd, lo(rs), lo(rt)); /* rd = rsl < rtl */ + emit(ctx, subu, tmp, hi(rs), hi(rt)); /* tmp = rsh - rth */ + emit_movn_r(ctx, rd, MIPS_R_ZERO, tmp); /* rd = 0 if tmp != 0 */ + emit(ctx, sltu, tmp, hi(rs), hi(rt)); /* tmp = rsh < rth */ + emit(ctx, or, rd, rd, tmp); /* rd = rd | tmp */ +} + +/* Emulation of 64-bit slti rd, rs, imm, where imm may be S32_MAX + 1 */ +static void emit_slti_r64(struct jit_context *ctx, u8 rd, + const u8 rs[], s64 imm) +{ + u8 t1 = MIPS_R_T8; + u8 t2 = MIPS_R_T9; + u8 cmp; + + /* + * if ((rs < 0) ^ (imm < 0)) t1 = imm >u rsl + * else t1 = rsl <u imm + */ + emit_mov_i(ctx, rd, (s32)imm); + emit(ctx, sltu, t1, lo(rs), rd); /* t1 = rsl <u imm */ + emit(ctx, sltu, t2, rd, lo(rs)); /* t2 = imm <u rsl */ + emit(ctx, srl, rd, hi(rs), 31); /* rd = rsh >> 31 */ + if (imm < 0) + emit_movz_r(ctx, t1, t2, rd); /* t1 = rd ? t1 : t2 */ + else + emit_movn_r(ctx, t1, t2, rd); /* t1 = rd ? t2 : t1 */ + /* + * if ((imm < 0 && rsh != 0xffffffff) || + * (imm >= 0 && rsh != 0)) + * t1 = 0 + */ + if (imm < 0) { + emit(ctx, addiu, rd, hi(rs), 1); /* rd = rsh + 1 */ + cmp = rd; + } else { /* imm >= 0 */ + cmp = hi(rs); + } + emit_movn_r(ctx, t1, MIPS_R_ZERO, cmp); /* t1 = 0 if cmp != 0 */ + + /* + * if (imm < 0) rd = rsh < -1 + * else rd = rsh != 0 + * rd = rd | t1 + */ + emit(ctx, slti, rd, hi(rs), imm < 0 ? -1 : 0); /* rd = rsh < hi(imm) */ + emit(ctx, or, rd, rd, t1); /* rd = rd | t1 */ +} + +/* Emulation of 64-bit(slt rd, rs, rt) */ +static void emit_slt_r64(struct jit_context *ctx, u8 rd, + const u8 rs[], const u8 rt[]) +{ + u8 t1 = MIPS_R_T7; + u8 t2 = MIPS_R_T8; + u8 t3 = MIPS_R_T9; + + /* + * if ((rs < 0) ^ (rt < 0)) t1 = rtl <u rsl + * else t1 = rsl <u rtl + * if (rsh == rth) t1 = 0 + */ + emit(ctx, sltu, t1, lo(rs), lo(rt)); /* t1 = rsl <u rtl */ + emit(ctx, sltu, t2, lo(rt), lo(rs)); /* t2 = rtl <u rsl */ + emit(ctx, xor, t3, hi(rs), hi(rt)); /* t3 = rlh ^ rth */ + emit(ctx, srl, rd, t3, 31); /* rd = t3 >> 31 */ + emit_movn_r(ctx, t1, t2, rd); /* t1 = rd ? t2 : t1 */ + emit_movn_r(ctx, t1, MIPS_R_ZERO, t3); /* t1 = 0 if t3 != 0 */ + + /* rd = (rsh < rth) | t1 */ + emit(ctx, slt, rd, hi(rs), hi(rt)); /* rd = rsh <s rth */ + emit(ctx, or, rd, rd, t1); /* rd = rd | t1 */ +} + +/* Jump immediate (64-bit) */ +static void emit_jmp_i64(struct jit_context *ctx, + const u8 dst[], s32 imm, s32 off, u8 op) +{ + u8 tmp = MIPS_R_T6; + + switch (op) { + /* No-op, used internally for branch optimization */ + case JIT_JNOP: + break; + /* PC += off if dst == imm */ + /* PC += off if dst != imm */ + case BPF_JEQ: + case BPF_JNE: + if (imm >= -0x7fff && imm <= 0x8000) { + emit(ctx, addiu, tmp, lo(dst), -imm); + } else if ((u32)imm <= 0xffff) { + emit(ctx, xori, tmp, lo(dst), imm); + } else { /* Register fallback */ + emit_mov_i(ctx, tmp, imm); + emit(ctx, xor, tmp, lo(dst), tmp); + } + if (imm < 0) { /* Compare sign extension */ + emit(ctx, addu, MIPS_R_T9, hi(dst), 1); + emit(ctx, or, tmp, tmp, MIPS_R_T9); + } else { /* Compare zero extension */ + emit(ctx, or, tmp, tmp, hi(dst)); + } + if (op == BPF_JEQ) + emit(ctx, beqz, tmp, off); + else /* BPF_JNE */ + emit(ctx, bnez, tmp, off); + break; + /* PC += off if dst & imm */ + /* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */ + case BPF_JSET: + case JIT_JNSET: + if ((u32)imm <= 0xffff) { + emit(ctx, andi, tmp, lo(dst), imm); + } else { /* Register fallback */ + emit_mov_i(ctx, tmp, imm); + emit(ctx, and, tmp, lo(dst), tmp); + } + if (imm < 0) /* Sign-extension pulls in high word */ + emit(ctx, or, tmp, tmp, hi(dst)); + if (op == BPF_JSET) + emit(ctx, bnez, tmp, off); + else /* JIT_JNSET */ + emit(ctx, beqz, tmp, off); + break; + /* PC += off if dst > imm */ + case BPF_JGT: + emit_sltiu_r64(ctx, tmp, dst, (s64)imm + 1); + emit(ctx, beqz, tmp, off); + break; + /* PC += off if dst >= imm */ + case BPF_JGE: + emit_sltiu_r64(ctx, tmp, dst, imm); + emit(ctx, beqz, tmp, off); + break; + /* PC += off if dst < imm */ + case BPF_JLT: + emit_sltiu_r64(ctx, tmp, dst, imm); + emit(ctx, bnez, tmp, off); + break; + /* PC += off if dst <= imm */ + case BPF_JLE: + emit_sltiu_r64(ctx, tmp, dst, (s64)imm + 1); + emit(ctx, bnez, tmp, off); + break; + /* PC += off if dst > imm (signed) */ + case BPF_JSGT: + emit_slti_r64(ctx, tmp, dst, (s64)imm + 1); + emit(ctx, beqz, tmp, off); + break; + /* PC += off if dst >= imm (signed) */ + case BPF_JSGE: + emit_slti_r64(ctx, tmp, dst, imm); + emit(ctx, beqz, tmp, off); + break; + /* PC += off if dst < imm (signed) */ + case BPF_JSLT: + emit_slti_r64(ctx, tmp, dst, imm); + emit(ctx, bnez, tmp, off); + break; + /* PC += off if dst <= imm (signed) */ + case BPF_JSLE: + emit_slti_r64(ctx, tmp, dst, (s64)imm + 1); + emit(ctx, bnez, tmp, off); + break; + } +} + +/* Jump register (64-bit) */ +static void emit_jmp_r64(struct jit_context *ctx, + const u8 dst[], const u8 src[], s32 off, u8 op) +{ + u8 t1 = MIPS_R_T6; + u8 t2 = MIPS_R_T7; + + switch (op) { + /* No-op, used internally for branch optimization */ + case JIT_JNOP: + break; + /* PC += off if dst == src */ + /* PC += off if dst != src */ + case BPF_JEQ: + case BPF_JNE: + emit(ctx, subu, t1, lo(dst), lo(src)); + emit(ctx, subu, t2, hi(dst), hi(src)); + emit(ctx, or, t1, t1, t2); + if (op == BPF_JEQ) + emit(ctx, beqz, t1, off); + else /* BPF_JNE */ + emit(ctx, bnez, t1, off); + break; + /* PC += off if dst & src */ + /* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */ + case BPF_JSET: + case JIT_JNSET: + emit(ctx, and, t1, lo(dst), lo(src)); + emit(ctx, and, t2, hi(dst), hi(src)); + emit(ctx, or, t1, t1, t2); + if (op == BPF_JSET) + emit(ctx, bnez, t1, off); + else /* JIT_JNSET */ + emit(ctx, beqz, t1, off); + break; + /* PC += off if dst > src */ + case BPF_JGT: + emit_sltu_r64(ctx, t1, src, dst); + emit(ctx, bnez, t1, off); + break; + /* PC += off if dst >= src */ + case BPF_JGE: + emit_sltu_r64(ctx, t1, dst, src); + emit(ctx, beqz, t1, off); + break; + /* PC += off if dst < src */ + case BPF_JLT: + emit_sltu_r64(ctx, t1, dst, src); + emit(ctx, bnez, t1, off); + break; + /* PC += off if dst <= src */ + case BPF_JLE: + emit_sltu_r64(ctx, t1, src, dst); + emit(ctx, beqz, t1, off); + break; + /* PC += off if dst > src (signed) */ + case BPF_JSGT: + emit_slt_r64(ctx, t1, src, dst); + emit(ctx, bnez, t1, off); + break; + /* PC += off if dst >= src (signed) */ + case BPF_JSGE: + emit_slt_r64(ctx, t1, dst, src); + emit(ctx, beqz, t1, off); + break; + /* PC += off if dst < src (signed) */ + case BPF_JSLT: + emit_slt_r64(ctx, t1, dst, src); + emit(ctx, bnez, t1, off); + break; + /* PC += off if dst <= src (signed) */ + case BPF_JSLE: + emit_slt_r64(ctx, t1, src, dst); + emit(ctx, beqz, t1, off); + break; + } +} + +/* Function call */ +static int emit_call(struct jit_context *ctx, const struct bpf_insn *insn) +{ + bool fixed; + u64 addr; + + /* Decode the call address */ + if (bpf_jit_get_func_addr(ctx->program, insn, false, + &addr, &fixed) < 0) + return -1; + if (!fixed) + return -1; + + /* Push stack arguments */ + push_regs(ctx, JIT_STACK_REGS, 0, JIT_RESERVED_STACK); + + /* Emit function call */ + emit_mov_i(ctx, MIPS_R_T9, addr); + emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); + emit(ctx, nop); /* Delay slot */ + + clobber_reg(ctx, MIPS_R_RA); + clobber_reg(ctx, MIPS_R_V0); + clobber_reg(ctx, MIPS_R_V1); + return 0; +} + +/* Function tail call */ +static int emit_tail_call(struct jit_context *ctx) +{ + u8 ary = lo(bpf2mips32[BPF_REG_2]); + u8 ind = lo(bpf2mips32[BPF_REG_3]); + u8 t1 = MIPS_R_T8; + u8 t2 = MIPS_R_T9; + int off; + + /* + * Tail call: + * eBPF R1 - function argument (context ptr), passed in a0-a1 + * eBPF R2 - ptr to object with array of function entry points + * eBPF R3 - array index of function to be called + * stack[sz] - remaining tail call count, initialized in prologue + */ + + /* if (ind >= ary->map.max_entries) goto out */ + off = offsetof(struct bpf_array, map.max_entries); + if (off > 0x7fff) + return -1; + emit(ctx, lw, t1, off, ary); /* t1 = ary->map.max_entries*/ + emit_load_delay(ctx); /* Load delay slot */ + emit(ctx, sltu, t1, ind, t1); /* t1 = ind < t1 */ + emit(ctx, beqz, t1, get_offset(ctx, 1)); /* PC += off(1) if t1 == 0 */ + /* (next insn delay slot) */ + /* if (TCC-- <= 0) goto out */ + emit(ctx, lw, t2, ctx->stack_size, MIPS_R_SP); /* t2 = *(SP + size) */ + emit_load_delay(ctx); /* Load delay slot */ + emit(ctx, blez, t2, get_offset(ctx, 1)); /* PC += off(1) if t2 <= 0 */ + emit(ctx, addiu, t2, t2, -1); /* t2-- (delay slot) */ + emit(ctx, sw, t2, ctx->stack_size, MIPS_R_SP); /* *(SP + size) = t2 */ + + /* prog = ary->ptrs[ind] */ + off = offsetof(struct bpf_array, ptrs); + if (off > 0x7fff) + return -1; + emit(ctx, sll, t1, ind, 2); /* t1 = ind << 2 */ + emit(ctx, addu, t1, t1, ary); /* t1 += ary */ + emit(ctx, lw, t2, off, t1); /* t2 = *(t1 + off) */ + emit_load_delay(ctx); /* Load delay slot */ + + /* if (prog == 0) goto out */ + emit(ctx, beqz, t2, get_offset(ctx, 1)); /* PC += off(1) if t2 == 0 */ + emit(ctx, nop); /* Delay slot */ + + /* func = prog->bpf_func + 8 (prologue skip offset) */ + off = offsetof(struct bpf_prog, bpf_func); + if (off > 0x7fff) + return -1; + emit(ctx, lw, t1, off, t2); /* t1 = *(t2 + off) */ + emit_load_delay(ctx); /* Load delay slot */ + emit(ctx, addiu, t1, t1, JIT_TCALL_SKIP); /* t1 += skip (8 or 12) */ + + /* goto func */ + build_epilogue(ctx, t1); + return 0; +} + +/* + * Stack frame layout for a JITed program (stack grows down). + * + * Higher address : Caller's stack frame : + * :----------------------------: + * : 64-bit eBPF args r3-r5 : + * :----------------------------: + * : Reserved / tail call count : + * +============================+ <--- MIPS sp before call + * | Callee-saved registers, | + * | including RA and FP | + * +----------------------------+ <--- eBPF FP (MIPS zero,fp) + * | Local eBPF variables | + * | allocated by program | + * +----------------------------+ + * | Reserved for caller-saved | + * | registers | + * +----------------------------+ + * | Reserved for 64-bit eBPF | + * | args r3-r5 & args passed | + * | on stack in kernel calls | + * Lower address +============================+ <--- MIPS sp + */ + +/* Build program prologue to set up the stack and registers */ +void build_prologue(struct jit_context *ctx) +{ + const u8 *r1 = bpf2mips32[BPF_REG_1]; + const u8 *fp = bpf2mips32[BPF_REG_FP]; + int stack, saved, locals, reserved; + + /* + * The first two instructions initialize TCC in the reserved (for us) + * 16-byte area in the parent's stack frame. On a tail call, the + * calling function jumps into the prologue after these instructions. + */ + emit(ctx, ori, MIPS_R_T9, MIPS_R_ZERO, + min(MAX_TAIL_CALL_CNT + 1, 0xffff)); + emit(ctx, sw, MIPS_R_T9, 0, MIPS_R_SP); + + /* + * Register eBPF R1 contains the 32-bit context pointer argument. + * A 32-bit argument is always passed in MIPS register a0, regardless + * of CPU endianness. Initialize R1 accordingly and zero-extend. + */ +#ifdef __BIG_ENDIAN + emit(ctx, move, lo(r1), MIPS_R_A0); +#endif + + /* === Entry-point for tail calls === */ + + /* Zero-extend the 32-bit argument */ + emit(ctx, move, hi(r1), MIPS_R_ZERO); + + /* If the eBPF frame pointer was accessed it must be saved */ + if (ctx->accessed & BIT(BPF_REG_FP)) + clobber_reg64(ctx, fp); + + /* Compute the stack space needed for callee-saved registers */ + saved = hweight32(ctx->clobbered & JIT_CALLEE_REGS) * sizeof(u32); + saved = ALIGN(saved, MIPS_STACK_ALIGNMENT); + + /* Stack space used by eBPF program local data */ + locals = ALIGN(ctx->program->aux->stack_depth, MIPS_STACK_ALIGNMENT); + + /* + * If we are emitting function calls, reserve extra stack space for + * caller-saved registers and function arguments passed on the stack. + * The required space is computed automatically during resource + * usage discovery (pass 1). + */ + reserved = ctx->stack_used; + + /* Allocate the stack frame */ + stack = ALIGN(saved + locals + reserved, MIPS_STACK_ALIGNMENT); + emit(ctx, addiu, MIPS_R_SP, MIPS_R_SP, -stack); + + /* Store callee-saved registers on stack */ + push_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, stack - saved); + + /* Initialize the eBPF frame pointer if accessed */ + if (ctx->accessed & BIT(BPF_REG_FP)) + emit(ctx, addiu, lo(fp), MIPS_R_SP, stack - saved); + + ctx->saved_size = saved; + ctx->stack_size = stack; +} + +/* Build the program epilogue to restore the stack and registers */ +void build_epilogue(struct jit_context *ctx, int dest_reg) +{ + /* Restore callee-saved registers from stack */ + pop_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, + ctx->stack_size - ctx->saved_size); + /* + * A 32-bit return value is always passed in MIPS register v0, + * but on big-endian targets the low part of R0 is mapped to v1. + */ +#ifdef __BIG_ENDIAN + emit(ctx, move, MIPS_R_V0, MIPS_R_V1); +#endif + + /* Jump to the return address and adjust the stack pointer */ + emit(ctx, jr, dest_reg); + emit(ctx, addiu, MIPS_R_SP, MIPS_R_SP, ctx->stack_size); +} + +/* Build one eBPF instruction */ +int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) +{ + const u8 *dst = bpf2mips32[insn->dst_reg]; + const u8 *src = bpf2mips32[insn->src_reg]; + const u8 *res = bpf2mips32[BPF_REG_0]; + const u8 *tmp = bpf2mips32[JIT_REG_TMP]; + u8 code = insn->code; + s16 off = insn->off; + s32 imm = insn->imm; + s32 val, rel; + u8 alu, jmp; + + switch (code) { + /* ALU operations */ + /* dst = imm */ + case BPF_ALU | BPF_MOV | BPF_K: + emit_mov_i(ctx, lo(dst), imm); + emit_zext_ver(ctx, dst); + break; + /* dst = src */ + case BPF_ALU | BPF_MOV | BPF_X: + if (imm == 1) { + /* Special mov32 for zext */ + emit_mov_i(ctx, hi(dst), 0); + } else { + emit_mov_r(ctx, lo(dst), lo(src)); + emit_zext_ver(ctx, dst); + } + break; + /* dst = -dst */ + case BPF_ALU | BPF_NEG: + emit_alu_i(ctx, lo(dst), 0, BPF_NEG); + emit_zext_ver(ctx, dst); + break; + /* dst = dst & imm */ + /* dst = dst | imm */ + /* dst = dst ^ imm */ + /* dst = dst << imm */ + /* dst = dst >> imm */ + /* dst = dst >> imm (arithmetic) */ + /* dst = dst + imm */ + /* dst = dst - imm */ + /* dst = dst * imm */ + /* dst = dst / imm */ + /* dst = dst % imm */ + case BPF_ALU | BPF_OR | BPF_K: + case BPF_ALU | BPF_AND | BPF_K: + case BPF_ALU | BPF_XOR | BPF_K: + case BPF_ALU | BPF_LSH | BPF_K: + case BPF_ALU | BPF_RSH | BPF_K: + case BPF_ALU | BPF_ARSH | BPF_K: + case BPF_ALU | BPF_ADD | BPF_K: + case BPF_ALU | BPF_SUB | BPF_K: + case BPF_ALU | BPF_MUL | BPF_K: + case BPF_ALU | BPF_DIV | BPF_K: + case BPF_ALU | BPF_MOD | BPF_K: + if (!valid_alu_i(BPF_OP(code), imm)) { + emit_mov_i(ctx, MIPS_R_T6, imm); + emit_alu_r(ctx, lo(dst), MIPS_R_T6, BPF_OP(code)); + } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { + emit_alu_i(ctx, lo(dst), val, alu); + } + emit_zext_ver(ctx, dst); + break; + /* dst = dst & src */ + /* dst = dst | src */ + /* dst = dst ^ src */ + /* dst = dst << src */ + /* dst = dst >> src */ + /* dst = dst >> src (arithmetic) */ + /* dst = dst + src */ + /* dst = dst - src */ + /* dst = dst * src */ + /* dst = dst / src */ + /* dst = dst % src */ + case BPF_ALU | BPF_AND | BPF_X: + case BPF_ALU | BPF_OR | BPF_X: + case BPF_ALU | BPF_XOR | BPF_X: + case BPF_ALU | BPF_LSH | BPF_X: + case BPF_ALU | BPF_RSH | BPF_X: + case BPF_ALU | BPF_ARSH | BPF_X: + case BPF_ALU | BPF_ADD | BPF_X: + case BPF_ALU | BPF_SUB | BPF_X: + case BPF_ALU | BPF_MUL | BPF_X: + case BPF_ALU | BPF_DIV | BPF_X: + case BPF_ALU | BPF_MOD | BPF_X: + emit_alu_r(ctx, lo(dst), lo(src), BPF_OP(code)); + emit_zext_ver(ctx, dst); + break; + /* dst = imm (64-bit) */ + case BPF_ALU64 | BPF_MOV | BPF_K: + emit_mov_se_i64(ctx, dst, imm); + break; + /* dst = src (64-bit) */ + case BPF_ALU64 | BPF_MOV | BPF_X: + emit_mov_r(ctx, lo(dst), lo(src)); + emit_mov_r(ctx, hi(dst), hi(src)); + break; + /* dst = -dst (64-bit) */ + case BPF_ALU64 | BPF_NEG: + emit_neg_i64(ctx, dst); + break; + /* dst = dst & imm (64-bit) */ + case BPF_ALU64 | BPF_AND | BPF_K: + emit_alu_i64(ctx, dst, imm, BPF_OP(code)); + break; + /* dst = dst | imm (64-bit) */ + /* dst = dst ^ imm (64-bit) */ + /* dst = dst + imm (64-bit) */ + /* dst = dst - imm (64-bit) */ + case BPF_ALU64 | BPF_OR | BPF_K: + case BPF_ALU64 | BPF_XOR | BPF_K: + case BPF_ALU64 | BPF_ADD | BPF_K: + case BPF_ALU64 | BPF_SUB | BPF_K: + if (imm) + emit_alu_i64(ctx, dst, imm, BPF_OP(code)); + break; + /* dst = dst << imm (64-bit) */ + /* dst = dst >> imm (64-bit) */ + /* dst = dst >> imm (64-bit, arithmetic) */ + case BPF_ALU64 | BPF_LSH | BPF_K: + case BPF_ALU64 | BPF_RSH | BPF_K: + case BPF_ALU64 | BPF_ARSH | BPF_K: + if (imm) + emit_shift_i64(ctx, dst, imm, BPF_OP(code)); + break; + /* dst = dst * imm (64-bit) */ + case BPF_ALU64 | BPF_MUL | BPF_K: + emit_mul_i64(ctx, dst, imm); + break; + /* dst = dst / imm (64-bit) */ + /* dst = dst % imm (64-bit) */ + case BPF_ALU64 | BPF_DIV | BPF_K: + case BPF_ALU64 | BPF_MOD | BPF_K: + /* + * Sign-extend the immediate value into a temporary register, + * and then do the operation on this register. + */ + emit_mov_se_i64(ctx, tmp, imm); + emit_divmod_r64(ctx, dst, tmp, BPF_OP(code)); + break; + /* dst = dst & src (64-bit) */ + /* dst = dst | src (64-bit) */ + /* dst = dst ^ src (64-bit) */ + /* dst = dst + src (64-bit) */ + /* dst = dst - src (64-bit) */ + case BPF_ALU64 | BPF_AND | BPF_X: + case BPF_ALU64 | BPF_OR | BPF_X: + case BPF_ALU64 | BPF_XOR | BPF_X: + case BPF_ALU64 | BPF_ADD | BPF_X: + case BPF_ALU64 | BPF_SUB | BPF_X: + emit_alu_r64(ctx, dst, src, BPF_OP(code)); + break; + /* dst = dst << src (64-bit) */ + /* dst = dst >> src (64-bit) */ + /* dst = dst >> src (64-bit, arithmetic) */ + case BPF_ALU64 | BPF_LSH | BPF_X: + case BPF_ALU64 | BPF_RSH | BPF_X: + case BPF_ALU64 | BPF_ARSH | BPF_X: + emit_shift_r64(ctx, dst, lo(src), BPF_OP(code)); + break; + /* dst = dst * src (64-bit) */ + case BPF_ALU64 | BPF_MUL | BPF_X: + emit_mul_r64(ctx, dst, src); + break; + /* dst = dst / src (64-bit) */ + /* dst = dst % src (64-bit) */ + case BPF_ALU64 | BPF_DIV | BPF_X: + case BPF_ALU64 | BPF_MOD | BPF_X: + emit_divmod_r64(ctx, dst, src, BPF_OP(code)); + break; + /* dst = htole(dst) */ + /* dst = htobe(dst) */ + case BPF_ALU | BPF_END | BPF_FROM_LE: + case BPF_ALU | BPF_END | BPF_FROM_BE: + if (BPF_SRC(code) == +#ifdef __BIG_ENDIAN + BPF_FROM_LE +#else + BPF_FROM_BE +#endif + ) + emit_bswap_r64(ctx, dst, imm); + else + emit_trunc_r64(ctx, dst, imm); + break; + /* dst = imm64 */ + case BPF_LD | BPF_IMM | BPF_DW: + emit_mov_i(ctx, lo(dst), imm); + emit_mov_i(ctx, hi(dst), insn[1].imm); + return 1; + /* LDX: dst = *(size *)(src + off) */ + case BPF_LDX | BPF_MEM | BPF_W: + case BPF_LDX | BPF_MEM | BPF_H: + case BPF_LDX | BPF_MEM | BPF_B: + case BPF_LDX | BPF_MEM | BPF_DW: + emit_ldx(ctx, dst, lo(src), off, BPF_SIZE(code)); + break; + /* ST: *(size *)(dst + off) = imm */ + case BPF_ST | BPF_MEM | BPF_W: + case BPF_ST | BPF_MEM | BPF_H: + case BPF_ST | BPF_MEM | BPF_B: + case BPF_ST | BPF_MEM | BPF_DW: + switch (BPF_SIZE(code)) { + case BPF_DW: + /* Sign-extend immediate value into temporary reg */ + emit_mov_se_i64(ctx, tmp, imm); + break; + case BPF_W: + case BPF_H: + case BPF_B: + emit_mov_i(ctx, lo(tmp), imm); + break; + } + emit_stx(ctx, lo(dst), tmp, off, BPF_SIZE(code)); + break; + /* STX: *(size *)(dst + off) = src */ + case BPF_STX | BPF_MEM | BPF_W: + case BPF_STX | BPF_MEM | BPF_H: + case BPF_STX | BPF_MEM | BPF_B: + case BPF_STX | BPF_MEM | BPF_DW: + emit_stx(ctx, lo(dst), src, off, BPF_SIZE(code)); + break; + /* Speculation barrier */ + case BPF_ST | BPF_NOSPEC: + break; + /* Atomics */ + case BPF_STX | BPF_ATOMIC | BPF_W: + switch (imm) { + case BPF_ADD: + case BPF_ADD | BPF_FETCH: + case BPF_AND: + case BPF_AND | BPF_FETCH: + case BPF_OR: + case BPF_OR | BPF_FETCH: + case BPF_XOR: + case BPF_XOR | BPF_FETCH: + case BPF_XCHG: + if (cpu_has_llsc) + emit_atomic_r(ctx, lo(dst), lo(src), off, imm); + else /* Non-ll/sc fallback */ + emit_atomic_r32(ctx, lo(dst), lo(src), + off, imm); + if (imm & BPF_FETCH) + emit_zext_ver(ctx, src); + break; + case BPF_CMPXCHG: + if (cpu_has_llsc) + emit_cmpxchg_r(ctx, lo(dst), lo(src), + lo(res), off); + else /* Non-ll/sc fallback */ + emit_cmpxchg_r32(ctx, lo(dst), lo(src), off); + /* Result zero-extension inserted by verifier */ + break; + default: + goto notyet; + } + break; + /* Atomics (64-bit) */ + case BPF_STX | BPF_ATOMIC | BPF_DW: + switch (imm) { + case BPF_ADD: + case BPF_ADD | BPF_FETCH: + case BPF_AND: + case BPF_AND | BPF_FETCH: + case BPF_OR: + case BPF_OR | BPF_FETCH: + case BPF_XOR: + case BPF_XOR | BPF_FETCH: + case BPF_XCHG: + emit_atomic_r64(ctx, lo(dst), src, off, imm); + break; + case BPF_CMPXCHG: + emit_cmpxchg_r64(ctx, lo(dst), src, off); + break; + default: + goto notyet; + } + break; + /* PC += off if dst == src */ + /* PC += off if dst != src */ + /* PC += off if dst & src */ + /* PC += off if dst > src */ + /* PC += off if dst >= src */ + /* PC += off if dst < src */ + /* PC += off if dst <= src */ + /* PC += off if dst > src (signed) */ + /* PC += off if dst >= src (signed) */ + /* PC += off if dst < src (signed) */ + /* PC += off if dst <= src (signed) */ + case BPF_JMP32 | BPF_JEQ | BPF_X: + case BPF_JMP32 | BPF_JNE | BPF_X: + case BPF_JMP32 | BPF_JSET | BPF_X: + case BPF_JMP32 | BPF_JGT | BPF_X: + case BPF_JMP32 | BPF_JGE | BPF_X: + case BPF_JMP32 | BPF_JLT | BPF_X: + case BPF_JMP32 | BPF_JLE | BPF_X: + case BPF_JMP32 | BPF_JSGT | BPF_X: + case BPF_JMP32 | BPF_JSGE | BPF_X: + case BPF_JMP32 | BPF_JSLT | BPF_X: + case BPF_JMP32 | BPF_JSLE | BPF_X: + if (off == 0) + break; + setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); + emit_jmp_r(ctx, lo(dst), lo(src), rel, jmp); + if (finish_jmp(ctx, jmp, off) < 0) + goto toofar; + break; + /* PC += off if dst == imm */ + /* PC += off if dst != imm */ + /* PC += off if dst & imm */ + /* PC += off if dst > imm */ + /* PC += off if dst >= imm */ + /* PC += off if dst < imm */ + /* PC += off if dst <= imm */ + /* PC += off if dst > imm (signed) */ + /* PC += off if dst >= imm (signed) */ + /* PC += off if dst < imm (signed) */ + /* PC += off if dst <= imm (signed) */ + case BPF_JMP32 | BPF_JEQ | BPF_K: + case BPF_JMP32 | BPF_JNE | BPF_K: + case BPF_JMP32 | BPF_JSET | BPF_K: + case BPF_JMP32 | BPF_JGT | BPF_K: + case BPF_JMP32 | BPF_JGE | BPF_K: + case BPF_JMP32 | BPF_JLT | BPF_K: + case BPF_JMP32 | BPF_JLE | BPF_K: + case BPF_JMP32 | BPF_JSGT | BPF_K: + case BPF_JMP32 | BPF_JSGE | BPF_K: + case BPF_JMP32 | BPF_JSLT | BPF_K: + case BPF_JMP32 | BPF_JSLE | BPF_K: + if (off == 0) + break; + setup_jmp_i(ctx, imm, 32, BPF_OP(code), off, &jmp, &rel); + if (valid_jmp_i(jmp, imm)) { + emit_jmp_i(ctx, lo(dst), imm, rel, jmp); + } else { + /* Move large immediate to register */ + emit_mov_i(ctx, MIPS_R_T6, imm); + emit_jmp_r(ctx, lo(dst), MIPS_R_T6, rel, jmp); + } + if (finish_jmp(ctx, jmp, off) < 0) + goto toofar; + break; + /* PC += off if dst == src */ + /* PC += off if dst != src */ + /* PC += off if dst & src */ + /* PC += off if dst > src */ + /* PC += off if dst >= src */ + /* PC += off if dst < src */ + /* PC += off if dst <= src */ + /* PC += off if dst > src (signed) */ + /* PC += off if dst >= src (signed) */ + /* PC += off if dst < src (signed) */ + /* PC += off if dst <= src (signed) */ + case BPF_JMP | BPF_JEQ | BPF_X: + case BPF_JMP | BPF_JNE | BPF_X: + case BPF_JMP | BPF_JSET | BPF_X: + case BPF_JMP | BPF_JGT | BPF_X: + case BPF_JMP | BPF_JGE | BPF_X: + case BPF_JMP | BPF_JLT | BPF_X: + case BPF_JMP | BPF_JLE | BPF_X: + case BPF_JMP | BPF_JSGT | BPF_X: + case BPF_JMP | BPF_JSGE | BPF_X: + case BPF_JMP | BPF_JSLT | BPF_X: + case BPF_JMP | BPF_JSLE | BPF_X: + if (off == 0) + break; + setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); + emit_jmp_r64(ctx, dst, src, rel, jmp); + if (finish_jmp(ctx, jmp, off) < 0) + goto toofar; + break; + /* PC += off if dst == imm */ + /* PC += off if dst != imm */ + /* PC += off if dst & imm */ + /* PC += off if dst > imm */ + /* PC += off if dst >= imm */ + /* PC += off if dst < imm */ + /* PC += off if dst <= imm */ + /* PC += off if dst > imm (signed) */ + /* PC += off if dst >= imm (signed) */ + /* PC += off if dst < imm (signed) */ + /* PC += off if dst <= imm (signed) */ + case BPF_JMP | BPF_JEQ | BPF_K: + case BPF_JMP | BPF_JNE | BPF_K: + case BPF_JMP | BPF_JSET | BPF_K: + case BPF_JMP | BPF_JGT | BPF_K: + case BPF_JMP | BPF_JGE | BPF_K: + case BPF_JMP | BPF_JLT | BPF_K: + case BPF_JMP | BPF_JLE | BPF_K: + case BPF_JMP | BPF_JSGT | BPF_K: + case BPF_JMP | BPF_JSGE | BPF_K: + case BPF_JMP | BPF_JSLT | BPF_K: + case BPF_JMP | BPF_JSLE | BPF_K: + if (off == 0) + break; + setup_jmp_i(ctx, imm, 64, BPF_OP(code), off, &jmp, &rel); + emit_jmp_i64(ctx, dst, imm, rel, jmp); + if (finish_jmp(ctx, jmp, off) < 0) + goto toofar; + break; + /* PC += off */ + case BPF_JMP | BPF_JA: + if (off == 0) + break; + if (emit_ja(ctx, off) < 0) + goto toofar; + break; + /* Tail call */ + case BPF_JMP | BPF_TAIL_CALL: + if (emit_tail_call(ctx) < 0) + goto invalid; + break; + /* Function call */ + case BPF_JMP | BPF_CALL: + if (emit_call(ctx, insn) < 0) + goto invalid; + break; + /* Function return */ + case BPF_JMP | BPF_EXIT: + /* + * Optimization: when last instruction is EXIT + * simply continue to epilogue. + */ + if (ctx->bpf_index == ctx->program->len - 1) + break; + if (emit_exit(ctx) < 0) + goto toofar; + break; + + default: +invalid: + pr_err_once("unknown opcode %02x\n", code); + return -EINVAL; +notyet: + pr_info_once("*** NOT YET: opcode %02x ***\n", code); + return -EFAULT; +toofar: + pr_info_once("*** TOO FAR: jump at %u opcode %02x ***\n", + ctx->bpf_index, code); + return -E2BIG; + } + return 0; +} diff --git a/arch/mips/net/bpf_jit_comp64.c b/arch/mips/net/bpf_jit_comp64.c new file mode 100644 index 000000000000..815ade724227 --- /dev/null +++ b/arch/mips/net/bpf_jit_comp64.c @@ -0,0 +1,1060 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Just-In-Time compiler for eBPF bytecode on MIPS. + * Implementation of JIT functions for 64-bit CPUs. + * + * Copyright (c) 2021 Anyfi Networks AB. + * Author: Johan Almbladh <johan.almbladh@gmail.com> + * + * Based on code and ideas from + * Copyright (c) 2017 Cavium, Inc. + * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com> + * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> + */ + +#include <linux/errno.h> +#include <linux/filter.h> +#include <linux/bpf.h> +#include <asm/cpu-features.h> +#include <asm/isa-rev.h> +#include <asm/uasm.h> + +#include "bpf_jit_comp.h" + +/* MIPS t0-t3 are not available in the n64 ABI */ +#undef MIPS_R_T0 +#undef MIPS_R_T1 +#undef MIPS_R_T2 +#undef MIPS_R_T3 + +/* Stack is 16-byte aligned in n64 ABI */ +#define MIPS_STACK_ALIGNMENT 16 + +/* Extra 64-bit eBPF registers used by JIT */ +#define JIT_REG_TC (MAX_BPF_JIT_REG + 0) +#define JIT_REG_ZX (MAX_BPF_JIT_REG + 1) + +/* Number of prologue bytes to skip when doing a tail call */ +#define JIT_TCALL_SKIP 4 + +/* Callee-saved CPU registers that the JIT must preserve */ +#define JIT_CALLEE_REGS \ + (BIT(MIPS_R_S0) | \ + BIT(MIPS_R_S1) | \ + BIT(MIPS_R_S2) | \ + BIT(MIPS_R_S3) | \ + BIT(MIPS_R_S4) | \ + BIT(MIPS_R_S5) | \ + BIT(MIPS_R_S6) | \ + BIT(MIPS_R_S7) | \ + BIT(MIPS_R_GP) | \ + BIT(MIPS_R_FP) | \ + BIT(MIPS_R_RA)) + +/* Caller-saved CPU registers available for JIT use */ +#define JIT_CALLER_REGS \ + (BIT(MIPS_R_A5) | \ + BIT(MIPS_R_A6) | \ + BIT(MIPS_R_A7)) +/* + * Mapping of 64-bit eBPF registers to 64-bit native MIPS registers. + * MIPS registers t4 - t7 may be used by the JIT as temporary registers. + * MIPS registers t8 - t9 are reserved for single-register common functions. + */ +static const u8 bpf2mips64[] = { + /* Return value from in-kernel function, and exit value from eBPF */ + [BPF_REG_0] = MIPS_R_V0, + /* Arguments from eBPF program to in-kernel function */ + [BPF_REG_1] = MIPS_R_A0, + [BPF_REG_2] = MIPS_R_A1, + [BPF_REG_3] = MIPS_R_A2, + [BPF_REG_4] = MIPS_R_A3, + [BPF_REG_5] = MIPS_R_A4, + /* Callee-saved registers that in-kernel function will preserve */ + [BPF_REG_6] = MIPS_R_S0, + [BPF_REG_7] = MIPS_R_S1, + [BPF_REG_8] = MIPS_R_S2, + [BPF_REG_9] = MIPS_R_S3, + /* Read-only frame pointer to access the eBPF stack */ + [BPF_REG_FP] = MIPS_R_FP, + /* Temporary register for blinding constants */ + [BPF_REG_AX] = MIPS_R_AT, + /* Tail call count register, caller-saved */ + [JIT_REG_TC] = MIPS_R_A5, + /* Constant for register zero-extension */ + [JIT_REG_ZX] = MIPS_R_V1, +}; + +/* + * MIPS 32-bit operations on 64-bit registers generate a sign-extended + * result. However, the eBPF ISA mandates zero-extension, so we rely on the + * verifier to add that for us (emit_zext_ver). In addition, ALU arithmetic + * operations, right shift and byte swap require properly sign-extended + * operands or the result is unpredictable. We emit explicit sign-extensions + * in those cases. + */ + +/* Sign extension */ +static void emit_sext(struct jit_context *ctx, u8 dst, u8 src) +{ + emit(ctx, sll, dst, src, 0); + clobber_reg(ctx, dst); +} + +/* Zero extension */ +static void emit_zext(struct jit_context *ctx, u8 dst) +{ + if (cpu_has_mips64r2 || cpu_has_mips64r6) { + emit(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); + } else { + emit(ctx, and, dst, dst, bpf2mips64[JIT_REG_ZX]); + access_reg(ctx, JIT_REG_ZX); /* We need the ZX register */ + } + clobber_reg(ctx, dst); +} + +/* Zero extension, if verifier does not do it for us */ +static void emit_zext_ver(struct jit_context *ctx, u8 dst) +{ + if (!ctx->program->aux->verifier_zext) + emit_zext(ctx, dst); +} + +/* dst = imm (64-bit) */ +static void emit_mov_i64(struct jit_context *ctx, u8 dst, u64 imm64) +{ + if (imm64 >= 0xffffffffffff8000ULL || imm64 < 0x8000ULL) { + emit(ctx, daddiu, dst, MIPS_R_ZERO, (s16)imm64); + } else if (imm64 >= 0xffffffff80000000ULL || + (imm64 < 0x80000000 && imm64 > 0xffff)) { + emit(ctx, lui, dst, (s16)(imm64 >> 16)); + emit(ctx, ori, dst, dst, (u16)imm64 & 0xffff); + } else { + u8 acc = MIPS_R_ZERO; + int shift = 0; + int k; + + for (k = 0; k < 4; k++) { + u16 half = imm64 >> (48 - 16 * k); + + if (acc == dst) + shift += 16; + + if (half) { + if (shift) + emit(ctx, dsll_safe, dst, dst, shift); + emit(ctx, ori, dst, acc, half); + acc = dst; + shift = 0; + } + } + if (shift) + emit(ctx, dsll_safe, dst, dst, shift); + } + clobber_reg(ctx, dst); +} + +/* ALU immediate operation (64-bit) */ +static void emit_alu_i64(struct jit_context *ctx, u8 dst, s32 imm, u8 op) +{ + switch (BPF_OP(op)) { + /* dst = dst | imm */ + case BPF_OR: + emit(ctx, ori, dst, dst, (u16)imm); + break; + /* dst = dst ^ imm */ + case BPF_XOR: + emit(ctx, xori, dst, dst, (u16)imm); + break; + /* dst = -dst */ + case BPF_NEG: + emit(ctx, dsubu, dst, MIPS_R_ZERO, dst); + break; + /* dst = dst << imm */ + case BPF_LSH: + emit(ctx, dsll_safe, dst, dst, imm); + break; + /* dst = dst >> imm */ + case BPF_RSH: + emit(ctx, dsrl_safe, dst, dst, imm); + break; + /* dst = dst >> imm (arithmetic) */ + case BPF_ARSH: + emit(ctx, dsra_safe, dst, dst, imm); + break; + /* dst = dst + imm */ + case BPF_ADD: + emit(ctx, daddiu, dst, dst, imm); + break; + /* dst = dst - imm */ + case BPF_SUB: + emit(ctx, daddiu, dst, dst, -imm); + break; + default: + /* Width-generic operations */ + emit_alu_i(ctx, dst, imm, op); + } + clobber_reg(ctx, dst); +} + +/* ALU register operation (64-bit) */ +static void emit_alu_r64(struct jit_context *ctx, u8 dst, u8 src, u8 op) +{ + switch (BPF_OP(op)) { + /* dst = dst << src */ + case BPF_LSH: + emit(ctx, dsllv, dst, dst, src); + break; + /* dst = dst >> src */ + case BPF_RSH: + emit(ctx, dsrlv, dst, dst, src); + break; + /* dst = dst >> src (arithmetic) */ + case BPF_ARSH: + emit(ctx, dsrav, dst, dst, src); + break; + /* dst = dst + src */ + case BPF_ADD: + emit(ctx, daddu, dst, dst, src); + break; + /* dst = dst - src */ + case BPF_SUB: + emit(ctx, dsubu, dst, dst, src); + break; + /* dst = dst * src */ + case BPF_MUL: + if (cpu_has_mips64r6) { + emit(ctx, dmulu, dst, dst, src); + } else { + emit(ctx, dmultu, dst, src); + emit(ctx, mflo, dst); + } + break; + /* dst = dst / src */ + case BPF_DIV: + if (cpu_has_mips64r6) { + emit(ctx, ddivu_r6, dst, dst, src); + } else { + emit(ctx, ddivu, dst, src); + emit(ctx, mflo, dst); + } + break; + /* dst = dst % src */ + case BPF_MOD: + if (cpu_has_mips64r6) { + emit(ctx, dmodu, dst, dst, src); + } else { + emit(ctx, ddivu, dst, src); + emit(ctx, mfhi, dst); + } + break; + default: + /* Width-generic operations */ + emit_alu_r(ctx, dst, src, op); + } + clobber_reg(ctx, dst); +} + +/* Swap sub words in a register double word */ +static void emit_swap_r64(struct jit_context *ctx, u8 dst, u8 mask, u32 bits) +{ + u8 tmp = MIPS_R_T9; + + emit(ctx, and, tmp, dst, mask); /* tmp = dst & mask */ + emit(ctx, dsll, tmp, tmp, bits); /* tmp = tmp << bits */ + emit(ctx, dsrl, dst, dst, bits); /* dst = dst >> bits */ + emit(ctx, and, dst, dst, mask); /* dst = dst & mask */ + emit(ctx, or, dst, dst, tmp); /* dst = dst | tmp */ +} + +/* Swap bytes and truncate a register double word, word or half word */ +static void emit_bswap_r64(struct jit_context *ctx, u8 dst, u32 width) +{ + switch (width) { + /* Swap bytes in a double word */ + case 64: + if (cpu_has_mips64r2 || cpu_has_mips64r6) { + emit(ctx, dsbh, dst, dst); + emit(ctx, dshd, dst, dst); + } else { + u8 t1 = MIPS_R_T6; + u8 t2 = MIPS_R_T7; + + emit(ctx, dsll32, t2, dst, 0); /* t2 = dst << 32 */ + emit(ctx, dsrl32, dst, dst, 0); /* dst = dst >> 32 */ + emit(ctx, or, dst, dst, t2); /* dst = dst | t2 */ + + emit(ctx, ori, t2, MIPS_R_ZERO, 0xffff); + emit(ctx, dsll32, t1, t2, 0); /* t1 = t2 << 32 */ + emit(ctx, or, t1, t1, t2); /* t1 = t1 | t2 */ + emit_swap_r64(ctx, dst, t1, 16);/* dst = swap16(dst) */ + + emit(ctx, lui, t2, 0xff); /* t2 = 0x00ff0000 */ + emit(ctx, ori, t2, t2, 0xff); /* t2 = t2 | 0x00ff */ + emit(ctx, dsll32, t1, t2, 0); /* t1 = t2 << 32 */ + emit(ctx, or, t1, t1, t2); /* t1 = t1 | t2 */ + emit_swap_r64(ctx, dst, t1, 8); /* dst = swap8(dst) */ + } + break; + /* Swap bytes in a half word */ + /* Swap bytes in a word */ + case 32: + case 16: + emit_sext(ctx, dst, dst); + emit_bswap_r(ctx, dst, width); + if (cpu_has_mips64r2 || cpu_has_mips64r6) + emit_zext(ctx, dst); + break; + } + clobber_reg(ctx, dst); +} + +/* Truncate a register double word, word or half word */ +static void emit_trunc_r64(struct jit_context *ctx, u8 dst, u32 width) +{ + switch (width) { + case 64: + break; + /* Zero-extend a word */ + case 32: + emit_zext(ctx, dst); + break; + /* Zero-extend a half word */ + case 16: + emit(ctx, andi, dst, dst, 0xffff); + break; + } + clobber_reg(ctx, dst); +} + +/* Load operation: dst = *(size*)(src + off) */ +static void emit_ldx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size) +{ + switch (size) { + /* Load a byte */ + case BPF_B: + emit(ctx, lbu, dst, off, src); + break; + /* Load a half word */ + case BPF_H: + emit(ctx, lhu, dst, off, src); + break; + /* Load a word */ + case BPF_W: + emit(ctx, lwu, dst, off, src); + break; + /* Load a double word */ + case BPF_DW: + emit(ctx, ld, dst, off, src); + break; + } + clobber_reg(ctx, dst); +} + +/* Store operation: *(size *)(dst + off) = src */ +static void emit_stx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size) +{ + switch (size) { + /* Store a byte */ + case BPF_B: + emit(ctx, sb, src, off, dst); + break; + /* Store a half word */ + case BPF_H: + emit(ctx, sh, src, off, dst); + break; + /* Store a word */ + case BPF_W: + emit(ctx, sw, src, off, dst); + break; + /* Store a double word */ + case BPF_DW: + emit(ctx, sd, src, off, dst); + break; + } +} + +/* Atomic read-modify-write */ +static void emit_atomic_r64(struct jit_context *ctx, + u8 dst, u8 src, s16 off, u8 code) +{ + u8 t1 = MIPS_R_T6; + u8 t2 = MIPS_R_T7; + + LLSC_sync(ctx); + emit(ctx, lld, t1, off, dst); + switch (code) { + case BPF_ADD: + case BPF_ADD | BPF_FETCH: + emit(ctx, daddu, t2, t1, src); + break; + case BPF_AND: + case BPF_AND | BPF_FETCH: + emit(ctx, and, t2, t1, src); + break; + case BPF_OR: + case BPF_OR | BPF_FETCH: + emit(ctx, or, t2, t1, src); + break; + case BPF_XOR: + case BPF_XOR | BPF_FETCH: + emit(ctx, xor, t2, t1, src); + break; + case BPF_XCHG: + emit(ctx, move, t2, src); + break; + } + emit(ctx, scd, t2, off, dst); + emit(ctx, LLSC_beqz, t2, -16 - LLSC_offset); + emit(ctx, nop); /* Delay slot */ + + if (code & BPF_FETCH) { + emit(ctx, move, src, t1); + clobber_reg(ctx, src); + } +} + +/* Atomic compare-and-exchange */ +static void emit_cmpxchg_r64(struct jit_context *ctx, u8 dst, u8 src, s16 off) +{ + u8 r0 = bpf2mips64[BPF_REG_0]; + u8 t1 = MIPS_R_T6; + u8 t2 = MIPS_R_T7; + + LLSC_sync(ctx); + emit(ctx, lld, t1, off, dst); + emit(ctx, bne, t1, r0, 12); + emit(ctx, move, t2, src); /* Delay slot */ + emit(ctx, scd, t2, off, dst); + emit(ctx, LLSC_beqz, t2, -20 - LLSC_offset); + emit(ctx, move, r0, t1); /* Delay slot */ + + clobber_reg(ctx, r0); +} + +/* Function call */ +static int emit_call(struct jit_context *ctx, const struct bpf_insn *insn) +{ + u8 zx = bpf2mips64[JIT_REG_ZX]; + u8 tmp = MIPS_R_T6; + bool fixed; + u64 addr; + + /* Decode the call address */ + if (bpf_jit_get_func_addr(ctx->program, insn, false, + &addr, &fixed) < 0) + return -1; + if (!fixed) + return -1; + + /* Push caller-saved registers on stack */ + push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0); + + /* Emit function call */ + emit_mov_i64(ctx, tmp, addr & JALR_MASK); + emit(ctx, jalr, MIPS_R_RA, tmp); + emit(ctx, nop); /* Delay slot */ + + /* Restore caller-saved registers */ + pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0); + + /* Re-initialize the JIT zero-extension register if accessed */ + if (ctx->accessed & BIT(JIT_REG_ZX)) { + emit(ctx, daddiu, zx, MIPS_R_ZERO, -1); + emit(ctx, dsrl32, zx, zx, 0); + } + + clobber_reg(ctx, MIPS_R_RA); + clobber_reg(ctx, MIPS_R_V0); + clobber_reg(ctx, MIPS_R_V1); + return 0; +} + +/* Function tail call */ +static int emit_tail_call(struct jit_context *ctx) +{ + u8 ary = bpf2mips64[BPF_REG_2]; + u8 ind = bpf2mips64[BPF_REG_3]; + u8 tcc = bpf2mips64[JIT_REG_TC]; + u8 tmp = MIPS_R_T6; + int off; + + /* + * Tail call: + * eBPF R1 - function argument (context ptr), passed in a0-a1 + * eBPF R2 - ptr to object with array of function entry points + * eBPF R3 - array index of function to be called + */ + + /* if (ind >= ary->map.max_entries) goto out */ + off = offsetof(struct bpf_array, map.max_entries); + if (off > 0x7fff) + return -1; + emit(ctx, lwu, tmp, off, ary); /* tmp = ary->map.max_entrs*/ + emit(ctx, sltu, tmp, ind, tmp); /* tmp = ind < t1 */ + emit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/ + + /* if (--TCC < 0) goto out */ + emit(ctx, daddiu, tcc, tcc, -1); /* tcc-- (delay slot) */ + emit(ctx, bltz, tcc, get_offset(ctx, 1)); /* PC += off(1) if tcc < 0 */ + /* (next insn delay slot) */ + /* prog = ary->ptrs[ind] */ + off = offsetof(struct bpf_array, ptrs); + if (off > 0x7fff) + return -1; + emit(ctx, dsll, tmp, ind, 3); /* tmp = ind << 3 */ + emit(ctx, daddu, tmp, tmp, ary); /* tmp += ary */ + emit(ctx, ld, tmp, off, tmp); /* tmp = *(tmp + off) */ + + /* if (prog == 0) goto out */ + emit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/ + emit(ctx, nop); /* Delay slot */ + + /* func = prog->bpf_func + 8 (prologue skip offset) */ + off = offsetof(struct bpf_prog, bpf_func); + if (off > 0x7fff) + return -1; + emit(ctx, ld, tmp, off, tmp); /* tmp = *(tmp + off) */ + emit(ctx, daddiu, tmp, tmp, JIT_TCALL_SKIP); /* tmp += skip (4) */ + + /* goto func */ + build_epilogue(ctx, tmp); + access_reg(ctx, JIT_REG_TC); + return 0; +} + +/* + * Stack frame layout for a JITed program (stack grows down). + * + * Higher address : Previous stack frame : + * +===========================+ <--- MIPS sp before call + * | Callee-saved registers, | + * | including RA and FP | + * +---------------------------+ <--- eBPF FP (MIPS fp) + * | Local eBPF variables | + * | allocated by program | + * +---------------------------+ + * | Reserved for caller-saved | + * | registers | + * Lower address +===========================+ <--- MIPS sp + */ + +/* Build program prologue to set up the stack and registers */ +void build_prologue(struct jit_context *ctx) +{ + u8 fp = bpf2mips64[BPF_REG_FP]; + u8 tc = bpf2mips64[JIT_REG_TC]; + u8 zx = bpf2mips64[JIT_REG_ZX]; + int stack, saved, locals, reserved; + + /* + * The first instruction initializes the tail call count register. + * On a tail call, the calling function jumps into the prologue + * after this instruction. + */ + emit(ctx, addiu, tc, MIPS_R_ZERO, min(MAX_TAIL_CALL_CNT + 1, 0xffff)); + + /* === Entry-point for tail calls === */ + + /* + * If the eBPF frame pointer and tail call count registers were + * accessed they must be preserved. Mark them as clobbered here + * to save and restore them on the stack as needed. + */ + if (ctx->accessed & BIT(BPF_REG_FP)) + clobber_reg(ctx, fp); + if (ctx->accessed & BIT(JIT_REG_TC)) + clobber_reg(ctx, tc); + if (ctx->accessed & BIT(JIT_REG_ZX)) + clobber_reg(ctx, zx); + + /* Compute the stack space needed for callee-saved registers */ + saved = hweight32(ctx->clobbered & JIT_CALLEE_REGS) * sizeof(u64); + saved = ALIGN(saved, MIPS_STACK_ALIGNMENT); + + /* Stack space used by eBPF program local data */ + locals = ALIGN(ctx->program->aux->stack_depth, MIPS_STACK_ALIGNMENT); + + /* + * If we are emitting function calls, reserve extra stack space for + * caller-saved registers needed by the JIT. The required space is + * computed automatically during resource usage discovery (pass 1). + */ + reserved = ctx->stack_used; + + /* Allocate the stack frame */ + stack = ALIGN(saved + locals + reserved, MIPS_STACK_ALIGNMENT); + if (stack) + emit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, -stack); + + /* Store callee-saved registers on stack */ + push_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, stack - saved); + + /* Initialize the eBPF frame pointer if accessed */ + if (ctx->accessed & BIT(BPF_REG_FP)) + emit(ctx, daddiu, fp, MIPS_R_SP, stack - saved); + + /* Initialize the ePF JIT zero-extension register if accessed */ + if (ctx->accessed & BIT(JIT_REG_ZX)) { + emit(ctx, daddiu, zx, MIPS_R_ZERO, -1); + emit(ctx, dsrl32, zx, zx, 0); + } + + ctx->saved_size = saved; + ctx->stack_size = stack; +} + +/* Build the program epilogue to restore the stack and registers */ +void build_epilogue(struct jit_context *ctx, int dest_reg) +{ + /* Restore callee-saved registers from stack */ + pop_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, + ctx->stack_size - ctx->saved_size); + + /* Release the stack frame */ + if (ctx->stack_size) + emit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, ctx->stack_size); + + /* Jump to return address and sign-extend the 32-bit return value */ + emit(ctx, jr, dest_reg); + emit(ctx, sll, MIPS_R_V0, MIPS_R_V0, 0); /* Delay slot */ +} + +/* Build one eBPF instruction */ +int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) +{ + u8 dst = bpf2mips64[insn->dst_reg]; + u8 src = bpf2mips64[insn->src_reg]; + u8 res = bpf2mips64[BPF_REG_0]; + u8 code = insn->code; + s16 off = insn->off; + s32 imm = insn->imm; + s32 val, rel; + u8 alu, jmp; + + switch (code) { + /* ALU operations */ + /* dst = imm */ + case BPF_ALU | BPF_MOV | BPF_K: + emit_mov_i(ctx, dst, imm); + emit_zext_ver(ctx, dst); + break; + /* dst = src */ + case BPF_ALU | BPF_MOV | BPF_X: + if (imm == 1) { + /* Special mov32 for zext */ + emit_zext(ctx, dst); + } else { + emit_mov_r(ctx, dst, src); + emit_zext_ver(ctx, dst); + } + break; + /* dst = -dst */ + case BPF_ALU | BPF_NEG: + emit_sext(ctx, dst, dst); + emit_alu_i(ctx, dst, 0, BPF_NEG); + emit_zext_ver(ctx, dst); + break; + /* dst = dst & imm */ + /* dst = dst | imm */ + /* dst = dst ^ imm */ + /* dst = dst << imm */ + case BPF_ALU | BPF_OR | BPF_K: + case BPF_ALU | BPF_AND | BPF_K: + case BPF_ALU | BPF_XOR | BPF_K: + case BPF_ALU | BPF_LSH | BPF_K: + if (!valid_alu_i(BPF_OP(code), imm)) { + emit_mov_i(ctx, MIPS_R_T4, imm); + emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); + } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { + emit_alu_i(ctx, dst, val, alu); + } + emit_zext_ver(ctx, dst); + break; + /* dst = dst >> imm */ + /* dst = dst >> imm (arithmetic) */ + /* dst = dst + imm */ + /* dst = dst - imm */ + /* dst = dst * imm */ + /* dst = dst / imm */ + /* dst = dst % imm */ + case BPF_ALU | BPF_RSH | BPF_K: + case BPF_ALU | BPF_ARSH | BPF_K: + case BPF_ALU | BPF_ADD | BPF_K: + case BPF_ALU | BPF_SUB | BPF_K: + case BPF_ALU | BPF_MUL | BPF_K: + case BPF_ALU | BPF_DIV | BPF_K: + case BPF_ALU | BPF_MOD | BPF_K: + if (!valid_alu_i(BPF_OP(code), imm)) { + emit_sext(ctx, dst, dst); + emit_mov_i(ctx, MIPS_R_T4, imm); + emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); + } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { + emit_sext(ctx, dst, dst); + emit_alu_i(ctx, dst, val, alu); + } + emit_zext_ver(ctx, dst); + break; + /* dst = dst & src */ + /* dst = dst | src */ + /* dst = dst ^ src */ + /* dst = dst << src */ + case BPF_ALU | BPF_AND | BPF_X: + case BPF_ALU | BPF_OR | BPF_X: + case BPF_ALU | BPF_XOR | BPF_X: + case BPF_ALU | BPF_LSH | BPF_X: + emit_alu_r(ctx, dst, src, BPF_OP(code)); + emit_zext_ver(ctx, dst); + break; + /* dst = dst >> src */ + /* dst = dst >> src (arithmetic) */ + /* dst = dst + src */ + /* dst = dst - src */ + /* dst = dst * src */ + /* dst = dst / src */ + /* dst = dst % src */ + case BPF_ALU | BPF_RSH | BPF_X: + case BPF_ALU | BPF_ARSH | BPF_X: + case BPF_ALU | BPF_ADD | BPF_X: + case BPF_ALU | BPF_SUB | BPF_X: + case BPF_ALU | BPF_MUL | BPF_X: + case BPF_ALU | BPF_DIV | BPF_X: + case BPF_ALU | BPF_MOD | BPF_X: + emit_sext(ctx, dst, dst); + emit_sext(ctx, MIPS_R_T4, src); + emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); + emit_zext_ver(ctx, dst); + break; + /* dst = imm (64-bit) */ + case BPF_ALU64 | BPF_MOV | BPF_K: + emit_mov_i(ctx, dst, imm); + break; + /* dst = src (64-bit) */ + case BPF_ALU64 | BPF_MOV | BPF_X: + emit_mov_r(ctx, dst, src); + break; + /* dst = -dst (64-bit) */ + case BPF_ALU64 | BPF_NEG: + emit_alu_i64(ctx, dst, 0, BPF_NEG); + break; + /* dst = dst & imm (64-bit) */ + /* dst = dst | imm (64-bit) */ + /* dst = dst ^ imm (64-bit) */ + /* dst = dst << imm (64-bit) */ + /* dst = dst >> imm (64-bit) */ + /* dst = dst >> imm ((64-bit, arithmetic) */ + /* dst = dst + imm (64-bit) */ + /* dst = dst - imm (64-bit) */ + /* dst = dst * imm (64-bit) */ + /* dst = dst / imm (64-bit) */ + /* dst = dst % imm (64-bit) */ + case BPF_ALU64 | BPF_AND | BPF_K: + case BPF_ALU64 | BPF_OR | BPF_K: + case BPF_ALU64 | BPF_XOR | BPF_K: + case BPF_ALU64 | BPF_LSH | BPF_K: + case BPF_ALU64 | BPF_RSH | BPF_K: + case BPF_ALU64 | BPF_ARSH | BPF_K: + case BPF_ALU64 | BPF_ADD | BPF_K: + case BPF_ALU64 | BPF_SUB | BPF_K: + case BPF_ALU64 | BPF_MUL | BPF_K: + case BPF_ALU64 | BPF_DIV | BPF_K: + case BPF_ALU64 | BPF_MOD | BPF_K: + if (!valid_alu_i(BPF_OP(code), imm)) { + emit_mov_i(ctx, MIPS_R_T4, imm); + emit_alu_r64(ctx, dst, MIPS_R_T4, BPF_OP(code)); + } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { + emit_alu_i64(ctx, dst, val, alu); + } + break; + /* dst = dst & src (64-bit) */ + /* dst = dst | src (64-bit) */ + /* dst = dst ^ src (64-bit) */ + /* dst = dst << src (64-bit) */ + /* dst = dst >> src (64-bit) */ + /* dst = dst >> src (64-bit, arithmetic) */ + /* dst = dst + src (64-bit) */ + /* dst = dst - src (64-bit) */ + /* dst = dst * src (64-bit) */ + /* dst = dst / src (64-bit) */ + /* dst = dst % src (64-bit) */ + case BPF_ALU64 | BPF_AND | BPF_X: + case BPF_ALU64 | BPF_OR | BPF_X: + case BPF_ALU64 | BPF_XOR | BPF_X: + case BPF_ALU64 | BPF_LSH | BPF_X: + case BPF_ALU64 | BPF_RSH | BPF_X: + case BPF_ALU64 | BPF_ARSH | BPF_X: + case BPF_ALU64 | BPF_ADD | BPF_X: + case BPF_ALU64 | BPF_SUB | BPF_X: + case BPF_ALU64 | BPF_MUL | BPF_X: + case BPF_ALU64 | BPF_DIV | BPF_X: + case BPF_ALU64 | BPF_MOD | BPF_X: + emit_alu_r64(ctx, dst, src, BPF_OP(code)); + break; + /* dst = htole(dst) */ + /* dst = htobe(dst) */ + case BPF_ALU | BPF_END | BPF_FROM_LE: + case BPF_ALU | BPF_END | BPF_FROM_BE: + if (BPF_SRC(code) == +#ifdef __BIG_ENDIAN + BPF_FROM_LE +#else + BPF_FROM_BE +#endif + ) + emit_bswap_r64(ctx, dst, imm); + else + emit_trunc_r64(ctx, dst, imm); + break; + /* dst = imm64 */ + case BPF_LD | BPF_IMM | BPF_DW: + emit_mov_i64(ctx, dst, (u32)imm | ((u64)insn[1].imm << 32)); + return 1; + /* LDX: dst = *(size *)(src + off) */ + case BPF_LDX | BPF_MEM | BPF_W: + case BPF_LDX | BPF_MEM | BPF_H: + case BPF_LDX | BPF_MEM | BPF_B: + case BPF_LDX | BPF_MEM | BPF_DW: + emit_ldx(ctx, dst, src, off, BPF_SIZE(code)); + break; + /* ST: *(size *)(dst + off) = imm */ + case BPF_ST | BPF_MEM | BPF_W: + case BPF_ST | BPF_MEM | BPF_H: + case BPF_ST | BPF_MEM | BPF_B: + case BPF_ST | BPF_MEM | BPF_DW: + emit_mov_i(ctx, MIPS_R_T4, imm); + emit_stx(ctx, dst, MIPS_R_T4, off, BPF_SIZE(code)); + break; + /* STX: *(size *)(dst + off) = src */ + case BPF_STX | BPF_MEM | BPF_W: + case BPF_STX | BPF_MEM | BPF_H: + case BPF_STX | BPF_MEM | BPF_B: + case BPF_STX | BPF_MEM | BPF_DW: + emit_stx(ctx, dst, src, off, BPF_SIZE(code)); + break; + /* Speculation barrier */ + case BPF_ST | BPF_NOSPEC: + break; + /* Atomics */ + case BPF_STX | BPF_ATOMIC | BPF_W: + case BPF_STX | BPF_ATOMIC | BPF_DW: + switch (imm) { + case BPF_ADD: + case BPF_ADD | BPF_FETCH: + case BPF_AND: + case BPF_AND | BPF_FETCH: + case BPF_OR: + case BPF_OR | BPF_FETCH: + case BPF_XOR: + case BPF_XOR | BPF_FETCH: + case BPF_XCHG: + if (BPF_SIZE(code) == BPF_DW) { + emit_atomic_r64(ctx, dst, src, off, imm); + } else if (imm & BPF_FETCH) { + u8 tmp = dst; + + if (src == dst) { /* Don't overwrite dst */ + emit_mov_r(ctx, MIPS_R_T4, dst); + tmp = MIPS_R_T4; + } + emit_sext(ctx, src, src); + emit_atomic_r(ctx, tmp, src, off, imm); + emit_zext_ver(ctx, src); + } else { /* 32-bit, no fetch */ + emit_sext(ctx, MIPS_R_T4, src); + emit_atomic_r(ctx, dst, MIPS_R_T4, off, imm); + } + break; + case BPF_CMPXCHG: + if (BPF_SIZE(code) == BPF_DW) { + emit_cmpxchg_r64(ctx, dst, src, off); + } else { + u8 tmp = res; + + if (res == dst) /* Don't overwrite dst */ + tmp = MIPS_R_T4; + emit_sext(ctx, tmp, res); + emit_sext(ctx, MIPS_R_T5, src); + emit_cmpxchg_r(ctx, dst, MIPS_R_T5, tmp, off); + if (res == dst) /* Restore result */ + emit_mov_r(ctx, res, MIPS_R_T4); + /* Result zext inserted by verifier */ + } + break; + default: + goto notyet; + } + break; + /* PC += off if dst == src */ + /* PC += off if dst != src */ + /* PC += off if dst & src */ + /* PC += off if dst > src */ + /* PC += off if dst >= src */ + /* PC += off if dst < src */ + /* PC += off if dst <= src */ + /* PC += off if dst > src (signed) */ + /* PC += off if dst >= src (signed) */ + /* PC += off if dst < src (signed) */ + /* PC += off if dst <= src (signed) */ + case BPF_JMP32 | BPF_JEQ | BPF_X: + case BPF_JMP32 | BPF_JNE | BPF_X: + case BPF_JMP32 | BPF_JSET | BPF_X: + case BPF_JMP32 | BPF_JGT | BPF_X: + case BPF_JMP32 | BPF_JGE | BPF_X: + case BPF_JMP32 | BPF_JLT | BPF_X: + case BPF_JMP32 | BPF_JLE | BPF_X: + case BPF_JMP32 | BPF_JSGT | BPF_X: + case BPF_JMP32 | BPF_JSGE | BPF_X: + case BPF_JMP32 | BPF_JSLT | BPF_X: + case BPF_JMP32 | BPF_JSLE | BPF_X: + if (off == 0) + break; + setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); + emit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */ + emit_sext(ctx, MIPS_R_T5, src); /* Sign-extended src */ + emit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp); + if (finish_jmp(ctx, jmp, off) < 0) + goto toofar; + break; + /* PC += off if dst == imm */ + /* PC += off if dst != imm */ + /* PC += off if dst & imm */ + /* PC += off if dst > imm */ + /* PC += off if dst >= imm */ + /* PC += off if dst < imm */ + /* PC += off if dst <= imm */ + /* PC += off if dst > imm (signed) */ + /* PC += off if dst >= imm (signed) */ + /* PC += off if dst < imm (signed) */ + /* PC += off if dst <= imm (signed) */ + case BPF_JMP32 | BPF_JEQ | BPF_K: + case BPF_JMP32 | BPF_JNE | BPF_K: + case BPF_JMP32 | BPF_JSET | BPF_K: + case BPF_JMP32 | BPF_JGT | BPF_K: + case BPF_JMP32 | BPF_JGE | BPF_K: + case BPF_JMP32 | BPF_JLT | BPF_K: + case BPF_JMP32 | BPF_JLE | BPF_K: + case BPF_JMP32 | BPF_JSGT | BPF_K: + case BPF_JMP32 | BPF_JSGE | BPF_K: + case BPF_JMP32 | BPF_JSLT | BPF_K: + case BPF_JMP32 | BPF_JSLE | BPF_K: + if (off == 0) + break; + setup_jmp_i(ctx, imm, 32, BPF_OP(code), off, &jmp, &rel); + emit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */ + if (valid_jmp_i(jmp, imm)) { + emit_jmp_i(ctx, MIPS_R_T4, imm, rel, jmp); + } else { + /* Move large immediate to register, sign-extended */ + emit_mov_i(ctx, MIPS_R_T5, imm); + emit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp); + } + if (finish_jmp(ctx, jmp, off) < 0) + goto toofar; + break; + /* PC += off if dst == src */ + /* PC += off if dst != src */ + /* PC += off if dst & src */ + /* PC += off if dst > src */ + /* PC += off if dst >= src */ + /* PC += off if dst < src */ + /* PC += off if dst <= src */ + /* PC += off if dst > src (signed) */ + /* PC += off if dst >= src (signed) */ + /* PC += off if dst < src (signed) */ + /* PC += off if dst <= src (signed) */ + case BPF_JMP | BPF_JEQ | BPF_X: + case BPF_JMP | BPF_JNE | BPF_X: + case BPF_JMP | BPF_JSET | BPF_X: + case BPF_JMP | BPF_JGT | BPF_X: + case BPF_JMP | BPF_JGE | BPF_X: + case BPF_JMP | BPF_JLT | BPF_X: + case BPF_JMP | BPF_JLE | BPF_X: + case BPF_JMP | BPF_JSGT | BPF_X: + case BPF_JMP | BPF_JSGE | BPF_X: + case BPF_JMP | BPF_JSLT | BPF_X: + case BPF_JMP | BPF_JSLE | BPF_X: + if (off == 0) + break; + setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); + emit_jmp_r(ctx, dst, src, rel, jmp); + if (finish_jmp(ctx, jmp, off) < 0) + goto toofar; + break; + /* PC += off if dst == imm */ + /* PC += off if dst != imm */ + /* PC += off if dst & imm */ + /* PC += off if dst > imm */ + /* PC += off if dst >= imm */ + /* PC += off if dst < imm */ + /* PC += off if dst <= imm */ + /* PC += off if dst > imm (signed) */ + /* PC += off if dst >= imm (signed) */ + /* PC += off if dst < imm (signed) */ + /* PC += off if dst <= imm (signed) */ + case BPF_JMP | BPF_JEQ | BPF_K: + case BPF_JMP | BPF_JNE | BPF_K: + case BPF_JMP | BPF_JSET | BPF_K: + case BPF_JMP | BPF_JGT | BPF_K: + case BPF_JMP | BPF_JGE | BPF_K: + case BPF_JMP | BPF_JLT | BPF_K: + case BPF_JMP | BPF_JLE | BPF_K: + case BPF_JMP | BPF_JSGT | BPF_K: + case BPF_JMP | BPF_JSGE | BPF_K: + case BPF_JMP | BPF_JSLT | BPF_K: + case BPF_JMP | BPF_JSLE | BPF_K: + if (off == 0) + break; + setup_jmp_i(ctx, imm, 64, BPF_OP(code), off, &jmp, &rel); + if (valid_jmp_i(jmp, imm)) { + emit_jmp_i(ctx, dst, imm, rel, jmp); + } else { + /* Move large immediate to register */ + emit_mov_i(ctx, MIPS_R_T4, imm); + emit_jmp_r(ctx, dst, MIPS_R_T4, rel, jmp); + } + if (finish_jmp(ctx, jmp, off) < 0) + goto toofar; + break; + /* PC += off */ + case BPF_JMP | BPF_JA: + if (off == 0) + break; + if (emit_ja(ctx, off) < 0) + goto toofar; + break; + /* Tail call */ + case BPF_JMP | BPF_TAIL_CALL: + if (emit_tail_call(ctx) < 0) + goto invalid; + break; + /* Function call */ + case BPF_JMP | BPF_CALL: + if (emit_call(ctx, insn) < 0) + goto invalid; + break; + /* Function return */ + case BPF_JMP | BPF_EXIT: + /* + * Optimization: when last instruction is EXIT + * simply continue to epilogue. + */ + if (ctx->bpf_index == ctx->program->len - 1) + break; + if (emit_exit(ctx) < 0) + goto toofar; + break; + + default: +invalid: + pr_err_once("unknown opcode %02x\n", code); + return -EINVAL; +notyet: + pr_info_once("*** NOT YET: opcode %02x ***\n", code); + return -EFAULT; +toofar: + pr_info_once("*** TOO FAR: jump at %u opcode %02x ***\n", + ctx->bpf_index, code); + return -E2BIG; + } + return 0; +} diff --git a/arch/mips/net/ebpf_jit.c b/arch/mips/net/ebpf_jit.c deleted file mode 100644 index 3a73e9375712..000000000000 --- a/arch/mips/net/ebpf_jit.c +++ /dev/null @@ -1,1938 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Just-In-Time compiler for eBPF filters on MIPS - * - * Copyright (c) 2017 Cavium, Inc. - * - * Based on code from: - * - * Copyright (c) 2014 Imagination Technologies Ltd. - * Author: Markos Chandras <markos.chandras@imgtec.com> - */ - -#include <linux/bitops.h> -#include <linux/errno.h> -#include <linux/filter.h> -#include <linux/bpf.h> -#include <linux/slab.h> -#include <asm/bitops.h> -#include <asm/byteorder.h> -#include <asm/cacheflush.h> -#include <asm/cpu-features.h> -#include <asm/isa-rev.h> -#include <asm/uasm.h> - -/* Registers used by JIT */ -#define MIPS_R_ZERO 0 -#define MIPS_R_AT 1 -#define MIPS_R_V0 2 /* BPF_R0 */ -#define MIPS_R_V1 3 -#define MIPS_R_A0 4 /* BPF_R1 */ -#define MIPS_R_A1 5 /* BPF_R2 */ -#define MIPS_R_A2 6 /* BPF_R3 */ -#define MIPS_R_A3 7 /* BPF_R4 */ -#define MIPS_R_A4 8 /* BPF_R5 */ -#define MIPS_R_T4 12 /* BPF_AX */ -#define MIPS_R_T5 13 -#define MIPS_R_T6 14 -#define MIPS_R_T7 15 -#define MIPS_R_S0 16 /* BPF_R6 */ -#define MIPS_R_S1 17 /* BPF_R7 */ -#define MIPS_R_S2 18 /* BPF_R8 */ -#define MIPS_R_S3 19 /* BPF_R9 */ -#define MIPS_R_S4 20 /* BPF_TCC */ -#define MIPS_R_S5 21 -#define MIPS_R_S6 22 -#define MIPS_R_S7 23 -#define MIPS_R_T8 24 -#define MIPS_R_T9 25 -#define MIPS_R_SP 29 -#define MIPS_R_RA 31 - -/* eBPF flags */ -#define EBPF_SAVE_S0 BIT(0) -#define EBPF_SAVE_S1 BIT(1) -#define EBPF_SAVE_S2 BIT(2) -#define EBPF_SAVE_S3 BIT(3) -#define EBPF_SAVE_S4 BIT(4) -#define EBPF_SAVE_RA BIT(5) -#define EBPF_SEEN_FP BIT(6) -#define EBPF_SEEN_TC BIT(7) -#define EBPF_TCC_IN_V1 BIT(8) - -/* - * For the mips64 ISA, we need to track the value range or type for - * each JIT register. The BPF machine requires zero extended 32-bit - * values, but the mips64 ISA requires sign extended 32-bit values. - * At each point in the BPF program we track the state of every - * register so that we can zero extend or sign extend as the BPF - * semantics require. - */ -enum reg_val_type { - /* uninitialized */ - REG_UNKNOWN, - /* not known to be 32-bit compatible. */ - REG_64BIT, - /* 32-bit compatible, no truncation needed for 64-bit ops. */ - REG_64BIT_32BIT, - /* 32-bit compatible, need truncation for 64-bit ops. */ - REG_32BIT, - /* 32-bit no sign/zero extension needed. */ - REG_32BIT_POS -}; - -/* - * high bit of offsets indicates if long branch conversion done at - * this insn. - */ -#define OFFSETS_B_CONV BIT(31) - -/** - * struct jit_ctx - JIT context - * @skf: The sk_filter - * @stack_size: eBPF stack size - * @idx: Instruction index - * @flags: JIT flags - * @offsets: Instruction offsets - * @target: Memory location for the compiled filter - * @reg_val_types Packed enum reg_val_type for each register. - */ -struct jit_ctx { - const struct bpf_prog *skf; - int stack_size; - u32 idx; - u32 flags; - u32 *offsets; - u32 *target; - u64 *reg_val_types; - unsigned int long_b_conversion:1; - unsigned int gen_b_offsets:1; - unsigned int use_bbit_insns:1; -}; - -static void set_reg_val_type(u64 *rvt, int reg, enum reg_val_type type) -{ - *rvt &= ~(7ull << (reg * 3)); - *rvt |= ((u64)type << (reg * 3)); -} - -static enum reg_val_type get_reg_val_type(const struct jit_ctx *ctx, - int index, int reg) -{ - return (ctx->reg_val_types[index] >> (reg * 3)) & 7; -} - -/* Simply emit the instruction if the JIT memory space has been allocated */ -#define emit_instr_long(ctx, func64, func32, ...) \ -do { \ - if ((ctx)->target != NULL) { \ - u32 *p = &(ctx)->target[ctx->idx]; \ - if (IS_ENABLED(CONFIG_64BIT)) \ - uasm_i_##func64(&p, ##__VA_ARGS__); \ - else \ - uasm_i_##func32(&p, ##__VA_ARGS__); \ - } \ - (ctx)->idx++; \ -} while (0) - -#define emit_instr(ctx, func, ...) \ - emit_instr_long(ctx, func, func, ##__VA_ARGS__) - -static unsigned int j_target(struct jit_ctx *ctx, int target_idx) -{ - unsigned long target_va, base_va; - unsigned int r; - - if (!ctx->target) - return 0; - - base_va = (unsigned long)ctx->target; - target_va = base_va + (ctx->offsets[target_idx] & ~OFFSETS_B_CONV); - - if ((base_va & ~0x0ffffffful) != (target_va & ~0x0ffffffful)) - return (unsigned int)-1; - r = target_va & 0x0ffffffful; - return r; -} - -/* Compute the immediate value for PC-relative branches. */ -static u32 b_imm(unsigned int tgt, struct jit_ctx *ctx) -{ - if (!ctx->gen_b_offsets) - return 0; - - /* - * We want a pc-relative branch. tgt is the instruction offset - * we want to jump to. - - * Branch on MIPS: - * I: target_offset <- sign_extend(offset) - * I+1: PC += target_offset (delay slot) - * - * ctx->idx currently points to the branch instruction - * but the offset is added to the delay slot so we need - * to subtract 4. - */ - return (ctx->offsets[tgt] & ~OFFSETS_B_CONV) - - (ctx->idx * 4) - 4; -} - -enum which_ebpf_reg { - src_reg, - src_reg_no_fp, - dst_reg, - dst_reg_fp_ok -}; - -/* - * For eBPF, the register mapping naturally falls out of the - * requirements of eBPF and the MIPS n64 ABI. We don't maintain a - * separate frame pointer, so BPF_REG_10 relative accesses are - * adjusted to be $sp relative. - */ -static int ebpf_to_mips_reg(struct jit_ctx *ctx, - const struct bpf_insn *insn, - enum which_ebpf_reg w) -{ - int ebpf_reg = (w == src_reg || w == src_reg_no_fp) ? - insn->src_reg : insn->dst_reg; - - switch (ebpf_reg) { - case BPF_REG_0: - return MIPS_R_V0; - case BPF_REG_1: - return MIPS_R_A0; - case BPF_REG_2: - return MIPS_R_A1; - case BPF_REG_3: - return MIPS_R_A2; - case BPF_REG_4: - return MIPS_R_A3; - case BPF_REG_5: - return MIPS_R_A4; - case BPF_REG_6: - ctx->flags |= EBPF_SAVE_S0; - return MIPS_R_S0; - case BPF_REG_7: - ctx->flags |= EBPF_SAVE_S1; - return MIPS_R_S1; - case BPF_REG_8: - ctx->flags |= EBPF_SAVE_S2; - return MIPS_R_S2; - case BPF_REG_9: - ctx->flags |= EBPF_SAVE_S3; - return MIPS_R_S3; - case BPF_REG_10: - if (w == dst_reg || w == src_reg_no_fp) - goto bad_reg; - ctx->flags |= EBPF_SEEN_FP; - /* - * Needs special handling, return something that - * cannot be clobbered just in case. - */ - return MIPS_R_ZERO; - case BPF_REG_AX: - return MIPS_R_T4; - default: -bad_reg: - WARN(1, "Illegal bpf reg: %d\n", ebpf_reg); - return -EINVAL; - } -} -/* - * eBPF stack frame will be something like: - * - * Entry $sp ------> +--------------------------------+ - * | $ra (optional) | - * +--------------------------------+ - * | $s0 (optional) | - * +--------------------------------+ - * | $s1 (optional) | - * +--------------------------------+ - * | $s2 (optional) | - * +--------------------------------+ - * | $s3 (optional) | - * +--------------------------------+ - * | $s4 (optional) | - * +--------------------------------+ - * | tmp-storage (if $ra saved) | - * $sp + tmp_offset --> +--------------------------------+ <--BPF_REG_10 - * | BPF_REG_10 relative storage | - * | MAX_BPF_STACK (optional) | - * | . | - * | . | - * | . | - * $sp --------> +--------------------------------+ - * - * If BPF_REG_10 is never referenced, then the MAX_BPF_STACK sized - * area is not allocated. - */ -static int gen_int_prologue(struct jit_ctx *ctx) -{ - int stack_adjust = 0; - int store_offset; - int locals_size; - - if (ctx->flags & EBPF_SAVE_RA) - /* - * If RA we are doing a function call and may need - * extra 8-byte tmp area. - */ - stack_adjust += 2 * sizeof(long); - if (ctx->flags & EBPF_SAVE_S0) - stack_adjust += sizeof(long); - if (ctx->flags & EBPF_SAVE_S1) - stack_adjust += sizeof(long); - if (ctx->flags & EBPF_SAVE_S2) - stack_adjust += sizeof(long); - if (ctx->flags & EBPF_SAVE_S3) - stack_adjust += sizeof(long); - if (ctx->flags & EBPF_SAVE_S4) - stack_adjust += sizeof(long); - - BUILD_BUG_ON(MAX_BPF_STACK & 7); - locals_size = (ctx->flags & EBPF_SEEN_FP) ? MAX_BPF_STACK : 0; - - stack_adjust += locals_size; - - ctx->stack_size = stack_adjust; - - /* - * First instruction initializes the tail call count (TCC). - * On tail call we skip this instruction, and the TCC is - * passed in $v1 from the caller. - */ - emit_instr(ctx, addiu, MIPS_R_V1, MIPS_R_ZERO, MAX_TAIL_CALL_CNT); - if (stack_adjust) - emit_instr_long(ctx, daddiu, addiu, - MIPS_R_SP, MIPS_R_SP, -stack_adjust); - else - return 0; - - store_offset = stack_adjust - sizeof(long); - - if (ctx->flags & EBPF_SAVE_RA) { - emit_instr_long(ctx, sd, sw, - MIPS_R_RA, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S0) { - emit_instr_long(ctx, sd, sw, - MIPS_R_S0, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S1) { - emit_instr_long(ctx, sd, sw, - MIPS_R_S1, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S2) { - emit_instr_long(ctx, sd, sw, - MIPS_R_S2, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S3) { - emit_instr_long(ctx, sd, sw, - MIPS_R_S3, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S4) { - emit_instr_long(ctx, sd, sw, - MIPS_R_S4, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - - if ((ctx->flags & EBPF_SEEN_TC) && !(ctx->flags & EBPF_TCC_IN_V1)) - emit_instr_long(ctx, daddu, addu, - MIPS_R_S4, MIPS_R_V1, MIPS_R_ZERO); - - return 0; -} - -static int build_int_epilogue(struct jit_ctx *ctx, int dest_reg) -{ - const struct bpf_prog *prog = ctx->skf; - int stack_adjust = ctx->stack_size; - int store_offset = stack_adjust - sizeof(long); - enum reg_val_type td; - int r0 = MIPS_R_V0; - - if (dest_reg == MIPS_R_RA) { - /* Don't let zero extended value escape. */ - td = get_reg_val_type(ctx, prog->len, BPF_REG_0); - if (td == REG_64BIT) - emit_instr(ctx, sll, r0, r0, 0); - } - - if (ctx->flags & EBPF_SAVE_RA) { - emit_instr_long(ctx, ld, lw, - MIPS_R_RA, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S0) { - emit_instr_long(ctx, ld, lw, - MIPS_R_S0, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S1) { - emit_instr_long(ctx, ld, lw, - MIPS_R_S1, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S2) { - emit_instr_long(ctx, ld, lw, - MIPS_R_S2, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S3) { - emit_instr_long(ctx, ld, lw, - MIPS_R_S3, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - if (ctx->flags & EBPF_SAVE_S4) { - emit_instr_long(ctx, ld, lw, - MIPS_R_S4, store_offset, MIPS_R_SP); - store_offset -= sizeof(long); - } - emit_instr(ctx, jr, dest_reg); - - if (stack_adjust) - emit_instr_long(ctx, daddiu, addiu, - MIPS_R_SP, MIPS_R_SP, stack_adjust); - else - emit_instr(ctx, nop); - - return 0; -} - -static void gen_imm_to_reg(const struct bpf_insn *insn, int reg, - struct jit_ctx *ctx) -{ - if (insn->imm >= S16_MIN && insn->imm <= S16_MAX) { - emit_instr(ctx, addiu, reg, MIPS_R_ZERO, insn->imm); - } else { - int lower = (s16)(insn->imm & 0xffff); - int upper = insn->imm - lower; - - emit_instr(ctx, lui, reg, upper >> 16); - emit_instr(ctx, addiu, reg, reg, lower); - } -} - -static int gen_imm_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, - int idx) -{ - int upper_bound, lower_bound; - int dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - - if (dst < 0) - return dst; - - switch (BPF_OP(insn->code)) { - case BPF_MOV: - case BPF_ADD: - upper_bound = S16_MAX; - lower_bound = S16_MIN; - break; - case BPF_SUB: - upper_bound = -(int)S16_MIN; - lower_bound = -(int)S16_MAX; - break; - case BPF_AND: - case BPF_OR: - case BPF_XOR: - upper_bound = 0xffff; - lower_bound = 0; - break; - case BPF_RSH: - case BPF_LSH: - case BPF_ARSH: - /* Shift amounts are truncated, no need for bounds */ - upper_bound = S32_MAX; - lower_bound = S32_MIN; - break; - default: - return -EINVAL; - } - - /* - * Immediate move clobbers the register, so no sign/zero - * extension needed. - */ - if (BPF_CLASS(insn->code) == BPF_ALU64 && - BPF_OP(insn->code) != BPF_MOV && - get_reg_val_type(ctx, idx, insn->dst_reg) == REG_32BIT) - emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); - /* BPF_ALU | BPF_LSH doesn't need separate sign extension */ - if (BPF_CLASS(insn->code) == BPF_ALU && - BPF_OP(insn->code) != BPF_LSH && - BPF_OP(insn->code) != BPF_MOV && - get_reg_val_type(ctx, idx, insn->dst_reg) != REG_32BIT) - emit_instr(ctx, sll, dst, dst, 0); - - if (insn->imm >= lower_bound && insn->imm <= upper_bound) { - /* single insn immediate case */ - switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) { - case BPF_ALU64 | BPF_MOV: - emit_instr(ctx, daddiu, dst, MIPS_R_ZERO, insn->imm); - break; - case BPF_ALU64 | BPF_AND: - case BPF_ALU | BPF_AND: - emit_instr(ctx, andi, dst, dst, insn->imm); - break; - case BPF_ALU64 | BPF_OR: - case BPF_ALU | BPF_OR: - emit_instr(ctx, ori, dst, dst, insn->imm); - break; - case BPF_ALU64 | BPF_XOR: - case BPF_ALU | BPF_XOR: - emit_instr(ctx, xori, dst, dst, insn->imm); - break; - case BPF_ALU64 | BPF_ADD: - emit_instr(ctx, daddiu, dst, dst, insn->imm); - break; - case BPF_ALU64 | BPF_SUB: - emit_instr(ctx, daddiu, dst, dst, -insn->imm); - break; - case BPF_ALU64 | BPF_RSH: - emit_instr(ctx, dsrl_safe, dst, dst, insn->imm & 0x3f); - break; - case BPF_ALU | BPF_RSH: - emit_instr(ctx, srl, dst, dst, insn->imm & 0x1f); - break; - case BPF_ALU64 | BPF_LSH: - emit_instr(ctx, dsll_safe, dst, dst, insn->imm & 0x3f); - break; - case BPF_ALU | BPF_LSH: - emit_instr(ctx, sll, dst, dst, insn->imm & 0x1f); - break; - case BPF_ALU64 | BPF_ARSH: - emit_instr(ctx, dsra_safe, dst, dst, insn->imm & 0x3f); - break; - case BPF_ALU | BPF_ARSH: - emit_instr(ctx, sra, dst, dst, insn->imm & 0x1f); - break; - case BPF_ALU | BPF_MOV: - emit_instr(ctx, addiu, dst, MIPS_R_ZERO, insn->imm); - break; - case BPF_ALU | BPF_ADD: - emit_instr(ctx, addiu, dst, dst, insn->imm); - break; - case BPF_ALU | BPF_SUB: - emit_instr(ctx, addiu, dst, dst, -insn->imm); - break; - default: - return -EINVAL; - } - } else { - /* multi insn immediate case */ - if (BPF_OP(insn->code) == BPF_MOV) { - gen_imm_to_reg(insn, dst, ctx); - } else { - gen_imm_to_reg(insn, MIPS_R_AT, ctx); - switch (BPF_OP(insn->code) | BPF_CLASS(insn->code)) { - case BPF_ALU64 | BPF_AND: - case BPF_ALU | BPF_AND: - emit_instr(ctx, and, dst, dst, MIPS_R_AT); - break; - case BPF_ALU64 | BPF_OR: - case BPF_ALU | BPF_OR: - emit_instr(ctx, or, dst, dst, MIPS_R_AT); - break; - case BPF_ALU64 | BPF_XOR: - case BPF_ALU | BPF_XOR: - emit_instr(ctx, xor, dst, dst, MIPS_R_AT); - break; - case BPF_ALU64 | BPF_ADD: - emit_instr(ctx, daddu, dst, dst, MIPS_R_AT); - break; - case BPF_ALU64 | BPF_SUB: - emit_instr(ctx, dsubu, dst, dst, MIPS_R_AT); - break; - case BPF_ALU | BPF_ADD: - emit_instr(ctx, addu, dst, dst, MIPS_R_AT); - break; - case BPF_ALU | BPF_SUB: - emit_instr(ctx, subu, dst, dst, MIPS_R_AT); - break; - default: - return -EINVAL; - } - } - } - - return 0; -} - -static void emit_const_to_reg(struct jit_ctx *ctx, int dst, u64 value) -{ - if (value >= 0xffffffffffff8000ull || value < 0x8000ull) { - emit_instr(ctx, daddiu, dst, MIPS_R_ZERO, (int)value); - } else if (value >= 0xffffffff80000000ull || - (value < 0x80000000 && value > 0xffff)) { - emit_instr(ctx, lui, dst, (s32)(s16)(value >> 16)); - emit_instr(ctx, ori, dst, dst, (unsigned int)(value & 0xffff)); - } else { - int i; - bool seen_part = false; - int needed_shift = 0; - - for (i = 0; i < 4; i++) { - u64 part = (value >> (16 * (3 - i))) & 0xffff; - - if (seen_part && needed_shift > 0 && (part || i == 3)) { - emit_instr(ctx, dsll_safe, dst, dst, needed_shift); - needed_shift = 0; - } - if (part) { - if (i == 0 || (!seen_part && i < 3 && part < 0x8000)) { - emit_instr(ctx, lui, dst, (s32)(s16)part); - needed_shift = -16; - } else { - emit_instr(ctx, ori, dst, - seen_part ? dst : MIPS_R_ZERO, - (unsigned int)part); - } - seen_part = true; - } - if (seen_part) - needed_shift += 16; - } - } -} - -static int emit_bpf_tail_call(struct jit_ctx *ctx, int this_idx) -{ - int off, b_off; - int tcc_reg; - - ctx->flags |= EBPF_SEEN_TC; - /* - * if (index >= array->map.max_entries) - * goto out; - */ - off = offsetof(struct bpf_array, map.max_entries); - emit_instr(ctx, lwu, MIPS_R_T5, off, MIPS_R_A1); - emit_instr(ctx, sltu, MIPS_R_AT, MIPS_R_T5, MIPS_R_A2); - b_off = b_imm(this_idx + 1, ctx); - emit_instr(ctx, bne, MIPS_R_AT, MIPS_R_ZERO, b_off); - /* - * if (TCC-- < 0) - * goto out; - */ - /* Delay slot */ - tcc_reg = (ctx->flags & EBPF_TCC_IN_V1) ? MIPS_R_V1 : MIPS_R_S4; - emit_instr(ctx, daddiu, MIPS_R_T5, tcc_reg, -1); - b_off = b_imm(this_idx + 1, ctx); - emit_instr(ctx, bltz, tcc_reg, b_off); - /* - * prog = array->ptrs[index]; - * if (prog == NULL) - * goto out; - */ - /* Delay slot */ - emit_instr(ctx, dsll, MIPS_R_T8, MIPS_R_A2, 3); - emit_instr(ctx, daddu, MIPS_R_T8, MIPS_R_T8, MIPS_R_A1); - off = offsetof(struct bpf_array, ptrs); - emit_instr(ctx, ld, MIPS_R_AT, off, MIPS_R_T8); - b_off = b_imm(this_idx + 1, ctx); - emit_instr(ctx, beq, MIPS_R_AT, MIPS_R_ZERO, b_off); - /* Delay slot */ - emit_instr(ctx, nop); - - /* goto *(prog->bpf_func + 4); */ - off = offsetof(struct bpf_prog, bpf_func); - emit_instr(ctx, ld, MIPS_R_T9, off, MIPS_R_AT); - /* All systems are go... propagate TCC */ - emit_instr(ctx, daddu, MIPS_R_V1, MIPS_R_T5, MIPS_R_ZERO); - /* Skip first instruction (TCC initialization) */ - emit_instr(ctx, daddiu, MIPS_R_T9, MIPS_R_T9, 4); - return build_int_epilogue(ctx, MIPS_R_T9); -} - -static bool is_bad_offset(int b_off) -{ - return b_off > 0x1ffff || b_off < -0x20000; -} - -/* Returns the number of insn slots consumed. */ -static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, - int this_idx, int exit_idx) -{ - int src, dst, r, td, ts, mem_off, b_off; - bool need_swap, did_move, cmp_eq; - unsigned int target = 0; - u64 t64; - s64 t64s; - int bpf_op = BPF_OP(insn->code); - - if (IS_ENABLED(CONFIG_32BIT) && ((BPF_CLASS(insn->code) == BPF_ALU64) - || (bpf_op == BPF_DW))) - return -EINVAL; - - switch (insn->code) { - case BPF_ALU64 | BPF_ADD | BPF_K: /* ALU64_IMM */ - case BPF_ALU64 | BPF_SUB | BPF_K: /* ALU64_IMM */ - case BPF_ALU64 | BPF_OR | BPF_K: /* ALU64_IMM */ - case BPF_ALU64 | BPF_AND | BPF_K: /* ALU64_IMM */ - case BPF_ALU64 | BPF_LSH | BPF_K: /* ALU64_IMM */ - case BPF_ALU64 | BPF_RSH | BPF_K: /* ALU64_IMM */ - case BPF_ALU64 | BPF_XOR | BPF_K: /* ALU64_IMM */ - case BPF_ALU64 | BPF_ARSH | BPF_K: /* ALU64_IMM */ - case BPF_ALU64 | BPF_MOV | BPF_K: /* ALU64_IMM */ - case BPF_ALU | BPF_MOV | BPF_K: /* ALU32_IMM */ - case BPF_ALU | BPF_ADD | BPF_K: /* ALU32_IMM */ - case BPF_ALU | BPF_SUB | BPF_K: /* ALU32_IMM */ - case BPF_ALU | BPF_OR | BPF_K: /* ALU64_IMM */ - case BPF_ALU | BPF_AND | BPF_K: /* ALU64_IMM */ - case BPF_ALU | BPF_LSH | BPF_K: /* ALU64_IMM */ - case BPF_ALU | BPF_RSH | BPF_K: /* ALU64_IMM */ - case BPF_ALU | BPF_XOR | BPF_K: /* ALU64_IMM */ - case BPF_ALU | BPF_ARSH | BPF_K: /* ALU64_IMM */ - r = gen_imm_insn(insn, ctx, this_idx); - if (r < 0) - return r; - break; - case BPF_ALU64 | BPF_MUL | BPF_K: /* ALU64_IMM */ - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) - emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); - if (insn->imm == 1) /* Mult by 1 is a nop */ - break; - gen_imm_to_reg(insn, MIPS_R_AT, ctx); - if (MIPS_ISA_REV >= 6) { - emit_instr(ctx, dmulu, dst, dst, MIPS_R_AT); - } else { - emit_instr(ctx, dmultu, MIPS_R_AT, dst); - emit_instr(ctx, mflo, dst); - } - break; - case BPF_ALU64 | BPF_NEG | BPF_K: /* ALU64_IMM */ - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) - emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); - emit_instr(ctx, dsubu, dst, MIPS_R_ZERO, dst); - break; - case BPF_ALU | BPF_MUL | BPF_K: /* ALU_IMM */ - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - td = get_reg_val_type(ctx, this_idx, insn->dst_reg); - if (td == REG_64BIT) { - /* sign extend */ - emit_instr(ctx, sll, dst, dst, 0); - } - if (insn->imm == 1) /* Mult by 1 is a nop */ - break; - gen_imm_to_reg(insn, MIPS_R_AT, ctx); - if (MIPS_ISA_REV >= 6) { - emit_instr(ctx, mulu, dst, dst, MIPS_R_AT); - } else { - emit_instr(ctx, multu, dst, MIPS_R_AT); - emit_instr(ctx, mflo, dst); - } - break; - case BPF_ALU | BPF_NEG | BPF_K: /* ALU_IMM */ - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - td = get_reg_val_type(ctx, this_idx, insn->dst_reg); - if (td == REG_64BIT) { - /* sign extend */ - emit_instr(ctx, sll, dst, dst, 0); - } - emit_instr(ctx, subu, dst, MIPS_R_ZERO, dst); - break; - case BPF_ALU | BPF_DIV | BPF_K: /* ALU_IMM */ - case BPF_ALU | BPF_MOD | BPF_K: /* ALU_IMM */ - if (insn->imm == 0) - return -EINVAL; - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - td = get_reg_val_type(ctx, this_idx, insn->dst_reg); - if (td == REG_64BIT) - /* sign extend */ - emit_instr(ctx, sll, dst, dst, 0); - if (insn->imm == 1) { - /* div by 1 is a nop, mod by 1 is zero */ - if (bpf_op == BPF_MOD) - emit_instr(ctx, addu, dst, MIPS_R_ZERO, MIPS_R_ZERO); - break; - } - gen_imm_to_reg(insn, MIPS_R_AT, ctx); - if (MIPS_ISA_REV >= 6) { - if (bpf_op == BPF_DIV) - emit_instr(ctx, divu_r6, dst, dst, MIPS_R_AT); - else - emit_instr(ctx, modu, dst, dst, MIPS_R_AT); - break; - } - emit_instr(ctx, divu, dst, MIPS_R_AT); - if (bpf_op == BPF_DIV) - emit_instr(ctx, mflo, dst); - else - emit_instr(ctx, mfhi, dst); - break; - case BPF_ALU64 | BPF_DIV | BPF_K: /* ALU_IMM */ - case BPF_ALU64 | BPF_MOD | BPF_K: /* ALU_IMM */ - if (insn->imm == 0) - return -EINVAL; - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) - emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); - if (insn->imm == 1) { - /* div by 1 is a nop, mod by 1 is zero */ - if (bpf_op == BPF_MOD) - emit_instr(ctx, addu, dst, MIPS_R_ZERO, MIPS_R_ZERO); - break; - } - gen_imm_to_reg(insn, MIPS_R_AT, ctx); - if (MIPS_ISA_REV >= 6) { - if (bpf_op == BPF_DIV) - emit_instr(ctx, ddivu_r6, dst, dst, MIPS_R_AT); - else - emit_instr(ctx, modu, dst, dst, MIPS_R_AT); - break; - } - emit_instr(ctx, ddivu, dst, MIPS_R_AT); - if (bpf_op == BPF_DIV) - emit_instr(ctx, mflo, dst); - else - emit_instr(ctx, mfhi, dst); - break; - case BPF_ALU64 | BPF_MOV | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_ADD | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_SUB | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_XOR | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_OR | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_AND | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_MUL | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_DIV | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_MOD | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_LSH | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_RSH | BPF_X: /* ALU64_REG */ - case BPF_ALU64 | BPF_ARSH | BPF_X: /* ALU64_REG */ - src = ebpf_to_mips_reg(ctx, insn, src_reg); - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (src < 0 || dst < 0) - return -EINVAL; - if (get_reg_val_type(ctx, this_idx, insn->dst_reg) == REG_32BIT) - emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); - did_move = false; - if (insn->src_reg == BPF_REG_10) { - if (bpf_op == BPF_MOV) { - emit_instr(ctx, daddiu, dst, MIPS_R_SP, MAX_BPF_STACK); - did_move = true; - } else { - emit_instr(ctx, daddiu, MIPS_R_AT, MIPS_R_SP, MAX_BPF_STACK); - src = MIPS_R_AT; - } - } else if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) { - int tmp_reg = MIPS_R_AT; - - if (bpf_op == BPF_MOV) { - tmp_reg = dst; - did_move = true; - } - emit_instr(ctx, daddu, tmp_reg, src, MIPS_R_ZERO); - emit_instr(ctx, dinsu, tmp_reg, MIPS_R_ZERO, 32, 32); - src = MIPS_R_AT; - } - switch (bpf_op) { - case BPF_MOV: - if (!did_move) - emit_instr(ctx, daddu, dst, src, MIPS_R_ZERO); - break; - case BPF_ADD: - emit_instr(ctx, daddu, dst, dst, src); - break; - case BPF_SUB: - emit_instr(ctx, dsubu, dst, dst, src); - break; - case BPF_XOR: - emit_instr(ctx, xor, dst, dst, src); - break; - case BPF_OR: - emit_instr(ctx, or, dst, dst, src); - break; - case BPF_AND: - emit_instr(ctx, and, dst, dst, src); - break; - case BPF_MUL: - if (MIPS_ISA_REV >= 6) { - emit_instr(ctx, dmulu, dst, dst, src); - } else { - emit_instr(ctx, dmultu, dst, src); - emit_instr(ctx, mflo, dst); - } - break; - case BPF_DIV: - case BPF_MOD: - if (MIPS_ISA_REV >= 6) { - if (bpf_op == BPF_DIV) - emit_instr(ctx, ddivu_r6, - dst, dst, src); - else - emit_instr(ctx, modu, dst, dst, src); - break; - } - emit_instr(ctx, ddivu, dst, src); - if (bpf_op == BPF_DIV) - emit_instr(ctx, mflo, dst); - else - emit_instr(ctx, mfhi, dst); - break; - case BPF_LSH: - emit_instr(ctx, dsllv, dst, dst, src); - break; - case BPF_RSH: - emit_instr(ctx, dsrlv, dst, dst, src); - break; - case BPF_ARSH: - emit_instr(ctx, dsrav, dst, dst, src); - break; - default: - pr_err("ALU64_REG NOT HANDLED\n"); - return -EINVAL; - } - break; - case BPF_ALU | BPF_MOV | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_ADD | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_SUB | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_XOR | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_OR | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_AND | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_MUL | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_DIV | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_MOD | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_LSH | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_RSH | BPF_X: /* ALU_REG */ - case BPF_ALU | BPF_ARSH | BPF_X: /* ALU_REG */ - src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp); - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (src < 0 || dst < 0) - return -EINVAL; - td = get_reg_val_type(ctx, this_idx, insn->dst_reg); - if (td == REG_64BIT) { - /* sign extend */ - emit_instr(ctx, sll, dst, dst, 0); - } - did_move = false; - ts = get_reg_val_type(ctx, this_idx, insn->src_reg); - if (ts == REG_64BIT) { - int tmp_reg = MIPS_R_AT; - - if (bpf_op == BPF_MOV) { - tmp_reg = dst; - did_move = true; - } - /* sign extend */ - emit_instr(ctx, sll, tmp_reg, src, 0); - src = MIPS_R_AT; - } - switch (bpf_op) { - case BPF_MOV: - if (!did_move) - emit_instr(ctx, addu, dst, src, MIPS_R_ZERO); - break; - case BPF_ADD: - emit_instr(ctx, addu, dst, dst, src); - break; - case BPF_SUB: - emit_instr(ctx, subu, dst, dst, src); - break; - case BPF_XOR: - emit_instr(ctx, xor, dst, dst, src); - break; - case BPF_OR: - emit_instr(ctx, or, dst, dst, src); - break; - case BPF_AND: - emit_instr(ctx, and, dst, dst, src); - break; - case BPF_MUL: - emit_instr(ctx, mul, dst, dst, src); - break; - case BPF_DIV: - case BPF_MOD: - if (MIPS_ISA_REV >= 6) { - if (bpf_op == BPF_DIV) - emit_instr(ctx, divu_r6, dst, dst, src); - else - emit_instr(ctx, modu, dst, dst, src); - break; - } - emit_instr(ctx, divu, dst, src); - if (bpf_op == BPF_DIV) - emit_instr(ctx, mflo, dst); - else - emit_instr(ctx, mfhi, dst); - break; - case BPF_LSH: - emit_instr(ctx, sllv, dst, dst, src); - break; - case BPF_RSH: - emit_instr(ctx, srlv, dst, dst, src); - break; - case BPF_ARSH: - emit_instr(ctx, srav, dst, dst, src); - break; - default: - pr_err("ALU_REG NOT HANDLED\n"); - return -EINVAL; - } - break; - case BPF_JMP | BPF_EXIT: - if (this_idx + 1 < exit_idx) { - b_off = b_imm(exit_idx, ctx); - if (is_bad_offset(b_off)) - return -E2BIG; - emit_instr(ctx, beq, MIPS_R_ZERO, MIPS_R_ZERO, b_off); - emit_instr(ctx, nop); - } - break; - case BPF_JMP | BPF_JEQ | BPF_K: /* JMP_IMM */ - case BPF_JMP | BPF_JNE | BPF_K: /* JMP_IMM */ - cmp_eq = (bpf_op == BPF_JEQ); - dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok); - if (dst < 0) - return dst; - if (insn->imm == 0) { - src = MIPS_R_ZERO; - } else { - gen_imm_to_reg(insn, MIPS_R_AT, ctx); - src = MIPS_R_AT; - } - goto jeq_common; - case BPF_JMP | BPF_JEQ | BPF_X: /* JMP_REG */ - case BPF_JMP | BPF_JNE | BPF_X: - case BPF_JMP | BPF_JSLT | BPF_X: - case BPF_JMP | BPF_JSLE | BPF_X: - case BPF_JMP | BPF_JSGT | BPF_X: - case BPF_JMP | BPF_JSGE | BPF_X: - case BPF_JMP | BPF_JLT | BPF_X: - case BPF_JMP | BPF_JLE | BPF_X: - case BPF_JMP | BPF_JGT | BPF_X: - case BPF_JMP | BPF_JGE | BPF_X: - case BPF_JMP | BPF_JSET | BPF_X: - src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp); - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (src < 0 || dst < 0) - return -EINVAL; - td = get_reg_val_type(ctx, this_idx, insn->dst_reg); - ts = get_reg_val_type(ctx, this_idx, insn->src_reg); - if (td == REG_32BIT && ts != REG_32BIT) { - emit_instr(ctx, sll, MIPS_R_AT, src, 0); - src = MIPS_R_AT; - } else if (ts == REG_32BIT && td != REG_32BIT) { - emit_instr(ctx, sll, MIPS_R_AT, dst, 0); - dst = MIPS_R_AT; - } - if (bpf_op == BPF_JSET) { - emit_instr(ctx, and, MIPS_R_AT, dst, src); - cmp_eq = false; - dst = MIPS_R_AT; - src = MIPS_R_ZERO; - } else if (bpf_op == BPF_JSGT || bpf_op == BPF_JSLE) { - emit_instr(ctx, dsubu, MIPS_R_AT, dst, src); - if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) { - b_off = b_imm(exit_idx, ctx); - if (is_bad_offset(b_off)) - return -E2BIG; - if (bpf_op == BPF_JSGT) - emit_instr(ctx, blez, MIPS_R_AT, b_off); - else - emit_instr(ctx, bgtz, MIPS_R_AT, b_off); - emit_instr(ctx, nop); - return 2; /* We consumed the exit. */ - } - b_off = b_imm(this_idx + insn->off + 1, ctx); - if (is_bad_offset(b_off)) - return -E2BIG; - if (bpf_op == BPF_JSGT) - emit_instr(ctx, bgtz, MIPS_R_AT, b_off); - else - emit_instr(ctx, blez, MIPS_R_AT, b_off); - emit_instr(ctx, nop); - break; - } else if (bpf_op == BPF_JSGE || bpf_op == BPF_JSLT) { - emit_instr(ctx, slt, MIPS_R_AT, dst, src); - cmp_eq = bpf_op == BPF_JSGE; - dst = MIPS_R_AT; - src = MIPS_R_ZERO; - } else if (bpf_op == BPF_JGT || bpf_op == BPF_JLE) { - /* dst or src could be AT */ - emit_instr(ctx, dsubu, MIPS_R_T8, dst, src); - emit_instr(ctx, sltu, MIPS_R_AT, dst, src); - /* SP known to be non-zero, movz becomes boolean not */ - if (MIPS_ISA_REV >= 6) { - emit_instr(ctx, seleqz, MIPS_R_T9, - MIPS_R_SP, MIPS_R_T8); - } else { - emit_instr(ctx, movz, MIPS_R_T9, - MIPS_R_SP, MIPS_R_T8); - emit_instr(ctx, movn, MIPS_R_T9, - MIPS_R_ZERO, MIPS_R_T8); - } - emit_instr(ctx, or, MIPS_R_AT, MIPS_R_T9, MIPS_R_AT); - cmp_eq = bpf_op == BPF_JGT; - dst = MIPS_R_AT; - src = MIPS_R_ZERO; - } else if (bpf_op == BPF_JGE || bpf_op == BPF_JLT) { - emit_instr(ctx, sltu, MIPS_R_AT, dst, src); - cmp_eq = bpf_op == BPF_JGE; - dst = MIPS_R_AT; - src = MIPS_R_ZERO; - } else { /* JNE/JEQ case */ - cmp_eq = (bpf_op == BPF_JEQ); - } -jeq_common: - /* - * If the next insn is EXIT and we are jumping arround - * only it, invert the sense of the compare and - * conditionally jump to the exit. Poor man's branch - * chaining. - */ - if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) { - b_off = b_imm(exit_idx, ctx); - if (is_bad_offset(b_off)) { - target = j_target(ctx, exit_idx); - if (target == (unsigned int)-1) - return -E2BIG; - cmp_eq = !cmp_eq; - b_off = 4 * 3; - if (!(ctx->offsets[this_idx] & OFFSETS_B_CONV)) { - ctx->offsets[this_idx] |= OFFSETS_B_CONV; - ctx->long_b_conversion = 1; - } - } - - if (cmp_eq) - emit_instr(ctx, bne, dst, src, b_off); - else - emit_instr(ctx, beq, dst, src, b_off); - emit_instr(ctx, nop); - if (ctx->offsets[this_idx] & OFFSETS_B_CONV) { - emit_instr(ctx, j, target); - emit_instr(ctx, nop); - } - return 2; /* We consumed the exit. */ - } - b_off = b_imm(this_idx + insn->off + 1, ctx); - if (is_bad_offset(b_off)) { - target = j_target(ctx, this_idx + insn->off + 1); - if (target == (unsigned int)-1) - return -E2BIG; - cmp_eq = !cmp_eq; - b_off = 4 * 3; - if (!(ctx->offsets[this_idx] & OFFSETS_B_CONV)) { - ctx->offsets[this_idx] |= OFFSETS_B_CONV; - ctx->long_b_conversion = 1; - } - } - - if (cmp_eq) - emit_instr(ctx, beq, dst, src, b_off); - else - emit_instr(ctx, bne, dst, src, b_off); - emit_instr(ctx, nop); - if (ctx->offsets[this_idx] & OFFSETS_B_CONV) { - emit_instr(ctx, j, target); - emit_instr(ctx, nop); - } - break; - case BPF_JMP | BPF_JSGT | BPF_K: /* JMP_IMM */ - case BPF_JMP | BPF_JSGE | BPF_K: /* JMP_IMM */ - case BPF_JMP | BPF_JSLT | BPF_K: /* JMP_IMM */ - case BPF_JMP | BPF_JSLE | BPF_K: /* JMP_IMM */ - cmp_eq = (bpf_op == BPF_JSGE); - dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok); - if (dst < 0) - return dst; - - if (insn->imm == 0) { - if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) { - b_off = b_imm(exit_idx, ctx); - if (is_bad_offset(b_off)) - return -E2BIG; - switch (bpf_op) { - case BPF_JSGT: - emit_instr(ctx, blez, dst, b_off); - break; - case BPF_JSGE: - emit_instr(ctx, bltz, dst, b_off); - break; - case BPF_JSLT: - emit_instr(ctx, bgez, dst, b_off); - break; - case BPF_JSLE: - emit_instr(ctx, bgtz, dst, b_off); - break; - } - emit_instr(ctx, nop); - return 2; /* We consumed the exit. */ - } - b_off = b_imm(this_idx + insn->off + 1, ctx); - if (is_bad_offset(b_off)) - return -E2BIG; - switch (bpf_op) { - case BPF_JSGT: - emit_instr(ctx, bgtz, dst, b_off); - break; - case BPF_JSGE: - emit_instr(ctx, bgez, dst, b_off); - break; - case BPF_JSLT: - emit_instr(ctx, bltz, dst, b_off); - break; - case BPF_JSLE: - emit_instr(ctx, blez, dst, b_off); - break; - } - emit_instr(ctx, nop); - break; - } - /* - * only "LT" compare available, so we must use imm + 1 - * to generate "GT" and imm -1 to generate LE - */ - if (bpf_op == BPF_JSGT) - t64s = insn->imm + 1; - else if (bpf_op == BPF_JSLE) - t64s = insn->imm + 1; - else - t64s = insn->imm; - - cmp_eq = bpf_op == BPF_JSGT || bpf_op == BPF_JSGE; - if (t64s >= S16_MIN && t64s <= S16_MAX) { - emit_instr(ctx, slti, MIPS_R_AT, dst, (int)t64s); - src = MIPS_R_AT; - dst = MIPS_R_ZERO; - goto jeq_common; - } - emit_const_to_reg(ctx, MIPS_R_AT, (u64)t64s); - emit_instr(ctx, slt, MIPS_R_AT, dst, MIPS_R_AT); - src = MIPS_R_AT; - dst = MIPS_R_ZERO; - goto jeq_common; - - case BPF_JMP | BPF_JGT | BPF_K: - case BPF_JMP | BPF_JGE | BPF_K: - case BPF_JMP | BPF_JLT | BPF_K: - case BPF_JMP | BPF_JLE | BPF_K: - cmp_eq = (bpf_op == BPF_JGE); - dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok); - if (dst < 0) - return dst; - /* - * only "LT" compare available, so we must use imm + 1 - * to generate "GT" and imm -1 to generate LE - */ - if (bpf_op == BPF_JGT) - t64s = (u64)(u32)(insn->imm) + 1; - else if (bpf_op == BPF_JLE) - t64s = (u64)(u32)(insn->imm) + 1; - else - t64s = (u64)(u32)(insn->imm); - - cmp_eq = bpf_op == BPF_JGT || bpf_op == BPF_JGE; - - emit_const_to_reg(ctx, MIPS_R_AT, (u64)t64s); - emit_instr(ctx, sltu, MIPS_R_AT, dst, MIPS_R_AT); - src = MIPS_R_AT; - dst = MIPS_R_ZERO; - goto jeq_common; - - case BPF_JMP | BPF_JSET | BPF_K: /* JMP_IMM */ - dst = ebpf_to_mips_reg(ctx, insn, dst_reg_fp_ok); - if (dst < 0) - return dst; - - if (ctx->use_bbit_insns && hweight32((u32)insn->imm) == 1) { - if ((insn + 1)->code == (BPF_JMP | BPF_EXIT) && insn->off == 1) { - b_off = b_imm(exit_idx, ctx); - if (is_bad_offset(b_off)) - return -E2BIG; - emit_instr(ctx, bbit0, dst, ffs((u32)insn->imm) - 1, b_off); - emit_instr(ctx, nop); - return 2; /* We consumed the exit. */ - } - b_off = b_imm(this_idx + insn->off + 1, ctx); - if (is_bad_offset(b_off)) - return -E2BIG; - emit_instr(ctx, bbit1, dst, ffs((u32)insn->imm) - 1, b_off); - emit_instr(ctx, nop); - break; - } - t64 = (u32)insn->imm; - emit_const_to_reg(ctx, MIPS_R_AT, t64); - emit_instr(ctx, and, MIPS_R_AT, dst, MIPS_R_AT); - src = MIPS_R_AT; - dst = MIPS_R_ZERO; - cmp_eq = false; - goto jeq_common; - - case BPF_JMP | BPF_JA: - /* - * Prefer relative branch for easier debugging, but - * fall back if needed. - */ - b_off = b_imm(this_idx + insn->off + 1, ctx); - if (is_bad_offset(b_off)) { - target = j_target(ctx, this_idx + insn->off + 1); - if (target == (unsigned int)-1) - return -E2BIG; - emit_instr(ctx, j, target); - } else { - emit_instr(ctx, b, b_off); - } - emit_instr(ctx, nop); - break; - case BPF_LD | BPF_DW | BPF_IMM: - if (insn->src_reg != 0) - return -EINVAL; - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - t64 = ((u64)(u32)insn->imm) | ((u64)(insn + 1)->imm << 32); - emit_const_to_reg(ctx, dst, t64); - return 2; /* Double slot insn */ - - case BPF_JMP | BPF_CALL: - ctx->flags |= EBPF_SAVE_RA; - t64s = (s64)insn->imm + (long)__bpf_call_base; - emit_const_to_reg(ctx, MIPS_R_T9, (u64)t64s); - emit_instr(ctx, jalr, MIPS_R_RA, MIPS_R_T9); - /* delay slot */ - emit_instr(ctx, nop); - break; - - case BPF_JMP | BPF_TAIL_CALL: - if (emit_bpf_tail_call(ctx, this_idx)) - return -EINVAL; - break; - - case BPF_ALU | BPF_END | BPF_FROM_BE: - case BPF_ALU | BPF_END | BPF_FROM_LE: - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - td = get_reg_val_type(ctx, this_idx, insn->dst_reg); - if (insn->imm == 64 && td == REG_32BIT) - emit_instr(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); - - if (insn->imm != 64 && td == REG_64BIT) { - /* sign extend */ - emit_instr(ctx, sll, dst, dst, 0); - } - -#ifdef __BIG_ENDIAN - need_swap = (BPF_SRC(insn->code) == BPF_FROM_LE); -#else - need_swap = (BPF_SRC(insn->code) == BPF_FROM_BE); -#endif - if (insn->imm == 16) { - if (need_swap) - emit_instr(ctx, wsbh, dst, dst); - emit_instr(ctx, andi, dst, dst, 0xffff); - } else if (insn->imm == 32) { - if (need_swap) { - emit_instr(ctx, wsbh, dst, dst); - emit_instr(ctx, rotr, dst, dst, 16); - } - } else { /* 64-bit*/ - if (need_swap) { - emit_instr(ctx, dsbh, dst, dst); - emit_instr(ctx, dshd, dst, dst); - } - } - break; - - case BPF_ST | BPF_NOSPEC: /* speculation barrier */ - break; - - case BPF_ST | BPF_B | BPF_MEM: - case BPF_ST | BPF_H | BPF_MEM: - case BPF_ST | BPF_W | BPF_MEM: - case BPF_ST | BPF_DW | BPF_MEM: - if (insn->dst_reg == BPF_REG_10) { - ctx->flags |= EBPF_SEEN_FP; - dst = MIPS_R_SP; - mem_off = insn->off + MAX_BPF_STACK; - } else { - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - mem_off = insn->off; - } - gen_imm_to_reg(insn, MIPS_R_AT, ctx); - switch (BPF_SIZE(insn->code)) { - case BPF_B: - emit_instr(ctx, sb, MIPS_R_AT, mem_off, dst); - break; - case BPF_H: - emit_instr(ctx, sh, MIPS_R_AT, mem_off, dst); - break; - case BPF_W: - emit_instr(ctx, sw, MIPS_R_AT, mem_off, dst); - break; - case BPF_DW: - emit_instr(ctx, sd, MIPS_R_AT, mem_off, dst); - break; - } - break; - - case BPF_LDX | BPF_B | BPF_MEM: - case BPF_LDX | BPF_H | BPF_MEM: - case BPF_LDX | BPF_W | BPF_MEM: - case BPF_LDX | BPF_DW | BPF_MEM: - if (insn->src_reg == BPF_REG_10) { - ctx->flags |= EBPF_SEEN_FP; - src = MIPS_R_SP; - mem_off = insn->off + MAX_BPF_STACK; - } else { - src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp); - if (src < 0) - return src; - mem_off = insn->off; - } - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - switch (BPF_SIZE(insn->code)) { - case BPF_B: - emit_instr(ctx, lbu, dst, mem_off, src); - break; - case BPF_H: - emit_instr(ctx, lhu, dst, mem_off, src); - break; - case BPF_W: - emit_instr(ctx, lw, dst, mem_off, src); - break; - case BPF_DW: - emit_instr(ctx, ld, dst, mem_off, src); - break; - } - break; - - case BPF_STX | BPF_B | BPF_MEM: - case BPF_STX | BPF_H | BPF_MEM: - case BPF_STX | BPF_W | BPF_MEM: - case BPF_STX | BPF_DW | BPF_MEM: - case BPF_STX | BPF_W | BPF_ATOMIC: - case BPF_STX | BPF_DW | BPF_ATOMIC: - if (insn->dst_reg == BPF_REG_10) { - ctx->flags |= EBPF_SEEN_FP; - dst = MIPS_R_SP; - mem_off = insn->off + MAX_BPF_STACK; - } else { - dst = ebpf_to_mips_reg(ctx, insn, dst_reg); - if (dst < 0) - return dst; - mem_off = insn->off; - } - src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp); - if (src < 0) - return src; - if (BPF_MODE(insn->code) == BPF_ATOMIC) { - if (insn->imm != BPF_ADD) { - pr_err("ATOMIC OP %02x NOT HANDLED\n", insn->imm); - return -EINVAL; - } - - /* - * If mem_off does not fit within the 9 bit ll/sc - * instruction immediate field, use a temp reg. - */ - if (MIPS_ISA_REV >= 6 && - (mem_off >= BIT(8) || mem_off < -BIT(8))) { - emit_instr(ctx, daddiu, MIPS_R_T6, - dst, mem_off); - mem_off = 0; - dst = MIPS_R_T6; - } - switch (BPF_SIZE(insn->code)) { - case BPF_W: - if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) { - emit_instr(ctx, sll, MIPS_R_AT, src, 0); - src = MIPS_R_AT; - } - emit_instr(ctx, ll, MIPS_R_T8, mem_off, dst); - emit_instr(ctx, addu, MIPS_R_T8, MIPS_R_T8, src); - emit_instr(ctx, sc, MIPS_R_T8, mem_off, dst); - /* - * On failure back up to LL (-4 - * instructions of 4 bytes each - */ - emit_instr(ctx, beq, MIPS_R_T8, MIPS_R_ZERO, -4 * 4); - emit_instr(ctx, nop); - break; - case BPF_DW: - if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) { - emit_instr(ctx, daddu, MIPS_R_AT, src, MIPS_R_ZERO); - emit_instr(ctx, dinsu, MIPS_R_AT, MIPS_R_ZERO, 32, 32); - src = MIPS_R_AT; - } - emit_instr(ctx, lld, MIPS_R_T8, mem_off, dst); - emit_instr(ctx, daddu, MIPS_R_T8, MIPS_R_T8, src); - emit_instr(ctx, scd, MIPS_R_T8, mem_off, dst); - emit_instr(ctx, beq, MIPS_R_T8, MIPS_R_ZERO, -4 * 4); - emit_instr(ctx, nop); - break; - } - } else { /* BPF_MEM */ - switch (BPF_SIZE(insn->code)) { - case BPF_B: - emit_instr(ctx, sb, src, mem_off, dst); - break; - case BPF_H: - emit_instr(ctx, sh, src, mem_off, dst); - break; - case BPF_W: - emit_instr(ctx, sw, src, mem_off, dst); - break; - case BPF_DW: - if (get_reg_val_type(ctx, this_idx, insn->src_reg) == REG_32BIT) { - emit_instr(ctx, daddu, MIPS_R_AT, src, MIPS_R_ZERO); - emit_instr(ctx, dinsu, MIPS_R_AT, MIPS_R_ZERO, 32, 32); - src = MIPS_R_AT; - } - emit_instr(ctx, sd, src, mem_off, dst); - break; - } - } - break; - - default: - pr_err("NOT HANDLED %d - (%02x)\n", - this_idx, (unsigned int)insn->code); - return -EINVAL; - } - return 1; -} - -#define RVT_VISITED_MASK 0xc000000000000000ull -#define RVT_FALL_THROUGH 0x4000000000000000ull -#define RVT_BRANCH_TAKEN 0x8000000000000000ull -#define RVT_DONE (RVT_FALL_THROUGH | RVT_BRANCH_TAKEN) - -static int build_int_body(struct jit_ctx *ctx) -{ - const struct bpf_prog *prog = ctx->skf; - const struct bpf_insn *insn; - int i, r; - - for (i = 0; i < prog->len; ) { - insn = prog->insnsi + i; - if ((ctx->reg_val_types[i] & RVT_VISITED_MASK) == 0) { - /* dead instruction, don't emit it. */ - i++; - continue; - } - - if (ctx->target == NULL) - ctx->offsets[i] = (ctx->offsets[i] & OFFSETS_B_CONV) | (ctx->idx * 4); - - r = build_one_insn(insn, ctx, i, prog->len); - if (r < 0) - return r; - i += r; - } - /* epilogue offset */ - if (ctx->target == NULL) - ctx->offsets[i] = ctx->idx * 4; - - /* - * All exits have an offset of the epilogue, some offsets may - * not have been set due to banch-around threading, so set - * them now. - */ - if (ctx->target == NULL) - for (i = 0; i < prog->len; i++) { - insn = prog->insnsi + i; - if (insn->code == (BPF_JMP | BPF_EXIT)) - ctx->offsets[i] = ctx->idx * 4; - } - return 0; -} - -/* return the last idx processed, or negative for error */ -static int reg_val_propagate_range(struct jit_ctx *ctx, u64 initial_rvt, - int start_idx, bool follow_taken) -{ - const struct bpf_prog *prog = ctx->skf; - const struct bpf_insn *insn; - u64 exit_rvt = initial_rvt; - u64 *rvt = ctx->reg_val_types; - int idx; - int reg; - - for (idx = start_idx; idx < prog->len; idx++) { - rvt[idx] = (rvt[idx] & RVT_VISITED_MASK) | exit_rvt; - insn = prog->insnsi + idx; - switch (BPF_CLASS(insn->code)) { - case BPF_ALU: - switch (BPF_OP(insn->code)) { - case BPF_ADD: - case BPF_SUB: - case BPF_MUL: - case BPF_DIV: - case BPF_OR: - case BPF_AND: - case BPF_LSH: - case BPF_RSH: - case BPF_NEG: - case BPF_MOD: - case BPF_XOR: - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); - break; - case BPF_MOV: - if (BPF_SRC(insn->code)) { - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); - } else { - /* IMM to REG move*/ - if (insn->imm >= 0) - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); - else - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); - } - break; - case BPF_END: - if (insn->imm == 64) - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); - else if (insn->imm == 32) - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); - else /* insn->imm == 16 */ - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); - break; - } - rvt[idx] |= RVT_DONE; - break; - case BPF_ALU64: - switch (BPF_OP(insn->code)) { - case BPF_MOV: - if (BPF_SRC(insn->code)) { - /* REG to REG move*/ - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); - } else { - /* IMM to REG move*/ - if (insn->imm >= 0) - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); - else - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT_32BIT); - } - break; - default: - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); - } - rvt[idx] |= RVT_DONE; - break; - case BPF_LD: - switch (BPF_SIZE(insn->code)) { - case BPF_DW: - if (BPF_MODE(insn->code) == BPF_IMM) { - s64 val; - - val = (s64)((u32)insn->imm | ((u64)(insn + 1)->imm << 32)); - if (val > 0 && val <= S32_MAX) - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); - else if (val >= S32_MIN && val <= S32_MAX) - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT_32BIT); - else - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); - rvt[idx] |= RVT_DONE; - idx++; - } else { - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); - } - break; - case BPF_B: - case BPF_H: - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); - break; - case BPF_W: - if (BPF_MODE(insn->code) == BPF_IMM) - set_reg_val_type(&exit_rvt, insn->dst_reg, - insn->imm >= 0 ? REG_32BIT_POS : REG_32BIT); - else - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); - break; - } - rvt[idx] |= RVT_DONE; - break; - case BPF_LDX: - switch (BPF_SIZE(insn->code)) { - case BPF_DW: - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_64BIT); - break; - case BPF_B: - case BPF_H: - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT_POS); - break; - case BPF_W: - set_reg_val_type(&exit_rvt, insn->dst_reg, REG_32BIT); - break; - } - rvt[idx] |= RVT_DONE; - break; - case BPF_JMP: - switch (BPF_OP(insn->code)) { - case BPF_EXIT: - rvt[idx] = RVT_DONE | exit_rvt; - rvt[prog->len] = exit_rvt; - return idx; - case BPF_JA: - rvt[idx] |= RVT_DONE; - idx += insn->off; - break; - case BPF_JEQ: - case BPF_JGT: - case BPF_JGE: - case BPF_JLT: - case BPF_JLE: - case BPF_JSET: - case BPF_JNE: - case BPF_JSGT: - case BPF_JSGE: - case BPF_JSLT: - case BPF_JSLE: - if (follow_taken) { - rvt[idx] |= RVT_BRANCH_TAKEN; - idx += insn->off; - follow_taken = false; - } else { - rvt[idx] |= RVT_FALL_THROUGH; - } - break; - case BPF_CALL: - set_reg_val_type(&exit_rvt, BPF_REG_0, REG_64BIT); - /* Upon call return, argument registers are clobbered. */ - for (reg = BPF_REG_0; reg <= BPF_REG_5; reg++) - set_reg_val_type(&exit_rvt, reg, REG_64BIT); - - rvt[idx] |= RVT_DONE; - break; - default: - WARN(1, "Unhandled BPF_JMP case.\n"); - rvt[idx] |= RVT_DONE; - break; - } - break; - default: - rvt[idx] |= RVT_DONE; - break; - } - } - return idx; -} - -/* - * Track the value range (i.e. 32-bit vs. 64-bit) of each register at - * each eBPF insn. This allows unneeded sign and zero extension - * operations to be omitted. - * - * Doesn't handle yet confluence of control paths with conflicting - * ranges, but it is good enough for most sane code. - */ -static int reg_val_propagate(struct jit_ctx *ctx) -{ - const struct bpf_prog *prog = ctx->skf; - u64 exit_rvt; - int reg; - int i; - - /* - * 11 registers * 3 bits/reg leaves top bits free for other - * uses. Bit-62..63 used to see if we have visited an insn. - */ - exit_rvt = 0; - - /* Upon entry, argument registers are 64-bit. */ - for (reg = BPF_REG_1; reg <= BPF_REG_5; reg++) - set_reg_val_type(&exit_rvt, reg, REG_64BIT); - - /* - * First follow all conditional branches on the fall-through - * edge of control flow.. - */ - reg_val_propagate_range(ctx, exit_rvt, 0, false); -restart_search: - /* - * Then repeatedly find the first conditional branch where - * both edges of control flow have not been taken, and follow - * the branch taken edge. We will end up restarting the - * search once per conditional branch insn. - */ - for (i = 0; i < prog->len; i++) { - u64 rvt = ctx->reg_val_types[i]; - - if ((rvt & RVT_VISITED_MASK) == RVT_DONE || - (rvt & RVT_VISITED_MASK) == 0) - continue; - if ((rvt & RVT_VISITED_MASK) == RVT_FALL_THROUGH) { - reg_val_propagate_range(ctx, rvt & ~RVT_VISITED_MASK, i, true); - } else { /* RVT_BRANCH_TAKEN */ - WARN(1, "Unexpected RVT_BRANCH_TAKEN case.\n"); - reg_val_propagate_range(ctx, rvt & ~RVT_VISITED_MASK, i, false); - } - goto restart_search; - } - /* - * Eventually all conditional branches have been followed on - * both branches and we are done. Any insn that has not been - * visited at this point is dead. - */ - - return 0; -} - -static void jit_fill_hole(void *area, unsigned int size) -{ - u32 *p; - - /* We are guaranteed to have aligned memory. */ - for (p = area; size >= sizeof(u32); size -= sizeof(u32)) - uasm_i_break(&p, BRK_BUG); /* Increments p */ -} - -struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) -{ - struct bpf_prog *orig_prog = prog; - bool tmp_blinded = false; - struct bpf_prog *tmp; - struct bpf_binary_header *header = NULL; - struct jit_ctx ctx; - unsigned int image_size; - u8 *image_ptr; - - if (!prog->jit_requested) - return prog; - - tmp = bpf_jit_blind_constants(prog); - /* If blinding was requested and we failed during blinding, - * we must fall back to the interpreter. - */ - if (IS_ERR(tmp)) - return orig_prog; - if (tmp != prog) { - tmp_blinded = true; - prog = tmp; - } - - memset(&ctx, 0, sizeof(ctx)); - - preempt_disable(); - switch (current_cpu_type()) { - case CPU_CAVIUM_OCTEON: - case CPU_CAVIUM_OCTEON_PLUS: - case CPU_CAVIUM_OCTEON2: - case CPU_CAVIUM_OCTEON3: - ctx.use_bbit_insns = 1; - break; - default: - ctx.use_bbit_insns = 0; - } - preempt_enable(); - - ctx.offsets = kcalloc(prog->len + 1, sizeof(*ctx.offsets), GFP_KERNEL); - if (ctx.offsets == NULL) - goto out_err; - - ctx.reg_val_types = kcalloc(prog->len + 1, sizeof(*ctx.reg_val_types), GFP_KERNEL); - if (ctx.reg_val_types == NULL) - goto out_err; - - ctx.skf = prog; - - if (reg_val_propagate(&ctx)) - goto out_err; - - /* - * First pass discovers used resources and instruction offsets - * assuming short branches are used. - */ - if (build_int_body(&ctx)) - goto out_err; - - /* - * If no calls are made (EBPF_SAVE_RA), then tail call count - * in $v1, else we must save in n$s4. - */ - if (ctx.flags & EBPF_SEEN_TC) { - if (ctx.flags & EBPF_SAVE_RA) - ctx.flags |= EBPF_SAVE_S4; - else - ctx.flags |= EBPF_TCC_IN_V1; - } - - /* - * Second pass generates offsets, if any branches are out of - * range a jump-around long sequence is generated, and we have - * to try again from the beginning to generate the new - * offsets. This is done until no additional conversions are - * necessary. - */ - do { - ctx.idx = 0; - ctx.gen_b_offsets = 1; - ctx.long_b_conversion = 0; - if (gen_int_prologue(&ctx)) - goto out_err; - if (build_int_body(&ctx)) - goto out_err; - if (build_int_epilogue(&ctx, MIPS_R_RA)) - goto out_err; - } while (ctx.long_b_conversion); - - image_size = 4 * ctx.idx; - - header = bpf_jit_binary_alloc(image_size, &image_ptr, - sizeof(u32), jit_fill_hole); - if (header == NULL) - goto out_err; - - ctx.target = (u32 *)image_ptr; - - /* Third pass generates the code */ - ctx.idx = 0; - if (gen_int_prologue(&ctx)) - goto out_err; - if (build_int_body(&ctx)) - goto out_err; - if (build_int_epilogue(&ctx, MIPS_R_RA)) - goto out_err; - - /* Update the icache */ - flush_icache_range((unsigned long)ctx.target, - (unsigned long)&ctx.target[ctx.idx]); - - if (bpf_jit_enable > 1) - /* Dump JIT code */ - bpf_jit_dump(prog->len, image_size, 2, ctx.target); - - bpf_jit_binary_lock_ro(header); - prog->bpf_func = (void *)ctx.target; - prog->jited = 1; - prog->jited_len = image_size; -out_normal: - if (tmp_blinded) - bpf_jit_prog_release_other(prog, prog == orig_prog ? - tmp : orig_prog); - kfree(ctx.offsets); - kfree(ctx.reg_val_types); - - return prog; - -out_err: - prog = orig_prog; - if (header) - bpf_jit_binary_free(header); - goto out_normal; -} diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig deleted file mode 100644 index 412351c5acc6..000000000000 --- a/arch/mips/netlogic/Kconfig +++ /dev/null @@ -1,86 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -if NLM_XLP_BOARD || NLM_XLR_BOARD - -if NLM_XLP_BOARD -config DT_XLP_EVP - bool "Built-in device tree for XLP EVP boards" - default y - select BUILTIN_DTB - help - Add an FDT blob for XLP EVP boards into the kernel. - This DTB will be used if the firmware does not pass in a DTB - pointer to the kernel. The corresponding DTS file is at - arch/mips/netlogic/dts/xlp_evp.dts - -config DT_XLP_SVP - bool "Built-in device tree for XLP SVP boards" - default y - select BUILTIN_DTB - help - Add an FDT blob for XLP VP boards into the kernel. - This DTB will be used if the firmware does not pass in a DTB - pointer to the kernel. The corresponding DTS file is at - arch/mips/netlogic/dts/xlp_svp.dts - -config DT_XLP_FVP - bool "Built-in device tree for XLP FVP boards" - default y - select BUILTIN_DTB - help - Add an FDT blob for XLP FVP board into the kernel. - This DTB will be used if the firmware does not pass in a DTB - pointer to the kernel. The corresponding DTS file is at - arch/mips/netlogic/dts/xlp_fvp.dts - -config DT_XLP_GVP - bool "Built-in device tree for XLP GVP boards" - default y - select BUILTIN_DTB - help - Add an FDT blob for XLP GVP board into the kernel. - This DTB will be used if the firmware does not pass in a DTB - pointer to the kernel. The corresponding DTS file is at - arch/mips/netlogic/dts/xlp_gvp.dts - -config DT_XLP_RVP - bool "Built-in device tree for XLP RVP boards" - default y - help - Add an FDT blob for XLP RVP board into the kernel. - This DTB will be used if the firmware does not pass in a DTB - pointer to the kernel. The corresponding DTS file is at - arch/mips/netlogic/dts/xlp_rvp.dts - -config NLM_MULTINODE - bool "Support for multi-chip boards" - depends on NLM_XLP_BOARD - default n - help - Add support for boards with 2 or 4 XLPs connected over ICI. - -if NLM_MULTINODE -choice - prompt "Number of XLPs on the board" - default NLM_MULTINODE_2 - help - In the multi-node case, specify the number of SoCs on the board. - -config NLM_MULTINODE_2 - bool "Dual-XLP board" - help - Support boards with upto two XLPs connected over ICI. - -config NLM_MULTINODE_4 - bool "Quad-XLP board" - help - Support boards with upto four XLPs connected over ICI. - -endchoice - -endif -endif - -config NLM_COMMON - bool - -endif diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile deleted file mode 100644 index c53561589db9..000000000000 --- a/arch/mips/netlogic/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_NLM_COMMON) += common/ -obj-$(CONFIG_CPU_XLR) += xlr/ -obj-$(CONFIG_CPU_XLP) += xlp/ diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform deleted file mode 100644 index 4195a097f5f2..000000000000 --- a/arch/mips/netlogic/Platform +++ /dev/null @@ -1,16 +0,0 @@ -# -# NETLOGIC includes -# -cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic -cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic - -# -# use mips64 if xlr is not available -# -cflags-$(CONFIG_CPU_XLR) += $(call cc-option,-march=xlr,-march=mips64) -cflags-$(CONFIG_CPU_XLP) += $(call cc-option,-march=xlp,-march=mips64r2) - -# -# NETLOGIC processor support -# -load-$(CONFIG_NLM_COMMON) += 0xffffffff80100000 diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile deleted file mode 100644 index 89f6e3f39fed..000000000000 --- a/arch/mips/netlogic/common/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-y += irq.o time.o -obj-y += reset.o -obj-$(CONFIG_SMP) += smp.o smpboot.o -obj-$(CONFIG_EARLY_PRINTK) += earlycons.o diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c deleted file mode 100644 index 8f5bc1597550..000000000000 --- a/arch/mips/netlogic/common/earlycons.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/types.h> -#include <linux/serial_reg.h> - -#include <asm/mipsregs.h> -#include <asm/setup.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> - -#if defined(CONFIG_CPU_XLP) -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/uart.h> -#elif defined(CONFIG_CPU_XLR) -#include <asm/netlogic/xlr/iomap.h> -#endif - -void prom_putchar(char c) -{ - uint64_t uartbase; - -#if defined(CONFIG_CPU_XLP) - uartbase = nlm_get_uart_regbase(0, 0); -#elif defined(CONFIG_CPU_XLR) - uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); -#endif - while ((nlm_read_reg(uartbase, UART_LSR) & UART_LSR_THRE) == 0) - ; - nlm_write_reg(uartbase, UART_TX, c); -} diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c deleted file mode 100644 index c25a2ce5e29f..000000000000 --- a/arch/mips/netlogic/common/irq.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/linkage.h> -#include <linux/interrupt.h> -#include <linux/mm.h> -#include <linux/slab.h> -#include <linux/irq.h> - -#include <linux/irqdomain.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> - -#include <asm/errno.h> -#include <asm/signal.h> -#include <asm/ptrace.h> -#include <asm/mipsregs.h> -#include <asm/thread_info.h> - -#include <asm/netlogic/mips-extns.h> -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> - -#if defined(CONFIG_CPU_XLP) -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/pic.h> -#elif defined(CONFIG_CPU_XLR) -#include <asm/netlogic/xlr/iomap.h> -#include <asm/netlogic/xlr/pic.h> -#include <asm/netlogic/xlr/fmn.h> -#else -#error "Unknown CPU" -#endif - -#ifdef CONFIG_SMP -#define SMP_IRQ_MASK ((1ULL << IRQ_IPI_SMP_FUNCTION) | \ - (1ULL << IRQ_IPI_SMP_RESCHEDULE)) -#else -#define SMP_IRQ_MASK 0 -#endif -#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \ - (1ull << IRQ_FMN)) - -struct nlm_pic_irq { - void (*extra_ack)(struct irq_data *); - struct nlm_soc_info *node; - int picirq; - int irt; - int flags; -}; - -static void xlp_pic_enable(struct irq_data *d) -{ - unsigned long flags; - struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d); - - BUG_ON(!pd); - spin_lock_irqsave(&pd->node->piclock, flags); - nlm_pic_enable_irt(pd->node->picbase, pd->irt); - spin_unlock_irqrestore(&pd->node->piclock, flags); -} - -static void xlp_pic_disable(struct irq_data *d) -{ - struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d); - unsigned long flags; - - BUG_ON(!pd); - spin_lock_irqsave(&pd->node->piclock, flags); - nlm_pic_disable_irt(pd->node->picbase, pd->irt); - spin_unlock_irqrestore(&pd->node->piclock, flags); -} - -static void xlp_pic_mask_ack(struct irq_data *d) -{ - struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d); - - clear_c0_eimr(pd->picirq); - ack_c0_eirr(pd->picirq); -} - -static void xlp_pic_unmask(struct irq_data *d) -{ - struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d); - - BUG_ON(!pd); - - if (pd->extra_ack) - pd->extra_ack(d); - - /* re-enable the intr on this cpu */ - set_c0_eimr(pd->picirq); - - /* Ack is a single write, no need to lock */ - nlm_pic_ack(pd->node->picbase, pd->irt); -} - -static struct irq_chip xlp_pic = { - .name = "XLP-PIC", - .irq_enable = xlp_pic_enable, - .irq_disable = xlp_pic_disable, - .irq_mask_ack = xlp_pic_mask_ack, - .irq_unmask = xlp_pic_unmask, -}; - -static void cpuintr_disable(struct irq_data *d) -{ - clear_c0_eimr(d->irq); -} - -static void cpuintr_enable(struct irq_data *d) -{ - set_c0_eimr(d->irq); -} - -static void cpuintr_ack(struct irq_data *d) -{ - ack_c0_eirr(d->irq); -} - -/* - * Chip definition for CPU originated interrupts(timer, msg) and - * IPIs - */ -struct irq_chip nlm_cpu_intr = { - .name = "XLP-CPU-INTR", - .irq_enable = cpuintr_enable, - .irq_disable = cpuintr_disable, - .irq_mask = cpuintr_disable, - .irq_ack = cpuintr_ack, - .irq_eoi = cpuintr_enable, -}; - -static void __init nlm_init_percpu_irqs(void) -{ - int i; - - for (i = 0; i < PIC_IRT_FIRST_IRQ; i++) - irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq); -#ifdef CONFIG_SMP - irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr, - nlm_smp_function_ipi_handler); - irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr, - nlm_smp_resched_ipi_handler); -#endif -} - - -void nlm_setup_pic_irq(int node, int picirq, int irq, int irt) -{ - struct nlm_pic_irq *pic_data; - int xirq; - - xirq = nlm_irq_to_xirq(node, irq); - pic_data = kzalloc(sizeof(*pic_data), GFP_KERNEL); - BUG_ON(pic_data == NULL); - pic_data->irt = irt; - pic_data->picirq = picirq; - pic_data->node = nlm_get_node(node); - irq_set_chip_and_handler(xirq, &xlp_pic, handle_level_irq); - irq_set_chip_data(xirq, pic_data); -} - -void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *)) -{ - struct nlm_pic_irq *pic_data; - int xirq; - - xirq = nlm_irq_to_xirq(node, irq); - pic_data = irq_get_chip_data(xirq); - if (WARN_ON(!pic_data)) - return; - pic_data->extra_ack = xack; -} - -static void nlm_init_node_irqs(int node) -{ - struct nlm_soc_info *nodep; - int i, irt; - - pr_info("Init IRQ for node %d\n", node); - nodep = nlm_get_node(node); - nodep->irqmask = PERCPU_IRQ_MASK; - for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) { - irt = nlm_irq_to_irt(i); - if (irt == -1) /* unused irq */ - continue; - nodep->irqmask |= 1ull << i; - if (irt == -2) /* not a direct PIC irq */ - continue; - - nlm_pic_init_irt(nodep->picbase, irt, i, - node * nlm_threads_per_node(), 0); - nlm_setup_pic_irq(node, i, i, irt); - } -} - -void nlm_smp_irq_init(int hwtid) -{ - int cpu, node; - - cpu = hwtid % nlm_threads_per_node(); - node = hwtid / nlm_threads_per_node(); - - if (cpu == 0 && node != 0) - nlm_init_node_irqs(node); - write_c0_eimr(nlm_get_node(node)->irqmask); -} - -asmlinkage void plat_irq_dispatch(void) -{ - uint64_t eirr; - int i, node; - - node = nlm_nodeid(); - eirr = read_c0_eirr_and_eimr(); - if (eirr == 0) - return; - - i = __ffs64(eirr); - /* per-CPU IRQs don't need translation */ - if (i < PIC_IRQ_BASE) { - do_IRQ(i); - return; - } - -#if defined(CONFIG_PCI_MSI) && defined(CONFIG_CPU_XLP) - /* PCI interrupts need a second level dispatch for MSI bits */ - if (i >= PIC_PCIE_LINK_MSI_IRQ(0) && i <= PIC_PCIE_LINK_MSI_IRQ(3)) { - nlm_dispatch_msi(node, i); - return; - } - if (i >= PIC_PCIE_MSIX_IRQ(0) && i <= PIC_PCIE_MSIX_IRQ(3)) { - nlm_dispatch_msix(node, i); - return; - } - -#endif - /* top level irq handling */ - do_IRQ(nlm_irq_to_xirq(node, i)); -} - -#ifdef CONFIG_CPU_XLP -static int __init xlp_of_pic_init(struct device_node *node, - struct device_node *parent) -{ - const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1; - struct irq_domain *xlp_pic_domain; - struct resource res; - int socid, ret, bus; - - /* we need a hack to get the PIC's SoC chip id */ - ret = of_address_to_resource(node, 0, &res); - if (ret < 0) { - pr_err("PIC %pOFn: reg property not found!\n", node); - return -EINVAL; - } - - if (cpu_is_xlp9xx()) { - bus = (res.start >> 20) & 0xf; - for (socid = 0; socid < NLM_NR_NODES; socid++) { - if (!nlm_node_present(socid)) - continue; - if (nlm_get_node(socid)->socbus == bus) - break; - } - if (socid == NLM_NR_NODES) { - pr_err("PIC %pOFn: Node mapping for bus %d not found!\n", - node, bus); - return -EINVAL; - } - } else { - socid = (res.start >> 18) & 0x3; - if (!nlm_node_present(socid)) { - pr_err("PIC %pOFn: node %d does not exist!\n", - node, socid); - return -EINVAL; - } - } - - if (!nlm_node_present(socid)) { - pr_err("PIC %pOFn: node %d does not exist!\n", node, socid); - return -EINVAL; - } - - xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs, - nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE, - &irq_domain_simple_ops, NULL); - if (xlp_pic_domain == NULL) { - pr_err("PIC %pOFn: Creating legacy domain failed!\n", node); - return -EINVAL; - } - pr_info("Node %d: IRQ domain created for PIC@%pR\n", socid, &res); - return 0; -} - -static struct of_device_id __initdata xlp_pic_irq_ids[] = { - { .compatible = "netlogic,xlp-pic", .data = xlp_of_pic_init }, - {}, -}; -#endif - -void __init arch_init_irq(void) -{ - /* Initialize the irq descriptors */ - nlm_init_percpu_irqs(); - nlm_init_node_irqs(0); - write_c0_eimr(nlm_current_node()->irqmask); -#if defined(CONFIG_CPU_XLR) - nlm_setup_fmn_irq(); -#endif -#ifdef CONFIG_CPU_XLP - of_irq_init(xlp_pic_irq_ids); -#endif -} diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S deleted file mode 100644 index c474981a6c0d..000000000000 --- a/arch/mips/netlogic/common/reset.S +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright 2003-2013 Broadcom Corporation. - * All Rights Reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -#include <asm/asm.h> -#include <asm/asm-offsets.h> -#include <asm/cpu.h> -#include <asm/cacheops.h> -#include <asm/regdef.h> -#include <asm/mipsregs.h> -#include <asm/stackframe.h> -#include <asm/asmmacro.h> -#include <asm/addrspace.h> - -#include <asm/netlogic/common.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/sys.h> -#include <asm/netlogic/xlp-hal/cpucontrol.h> - -#define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ - XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \ - SYS_CPU_NONCOHERENT_MODE * 4 - -/* Enable XLP features and workarounds in the LSU */ -.macro xlp_config_lsu - li t0, LSU_DEFEATURE - mfcr t1, t0 - - lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */ - or t1, t1, t2 - mtcr t1, t0 - - li t0, ICU_DEFEATURE - mfcr t1, t0 - ori t1, 0x1000 /* Enable Icache partitioning */ - mtcr t1, t0 - - li t0, SCHED_DEFEATURE - lui t1, 0x0100 /* Disable BRU accepting ALU ops */ - mtcr t1, t0 -.endm - -/* - * Allow access to physical mem >64G by enabling ELPA in PAGEGRAIN - * register. This is needed before going to C code since the SP can - * in this region. Called from all HW threads. - */ -.macro xlp_early_mmu_init - mfc0 t0, CP0_PAGEMASK, 1 - li t1, (1 << 29) /* ELPA bit */ - or t0, t1 - mtc0 t0, CP0_PAGEMASK, 1 -.endm - -/* - * L1D cache has to be flushed before enabling threads in XLP. - * On XLP8xx/XLP3xx, we do a low level flush using processor control - * registers. On XLPII CPUs, usual cache instructions work. - */ -.macro xlp_flush_l1_dcache - mfc0 t0, CP0_PRID - andi t0, t0, PRID_IMP_MASK - slt t1, t0, 0x1200 - beqz t1, 15f - nop - - /* XLP8xx low level cache flush */ - li t0, LSU_DEBUG_DATA0 - li t1, LSU_DEBUG_ADDR - li t2, 0 /* index */ - li t3, 0x1000 /* loop count */ -11: - sll v0, t2, 5 - mtcr zero, t0 - ori v1, v0, 0x3 /* way0 | write_enable | write_active */ - mtcr v1, t1 -12: - mfcr v1, t1 - andi v1, 0x1 /* wait for write_active == 0 */ - bnez v1, 12b - nop - mtcr zero, t0 - ori v1, v0, 0x7 /* way1 | write_enable | write_active */ - mtcr v1, t1 -13: - mfcr v1, t1 - andi v1, 0x1 /* wait for write_active == 0 */ - bnez v1, 13b - nop - addi t2, 1 - bne t3, t2, 11b - nop - b 17f - nop - - /* XLPII CPUs, Invalidate all 64k of L1 D-cache */ -15: - li t0, 0x80000000 - li t1, 0x80010000 -16: cache Index_Writeback_Inv_D, 0(t0) - addiu t0, t0, 32 - bne t0, t1, 16b - nop -17: -.endm - -/* - * nlm_reset_entry will be copied to the reset entry point for - * XLR and XLP. The XLP cores start here when they are woken up. This - * is also the NMI entry point. - * - * We use scratch reg 6/7 to save k0/k1 and check for NMI first. - * - * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS - * location, this will have the thread mask (used when core is woken up) - * and the current NMI handler in case we reached here for an NMI. - * - * When a core or thread is newly woken up, it marks itself ready and - * loops in a 'wait'. When the CPU really needs waking up, we send an NMI - * IPI to it, with the NMI handler set to prom_boot_secondary_cpus - */ - .set noreorder - .set noat - .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ - -FEXPORT(nlm_reset_entry) - dmtc0 k0, $22, 6 - dmtc0 k1, $22, 7 - mfc0 k0, CP0_STATUS - li k1, 0x80000 - and k1, k0, k1 - beqz k1, 1f /* go to real reset entry */ - nop - li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ - ld k0, BOOT_NMI_HANDLER(k1) - jr k0 - nop - -1: /* Entry point on core wakeup */ - mfc0 t0, CP0_PRID /* processor ID */ - andi t0, PRID_IMP_MASK - li t1, 0x1500 /* XLP 9xx */ - beq t0, t1, 2f /* does not need to set coherent */ - nop - - li t1, 0x1300 /* XLP 5xx */ - beq t0, t1, 2f /* does not need to set coherent */ - nop - - /* set bit in SYS coherent register for the core */ - mfc0 t0, CP0_EBASE - mfc0 t1, CP0_EBASE - srl t1, 5 - andi t1, 0x3 /* t1 <- node */ - li t2, 0x40000 - mul t3, t2, t1 /* t3 = node * 0x40000 */ - srl t0, t0, 2 - and t0, t0, 0x7 /* t0 <- core */ - li t1, 0x1 - sll t0, t1, t0 - nor t0, t0, zero /* t0 <- ~(1 << core) */ - li t2, SYS_CPU_COHERENT_BASE - add t2, t2, t3 /* t2 <- SYS offset for node */ - lw t1, 0(t2) - and t1, t1, t0 - sw t1, 0(t2) - - /* read back to ensure complete */ - lw t1, 0(t2) - sync - -2: - /* Configure LSU on Non-0 Cores. */ - xlp_config_lsu - /* FALL THROUGH */ - -/* - * Wake up sibling threads from the initial thread in a core. - */ -EXPORT(nlm_boot_siblings) - /* core L1D flush before enable threads */ - xlp_flush_l1_dcache - /* save ra and sp, will be used later (only for boot cpu) */ - dmtc0 ra, $22, 6 - dmtc0 sp, $22, 7 - /* Enable hw threads by writing to MAP_THREADMODE of the core */ - li t0, CKSEG1ADDR(RESET_DATA_PHYS) - lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ - li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) - mfcr t2, t0 - or t2, t2, t1 - mtcr t2, t0 - - /* - * The new hardware thread starts at the next instruction - * For all the cases other than core 0 thread 0, we will - * jump to the secondary wait function. - - * NOTE: All GPR contents are lost after the mtcr above! - */ - mfc0 v0, CP0_EBASE - andi v0, 0x3ff /* v0 <- node/core */ - - /* - * Errata: to avoid potential live lock, setup IFU_BRUB_RESERVE - * when running 4 threads per core - */ - andi v1, v0, 0x3 /* v1 <- thread id */ - bnez v1, 2f - nop - - /* thread 0 of each core. */ - li t0, CKSEG1ADDR(RESET_DATA_PHYS) - lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ - subu t1, 0x3 /* 4-thread per core mode? */ - bnez t1, 2f - nop - - li t0, IFU_BRUB_RESERVE - li t1, 0x55 - mtcr t1, t0 - _ehb -2: - beqz v0, 4f /* boot cpu (cpuid == 0)? */ - nop - - /* setup status reg */ - move t1, zero -#ifdef CONFIG_64BIT - ori t1, ST0_KX -#endif - mtc0 t1, CP0_STATUS - - xlp_early_mmu_init - - /* mark CPU ready */ - li t3, CKSEG1ADDR(RESET_DATA_PHYS) - ADDIU t1, t3, BOOT_CPU_READY - sll v1, v0, 2 - PTR_ADDU t1, v1 - li t2, 1 - sw t2, 0(t1) - /* Wait until NMI hits */ -3: wait - b 3b - nop - - /* - * For the boot CPU, we have to restore ra and sp and return, rest - * of the registers will be restored by the caller - */ -4: - dmfc0 ra, $22, 6 - dmfc0 sp, $22, 7 - jr ra - nop -EXPORT(nlm_reset_entry_end) - -LEAF(nlm_init_boot_cpu) -#ifdef CONFIG_CPU_XLP - xlp_config_lsu - xlp_early_mmu_init -#endif - jr ra - nop -END(nlm_init_boot_cpu) diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c deleted file mode 100644 index 39a300bd6cc2..000000000000 --- a/arch/mips/netlogic/common/smp.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/sched/task_stack.h> -#include <linux/smp.h> -#include <linux/irq.h> - -#include <asm/mmu_context.h> - -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/mips-extns.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> - -#if defined(CONFIG_CPU_XLP) -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/pic.h> -#elif defined(CONFIG_CPU_XLR) -#include <asm/netlogic/xlr/iomap.h> -#include <asm/netlogic/xlr/pic.h> -#include <asm/netlogic/xlr/xlr.h> -#else -#error "Unknown CPU" -#endif - -void nlm_send_ipi_single(int logical_cpu, unsigned int action) -{ - unsigned int hwtid; - uint64_t picbase; - - /* node id is part of hwtid, and needed for send_ipi */ - hwtid = cpu_logical_map(logical_cpu); - picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase; - - if (action & SMP_CALL_FUNCTION) - nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0); - if (action & SMP_RESCHEDULE_YOURSELF) - nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0); -} - -void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) -{ - int cpu; - - for_each_cpu(cpu, mask) { - nlm_send_ipi_single(cpu, action); - } -} - -/* IRQ_IPI_SMP_FUNCTION Handler */ -void nlm_smp_function_ipi_handler(struct irq_desc *desc) -{ - unsigned int irq = irq_desc_get_irq(desc); - clear_c0_eimr(irq); - ack_c0_eirr(irq); - generic_smp_call_function_interrupt(); - set_c0_eimr(irq); -} - -/* IRQ_IPI_SMP_RESCHEDULE handler */ -void nlm_smp_resched_ipi_handler(struct irq_desc *desc) -{ - unsigned int irq = irq_desc_get_irq(desc); - clear_c0_eimr(irq); - ack_c0_eirr(irq); - scheduler_ipi(); - set_c0_eimr(irq); -} - -/* - * Called before going into mips code, early cpu init - */ -void nlm_early_init_secondary(int cpu) -{ - change_c0_config(CONF_CM_CMASK, 0x3); -#ifdef CONFIG_CPU_XLP - xlp_mmu_init(); -#endif - write_c0_ebase(nlm_current_node()->ebase); -} - -/* - * Code to run on secondary just after probing the CPU - */ -static void nlm_init_secondary(void) -{ - int hwtid; - - hwtid = hard_smp_processor_id(); - cpu_set_core(¤t_cpu_data, hwtid / NLM_THREADS_PER_CORE); - current_cpu_data.package = nlm_nodeid(); - nlm_percpu_init(hwtid); - nlm_smp_irq_init(hwtid); -} - -void nlm_prepare_cpus(unsigned int max_cpus) -{ - /* declare we are SMT capable */ - smp_num_siblings = nlm_threads_per_core; -} - -void nlm_smp_finish(void) -{ - local_irq_enable(); -} - -/* - * Boot all other cpus in the system, initialize them, and bring them into - * the boot function - */ -unsigned long nlm_next_gp; -unsigned long nlm_next_sp; -static cpumask_t phys_cpu_present_mask; - -int nlm_boot_secondary(int logical_cpu, struct task_struct *idle) -{ - uint64_t picbase; - int hwtid; - - hwtid = cpu_logical_map(logical_cpu); - picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase; - - nlm_next_sp = (unsigned long)__KSTK_TOS(idle); - nlm_next_gp = (unsigned long)task_thread_info(idle); - - /* barrier for sp/gp store above */ - __sync(); - nlm_pic_send_ipi(picbase, hwtid, 1, 1); /* NMI */ - - return 0; -} - -void __init nlm_smp_setup(void) -{ - unsigned int boot_cpu; - int num_cpus, i, ncore, node; - volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); - - boot_cpu = hard_smp_processor_id(); - cpumask_clear(&phys_cpu_present_mask); - - cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask); - __cpu_number_map[boot_cpu] = 0; - __cpu_logical_map[0] = boot_cpu; - set_cpu_possible(0, true); - - num_cpus = 1; - for (i = 0; i < NR_CPUS; i++) { - /* - * cpu_ready array is not set for the boot_cpu, - * it is only set for ASPs (see smpboot.S) - */ - if (cpu_ready[i]) { - cpumask_set_cpu(i, &phys_cpu_present_mask); - __cpu_number_map[i] = num_cpus; - __cpu_logical_map[num_cpus] = i; - set_cpu_possible(num_cpus, true); - node = nlm_hwtid_to_node(i); - cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask); - ++num_cpus; - } - } - - pr_info("Physical CPU mask: %*pb\n", - cpumask_pr_args(&phys_cpu_present_mask)); - pr_info("Possible CPU mask: %*pb\n", - cpumask_pr_args(cpu_possible_mask)); - - /* check with the cores we have woken up */ - for (ncore = 0, i = 0; i < NLM_NR_NODES; i++) - ncore += hweight32(nlm_get_node(i)->coremask); - - pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore, - nlm_threads_per_core, num_cpus); - - /* switch NMI handler to boot CPUs */ - nlm_set_nmi_handler(nlm_boot_secondary_cpus); -} - -static int nlm_parse_cpumask(cpumask_t *wakeup_mask) -{ - uint32_t core0_thr_mask, core_thr_mask; - int threadmode, i, j; - - core0_thr_mask = 0; - for (i = 0; i < NLM_THREADS_PER_CORE; i++) - if (cpumask_test_cpu(i, wakeup_mask)) - core0_thr_mask |= (1 << i); - switch (core0_thr_mask) { - case 1: - nlm_threads_per_core = 1; - threadmode = 0; - break; - case 3: - nlm_threads_per_core = 2; - threadmode = 2; - break; - case 0xf: - nlm_threads_per_core = 4; - threadmode = 3; - break; - default: - goto unsupp; - } - - /* Verify other cores CPU masks */ - for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) { - core_thr_mask = 0; - for (j = 0; j < NLM_THREADS_PER_CORE; j++) - if (cpumask_test_cpu(i + j, wakeup_mask)) - core_thr_mask |= (1 << j); - if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask) - goto unsupp; - } - return threadmode; - -unsupp: - panic("Unsupported CPU mask %*pb", cpumask_pr_args(wakeup_mask)); - return 0; -} - -int nlm_wakeup_secondary_cpus(void) -{ - u32 *reset_data; - int threadmode; - - /* verify the mask and setup core config variables */ - threadmode = nlm_parse_cpumask(&nlm_cpumask); - - /* Setup CPU init parameters */ - reset_data = nlm_get_boot_data(BOOT_THREAD_MODE); - *reset_data = threadmode; - -#ifdef CONFIG_CPU_XLP - xlp_wakeup_secondary_cpus(); -#else - xlr_wakeup_secondary_cpus(); -#endif - return 0; -} - -const struct plat_smp_ops nlm_smp_ops = { - .send_ipi_single = nlm_send_ipi_single, - .send_ipi_mask = nlm_send_ipi_mask, - .init_secondary = nlm_init_secondary, - .smp_finish = nlm_smp_finish, - .boot_secondary = nlm_boot_secondary, - .smp_setup = nlm_smp_setup, - .prepare_cpus = nlm_prepare_cpus, -}; diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S deleted file mode 100644 index 509c1a7e7c05..000000000000 --- a/arch/mips/netlogic/common/smpboot.S +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -#include <asm/asm.h> -#include <asm/asm-offsets.h> -#include <asm/regdef.h> -#include <asm/mipsregs.h> -#include <asm/stackframe.h> -#include <asm/asmmacro.h> -#include <asm/addrspace.h> - -#include <asm/netlogic/common.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/sys.h> -#include <asm/netlogic/xlp-hal/cpucontrol.h> - - .set noreorder - .set noat - .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ - -/* Called by the boot cpu to wake up its sibling threads */ -NESTED(xlp_boot_core0_siblings, PT_SIZE, sp) - /* CPU register contents lost when enabling threads, save them first */ - SAVE_ALL - sync - /* find the location to which nlm_boot_siblings was relocated */ - li t0, CKSEG1ADDR(RESET_VEC_PHYS) - PTR_LA t1, nlm_reset_entry - PTR_LA t2, nlm_boot_siblings - dsubu t2, t1 - daddu t2, t0 - /* call it */ - jalr t2 - nop - RESTORE_ALL - jr ra - nop -END(xlp_boot_core0_siblings) - -NESTED(nlm_boot_secondary_cpus, 16, sp) - /* Initialize CP0 Status */ - move t1, zero -#ifdef CONFIG_64BIT - ori t1, ST0_KX -#endif - mtc0 t1, CP0_STATUS - PTR_LA t1, nlm_next_sp - PTR_L sp, 0(t1) - PTR_LA t1, nlm_next_gp - PTR_L gp, 0(t1) - - /* a0 has the processor id */ - mfc0 a0, CP0_EBASE - andi a0, 0x3ff /* a0 <- node/core */ - PTR_LA t0, nlm_early_init_secondary - jalr t0 - nop - - PTR_LA t0, smp_bootstrap - jr t0 - nop -END(nlm_boot_secondary_cpus) - -/* - * In case of RMIboot bootloader which is used on XLR boards, the CPUs - * be already woken up and waiting in bootloader code. - * This will get them out of the bootloader code and into linux. Needed - * because the bootloader area will be taken and initialized by linux. - */ -NESTED(nlm_rmiboot_preboot, 16, sp) - mfc0 t0, $15, 1 /* read ebase */ - andi t0, 0x1f /* t0 has the processor_id() */ - andi t2, t0, 0x3 /* thread num */ - sll t0, 2 /* offset in cpu array */ - - li t3, CKSEG1ADDR(RESET_DATA_PHYS) - ADDIU t1, t3, BOOT_CPU_READY - ADDU t1, t0 - li t3, 1 - sw t3, 0(t1) - - bnez t2, 1f /* skip thread programming */ - nop /* for thread id != 0 */ - - /* - * XLR MMU setup only for first thread in core - */ - li t0, 0x400 - mfcr t1, t0 - li t2, 6 /* XLR thread mode mask */ - nor t3, t2, zero - and t2, t1, t2 /* t2 - current thread mode */ - li v0, CKSEG1ADDR(RESET_DATA_PHYS) - lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */ - sll v1, 1 - beq v1, t2, 1f /* same as request value */ - nop /* nothing to do */ - - and t2, t1, t3 /* mask out old thread mode */ - or t1, t2, v1 /* put in new value */ - mtcr t1, t0 /* update core control */ - - /* wait for NMI to hit */ -1: wait - b 1b - nop -END(nlm_rmiboot_preboot) diff --git a/arch/mips/netlogic/common/time.c b/arch/mips/netlogic/common/time.c deleted file mode 100644 index cbbf0d48216b..000000000000 --- a/arch/mips/netlogic/common/time.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/init.h> - -#include <asm/time.h> -#include <asm/cpu-features.h> - -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/haldefs.h> - -#if defined(CONFIG_CPU_XLP) -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/sys.h> -#include <asm/netlogic/xlp-hal/pic.h> -#elif defined(CONFIG_CPU_XLR) -#include <asm/netlogic/xlr/iomap.h> -#include <asm/netlogic/xlr/pic.h> -#include <asm/netlogic/xlr/xlr.h> -#else -#error "Unknown CPU" -#endif - -unsigned int get_c0_compare_int(void) -{ - return IRQ_TIMER; -} - -static u64 nlm_get_pic_timer(struct clocksource *cs) -{ - uint64_t picbase = nlm_get_node(0)->picbase; - - return ~nlm_pic_read_timer(picbase, PIC_CLOCK_TIMER); -} - -static u64 nlm_get_pic_timer32(struct clocksource *cs) -{ - uint64_t picbase = nlm_get_node(0)->picbase; - - return ~nlm_pic_read_timer32(picbase, PIC_CLOCK_TIMER); -} - -static struct clocksource csrc_pic = { - .name = "PIC", - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static void nlm_init_pic_timer(void) -{ - uint64_t picbase = nlm_get_node(0)->picbase; - u32 picfreq; - - nlm_pic_set_timer(picbase, PIC_CLOCK_TIMER, ~0ULL, 0, 0); - if (current_cpu_data.cputype == CPU_XLR) { - csrc_pic.mask = CLOCKSOURCE_MASK(32); - csrc_pic.read = nlm_get_pic_timer32; - } else { - csrc_pic.mask = CLOCKSOURCE_MASK(64); - csrc_pic.read = nlm_get_pic_timer; - } - csrc_pic.rating = 1000; - picfreq = pic_timer_freq(); - clocksource_register_hz(&csrc_pic, picfreq); - pr_info("PIC clock source added, frequency %d\n", picfreq); -} - -void __init plat_time_init(void) -{ - nlm_init_pic_timer(); - mips_hpt_frequency = nlm_get_cpu_frequency(); - if (current_cpu_type() == CPU_XLR) - preset_lpj = mips_hpt_frequency / (3 * HZ); - else - preset_lpj = mips_hpt_frequency / (2 * HZ); - pr_info("MIPS counter frequency [%ld]\n", - (unsigned long)mips_hpt_frequency); -} diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile deleted file mode 100644 index d62465717393..000000000000 --- a/arch/mips/netlogic/xlp/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-y += setup.o nlm_hal.o cop2-ex.o dt.o -obj-$(CONFIG_SMP) += wakeup.o -ifdef CONFIG_USB -obj-y += usb-init.o -obj-y += usb-init-xlp2.o -endif -ifdef CONFIG_SATA_AHCI -obj-y += ahci-init.o -obj-y += ahci-init-xlp2.o -endif diff --git a/arch/mips/netlogic/xlp/ahci-init-xlp2.c b/arch/mips/netlogic/xlp/ahci-init-xlp2.c deleted file mode 100644 index c11b9c7dc7c8..000000000000 --- a/arch/mips/netlogic/xlp/ahci-init-xlp2.c +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2003-2014 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/dma-mapping.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/bitops.h> -#include <linux/pci_ids.h> -#include <linux/nodemask.h> - -#include <asm/cpu.h> -#include <asm/mipsregs.h> - -#include <asm/netlogic/common.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/mips-extns.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/iomap.h> - -#define SATA_CTL 0x0 -#define SATA_STATUS 0x1 /* Status Reg */ -#define SATA_INT 0x2 /* Interrupt Reg */ -#define SATA_INT_MASK 0x3 /* Interrupt Mask Reg */ -#define SATA_BIU_TIMEOUT 0x4 -#define AXIWRSPERRLOG 0x5 -#define AXIRDSPERRLOG 0x6 -#define BiuTimeoutLow 0x7 -#define BiuTimeoutHi 0x8 -#define BiuSlvErLow 0x9 -#define BiuSlvErHi 0xa -#define IO_CONFIG_SWAP_DIS 0xb -#define CR_REG_TIMER 0xc -#define CORE_ID 0xd -#define AXI_SLAVE_OPT1 0xe -#define PHY_MEM_ACCESS 0xf -#define PHY0_CNTRL 0x10 -#define PHY0_STAT 0x11 -#define PHY0_RX_ALIGN 0x12 -#define PHY0_RX_EQ_LO 0x13 -#define PHY0_RX_EQ_HI 0x14 -#define PHY0_BIST_LOOP 0x15 -#define PHY1_CNTRL 0x16 -#define PHY1_STAT 0x17 -#define PHY1_RX_ALIGN 0x18 -#define PHY1_RX_EQ_LO 0x19 -#define PHY1_RX_EQ_HI 0x1a -#define PHY1_BIST_LOOP 0x1b -#define RdExBase 0x1c -#define RdExLimit 0x1d -#define CacheAllocBase 0x1e -#define CacheAllocLimit 0x1f -#define BiuSlaveCmdGstNum 0x20 - -/*SATA_CTL Bits */ -#define SATA_RST_N BIT(0) /* Active low reset sata_core phy */ -#define SataCtlReserve0 BIT(1) -#define M_CSYSREQ BIT(2) /* AXI master low power, not used */ -#define S_CSYSREQ BIT(3) /* AXI slave low power, not used */ -#define P0_CP_DET BIT(8) /* Reserved, bring in from pad */ -#define P0_MP_SW BIT(9) /* Mech Switch */ -#define P0_DISABLE BIT(10) /* disable p0 */ -#define P0_ACT_LED_EN BIT(11) /* Active LED enable */ -#define P0_IRST_HARD_SYNTH BIT(12) /* PHY hard synth reset */ -#define P0_IRST_HARD_TXRX BIT(13) /* PHY lane hard reset */ -#define P0_IRST_POR BIT(14) /* PHY power on reset*/ -#define P0_IPDTXL BIT(15) /* PHY Tx lane dis/power down */ -#define P0_IPDRXL BIT(16) /* PHY Rx lane dis/power down */ -#define P0_IPDIPDMSYNTH BIT(17) /* PHY synthesizer dis/porwer down */ -#define P0_CP_POD_EN BIT(18) /* CP_POD enable */ -#define P0_AT_BYPASS BIT(19) /* P0 address translation by pass */ -#define P1_CP_DET BIT(20) /* Reserved,Cold Detect */ -#define P1_MP_SW BIT(21) /* Mech Switch */ -#define P1_DISABLE BIT(22) /* disable p1 */ -#define P1_ACT_LED_EN BIT(23) /* Active LED enable */ -#define P1_IRST_HARD_SYNTH BIT(24) /* PHY hard synth reset */ -#define P1_IRST_HARD_TXRX BIT(25) /* PHY lane hard reset */ -#define P1_IRST_POR BIT(26) /* PHY power on reset*/ -#define P1_IPDTXL BIT(27) /* PHY Tx lane dis/porwer down */ -#define P1_IPDRXL BIT(28) /* PHY Rx lane dis/porwer down */ -#define P1_IPDIPDMSYNTH BIT(29) /* PHY synthesizer dis/porwer down */ -#define P1_CP_POD_EN BIT(30) -#define P1_AT_BYPASS BIT(31) /* P1 address translation by pass */ - -/* Status register */ -#define M_CACTIVE BIT(0) /* m_cactive, not used */ -#define S_CACTIVE BIT(1) /* s_cactive, not used */ -#define P0_PHY_READY BIT(8) /* phy is ready */ -#define P0_CP_POD BIT(9) /* Cold PowerOn */ -#define P0_SLUMBER BIT(10) /* power mode slumber */ -#define P0_PATIAL BIT(11) /* power mode patial */ -#define P0_PHY_SIG_DET BIT(12) /* phy dignal detect */ -#define P0_PHY_CALI BIT(13) /* phy calibration done */ -#define P1_PHY_READY BIT(16) /* phy is ready */ -#define P1_CP_POD BIT(17) /* Cold PowerOn */ -#define P1_SLUMBER BIT(18) /* power mode slumber */ -#define P1_PATIAL BIT(19) /* power mode patial */ -#define P1_PHY_SIG_DET BIT(20) /* phy dignal detect */ -#define P1_PHY_CALI BIT(21) /* phy calibration done */ - -/* SATA CR_REG_TIMER bits */ -#define CR_TIME_SCALE (0x1000 << 0) - -/* SATA PHY specific registers start and end address */ -#define RXCDRCALFOSC0 0x0065 -#define CALDUTY 0x006e -#define RXDPIF 0x8065 -#define PPMDRIFTMAX_HI 0x80A4 - -#define nlm_read_sata_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_sata_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_sata_pcibase(node) \ - nlm_pcicfg_base(XLP9XX_IO_SATA_OFFSET(node)) -#define nlm_get_sata_regbase(node) \ - (nlm_get_sata_pcibase(node) + 0x100) - -/* SATA PHY config for register block 1 0x0065 .. 0x006e */ -static const u8 sata_phy_config1[] = { - 0xC9, 0xC9, 0x07, 0x07, 0x18, 0x18, 0x01, 0x01, 0x22, 0x00 -}; - -/* SATA PHY config for register block 2 0x8065 .. 0x80A4 */ -static const u8 sata_phy_config2[] = { - 0xAA, 0x00, 0x4C, 0xC9, 0xC9, 0x07, 0x07, 0x18, - 0x18, 0x05, 0x0C, 0x10, 0x00, 0x10, 0x00, 0xFF, - 0xCF, 0xF7, 0xE1, 0xF5, 0xFD, 0xFD, 0xFF, 0xFF, - 0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5, 0xFD, 0xFD, - 0xF5, 0xF5, 0xFF, 0xFF, 0xE3, 0xE7, 0xDB, 0xF5, - 0xFD, 0xFD, 0xF5, 0xF5, 0xFF, 0xFF, 0xFF, 0xF5, - 0x3F, 0x00, 0x32, 0x00, 0x03, 0x01, 0x05, 0x05, - 0x04, 0x00, 0x00, 0x08, 0x04, 0x00, 0x00, 0x04, -}; - -const int sata_phy_debug = 0; /* set to verify PHY writes */ - -static void sata_clear_glue_reg(u64 regbase, u32 off, u32 bit) -{ - u32 reg_val; - - reg_val = nlm_read_sata_reg(regbase, off); - nlm_write_sata_reg(regbase, off, (reg_val & ~bit)); -} - -static void sata_set_glue_reg(u64 regbase, u32 off, u32 bit) -{ - u32 reg_val; - - reg_val = nlm_read_sata_reg(regbase, off); - nlm_write_sata_reg(regbase, off, (reg_val | bit)); -} - -static void write_phy_reg(u64 regbase, u32 addr, u32 physel, u8 data) -{ - nlm_write_sata_reg(regbase, PHY_MEM_ACCESS, - (1u << 31) | (physel << 24) | (data << 16) | addr); - udelay(850); -} - -static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel) -{ - u32 val; - - nlm_write_sata_reg(regbase, PHY_MEM_ACCESS, - (0 << 31) | (physel << 24) | (0 << 16) | addr); - udelay(850); - val = nlm_read_sata_reg(regbase, PHY_MEM_ACCESS); - return (val >> 16) & 0xff; -} - -static void config_sata_phy(u64 regbase) -{ - u32 port, i, reg; - u8 val; - - for (port = 0; port < 2; port++) { - for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) - write_phy_reg(regbase, reg, port, sata_phy_config1[i]); - - for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) - write_phy_reg(regbase, reg, port, sata_phy_config2[i]); - - /* Fix for PHY link up failures at lower temperatures */ - write_phy_reg(regbase, 0x800F, port, 0x1f); - - val = read_phy_reg(regbase, 0x0029, port); - write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1)); - - val = read_phy_reg(regbase, 0x0056, port); - write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3)); - - val = read_phy_reg(regbase, 0x0018, port); - write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0)); - } -} - -static void check_phy_register(u64 regbase, u32 addr, u32 physel, u8 xdata) -{ - u8 data; - - data = read_phy_reg(regbase, addr, physel); - pr_info("PHY read addr = 0x%x physel = %d data = 0x%x %s\n", - addr, physel, data, data == xdata ? "TRUE" : "FALSE"); -} - -static void verify_sata_phy_config(u64 regbase) -{ - u32 port, i, reg; - - for (port = 0; port < 2; port++) { - for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) - check_phy_register(regbase, reg, port, - sata_phy_config1[i]); - - for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) - check_phy_register(regbase, reg, port, - sata_phy_config2[i]); - } -} - -static void nlm_sata_firmware_init(int node) -{ - u32 reg_val; - u64 regbase; - int n; - - pr_info("Initializing XLP9XX On-chip AHCI...\n"); - regbase = nlm_get_sata_regbase(node); - - /* Reset port0 */ - sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_POR); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_SYNTH); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDTXL); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDRXL); - sata_clear_glue_reg(regbase, SATA_CTL, P0_IPDIPDMSYNTH); - - /* port1 */ - sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_POR); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_TXRX); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_SYNTH); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDTXL); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDRXL); - sata_clear_glue_reg(regbase, SATA_CTL, P1_IPDIPDMSYNTH); - udelay(300); - - /* Set PHY */ - sata_set_glue_reg(regbase, SATA_CTL, P0_IPDTXL); - sata_set_glue_reg(regbase, SATA_CTL, P0_IPDRXL); - sata_set_glue_reg(regbase, SATA_CTL, P0_IPDIPDMSYNTH); - sata_set_glue_reg(regbase, SATA_CTL, P1_IPDTXL); - sata_set_glue_reg(regbase, SATA_CTL, P1_IPDRXL); - sata_set_glue_reg(regbase, SATA_CTL, P1_IPDIPDMSYNTH); - - udelay(1000); - sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_POR); - udelay(1000); - sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_POR); - udelay(1000); - - /* setup PHY */ - config_sata_phy(regbase); - if (sata_phy_debug) - verify_sata_phy_config(regbase); - - udelay(1000); - sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_TXRX); - sata_set_glue_reg(regbase, SATA_CTL, P0_IRST_HARD_SYNTH); - sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_TXRX); - sata_set_glue_reg(regbase, SATA_CTL, P1_IRST_HARD_SYNTH); - udelay(300); - - /* Override reset in serial PHY mode */ - sata_set_glue_reg(regbase, CR_REG_TIMER, CR_TIME_SCALE); - /* Set reset SATA */ - sata_set_glue_reg(regbase, SATA_CTL, SATA_RST_N); - sata_set_glue_reg(regbase, SATA_CTL, M_CSYSREQ); - sata_set_glue_reg(regbase, SATA_CTL, S_CSYSREQ); - - pr_debug("Waiting for PHYs to come up.\n"); - n = 10000; - do { - reg_val = nlm_read_sata_reg(regbase, SATA_STATUS); - if ((reg_val & P1_PHY_READY) && (reg_val & P0_PHY_READY)) - break; - udelay(10); - } while (--n > 0); - - if (reg_val & P0_PHY_READY) - pr_info("PHY0 is up.\n"); - else - pr_info("PHY0 is down.\n"); - if (reg_val & P1_PHY_READY) - pr_info("PHY1 is up.\n"); - else - pr_info("PHY1 is down.\n"); - - pr_info("XLP AHCI Init Done.\n"); -} - -static int __init nlm_ahci_init(void) -{ - int node; - - if (!cpu_is_xlp9xx()) - return 0; - for (node = 0; node < NLM_NR_NODES; node++) - if (nlm_node_present(node)) - nlm_sata_firmware_init(node); - return 0; -} - -static void nlm_sata_intr_ack(struct irq_data *data) -{ - u64 regbase; - u32 val; - int node; - - node = data->irq / NLM_IRQS_PER_NODE; - regbase = nlm_get_sata_regbase(node); - val = nlm_read_sata_reg(regbase, SATA_INT); - sata_set_glue_reg(regbase, SATA_INT, val); -} - -static void nlm_sata_fixup_bar(struct pci_dev *dev) -{ - dev->resource[5] = dev->resource[0]; - memset(&dev->resource[0], 0, sizeof(dev->resource[0])); -} - -static void nlm_sata_fixup_final(struct pci_dev *dev) -{ - u32 val; - u64 regbase; - int node; - - /* Find end bridge function to find node */ - node = xlp_socdev_to_node(dev); - regbase = nlm_get_sata_regbase(node); - - /* clear pending interrupts and then enable them */ - val = nlm_read_sata_reg(regbase, SATA_INT); - sata_set_glue_reg(regbase, SATA_INT, val); - - /* Enable only the core interrupt */ - sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1); - - dev->irq = nlm_irq_to_xirq(node, PIC_SATA_IRQ); - nlm_set_pic_extra_ack(node, PIC_SATA_IRQ, nlm_sata_intr_ack); -} - -arch_initcall(nlm_ahci_init); - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_SATA, - nlm_sata_fixup_bar); - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_SATA, - nlm_sata_fixup_final); diff --git a/arch/mips/netlogic/xlp/ahci-init.c b/arch/mips/netlogic/xlp/ahci-init.c deleted file mode 100644 index 92be1a3258b1..000000000000 --- a/arch/mips/netlogic/xlp/ahci-init.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2003-2014 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/dma-mapping.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/irq.h> -#include <linux/bitops.h> - -#include <asm/cpu.h> -#include <asm/mipsregs.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/mips-extns.h> - -#define SATA_CTL 0x0 -#define SATA_STATUS 0x1 /* Status Reg */ -#define SATA_INT 0x2 /* Interrupt Reg */ -#define SATA_INT_MASK 0x3 /* Interrupt Mask Reg */ -#define SATA_CR_REG_TIMER 0x4 /* PHY Conrol Timer Reg */ -#define SATA_CORE_ID 0x5 /* Core ID Reg */ -#define SATA_AXI_SLAVE_OPT1 0x6 /* AXI Slave Options Reg */ -#define SATA_PHY_LOS_LEV 0x7 /* PHY LOS Level Reg */ -#define SATA_PHY_MULTI 0x8 /* PHY Multiplier Reg */ -#define SATA_PHY_CLK_SEL 0x9 /* Clock Select Reg */ -#define SATA_PHY_AMP1_GEN1 0xa /* PHY Transmit Amplitude Reg 1 */ -#define SATA_PHY_AMP1_GEN2 0xb /* PHY Transmit Amplitude Reg 2 */ -#define SATA_PHY_AMP1_GEN3 0xc /* PHY Transmit Amplitude Reg 3 */ -#define SATA_PHY_PRE1 0xd /* PHY Transmit Preemphasis Reg 1 */ -#define SATA_PHY_PRE2 0xe /* PHY Transmit Preemphasis Reg 2 */ -#define SATA_PHY_PRE3 0xf /* PHY Transmit Preemphasis Reg 3 */ -#define SATA_SPDMODE 0x10 /* Speed Mode Reg */ -#define SATA_REFCLK 0x11 /* Reference Clock Control Reg */ -#define SATA_BYTE_SWAP_DIS 0x12 /* byte swap disable */ - -/*SATA_CTL Bits */ -#define SATA_RST_N BIT(0) -#define PHY0_RESET_N BIT(16) -#define PHY1_RESET_N BIT(17) -#define PHY2_RESET_N BIT(18) -#define PHY3_RESET_N BIT(19) -#define M_CSYSREQ BIT(2) -#define S_CSYSREQ BIT(3) - -/*SATA_STATUS Bits */ -#define P0_PHY_READY BIT(4) -#define P1_PHY_READY BIT(5) -#define P2_PHY_READY BIT(6) -#define P3_PHY_READY BIT(7) - -#define nlm_read_sata_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_sata_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_sata_pcibase(node) \ - nlm_pcicfg_base(XLP_IO_SATA_OFFSET(node)) -/* SATA device specific configuration registers are starts at 0x900 offset */ -#define nlm_get_sata_regbase(node) \ - (nlm_get_sata_pcibase(node) + 0x900) - -static void sata_clear_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit) -{ - uint32_t reg_val; - - reg_val = nlm_read_sata_reg(regbase, off); - nlm_write_sata_reg(regbase, off, (reg_val & ~bit)); -} - -static void sata_set_glue_reg(uint64_t regbase, uint32_t off, uint32_t bit) -{ - uint32_t reg_val; - - reg_val = nlm_read_sata_reg(regbase, off); - nlm_write_sata_reg(regbase, off, (reg_val | bit)); -} - -static void nlm_sata_firmware_init(int node) -{ - uint32_t reg_val; - uint64_t regbase; - int i; - - pr_info("XLP AHCI Initialization started.\n"); - regbase = nlm_get_sata_regbase(node); - - /* Reset SATA */ - sata_clear_glue_reg(regbase, SATA_CTL, SATA_RST_N); - /* Reset PHY */ - sata_clear_glue_reg(regbase, SATA_CTL, - (PHY3_RESET_N | PHY2_RESET_N - | PHY1_RESET_N | PHY0_RESET_N)); - - /* Set SATA */ - sata_set_glue_reg(regbase, SATA_CTL, SATA_RST_N); - /* Set PHY */ - sata_set_glue_reg(regbase, SATA_CTL, - (PHY3_RESET_N | PHY2_RESET_N - | PHY1_RESET_N | PHY0_RESET_N)); - - pr_debug("Waiting for PHYs to come up.\n"); - i = 0; - do { - reg_val = nlm_read_sata_reg(regbase, SATA_STATUS); - i++; - } while (((reg_val & 0xF0) != 0xF0) && (i < 10000)); - - for (i = 0; i < 4; i++) { - if (reg_val & (P0_PHY_READY << i)) - pr_info("PHY%d is up.\n", i); - else - pr_info("PHY%d is down.\n", i); - } - - pr_info("XLP AHCI init done.\n"); -} - -static int __init nlm_ahci_init(void) -{ - int node = 0; - int chip = read_c0_prid() & PRID_IMP_MASK; - - if (chip == PRID_IMP_NETLOGIC_XLP3XX) - nlm_sata_firmware_init(node); - return 0; -} - -static void nlm_sata_intr_ack(struct irq_data *data) -{ - uint32_t val = 0; - uint64_t regbase; - - regbase = nlm_get_sata_regbase(nlm_nodeid()); - val = nlm_read_sata_reg(regbase, SATA_INT); - sata_set_glue_reg(regbase, SATA_INT, val); -} - -static void nlm_sata_fixup_bar(struct pci_dev *dev) -{ - /* - * The AHCI resource is in BAR 0, move it to - * BAR 5, where it is expected - */ - dev->resource[5] = dev->resource[0]; - memset(&dev->resource[0], 0, sizeof(dev->resource[0])); -} - -static void nlm_sata_fixup_final(struct pci_dev *dev) -{ - uint32_t val; - uint64_t regbase; - int node = 0; /* XLP3XX does not support multi-node */ - - regbase = nlm_get_sata_regbase(node); - - /* clear pending interrupts and then enable them */ - val = nlm_read_sata_reg(regbase, SATA_INT); - sata_set_glue_reg(regbase, SATA_INT, val); - - /* Mask the core interrupt. If all the interrupts - * are enabled there are spurious interrupt flow - * happening, to avoid only enable core interrupt - * mask. - */ - sata_set_glue_reg(regbase, SATA_INT_MASK, 0x1); - - dev->irq = PIC_SATA_IRQ; - nlm_set_pic_extra_ack(node, PIC_SATA_IRQ, nlm_sata_intr_ack); -} - -arch_initcall(nlm_ahci_init); - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_SATA, - nlm_sata_fixup_bar); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_SATA, - nlm_sata_fixup_final); diff --git a/arch/mips/netlogic/xlp/cop2-ex.c b/arch/mips/netlogic/xlp/cop2-ex.c deleted file mode 100644 index 21e439b3db70..000000000000 --- a/arch/mips/netlogic/xlp/cop2-ex.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2013 Broadcom Corporation. - * - * based on arch/mips/cavium-octeon/cpu.c - * Copyright (C) 2009 Wind River Systems, - * written by Ralf Baechle <ralf@linux-mips.org> - */ -#include <linux/capability.h> -#include <linux/init.h> -#include <linux/irqflags.h> -#include <linux/notifier.h> -#include <linux/prefetch.h> -#include <linux/ptrace.h> -#include <linux/sched.h> -#include <linux/sched/task_stack.h> - -#include <asm/cop2.h> -#include <asm/current.h> -#include <asm/mipsregs.h> -#include <asm/page.h> - -#include <asm/netlogic/mips-extns.h> - -/* - * 64 bit ops are done in inline assembly to support 32 bit - * compilation - */ -void nlm_cop2_save(struct nlm_cop2_state *r) -{ - asm volatile( - ".set push\n" - ".set noat\n" - "dmfc2 $1, $0, 0\n" - "sd $1, 0(%1)\n" - "dmfc2 $1, $0, 1\n" - "sd $1, 8(%1)\n" - "dmfc2 $1, $0, 2\n" - "sd $1, 16(%1)\n" - "dmfc2 $1, $0, 3\n" - "sd $1, 24(%1)\n" - "dmfc2 $1, $1, 0\n" - "sd $1, 0(%2)\n" - "dmfc2 $1, $1, 1\n" - "sd $1, 8(%2)\n" - "dmfc2 $1, $1, 2\n" - "sd $1, 16(%2)\n" - "dmfc2 $1, $1, 3\n" - "sd $1, 24(%2)\n" - ".set pop\n" - : "=m"(*r) - : "r"(r->tx), "r"(r->rx)); - - r->tx_msg_status = __read_32bit_c2_register($2, 0); - r->rx_msg_status = __read_32bit_c2_register($3, 0) & 0x0fffffff; -} - -void nlm_cop2_restore(struct nlm_cop2_state *r) -{ - u32 rstat; - - asm volatile( - ".set push\n" - ".set noat\n" - "ld $1, 0(%1)\n" - "dmtc2 $1, $0, 0\n" - "ld $1, 8(%1)\n" - "dmtc2 $1, $0, 1\n" - "ld $1, 16(%1)\n" - "dmtc2 $1, $0, 2\n" - "ld $1, 24(%1)\n" - "dmtc2 $1, $0, 3\n" - "ld $1, 0(%2)\n" - "dmtc2 $1, $1, 0\n" - "ld $1, 8(%2)\n" - "dmtc2 $1, $1, 1\n" - "ld $1, 16(%2)\n" - "dmtc2 $1, $1, 2\n" - "ld $1, 24(%2)\n" - "dmtc2 $1, $1, 3\n" - ".set pop\n" - : : "m"(*r), "r"(r->tx), "r"(r->rx)); - - __write_32bit_c2_register($2, 0, r->tx_msg_status); - rstat = __read_32bit_c2_register($3, 0) & 0xf0000000u; - __write_32bit_c2_register($3, 0, r->rx_msg_status | rstat); -} - -static int nlm_cu2_call(struct notifier_block *nfb, unsigned long action, - void *data) -{ - unsigned long flags; - unsigned int status; - - switch (action) { - case CU2_EXCEPTION: - if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) - break; - local_irq_save(flags); - KSTK_STATUS(current) |= ST0_CU2; - status = read_c0_status(); - write_c0_status(status | ST0_CU2); - nlm_cop2_restore(&(current->thread.cp2)); - write_c0_status(status & ~ST0_CU2); - local_irq_restore(flags); - pr_info("COP2 access enabled for pid %d (%s)\n", - current->pid, current->comm); - return NOTIFY_BAD; /* Don't call default notifier */ - } - - return NOTIFY_OK; /* Let default notifier send signals */ -} - -static int __init nlm_cu2_setup(void) -{ - return cu2_notifier(nlm_cu2_call, 0); -} -early_initcall(nlm_cu2_setup); diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c deleted file mode 100644 index c856f2a3ea42..000000000000 --- a/arch/mips/netlogic/xlp/dt.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2003-2013 Broadcom Corporation. - * All Rights Reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/memblock.h> - -#include <linux/of_fdt.h> -#include <linux/of_platform.h> -#include <linux/of_device.h> - -#include <asm/prom.h> - -extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_xlp_fvp_begin[], - __dtb_xlp_gvp_begin[], __dtb_xlp_rvp_begin[]; -static void *xlp_fdt_blob; - -void __init *xlp_dt_init(void *fdtp) -{ - if (!fdtp) { - switch (current_cpu_data.processor_id & PRID_IMP_MASK) { -#ifdef CONFIG_DT_XLP_RVP - case PRID_IMP_NETLOGIC_XLP5XX: - fdtp = __dtb_xlp_rvp_begin; - break; -#endif -#ifdef CONFIG_DT_XLP_GVP - case PRID_IMP_NETLOGIC_XLP9XX: - fdtp = __dtb_xlp_gvp_begin; - break; -#endif -#ifdef CONFIG_DT_XLP_FVP - case PRID_IMP_NETLOGIC_XLP2XX: - fdtp = __dtb_xlp_fvp_begin; - break; -#endif -#ifdef CONFIG_DT_XLP_SVP - case PRID_IMP_NETLOGIC_XLP3XX: - fdtp = __dtb_xlp_svp_begin; - break; -#endif -#ifdef CONFIG_DT_XLP_EVP - case PRID_IMP_NETLOGIC_XLP8XX: - fdtp = __dtb_xlp_evp_begin; - break; -#endif - default: - /* Pick a built-in if any, and hope for the best */ - fdtp = __dtb_start; - break; - } - } - xlp_fdt_blob = fdtp; - return fdtp; -} - -void __init xlp_early_init_devtree(void) -{ - __dt_setup_arch(xlp_fdt_blob); -} - -void __init device_tree_init(void) -{ - unflatten_and_copy_device_tree(); -} diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c deleted file mode 100644 index 25ee69489e5e..000000000000 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/mm.h> -#include <linux/delay.h> - -#include <asm/mipsregs.h> -#include <asm/time.h> - -#include <asm/netlogic/common.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/bridge.h> -#include <asm/netlogic/xlp-hal/pic.h> -#include <asm/netlogic/xlp-hal/sys.h> - -/* Main initialization */ -void nlm_node_init(int node) -{ - struct nlm_soc_info *nodep; - - nodep = nlm_get_node(node); - if (node == 0) - nodep->coremask = 1; /* node 0, boot cpu */ - nodep->sysbase = nlm_get_sys_regbase(node); - nodep->picbase = nlm_get_pic_regbase(node); - nodep->ebase = read_c0_ebase() & MIPS_EBASE_BASE; - if (cpu_is_xlp9xx()) - nodep->socbus = xlp9xx_get_socbus(node); - else - nodep->socbus = 0; - spin_lock_init(&nodep->piclock); -} - -static int xlp9xx_irq_to_irt(int irq) -{ - switch (irq) { - case PIC_GPIO_IRQ: - return 12; - case PIC_I2C_0_IRQ: - return 125; - case PIC_I2C_1_IRQ: - return 126; - case PIC_I2C_2_IRQ: - return 127; - case PIC_I2C_3_IRQ: - return 128; - case PIC_9XX_XHCI_0_IRQ: - return 114; - case PIC_9XX_XHCI_1_IRQ: - return 115; - case PIC_9XX_XHCI_2_IRQ: - return 116; - case PIC_UART_0_IRQ: - return 133; - case PIC_UART_1_IRQ: - return 134; - case PIC_SATA_IRQ: - return 143; - case PIC_NAND_IRQ: - return 151; - case PIC_SPI_IRQ: - return 152; - case PIC_MMC_IRQ: - return 153; - case PIC_PCIE_LINK_LEGACY_IRQ(0): - case PIC_PCIE_LINK_LEGACY_IRQ(1): - case PIC_PCIE_LINK_LEGACY_IRQ(2): - case PIC_PCIE_LINK_LEGACY_IRQ(3): - return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE; - } - return -1; -} - -static int xlp_irq_to_irt(int irq) -{ - uint64_t pcibase; - int devoff, irt; - - devoff = 0; - switch (irq) { - case PIC_UART_0_IRQ: - devoff = XLP_IO_UART0_OFFSET(0); - break; - case PIC_UART_1_IRQ: - devoff = XLP_IO_UART1_OFFSET(0); - break; - case PIC_MMC_IRQ: - devoff = XLP_IO_MMC_OFFSET(0); - break; - case PIC_I2C_0_IRQ: /* I2C will be fixed up */ - case PIC_I2C_1_IRQ: - case PIC_I2C_2_IRQ: - case PIC_I2C_3_IRQ: - if (cpu_is_xlpii()) - devoff = XLP2XX_IO_I2C_OFFSET(0); - else - devoff = XLP_IO_I2C0_OFFSET(0); - break; - case PIC_SATA_IRQ: - devoff = XLP_IO_SATA_OFFSET(0); - break; - case PIC_GPIO_IRQ: - devoff = XLP_IO_GPIO_OFFSET(0); - break; - case PIC_NAND_IRQ: - devoff = XLP_IO_NAND_OFFSET(0); - break; - case PIC_SPI_IRQ: - devoff = XLP_IO_SPI_OFFSET(0); - break; - default: - if (cpu_is_xlpii()) { - switch (irq) { - /* XLP2XX has three XHCI USB controller */ - case PIC_2XX_XHCI_0_IRQ: - devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0); - break; - case PIC_2XX_XHCI_1_IRQ: - devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0); - break; - case PIC_2XX_XHCI_2_IRQ: - devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0); - break; - } - } else { - switch (irq) { - case PIC_EHCI_0_IRQ: - devoff = XLP_IO_USB_EHCI0_OFFSET(0); - break; - case PIC_EHCI_1_IRQ: - devoff = XLP_IO_USB_EHCI1_OFFSET(0); - break; - case PIC_OHCI_0_IRQ: - devoff = XLP_IO_USB_OHCI0_OFFSET(0); - break; - case PIC_OHCI_1_IRQ: - devoff = XLP_IO_USB_OHCI1_OFFSET(0); - break; - case PIC_OHCI_2_IRQ: - devoff = XLP_IO_USB_OHCI2_OFFSET(0); - break; - case PIC_OHCI_3_IRQ: - devoff = XLP_IO_USB_OHCI3_OFFSET(0); - break; - } - } - } - - if (devoff != 0) { - uint32_t val; - - pcibase = nlm_pcicfg_base(devoff); - val = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG); - if (val == 0xffffffff) { - irt = -1; - } else { - irt = val & 0xffff; - /* HW weirdness, I2C IRT entry has to be fixed up */ - switch (irq) { - case PIC_I2C_1_IRQ: - irt = irt + 1; break; - case PIC_I2C_2_IRQ: - irt = irt + 2; break; - case PIC_I2C_3_IRQ: - irt = irt + 3; break; - } - } - } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) && - irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) { - /* HW bug, PCI IRT entries are bad on early silicon, fix */ - irt = PIC_IRT_PCIE_LINK_INDEX(irq - - PIC_PCIE_LINK_LEGACY_IRQ_BASE); - } else { - irt = -1; - } - return irt; -} - -int nlm_irq_to_irt(int irq) -{ - /* return -2 for irqs without 1-1 mapping */ - if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) && irq <= PIC_PCIE_LINK_MSI_IRQ(3)) - return -2; - if (irq >= PIC_PCIE_MSIX_IRQ(0) && irq <= PIC_PCIE_MSIX_IRQ(3)) - return -2; - - if (cpu_is_xlp9xx()) - return xlp9xx_irq_to_irt(irq); - else - return xlp_irq_to_irt(irq); -} - -static unsigned int nlm_xlp2_get_core_frequency(int node, int core) -{ - unsigned int pll_post_div, ctrl_val0, ctrl_val1, denom; - uint64_t num, sysbase, clockbase; - - if (cpu_is_xlp9xx()) { - clockbase = nlm_get_clock_regbase(node); - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_CPU_PLL_CTRL0(core)); - ctrl_val1 = nlm_read_sys_reg(clockbase, - SYS_9XX_CPU_PLL_CTRL1(core)); - } else { - sysbase = nlm_get_node(node)->sysbase; - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_CPU_PLL_CTRL0(core)); - ctrl_val1 = nlm_read_sys_reg(sysbase, - SYS_CPU_PLL_CTRL1(core)); - } - - /* Find PLL post divider value */ - switch ((ctrl_val0 >> 24) & 0x7) { - case 1: - pll_post_div = 2; - break; - case 3: - pll_post_div = 4; - break; - case 7: - pll_post_div = 8; - break; - case 6: - pll_post_div = 16; - break; - case 0: - default: - pll_post_div = 1; - break; - } - - num = 1000000ULL * (400 * 3 + 100 * (ctrl_val1 & 0x3f)); - denom = 3 * pll_post_div; - do_div(num, denom); - - return (unsigned int)num; -} - -static unsigned int nlm_xlp_get_core_frequency(int node, int core) -{ - unsigned int pll_divf, pll_divr, dfs_div, ext_div; - unsigned int rstval, dfsval, denom; - uint64_t num, sysbase; - - sysbase = nlm_get_node(node)->sysbase; - rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG); - dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE); - pll_divf = ((rstval >> 10) & 0x7f) + 1; - pll_divr = ((rstval >> 8) & 0x3) + 1; - ext_div = ((rstval >> 30) & 0x3) + 1; - dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1; - - num = 800000000ULL * pll_divf; - denom = 3 * pll_divr * ext_div * dfs_div; - do_div(num, denom); - - return (unsigned int)num; -} - -unsigned int nlm_get_core_frequency(int node, int core) -{ - if (cpu_is_xlpii()) - return nlm_xlp2_get_core_frequency(node, core); - else - return nlm_xlp_get_core_frequency(node, core); -} - -/* - * Calculate PIC frequency from PLL registers. - * freq_out = (ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13) / - * ((2^ctrl0[7:5]) * Table(ctrl0[26:24])) - */ -static unsigned int nlm_xlp2_get_pic_frequency(int node) -{ - u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div, cpu_xlp9xx; - u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div; - u64 sysbase, pll_out_freq_num, ref_clk_select, clockbase, ref_clk; - - sysbase = nlm_get_node(node)->sysbase; - clockbase = nlm_get_clock_regbase(node); - cpu_xlp9xx = cpu_is_xlp9xx(); - - /* Find ref_clk_base */ - if (cpu_xlp9xx) - ref_clk_select = (nlm_read_sys_reg(sysbase, - SYS_9XX_POWER_ON_RESET_CFG) >> 18) & 0x3; - else - ref_clk_select = (nlm_read_sys_reg(sysbase, - SYS_POWER_ON_RESET_CFG) >> 18) & 0x3; - switch (ref_clk_select) { - case 0: - ref_clk = 200000000ULL; - ref_div = 3; - break; - case 1: - ref_clk = 100000000ULL; - ref_div = 1; - break; - case 2: - ref_clk = 125000000ULL; - ref_div = 1; - break; - case 3: - ref_clk = 400000000ULL; - ref_div = 3; - break; - } - - /* Find the clock source PLL device for PIC */ - if (cpu_xlp9xx) { - reg_select = nlm_read_sys_reg(clockbase, - SYS_9XX_CLK_DEV_SEL_REG) & 0x3; - switch (reg_select) { - case 0: - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL0); - ctrl_val2 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL2); - break; - case 1: - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL0_DEVX(0)); - ctrl_val2 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL2_DEVX(0)); - break; - case 2: - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL0_DEVX(1)); - ctrl_val2 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL2_DEVX(1)); - break; - case 3: - ctrl_val0 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL0_DEVX(2)); - ctrl_val2 = nlm_read_sys_reg(clockbase, - SYS_9XX_PLL_CTRL2_DEVX(2)); - break; - } - } else { - reg_select = (nlm_read_sys_reg(sysbase, - SYS_CLK_DEV_SEL_REG) >> 22) & 0x3; - switch (reg_select) { - case 0: - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL0); - ctrl_val2 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL2); - break; - case 1: - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL0_DEVX(0)); - ctrl_val2 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL2_DEVX(0)); - break; - case 2: - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL0_DEVX(1)); - ctrl_val2 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL2_DEVX(1)); - break; - case 3: - ctrl_val0 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL0_DEVX(2)); - ctrl_val2 = nlm_read_sys_reg(sysbase, - SYS_PLL_CTRL2_DEVX(2)); - break; - } - } - - vco_post_div = (ctrl_val0 >> 5) & 0x7; - pll_post_div = (ctrl_val0 >> 24) & 0x7; - mdiv = ctrl_val2 & 0xff; - fdiv = (ctrl_val2 >> 8) & 0x1fff; - - /* Find PLL post divider value */ - switch (pll_post_div) { - case 1: - pll_post_div = 2; - break; - case 3: - pll_post_div = 4; - break; - case 7: - pll_post_div = 8; - break; - case 6: - pll_post_div = 16; - break; - case 0: - default: - pll_post_div = 1; - break; - } - - fdiv = fdiv/(1 << 13); - pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv; - pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div; - - if (pll_out_freq_den > 0) - do_div(pll_out_freq_num, pll_out_freq_den); - - /* PIC post divider, which happens after PLL */ - if (cpu_xlp9xx) - pic_div = nlm_read_sys_reg(clockbase, - SYS_9XX_CLK_DEV_DIV_REG) & 0x3; - else - pic_div = (nlm_read_sys_reg(sysbase, - SYS_CLK_DEV_DIV_REG) >> 22) & 0x3; - do_div(pll_out_freq_num, 1 << pic_div); - - return pll_out_freq_num; -} - -unsigned int nlm_get_pic_frequency(int node) -{ - if (cpu_is_xlpii()) - return nlm_xlp2_get_pic_frequency(node); - else - return 133333333; -} - -unsigned int nlm_get_cpu_frequency(void) -{ - return nlm_get_core_frequency(0, 0); -} - -/* - * Fills upto 8 pairs of entries containing the DRAM map of a node - * if node < 0, get dram map for all nodes - */ -int nlm_get_dram_map(int node, uint64_t *dram_map, int nentries) -{ - uint64_t bridgebase, base, lim; - uint32_t val; - unsigned int barreg, limreg, xlatreg; - int i, n, rv; - - /* Look only at mapping on Node 0, we don't handle crazy configs */ - bridgebase = nlm_get_bridge_regbase(0); - rv = 0; - for (i = 0; i < 8; i++) { - if (rv + 1 >= nentries) - break; - if (cpu_is_xlp9xx()) { - barreg = BRIDGE_9XX_DRAM_BAR(i); - limreg = BRIDGE_9XX_DRAM_LIMIT(i); - xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i); - } else { - barreg = BRIDGE_DRAM_BAR(i); - limreg = BRIDGE_DRAM_LIMIT(i); - xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i); - } - if (node >= 0) { - /* node specified, get node mapping of BAR */ - val = nlm_read_bridge_reg(bridgebase, xlatreg); - n = (val >> 1) & 0x3; - if (n != node) - continue; - } - val = nlm_read_bridge_reg(bridgebase, barreg); - val = (val >> 12) & 0xfffff; - base = (uint64_t) val << 20; - val = nlm_read_bridge_reg(bridgebase, limreg); - val = (val >> 12) & 0xfffff; - if (val == 0) /* BAR not used */ - continue; - lim = ((uint64_t)val + 1) << 20; - dram_map[rv] = base; - dram_map[rv + 1] = lim; - rv += 2; - } - return rv; -} diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c deleted file mode 100644 index 9fbaa1e5b340..000000000000 --- a/arch/mips/netlogic/xlp/setup.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/of_fdt.h> -#include <linux/memblock.h> - -#include <asm/idle.h> -#include <asm/reboot.h> -#include <asm/time.h> -#include <asm/bootinfo.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/sys.h> - -uint64_t nlm_io_base; -struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; -cpumask_t nlm_cpumask = CPU_MASK_CPU0; -unsigned int nlm_threads_per_core; - -static void nlm_linux_exit(void) -{ - uint64_t sysbase = nlm_get_node(0)->sysbase; - - if (cpu_is_xlp9xx()) - nlm_write_sys_reg(sysbase, SYS_9XX_CHIP_RESET, 1); - else - nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1); - for ( ; ; ) - cpu_wait(); -} - -static void nlm_fixup_mem(void) -{ - const int pref_backup = 512; - struct memblock_region *mem; - - for_each_mem_region(mem) { - memblock_remove(mem->base + mem->size - pref_backup, - pref_backup); - } -} - -static void __init xlp_init_mem_from_bars(void) -{ - uint64_t map[16]; - int i, n; - - n = nlm_get_dram_map(-1, map, ARRAY_SIZE(map)); /* -1 : all nodes */ - for (i = 0; i < n; i += 2) { - /* exclude 0x1000_0000-0x2000_0000, u-boot device */ - if (map[i] <= 0x10000000 && map[i+1] > 0x10000000) - map[i+1] = 0x10000000; - if (map[i] > 0x10000000 && map[i] < 0x20000000) - map[i] = 0x20000000; - - memblock_add(map[i], map[i+1] - map[i]); - } -} - -void __init plat_mem_setup(void) -{ -#ifdef CONFIG_SMP - nlm_wakeup_secondary_cpus(); - - /* update TLB size after waking up threads */ - current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; - - register_smp_ops(&nlm_smp_ops); -#endif - _machine_restart = (void (*)(char *))nlm_linux_exit; - _machine_halt = nlm_linux_exit; - pm_power_off = nlm_linux_exit; - - /* memory and bootargs from DT */ - xlp_early_init_devtree(); - - if (memblock_end_of_DRAM() == 0) { - pr_info("Using DRAM BARs for memory map.\n"); - xlp_init_mem_from_bars(); - } - /* Calculate and setup wired entries for mapped kernel */ - nlm_fixup_mem(); -} - -const char *get_system_type(void) -{ - switch (read_c0_prid() & PRID_IMP_MASK) { - case PRID_IMP_NETLOGIC_XLP9XX: - case PRID_IMP_NETLOGIC_XLP5XX: - case PRID_IMP_NETLOGIC_XLP2XX: - return "Broadcom XLPII Series"; - default: - return "Netlogic XLP Series"; - } -} - -void xlp_mmu_init(void) -{ - u32 conf4; - - if (cpu_is_xlpii()) { - /* XLPII series has extended pagesize in config 4 */ - conf4 = read_c0_config4() & ~0x1f00u; - write_c0_config4(conf4 | ((PAGE_SHIFT - 10) / 2 << 8)); - } else { - /* enable extended TLB and Large Fixed TLB */ - write_c0_config6(read_c0_config6() | 0x24); - - /* set page mask of extended Fixed TLB in config7 */ - write_c0_config7(PM_DEFAULT_MASK >> - (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); - } -} - -void nlm_percpu_init(int hwcpuid) -{ -} - -void __init prom_init(void) -{ - void *reset_vec; - - nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); - nlm_init_boot_cpu(); - xlp_mmu_init(); - nlm_node_init(0); - xlp_dt_init((void *)(long)fw_arg0); - - /* Update reset entry point with CPU init code */ - reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); - memset(reset_vec, 0, RESET_VEC_SIZE); - memcpy(reset_vec, (void *)nlm_reset_entry, - (nlm_reset_entry_end - nlm_reset_entry)); - -#ifdef CONFIG_SMP - cpumask_setall(&nlm_cpumask); -#endif -} diff --git a/arch/mips/netlogic/xlp/usb-init-xlp2.c b/arch/mips/netlogic/xlp/usb-init-xlp2.c deleted file mode 100644 index 2524939a5e3a..000000000000 --- a/arch/mips/netlogic/xlp/usb-init-xlp2.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (c) 2003-2013 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/dma-mapping.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/pci_ids.h> -#include <linux/platform_device.h> -#include <linux/irq.h> - -#include <asm/netlogic/common.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> - -#define XLPII_USB3_CTL_0 0xc0 -#define XLPII_VAUXRST BIT(0) -#define XLPII_VCCRST BIT(1) -#define XLPII_NUM2PORT 9 -#define XLPII_NUM3PORT 13 -#define XLPII_RTUNEREQ BIT(20) -#define XLPII_MS_CSYSREQ BIT(21) -#define XLPII_XS_CSYSREQ BIT(22) -#define XLPII_RETENABLEN BIT(23) -#define XLPII_TX2RX BIT(24) -#define XLPII_XHCIREV BIT(25) -#define XLPII_ECCDIS BIT(26) - -#define XLPII_USB3_INT_REG 0xc2 -#define XLPII_USB3_INT_MASK 0xc3 - -#define XLPII_USB_PHY_TEST 0xc6 -#define XLPII_PRESET BIT(0) -#define XLPII_ATERESET BIT(1) -#define XLPII_LOOPEN BIT(2) -#define XLPII_TESTPDHSP BIT(3) -#define XLPII_TESTPDSSP BIT(4) -#define XLPII_TESTBURNIN BIT(5) - -#define XLPII_USB_PHY_LOS_LV 0xc9 -#define XLPII_LOSLEV 0 -#define XLPII_LOSBIAS 5 -#define XLPII_SQRXTX 8 -#define XLPII_TXBOOST 11 -#define XLPII_RSLKSEL 16 -#define XLPII_FSEL 20 - -#define XLPII_USB_RFCLK_REG 0xcc -#define XLPII_VVLD 30 - -#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) - -#define nlm_xlpii_get_usb_pcibase(node, inst) \ - nlm_pcicfg_base(cpu_is_xlp9xx() ? \ - XLP9XX_IO_USB_OFFSET(node, inst) : \ - XLP2XX_IO_USB_OFFSET(node, inst)) -#define nlm_xlpii_get_usb_regbase(node, inst) \ - (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) - -static void xlp2xx_usb_ack(struct irq_data *data) -{ - u64 port_addr; - - switch (data->irq) { - case PIC_2XX_XHCI_0_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(0, 1); - break; - case PIC_2XX_XHCI_1_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(0, 2); - break; - case PIC_2XX_XHCI_2_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(0, 3); - break; - default: - pr_err("No matching USB irq!\n"); - return; - } - nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); -} - -static void xlp9xx_usb_ack(struct irq_data *data) -{ - u64 port_addr; - int node, irq; - - /* Find the node and irq on the node */ - irq = data->irq % NLM_IRQS_PER_NODE; - node = data->irq / NLM_IRQS_PER_NODE; - - switch (irq) { - case PIC_9XX_XHCI_0_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(node, 1); - break; - case PIC_9XX_XHCI_1_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(node, 2); - break; - case PIC_9XX_XHCI_2_IRQ: - port_addr = nlm_xlpii_get_usb_regbase(node, 3); - break; - default: - pr_err("No matching USB irq %d node %d!\n", irq, node); - return; - } - nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); -} - -static void nlm_xlpii_usb_hw_reset(int node, int port) -{ - u64 port_addr, xhci_base, pci_base; - void __iomem *corebase; - u32 val; - - port_addr = nlm_xlpii_get_usb_regbase(node, port); - - /* Set frequency */ - val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV); - val &= ~(0x3f << XLPII_FSEL); - val |= (0x27 << XLPII_FSEL); - nlm_write_usb_reg(port_addr, XLPII_USB_PHY_LOS_LV, val); - - val = nlm_read_usb_reg(port_addr, XLPII_USB_RFCLK_REG); - val |= (1 << XLPII_VVLD); - nlm_write_usb_reg(port_addr, XLPII_USB_RFCLK_REG, val); - - /* PHY reset */ - val = nlm_read_usb_reg(port_addr, XLPII_USB_PHY_TEST); - val &= (XLPII_ATERESET | XLPII_LOOPEN | XLPII_TESTPDHSP - | XLPII_TESTPDSSP | XLPII_TESTBURNIN); - nlm_write_usb_reg(port_addr, XLPII_USB_PHY_TEST, val); - - /* Setup control register */ - val = XLPII_VAUXRST | XLPII_VCCRST | (1 << XLPII_NUM2PORT) - | (1 << XLPII_NUM3PORT) | XLPII_MS_CSYSREQ | XLPII_XS_CSYSREQ - | XLPII_RETENABLEN | XLPII_XHCIREV; - nlm_write_usb_reg(port_addr, XLPII_USB3_CTL_0, val); - - /* Enable interrupts */ - nlm_write_usb_reg(port_addr, XLPII_USB3_INT_MASK, 0x00000001); - - /* Clear all interrupts */ - nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); - - udelay(2000); - - /* XHCI configuration at PCI mem */ - pci_base = nlm_xlpii_get_usb_pcibase(node, port); - xhci_base = nlm_read_usb_reg(pci_base, 0x4) & ~0xf; - corebase = ioremap(xhci_base, 0x10000); - if (!corebase) - return; - - writel(0x240002, corebase + 0xc2c0); - /* GCTL 0xc110 */ - val = readl(corebase + 0xc110); - val &= ~(0x3 << 12); - val |= (1 << 12); - writel(val, corebase + 0xc110); - udelay(100); - - /* PHYCFG 0xc200 */ - val = readl(corebase + 0xc200); - val &= ~(1 << 6); - writel(val, corebase + 0xc200); - udelay(100); - - /* PIPECTL 0xc2c0 */ - val = readl(corebase + 0xc2c0); - val &= ~(1 << 17); - writel(val, corebase + 0xc2c0); - - iounmap(corebase); -} - -static int __init nlm_platform_xlpii_usb_init(void) -{ - int node; - - if (!cpu_is_xlpii()) - return 0; - - if (!cpu_is_xlp9xx()) { - /* XLP 2XX single node */ - pr_info("Initializing 2XX USB Interface\n"); - nlm_xlpii_usb_hw_reset(0, 1); - nlm_xlpii_usb_hw_reset(0, 2); - nlm_xlpii_usb_hw_reset(0, 3); - nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlp2xx_usb_ack); - nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlp2xx_usb_ack); - nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlp2xx_usb_ack); - return 0; - } - - /* XLP 9XX, multi-node */ - pr_info("Initializing 9XX/5XX USB Interface\n"); - for (node = 0; node < NLM_NR_NODES; node++) { - if (!nlm_node_present(node)) - continue; - nlm_xlpii_usb_hw_reset(node, 1); - nlm_xlpii_usb_hw_reset(node, 2); - nlm_xlpii_usb_hw_reset(node, 3); - nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack); - nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack); - nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_2_IRQ, xlp9xx_usb_ack); - } - return 0; -} - -arch_initcall(nlm_platform_xlpii_usb_init); - -static u64 xlp_usb_dmamask = ~(u32)0; - -/* Fixup the IRQ for USB devices which is exist on XLP9XX SOC PCIE bus */ -static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev) -{ - int node; - - node = xlp_socdev_to_node(dev); - dev->dev.dma_mask = &xlp_usb_dmamask; - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - switch (dev->devfn) { - case 0x21: - dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_0_IRQ); - break; - case 0x22: - dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ); - break; - case 0x23: - dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_2_IRQ); - break; - } -} - -/* Fixup the IRQ for USB devices which is exist on XLP2XX SOC PCIE bus */ -static void nlm_xlp2xx_usb_fixup_final(struct pci_dev *dev) -{ - dev->dev.dma_mask = &xlp_usb_dmamask; - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - switch (dev->devfn) { - case 0x21: - dev->irq = PIC_2XX_XHCI_0_IRQ; - break; - case 0x22: - dev->irq = PIC_2XX_XHCI_1_IRQ; - break; - case 0x23: - dev->irq = PIC_2XX_XHCI_2_IRQ; - break; - } -} - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_XHCI, - nlm_xlp9xx_usb_fixup_final); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI, - nlm_xlp2xx_usb_fixup_final); diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c deleted file mode 100644 index f8117985f0f8..000000000000 --- a/arch/mips/netlogic/xlp/usb-init.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/dma-mapping.h> -#include <linux/kernel.h> -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/platform_device.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> - -/* - * USB glue logic registers, used only during initialization - */ -#define USB_CTL_0 0x01 -#define USB_PHY_0 0x0A -#define USB_PHY_RESET 0x01 -#define USB_PHY_PORT_RESET_0 0x10 -#define USB_PHY_PORT_RESET_1 0x20 -#define USB_CONTROLLER_RESET 0x01 -#define USB_INT_STATUS 0x0E -#define USB_INT_EN 0x0F -#define USB_PHY_INTERRUPT_EN 0x01 -#define USB_OHCI_INTERRUPT_EN 0x02 -#define USB_OHCI_INTERRUPT1_EN 0x04 -#define USB_OHCI_INTERRUPT2_EN 0x08 -#define USB_CTRL_INTERRUPT_EN 0x10 - -#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) -#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) -#define nlm_get_usb_pcibase(node, inst) \ - nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst)) -#define nlm_get_usb_regbase(node, inst) \ - (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) - -static void nlm_usb_intr_en(int node, int port) -{ - uint32_t val; - uint64_t port_addr; - - port_addr = nlm_get_usb_regbase(node, port); - val = nlm_read_usb_reg(port_addr, USB_INT_EN); - val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN | - USB_OHCI_INTERRUPT1_EN | USB_OHCI_INTERRUPT2_EN; - nlm_write_usb_reg(port_addr, USB_INT_EN, val); -} - -static void nlm_usb_hw_reset(int node, int port) -{ - uint64_t port_addr; - uint32_t val; - - /* reset USB phy */ - port_addr = nlm_get_usb_regbase(node, port); - val = nlm_read_usb_reg(port_addr, USB_PHY_0); - val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1); - nlm_write_usb_reg(port_addr, USB_PHY_0, val); - - mdelay(100); - val = nlm_read_usb_reg(port_addr, USB_CTL_0); - val &= ~(USB_CONTROLLER_RESET); - val |= 0x4; - nlm_write_usb_reg(port_addr, USB_CTL_0, val); -} - -static int __init nlm_platform_usb_init(void) -{ - if (cpu_is_xlpii()) - return 0; - - pr_info("Initializing USB Interface\n"); - nlm_usb_hw_reset(0, 0); - nlm_usb_hw_reset(0, 3); - - /* Enable PHY interrupts */ - nlm_usb_intr_en(0, 0); - nlm_usb_intr_en(0, 3); - - return 0; -} - -arch_initcall(nlm_platform_usb_init); - -static u64 xlp_usb_dmamask = ~(u32)0; - -/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */ -static void nlm_usb_fixup_final(struct pci_dev *dev) -{ - dev->dev.dma_mask = &xlp_usb_dmamask; - dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - switch (dev->devfn) { - case 0x10: - dev->irq = PIC_EHCI_0_IRQ; - break; - case 0x11: - dev->irq = PIC_OHCI_0_IRQ; - break; - case 0x12: - dev->irq = PIC_OHCI_1_IRQ; - break; - case 0x13: - dev->irq = PIC_EHCI_1_IRQ; - break; - case 0x14: - dev->irq = PIC_OHCI_2_IRQ; - break; - case 0x15: - dev->irq = PIC_OHCI_3_IRQ; - break; - } -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI, - nlm_usb_fixup_final); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI, - nlm_usb_fixup_final); diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c deleted file mode 100644 index d61004dd71b4..000000000000 --- a/arch/mips/netlogic/xlp/wakeup.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/threads.h> - -#include <asm/asm.h> -#include <asm/asm-offsets.h> -#include <asm/mipsregs.h> -#include <asm/addrspace.h> -#include <asm/string.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/mips-extns.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/pic.h> -#include <asm/netlogic/xlp-hal/sys.h> - -static int xlp_wakeup_core(uint64_t sysbase, int node, int core) -{ - uint32_t coremask, value; - int count, resetreg; - - coremask = (1 << core); - - /* Enable CPU clock in case of 8xx/3xx */ - if (!cpu_is_xlpii()) { - value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL); - value &= ~coremask; - nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value); - } - - /* On 9XX, mark coherent first */ - if (cpu_is_xlp9xx()) { - value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE); - value &= ~coremask; - nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value); - } - - /* Remove CPU Reset */ - resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET; - value = nlm_read_sys_reg(sysbase, resetreg); - value &= ~coremask; - nlm_write_sys_reg(sysbase, resetreg, value); - - /* We are done on 9XX */ - if (cpu_is_xlp9xx()) - return 1; - - /* Poll for CPU to mark itself coherent on other type of XLP */ - count = 100000; - do { - value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE); - } while ((value & coremask) != 0 && --count > 0); - - return count != 0; -} - -static int wait_for_cpus(int cpu, int bootcpu) -{ - volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); - int i, count, notready; - - count = 0x800000; - do { - notready = nlm_threads_per_core; - for (i = 0; i < nlm_threads_per_core; i++) - if (cpu_ready[cpu + i] || (cpu + i) == bootcpu) - --notready; - } while (notready != 0 && --count > 0); - - return count != 0; -} - -static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) -{ - struct nlm_soc_info *nodep; - uint64_t syspcibase, fusebase; - uint32_t syscoremask, mask, fusemask; - int core, n, cpu, ncores; - - for (n = 0; n < NLM_NR_NODES; n++) { - if (n != 0) { - /* check if node exists and is online */ - if (cpu_is_xlp9xx()) { - int b = xlp9xx_get_socbus(n); - pr_info("Node %d SoC PCI bus %d.\n", n, b); - if (b == 0) - break; - } else { - syspcibase = nlm_get_sys_pcibase(n); - if (nlm_read_reg(syspcibase, 0) == 0xffffffff) - break; - } - nlm_node_init(n); - } - - /* read cores in reset from SYS */ - nodep = nlm_get_node(n); - - if (cpu_is_xlp9xx()) { - fusebase = nlm_get_fuse_regbase(n); - fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6); - switch (read_c0_prid() & PRID_IMP_MASK) { - case PRID_IMP_NETLOGIC_XLP5XX: - mask = 0xff; - break; - case PRID_IMP_NETLOGIC_XLP9XX: - default: - mask = 0xfffff; - break; - } - } else { - fusemask = nlm_read_sys_reg(nodep->sysbase, - SYS_EFUSE_DEVICE_CFG_STATUS0); - switch (read_c0_prid() & PRID_IMP_MASK) { - case PRID_IMP_NETLOGIC_XLP3XX: - mask = 0xf; - break; - case PRID_IMP_NETLOGIC_XLP2XX: - mask = 0x3; - break; - case PRID_IMP_NETLOGIC_XLP8XX: - default: - mask = 0xff; - break; - } - } - - /* - * Fused out cores are set in the fusemask, and the remaining - * cores are renumbered to range 0 .. nactive-1 - */ - syscoremask = (1 << hweight32(~fusemask & mask)) - 1; - - pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask); - ncores = nlm_cores_per_node(); - for (core = 0; core < ncores; core++) { - /* we will be on node 0 core 0 */ - if (n == 0 && core == 0) - continue; - - /* see if the core exists */ - if ((syscoremask & (1 << core)) == 0) - continue; - - /* see if at least the first hw thread is enabled */ - cpu = (n * ncores + core) * NLM_THREADS_PER_CORE; - if (!cpumask_test_cpu(cpu, wakeup_mask)) - continue; - - /* wake up the core */ - if (!xlp_wakeup_core(nodep->sysbase, n, core)) - continue; - - /* core is up */ - nodep->coremask |= 1u << core; - - /* spin until the hw threads sets their ready */ - if (!wait_for_cpus(cpu, 0)) - pr_err("Node %d : timeout core %d\n", n, core); - } - } -} - -void xlp_wakeup_secondary_cpus(void) -{ - /* - * In case of u-boot, the secondaries are in reset - * first wakeup core 0 threads - */ - xlp_boot_core0_siblings(); - if (!wait_for_cpus(0, 0)) - pr_err("Node 0 : timeout core 0\n"); - - /* now get other cores out of reset */ - xlp_enable_secondary_cores(&nlm_cpumask); -} diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile deleted file mode 100644 index 7c83100e5722..000000000000 --- a/arch/mips/netlogic/xlr/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y += fmn.o fmn-config.o setup.o platform.o platform-flash.o -obj-$(CONFIG_SMP) += wakeup.o diff --git a/arch/mips/netlogic/xlr/fmn-config.c b/arch/mips/netlogic/xlr/fmn-config.c deleted file mode 100644 index 15483537e8cf..000000000000 --- a/arch/mips/netlogic/xlr/fmn-config.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <asm/cpu-info.h> -#include <linux/irq.h> -#include <linux/interrupt.h> - -#include <asm/cpu.h> -#include <asm/mipsregs.h> -#include <asm/netlogic/xlr/fmn.h> -#include <asm/netlogic/xlr/xlr.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/haldefs.h> - -struct xlr_board_fmn_config xlr_board_fmn_config; - -static void __maybe_unused print_credit_config(struct xlr_fmn_info *fmn_info) -{ - int bkt; - - pr_info("Bucket size :\n"); - pr_info("Station\t: Size\n"); - for (bkt = 0; bkt < 16; bkt++) - pr_info(" %d %d %d %d %d %d %d %d\n", - xlr_board_fmn_config.bucket_size[(bkt * 8) + 0], - xlr_board_fmn_config.bucket_size[(bkt * 8) + 1], - xlr_board_fmn_config.bucket_size[(bkt * 8) + 2], - xlr_board_fmn_config.bucket_size[(bkt * 8) + 3], - xlr_board_fmn_config.bucket_size[(bkt * 8) + 4], - xlr_board_fmn_config.bucket_size[(bkt * 8) + 5], - xlr_board_fmn_config.bucket_size[(bkt * 8) + 6], - xlr_board_fmn_config.bucket_size[(bkt * 8) + 7]); - pr_info("\n"); - - pr_info("Credits distribution :\n"); - pr_info("Station\t: Size\n"); - for (bkt = 0; bkt < 16; bkt++) - pr_info(" %d %d %d %d %d %d %d %d\n", - fmn_info->credit_config[(bkt * 8) + 0], - fmn_info->credit_config[(bkt * 8) + 1], - fmn_info->credit_config[(bkt * 8) + 2], - fmn_info->credit_config[(bkt * 8) + 3], - fmn_info->credit_config[(bkt * 8) + 4], - fmn_info->credit_config[(bkt * 8) + 5], - fmn_info->credit_config[(bkt * 8) + 6], - fmn_info->credit_config[(bkt * 8) + 7]); - pr_info("\n"); -} - -static void check_credit_distribution(void) -{ - struct xlr_board_fmn_config *cfg = &xlr_board_fmn_config; - int bkt, n, total_credits, ncores; - - ncores = hweight32(nlm_current_node()->coremask); - for (bkt = 0; bkt < 128; bkt++) { - total_credits = 0; - for (n = 0; n < ncores; n++) - total_credits += cfg->cpu[n].credit_config[bkt]; - total_credits += cfg->gmac[0].credit_config[bkt]; - total_credits += cfg->gmac[1].credit_config[bkt]; - total_credits += cfg->dma.credit_config[bkt]; - total_credits += cfg->cmp.credit_config[bkt]; - total_credits += cfg->sae.credit_config[bkt]; - total_credits += cfg->xgmac[0].credit_config[bkt]; - total_credits += cfg->xgmac[1].credit_config[bkt]; - if (total_credits > cfg->bucket_size[bkt]) - pr_err("ERROR: Bucket %d: credits (%d) > size (%d)\n", - bkt, total_credits, cfg->bucket_size[bkt]); - } - pr_info("Credit distribution complete.\n"); -} - -/** - * setup_fmn_cc - Configure bucket size and credits for a device. - * @dev_info: FMN information structure for each devices - * @start_stn_id: Starting station id of dev_info - * @end_stn_id: End station id of dev_info - * @num_buckets: Total number of buckets for den_info - * @cpu_credits: Allowed credits to cpu for each devices pointing by dev_info - * @size: Size of the each buckets in the device station - * - * 'size' is the size of the buckets for the device. This size is - * distributed among all the CPUs - * so that all of them can send messages to the device. - * - * The device is also given 'cpu_credits' to send messages to the CPUs - */ -static void setup_fmn_cc(struct xlr_fmn_info *dev_info, int start_stn_id, - int end_stn_id, int num_buckets, int cpu_credits, int size) -{ - int i, j, num_core, n, credits_per_cpu; - struct xlr_fmn_info *cpu = xlr_board_fmn_config.cpu; - - num_core = hweight32(nlm_current_node()->coremask); - dev_info->num_buckets = num_buckets; - dev_info->start_stn_id = start_stn_id; - dev_info->end_stn_id = end_stn_id; - - n = num_core; - if (num_core == 3) - n = 4; - - for (i = start_stn_id; i <= end_stn_id; i++) { - xlr_board_fmn_config.bucket_size[i] = size; - - /* Dividing device credits equally to cpus */ - credits_per_cpu = size / n; - for (j = 0; j < num_core; j++) - cpu[j].credit_config[i] = credits_per_cpu; - - /* credits left to distribute */ - credits_per_cpu = size - (credits_per_cpu * num_core); - - /* distribute the remaining credits (if any), among cores */ - for (j = 0; (j < num_core) && (credits_per_cpu >= 4); j++) { - cpu[j].credit_config[i] += 4; - credits_per_cpu -= 4; - } - } - - /* Distributing cpu per bucket credits to devices */ - for (i = 0; i < num_core; i++) { - for (j = 0; j < FMN_CORE_NBUCKETS; j++) - dev_info->credit_config[(i * 8) + j] = cpu_credits; - } -} - -/* - * Each core has 256 slots and 8 buckets, - * Configure the 8 buckets each with 32 slots - */ -static void setup_cpu_fmninfo(struct xlr_fmn_info *cpu, int num_core) -{ - int i, j; - - for (i = 0; i < num_core; i++) { - cpu[i].start_stn_id = (8 * i); - cpu[i].end_stn_id = (8 * i + 8); - - for (j = cpu[i].start_stn_id; j < cpu[i].end_stn_id; j++) - xlr_board_fmn_config.bucket_size[j] = 32; - } -} - -/** - * xlr_board_info_setup - Setup FMN details - * - * Setup the FMN details for each devices according to the device available - * in each variant of XLR/XLS processor - */ -void xlr_board_info_setup(void) -{ - struct xlr_fmn_info *cpu = xlr_board_fmn_config.cpu; - struct xlr_fmn_info *gmac = xlr_board_fmn_config.gmac; - struct xlr_fmn_info *xgmac = xlr_board_fmn_config.xgmac; - struct xlr_fmn_info *dma = &xlr_board_fmn_config.dma; - struct xlr_fmn_info *cmp = &xlr_board_fmn_config.cmp; - struct xlr_fmn_info *sae = &xlr_board_fmn_config.sae; - int processor_id, num_core; - - num_core = hweight32(nlm_current_node()->coremask); - processor_id = read_c0_prid() & PRID_IMP_MASK; - - setup_cpu_fmninfo(cpu, num_core); - switch (processor_id) { - case PRID_IMP_NETLOGIC_XLS104: - case PRID_IMP_NETLOGIC_XLS108: - setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, - FMN_STNID_GMAC0_TX3, 8, 16, 32); - setup_fmn_cc(dma, FMN_STNID_DMA_0, - FMN_STNID_DMA_3, 4, 8, 64); - setup_fmn_cc(sae, FMN_STNID_SEC0, - FMN_STNID_SEC1, 2, 8, 128); - break; - - case PRID_IMP_NETLOGIC_XLS204: - case PRID_IMP_NETLOGIC_XLS208: - setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, - FMN_STNID_GMAC0_TX3, 8, 16, 32); - setup_fmn_cc(dma, FMN_STNID_DMA_0, - FMN_STNID_DMA_3, 4, 8, 64); - setup_fmn_cc(sae, FMN_STNID_SEC0, - FMN_STNID_SEC1, 2, 8, 128); - break; - - case PRID_IMP_NETLOGIC_XLS404: - case PRID_IMP_NETLOGIC_XLS408: - case PRID_IMP_NETLOGIC_XLS404B: - case PRID_IMP_NETLOGIC_XLS408B: - case PRID_IMP_NETLOGIC_XLS416B: - case PRID_IMP_NETLOGIC_XLS608B: - case PRID_IMP_NETLOGIC_XLS616B: - setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, - FMN_STNID_GMAC0_TX3, 8, 8, 32); - setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0, - FMN_STNID_GMAC1_TX3, 8, 8, 32); - setup_fmn_cc(dma, FMN_STNID_DMA_0, - FMN_STNID_DMA_3, 4, 4, 64); - setup_fmn_cc(cmp, FMN_STNID_CMP_0, - FMN_STNID_CMP_3, 4, 4, 64); - setup_fmn_cc(sae, FMN_STNID_SEC0, - FMN_STNID_SEC1, 2, 8, 128); - break; - - case PRID_IMP_NETLOGIC_XLS412B: - setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, - FMN_STNID_GMAC0_TX3, 8, 8, 32); - setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0, - FMN_STNID_GMAC1_TX3, 8, 8, 32); - setup_fmn_cc(dma, FMN_STNID_DMA_0, - FMN_STNID_DMA_3, 4, 4, 64); - setup_fmn_cc(cmp, FMN_STNID_CMP_0, - FMN_STNID_CMP_3, 4, 4, 64); - setup_fmn_cc(sae, FMN_STNID_SEC0, - FMN_STNID_SEC1, 2, 8, 128); - break; - - case PRID_IMP_NETLOGIC_XLR308: - case PRID_IMP_NETLOGIC_XLR308C: - setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, - FMN_STNID_GMAC0_TX3, 8, 16, 32); - setup_fmn_cc(dma, FMN_STNID_DMA_0, - FMN_STNID_DMA_3, 4, 8, 64); - setup_fmn_cc(sae, FMN_STNID_SEC0, - FMN_STNID_SEC1, 2, 4, 128); - break; - - case PRID_IMP_NETLOGIC_XLR532: - case PRID_IMP_NETLOGIC_XLR532C: - case PRID_IMP_NETLOGIC_XLR516C: - case PRID_IMP_NETLOGIC_XLR508C: - setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, - FMN_STNID_GMAC0_TX3, 8, 16, 32); - setup_fmn_cc(dma, FMN_STNID_DMA_0, - FMN_STNID_DMA_3, 4, 8, 64); - setup_fmn_cc(sae, FMN_STNID_SEC0, - FMN_STNID_SEC1, 2, 4, 128); - break; - - case PRID_IMP_NETLOGIC_XLR732: - case PRID_IMP_NETLOGIC_XLR716: - setup_fmn_cc(&xgmac[0], FMN_STNID_XMAC0_00_TX, - FMN_STNID_XMAC0_15_TX, 8, 0, 32); - setup_fmn_cc(&xgmac[1], FMN_STNID_XMAC1_00_TX, - FMN_STNID_XMAC1_15_TX, 8, 0, 32); - setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, - FMN_STNID_GMAC0_TX3, 8, 24, 32); - setup_fmn_cc(dma, FMN_STNID_DMA_0, - FMN_STNID_DMA_3, 4, 4, 64); - setup_fmn_cc(sae, FMN_STNID_SEC0, - FMN_STNID_SEC1, 2, 4, 128); - break; - default: - pr_err("Unknown CPU with processor ID [%d]\n", processor_id); - pr_err("Error: Cannot initialize FMN credits.\n"); - } - - check_credit_distribution(); - -#if 0 /* debug */ - print_credit_config(&cpu[0]); - print_credit_config(&gmac[0]); -#endif -} diff --git a/arch/mips/netlogic/xlr/fmn.c b/arch/mips/netlogic/xlr/fmn.c deleted file mode 100644 index f90303f31967..000000000000 --- a/arch/mips/netlogic/xlr/fmn.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/irqreturn.h> -#include <linux/irq.h> -#include <linux/interrupt.h> - -#include <asm/mipsregs.h> -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/xlr/fmn.h> -#include <asm/netlogic/common.h> - -#define COP2_CC_INIT_CPU_DEST(dest, conf) \ -do { \ - nlm_write_c2_cc##dest(0, conf[(dest * 8) + 0]); \ - nlm_write_c2_cc##dest(1, conf[(dest * 8) + 1]); \ - nlm_write_c2_cc##dest(2, conf[(dest * 8) + 2]); \ - nlm_write_c2_cc##dest(3, conf[(dest * 8) + 3]); \ - nlm_write_c2_cc##dest(4, conf[(dest * 8) + 4]); \ - nlm_write_c2_cc##dest(5, conf[(dest * 8) + 5]); \ - nlm_write_c2_cc##dest(6, conf[(dest * 8) + 6]); \ - nlm_write_c2_cc##dest(7, conf[(dest * 8) + 7]); \ -} while (0) - -struct fmn_message_handler { - void (*action)(int, int, int, int, struct nlm_fmn_msg *, void *); - void *arg; -} msg_handlers[128]; - -/* - * FMN interrupt handler. We configure the FMN so that any messages in - * any of the CPU buckets will trigger an interrupt on the CPU. - * The message can be from any device on the FMN (like NAE/SAE/DMA). - * The source station id is used to figure out which of the registered - * handlers have to be called. - */ -static irqreturn_t fmn_message_handler(int irq, void *data) -{ - struct fmn_message_handler *hndlr; - int bucket, rv; - int size = 0, code = 0, src_stnid = 0; - struct nlm_fmn_msg msg; - uint32_t mflags, bkt_status; - - mflags = nlm_cop2_enable_irqsave(); - /* Disable message ring interrupt */ - nlm_fmn_setup_intr(irq, 0); - while (1) { - /* 8 bkts per core, [24:31] each bit represents one bucket - * Bit is Zero if bucket is not empty */ - bkt_status = (nlm_read_c2_status0() >> 24) & 0xff; - if (bkt_status == 0xff) - break; - for (bucket = 0; bucket < 8; bucket++) { - /* Continue on empty bucket */ - if (bkt_status & (1 << bucket)) - continue; - rv = nlm_fmn_receive(bucket, &size, &code, &src_stnid, - &msg); - if (rv != 0) - continue; - - hndlr = &msg_handlers[src_stnid]; - if (hndlr->action == NULL) - pr_warn("No msgring handler for stnid %d\n", - src_stnid); - else { - nlm_cop2_disable_irqrestore(mflags); - hndlr->action(bucket, src_stnid, size, code, - &msg, hndlr->arg); - mflags = nlm_cop2_enable_irqsave(); - } - } - } - /* Enable message ring intr, to any thread in core */ - nlm_fmn_setup_intr(irq, (1 << nlm_threads_per_core) - 1); - nlm_cop2_disable_irqrestore(mflags); - return IRQ_HANDLED; -} - -void xlr_percpu_fmn_init(void) -{ - struct xlr_fmn_info *cpu_fmn_info; - int *bucket_sizes; - uint32_t flags; - int id; - - BUG_ON(nlm_thread_id() != 0); - id = nlm_core_id(); - - bucket_sizes = xlr_board_fmn_config.bucket_size; - cpu_fmn_info = &xlr_board_fmn_config.cpu[id]; - flags = nlm_cop2_enable_irqsave(); - - /* Setup bucket sizes for the core. */ - nlm_write_c2_bucksize(0, bucket_sizes[id * 8 + 0]); - nlm_write_c2_bucksize(1, bucket_sizes[id * 8 + 1]); - nlm_write_c2_bucksize(2, bucket_sizes[id * 8 + 2]); - nlm_write_c2_bucksize(3, bucket_sizes[id * 8 + 3]); - nlm_write_c2_bucksize(4, bucket_sizes[id * 8 + 4]); - nlm_write_c2_bucksize(5, bucket_sizes[id * 8 + 5]); - nlm_write_c2_bucksize(6, bucket_sizes[id * 8 + 6]); - nlm_write_c2_bucksize(7, bucket_sizes[id * 8 + 7]); - - /* - * For sending FMN messages, we need credits on the destination - * bucket. Program the credits this core has on the 128 possible - * destination buckets. - * We cannot use a loop here, because the the first argument has - * to be a constant integer value. - */ - COP2_CC_INIT_CPU_DEST(0, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(1, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(2, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(3, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(4, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(5, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(6, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(7, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(8, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(9, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(10, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(11, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(12, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(13, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(14, cpu_fmn_info->credit_config); - COP2_CC_INIT_CPU_DEST(15, cpu_fmn_info->credit_config); - - /* enable FMN interrupts on this CPU */ - nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1); - nlm_cop2_disable_irqrestore(flags); -} - - -/* - * Register a FMN message handler with respect to the source station id - * @stnid: source station id - * @action: Handler function pointer - */ -int nlm_register_fmn_handler(int start_stnid, int end_stnid, - void (*action)(int, int, int, int, struct nlm_fmn_msg *, void *), - void *arg) -{ - int sstnid; - - for (sstnid = start_stnid; sstnid <= end_stnid; sstnid++) { - msg_handlers[sstnid].arg = arg; - smp_wmb(); - msg_handlers[sstnid].action = action; - } - pr_debug("Registered FMN msg handler for stnid %d-%d\n", - start_stnid, end_stnid); - return 0; -} - -void nlm_setup_fmn_irq(void) -{ - uint32_t flags; - - /* request irq only once */ - if (request_irq(IRQ_FMN, fmn_message_handler, IRQF_PERCPU, "fmn", NULL)) - pr_err("Failed to request irq %d (fmn)\n", IRQ_FMN); - - flags = nlm_cop2_enable_irqsave(); - nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1); - nlm_cop2_disable_irqrestore(flags); -} diff --git a/arch/mips/netlogic/xlr/platform-flash.c b/arch/mips/netlogic/xlr/platform-flash.c deleted file mode 100644 index cf9162284b07..000000000000 --- a/arch/mips/netlogic/xlr/platform-flash.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright 2011, Netlogic Microsystems. - * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/ioport.h> -#include <linux/resource.h> -#include <linux/spi/flash.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/platnand.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlr/iomap.h> -#include <asm/netlogic/xlr/flash.h> -#include <asm/netlogic/xlr/bridge.h> -#include <asm/netlogic/xlr/gpio.h> -#include <asm/netlogic/xlr/xlr.h> - -/* - * Default NOR partition layout - */ -static struct mtd_partition xlr_nor_parts[] = { - { - .name = "User FS", - .offset = 0x800000, - .size = MTDPART_SIZ_FULL, - } -}; - -/* - * Default NAND partition layout - */ -static struct mtd_partition xlr_nand_parts[] = { - { - .name = "Root Filesystem", - .offset = 64 * 64 * 2048, - .size = 432 * 64 * 2048, - }, - { - .name = "Home Filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -/* Use PHYSMAP flash for NOR */ -struct physmap_flash_data xlr_nor_data = { - .width = 2, - .parts = xlr_nor_parts, - .nr_parts = ARRAY_SIZE(xlr_nor_parts), -}; - -static struct resource xlr_nor_res[] = { - { - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device xlr_nor_dev = { - .name = "physmap-flash", - .dev = { - .platform_data = &xlr_nor_data, - }, - .num_resources = ARRAY_SIZE(xlr_nor_res), - .resource = xlr_nor_res, -}; - -/* - * Use "gen_nand" driver for NAND flash - * - * There seems to be no way to store a private pointer containing - * platform specific info in gen_nand drivier. We will use a global - * struct for now, since we currently have only one NAND chip per board. - */ -struct xlr_nand_flash_priv { - int cs; - uint64_t flash_mmio; -}; - -static struct xlr_nand_flash_priv nand_priv; - -static void xlr_nand_ctrl(struct nand_chip *chip, int cmd, - unsigned int ctrl) -{ - if (ctrl & NAND_CLE) - nlm_write_reg(nand_priv.flash_mmio, - FLASH_NAND_CLE(nand_priv.cs), cmd); - else if (ctrl & NAND_ALE) - nlm_write_reg(nand_priv.flash_mmio, - FLASH_NAND_ALE(nand_priv.cs), cmd); -} - -struct platform_nand_data xlr_nand_data = { - .chip = { - .nr_chips = 1, - .nr_partitions = ARRAY_SIZE(xlr_nand_parts), - .chip_delay = 50, - .partitions = xlr_nand_parts, - }, - .ctrl = { - .cmd_ctrl = xlr_nand_ctrl, - }, -}; - -static struct resource xlr_nand_res[] = { - { - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device xlr_nand_dev = { - .name = "gen_nand", - .id = -1, - .num_resources = ARRAY_SIZE(xlr_nand_res), - .resource = xlr_nand_res, - .dev = { - .platform_data = &xlr_nand_data, - } -}; - -/* - * XLR/XLS supports upto 8 devices on its FLASH interface. The value in - * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the - * flash devices. - * Under this, each flash device has an offset and size given by the - * CSBASE_ADDR and CSBASE_MASK registers for the device. - * - * The CSBASE_ registers are expected to be setup by the bootloader. - */ -static void setup_flash_resource(uint64_t flash_mmio, - uint64_t flash_map_base, int cs, struct resource *res) -{ - u32 base, mask; - - base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); - mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); - - res->start = flash_map_base + ((unsigned long)base << 16); - res->end = res->start + (mask + 1) * 64 * 1024; -} - -static int __init xlr_flash_init(void) -{ - uint64_t gpio_mmio, flash_mmio, flash_map_base; - u32 gpio_resetcfg, flash_bar; - int cs, boot_nand, boot_nor; - - /* Flash address bits 39:24 is in bridge flash BAR */ - flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR); - flash_map_base = (flash_bar & 0xffff0000) << 8; - - gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); - flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET); - - /* Get the chip reset config */ - gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG); - - /* Check for boot flash type */ - boot_nor = boot_nand = 0; - if (nlm_chip_is_xls()) { - /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */ - if (gpio_resetcfg & (1 << 16)) - boot_nand = 1; - - /* check boot from PCMCIA, (GPIO reset reg bit 15 */ - if ((gpio_resetcfg & (1 << 15)) == 0) - boot_nor = 1; /* not set, booted from NOR */ - } else { /* XLR */ - /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */ - if ((gpio_resetcfg & (1 << 16)) == 0) - boot_nor = 1; /* not set, booted from NOR */ - } - - /* boot flash at chip select 0 */ - cs = 0; - - if (boot_nand) { - nand_priv.cs = cs; - nand_priv.flash_mmio = flash_mmio; - setup_flash_resource(flash_mmio, flash_map_base, cs, - xlr_nand_res); - - /* Initialize NAND flash at CS 0 */ - nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs), - FLASH_NAND_CSDEV_PARAM); - nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs), - FLASH_NAND_CSTIME_PARAMA); - nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs), - FLASH_NAND_CSTIME_PARAMB); - - pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res); - return platform_device_register(&xlr_nand_dev); - } - - if (boot_nor) { - setup_flash_resource(flash_mmio, flash_map_base, cs, - xlr_nor_res); - pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res); - return platform_device_register(&xlr_nor_dev); - } - return 0; -} - -arch_initcall(xlr_flash_init); diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c deleted file mode 100644 index 4785932af248..000000000000 --- a/arch/mips/netlogic/xlr/platform.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright 2011, Netlogic Microsystems. - * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/device.h> -#include <linux/platform_device.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/resource.h> -#include <linux/serial_8250.h> -#include <linux/serial_reg.h> -#include <linux/i2c.h> -#include <linux/usb/ehci_pdriver.h> -#include <linux/usb/ohci_pdriver.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/xlr/iomap.h> -#include <asm/netlogic/xlr/pic.h> -#include <asm/netlogic/xlr/xlr.h> - -static unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) -{ - uint64_t uartbase; - unsigned int value; - - /* sign extend to 64 bits, if needed */ - uartbase = (uint64_t)(long)p->membase; - value = nlm_read_reg(uartbase, offset); - - /* See XLR/XLS errata */ - if (offset == UART_MSR) - value ^= 0xF0; - else if (offset == UART_MCR) - value ^= 0x3; - - return value; -} - -static void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) -{ - uint64_t uartbase; - - /* sign extend to 64 bits, if needed */ - uartbase = (uint64_t)(long)p->membase; - - /* See XLR/XLS errata */ - if (offset == UART_MSR) - value ^= 0xF0; - else if (offset == UART_MCR) - value ^= 0x3; - - nlm_write_reg(uartbase, offset, value); -} - -#define PORT(_irq) \ - { \ - .irq = _irq, \ - .regshift = 2, \ - .iotype = UPIO_MEM32, \ - .flags = (UPF_SKIP_TEST | \ - UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\ - .uartclk = PIC_CLK_HZ, \ - .type = PORT_16550A, \ - .serial_in = nlm_xlr_uart_in, \ - .serial_out = nlm_xlr_uart_out, \ - } - -static struct plat_serial8250_port xlr_uart_data[] = { - PORT(PIC_UART_0_IRQ), - PORT(PIC_UART_1_IRQ), - {}, -}; - -static struct platform_device uart_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = xlr_uart_data, - }, -}; - -static int __init nlm_uart_init(void) -{ - unsigned long uartbase; - - uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); - xlr_uart_data[0].membase = (void __iomem *)uartbase; - xlr_uart_data[0].mapbase = CPHYSADDR(uartbase); - - uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_1_OFFSET); - xlr_uart_data[1].membase = (void __iomem *)uartbase; - xlr_uart_data[1].mapbase = CPHYSADDR(uartbase); - - return platform_device_register(&uart_device); -} - -arch_initcall(nlm_uart_init); - -#ifdef CONFIG_USB -/* Platform USB devices, only on XLS chips */ -static u64 xls_usb_dmamask = ~(u32)0; -#define USB_PLATFORM_DEV(n, i, irq) \ - { \ - .name = n, \ - .id = i, \ - .num_resources = 2, \ - .dev = { \ - .dma_mask = &xls_usb_dmamask, \ - .coherent_dma_mask = 0xffffffff, \ - }, \ - .resource = (struct resource[]) { \ - { \ - .flags = IORESOURCE_MEM, \ - }, \ - { \ - .start = irq, \ - .end = irq, \ - .flags = IORESOURCE_IRQ, \ - }, \ - }, \ - } - -static struct usb_ehci_pdata xls_usb_ehci_pdata = { - .caps_offset = 0, -}; - -static struct usb_ohci_pdata xls_usb_ohci_pdata; - -static struct platform_device xls_usb_ehci_device = - USB_PLATFORM_DEV("ehci-platform", 0, PIC_USB_IRQ); -static struct platform_device xls_usb_ohci_device_0 = - USB_PLATFORM_DEV("ohci-platform", 1, PIC_USB_IRQ); -static struct platform_device xls_usb_ohci_device_1 = - USB_PLATFORM_DEV("ohci-platform", 2, PIC_USB_IRQ); - -static struct platform_device *xls_platform_devices[] = { - &xls_usb_ehci_device, - &xls_usb_ohci_device_0, - &xls_usb_ohci_device_1, -}; - -int xls_platform_usb_init(void) -{ - uint64_t usb_mmio, gpio_mmio; - unsigned long memres; - uint32_t val; - - if (!nlm_chip_is_xls()) - return 0; - - gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); - usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_1_OFFSET); - - /* Clear Rogue Phy INTs */ - nlm_write_reg(usb_mmio, 49, 0x10000000); - /* Enable all interrupts */ - nlm_write_reg(usb_mmio, 50, 0x1f000000); - - /* Enable ports */ - nlm_write_reg(usb_mmio, 1, 0x07000500); - - val = nlm_read_reg(gpio_mmio, 21); - if (((val >> 22) & 0x01) == 0) { - pr_info("Detected USB Device mode - Not supported!\n"); - nlm_write_reg(usb_mmio, 0, 0x01000000); - return 0; - } - - pr_info("Detected USB Host mode - Adding XLS USB devices.\n"); - /* Clear reset, host mode */ - nlm_write_reg(usb_mmio, 0, 0x02000000); - - /* Memory resource for various XLS usb ports */ - usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET); - memres = CPHYSADDR((unsigned long)usb_mmio); - xls_usb_ehci_device.resource[0].start = memres; - xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1; - xls_usb_ehci_device.dev.platform_data = &xls_usb_ehci_pdata; - - memres += 0x400; - xls_usb_ohci_device_0.resource[0].start = memres; - xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1; - xls_usb_ohci_device_0.dev.platform_data = &xls_usb_ohci_pdata; - - memres += 0x400; - xls_usb_ohci_device_1.resource[0].start = memres; - xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1; - xls_usb_ohci_device_1.dev.platform_data = &xls_usb_ohci_pdata; - - return platform_add_devices(xls_platform_devices, - ARRAY_SIZE(xls_platform_devices)); -} - -arch_initcall(xls_platform_usb_init); -#endif - -#ifdef CONFIG_I2C -static struct i2c_board_info nlm_i2c_board_info1[] __initdata = { - /* All XLR boards have this RTC and Max6657 Temp Chip */ - [0] = { - .type = "ds1374", - .addr = 0x68 - }, - [1] = { - .type = "lm90", - .addr = 0x4c - }, -}; - -static struct resource i2c_resources[] = { - [0] = { - .start = 0, /* filled at init */ - .end = 0, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device nlm_xlr_i2c_1 = { - .name = "xlr-i2cbus", - .id = 1, - .num_resources = 1, - .resource = i2c_resources, -}; - -static int __init nlm_i2c_init(void) -{ - int err = 0; - unsigned int offset; - - /* I2C bus 0 does not have any useful devices, configure only bus 1 */ - offset = NETLOGIC_IO_I2C_1_OFFSET; - nlm_xlr_i2c_1.resource[0].start = CPHYSADDR(nlm_mmio_base(offset)); - nlm_xlr_i2c_1.resource[0].end = nlm_xlr_i2c_1.resource[0].start + 0xfff; - - platform_device_register(&nlm_xlr_i2c_1); - - err = i2c_register_board_info(1, nlm_i2c_board_info1, - ARRAY_SIZE(nlm_i2c_board_info1)); - if (err < 0) - pr_err("nlm-i2c: cannot register board I2C devices\n"); - return err; -} - -arch_initcall(nlm_i2c_init); -#endif diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c deleted file mode 100644 index aa83d691df0f..000000000000 --- a/arch/mips/netlogic/xlr/setup.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/kernel.h> -#include <linux/serial_8250.h> -#include <linux/memblock.h> -#include <linux/pm.h> - -#include <asm/idle.h> -#include <asm/reboot.h> -#include <asm/time.h> -#include <asm/bootinfo.h> - -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/psb-bootinfo.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> - -#include <asm/netlogic/xlr/xlr.h> -#include <asm/netlogic/xlr/iomap.h> -#include <asm/netlogic/xlr/pic.h> -#include <asm/netlogic/xlr/gpio.h> -#include <asm/netlogic/xlr/fmn.h> - -uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE; -struct psb_info nlm_prom_info; - -/* default to uniprocessor */ -unsigned int nlm_threads_per_core = 1; -struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; -cpumask_t nlm_cpumask = CPU_MASK_CPU0; - -static void nlm_linux_exit(void) -{ - uint64_t gpiobase; - - gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); - /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ - nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1); - for ( ; ; ) - cpu_wait(); -} - -void __init plat_mem_setup(void) -{ - _machine_restart = (void (*)(char *))nlm_linux_exit; - _machine_halt = nlm_linux_exit; - pm_power_off = nlm_linux_exit; -} - -const char *get_system_type(void) -{ - return "Netlogic XLR/XLS Series"; -} - -unsigned int nlm_get_cpu_frequency(void) -{ - return (unsigned int)nlm_prom_info.cpu_frequency; -} - -void nlm_percpu_init(int hwcpuid) -{ - if (hwcpuid % 4 == 0) - xlr_percpu_fmn_init(); -} - -static void __init build_arcs_cmdline(int *argv) -{ - int i, remain, len; - char *arg; - - remain = sizeof(arcs_cmdline) - 1; - arcs_cmdline[0] = '\0'; - for (i = 0; argv[i] != 0; i++) { - arg = (char *)(long)argv[i]; - len = strlen(arg); - if (len + 1 > remain) - break; - strcat(arcs_cmdline, arg); - strcat(arcs_cmdline, " "); - remain -= len + 1; - } - - /* Add the default options here */ - if ((strstr(arcs_cmdline, "console=")) == NULL) { - arg = "console=ttyS0,38400 "; - len = strlen(arg); - if (len > remain) - goto fail; - strcat(arcs_cmdline, arg); - remain -= len; - } -#ifdef CONFIG_BLK_DEV_INITRD - if ((strstr(arcs_cmdline, "rdinit=")) == NULL) { - arg = "rdinit=/sbin/init "; - len = strlen(arg); - if (len > remain) - goto fail; - strcat(arcs_cmdline, arg); - remain -= len; - } -#endif - return; -fail: - panic("Cannot add %s, command line too big!", arg); -} - -static void prom_add_memory(void) -{ - struct nlm_boot_mem_map *bootm; - u64 start, size; - u64 pref_backup = 512; /* avoid pref walking beyond end */ - int i; - - bootm = (void *)(long)nlm_prom_info.psb_mem_map; - for (i = 0; i < bootm->nr_map; i++) { - if (bootm->map[i].type != NLM_BOOT_MEM_RAM) - continue; - start = bootm->map[i].addr; - size = bootm->map[i].size; - - /* Work around for using bootloader mem */ - if (i == 0 && start == 0 && size == 0x0c000000) - size = 0x0ff00000; - - memblock_add(start, size - pref_backup); - } -} - -static void nlm_init_node(void) -{ - struct nlm_soc_info *nodep; - - nodep = nlm_current_node(); - nodep->picbase = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET); - nodep->ebase = read_c0_ebase() & MIPS_EBASE_BASE; - spin_lock_init(&nodep->piclock); -} - -void __init prom_init(void) -{ - int *argv, *envp; /* passed as 32 bit ptrs */ - struct psb_info *prom_infop; - void *reset_vec; -#ifdef CONFIG_SMP - int i; -#endif - - /* truncate to 32 bit and sign extend all args */ - argv = (int *)(long)(int)fw_arg1; - envp = (int *)(long)(int)fw_arg2; - prom_infop = (struct psb_info *)(long)(int)fw_arg3; - - nlm_prom_info = *prom_infop; - nlm_init_node(); - - /* Update reset entry point with CPU init code */ - reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); - memset(reset_vec, 0, RESET_VEC_SIZE); - memcpy(reset_vec, (void *)nlm_reset_entry, - (nlm_reset_entry_end - nlm_reset_entry)); - - build_arcs_cmdline(argv); - prom_add_memory(); - -#ifdef CONFIG_SMP - for (i = 0; i < 32; i++) - if (nlm_prom_info.online_cpu_map & (1 << i)) - cpumask_set_cpu(i, &nlm_cpumask); - nlm_wakeup_secondary_cpus(); - register_smp_ops(&nlm_smp_ops); -#endif - xlr_board_info_setup(); - xlr_percpu_fmn_init(); -} diff --git a/arch/mips/netlogic/xlr/wakeup.c b/arch/mips/netlogic/xlr/wakeup.c deleted file mode 100644 index d61cba1e9c65..000000000000 --- a/arch/mips/netlogic/xlr/wakeup.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/delay.h> -#include <linux/threads.h> - -#include <asm/asm.h> -#include <asm/asm-offsets.h> -#include <asm/mipsregs.h> -#include <asm/addrspace.h> -#include <asm/string.h> - -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/mips-extns.h> - -#include <asm/netlogic/xlr/iomap.h> -#include <asm/netlogic/xlr/pic.h> - -int xlr_wakeup_secondary_cpus(void) -{ - struct nlm_soc_info *nodep; - unsigned int i, j, boot_cpu; - volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); - - /* - * In case of RMI boot, hit with NMI to get the cores - * from bootloader to linux code. - */ - nodep = nlm_get_node(0); - boot_cpu = hard_smp_processor_id(); - nlm_set_nmi_handler(nlm_rmiboot_preboot); - for (i = 0; i < NR_CPUS; i++) { - if (i == boot_cpu || !cpumask_test_cpu(i, &nlm_cpumask)) - continue; - nlm_pic_send_ipi(nodep->picbase, i, 1, 1); /* send NMI */ - } - - /* Fill up the coremask early */ - nodep->coremask = 1; - for (i = 1; i < nlm_cores_per_node(); i++) { - for (j = 1000000; j > 0; j--) { - if (cpu_ready[i * NLM_THREADS_PER_CORE]) - break; - udelay(10); - } - if (j != 0) - nodep->coremask |= (1u << i); - else - pr_err("Failed to wakeup core %d\n", i); - } - - return 0; -} diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index f3eecc065e5c..6ddefafd00cb 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -56,10 +56,7 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o -obj-$(CONFIG_CPU_XLR) += pci-xlr.o -obj-$(CONFIG_CPU_XLP) += pci-xlp.o ifdef CONFIG_PCI_MSI obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o -obj-$(CONFIG_CPU_XLP) += msi-xlp.o endif diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index 44be65c3e6bb..00206ff52988 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -36,6 +36,21 @@ #define VIA_COBALT_BRD_ID_REG 0x94 #define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4) +/* + * Default value of PCI Class Code on GT64111 is PCI_CLASS_MEMORY_OTHER (0x0580) + * instead of PCI_CLASS_BRIDGE_HOST (0x0600). Galileo explained this choice in + * document "GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs", + * section "6.5.3 PCI Autoconfiguration at RESET": + * + * Some PCs refuse to configure host bridges if they are found plugged into + * a PCI slot (ask the BIOS vendors why...). The "Memory Controller" Class + * Code does not cause a problem for these non-compliant BIOSes, so we used + * this as the default in the GT-64111. + * + * So fix the incorrect default value of PCI Class Code. More details are on: + * https://lore.kernel.org/r/20211102154831.xtrlgrmrizl5eidl@pali/ + * https://lore.kernel.org/r/20211102150201.GA11675@alpha.franken.de/ + */ static void qube_raq_galileo_early_fixup(struct pci_dev *dev) { if (dev->devfn == PCI_DEVFN(0, 0) && diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c deleted file mode 100644 index bb14335f804b..000000000000 --- a/arch/mips/pci/msi-xlp.c +++ /dev/null @@ -1,571 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/msi.h> -#include <linux/mm.h> -#include <linux/irq.h> -#include <linux/irqdesc.h> -#include <linux/console.h> - -#include <asm/io.h> - -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/mips-extns.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/pic.h> -#include <asm/netlogic/xlp-hal/pcibus.h> -#include <asm/netlogic/xlp-hal/bridge.h> - -#define XLP_MSIVEC_PER_LINK 32 -#define XLP_MSIXVEC_TOTAL (cpu_is_xlp9xx() ? 128 : 32) -#define XLP_MSIXVEC_PER_LINK (cpu_is_xlp9xx() ? 32 : 8) - -/* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */ -static inline int nlm_link_msiirq(int link, int msivec) -{ - return NLM_MSI_VEC_BASE + link * XLP_MSIVEC_PER_LINK + msivec; -} - -/* get the link MSI vector from irq number */ -static inline int nlm_irq_msivec(int irq) -{ - return (irq - NLM_MSI_VEC_BASE) % XLP_MSIVEC_PER_LINK; -} - -/* get the link from the irq number */ -static inline int nlm_irq_msilink(int irq) -{ - int total_msivec = XLP_MSIVEC_PER_LINK * PCIE_NLINKS; - - return ((irq - NLM_MSI_VEC_BASE) % total_msivec) / - XLP_MSIVEC_PER_LINK; -} - -/* - * For XLP 8xx/4xx/3xx/2xx, only 32 MSI-X vectors are possible because - * there are only 32 PIC interrupts for MSI. We split them statically - * and use 8 MSI-X vectors per link - this keeps the allocation and - * lookup simple. - * On XLP 9xx, there are 32 vectors per link, and the interrupts are - * not routed thru PIC, so we can use all 128 MSI-X vectors. - */ -static inline int nlm_link_msixirq(int link, int bit) -{ - return NLM_MSIX_VEC_BASE + link * XLP_MSIXVEC_PER_LINK + bit; -} - -/* get the link MSI vector from irq number */ -static inline int nlm_irq_msixvec(int irq) -{ - return (irq - NLM_MSIX_VEC_BASE) % XLP_MSIXVEC_TOTAL; -} - -/* get the link from MSIX vec */ -static inline int nlm_irq_msixlink(int msixvec) -{ - return msixvec / XLP_MSIXVEC_PER_LINK; -} - -/* - * Per link MSI and MSI-X information, set as IRQ handler data for - * MSI and MSI-X interrupts. - */ -struct xlp_msi_data { - struct nlm_soc_info *node; - uint64_t lnkbase; - uint32_t msi_enabled_mask; - uint32_t msi_alloc_mask; - uint32_t msix_alloc_mask; - spinlock_t msi_lock; -}; - -/* - * MSI Chip definitions - * - * On XLP, there is a PIC interrupt associated with each PCIe link on the - * chip (which appears as a PCI bridge to us). This gives us 32 MSI irqa - * per link and 128 overall. - * - * When a device connected to the link raises a MSI interrupt, we get a - * link interrupt and we then have to look at PCIE_MSI_STATUS register at - * the bridge to map it to the IRQ - */ -static void xlp_msi_enable(struct irq_data *d) -{ - struct xlp_msi_data *md = irq_data_get_irq_chip_data(d); - unsigned long flags; - int vec; - - vec = nlm_irq_msivec(d->irq); - spin_lock_irqsave(&md->msi_lock, flags); - md->msi_enabled_mask |= 1u << vec; - if (cpu_is_xlp9xx()) - nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN, - md->msi_enabled_mask); - else - nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask); - spin_unlock_irqrestore(&md->msi_lock, flags); -} - -static void xlp_msi_disable(struct irq_data *d) -{ - struct xlp_msi_data *md = irq_data_get_irq_chip_data(d); - unsigned long flags; - int vec; - - vec = nlm_irq_msivec(d->irq); - spin_lock_irqsave(&md->msi_lock, flags); - md->msi_enabled_mask &= ~(1u << vec); - if (cpu_is_xlp9xx()) - nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN, - md->msi_enabled_mask); - else - nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask); - spin_unlock_irqrestore(&md->msi_lock, flags); -} - -static void xlp_msi_mask_ack(struct irq_data *d) -{ - struct xlp_msi_data *md = irq_data_get_irq_chip_data(d); - int link, vec; - - link = nlm_irq_msilink(d->irq); - vec = nlm_irq_msivec(d->irq); - xlp_msi_disable(d); - - /* Ack MSI on bridge */ - if (cpu_is_xlp9xx()) - nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec); - else - nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec); - -} - -static struct irq_chip xlp_msi_chip = { - .name = "XLP-MSI", - .irq_enable = xlp_msi_enable, - .irq_disable = xlp_msi_disable, - .irq_mask_ack = xlp_msi_mask_ack, - .irq_unmask = xlp_msi_enable, -}; - -/* - * XLP8XX/4XX/3XX/2XX: - * The MSI-X interrupt handling is different from MSI, there are 32 MSI-X - * interrupts generated by the PIC and each of these correspond to a MSI-X - * vector (0-31) that can be assigned. - * - * We divide the MSI-X vectors to 8 per link and do a per-link allocation - * - * XLP9XX: - * 32 MSI-X vectors are available per link, and the interrupts are not routed - * thru the PIC. PIC ack not needed. - * - * Enable and disable done using standard MSI functions. - */ -static void xlp_msix_mask_ack(struct irq_data *d) -{ - struct xlp_msi_data *md; - int link, msixvec; - uint32_t status_reg, bit; - - msixvec = nlm_irq_msixvec(d->irq); - link = nlm_irq_msixlink(msixvec); - pci_msi_mask_irq(d); - md = irq_data_get_irq_chip_data(d); - - /* Ack MSI on bridge */ - if (cpu_is_xlp9xx()) { - status_reg = PCIE_9XX_MSIX_STATUSX(link); - bit = msixvec % XLP_MSIXVEC_PER_LINK; - } else { - status_reg = PCIE_MSIX_STATUS; - bit = msixvec; - } - nlm_write_reg(md->lnkbase, status_reg, 1u << bit); - - if (!cpu_is_xlp9xx()) - nlm_pic_ack(md->node->picbase, - PIC_IRT_PCIE_MSIX_INDEX(msixvec)); -} - -static struct irq_chip xlp_msix_chip = { - .name = "XLP-MSIX", - .irq_enable = pci_msi_unmask_irq, - .irq_disable = pci_msi_mask_irq, - .irq_mask_ack = xlp_msix_mask_ack, - .irq_unmask = pci_msi_unmask_irq, -}; - -void arch_teardown_msi_irq(unsigned int irq) -{ -} - -/* - * Setup a PCIe link for MSI. By default, the links are in - * legacy interrupt mode. We will switch them to MSI mode - * at the first MSI request. - */ -static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr) -{ - u32 val; - - if (cpu_is_xlp9xx()) { - val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0); - if ((val & 0x200) == 0) { - val |= 0x200; /* MSI Interrupt enable */ - nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val); - } - } else { - val = nlm_read_reg(lnkbase, PCIE_INT_EN0); - if ((val & 0x200) == 0) { - val |= 0x200; - nlm_write_reg(lnkbase, PCIE_INT_EN0, val); - } - } - - val = nlm_read_reg(lnkbase, 0x1); /* CMD */ - if ((val & 0x0400) == 0) { - val |= 0x0400; - nlm_write_reg(lnkbase, 0x1, val); - } - - /* Update IRQ in the PCI irq reg */ - val = nlm_read_pci_reg(lnkbase, 0xf); - val &= ~0x1fu; - val |= (1 << 8) | lirq; - nlm_write_pci_reg(lnkbase, 0xf, val); - - /* MSI addr */ - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32); - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff); - - /* MSI cap for bridge */ - val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP); - if ((val & (1 << 16)) == 0) { - val |= 0xb << 16; /* mmc32, msi enable */ - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val); - } -} - -/* - * Allocate a MSI vector on a link - */ -static int xlp_setup_msi(uint64_t lnkbase, int node, int link, - struct msi_desc *desc) -{ - struct xlp_msi_data *md; - struct msi_msg msg; - unsigned long flags; - int msivec, irt, lirq, xirq, ret; - uint64_t msiaddr; - - /* Get MSI data for the link */ - lirq = PIC_PCIE_LINK_MSI_IRQ(link); - xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0)); - md = irq_get_chip_data(xirq); - msiaddr = MSI_LINK_ADDR(node, link); - - spin_lock_irqsave(&md->msi_lock, flags); - if (md->msi_alloc_mask == 0) { - xlp_config_link_msi(lnkbase, lirq, msiaddr); - /* switch the link IRQ to MSI range */ - if (cpu_is_xlp9xx()) - irt = PIC_9XX_IRT_PCIE_LINK_INDEX(link); - else - irt = PIC_IRT_PCIE_LINK_INDEX(link); - nlm_setup_pic_irq(node, lirq, lirq, irt); - nlm_pic_init_irt(nlm_get_node(node)->picbase, irt, lirq, - node * nlm_threads_per_node(), 1 /*en */); - } - - /* allocate a MSI vec, and tell the bridge about it */ - msivec = fls(md->msi_alloc_mask); - if (msivec == XLP_MSIVEC_PER_LINK) { - spin_unlock_irqrestore(&md->msi_lock, flags); - return -ENOMEM; - } - md->msi_alloc_mask |= (1u << msivec); - spin_unlock_irqrestore(&md->msi_lock, flags); - - msg.address_hi = msiaddr >> 32; - msg.address_lo = msiaddr & 0xffffffff; - msg.data = 0xc00 | msivec; - - xirq = xirq + msivec; /* msi mapped to global irq space */ - ret = irq_set_msi_desc(xirq, desc); - if (ret < 0) - return ret; - - pci_write_msi_msg(xirq, &msg); - return 0; -} - -/* - * Switch a link to MSI-X mode - */ -static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr) -{ - u32 val; - - val = nlm_read_reg(lnkbase, 0x2C); - if ((val & 0x80000000U) == 0) { - val |= 0x80000000U; - nlm_write_reg(lnkbase, 0x2C, val); - } - - if (cpu_is_xlp9xx()) { - val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0); - if ((val & 0x200) == 0) { - val |= 0x200; /* MSI Interrupt enable */ - nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val); - } - } else { - val = nlm_read_reg(lnkbase, PCIE_INT_EN0); - if ((val & 0x200) == 0) { - val |= 0x200; /* MSI Interrupt enable */ - nlm_write_reg(lnkbase, PCIE_INT_EN0, val); - } - } - - val = nlm_read_reg(lnkbase, 0x1); /* CMD */ - if ((val & 0x0400) == 0) { - val |= 0x0400; - nlm_write_reg(lnkbase, 0x1, val); - } - - /* Update IRQ in the PCI irq reg */ - val = nlm_read_pci_reg(lnkbase, 0xf); - val &= ~0x1fu; - val |= (1 << 8) | lirq; - nlm_write_pci_reg(lnkbase, 0xf, val); - - if (cpu_is_xlp9xx()) { - /* MSI-X addresses */ - nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE, - msixaddr >> 8); - nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT, - (msixaddr + MSI_ADDR_SZ) >> 8); - } else { - /* MSI-X addresses */ - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE, - msixaddr >> 8); - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT, - (msixaddr + MSI_ADDR_SZ) >> 8); - } -} - -/* - * Allocate a MSI-X vector - */ -static int xlp_setup_msix(uint64_t lnkbase, int node, int link, - struct msi_desc *desc) -{ - struct xlp_msi_data *md; - struct msi_msg msg; - unsigned long flags; - int t, msixvec, lirq, xirq, ret; - uint64_t msixaddr; - - /* Get MSI data for the link */ - lirq = PIC_PCIE_MSIX_IRQ(link); - xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0)); - md = irq_get_chip_data(xirq); - msixaddr = MSIX_LINK_ADDR(node, link); - - spin_lock_irqsave(&md->msi_lock, flags); - /* switch the PCIe link to MSI-X mode at the first alloc */ - if (md->msix_alloc_mask == 0) - xlp_config_link_msix(lnkbase, lirq, msixaddr); - - /* allocate a MSI-X vec, and tell the bridge about it */ - t = fls(md->msix_alloc_mask); - if (t == XLP_MSIXVEC_PER_LINK) { - spin_unlock_irqrestore(&md->msi_lock, flags); - return -ENOMEM; - } - md->msix_alloc_mask |= (1u << t); - spin_unlock_irqrestore(&md->msi_lock, flags); - - xirq += t; - msixvec = nlm_irq_msixvec(xirq); - - msg.address_hi = msixaddr >> 32; - msg.address_lo = msixaddr & 0xffffffff; - msg.data = 0xc00 | msixvec; - - ret = irq_set_msi_desc(xirq, desc); - if (ret < 0) - return ret; - - pci_write_msi_msg(xirq, &msg); - return 0; -} - -int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) -{ - struct pci_dev *lnkdev; - uint64_t lnkbase; - int node, link, slot; - - lnkdev = xlp_get_pcie_link(dev); - if (lnkdev == NULL) { - dev_err(&dev->dev, "Could not find bridge\n"); - return 1; - } - slot = PCI_SLOT(lnkdev->devfn); - link = PCI_FUNC(lnkdev->devfn); - node = slot / 8; - lnkbase = nlm_get_pcie_base(node, link); - - if (desc->msi_attrib.is_msix) - return xlp_setup_msix(lnkbase, node, link, desc); - else - return xlp_setup_msi(lnkbase, node, link, desc); -} - -void __init xlp_init_node_msi_irqs(int node, int link) -{ - struct nlm_soc_info *nodep; - struct xlp_msi_data *md; - int irq, i, irt, msixvec, val; - - pr_info("[%d %d] Init node PCI IRT\n", node, link); - nodep = nlm_get_node(node); - - /* Alloc an MSI block for the link */ - md = kzalloc(sizeof(*md), GFP_KERNEL); - spin_lock_init(&md->msi_lock); - md->msi_enabled_mask = 0; - md->msi_alloc_mask = 0; - md->msix_alloc_mask = 0; - md->node = nodep; - md->lnkbase = nlm_get_pcie_base(node, link); - - /* extended space for MSI interrupts */ - irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0)); - for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) { - irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq); - irq_set_chip_data(i, md); - } - - for (i = 0; i < XLP_MSIXVEC_PER_LINK ; i++) { - if (cpu_is_xlp9xx()) { - val = ((node * nlm_threads_per_node()) << 7 | - PIC_PCIE_MSIX_IRQ(link) << 1 | 0 << 0); - nlm_write_pcie_reg(md->lnkbase, PCIE_9XX_MSIX_VECX(i + - (link * XLP_MSIXVEC_PER_LINK)), val); - } else { - /* Initialize MSI-X irts to generate one interrupt - * per link - */ - msixvec = link * XLP_MSIXVEC_PER_LINK + i; - irt = PIC_IRT_PCIE_MSIX_INDEX(msixvec); - nlm_pic_init_irt(nodep->picbase, irt, - PIC_PCIE_MSIX_IRQ(link), - node * nlm_threads_per_node(), 1); - } - - /* Initialize MSI-X extended irq space for the link */ - irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i)); - irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq); - irq_set_chip_data(irq, md); - } -} - -void nlm_dispatch_msi(int node, int lirq) -{ - struct xlp_msi_data *md; - int link, i, irqbase; - u32 status; - - link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE; - irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0)); - md = irq_get_chip_data(irqbase); - if (cpu_is_xlp9xx()) - status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) & - md->msi_enabled_mask; - else - status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) & - md->msi_enabled_mask; - while (status) { - i = __ffs(status); - do_IRQ(irqbase + i); - status &= status - 1; - } - - /* Ack at eirr and PIC */ - ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link)); - if (cpu_is_xlp9xx()) - nlm_pic_ack(md->node->picbase, - PIC_9XX_IRT_PCIE_LINK_INDEX(link)); - else - nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link)); -} - -void nlm_dispatch_msix(int node, int lirq) -{ - struct xlp_msi_data *md; - int link, i, irqbase; - u32 status; - - link = lirq - PIC_PCIE_MSIX_IRQ_BASE; - irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0)); - md = irq_get_chip_data(irqbase); - if (cpu_is_xlp9xx()) - status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link)); - else - status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS); - - /* narrow it down to the MSI-x vectors for our link */ - if (!cpu_is_xlp9xx()) - status = (status >> (link * XLP_MSIXVEC_PER_LINK)) & - ((1 << XLP_MSIXVEC_PER_LINK) - 1); - - while (status) { - i = __ffs(status); - do_IRQ(irqbase + i); - status &= status - 1; - } - /* Ack at eirr and PIC */ - ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link)); -} diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c index 230d7dd273e2..ffac06a5ca20 100644 --- a/arch/mips/pci/pci-bcm47xx.c +++ b/arch/mips/pci/pci-bcm47xx.c @@ -41,8 +41,7 @@ static int bcm47xx_pcibios_plat_dev_init_ssb(struct pci_dev *dev) res = ssb_pcibios_plat_dev_init(dev); if (res < 0) { - printk(KERN_ALERT "PCI: Failed to init device %s\n", - pci_name(dev)); + pci_alert(dev, "PCI: Failed to init device\n"); return res; } @@ -52,8 +51,7 @@ static int bcm47xx_pcibios_plat_dev_init_ssb(struct pci_dev *dev) /* IRQ-0 and IRQ-1 are software interrupts. */ if (res < 2) { - printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n", - pci_name(dev)); + pci_alert(dev, "PCI: Failed to map IRQ of device\n"); return res; } @@ -69,8 +67,7 @@ static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev) res = bcma_core_pci_plat_dev_init(dev); if (res < 0) { - printk(KERN_ALERT "PCI: Failed to init device %s\n", - pci_name(dev)); + pci_alert(dev, "PCI: Failed to init device\n"); return res; } @@ -78,8 +75,7 @@ static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev) /* IRQ-0 and IRQ-1 are software interrupts. */ if (res < 2) { - printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n", - pci_name(dev)); + pci_alert(dev, "PCI: Failed to map IRQ of device\n"); return res; } @@ -93,12 +89,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev) #ifdef CONFIG_BCM47XX_SSB if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB) return bcm47xx_pcibios_plat_dev_init_ssb(dev); - else #endif #ifdef CONFIG_BCM47XX_BCMA if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) return bcm47xx_pcibios_plat_dev_init_bcma(dev); - else #endif - return 0; + return 0; } diff --git a/arch/mips/pci/pci-generic.c b/arch/mips/pci/pci-generic.c index 95b00017886c..18eb8a453a86 100644 --- a/arch/mips/pci/pci-generic.c +++ b/arch/mips/pci/pci-generic.c @@ -46,3 +46,17 @@ void pcibios_fixup_bus(struct pci_bus *bus) { pci_read_bridge_bases(bus); } + +int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) +{ + unsigned long vaddr; + + if (res->start != 0) { + WARN_ONCE(1, "resource start address is not zero\n"); + return -ENODEV; + } + + vaddr = (unsigned long)ioremap(phys_addr, resource_size(res)); + set_io_port_base(vaddr); + return 0; +} diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c deleted file mode 100644 index 9eff9137f78e..000000000000 --- a/arch/mips/pci/pci-xlp.c +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/msi.h> -#include <linux/mm.h> -#include <linux/irq.h> -#include <linux/irqdesc.h> -#include <linux/console.h> - -#include <asm/io.h> - -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/mips-extns.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/pic.h> -#include <asm/netlogic/xlp-hal/pcibus.h> -#include <asm/netlogic/xlp-hal/bridge.h> - -static void *pci_config_base; - -#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) - -/* PCI ops */ -static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, - int where) -{ - u32 data; - u32 *cfgaddr; - - where &= ~3; - if (cpu_is_xlp9xx()) { - /* be very careful on SoC buses */ - if (bus->number == 0) { - /* Scan only existing nodes - uboot bug? */ - if (PCI_SLOT(devfn) != 0 || - !nlm_node_present(PCI_FUNC(devfn))) - return 0xffffffff; - } else if (bus->parent->number == 0) { /* SoC bus */ - if (PCI_SLOT(devfn) == 0) /* b.0.0 hangs */ - return 0xffffffff; - if (devfn == 44) /* b.5.4 hangs */ - return 0xffffffff; - } - } else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) { - return 0xffffffff; - } - cfgaddr = (u32 *)(pci_config_base + - pci_cfg_addr(bus->number, devfn, where)); - data = *cfgaddr; - return data; -} - -static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, - int where, u32 data) -{ - u32 *cfgaddr; - - cfgaddr = (u32 *)(pci_config_base + - pci_cfg_addr(bus->number, devfn, where & ~3)); - *cfgaddr = data; -} - -static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - u32 data; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - data = pci_cfg_read_32bit(bus, devfn, where); - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - - -static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - data = pci_cfg_read_32bit(bus, devfn, where); - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else - data = val; - - pci_cfg_write_32bit(bus, devfn, where, data); - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops nlm_pci_ops = { - .read = nlm_pcibios_read, - .write = nlm_pcibios_write -}; - -static struct resource nlm_pci_mem_resource = { - .name = "XLP PCI MEM", - .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ - .end = 0xdfffffffUL, - .flags = IORESOURCE_MEM, -}; - -static struct resource nlm_pci_io_resource = { - .name = "XLP IO MEM", - .start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */ - .end = 0x17ffffffUL, - .flags = IORESOURCE_IO, -}; - -struct pci_controller nlm_pci_controller = { - .index = 0, - .pci_ops = &nlm_pci_ops, - .mem_resource = &nlm_pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_resource = &nlm_pci_io_resource, - .io_offset = 0x00000000UL, -}; - -struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) -{ - struct pci_bus *bus, *p; - - bus = dev->bus; - - if (cpu_is_xlp9xx()) { - /* find bus with grand parent number == 0 */ - for (p = bus->parent; p && p->parent && p->parent->number != 0; - p = p->parent) - bus = p; - return (p && p->parent) ? bus->self : NULL; - } else { - /* Find the bridge on bus 0 */ - for (p = bus->parent; p && p->number != 0; p = p->parent) - bus = p; - - return p ? bus->self : NULL; - } -} - -int xlp_socdev_to_node(const struct pci_dev *lnkdev) -{ - if (cpu_is_xlp9xx()) - return PCI_FUNC(lnkdev->bus->self->devfn); - else - return PCI_SLOT(lnkdev->devfn) / 8; -} - -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - struct pci_dev *lnkdev; - int lnkfunc, node; - - /* - * For XLP PCIe, there is an IRQ per Link, find out which - * link the device is on to assign interrupts - */ - lnkdev = xlp_get_pcie_link(dev); - if (lnkdev == NULL) - return 0; - - lnkfunc = PCI_FUNC(lnkdev->devfn); - node = xlp_socdev_to_node(lnkdev); - - return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc)); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -/* - * If big-endian, enable hardware byteswap on the PCIe bridges. - * This will make both the SoC and PCIe devices behave consistently with - * readl/writel. - */ -#ifdef __BIG_ENDIAN -static void xlp_config_pci_bswap(int node, int link) -{ - uint64_t nbubase, lnkbase; - u32 reg; - - nbubase = nlm_get_bridge_regbase(node); - lnkbase = nlm_get_pcie_base(node, link); - - /* - * Enable byte swap in hardware. Program each link's PCIe SWAP regions - * from the link's address ranges. - */ - if (cpu_is_xlp9xx()) { - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_9XX_PCIEMEM_BASE0 + link); - nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg); - - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_9XX_PCIEMEM_LIMIT0 + link); - nlm_write_pci_reg(lnkbase, - PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff); - - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_9XX_PCIEIO_BASE0 + link); - nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg); - - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_9XX_PCIEIO_LIMIT0 + link); - nlm_write_pci_reg(lnkbase, - PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff); - } else { - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); - - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_PCIEMEM_LIMIT0 + link); - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); - - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); - - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); - } -} -#else -/* Swap configuration not needed in little-endian mode */ -static inline void xlp_config_pci_bswap(int node, int link) {} -#endif /* __BIG_ENDIAN */ - -static int __init pcibios_init(void) -{ - uint64_t pciebase; - int link, n; - u32 reg; - - /* Firmware assigns PCI resources */ - pci_set_flags(PCI_PROBE_ONLY); - pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); - - /* Extend IO port for memory mapped io */ - ioport_resource.start = 0; - ioport_resource.end = ~0; - - for (n = 0; n < NLM_NR_NODES; n++) { - if (!nlm_node_present(n)) - continue; - - for (link = 0; link < PCIE_NLINKS; link++) { - pciebase = nlm_get_pcie_base(n, link); - if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) - continue; - xlp_config_pci_bswap(n, link); - xlp_init_node_msi_irqs(n, link); - - /* put in intpin and irq - u-boot does not */ - reg = nlm_read_pci_reg(pciebase, 0xf); - reg &= ~0x1ffu; - reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link); - nlm_write_pci_reg(pciebase, 0xf, reg); - pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); - } - } - - set_io_port_base(CKSEG1); - nlm_pci_controller.io_map_base = CKSEG1; - - register_pci_controller(&nlm_pci_controller); - pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource, - &nlm_pci_mem_resource); - - return 0; -} -arch_initcall(pcibios_init); diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c deleted file mode 100644 index 2a1c81a129ba..000000000000 --- a/arch/mips/pci/pci-xlr.c +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/msi.h> -#include <linux/mm.h> -#include <linux/irq.h> -#include <linux/irqdesc.h> -#include <linux/console.h> -#include <linux/pci_regs.h> - -#include <asm/io.h> - -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> - -#include <asm/netlogic/xlr/msidef.h> -#include <asm/netlogic/xlr/iomap.h> -#include <asm/netlogic/xlr/pic.h> -#include <asm/netlogic/xlr/xlr.h> - -static void *pci_config_base; - -#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) - -/* PCI ops */ -static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, - int where) -{ - u32 data; - u32 *cfgaddr; - - cfgaddr = (u32 *)(pci_config_base + - pci_cfg_addr(bus->number, devfn, where & ~3)); - data = *cfgaddr; - return cpu_to_le32(data); -} - -static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, - int where, u32 data) -{ - u32 *cfgaddr; - - cfgaddr = (u32 *)(pci_config_base + - pci_cfg_addr(bus->number, devfn, where & ~3)); - *cfgaddr = cpu_to_le32(data); -} - -static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - u32 data; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - data = pci_cfg_read_32bit(bus, devfn, where); - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - - -static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - data = pci_cfg_read_32bit(bus, devfn, where); - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else - data = val; - - pci_cfg_write_32bit(bus, devfn, where, data); - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops nlm_pci_ops = { - .read = nlm_pcibios_read, - .write = nlm_pcibios_write -}; - -static struct resource nlm_pci_mem_resource = { - .name = "XLR PCI MEM", - .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ - .end = 0xdfffffffUL, - .flags = IORESOURCE_MEM, -}; - -static struct resource nlm_pci_io_resource = { - .name = "XLR IO MEM", - .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ - .end = 0x100fffffUL, - .flags = IORESOURCE_IO, -}; - -struct pci_controller nlm_pci_controller = { - .index = 0, - .pci_ops = &nlm_pci_ops, - .mem_resource = &nlm_pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_resource = &nlm_pci_io_resource, - .io_offset = 0x00000000UL, -}; - -/* - * The top level PCIe links on the XLS PCIe controller appear as - * bridges. Given a device, this function finds which link it is - * on. - */ -static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev) -{ - struct pci_bus *bus, *p; - - /* Find the bridge on bus 0 */ - bus = dev->bus; - for (p = bus->parent; p && p->number != 0; p = p->parent) - bus = p; - - return p ? bus->self : NULL; -} - -static int nlm_pci_link_to_irq(int link) -{ - switch (link) { - case 0: - return PIC_PCIE_LINK0_IRQ; - case 1: - return PIC_PCIE_LINK1_IRQ; - case 2: - if (nlm_chip_is_xls_b()) - return PIC_PCIE_XLSB0_LINK2_IRQ; - else - return PIC_PCIE_LINK2_IRQ; - case 3: - if (nlm_chip_is_xls_b()) - return PIC_PCIE_XLSB0_LINK3_IRQ; - else - return PIC_PCIE_LINK3_IRQ; - } - WARN(1, "Unexpected link %d\n", link); - return 0; -} - -static int get_irq_vector(const struct pci_dev *dev) -{ - struct pci_dev *lnk; - int link; - - if (!nlm_chip_is_xls()) - return PIC_PCIX_IRQ; /* for XLR just one IRQ */ - - lnk = xls_get_pcie_link(dev); - if (lnk == NULL) - return 0; - - link = PCI_SLOT(lnk->devfn); - return nlm_pci_link_to_irq(link); -} - -#ifdef CONFIG_PCI_MSI -void arch_teardown_msi_irq(unsigned int irq) -{ -} - -int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) -{ - struct msi_msg msg; - struct pci_dev *lnk; - int irq, ret; - u16 val; - - /* MSI not supported on XLR */ - if (!nlm_chip_is_xls()) - return 1; - - /* - * Enable MSI on the XLS PCIe controller bridge which was disabled - * at enumeration, the bridge MSI capability is at 0x50 - */ - lnk = xls_get_pcie_link(dev); - if (lnk == NULL) - return 1; - - pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val); - if ((val & PCI_MSI_FLAGS_ENABLE) == 0) { - val |= PCI_MSI_FLAGS_ENABLE; - pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val); - } - - irq = get_irq_vector(dev); - if (irq <= 0) - return 1; - - msg.address_hi = MSI_ADDR_BASE_HI; - msg.address_lo = MSI_ADDR_BASE_LO | - MSI_ADDR_DEST_MODE_PHYSICAL | - MSI_ADDR_REDIRECTION_CPU; - - msg.data = MSI_DATA_TRIGGER_EDGE | - MSI_DATA_LEVEL_ASSERT | - MSI_DATA_DELIVERY_FIXED; - - ret = irq_set_msi_desc(irq, desc); - if (ret < 0) - return ret; - - pci_write_msi_msg(irq, &msg); - return 0; -} -#endif - -/* Extra ACK needed for XLR on chip PCI controller */ -static void xlr_pci_ack(struct irq_data *d) -{ - uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET); - - nlm_read_reg(pcibase, (0x140 >> 2)); -} - -/* Extra ACK needed for XLS on chip PCIe controller */ -static void xls_pcie_ack(struct irq_data *d) -{ - uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET); - - switch (d->irq) { - case PIC_PCIE_LINK0_IRQ: - nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); - break; - case PIC_PCIE_LINK1_IRQ: - nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); - break; - case PIC_PCIE_LINK2_IRQ: - nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); - break; - case PIC_PCIE_LINK3_IRQ: - nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff); - break; - } -} - -/* For XLS B silicon, the 3,4 PCI interrupts are different */ -static void xls_pcie_ack_b(struct irq_data *d) -{ - uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET); - - switch (d->irq) { - case PIC_PCIE_LINK0_IRQ: - nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); - break; - case PIC_PCIE_LINK1_IRQ: - nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); - break; - case PIC_PCIE_XLSB0_LINK2_IRQ: - nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); - break; - case PIC_PCIE_XLSB0_LINK3_IRQ: - nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff); - break; - } -} - -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return get_irq_vector(dev); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -static int __init pcibios_init(void) -{ - void (*extra_ack)(struct irq_data *); - int link, irq; - - /* PSB assigns PCI resources */ - pci_set_flags(PCI_PROBE_ONLY); - pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); - - /* Extend IO port for memory mapped io */ - ioport_resource.start = 0; - ioport_resource.end = ~0; - - set_io_port_base(CKSEG1); - nlm_pci_controller.io_map_base = CKSEG1; - - pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); - register_pci_controller(&nlm_pci_controller); - - /* - * For PCI interrupts, we need to ack the PCI controller too, overload - * irq handler data to do this - */ - if (!nlm_chip_is_xls()) { - /* XLR PCI controller ACK */ - nlm_set_pic_extra_ack(0, PIC_PCIX_IRQ, xlr_pci_ack); - } else { - if (nlm_chip_is_xls_b()) - extra_ack = xls_pcie_ack_b; - else - extra_ack = xls_pcie_ack; - for (link = 0; link < 4; link++) { - irq = nlm_pci_link_to_irq(link); - nlm_set_pic_extra_ack(0, irq, extra_ack); - } - } - return 0; -} - -arch_initcall(pcibios_init); diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index c800bf5559b5..120adad51d6a 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -51,7 +51,8 @@ choice select SYS_SUPPORTS_HIGHMEM select MIPS_GIC select CLKSRC_MIPS_GIC - select HAVE_PCI if PCI_MT7621 + select HAVE_PCI + select PCI_DRIVERS_GENERIC select SOC_BUS endchoice diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c index 23ad8dd9aa5e..b11693715547 100644 --- a/arch/mips/rb532/prom.c +++ b/arch/mips/rb532/prom.c @@ -16,7 +16,6 @@ #include <linux/console.h> #include <linux/memblock.h> #include <linux/ioport.h> -#include <linux/blkdev.h> #include <asm/bootinfo.h> #include <asm/mach-rc32434/ddr.h> diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c index 6173684b5aaa..adc2faeecf7c 100644 --- a/arch/mips/sgi-ip27/ip27-memory.c +++ b/arch/mips/sgi-ip27/ip27-memory.c @@ -341,7 +341,8 @@ static void __init szmem(void) continue; } memblock_add_node(PFN_PHYS(slot_getbasepfn(node, slot)), - PFN_PHYS(slot_psize), node); + PFN_PHYS(slot_psize), node, + MEMBLOCK_NONE); } } } diff --git a/arch/mips/sgi-ip30/ip30-setup.c b/arch/mips/sgi-ip30/ip30-setup.c index 44b1607e964d..75a34684e704 100644 --- a/arch/mips/sgi-ip30/ip30-setup.c +++ b/arch/mips/sgi-ip30/ip30-setup.c @@ -69,10 +69,10 @@ static void __init ip30_mem_init(void) total_mem += size; if (addr >= IP30_REAL_MEMORY_START) - memblock_free(addr, size); + memblock_phys_free(addr, size); else if ((addr + size) > IP30_REAL_MEMORY_START) - memblock_free(IP30_REAL_MEMORY_START, - size - IP30_MAX_PROM_MEMORY); + memblock_phys_free(IP30_REAL_MEMORY_START, + size - IP30_MAX_PROM_MEMORY); } pr_info("Detected %luMB of physical memory.\n", MEM_SHIFT(total_mem)); } diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c index a3323f8dcc1b..1a504294d85f 100644 --- a/arch/mips/sibyte/common/cfe.c +++ b/arch/mips/sibyte/common/cfe.c @@ -7,7 +7,6 @@ #include <linux/kernel.h> #include <linux/linkage.h> #include <linux/mm.h> -#include <linux/blkdev.h> #include <linux/memblock.h> #include <linux/pm.h> #include <linux/smp.h> diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 538a2791b48c..f07b15dd1c1a 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -11,7 +11,6 @@ #include <linux/spinlock.h> #include <linux/mm.h> #include <linux/memblock.h> -#include <linux/blkdev.h> #include <linux/init.h> #include <linux/kernel.h> #include <linux/screen_info.h> diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 240bb68ec247..ff3ba7e77890 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -18,14 +18,14 @@ static int a20r_set_periodic(struct clock_event_device *evt) { *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34; wmb(); - *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV; + *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV & 0xff; wmb(); *(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = SNI_COUNTER0_DIV >> 8; wmb(); *(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4; wmb(); - *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV; + *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV & 0xff; wmb(); *(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = SNI_COUNTER2_DIV >> 8; wmb(); |