diff options
Diffstat (limited to 'arch/sh/drivers')
| -rw-r--r-- | arch/sh/drivers/Makefile | 1 | ||||
| -rw-r--r-- | arch/sh/drivers/dma/Kconfig | 17 | ||||
| -rw-r--r-- | arch/sh/drivers/dma/dma-api.c | 2 | ||||
| -rw-r--r-- | arch/sh/drivers/dma/dma-pvr2.c | 9 | ||||
| -rw-r--r-- | arch/sh/drivers/dma/dma-sh.c | 37 | ||||
| -rw-r--r-- | arch/sh/drivers/dma/dma-sysfs.c | 10 | ||||
| -rw-r--r-- | arch/sh/drivers/heartbeat.c | 2 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/Makefile | 2 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/common.c | 17 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/fixups-cayman.c | 78 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/fixups-dreamcast.c | 2 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/ops-sh5.c | 65 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/pci-sh5.c | 217 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/pci-sh5.h | 108 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/pci-sh7780.c | 23 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/pci.c | 12 | ||||
| -rw-r--r-- | arch/sh/drivers/pci/pcie-sh7786.c | 22 | ||||
| -rw-r--r-- | arch/sh/drivers/platform_early.c | 13 | ||||
| -rw-r--r-- | arch/sh/drivers/push-switch.c | 2 | ||||
| -rw-r--r-- | arch/sh/drivers/superhyway/Makefile | 7 | ||||
| -rw-r--r-- | arch/sh/drivers/superhyway/ops-sh4-202.c | 168 |
21 files changed, 87 insertions, 727 deletions
diff --git a/arch/sh/drivers/Makefile b/arch/sh/drivers/Makefile index 56b0acace6e7..8bd10b904bf9 100644 --- a/arch/sh/drivers/Makefile +++ b/arch/sh/drivers/Makefile @@ -6,6 +6,5 @@ obj-y += dma/ platform_early.o obj-$(CONFIG_PCI) += pci/ -obj-$(CONFIG_SUPERHYWAY) += superhyway/ obj-$(CONFIG_PUSH_SWITCH) += push-switch.o obj-$(CONFIG_HEARTBEAT) += heartbeat.o diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig index d0de378beefe..08d937a6d249 100644 --- a/arch/sh/drivers/dma/Kconfig +++ b/arch/sh/drivers/dma/Kconfig @@ -28,17 +28,19 @@ config SH_DMA_API config NR_ONCHIP_DMA_CHANNELS int depends on SH_DMA - default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \ - CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7091 + default "4" if CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750 || \ + CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7751 || \ + CPU_SUBTYPE_SH7091 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \ CPU_SUBTYPE_SH7760 - default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || \ - CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7724 + default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7724 || \ + CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 default "6" help This allows you to specify the number of channels that the on-chip - DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the - SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6. + DMAC supports. This will be 4 for SH7709/SH7750/SH7750S/SH7751/SH7091, + 8 for SH7750R/SH7751R/SH7760, and 12 for SH7723/SH7724/SH7780/SH7785. + Default is 6. config SH_DMABRG bool "SH7760 DMABRG support" @@ -63,8 +65,7 @@ config PVR2_DMA config G2_DMA tristate "G2 Bus DMA support" - depends on SH_DREAMCAST - select SH_DMA_API + depends on SH_DREAMCAST && SH_DMA_API help This enables support for the DMA controller for the Dreamcast's G2 bus. Drivers that want this will generally enable this on diff --git a/arch/sh/drivers/dma/dma-api.c b/arch/sh/drivers/dma/dma-api.c index ab9170494dcc..89cd4a3b4cca 100644 --- a/arch/sh/drivers/dma/dma-api.c +++ b/arch/sh/drivers/dma/dma-api.c @@ -198,7 +198,7 @@ int request_dma(unsigned int chan, const char *dev_id) if (atomic_xchg(&channel->busy, 1)) return -EBUSY; - strlcpy(channel->dev_id, dev_id, sizeof(channel->dev_id)); + strscpy(channel->dev_id, dev_id, sizeof(channel->dev_id)); if (info->ops->request) { result = info->ops->request(channel); diff --git a/arch/sh/drivers/dma/dma-pvr2.c b/arch/sh/drivers/dma/dma-pvr2.c index b5dbd1f75768..21c347543e19 100644 --- a/arch/sh/drivers/dma/dma-pvr2.c +++ b/arch/sh/drivers/dma/dma-pvr2.c @@ -64,11 +64,6 @@ static int pvr2_xfer_dma(struct dma_channel *chan) return 0; } -static struct irqaction pvr2_dma_irq = { - .name = "pvr2 DMA handler", - .handler = pvr2_dma_interrupt, -}; - static struct dma_ops pvr2_dma_ops = { .request = pvr2_request_dma, .get_residue = pvr2_get_dma_residue, @@ -84,7 +79,9 @@ static struct dma_info pvr2_dma_info = { static int __init pvr2_dma_init(void) { - setup_irq(HW_EVENT_PVR2_DMA, &pvr2_dma_irq); + if (request_irq(HW_EVENT_PVR2_DMA, pvr2_dma_interrupt, 0, + "pvr2 DMA handler", NULL)) + pr_err("Failed to register pvr2 DMA handler interrupt\n"); request_dma(PVR2_CASCADE_CHAN, "pvr2 cascade"); return register_dmac(&pvr2_dma_info); diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index 96c626c2cd0a..306fba1564e5 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c @@ -19,6 +19,18 @@ #include <cpu/dma.h> /* + * Some of the SoCs feature two DMAC modules. In such a case, the channels are + * distributed equally among them. + */ +#ifdef SH_DMAC_BASE1 +#define SH_DMAC_NR_MD_CH (CONFIG_NR_ONCHIP_DMA_CHANNELS / 2) +#else +#define SH_DMAC_NR_MD_CH CONFIG_NR_ONCHIP_DMA_CHANNELS +#endif + +#define SH_DMAC_CH_SZ 0x10 + +/* * Define the default configuration for dual address memory-memory transfer. * The 0x400 value represents auto-request, external->external. */ @@ -29,7 +41,7 @@ static unsigned long dma_find_base(unsigned int chan) unsigned long base = SH_DMAC_BASE0; #ifdef SH_DMAC_BASE1 - if (chan >= 6) + if (chan >= SH_DMAC_NR_MD_CH) base = SH_DMAC_BASE1; #endif @@ -40,13 +52,13 @@ static unsigned long dma_base_addr(unsigned int chan) { unsigned long base = dma_find_base(chan); - /* Normalize offset calculation */ - if (chan >= 9) - chan -= 6; - if (chan >= 4) - base += 0x10; + chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ; + + /* DMAOR is placed inside the channel register space. Step over it. */ + if (chan >= DMAOR) + base += SH_DMAC_CH_SZ; - return base + (chan * 0x10); + return base + chan; } #ifdef CONFIG_SH_DMA_IRQ_MULTI @@ -250,12 +262,11 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan) #define NR_DMAOR 1 #endif -/* - * DMAOR bases are broken out amongst channel groups. DMAOR0 manages - * channels 0 - 5, DMAOR1 6 - 11 (optional). - */ -#define dmaor_read_reg(n) __raw_readw(dma_find_base((n)*6)) -#define dmaor_write_reg(n, data) __raw_writew(data, dma_find_base(n)*6) +#define dmaor_read_reg(n) __raw_readw(dma_find_base((n) * \ + SH_DMAC_NR_MD_CH) + DMAOR) +#define dmaor_write_reg(n, data) __raw_writew(data, \ + dma_find_base((n) * \ + SH_DMAC_NR_MD_CH) + DMAOR) static inline int dmaor_reset(int no) { diff --git a/arch/sh/drivers/dma/dma-sysfs.c b/arch/sh/drivers/dma/dma-sysfs.c index 8ef318150f84..9f666280d80c 100644 --- a/arch/sh/drivers/dma/dma-sysfs.c +++ b/arch/sh/drivers/dma/dma-sysfs.c @@ -15,7 +15,7 @@ #include <linux/string.h> #include <asm/dma.h> -static struct bus_type dma_subsys = { +static const struct bus_type dma_subsys = { .name = "dma", .dev_name = "dma", }; @@ -45,13 +45,19 @@ static DEVICE_ATTR(devices, S_IRUGO, dma_show_devices, NULL); static int __init dma_subsys_init(void) { + struct device *dev_root; int ret; ret = subsys_system_register(&dma_subsys, NULL); if (unlikely(ret)) return ret; - return device_create_file(dma_subsys.dev_root, &dev_attr_devices); + dev_root = bus_get_dev_root(&dma_subsys); + if (dev_root) { + ret = device_create_file(dev_root, &dev_attr_devices); + put_device(dev_root); + } + return ret; } postcore_initcall(dma_subsys_init); diff --git a/arch/sh/drivers/heartbeat.c b/arch/sh/drivers/heartbeat.c index cf2fcccca812..24391b444b28 100644 --- a/arch/sh/drivers/heartbeat.c +++ b/arch/sh/drivers/heartbeat.c @@ -96,7 +96,7 @@ static int heartbeat_drv_probe(struct platform_device *pdev) return -ENOMEM; } - hd->base = ioremap_nocache(res->start, resource_size(res)); + hd->base = ioremap(res->start, resource_size(res)); if (unlikely(!hd->base)) { dev_err(&pdev->dev, "ioremap failed\n"); diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile index 947bfe8bb0a7..d313fd3ce709 100644 --- a/arch/sh/drivers/pci/Makefile +++ b/arch/sh/drivers/pci/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7786) += pcie-sh7786.o ops-sh7786.o -obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ pci-dreamcast.o @@ -26,4 +25,3 @@ obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += fixups-sdk7780.o obj-$(CONFIG_SH_TITAN) += fixups-titan.o obj-$(CONFIG_SH_LANDISK) += fixups-landisk.o obj-$(CONFIG_SH_LBOX_RE2) += fixups-rts7751r2d.o -obj-$(CONFIG_SH_CAYMAN) += fixups-cayman.o diff --git a/arch/sh/drivers/pci/common.c b/arch/sh/drivers/pci/common.c index fe163ecd0719..ab9e791070b4 100644 --- a/arch/sh/drivers/pci/common.c +++ b/arch/sh/drivers/pci/common.c @@ -50,20 +50,21 @@ int __init pci_is_66mhz_capable(struct pci_channel *hose, int top_bus, int current_bus) { u32 pci_devfn; - unsigned short vid; + u16 vid; int cap66 = -1; u16 stat; + int ret; - printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n"); + pr_info("PCI: Checking 66MHz capabilities...\n"); for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) { if (PCI_FUNC(pci_devfn)) continue; - if (early_read_config_word(hose, top_bus, current_bus, - pci_devfn, PCI_VENDOR_ID, &vid) != - PCIBIOS_SUCCESSFUL) + ret = early_read_config_word(hose, top_bus, current_bus, + pci_devfn, PCI_VENDOR_ID, &vid); + if (ret != PCIBIOS_SUCCESSFUL) continue; - if (vid == 0xffff) + if (PCI_POSSIBLE_ERROR(vid)) continue; /* check 66MHz capability */ @@ -134,7 +135,7 @@ unsigned int pcibios_handle_status_errors(unsigned long addr, pcibios_report_status(PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT, 1); - printk("\n"); + pr_cont("\n"); cmd |= PCI_STATUS_REC_TARGET_ABORT; } @@ -143,7 +144,7 @@ unsigned int pcibios_handle_status_errors(unsigned long addr, printk(KERN_DEBUG "PCI: parity error detected: "); pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1); - printk("\n"); + pr_cont("\n"); cmd |= PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY; diff --git a/arch/sh/drivers/pci/fixups-cayman.c b/arch/sh/drivers/pci/fixups-cayman.c deleted file mode 100644 index c797bfbe2e98..000000000000 --- a/arch/sh/drivers/pci/fixups-cayman.c +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/types.h> -#include <cpu/irq.h> -#include "pci-sh5.h" - -int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int result = -1; - - /* The complication here is that the PCI IRQ lines from the Cayman's 2 - 5V slots get into the CPU via a different path from the IRQ lines - from the 3 3.3V slots. Thus, we have to detect whether the card's - interrupts go via the 5V or 3.3V path, i.e. the 'bridge swizzling' - at the point where we cross from 5V to 3.3V is not the normal case. - - The added complication is that we don't know that the 5V slots are - always bus 2, because a card containing a PCI-PCI bridge may be - plugged into a 3.3V slot, and this changes the bus numbering. - - Also, the Cayman has an intermediate PCI bus that goes a custom - expansion board header (and to the secondary bridge). This bus has - never been used in practice. - - The 1ary onboard PCI-PCI bridge is device 3 on bus 0 - The 2ary onboard PCI-PCI bridge is device 0 on the 2ary bus of - the 1ary bridge. - */ - - struct slot_pin { - int slot; - int pin; - } path[4]; - int i=0; - - while (dev->bus->number > 0) { - - slot = path[i].slot = PCI_SLOT(dev->devfn); - pin = path[i].pin = pci_swizzle_interrupt_pin(dev, pin); - dev = dev->bus->self; - i++; - if (i > 3) panic("PCI path to root bus too long!\n"); - } - - slot = PCI_SLOT(dev->devfn); - /* This is the slot on bus 0 through which the device is eventually - reachable. */ - - /* Now work back up. */ - if ((slot < 3) || (i == 0)) { - /* Bus 0 (incl. PCI-PCI bridge itself) : perform the final - swizzle now. */ - result = IRQ_INTA + pci_swizzle_interrupt_pin(dev, pin) - 1; - } else { - i--; - slot = path[i].slot; - pin = path[i].pin; - if (slot > 0) { - panic("PCI expansion bus device found - not handled!\n"); - } else { - if (i > 0) { - /* 5V slots */ - i--; - slot = path[i].slot; - pin = path[i].pin; - /* 'pin' was swizzled earlier wrt slot, don't do it again. */ - result = IRQ_P2INTA + (pin - 1); - } else { - /* IRQ for 2ary PCI-PCI bridge : unused */ - result = -1; - } - } - } - - return result; -} diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c index 7be8694c0d13..41e4daee8f04 100644 --- a/arch/sh/drivers/pci/fixups-dreamcast.c +++ b/arch/sh/drivers/pci/fixups-dreamcast.c @@ -19,7 +19,7 @@ #include <linux/init.h> #include <linux/irq.h> #include <linux/pci.h> -#include <linux/dma-mapping.h> +#include <linux/dma-map-ops.h> #include <asm/io.h> #include <asm/irq.h> diff --git a/arch/sh/drivers/pci/ops-sh5.c b/arch/sh/drivers/pci/ops-sh5.c deleted file mode 100644 index 9fbaf72949ab..000000000000 --- a/arch/sh/drivers/pci/ops-sh5.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Support functions for the SH5 PCI hardware. - * - * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) - * Copyright (C) 2003, 2004 Paul Mundt - * Copyright (C) 2004 Richard Curnow - */ -#include <linux/kernel.h> -#include <linux/rwsem.h> -#include <linux/smp.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/pci.h> -#include <linux/delay.h> -#include <linux/types.h> -#include <linux/irq.h> -#include <asm/io.h> -#include "pci-sh5.h" - -static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *val) -{ - SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); - - switch (size) { - case 1: - *val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3)); - break; - case 2: - *val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2)); - break; - case 4: - *val = SH5PCI_READ(PDR); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 val) -{ - SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where)); - - switch (size) { - case 1: - SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val); - break; - case 2: - SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val); - break; - case 4: - SH5PCI_WRITE(PDR, val); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops sh5_pci_ops = { - .read = sh5pci_read, - .write = sh5pci_write, -}; diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c deleted file mode 100644 index 49303fab187b..000000000000 --- a/arch/sh/drivers/pci/pci-sh5.c +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) - * Copyright (C) 2003, 2004 Paul Mundt - * Copyright (C) 2004 Richard Curnow - * - * Support functions for the SH5 PCI hardware. - */ - -#include <linux/kernel.h> -#include <linux/rwsem.h> -#include <linux/smp.h> -#include <linux/interrupt.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/pci.h> -#include <linux/delay.h> -#include <linux/types.h> -#include <linux/irq.h> -#include <cpu/irq.h> -#include <asm/io.h> -#include "pci-sh5.h" - -unsigned long pcicr_virt; -unsigned long PCI_IO_AREA; - -/* Rounds a number UP to the nearest power of two. Used for - * sizing the PCI window. - */ -static u32 __init r2p2(u32 num) -{ - int i = 31; - u32 tmp = num; - - if (num == 0) - return 0; - - do { - if (tmp & (1 << 31)) - break; - i--; - tmp <<= 1; - } while (i >= 0); - - tmp = 1 << i; - /* If the original number isn't a power of 2, round it up */ - if (tmp != num) - tmp <<= 1; - - return tmp; -} - -static irqreturn_t pcish5_err_irq(int irq, void *dev_id) -{ - struct pt_regs *regs = get_irq_regs(); - unsigned pci_int, pci_air, pci_cir, pci_aint; - - pci_int = SH5PCI_READ(INT); - pci_cir = SH5PCI_READ(CIR); - pci_air = SH5PCI_READ(AIR); - - if (pci_int) { - printk("PCI INTERRUPT (at %08llx)!\n", regs->pc); - printk("PCI INT -> 0x%x\n", pci_int & 0xffff); - printk("PCI AIR -> 0x%x\n", pci_air); - printk("PCI CIR -> 0x%x\n", pci_cir); - SH5PCI_WRITE(INT, ~0); - } - - pci_aint = SH5PCI_READ(AINT); - if (pci_aint) { - printk("PCI ARB INTERRUPT!\n"); - printk("PCI AINT -> 0x%x\n", pci_aint); - printk("PCI AIR -> 0x%x\n", pci_air); - printk("PCI CIR -> 0x%x\n", pci_cir); - SH5PCI_WRITE(AINT, ~0); - } - - return IRQ_HANDLED; -} - -static irqreturn_t pcish5_serr_irq(int irq, void *dev_id) -{ - printk("SERR IRQ\n"); - - return IRQ_NONE; -} - -static struct resource sh5_pci_resources[2]; - -static struct pci_channel sh5pci_controller = { - .pci_ops = &sh5_pci_ops, - .resources = sh5_pci_resources, - .nr_resources = ARRAY_SIZE(sh5_pci_resources), - .mem_offset = 0x00000000, - .io_offset = 0x00000000, -}; - -static int __init sh5pci_init(void) -{ - unsigned long memStart = __pa(memory_start); - unsigned long memSize = __pa(memory_end) - memStart; - u32 lsr0; - u32 uval; - - if (request_irq(IRQ_ERR, pcish5_err_irq, - 0, "PCI Error",NULL) < 0) { - printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n"); - return -EINVAL; - } - - if (request_irq(IRQ_SERR, pcish5_serr_irq, - 0, "PCI SERR interrupt", NULL) < 0) { - printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n"); - return -EINVAL; - } - - pcicr_virt = (unsigned long)ioremap_nocache(SH5PCI_ICR_BASE, 1024); - if (!pcicr_virt) { - panic("Unable to remap PCICR\n"); - } - - PCI_IO_AREA = (unsigned long)ioremap_nocache(SH5PCI_IO_BASE, 0x10000); - if (!PCI_IO_AREA) { - panic("Unable to remap PCIIO\n"); - } - - /* Clear snoop registers */ - SH5PCI_WRITE(CSCR0, 0); - SH5PCI_WRITE(CSCR1, 0); - - /* Switch off interrupts */ - SH5PCI_WRITE(INTM, 0); - SH5PCI_WRITE(AINTM, 0); - SH5PCI_WRITE(PINTM, 0); - - /* Set bus active, take it out of reset */ - uval = SH5PCI_READ(CR); - - /* Set command Register */ - SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE | - CR_PFCS | CR_BMAM); - - uval=SH5PCI_READ(CR); - - /* Allow it to be a master */ - /* NB - WE DISABLE I/O ACCESS to stop overlap */ - /* set WAIT bit to enable stepping, an attempt to improve stability */ - SH5PCI_WRITE_SHORT(CSR_CMD, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | - PCI_COMMAND_WAIT); - - /* - ** Set translation mapping memory in order to convert the address - ** used for the main bus, to the PCI internal address. - */ - SH5PCI_WRITE(MBR,0x40000000); - - /* Always set the max size 512M */ - SH5PCI_WRITE(MBMR, PCISH5_MEM_SIZCONV(512*1024*1024)); - - /* - ** I/O addresses are mapped at internal PCI specific address - ** as is described into the configuration bridge table. - ** These are changed to 0, to allow cards that have legacy - ** io such as vga to function correctly. We set the SH5 IOBAR to - ** 256K, which is a bit big as we can only have 64K of address space - */ - - SH5PCI_WRITE(IOBR,0x0); - - /* Set up a 256K window. Totally pointless waste of address space */ - SH5PCI_WRITE(IOBMR,0); - - /* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec. - * Ideally, we would want to map the I/O region somewhere, but it - * is so big this is not that easy! - */ - SH5PCI_WRITE(CSR_IBAR0,~0); - /* Set memory size value */ - memSize = memory_end - memory_start; - - /* Now we set up the mbars so the PCI bus can see the memory of - * the machine */ - if (memSize < (1024 * 1024)) { - printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%lx?\n", - memSize); - return -EINVAL; - } - - /* Set LSR 0 */ - lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 : - ((r2p2(memSize) - 0x100000) | 0x1); - SH5PCI_WRITE(LSR0, lsr0); - - /* Set MBAR 0 */ - SH5PCI_WRITE(CSR_MBAR0, memory_start); - SH5PCI_WRITE(LAR0, memory_start); - - SH5PCI_WRITE(CSR_MBAR1,0); - SH5PCI_WRITE(LAR1,0); - SH5PCI_WRITE(LSR1,0); - - /* Enable the PCI interrupts on the device */ - SH5PCI_WRITE(INTM, ~0); - SH5PCI_WRITE(AINTM, ~0); - SH5PCI_WRITE(PINTM, ~0); - - sh5_pci_resources[0].start = PCI_IO_AREA; - sh5_pci_resources[0].end = PCI_IO_AREA + 0x10000; - - sh5_pci_resources[1].start = memStart; - sh5_pci_resources[1].end = memStart + memSize; - - return register_pci_controller(&sh5pci_controller); -} -arch_initcall(sh5pci_init); diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h deleted file mode 100644 index 91348af0ef6c..000000000000 --- a/arch/sh/drivers/pci/pci-sh5.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) - * - * Definitions for the SH5 PCI hardware. - */ -#ifndef __PCI_SH5_H -#define __PCI_SH5_H - -/* Product ID */ -#define PCISH5_PID 0x350d - -/* vendor ID */ -#define PCISH5_VID 0x1054 - -/* Configuration types */ -#define ST_TYPE0 0x00 /* Configuration cycle type 0 */ -#define ST_TYPE1 0x01 /* Configuration cycle type 1 */ - -/* VCR data */ -#define PCISH5_VCR_STATUS 0x00 -#define PCISH5_VCR_VERSION 0x08 - -/* -** ICR register offsets and bits -*/ -#define PCISH5_ICR_CR 0x100 /* PCI control register values */ -#define CR_PBAM (1<<12) -#define CR_PFCS (1<<11) -#define CR_FTO (1<<10) -#define CR_PFE (1<<9) -#define CR_TBS (1<<8) -#define CR_SPUE (1<<7) -#define CR_BMAM (1<<6) -#define CR_HOST (1<<5) -#define CR_CLKEN (1<<4) -#define CR_SOCS (1<<3) -#define CR_IOCS (1<<2) -#define CR_RSTCTL (1<<1) -#define CR_CFINT (1<<0) -#define CR_LOCK_MASK 0xa5000000 - -#define PCISH5_ICR_INT 0x114 /* Interrupt registert values */ -#define INT_MADIM (1<<2) - -#define PCISH5_ICR_LSR0 0X104 /* Local space register values */ -#define PCISH5_ICR_LSR1 0X108 /* Local space register values */ -#define PCISH5_ICR_LAR0 0x10c /* Local address register values */ -#define PCISH5_ICR_LAR1 0x110 /* Local address register values */ -#define PCISH5_ICR_INTM 0x118 /* Interrupt mask register values */ -#define PCISH5_ICR_AIR 0x11c /* Interrupt error address information register values */ -#define PCISH5_ICR_CIR 0x120 /* Interrupt error command information register values */ -#define PCISH5_ICR_AINT 0x130 /* Interrupt error arbiter interrupt register values */ -#define PCISH5_ICR_AINTM 0x134 /* Interrupt error arbiter interrupt mask register values */ -#define PCISH5_ICR_BMIR 0x138 /* Interrupt error info register of bus master values */ -#define PCISH5_ICR_PAR 0x1c0 /* Pio address register values */ -#define PCISH5_ICR_MBR 0x1c4 /* Memory space bank register values */ -#define PCISH5_ICR_IOBR 0x1c8 /* I/O space bank register values */ -#define PCISH5_ICR_PINT 0x1cc /* power management interrupt register values */ -#define PCISH5_ICR_PINTM 0x1d0 /* power management interrupt mask register values */ -#define PCISH5_ICR_MBMR 0x1d8 /* memory space bank mask register values */ -#define PCISH5_ICR_IOBMR 0x1dc /* I/O space bank mask register values */ -#define PCISH5_ICR_CSCR0 0x210 /* PCI cache snoop control register 0 */ -#define PCISH5_ICR_CSCR1 0x214 /* PCI cache snoop control register 1 */ -#define PCISH5_ICR_PDR 0x220 /* Pio data register values */ - -/* These are configs space registers */ -#define PCISH5_ICR_CSR_VID 0x000 /* Vendor id */ -#define PCISH5_ICR_CSR_DID 0x002 /* Device id */ -#define PCISH5_ICR_CSR_CMD 0x004 /* Command register */ -#define PCISH5_ICR_CSR_STATUS 0x006 /* Stautus */ -#define PCISH5_ICR_CSR_IBAR0 0x010 /* I/O base address register */ -#define PCISH5_ICR_CSR_MBAR0 0x014 /* First Memory base address register */ -#define PCISH5_ICR_CSR_MBAR1 0x018 /* Second Memory base address register */ - -/* Base address of registers */ -#define SH5PCI_ICR_BASE (PHYS_PCI_BLOCK + 0x00040000) -#define SH5PCI_IO_BASE (PHYS_PCI_BLOCK + 0x00800000) -/* #define SH5PCI_VCR_BASE (P2SEG_PCICB_BLOCK + P2SEG) */ - -extern unsigned long pcicr_virt; -/* Register selection macro */ -#define PCISH5_ICR_REG(x) ( pcicr_virt + (PCISH5_ICR_##x)) -/* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */ - -/* Write I/O functions */ -#define SH5PCI_WRITE(reg,val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg)) -#define SH5PCI_WRITE_SHORT(reg,val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg)) -#define SH5PCI_WRITE_BYTE(reg,val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg)) - -/* Read I/O functions */ -#define SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg)) -#define SH5PCI_READ_SHORT(reg) __raw_readw(PCISH5_ICR_REG(reg)) -#define SH5PCI_READ_BYTE(reg) __raw_readb(PCISH5_ICR_REG(reg)) - -/* Set PCI config bits */ -#define SET_CONFIG_BITS(bus,devfn,where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000) - -/* Set PCI command register */ -#define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where) - -/* Size converters */ -#define PCISH5_MEM_SIZCONV(x) (((x / 0x40000) - 1) << 18) -#define PCISH5_IO_SIZCONV(x) (((x / 0x40000) - 1) << 18) - -extern struct pci_ops sh5_pci_ops; - -#endif /* __PCI_SH5_H */ diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c index 287b3a68570c..9a624a6ee354 100644 --- a/arch/sh/drivers/pci/pci-sh7780.c +++ b/arch/sh/drivers/pci/pci-sh7780.c @@ -148,7 +148,7 @@ static irqreturn_t sh7780_pci_serr_irq(int irq, void *dev_id) printk(KERN_DEBUG "PCI: system error received: "); pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1); - printk("\n"); + pr_cont("\n"); /* Deassert SERR */ __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); @@ -179,7 +179,7 @@ static int __init sh7780_pci_setup_irqs(struct pci_channel *hose) ret = request_irq(hose->serr_irq, sh7780_pci_serr_irq, 0, "PCI SERR interrupt", hose); if (unlikely(ret)) { - printk(KERN_ERR "PCI: Failed hooking SERR IRQ\n"); + pr_err("PCI: Failed hooking SERR IRQ\n"); return ret; } @@ -250,7 +250,7 @@ static int __init sh7780_pci_init(void) const char *type; int ret, i; - printk(KERN_NOTICE "PCI: Starting initialization.\n"); + pr_notice("PCI: Starting initialization.\n"); chan->reg_base = 0xfe040000; @@ -270,7 +270,7 @@ static int __init sh7780_pci_init(void) id = __raw_readw(chan->reg_base + PCI_VENDOR_ID); if (id != PCI_VENDOR_ID_RENESAS) { - printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id); + pr_err("PCI: Unknown vendor ID 0x%04x.\n", id); return -ENODEV; } @@ -281,14 +281,13 @@ static int __init sh7780_pci_init(void) (id == PCI_DEVICE_ID_RENESAS_SH7785) ? "SH7785" : NULL; if (unlikely(!type)) { - printk(KERN_ERR "PCI: Found an unsupported Renesas host " - "controller, device id 0x%04x.\n", id); + pr_err("PCI: Found an unsupported Renesas host controller, device id 0x%04x.\n", + id); return -EINVAL; } - printk(KERN_NOTICE "PCI: Found a Renesas %s host " - "controller, revision %d.\n", type, - __raw_readb(chan->reg_base + PCI_REVISION_ID)); + pr_notice("PCI: Found a Renesas %s host controller, revision %d.\n", + type, __raw_readb(chan->reg_base + PCI_REVISION_ID)); /* * Now throw it in to register initialization mode and @@ -395,9 +394,9 @@ static int __init sh7780_pci_init(void) sh7780_pci66_init(chan); - printk(KERN_NOTICE "PCI: Running at %dMHz.\n", - (__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) ? - 66 : 33); + pr_notice("PCI: Running at %dMHz.\n", + (__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) + ? 66 : 33); return 0; diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index c7784e156964..a3903304f33f 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -13,7 +13,6 @@ #include <linux/pci.h> #include <linux/init.h> #include <linux/types.h> -#include <linux/dma-debug.h> #include <linux/io.h> #include <linux/mutex.h> #include <linux/spinlock.h> @@ -120,8 +119,7 @@ int register_pci_controller(struct pci_channel *hose) * Do not panic here but later - this might happen before console init. */ if (!hose->io_map_base) { - printk(KERN_WARNING - "registering PCI controller with io_map_base unset\n"); + pr_warn("registering PCI controller with io_map_base unset\n"); } /* @@ -145,7 +143,7 @@ out: for (--i; i >= 0; i--) release_resource(&hose->resources[i]); - printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n"); + pr_warn("Skipping PCI bus scan due to resource conflict\n"); return -1; } @@ -213,8 +211,8 @@ pcibios_bus_report_status_early(struct pci_channel *hose, pci_devfn, PCI_STATUS, status & status_mask); if (warn) - printk("(%02x:%02x: %04X) ", current_bus, - pci_devfn, status); + pr_cont("(%02x:%02x: %04X) ", current_bus, pci_devfn, + status); } } @@ -249,7 +247,7 @@ pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask, pci_write_config_word(dev, PCI_STATUS, status & status_mask); if (warn) - printk("(%s: %04X) ", pci_name(dev), status); + pr_cont("(%s: %04X) ", pci_name(dev), status); } list_for_each_entry(dev, &bus->devices, bus_list) diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index e0b568aaa701..a78b9a935585 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -12,6 +12,7 @@ #include <linux/io.h> #include <linux/async.h> #include <linux/delay.h> +#include <linux/dma-map-ops.h> #include <linux/slab.h> #include <linux/clk.h> #include <linux/sh_clk.h> @@ -30,7 +31,8 @@ struct sh7786_pcie_port { static struct sh7786_pcie_port *sh7786_pcie_ports; static unsigned int nr_ports; -static unsigned long dma_pfn_offset; +size_t memsize; +u64 memstart; static struct sh7786_pcie_hwops { int (*core_init)(void); @@ -137,12 +139,12 @@ static void sh7786_pci_fixup(struct pci_dev *dev) * Prevent enumeration of root complex resources. */ if (pci_is_root_bus(dev->bus) && dev->devfn == 0) { - int i; + struct resource *r; - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; + pci_dev_for_each_resource(dev, r) { + r->start = 0; + r->end = 0; + r->flags = 0; } } } @@ -301,7 +303,6 @@ static int __init pcie_init(struct sh7786_pcie_port *port) struct pci_channel *chan = port->hose; unsigned int data; phys_addr_t memstart, memend; - size_t memsize; int ret, i, win; /* Begin initialization */ @@ -312,7 +313,7 @@ static int __init pcie_init(struct sh7786_pcie_port *port) * class to match. Hardware takes care of propagating the IDSETR * settings, so there is no need to bother with a quirk. */ - pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1); + pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, SH4A_PCIEIDSETR1); /* Initialize default capabilities. */ data = pci_read_reg(chan, SH4A_PCIEEXPCAP0); @@ -368,8 +369,6 @@ static int __init pcie_init(struct sh7786_pcie_port *port) memstart = ALIGN_DOWN(memstart, memsize); memsize = roundup_pow_of_two(memend - memstart); - dma_pfn_offset = memstart >> PAGE_SHIFT; - /* * If there's more than 512MB of memory, we need to roll over to * LAR1/LAMR1. @@ -487,7 +486,8 @@ int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin) void pcibios_bus_add_device(struct pci_dev *pdev) { - pdev->dev.dma_pfn_offset = dma_pfn_offset; + dma_direct_set_offset(&pdev->dev, __pa(memory_start), + __pa(memory_start) - memstart, memsize); } static int __init sh7786_pcie_core_init(void) diff --git a/arch/sh/drivers/platform_early.c b/arch/sh/drivers/platform_early.c index f6d148451dfc..143747c45206 100644 --- a/arch/sh/drivers/platform_early.c +++ b/arch/sh/drivers/platform_early.c @@ -246,7 +246,7 @@ static int __init sh_early_platform_driver_probe_id(char *class_str, case EARLY_PLATFORM_ID_ERROR: pr_warn("%s: unable to parse %s parameter\n", class_str, epdrv->pdrv->driver.name); - /* fall-through */ + fallthrough; case EARLY_PLATFORM_ID_UNSET: match = NULL; break; @@ -325,9 +325,9 @@ int __init sh_early_platform_driver_probe(char *class_str, } /** - * sh_early_platform_cleanup - clean up early platform code + * early_platform_cleanup - clean up early platform code */ -static int __init sh_early_platform_cleanup(void) +void __init early_platform_cleanup(void) { struct platform_device *pd, *pd2; @@ -337,11 +337,4 @@ static int __init sh_early_platform_cleanup(void) list_del(&pd->dev.devres_head); memset(&pd->dev.devres_head, 0, sizeof(pd->dev.devres_head)); } - - return 0; } -/* - * This must happen once after all early devices are probed but before probing - * real platform devices. - */ -subsys_initcall(sh_early_platform_cleanup); diff --git a/arch/sh/drivers/push-switch.c b/arch/sh/drivers/push-switch.c index 2813140fd92b..6ecba5f521eb 100644 --- a/arch/sh/drivers/push-switch.c +++ b/arch/sh/drivers/push-switch.c @@ -101,8 +101,8 @@ static int switch_drv_remove(struct platform_device *pdev) device_remove_file(&pdev->dev, &dev_attr_switch); platform_set_drvdata(pdev, NULL); + timer_shutdown_sync(&psw->debounce); flush_work(&psw->work); - del_timer_sync(&psw->debounce); free_irq(irq, pdev); kfree(psw); diff --git a/arch/sh/drivers/superhyway/Makefile b/arch/sh/drivers/superhyway/Makefile deleted file mode 100644 index aa6e3267c055..000000000000 --- a/arch/sh/drivers/superhyway/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the SuperHyway specific kernel interface routines under Linux. -# - -obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += ops-sh4-202.o - diff --git a/arch/sh/drivers/superhyway/ops-sh4-202.c b/arch/sh/drivers/superhyway/ops-sh4-202.c deleted file mode 100644 index 490142274e3b..000000000000 --- a/arch/sh/drivers/superhyway/ops-sh4-202.c +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * arch/sh/drivers/superhyway/ops-sh4-202.c - * - * SuperHyway bus support for SH4-202 - * - * Copyright (C) 2005 Paul Mundt - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/superhyway.h> -#include <linux/string.h> -#include <asm/addrspace.h> -#include <asm/io.h> - -#define PHYS_EMI_CBLOCK P4SEGADDR(0x1ec00000) -#define PHYS_EMI_DBLOCK P4SEGADDR(0x08000000) -#define PHYS_FEMI_CBLOCK P4SEGADDR(0x1f800000) -#define PHYS_FEMI_DBLOCK P4SEGADDR(0x00000000) - -#define PHYS_EPBR_BLOCK P4SEGADDR(0x1de00000) -#define PHYS_DMAC_BLOCK P4SEGADDR(0x1fa00000) -#define PHYS_PBR_BLOCK P4SEGADDR(0x1fc00000) - -static struct resource emi_resources[] = { - [0] = { - .start = PHYS_EMI_CBLOCK, - .end = PHYS_EMI_CBLOCK + 0x00300000 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = PHYS_EMI_DBLOCK, - .end = PHYS_EMI_DBLOCK + 0x08000000 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct superhyway_device emi_device = { - .name = "emi", - .num_resources = ARRAY_SIZE(emi_resources), - .resource = emi_resources, -}; - -static struct resource femi_resources[] = { - [0] = { - .start = PHYS_FEMI_CBLOCK, - .end = PHYS_FEMI_CBLOCK + 0x00100000 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = PHYS_FEMI_DBLOCK, - .end = PHYS_FEMI_DBLOCK + 0x08000000 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct superhyway_device femi_device = { - .name = "femi", - .num_resources = ARRAY_SIZE(femi_resources), - .resource = femi_resources, -}; - -static struct resource epbr_resources[] = { - [0] = { - .start = P4SEGADDR(0x1e7ffff8), - .end = P4SEGADDR(0x1e7ffff8 + (sizeof(u32) * 2) - 1), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = PHYS_EPBR_BLOCK, - .end = PHYS_EPBR_BLOCK + 0x00a00000 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct superhyway_device epbr_device = { - .name = "epbr", - .num_resources = ARRAY_SIZE(epbr_resources), - .resource = epbr_resources, -}; - -static struct resource dmac_resource = { - .start = PHYS_DMAC_BLOCK, - .end = PHYS_DMAC_BLOCK + 0x00100000 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct superhyway_device dmac_device = { - .name = "dmac", - .num_resources = 1, - .resource = &dmac_resource, -}; - -static struct resource pbr_resources[] = { - [0] = { - .start = P4SEGADDR(0x1ffffff8), - .end = P4SEGADDR(0x1ffffff8 + (sizeof(u32) * 2) - 1), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = PHYS_PBR_BLOCK, - .end = PHYS_PBR_BLOCK + 0x00400000 - (sizeof(u32) * 2) - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct superhyway_device pbr_device = { - .name = "pbr", - .num_resources = ARRAY_SIZE(pbr_resources), - .resource = pbr_resources, -}; - -static struct superhyway_device *sh4202_devices[] __initdata = { - &emi_device, &femi_device, &epbr_device, &dmac_device, &pbr_device, -}; - -static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr) -{ - u32 vcrh, vcrl; - u64 tmp; - - /* - * XXX: Even though the SH4-202 Evaluation Device documentation - * indicates that VCRL is mapped first with VCRH at a + 0x04 - * offset, the opposite seems to be true. - * - * Some modules (PBR and ePBR for instance) also appear to have - * VCRL/VCRH flipped in the documentation, but on the SH4-202 - * itself it appears that these are all consistently mapped with - * VCRH preceding VCRL. - * - * Do not trust the documentation, for it is evil. - */ - vcrh = __raw_readl(base); - vcrl = __raw_readl(base + sizeof(u32)); - - tmp = ((u64)vcrh << 32) | vcrl; - memcpy(vcr, &tmp, sizeof(u64)); - - return 0; -} - -static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr) -{ - u64 tmp = *(u64 *)&vcr; - - __raw_writel((tmp >> 32) & 0xffffffff, base); - __raw_writel(tmp & 0xffffffff, base + sizeof(u32)); - - return 0; -} - -static struct superhyway_ops sh4202_superhyway_ops = { - .read_vcr = sh4202_read_vcr, - .write_vcr = sh4202_write_vcr, -}; - -struct superhyway_bus superhyway_channels[] = { - { &sh4202_superhyway_ops, }, - { 0, }, -}; - -int __init superhyway_scan_bus(struct superhyway_bus *bus) -{ - return superhyway_add_devices(bus, sh4202_devices, - ARRAY_SIZE(sh4202_devices)); -} - |