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-rw-r--r--arch/tile/include/uapi/arch/abi.h101
-rw-r--r--arch/tile/include/uapi/arch/chip.h22
-rw-r--r--arch/tile/include/uapi/arch/chip_tilegx.h259
-rw-r--r--arch/tile/include/uapi/arch/chip_tilepro.h259
-rw-r--r--arch/tile/include/uapi/arch/icache.h94
-rw-r--r--arch/tile/include/uapi/arch/interrupts.h20
-rw-r--r--arch/tile/include/uapi/arch/interrupts_32.h310
-rw-r--r--arch/tile/include/uapi/arch/interrupts_64.h279
-rw-r--r--arch/tile/include/uapi/arch/intreg.h71
-rw-r--r--arch/tile/include/uapi/arch/opcode.h22
-rw-r--r--arch/tile/include/uapi/arch/opcode_tilegx.h1407
-rw-r--r--arch/tile/include/uapi/arch/opcode_tilepro.h1473
-rw-r--r--arch/tile/include/uapi/arch/sim.h644
-rw-r--r--arch/tile/include/uapi/arch/sim_def.h506
-rw-r--r--arch/tile/include/uapi/arch/spr_def.h27
-rw-r--r--arch/tile/include/uapi/arch/spr_def_32.h256
-rw-r--r--arch/tile/include/uapi/arch/spr_def_64.h217
-rw-r--r--arch/tile/include/uapi/asm/Kbuild24
-rw-r--r--arch/tile/include/uapi/asm/auxvec.h24
-rw-r--r--arch/tile/include/uapi/asm/bitsperlong.h27
-rw-r--r--arch/tile/include/uapi/asm/byteorder.h20
-rw-r--r--arch/tile/include/uapi/asm/cachectl.h43
-rw-r--r--arch/tile/include/uapi/asm/hardwall.h52
-rw-r--r--arch/tile/include/uapi/asm/kvm_para.h2
-rw-r--r--arch/tile/include/uapi/asm/mman.h43
-rw-r--r--arch/tile/include/uapi/asm/ptrace.h99
-rw-r--r--arch/tile/include/uapi/asm/setup.h22
-rw-r--r--arch/tile/include/uapi/asm/sigcontext.h44
-rw-r--r--arch/tile/include/uapi/asm/siginfo.h27
-rw-r--r--arch/tile/include/uapi/asm/signal.h28
-rw-r--r--arch/tile/include/uapi/asm/stat.h5
-rw-r--r--arch/tile/include/uapi/asm/swab.h24
-rw-r--r--arch/tile/include/uapi/asm/unistd.h38
33 files changed, 0 insertions, 6489 deletions
diff --git a/arch/tile/include/uapi/arch/abi.h b/arch/tile/include/uapi/arch/abi.h
deleted file mode 100644
index df161a484730..000000000000
--- a/arch/tile/include/uapi/arch/abi.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file
- *
- * ABI-related register definitions.
- */
-
-#ifndef __ARCH_ABI_H__
-
-#ifndef __tile__ /* support uncommon use of arch headers in non-tile builds */
-# include <arch/chip.h>
-# define __INT_REG_BITS CHIP_WORD_SIZE()
-#endif
-
-#include <arch/intreg.h>
-
-/* __need_int_reg_t is deprecated: just include <arch/intreg.h> */
-#ifndef __need_int_reg_t
-
-#define __ARCH_ABI_H__
-
-#ifndef __ASSEMBLER__
-/** Unsigned type that can hold a register. */
-typedef __uint_reg_t uint_reg_t;
-
-/** Signed type that can hold a register. */
-typedef __int_reg_t int_reg_t;
-#endif
-
-/** String prefix to use for printf(). */
-#define INT_REG_FMT __INT_REG_FMT
-
-/** Number of bits in a register. */
-#define INT_REG_BITS __INT_REG_BITS
-
-
-/* Registers 0 - 55 are "normal", but some perform special roles. */
-
-#define TREG_FP 52 /**< Frame pointer. */
-#define TREG_TP 53 /**< Thread pointer. */
-#define TREG_SP 54 /**< Stack pointer. */
-#define TREG_LR 55 /**< Link to calling function PC. */
-
-/** Index of last normal general-purpose register. */
-#define TREG_LAST_GPR 55
-
-/* Registers 56 - 62 are "special" network registers. */
-
-#define TREG_SN 56 /**< Static network access. */
-#define TREG_IDN0 57 /**< IDN demux 0 access. */
-#define TREG_IDN1 58 /**< IDN demux 1 access. */
-#define TREG_UDN0 59 /**< UDN demux 0 access. */
-#define TREG_UDN1 60 /**< UDN demux 1 access. */
-#define TREG_UDN2 61 /**< UDN demux 2 access. */
-#define TREG_UDN3 62 /**< UDN demux 3 access. */
-
-/* Register 63 is the "special" zero register. */
-
-#define TREG_ZERO 63 /**< "Zero" register; always reads as "0". */
-
-
-/** By convention, this register is used to hold the syscall number. */
-#define TREG_SYSCALL_NR 10
-
-/** Name of register that holds the syscall number, for use in assembly. */
-#define TREG_SYSCALL_NR_NAME r10
-
-
-/**
- * The ABI requires callers to allocate a caller state save area of
- * this many bytes at the bottom of each stack frame.
- */
-#define C_ABI_SAVE_AREA_SIZE (2 * (INT_REG_BITS / 8))
-
-/**
- * The operand to an 'info' opcode directing the backtracer to not
- * try to find the calling frame.
- */
-#define INFO_OP_CANNOT_BACKTRACE 2
-
-
-#endif /* !__need_int_reg_t */
-
-/* Make sure we later can get all the definitions and declarations. */
-#undef __need_int_reg_t
-
-#endif /* !__ARCH_ABI_H__ */
diff --git a/arch/tile/include/uapi/arch/chip.h b/arch/tile/include/uapi/arch/chip.h
deleted file mode 100644
index 7f55c6856c89..000000000000
--- a/arch/tile/include/uapi/arch/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#if __tile_chip__ == 1
-#include <arch/chip_tilepro.h>
-#elif defined(__tilegx__)
-#include <arch/chip_tilegx.h>
-#else
-#error Unexpected Tilera chip type
-#endif
diff --git a/arch/tile/include/uapi/arch/chip_tilegx.h b/arch/tile/include/uapi/arch/chip_tilegx.h
deleted file mode 100644
index c2a71a43b21c..000000000000
--- a/arch/tile/include/uapi/arch/chip_tilegx.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- * @file
- * Global header file.
- * This header file specifies defines for TILE-Gx.
- */
-
-#ifndef __ARCH_CHIP_H__
-#define __ARCH_CHIP_H__
-
-/** Specify chip version.
- * When possible, prefer the CHIP_xxx symbols below for future-proofing.
- * This is intended for cross-compiling; native compilation should
- * use the predefined __tile_chip__ symbol.
- */
-#define TILE_CHIP 10
-
-/** Specify chip revision.
- * This provides for the case of a respin of a particular chip type;
- * the normal value for this symbol is "0".
- * This is intended for cross-compiling; native compilation should
- * use the predefined __tile_chip_rev__ symbol.
- */
-#define TILE_CHIP_REV 0
-
-/** The name of this architecture. */
-#define CHIP_ARCH_NAME "tilegx"
-
-/** The ELF e_machine type for binaries for this chip. */
-#define CHIP_ELF_TYPE() EM_TILEGX
-
-/** The alternate ELF e_machine type for binaries for this chip. */
-#define CHIP_COMPAT_ELF_TYPE() 0x2597
-
-/** What is the native word size of the machine? */
-#define CHIP_WORD_SIZE() 64
-
-/** How many bits of a virtual address are used. Extra bits must be
- * the sign extension of the low bits.
- */
-#define CHIP_VA_WIDTH() 42
-
-/** How many bits are in a physical address? */
-#define CHIP_PA_WIDTH() 40
-
-/** Size of the L2 cache, in bytes. */
-#define CHIP_L2_CACHE_SIZE() 262144
-
-/** Log size of an L2 cache line in bytes. */
-#define CHIP_L2_LOG_LINE_SIZE() 6
-
-/** Size of an L2 cache line, in bytes. */
-#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
-
-/** Associativity of the L2 cache. */
-#define CHIP_L2_ASSOC() 8
-
-/** Size of the L1 data cache, in bytes. */
-#define CHIP_L1D_CACHE_SIZE() 32768
-
-/** Log size of an L1 data cache line in bytes. */
-#define CHIP_L1D_LOG_LINE_SIZE() 6
-
-/** Size of an L1 data cache line, in bytes. */
-#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
-
-/** Associativity of the L1 data cache. */
-#define CHIP_L1D_ASSOC() 2
-
-/** Size of the L1 instruction cache, in bytes. */
-#define CHIP_L1I_CACHE_SIZE() 32768
-
-/** Log size of an L1 instruction cache line in bytes. */
-#define CHIP_L1I_LOG_LINE_SIZE() 6
-
-/** Size of an L1 instruction cache line, in bytes. */
-#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
-
-/** Associativity of the L1 instruction cache. */
-#define CHIP_L1I_ASSOC() 2
-
-/** Stride with which flush instructions must be issued. */
-#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Stride with which inv instructions must be issued. */
-#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Stride with which finv instructions must be issued. */
-#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Can the local cache coherently cache data that is homed elsewhere? */
-#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
-
-/** How many simultaneous outstanding victims can the L2 cache have? */
-#define CHIP_MAX_OUTSTANDING_VICTIMS() 128
-
-/** Does the TLB support the NC and NOALLOC bits? */
-#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
-
-/** Does the chip support hash-for-home caching? */
-#define CHIP_HAS_CBOX_HOME_MAP() 1
-
-/** Number of entries in the chip's home map tables. */
-#define CHIP_CBOX_HOME_MAP_SIZE() 128
-
-/** Do uncacheable requests miss in the cache regardless of whether
- * there is matching data? */
-#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
-
-/** Does the mf instruction wait for victims? */
-#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
-
-/** Does the chip have an "inv" instruction that doesn't also flush? */
-#define CHIP_HAS_INV() 1
-
-/** Does the chip have a "wh64" instruction? */
-#define CHIP_HAS_WH64() 1
-
-/** Does this chip have a 'dword_align' instruction? */
-#define CHIP_HAS_DWORD_ALIGN() 0
-
-/** Number of performance counters. */
-#define CHIP_PERFORMANCE_COUNTERS() 4
-
-/** Does this chip have auxiliary performance counters? */
-#define CHIP_HAS_AUX_PERF_COUNTERS() 1
-
-/** Is the CBOX_MSR1 SPR supported? */
-#define CHIP_HAS_CBOX_MSR1() 0
-
-/** Is the TILE_RTF_HWM SPR supported? */
-#define CHIP_HAS_TILE_RTF_HWM() 1
-
-/** Is the TILE_WRITE_PENDING SPR supported? */
-#define CHIP_HAS_TILE_WRITE_PENDING() 0
-
-/** Is the PROC_STATUS SPR supported? */
-#define CHIP_HAS_PROC_STATUS_SPR() 1
-
-/** Is the DSTREAM_PF SPR supported? */
-#define CHIP_HAS_DSTREAM_PF() 1
-
-/** Log of the number of mshims we have. */
-#define CHIP_LOG_NUM_MSHIMS() 2
-
-/** Are the bases of the interrupt vector areas fixed? */
-#define CHIP_HAS_FIXED_INTVEC_BASE() 0
-
-/** Are the interrupt masks split up into 2 SPRs? */
-#define CHIP_HAS_SPLIT_INTR_MASK() 0
-
-/** Is the cycle count split up into 2 SPRs? */
-#define CHIP_HAS_SPLIT_CYCLE() 0
-
-/** Does the chip have a static network? */
-#define CHIP_HAS_SN() 0
-
-/** Does the chip have a static network processor? */
-#define CHIP_HAS_SN_PROC() 0
-
-/** Size of the L1 static network processor instruction cache, in bytes. */
-/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */
-
-/** Does the chip have DMA support in each tile? */
-#define CHIP_HAS_TILE_DMA() 0
-
-/** Does the chip have the second revision of the directly accessible
- * dynamic networks? This encapsulates a number of characteristics,
- * including the absence of the catch-all, the absence of inline message
- * tags, the absence of support for network context-switching, and so on.
- */
-#define CHIP_HAS_REV1_XDN() 1
-
-/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
-#define CHIP_HAS_CMPEXCH() 1
-
-/** Does the chip have memory-mapped I/O support? */
-#define CHIP_HAS_MMIO() 1
-
-/** Does the chip have post-completion interrupts? */
-#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1
-
-/** Does the chip have native single step support? */
-#define CHIP_HAS_SINGLE_STEP() 1
-
-#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
-
-/** How many entries are present in the instruction TLB? */
-#define CHIP_ITLB_ENTRIES() 16
-
-/** How many entries are present in the data TLB? */
-#define CHIP_DTLB_ENTRIES() 32
-
-/** How many MAF entries does the XAUI shim have? */
-#define CHIP_XAUI_MAF_ENTRIES() 32
-
-/** Does the memory shim have a source-id table? */
-#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
-
-/** Does the L1 instruction cache clear on reset? */
-#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
-
-/** Does the chip come out of reset with valid coordinates on all tiles?
- * Note that if defined, this also implies that the upper left is 1,1.
- */
-#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
-
-/** Does the chip have unified packet formats? */
-#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
-
-/** Does the chip support write reordering? */
-#define CHIP_HAS_WRITE_REORDERING() 1
-
-/** Does the chip support Y-X routing as well as X-Y? */
-#define CHIP_HAS_Y_X_ROUTING() 1
-
-/** Is INTCTRL_3 managed with the correct MPL? */
-#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
-
-/** Is it possible to configure the chip to be big-endian? */
-#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
-
-/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
-#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
-
-/** Is the DIAG_TRACE_WAY SPR supported? */
-#define CHIP_HAS_DIAG_TRACE_WAY() 0
-
-/** Is the MEM_STRIPE_CONFIG SPR supported? */
-#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
-
-/** Are the TLB_PERF SPRs supported? */
-#define CHIP_HAS_TLB_PERF() 1
-
-/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
-#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
-
-/** Does the chip support rev1 DMA packets? */
-#define CHIP_HAS_REV1_DMA_PACKETS() 1
-
-/** Does the chip have an IPI shim? */
-#define CHIP_HAS_IPI() 1
-
-#endif /* !__OPEN_SOURCE__ */
-#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/uapi/arch/chip_tilepro.h b/arch/tile/include/uapi/arch/chip_tilepro.h
deleted file mode 100644
index a8a3ed144dfe..000000000000
--- a/arch/tile/include/uapi/arch/chip_tilepro.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- * @file
- * Global header file.
- * This header file specifies defines for TILEPro.
- */
-
-#ifndef __ARCH_CHIP_H__
-#define __ARCH_CHIP_H__
-
-/** Specify chip version.
- * When possible, prefer the CHIP_xxx symbols below for future-proofing.
- * This is intended for cross-compiling; native compilation should
- * use the predefined __tile_chip__ symbol.
- */
-#define TILE_CHIP 1
-
-/** Specify chip revision.
- * This provides for the case of a respin of a particular chip type;
- * the normal value for this symbol is "0".
- * This is intended for cross-compiling; native compilation should
- * use the predefined __tile_chip_rev__ symbol.
- */
-#define TILE_CHIP_REV 0
-
-/** The name of this architecture. */
-#define CHIP_ARCH_NAME "tilepro"
-
-/** The ELF e_machine type for binaries for this chip. */
-#define CHIP_ELF_TYPE() EM_TILEPRO
-
-/** The alternate ELF e_machine type for binaries for this chip. */
-#define CHIP_COMPAT_ELF_TYPE() 0x2507
-
-/** What is the native word size of the machine? */
-#define CHIP_WORD_SIZE() 32
-
-/** How many bits of a virtual address are used. Extra bits must be
- * the sign extension of the low bits.
- */
-#define CHIP_VA_WIDTH() 32
-
-/** How many bits are in a physical address? */
-#define CHIP_PA_WIDTH() 36
-
-/** Size of the L2 cache, in bytes. */
-#define CHIP_L2_CACHE_SIZE() 65536
-
-/** Log size of an L2 cache line in bytes. */
-#define CHIP_L2_LOG_LINE_SIZE() 6
-
-/** Size of an L2 cache line, in bytes. */
-#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
-
-/** Associativity of the L2 cache. */
-#define CHIP_L2_ASSOC() 4
-
-/** Size of the L1 data cache, in bytes. */
-#define CHIP_L1D_CACHE_SIZE() 8192
-
-/** Log size of an L1 data cache line in bytes. */
-#define CHIP_L1D_LOG_LINE_SIZE() 4
-
-/** Size of an L1 data cache line, in bytes. */
-#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
-
-/** Associativity of the L1 data cache. */
-#define CHIP_L1D_ASSOC() 2
-
-/** Size of the L1 instruction cache, in bytes. */
-#define CHIP_L1I_CACHE_SIZE() 16384
-
-/** Log size of an L1 instruction cache line in bytes. */
-#define CHIP_L1I_LOG_LINE_SIZE() 6
-
-/** Size of an L1 instruction cache line, in bytes. */
-#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
-
-/** Associativity of the L1 instruction cache. */
-#define CHIP_L1I_ASSOC() 1
-
-/** Stride with which flush instructions must be issued. */
-#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Stride with which inv instructions must be issued. */
-#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Stride with which finv instructions must be issued. */
-#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Can the local cache coherently cache data that is homed elsewhere? */
-#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
-
-/** How many simultaneous outstanding victims can the L2 cache have? */
-#define CHIP_MAX_OUTSTANDING_VICTIMS() 4
-
-/** Does the TLB support the NC and NOALLOC bits? */
-#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
-
-/** Does the chip support hash-for-home caching? */
-#define CHIP_HAS_CBOX_HOME_MAP() 1
-
-/** Number of entries in the chip's home map tables. */
-#define CHIP_CBOX_HOME_MAP_SIZE() 64
-
-/** Do uncacheable requests miss in the cache regardless of whether
- * there is matching data? */
-#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
-
-/** Does the mf instruction wait for victims? */
-#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
-
-/** Does the chip have an "inv" instruction that doesn't also flush? */
-#define CHIP_HAS_INV() 1
-
-/** Does the chip have a "wh64" instruction? */
-#define CHIP_HAS_WH64() 1
-
-/** Does this chip have a 'dword_align' instruction? */
-#define CHIP_HAS_DWORD_ALIGN() 1
-
-/** Number of performance counters. */
-#define CHIP_PERFORMANCE_COUNTERS() 4
-
-/** Does this chip have auxiliary performance counters? */
-#define CHIP_HAS_AUX_PERF_COUNTERS() 1
-
-/** Is the CBOX_MSR1 SPR supported? */
-#define CHIP_HAS_CBOX_MSR1() 1
-
-/** Is the TILE_RTF_HWM SPR supported? */
-#define CHIP_HAS_TILE_RTF_HWM() 1
-
-/** Is the TILE_WRITE_PENDING SPR supported? */
-#define CHIP_HAS_TILE_WRITE_PENDING() 1
-
-/** Is the PROC_STATUS SPR supported? */
-#define CHIP_HAS_PROC_STATUS_SPR() 1
-
-/** Is the DSTREAM_PF SPR supported? */
-#define CHIP_HAS_DSTREAM_PF() 0
-
-/** Log of the number of mshims we have. */
-#define CHIP_LOG_NUM_MSHIMS() 2
-
-/** Are the bases of the interrupt vector areas fixed? */
-#define CHIP_HAS_FIXED_INTVEC_BASE() 1
-
-/** Are the interrupt masks split up into 2 SPRs? */
-#define CHIP_HAS_SPLIT_INTR_MASK() 1
-
-/** Is the cycle count split up into 2 SPRs? */
-#define CHIP_HAS_SPLIT_CYCLE() 1
-
-/** Does the chip have a static network? */
-#define CHIP_HAS_SN() 1
-
-/** Does the chip have a static network processor? */
-#define CHIP_HAS_SN_PROC() 0
-
-/** Size of the L1 static network processor instruction cache, in bytes. */
-/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 1 */
-
-/** Does the chip have DMA support in each tile? */
-#define CHIP_HAS_TILE_DMA() 1
-
-/** Does the chip have the second revision of the directly accessible
- * dynamic networks? This encapsulates a number of characteristics,
- * including the absence of the catch-all, the absence of inline message
- * tags, the absence of support for network context-switching, and so on.
- */
-#define CHIP_HAS_REV1_XDN() 0
-
-/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
-#define CHIP_HAS_CMPEXCH() 0
-
-/** Does the chip have memory-mapped I/O support? */
-#define CHIP_HAS_MMIO() 0
-
-/** Does the chip have post-completion interrupts? */
-#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0
-
-/** Does the chip have native single step support? */
-#define CHIP_HAS_SINGLE_STEP() 0
-
-#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
-
-/** How many entries are present in the instruction TLB? */
-#define CHIP_ITLB_ENTRIES() 16
-
-/** How many entries are present in the data TLB? */
-#define CHIP_DTLB_ENTRIES() 16
-
-/** How many MAF entries does the XAUI shim have? */
-#define CHIP_XAUI_MAF_ENTRIES() 32
-
-/** Does the memory shim have a source-id table? */
-#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
-
-/** Does the L1 instruction cache clear on reset? */
-#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
-
-/** Does the chip come out of reset with valid coordinates on all tiles?
- * Note that if defined, this also implies that the upper left is 1,1.
- */
-#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
-
-/** Does the chip have unified packet formats? */
-#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
-
-/** Does the chip support write reordering? */
-#define CHIP_HAS_WRITE_REORDERING() 1
-
-/** Does the chip support Y-X routing as well as X-Y? */
-#define CHIP_HAS_Y_X_ROUTING() 1
-
-/** Is INTCTRL_3 managed with the correct MPL? */
-#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
-
-/** Is it possible to configure the chip to be big-endian? */
-#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
-
-/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
-#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 1
-
-/** Is the DIAG_TRACE_WAY SPR supported? */
-#define CHIP_HAS_DIAG_TRACE_WAY() 1
-
-/** Is the MEM_STRIPE_CONFIG SPR supported? */
-#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
-
-/** Are the TLB_PERF SPRs supported? */
-#define CHIP_HAS_TLB_PERF() 1
-
-/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
-#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 1
-
-/** Does the chip support rev1 DMA packets? */
-#define CHIP_HAS_REV1_DMA_PACKETS() 1
-
-/** Does the chip have an IPI shim? */
-#define CHIP_HAS_IPI() 0
-
-#endif /* !__OPEN_SOURCE__ */
-#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/uapi/arch/icache.h b/arch/tile/include/uapi/arch/icache.h
deleted file mode 100644
index ff85a5d77f16..000000000000
--- a/arch/tile/include/uapi/arch/icache.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- */
-
-/**
- * @file
- *
- * Support for invalidating bytes in the instruction cache.
- */
-
-#ifndef __ARCH_ICACHE_H__
-#define __ARCH_ICACHE_H__
-
-#include <arch/chip.h>
-
-
-/**
- * Invalidate the instruction cache for the given range of memory.
- *
- * @param addr The start of memory to be invalidated.
- * @param size The number of bytes to be invalidated.
- * @param page_size The system's page size, e.g. getpagesize() in userspace.
- * This value must be a power of two no larger than the page containing
- * the code to be invalidated. If the value is smaller than the actual page
- * size, this function will still work, but may run slower than necessary.
- */
-static __inline void
-invalidate_icache(const void* addr, unsigned long size,
- unsigned long page_size)
-{
- const unsigned long cache_way_size =
- CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC();
- unsigned long max_useful_size;
- const char* start, *end;
- long num_passes;
-
- if (__builtin_expect(size == 0, 0))
- return;
-
-#ifdef __tilegx__
- /* Limit the number of bytes visited to avoid redundant iterations. */
- max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size;
-
- /* No PA aliasing is possible, so one pass always suffices. */
- num_passes = 1;
-#else
- /* Limit the number of bytes visited to avoid redundant iterations. */
- max_useful_size = cache_way_size;
-
- /*
- * Compute how many passes we need (we'll treat 0 as if it were 1).
- * This works because we know the page size is a power of two.
- */
- num_passes = cache_way_size >> __builtin_ctzl(page_size);
-#endif
-
- if (__builtin_expect(size > max_useful_size, 0))
- size = max_useful_size;
-
- /* Locate the first and last bytes to be invalidated. */
- start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE());
- end = (const char*)addr + size - 1;
-
- __insn_mf();
-
- do
- {
- const char* p;
-
- for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE())
- __insn_icoh(p);
-
- start += page_size;
- end += page_size;
- }
- while (--num_passes > 0);
-
- __insn_drain();
-}
-
-
-#endif /* __ARCH_ICACHE_H__ */
diff --git a/arch/tile/include/uapi/arch/interrupts.h b/arch/tile/include/uapi/arch/interrupts.h
deleted file mode 100644
index c288b5d82b4d..000000000000
--- a/arch/tile/include/uapi/arch/interrupts.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifdef __tilegx__
-#include <arch/interrupts_64.h>
-#else
-#include <arch/interrupts_32.h>
-#endif
diff --git a/arch/tile/include/uapi/arch/interrupts_32.h b/arch/tile/include/uapi/arch/interrupts_32.h
deleted file mode 100644
index a748752cec16..000000000000
--- a/arch/tile/include/uapi/arch/interrupts_32.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __ARCH_INTERRUPTS_H__
-#define __ARCH_INTERRUPTS_H__
-
-#ifndef __KERNEL__
-/** Mask for an interrupt. */
-/* Note: must handle breaking interrupts into high and low words manually. */
-#define INT_MASK_LO(intno) (1 << (intno))
-#define INT_MASK_HI(intno) (1 << ((intno) - 32))
-
-#ifndef __ASSEMBLER__
-#define INT_MASK(intno) (1ULL << (intno))
-#endif
-#endif
-
-
-/** Where a given interrupt executes */
-#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
-
-/** Where to store a vector for a given interrupt. */
-#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
-
-/** The base address of user-level interrupts. */
-#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
-
-
-/** Additional synthetic interrupt. */
-#define INT_BREAKPOINT (63)
-
-#define INT_ITLB_MISS 0
-#define INT_MEM_ERROR 1
-#define INT_ILL 2
-#define INT_GPV 3
-#define INT_SN_ACCESS 4
-#define INT_IDN_ACCESS 5
-#define INT_UDN_ACCESS 6
-#define INT_IDN_REFILL 7
-#define INT_UDN_REFILL 8
-#define INT_IDN_COMPLETE 9
-#define INT_UDN_COMPLETE 10
-#define INT_SWINT_3 11
-#define INT_SWINT_2 12
-#define INT_SWINT_1 13
-#define INT_SWINT_0 14
-#define INT_UNALIGN_DATA 15
-#define INT_DTLB_MISS 16
-#define INT_DTLB_ACCESS 17
-#define INT_DMATLB_MISS 18
-#define INT_DMATLB_ACCESS 19
-#define INT_SNITLB_MISS 20
-#define INT_SN_NOTIFY 21
-#define INT_SN_FIREWALL 22
-#define INT_IDN_FIREWALL 23
-#define INT_UDN_FIREWALL 24
-#define INT_TILE_TIMER 25
-#define INT_IDN_TIMER 26
-#define INT_UDN_TIMER 27
-#define INT_DMA_NOTIFY 28
-#define INT_IDN_CA 29
-#define INT_UDN_CA 30
-#define INT_IDN_AVAIL 31
-#define INT_UDN_AVAIL 32
-#define INT_PERF_COUNT 33
-#define INT_INTCTRL_3 34
-#define INT_INTCTRL_2 35
-#define INT_INTCTRL_1 36
-#define INT_INTCTRL_0 37
-#define INT_BOOT_ACCESS 38
-#define INT_WORLD_ACCESS 39
-#define INT_I_ASID 40
-#define INT_D_ASID 41
-#define INT_DMA_ASID 42
-#define INT_SNI_ASID 43
-#define INT_DMA_CPL 44
-#define INT_SN_CPL 45
-#define INT_DOUBLE_FAULT 46
-#define INT_SN_STATIC_ACCESS 47
-#define INT_AUX_PERF_COUNT 48
-
-#define NUM_INTERRUPTS 49
-
-#ifndef __ASSEMBLER__
-#define QUEUED_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_DMATLB_MISS) | \
- (1ULL << INT_DMATLB_ACCESS) | \
- (1ULL << INT_SNITLB_MISS) | \
- (1ULL << INT_SN_NOTIFY) | \
- (1ULL << INT_SN_FIREWALL) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_DMA_NOTIFY) | \
- (1ULL << INT_IDN_CA) | \
- (1ULL << INT_UDN_CA) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DMA_ASID) | \
- (1ULL << INT_SNI_ASID) | \
- (1ULL << INT_DMA_CPL) | \
- (1ULL << INT_SN_CPL) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- 0)
-#define NONQUEUED_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_SN_ACCESS) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_IDN_REFILL) | \
- (1ULL << INT_UDN_REFILL) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_SN_STATIC_ACCESS) | \
- 0)
-#define CRITICAL_MASKED_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_DMATLB_MISS) | \
- (1ULL << INT_DMATLB_ACCESS) | \
- (1ULL << INT_SNITLB_MISS) | \
- (1ULL << INT_SN_NOTIFY) | \
- (1ULL << INT_SN_FIREWALL) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_DMA_NOTIFY) | \
- (1ULL << INT_IDN_CA) | \
- (1ULL << INT_UDN_CA) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- 0)
-#define CRITICAL_UNMASKED_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_SN_ACCESS) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_IDN_REFILL) | \
- (1ULL << INT_UDN_REFILL) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DMA_ASID) | \
- (1ULL << INT_SNI_ASID) | \
- (1ULL << INT_DMA_CPL) | \
- (1ULL << INT_SN_CPL) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- (1ULL << INT_SN_STATIC_ACCESS) | \
- 0)
-#define MASKABLE_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_IDN_REFILL) | \
- (1ULL << INT_UDN_REFILL) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_DMATLB_MISS) | \
- (1ULL << INT_DMATLB_ACCESS) | \
- (1ULL << INT_SNITLB_MISS) | \
- (1ULL << INT_SN_NOTIFY) | \
- (1ULL << INT_SN_FIREWALL) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_DMA_NOTIFY) | \
- (1ULL << INT_IDN_CA) | \
- (1ULL << INT_UDN_CA) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- 0)
-#define UNMASKABLE_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_SN_ACCESS) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DMA_ASID) | \
- (1ULL << INT_SNI_ASID) | \
- (1ULL << INT_DMA_CPL) | \
- (1ULL << INT_SN_CPL) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- (1ULL << INT_SN_STATIC_ACCESS) | \
- 0)
-#define SYNC_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_SN_ACCESS) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_IDN_REFILL) | \
- (1ULL << INT_UDN_REFILL) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_SN_STATIC_ACCESS) | \
- 0)
-#define NON_SYNC_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_DMATLB_MISS) | \
- (1ULL << INT_DMATLB_ACCESS) | \
- (1ULL << INT_SNITLB_MISS) | \
- (1ULL << INT_SN_NOTIFY) | \
- (1ULL << INT_SN_FIREWALL) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_DMA_NOTIFY) | \
- (1ULL << INT_IDN_CA) | \
- (1ULL << INT_UDN_CA) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DMA_ASID) | \
- (1ULL << INT_SNI_ASID) | \
- (1ULL << INT_DMA_CPL) | \
- (1ULL << INT_SN_CPL) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- 0)
-#endif /* !__ASSEMBLER__ */
-#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/uapi/arch/interrupts_64.h b/arch/tile/include/uapi/arch/interrupts_64.h
deleted file mode 100644
index 142eaff3c244..000000000000
--- a/arch/tile/include/uapi/arch/interrupts_64.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __ARCH_INTERRUPTS_H__
-#define __ARCH_INTERRUPTS_H__
-
-#ifndef __KERNEL__
-/** Mask for an interrupt. */
-#ifdef __ASSEMBLER__
-/* Note: must handle breaking interrupts into high and low words manually. */
-#define INT_MASK(intno) (1 << (intno))
-#else
-#define INT_MASK(intno) (1ULL << (intno))
-#endif
-#endif
-
-
-/** Where a given interrupt executes */
-#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
-
-/** Where to store a vector for a given interrupt. */
-#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
-
-/** The base address of user-level interrupts. */
-#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
-
-
-/** Additional synthetic interrupt. */
-#define INT_BREAKPOINT (63)
-
-#define INT_MEM_ERROR 0
-#define INT_SINGLE_STEP_3 1
-#define INT_SINGLE_STEP_2 2
-#define INT_SINGLE_STEP_1 3
-#define INT_SINGLE_STEP_0 4
-#define INT_IDN_COMPLETE 5
-#define INT_UDN_COMPLETE 6
-#define INT_ITLB_MISS 7
-#define INT_ILL 8
-#define INT_GPV 9
-#define INT_IDN_ACCESS 10
-#define INT_UDN_ACCESS 11
-#define INT_SWINT_3 12
-#define INT_SWINT_2 13
-#define INT_SWINT_1 14
-#define INT_SWINT_0 15
-#define INT_ILL_TRANS 16
-#define INT_UNALIGN_DATA 17
-#define INT_DTLB_MISS 18
-#define INT_DTLB_ACCESS 19
-#define INT_IDN_FIREWALL 20
-#define INT_UDN_FIREWALL 21
-#define INT_TILE_TIMER 22
-#define INT_AUX_TILE_TIMER 23
-#define INT_IDN_TIMER 24
-#define INT_UDN_TIMER 25
-#define INT_IDN_AVAIL 26
-#define INT_UDN_AVAIL 27
-#define INT_IPI_3 28
-#define INT_IPI_2 29
-#define INT_IPI_1 30
-#define INT_IPI_0 31
-#define INT_PERF_COUNT 32
-#define INT_AUX_PERF_COUNT 33
-#define INT_INTCTRL_3 34
-#define INT_INTCTRL_2 35
-#define INT_INTCTRL_1 36
-#define INT_INTCTRL_0 37
-#define INT_BOOT_ACCESS 38
-#define INT_WORLD_ACCESS 39
-#define INT_I_ASID 40
-#define INT_D_ASID 41
-#define INT_DOUBLE_FAULT 42
-
-#define NUM_INTERRUPTS 43
-
-#ifndef __ASSEMBLER__
-#define QUEUED_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_AUX_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_IPI_3) | \
- (1ULL << INT_IPI_2) | \
- (1ULL << INT_IPI_1) | \
- (1ULL << INT_IPI_0) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- 0)
-#define NONQUEUED_INTERRUPTS ( \
- (1ULL << INT_SINGLE_STEP_3) | \
- (1ULL << INT_SINGLE_STEP_2) | \
- (1ULL << INT_SINGLE_STEP_1) | \
- (1ULL << INT_SINGLE_STEP_0) | \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_ILL_TRANS) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- 0)
-#define CRITICAL_MASKED_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_SINGLE_STEP_3) | \
- (1ULL << INT_SINGLE_STEP_2) | \
- (1ULL << INT_SINGLE_STEP_1) | \
- (1ULL << INT_SINGLE_STEP_0) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_AUX_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_IPI_3) | \
- (1ULL << INT_IPI_2) | \
- (1ULL << INT_IPI_1) | \
- (1ULL << INT_IPI_0) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- 0)
-#define CRITICAL_UNMASKED_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_ILL_TRANS) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- 0)
-#define MASKABLE_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_SINGLE_STEP_3) | \
- (1ULL << INT_SINGLE_STEP_2) | \
- (1ULL << INT_SINGLE_STEP_1) | \
- (1ULL << INT_SINGLE_STEP_0) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_AUX_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_IPI_3) | \
- (1ULL << INT_IPI_2) | \
- (1ULL << INT_IPI_1) | \
- (1ULL << INT_IPI_0) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- 0)
-#define UNMASKABLE_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_ILL_TRANS) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- 0)
-#define SYNC_INTERRUPTS ( \
- (1ULL << INT_SINGLE_STEP_3) | \
- (1ULL << INT_SINGLE_STEP_2) | \
- (1ULL << INT_SINGLE_STEP_1) | \
- (1ULL << INT_SINGLE_STEP_0) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_ILL_TRANS) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- 0)
-#define NON_SYNC_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_AUX_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_IPI_3) | \
- (1ULL << INT_IPI_2) | \
- (1ULL << INT_IPI_1) | \
- (1ULL << INT_IPI_0) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- 0)
-#endif /* !__ASSEMBLER__ */
-#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/uapi/arch/intreg.h b/arch/tile/include/uapi/arch/intreg.h
deleted file mode 100644
index 5387fb645bb8..000000000000
--- a/arch/tile/include/uapi/arch/intreg.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2017 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file
- *
- * Provide types and defines for the type that can hold a register,
- * in the implementation namespace.
- */
-
-#ifndef __ARCH_INTREG_H__
-#define __ARCH_INTREG_H__
-
-/*
- * Get number of bits in a register. __INT_REG_BITS may be defined
- * prior to including this header to force a particular bit width.
- */
-
-#ifndef __INT_REG_BITS
-# if defined __tilegx__
-# define __INT_REG_BITS 64
-# elif defined __tilepro__
-# define __INT_REG_BITS 32
-# else
-# error Unrecognized architecture
-# endif
-#endif
-
-#if __INT_REG_BITS == 64
-
-# ifndef __ASSEMBLER__
-/** Unsigned type that can hold a register. */
-typedef unsigned long long __uint_reg_t;
-
-/** Signed type that can hold a register. */
-typedef long long __int_reg_t;
-# endif
-
-/** String prefix to use for printf(). */
-# define __INT_REG_FMT "ll"
-
-#elif __INT_REG_BITS == 32
-
-# ifndef __ASSEMBLER__
-/** Unsigned type that can hold a register. */
-typedef unsigned long __uint_reg_t;
-
-/** Signed type that can hold a register. */
-typedef long __int_reg_t;
-# endif
-
-/** String prefix to use for printf(). */
-# define __INT_REG_FMT "l"
-
-#else
-# error Unrecognized value of __INT_REG_BITS
-#endif
-
-#endif /* !__ARCH_INTREG_H__ */
diff --git a/arch/tile/include/uapi/arch/opcode.h b/arch/tile/include/uapi/arch/opcode.h
deleted file mode 100644
index a9ce5961a028..000000000000
--- a/arch/tile/include/uapi/arch/opcode.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#if defined(__tilepro__)
-#include <arch/opcode_tilepro.h>
-#elif defined(__tilegx__)
-#include <arch/opcode_tilegx.h>
-#else
-#error Unexpected Tilera chip type
-#endif
diff --git a/arch/tile/include/uapi/arch/opcode_tilegx.h b/arch/tile/include/uapi/arch/opcode_tilegx.h
deleted file mode 100644
index 948ea544567f..000000000000
--- a/arch/tile/include/uapi/arch/opcode_tilegx.h
+++ /dev/null
@@ -1,1407 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* TILE-Gx opcode information.
- *
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- *
- *
- *
- *
- */
-
-#ifndef __ARCH_OPCODE_H__
-#define __ARCH_OPCODE_H__
-
-#ifndef __ASSEMBLER__
-
-typedef unsigned long long tilegx_bundle_bits;
-
-/* These are the bits that determine if a bundle is in the X encoding. */
-#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
-
-enum
-{
- /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
- TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
-
- /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
- TILEGX_NUM_PIPELINE_ENCODINGS = 5,
-
- /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
- TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
-
- /* Instructions take this many bytes. */
- TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
-
- /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
- TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
-
- /* Bundles should be aligned modulo this number of bytes. */
- TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
- (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
-
- /* Number of registers (some are magic, such as network I/O). */
- TILEGX_NUM_REGISTERS = 64,
-};
-
-/* Make a few "tile_" variables to simplify common code between
- architectures. */
-
-typedef tilegx_bundle_bits tile_bundle_bits;
-#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
-#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
-#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
- TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
-#define TILE_BPT_BUNDLE TILEGX_BPT_BUNDLE
-
-/* 64-bit pattern for a { bpt ; nop } bundle. */
-#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
-
-static __inline unsigned int
-get_BFEnd_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 24)) & 0xf);
-}
-
-static __inline unsigned int
-get_BFStart_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3f);
-}
-
-static __inline unsigned int
-get_BrOff_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 37)) & 0x0001ffc0);
-}
-
-static __inline unsigned int
-get_BrType_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 54)) & 0x1f);
-}
-
-static __inline unsigned int
-get_Dest_Imm8_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 43)) & 0x000000c0);
-}
-
-static __inline unsigned int
-get_Dest_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Imm16_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xffff);
-}
-
-static __inline unsigned int
-get_Imm16_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xffff);
-}
-
-static __inline unsigned int
-get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 20)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 51)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xff);
-}
-
-static __inline unsigned int
-get_JumpOff_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x7ffffff);
-}
-
-static __inline unsigned int
-get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 58)) & 0x1);
-}
-
-static __inline unsigned int
-get_MF_Imm14_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3fff);
-}
-
-static __inline unsigned int
-get_MT_Imm14_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 37)) & 0x00003fc0);
-}
-
-static __inline unsigned int
-get_Mode(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 62)) & 0x3);
-}
-
-static __inline unsigned int
-get_Opcode_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 28)) & 0x7);
-}
-
-static __inline unsigned int
-get_Opcode_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 59)) & 0x7);
-}
-
-static __inline unsigned int
-get_Opcode_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 27)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 58)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y2(tilegx_bundle_bits n)
-{
- return (((n >> 26)) & 0x00000001) |
- (((unsigned int)(n >> 56)) & 0x00000002);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3);
-}
-
-static __inline unsigned int
-get_ShAmt_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_ShAmt_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_ShAmt_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_ShAmt_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3);
-}
-
-static __inline unsigned int
-get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3);
-}
-
-static __inline unsigned int
-get_SrcA_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y2(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 20)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcBDest_Y2(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 51)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-
-static __inline int
-sign_extend(int n, int num_bits)
-{
- int shift = (int)(sizeof(int) * 8 - num_bits);
- return (n << shift) >> shift;
-}
-
-
-
-static __inline tilegx_bundle_bits
-create_BFEnd_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_BFOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 24);
-}
-
-static __inline tilegx_bundle_bits
-create_BFStart_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_BrOff_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_BrType_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_Imm8_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm16_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xffff) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm16_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8OpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 20);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8OpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xff)) << 51);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_JumpOff_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
-}
-
-static __inline tilegx_bundle_bits
-create_JumpOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x1)) << 58);
-}
-
-static __inline tilegx_bundle_bits
-create_MF_Imm14_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_MT_Imm14_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_Mode(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3)) << 62);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x7) << 28);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x7)) << 59);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 27);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xf)) << 58);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x00000001) << 26) |
- (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 20);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcBDest_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-
-enum
-{
- ADDI_IMM8_OPCODE_X0 = 1,
- ADDI_IMM8_OPCODE_X1 = 1,
- ADDI_OPCODE_Y0 = 0,
- ADDI_OPCODE_Y1 = 1,
- ADDLI_OPCODE_X0 = 1,
- ADDLI_OPCODE_X1 = 0,
- ADDXI_IMM8_OPCODE_X0 = 2,
- ADDXI_IMM8_OPCODE_X1 = 2,
- ADDXI_OPCODE_Y0 = 1,
- ADDXI_OPCODE_Y1 = 2,
- ADDXLI_OPCODE_X0 = 2,
- ADDXLI_OPCODE_X1 = 1,
- ADDXSC_RRR_0_OPCODE_X0 = 1,
- ADDXSC_RRR_0_OPCODE_X1 = 1,
- ADDX_RRR_0_OPCODE_X0 = 2,
- ADDX_RRR_0_OPCODE_X1 = 2,
- ADDX_RRR_0_OPCODE_Y0 = 0,
- ADDX_RRR_0_OPCODE_Y1 = 0,
- ADD_RRR_0_OPCODE_X0 = 3,
- ADD_RRR_0_OPCODE_X1 = 3,
- ADD_RRR_0_OPCODE_Y0 = 1,
- ADD_RRR_0_OPCODE_Y1 = 1,
- ANDI_IMM8_OPCODE_X0 = 3,
- ANDI_IMM8_OPCODE_X1 = 3,
- ANDI_OPCODE_Y0 = 2,
- ANDI_OPCODE_Y1 = 3,
- AND_RRR_0_OPCODE_X0 = 4,
- AND_RRR_0_OPCODE_X1 = 4,
- AND_RRR_5_OPCODE_Y0 = 0,
- AND_RRR_5_OPCODE_Y1 = 0,
- BEQZT_BRANCH_OPCODE_X1 = 16,
- BEQZ_BRANCH_OPCODE_X1 = 17,
- BFEXTS_BF_OPCODE_X0 = 4,
- BFEXTU_BF_OPCODE_X0 = 5,
- BFINS_BF_OPCODE_X0 = 6,
- BF_OPCODE_X0 = 3,
- BGEZT_BRANCH_OPCODE_X1 = 18,
- BGEZ_BRANCH_OPCODE_X1 = 19,
- BGTZT_BRANCH_OPCODE_X1 = 20,
- BGTZ_BRANCH_OPCODE_X1 = 21,
- BLBCT_BRANCH_OPCODE_X1 = 22,
- BLBC_BRANCH_OPCODE_X1 = 23,
- BLBST_BRANCH_OPCODE_X1 = 24,
- BLBS_BRANCH_OPCODE_X1 = 25,
- BLEZT_BRANCH_OPCODE_X1 = 26,
- BLEZ_BRANCH_OPCODE_X1 = 27,
- BLTZT_BRANCH_OPCODE_X1 = 28,
- BLTZ_BRANCH_OPCODE_X1 = 29,
- BNEZT_BRANCH_OPCODE_X1 = 30,
- BNEZ_BRANCH_OPCODE_X1 = 31,
- BRANCH_OPCODE_X1 = 2,
- CMOVEQZ_RRR_0_OPCODE_X0 = 5,
- CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
- CMOVNEZ_RRR_0_OPCODE_X0 = 6,
- CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
- CMPEQI_IMM8_OPCODE_X0 = 4,
- CMPEQI_IMM8_OPCODE_X1 = 4,
- CMPEQI_OPCODE_Y0 = 3,
- CMPEQI_OPCODE_Y1 = 4,
- CMPEQ_RRR_0_OPCODE_X0 = 7,
- CMPEQ_RRR_0_OPCODE_X1 = 5,
- CMPEQ_RRR_3_OPCODE_Y0 = 0,
- CMPEQ_RRR_3_OPCODE_Y1 = 2,
- CMPEXCH4_RRR_0_OPCODE_X1 = 6,
- CMPEXCH_RRR_0_OPCODE_X1 = 7,
- CMPLES_RRR_0_OPCODE_X0 = 8,
- CMPLES_RRR_0_OPCODE_X1 = 8,
- CMPLES_RRR_2_OPCODE_Y0 = 0,
- CMPLES_RRR_2_OPCODE_Y1 = 0,
- CMPLEU_RRR_0_OPCODE_X0 = 9,
- CMPLEU_RRR_0_OPCODE_X1 = 9,
- CMPLEU_RRR_2_OPCODE_Y0 = 1,
- CMPLEU_RRR_2_OPCODE_Y1 = 1,
- CMPLTSI_IMM8_OPCODE_X0 = 5,
- CMPLTSI_IMM8_OPCODE_X1 = 5,
- CMPLTSI_OPCODE_Y0 = 4,
- CMPLTSI_OPCODE_Y1 = 5,
- CMPLTS_RRR_0_OPCODE_X0 = 10,
- CMPLTS_RRR_0_OPCODE_X1 = 10,
- CMPLTS_RRR_2_OPCODE_Y0 = 2,
- CMPLTS_RRR_2_OPCODE_Y1 = 2,
- CMPLTUI_IMM8_OPCODE_X0 = 6,
- CMPLTUI_IMM8_OPCODE_X1 = 6,
- CMPLTU_RRR_0_OPCODE_X0 = 11,
- CMPLTU_RRR_0_OPCODE_X1 = 11,
- CMPLTU_RRR_2_OPCODE_Y0 = 3,
- CMPLTU_RRR_2_OPCODE_Y1 = 3,
- CMPNE_RRR_0_OPCODE_X0 = 12,
- CMPNE_RRR_0_OPCODE_X1 = 12,
- CMPNE_RRR_3_OPCODE_Y0 = 1,
- CMPNE_RRR_3_OPCODE_Y1 = 3,
- CMULAF_RRR_0_OPCODE_X0 = 13,
- CMULA_RRR_0_OPCODE_X0 = 14,
- CMULFR_RRR_0_OPCODE_X0 = 15,
- CMULF_RRR_0_OPCODE_X0 = 16,
- CMULHR_RRR_0_OPCODE_X0 = 17,
- CMULH_RRR_0_OPCODE_X0 = 18,
- CMUL_RRR_0_OPCODE_X0 = 19,
- CNTLZ_UNARY_OPCODE_X0 = 1,
- CNTLZ_UNARY_OPCODE_Y0 = 1,
- CNTTZ_UNARY_OPCODE_X0 = 2,
- CNTTZ_UNARY_OPCODE_Y0 = 2,
- CRC32_32_RRR_0_OPCODE_X0 = 20,
- CRC32_8_RRR_0_OPCODE_X0 = 21,
- DBLALIGN2_RRR_0_OPCODE_X0 = 22,
- DBLALIGN2_RRR_0_OPCODE_X1 = 13,
- DBLALIGN4_RRR_0_OPCODE_X0 = 23,
- DBLALIGN4_RRR_0_OPCODE_X1 = 14,
- DBLALIGN6_RRR_0_OPCODE_X0 = 24,
- DBLALIGN6_RRR_0_OPCODE_X1 = 15,
- DBLALIGN_RRR_0_OPCODE_X0 = 25,
- DRAIN_UNARY_OPCODE_X1 = 1,
- DTLBPR_UNARY_OPCODE_X1 = 2,
- EXCH4_RRR_0_OPCODE_X1 = 16,
- EXCH_RRR_0_OPCODE_X1 = 17,
- FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
- FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
- FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
- FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
- FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
- FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
- FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
- FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
- FETCHADD4_RRR_0_OPCODE_X1 = 18,
- FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
- FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
- FETCHADD_RRR_0_OPCODE_X1 = 21,
- FETCHAND4_RRR_0_OPCODE_X1 = 22,
- FETCHAND_RRR_0_OPCODE_X1 = 23,
- FETCHOR4_RRR_0_OPCODE_X1 = 24,
- FETCHOR_RRR_0_OPCODE_X1 = 25,
- FINV_UNARY_OPCODE_X1 = 3,
- FLUSHWB_UNARY_OPCODE_X1 = 4,
- FLUSH_UNARY_OPCODE_X1 = 5,
- FNOP_UNARY_OPCODE_X0 = 3,
- FNOP_UNARY_OPCODE_X1 = 6,
- FNOP_UNARY_OPCODE_Y0 = 3,
- FNOP_UNARY_OPCODE_Y1 = 8,
- FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
- FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
- FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
- FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
- FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
- FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
- FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
- FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
- ICOH_UNARY_OPCODE_X1 = 7,
- ILL_UNARY_OPCODE_X1 = 8,
- ILL_UNARY_OPCODE_Y1 = 9,
- IMM8_OPCODE_X0 = 4,
- IMM8_OPCODE_X1 = 3,
- INV_UNARY_OPCODE_X1 = 9,
- IRET_UNARY_OPCODE_X1 = 10,
- JALRP_UNARY_OPCODE_X1 = 11,
- JALRP_UNARY_OPCODE_Y1 = 10,
- JALR_UNARY_OPCODE_X1 = 12,
- JALR_UNARY_OPCODE_Y1 = 11,
- JAL_JUMP_OPCODE_X1 = 0,
- JRP_UNARY_OPCODE_X1 = 13,
- JRP_UNARY_OPCODE_Y1 = 12,
- JR_UNARY_OPCODE_X1 = 14,
- JR_UNARY_OPCODE_Y1 = 13,
- JUMP_OPCODE_X1 = 4,
- J_JUMP_OPCODE_X1 = 1,
- LD1S_ADD_IMM8_OPCODE_X1 = 7,
- LD1S_OPCODE_Y2 = 0,
- LD1S_UNARY_OPCODE_X1 = 15,
- LD1U_ADD_IMM8_OPCODE_X1 = 8,
- LD1U_OPCODE_Y2 = 1,
- LD1U_UNARY_OPCODE_X1 = 16,
- LD2S_ADD_IMM8_OPCODE_X1 = 9,
- LD2S_OPCODE_Y2 = 2,
- LD2S_UNARY_OPCODE_X1 = 17,
- LD2U_ADD_IMM8_OPCODE_X1 = 10,
- LD2U_OPCODE_Y2 = 3,
- LD2U_UNARY_OPCODE_X1 = 18,
- LD4S_ADD_IMM8_OPCODE_X1 = 11,
- LD4S_OPCODE_Y2 = 1,
- LD4S_UNARY_OPCODE_X1 = 19,
- LD4U_ADD_IMM8_OPCODE_X1 = 12,
- LD4U_OPCODE_Y2 = 2,
- LD4U_UNARY_OPCODE_X1 = 20,
- LDNA_ADD_IMM8_OPCODE_X1 = 21,
- LDNA_UNARY_OPCODE_X1 = 21,
- LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
- LDNT1S_UNARY_OPCODE_X1 = 22,
- LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
- LDNT1U_UNARY_OPCODE_X1 = 23,
- LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
- LDNT2S_UNARY_OPCODE_X1 = 24,
- LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
- LDNT2U_UNARY_OPCODE_X1 = 25,
- LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
- LDNT4S_UNARY_OPCODE_X1 = 26,
- LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
- LDNT4U_UNARY_OPCODE_X1 = 27,
- LDNT_ADD_IMM8_OPCODE_X1 = 19,
- LDNT_UNARY_OPCODE_X1 = 28,
- LD_ADD_IMM8_OPCODE_X1 = 20,
- LD_OPCODE_Y2 = 3,
- LD_UNARY_OPCODE_X1 = 29,
- LNK_UNARY_OPCODE_X1 = 30,
- LNK_UNARY_OPCODE_Y1 = 14,
- MFSPR_IMM8_OPCODE_X1 = 22,
- MF_UNARY_OPCODE_X1 = 31,
- MM_BF_OPCODE_X0 = 7,
- MNZ_RRR_0_OPCODE_X0 = 40,
- MNZ_RRR_0_OPCODE_X1 = 26,
- MNZ_RRR_4_OPCODE_Y0 = 2,
- MNZ_RRR_4_OPCODE_Y1 = 2,
- MODE_OPCODE_YA2 = 1,
- MODE_OPCODE_YB2 = 2,
- MODE_OPCODE_YC2 = 3,
- MTSPR_IMM8_OPCODE_X1 = 23,
- MULAX_RRR_0_OPCODE_X0 = 41,
- MULAX_RRR_3_OPCODE_Y0 = 2,
- MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
- MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
- MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
- MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
- MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
- MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
- MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
- MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
- MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
- MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
- MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
- MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
- MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
- MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
- MULX_RRR_0_OPCODE_X0 = 52,
- MULX_RRR_3_OPCODE_Y0 = 3,
- MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
- MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
- MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
- MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
- MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
- MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
- MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
- MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
- MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
- MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
- MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
- MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
- MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
- MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
- MZ_RRR_0_OPCODE_X0 = 63,
- MZ_RRR_0_OPCODE_X1 = 27,
- MZ_RRR_4_OPCODE_Y0 = 3,
- MZ_RRR_4_OPCODE_Y1 = 3,
- NAP_UNARY_OPCODE_X1 = 32,
- NOP_UNARY_OPCODE_X0 = 5,
- NOP_UNARY_OPCODE_X1 = 33,
- NOP_UNARY_OPCODE_Y0 = 5,
- NOP_UNARY_OPCODE_Y1 = 15,
- NOR_RRR_0_OPCODE_X0 = 64,
- NOR_RRR_0_OPCODE_X1 = 28,
- NOR_RRR_5_OPCODE_Y0 = 1,
- NOR_RRR_5_OPCODE_Y1 = 1,
- ORI_IMM8_OPCODE_X0 = 7,
- ORI_IMM8_OPCODE_X1 = 24,
- OR_RRR_0_OPCODE_X0 = 65,
- OR_RRR_0_OPCODE_X1 = 29,
- OR_RRR_5_OPCODE_Y0 = 2,
- OR_RRR_5_OPCODE_Y1 = 2,
- PCNT_UNARY_OPCODE_X0 = 6,
- PCNT_UNARY_OPCODE_Y0 = 6,
- REVBITS_UNARY_OPCODE_X0 = 7,
- REVBITS_UNARY_OPCODE_Y0 = 7,
- REVBYTES_UNARY_OPCODE_X0 = 8,
- REVBYTES_UNARY_OPCODE_Y0 = 8,
- ROTLI_SHIFT_OPCODE_X0 = 1,
- ROTLI_SHIFT_OPCODE_X1 = 1,
- ROTLI_SHIFT_OPCODE_Y0 = 0,
- ROTLI_SHIFT_OPCODE_Y1 = 0,
- ROTL_RRR_0_OPCODE_X0 = 66,
- ROTL_RRR_0_OPCODE_X1 = 30,
- ROTL_RRR_6_OPCODE_Y0 = 0,
- ROTL_RRR_6_OPCODE_Y1 = 0,
- RRR_0_OPCODE_X0 = 5,
- RRR_0_OPCODE_X1 = 5,
- RRR_0_OPCODE_Y0 = 5,
- RRR_0_OPCODE_Y1 = 6,
- RRR_1_OPCODE_Y0 = 6,
- RRR_1_OPCODE_Y1 = 7,
- RRR_2_OPCODE_Y0 = 7,
- RRR_2_OPCODE_Y1 = 8,
- RRR_3_OPCODE_Y0 = 8,
- RRR_3_OPCODE_Y1 = 9,
- RRR_4_OPCODE_Y0 = 9,
- RRR_4_OPCODE_Y1 = 10,
- RRR_5_OPCODE_Y0 = 10,
- RRR_5_OPCODE_Y1 = 11,
- RRR_6_OPCODE_Y0 = 11,
- RRR_6_OPCODE_Y1 = 12,
- RRR_7_OPCODE_Y0 = 12,
- RRR_7_OPCODE_Y1 = 13,
- RRR_8_OPCODE_Y0 = 13,
- RRR_9_OPCODE_Y0 = 14,
- SHIFT_OPCODE_X0 = 6,
- SHIFT_OPCODE_X1 = 6,
- SHIFT_OPCODE_Y0 = 15,
- SHIFT_OPCODE_Y1 = 14,
- SHL16INSLI_OPCODE_X0 = 7,
- SHL16INSLI_OPCODE_X1 = 7,
- SHL1ADDX_RRR_0_OPCODE_X0 = 67,
- SHL1ADDX_RRR_0_OPCODE_X1 = 31,
- SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
- SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
- SHL1ADD_RRR_0_OPCODE_X0 = 68,
- SHL1ADD_RRR_0_OPCODE_X1 = 32,
- SHL1ADD_RRR_1_OPCODE_Y0 = 0,
- SHL1ADD_RRR_1_OPCODE_Y1 = 0,
- SHL2ADDX_RRR_0_OPCODE_X0 = 69,
- SHL2ADDX_RRR_0_OPCODE_X1 = 33,
- SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
- SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
- SHL2ADD_RRR_0_OPCODE_X0 = 70,
- SHL2ADD_RRR_0_OPCODE_X1 = 34,
- SHL2ADD_RRR_1_OPCODE_Y0 = 1,
- SHL2ADD_RRR_1_OPCODE_Y1 = 1,
- SHL3ADDX_RRR_0_OPCODE_X0 = 71,
- SHL3ADDX_RRR_0_OPCODE_X1 = 35,
- SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
- SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
- SHL3ADD_RRR_0_OPCODE_X0 = 72,
- SHL3ADD_RRR_0_OPCODE_X1 = 36,
- SHL3ADD_RRR_1_OPCODE_Y0 = 2,
- SHL3ADD_RRR_1_OPCODE_Y1 = 2,
- SHLI_SHIFT_OPCODE_X0 = 2,
- SHLI_SHIFT_OPCODE_X1 = 2,
- SHLI_SHIFT_OPCODE_Y0 = 1,
- SHLI_SHIFT_OPCODE_Y1 = 1,
- SHLXI_SHIFT_OPCODE_X0 = 3,
- SHLXI_SHIFT_OPCODE_X1 = 3,
- SHLX_RRR_0_OPCODE_X0 = 73,
- SHLX_RRR_0_OPCODE_X1 = 37,
- SHL_RRR_0_OPCODE_X0 = 74,
- SHL_RRR_0_OPCODE_X1 = 38,
- SHL_RRR_6_OPCODE_Y0 = 1,
- SHL_RRR_6_OPCODE_Y1 = 1,
- SHRSI_SHIFT_OPCODE_X0 = 4,
- SHRSI_SHIFT_OPCODE_X1 = 4,
- SHRSI_SHIFT_OPCODE_Y0 = 2,
- SHRSI_SHIFT_OPCODE_Y1 = 2,
- SHRS_RRR_0_OPCODE_X0 = 75,
- SHRS_RRR_0_OPCODE_X1 = 39,
- SHRS_RRR_6_OPCODE_Y0 = 2,
- SHRS_RRR_6_OPCODE_Y1 = 2,
- SHRUI_SHIFT_OPCODE_X0 = 5,
- SHRUI_SHIFT_OPCODE_X1 = 5,
- SHRUI_SHIFT_OPCODE_Y0 = 3,
- SHRUI_SHIFT_OPCODE_Y1 = 3,
- SHRUXI_SHIFT_OPCODE_X0 = 6,
- SHRUXI_SHIFT_OPCODE_X1 = 6,
- SHRUX_RRR_0_OPCODE_X0 = 76,
- SHRUX_RRR_0_OPCODE_X1 = 40,
- SHRU_RRR_0_OPCODE_X0 = 77,
- SHRU_RRR_0_OPCODE_X1 = 41,
- SHRU_RRR_6_OPCODE_Y0 = 3,
- SHRU_RRR_6_OPCODE_Y1 = 3,
- SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
- ST1_ADD_IMM8_OPCODE_X1 = 25,
- ST1_OPCODE_Y2 = 0,
- ST1_RRR_0_OPCODE_X1 = 42,
- ST2_ADD_IMM8_OPCODE_X1 = 26,
- ST2_OPCODE_Y2 = 1,
- ST2_RRR_0_OPCODE_X1 = 43,
- ST4_ADD_IMM8_OPCODE_X1 = 27,
- ST4_OPCODE_Y2 = 2,
- ST4_RRR_0_OPCODE_X1 = 44,
- STNT1_ADD_IMM8_OPCODE_X1 = 28,
- STNT1_RRR_0_OPCODE_X1 = 45,
- STNT2_ADD_IMM8_OPCODE_X1 = 29,
- STNT2_RRR_0_OPCODE_X1 = 46,
- STNT4_ADD_IMM8_OPCODE_X1 = 30,
- STNT4_RRR_0_OPCODE_X1 = 47,
- STNT_ADD_IMM8_OPCODE_X1 = 31,
- STNT_RRR_0_OPCODE_X1 = 48,
- ST_ADD_IMM8_OPCODE_X1 = 32,
- ST_OPCODE_Y2 = 3,
- ST_RRR_0_OPCODE_X1 = 49,
- SUBXSC_RRR_0_OPCODE_X0 = 79,
- SUBXSC_RRR_0_OPCODE_X1 = 50,
- SUBX_RRR_0_OPCODE_X0 = 80,
- SUBX_RRR_0_OPCODE_X1 = 51,
- SUBX_RRR_0_OPCODE_Y0 = 2,
- SUBX_RRR_0_OPCODE_Y1 = 2,
- SUB_RRR_0_OPCODE_X0 = 81,
- SUB_RRR_0_OPCODE_X1 = 52,
- SUB_RRR_0_OPCODE_Y0 = 3,
- SUB_RRR_0_OPCODE_Y1 = 3,
- SWINT0_UNARY_OPCODE_X1 = 34,
- SWINT1_UNARY_OPCODE_X1 = 35,
- SWINT2_UNARY_OPCODE_X1 = 36,
- SWINT3_UNARY_OPCODE_X1 = 37,
- TBLIDXB0_UNARY_OPCODE_X0 = 9,
- TBLIDXB0_UNARY_OPCODE_Y0 = 9,
- TBLIDXB1_UNARY_OPCODE_X0 = 10,
- TBLIDXB1_UNARY_OPCODE_Y0 = 10,
- TBLIDXB2_UNARY_OPCODE_X0 = 11,
- TBLIDXB2_UNARY_OPCODE_Y0 = 11,
- TBLIDXB3_UNARY_OPCODE_X0 = 12,
- TBLIDXB3_UNARY_OPCODE_Y0 = 12,
- UNARY_RRR_0_OPCODE_X0 = 82,
- UNARY_RRR_0_OPCODE_X1 = 53,
- UNARY_RRR_1_OPCODE_Y0 = 3,
- UNARY_RRR_1_OPCODE_Y1 = 3,
- V1ADDI_IMM8_OPCODE_X0 = 8,
- V1ADDI_IMM8_OPCODE_X1 = 33,
- V1ADDUC_RRR_0_OPCODE_X0 = 83,
- V1ADDUC_RRR_0_OPCODE_X1 = 54,
- V1ADD_RRR_0_OPCODE_X0 = 84,
- V1ADD_RRR_0_OPCODE_X1 = 55,
- V1ADIFFU_RRR_0_OPCODE_X0 = 85,
- V1AVGU_RRR_0_OPCODE_X0 = 86,
- V1CMPEQI_IMM8_OPCODE_X0 = 9,
- V1CMPEQI_IMM8_OPCODE_X1 = 34,
- V1CMPEQ_RRR_0_OPCODE_X0 = 87,
- V1CMPEQ_RRR_0_OPCODE_X1 = 56,
- V1CMPLES_RRR_0_OPCODE_X0 = 88,
- V1CMPLES_RRR_0_OPCODE_X1 = 57,
- V1CMPLEU_RRR_0_OPCODE_X0 = 89,
- V1CMPLEU_RRR_0_OPCODE_X1 = 58,
- V1CMPLTSI_IMM8_OPCODE_X0 = 10,
- V1CMPLTSI_IMM8_OPCODE_X1 = 35,
- V1CMPLTS_RRR_0_OPCODE_X0 = 90,
- V1CMPLTS_RRR_0_OPCODE_X1 = 59,
- V1CMPLTUI_IMM8_OPCODE_X0 = 11,
- V1CMPLTUI_IMM8_OPCODE_X1 = 36,
- V1CMPLTU_RRR_0_OPCODE_X0 = 91,
- V1CMPLTU_RRR_0_OPCODE_X1 = 60,
- V1CMPNE_RRR_0_OPCODE_X0 = 92,
- V1CMPNE_RRR_0_OPCODE_X1 = 61,
- V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
- V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
- V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
- V1DDOTPU_RRR_0_OPCODE_X0 = 162,
- V1DOTPA_RRR_0_OPCODE_X0 = 95,
- V1DOTPUA_RRR_0_OPCODE_X0 = 163,
- V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
- V1DOTPUS_RRR_0_OPCODE_X0 = 97,
- V1DOTPU_RRR_0_OPCODE_X0 = 164,
- V1DOTP_RRR_0_OPCODE_X0 = 98,
- V1INT_H_RRR_0_OPCODE_X0 = 99,
- V1INT_H_RRR_0_OPCODE_X1 = 62,
- V1INT_L_RRR_0_OPCODE_X0 = 100,
- V1INT_L_RRR_0_OPCODE_X1 = 63,
- V1MAXUI_IMM8_OPCODE_X0 = 12,
- V1MAXUI_IMM8_OPCODE_X1 = 37,
- V1MAXU_RRR_0_OPCODE_X0 = 101,
- V1MAXU_RRR_0_OPCODE_X1 = 64,
- V1MINUI_IMM8_OPCODE_X0 = 13,
- V1MINUI_IMM8_OPCODE_X1 = 38,
- V1MINU_RRR_0_OPCODE_X0 = 102,
- V1MINU_RRR_0_OPCODE_X1 = 65,
- V1MNZ_RRR_0_OPCODE_X0 = 103,
- V1MNZ_RRR_0_OPCODE_X1 = 66,
- V1MULTU_RRR_0_OPCODE_X0 = 104,
- V1MULUS_RRR_0_OPCODE_X0 = 105,
- V1MULU_RRR_0_OPCODE_X0 = 106,
- V1MZ_RRR_0_OPCODE_X0 = 107,
- V1MZ_RRR_0_OPCODE_X1 = 67,
- V1SADAU_RRR_0_OPCODE_X0 = 108,
- V1SADU_RRR_0_OPCODE_X0 = 109,
- V1SHLI_SHIFT_OPCODE_X0 = 7,
- V1SHLI_SHIFT_OPCODE_X1 = 7,
- V1SHL_RRR_0_OPCODE_X0 = 110,
- V1SHL_RRR_0_OPCODE_X1 = 68,
- V1SHRSI_SHIFT_OPCODE_X0 = 8,
- V1SHRSI_SHIFT_OPCODE_X1 = 8,
- V1SHRS_RRR_0_OPCODE_X0 = 111,
- V1SHRS_RRR_0_OPCODE_X1 = 69,
- V1SHRUI_SHIFT_OPCODE_X0 = 9,
- V1SHRUI_SHIFT_OPCODE_X1 = 9,
- V1SHRU_RRR_0_OPCODE_X0 = 112,
- V1SHRU_RRR_0_OPCODE_X1 = 70,
- V1SUBUC_RRR_0_OPCODE_X0 = 113,
- V1SUBUC_RRR_0_OPCODE_X1 = 71,
- V1SUB_RRR_0_OPCODE_X0 = 114,
- V1SUB_RRR_0_OPCODE_X1 = 72,
- V2ADDI_IMM8_OPCODE_X0 = 14,
- V2ADDI_IMM8_OPCODE_X1 = 39,
- V2ADDSC_RRR_0_OPCODE_X0 = 115,
- V2ADDSC_RRR_0_OPCODE_X1 = 73,
- V2ADD_RRR_0_OPCODE_X0 = 116,
- V2ADD_RRR_0_OPCODE_X1 = 74,
- V2ADIFFS_RRR_0_OPCODE_X0 = 117,
- V2AVGS_RRR_0_OPCODE_X0 = 118,
- V2CMPEQI_IMM8_OPCODE_X0 = 15,
- V2CMPEQI_IMM8_OPCODE_X1 = 40,
- V2CMPEQ_RRR_0_OPCODE_X0 = 119,
- V2CMPEQ_RRR_0_OPCODE_X1 = 75,
- V2CMPLES_RRR_0_OPCODE_X0 = 120,
- V2CMPLES_RRR_0_OPCODE_X1 = 76,
- V2CMPLEU_RRR_0_OPCODE_X0 = 121,
- V2CMPLEU_RRR_0_OPCODE_X1 = 77,
- V2CMPLTSI_IMM8_OPCODE_X0 = 16,
- V2CMPLTSI_IMM8_OPCODE_X1 = 41,
- V2CMPLTS_RRR_0_OPCODE_X0 = 122,
- V2CMPLTS_RRR_0_OPCODE_X1 = 78,
- V2CMPLTUI_IMM8_OPCODE_X0 = 17,
- V2CMPLTUI_IMM8_OPCODE_X1 = 42,
- V2CMPLTU_RRR_0_OPCODE_X0 = 123,
- V2CMPLTU_RRR_0_OPCODE_X1 = 79,
- V2CMPNE_RRR_0_OPCODE_X0 = 124,
- V2CMPNE_RRR_0_OPCODE_X1 = 80,
- V2DOTPA_RRR_0_OPCODE_X0 = 125,
- V2DOTP_RRR_0_OPCODE_X0 = 126,
- V2INT_H_RRR_0_OPCODE_X0 = 127,
- V2INT_H_RRR_0_OPCODE_X1 = 81,
- V2INT_L_RRR_0_OPCODE_X0 = 128,
- V2INT_L_RRR_0_OPCODE_X1 = 82,
- V2MAXSI_IMM8_OPCODE_X0 = 18,
- V2MAXSI_IMM8_OPCODE_X1 = 43,
- V2MAXS_RRR_0_OPCODE_X0 = 129,
- V2MAXS_RRR_0_OPCODE_X1 = 83,
- V2MINSI_IMM8_OPCODE_X0 = 19,
- V2MINSI_IMM8_OPCODE_X1 = 44,
- V2MINS_RRR_0_OPCODE_X0 = 130,
- V2MINS_RRR_0_OPCODE_X1 = 84,
- V2MNZ_RRR_0_OPCODE_X0 = 131,
- V2MNZ_RRR_0_OPCODE_X1 = 85,
- V2MULFSC_RRR_0_OPCODE_X0 = 132,
- V2MULS_RRR_0_OPCODE_X0 = 133,
- V2MULTS_RRR_0_OPCODE_X0 = 134,
- V2MZ_RRR_0_OPCODE_X0 = 135,
- V2MZ_RRR_0_OPCODE_X1 = 86,
- V2PACKH_RRR_0_OPCODE_X0 = 136,
- V2PACKH_RRR_0_OPCODE_X1 = 87,
- V2PACKL_RRR_0_OPCODE_X0 = 137,
- V2PACKL_RRR_0_OPCODE_X1 = 88,
- V2PACKUC_RRR_0_OPCODE_X0 = 138,
- V2PACKUC_RRR_0_OPCODE_X1 = 89,
- V2SADAS_RRR_0_OPCODE_X0 = 139,
- V2SADAU_RRR_0_OPCODE_X0 = 140,
- V2SADS_RRR_0_OPCODE_X0 = 141,
- V2SADU_RRR_0_OPCODE_X0 = 142,
- V2SHLI_SHIFT_OPCODE_X0 = 10,
- V2SHLI_SHIFT_OPCODE_X1 = 10,
- V2SHLSC_RRR_0_OPCODE_X0 = 143,
- V2SHLSC_RRR_0_OPCODE_X1 = 90,
- V2SHL_RRR_0_OPCODE_X0 = 144,
- V2SHL_RRR_0_OPCODE_X1 = 91,
- V2SHRSI_SHIFT_OPCODE_X0 = 11,
- V2SHRSI_SHIFT_OPCODE_X1 = 11,
- V2SHRS_RRR_0_OPCODE_X0 = 145,
- V2SHRS_RRR_0_OPCODE_X1 = 92,
- V2SHRUI_SHIFT_OPCODE_X0 = 12,
- V2SHRUI_SHIFT_OPCODE_X1 = 12,
- V2SHRU_RRR_0_OPCODE_X0 = 146,
- V2SHRU_RRR_0_OPCODE_X1 = 93,
- V2SUBSC_RRR_0_OPCODE_X0 = 147,
- V2SUBSC_RRR_0_OPCODE_X1 = 94,
- V2SUB_RRR_0_OPCODE_X0 = 148,
- V2SUB_RRR_0_OPCODE_X1 = 95,
- V4ADDSC_RRR_0_OPCODE_X0 = 149,
- V4ADDSC_RRR_0_OPCODE_X1 = 96,
- V4ADD_RRR_0_OPCODE_X0 = 150,
- V4ADD_RRR_0_OPCODE_X1 = 97,
- V4INT_H_RRR_0_OPCODE_X0 = 151,
- V4INT_H_RRR_0_OPCODE_X1 = 98,
- V4INT_L_RRR_0_OPCODE_X0 = 152,
- V4INT_L_RRR_0_OPCODE_X1 = 99,
- V4PACKSC_RRR_0_OPCODE_X0 = 153,
- V4PACKSC_RRR_0_OPCODE_X1 = 100,
- V4SHLSC_RRR_0_OPCODE_X0 = 154,
- V4SHLSC_RRR_0_OPCODE_X1 = 101,
- V4SHL_RRR_0_OPCODE_X0 = 155,
- V4SHL_RRR_0_OPCODE_X1 = 102,
- V4SHRS_RRR_0_OPCODE_X0 = 156,
- V4SHRS_RRR_0_OPCODE_X1 = 103,
- V4SHRU_RRR_0_OPCODE_X0 = 157,
- V4SHRU_RRR_0_OPCODE_X1 = 104,
- V4SUBSC_RRR_0_OPCODE_X0 = 158,
- V4SUBSC_RRR_0_OPCODE_X1 = 105,
- V4SUB_RRR_0_OPCODE_X0 = 159,
- V4SUB_RRR_0_OPCODE_X1 = 106,
- WH64_UNARY_OPCODE_X1 = 38,
- XORI_IMM8_OPCODE_X0 = 20,
- XORI_IMM8_OPCODE_X1 = 45,
- XOR_RRR_0_OPCODE_X0 = 160,
- XOR_RRR_0_OPCODE_X1 = 107,
- XOR_RRR_5_OPCODE_Y0 = 3,
- XOR_RRR_5_OPCODE_Y1 = 3
-};
-
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* __ARCH_OPCODE_H__ */
diff --git a/arch/tile/include/uapi/arch/opcode_tilepro.h b/arch/tile/include/uapi/arch/opcode_tilepro.h
deleted file mode 100644
index 0d633688de63..000000000000
--- a/arch/tile/include/uapi/arch/opcode_tilepro.h
+++ /dev/null
@@ -1,1473 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* TILEPro opcode information.
- *
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- *
- *
- *
- *
- */
-
-#ifndef __ARCH_OPCODE_H__
-#define __ARCH_OPCODE_H__
-
-#ifndef __ASSEMBLER__
-
-typedef unsigned long long tilepro_bundle_bits;
-
-/* This is the bit that determines if a bundle is in the Y encoding. */
-#define TILEPRO_BUNDLE_Y_ENCODING_MASK ((tilepro_bundle_bits)1 << 63)
-
-enum
-{
- /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
- TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
-
- /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
- TILEPRO_NUM_PIPELINE_ENCODINGS = 5,
-
- /* Log base 2 of TILEPRO_BUNDLE_SIZE_IN_BYTES. */
- TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
-
- /* Instructions take this many bytes. */
- TILEPRO_BUNDLE_SIZE_IN_BYTES = 1 << TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES,
-
- /* Log base 2 of TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES. */
- TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
-
- /* Bundles should be aligned modulo this number of bytes. */
- TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES =
- (1 << TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
-
- /* Log base 2 of TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES. */
- TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
-
- /* Static network instructions take this many bytes. */
- TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES =
- (1 << TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
-
- /* Number of registers (some are magic, such as network I/O). */
- TILEPRO_NUM_REGISTERS = 64,
-
- /* Number of static network registers. */
- TILEPRO_NUM_SN_REGISTERS = 4
-};
-
-/* Make a few "tile_" variables to simplify common code between
- architectures. */
-
-typedef tilepro_bundle_bits tile_bundle_bits;
-#define TILE_BUNDLE_SIZE_IN_BYTES TILEPRO_BUNDLE_SIZE_IN_BYTES
-#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES
-#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
- TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
-#define TILE_BPT_BUNDLE TILEPRO_BPT_BUNDLE
-
-/* 64-bit pattern for a { bpt ; nop } bundle. */
-#define TILEPRO_BPT_BUNDLE 0x400b3cae70166000ULL
-
-static __inline unsigned int
-get_BrOff_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_BrOff_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x00007fff) |
- (((unsigned int)(n >> 20)) & 0x00018000);
-}
-
-static __inline unsigned int
-get_BrType_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0xf);
-}
-
-static __inline unsigned int
-get_Dest_Imm8_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 43)) & 0x000000c0);
-}
-
-static __inline unsigned int
-get_Dest_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 2)) & 0x3);
-}
-
-static __inline unsigned int
-get_Dest_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Imm16_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xffff);
-}
-
-static __inline unsigned int
-get_Imm16_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xffff);
-}
-
-static __inline unsigned int
-get_Imm8_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xff);
-}
-
-static __inline unsigned int
-get_ImmOpcodeExtension_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 20)) & 0x7f);
-}
-
-static __inline unsigned int
-get_ImmOpcodeExtension_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 51)) & 0x7f);
-}
-
-static __inline unsigned int
-get_ImmRROpcodeExtension_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 8)) & 0x3);
-}
-
-static __inline unsigned int
-get_JOffLong_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x00007fff) |
- (((unsigned int)(n >> 20)) & 0x00018000) |
- (((unsigned int)(n >> 14)) & 0x001e0000) |
- (((unsigned int)(n >> 16)) & 0x07e00000) |
- (((unsigned int)(n >> 31)) & 0x18000000);
-}
-
-static __inline unsigned int
-get_JOff_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x00007fff) |
- (((unsigned int)(n >> 20)) & 0x00018000) |
- (((unsigned int)(n >> 14)) & 0x001e0000) |
- (((unsigned int)(n >> 16)) & 0x07e00000) |
- (((unsigned int)(n >> 31)) & 0x08000000);
-}
-
-static __inline unsigned int
-get_MF_Imm15_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x00003fff) |
- (((unsigned int)(n >> 44)) & 0x00004000);
-}
-
-static __inline unsigned int
-get_MMEnd_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MMEnd_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MMStart_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 23)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MMStart_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 54)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MT_Imm15_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 37)) & 0x00003fc0) |
- (((unsigned int)(n >> 44)) & 0x00004000);
-}
-
-static __inline unsigned int
-get_Mode(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 63)) & 0x1);
-}
-
-static __inline unsigned int
-get_NoRegOpcodeExtension_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 10)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Opcode_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 28)) & 0x7);
-}
-
-static __inline unsigned int
-get_Opcode_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 59)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 27)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 59)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y2(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 56)) & 0x7);
-}
-
-static __inline unsigned int
-get_RROpcodeExtension_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 4)) & 0xf);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x1ff);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x1ff);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3);
-}
-
-static __inline unsigned int
-get_RouteOpcodeExtension_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_S_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 27)) & 0x1);
-}
-
-static __inline unsigned int
-get_S_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 58)) & 0x1);
-}
-
-static __inline unsigned int
-get_ShAmt_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_ShAmt_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_ShAmt_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_ShAmt_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_SrcA_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y2(tilepro_bundle_bits n)
-{
- return (((n >> 26)) & 0x00000001) |
- (((unsigned int)(n >> 50)) & 0x0000003e);
-}
-
-static __inline unsigned int
-get_SrcBDest_Y2(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 20)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Src_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 17)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 48)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 17)) & 0x7);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 48)) & 0x7);
-}
-
-
-static __inline int
-sign_extend(int n, int num_bits)
-{
- int shift = (int)(sizeof(int) * 8 - num_bits);
- return (n << shift) >> shift;
-}
-
-
-
-static __inline tilepro_bundle_bits
-create_BrOff_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_BrOff_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) |
- (((tilepro_bundle_bits)(n & 0x00018000)) << 20);
-}
-
-static __inline tilepro_bundle_bits
-create_BrType_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xf)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_Imm8_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilepro_bundle_bits)(n & 0x000000c0)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 2);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm16_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xffff) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm16_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xffff)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_ImmOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x7f) << 20);
-}
-
-static __inline tilepro_bundle_bits
-create_ImmOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x7f)) << 51);
-}
-
-static __inline tilepro_bundle_bits
-create_ImmRROpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 8);
-}
-
-static __inline tilepro_bundle_bits
-create_JOffLong_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) |
- (((tilepro_bundle_bits)(n & 0x00018000)) << 20) |
- (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) |
- (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) |
- (((tilepro_bundle_bits)(n & 0x18000000)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_JOff_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) |
- (((tilepro_bundle_bits)(n & 0x00018000)) << 20) |
- (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) |
- (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) |
- (((tilepro_bundle_bits)(n & 0x08000000)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_MF_Imm15_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x00003fff)) << 37) |
- (((tilepro_bundle_bits)(n & 0x00004000)) << 44);
-}
-
-static __inline tilepro_bundle_bits
-create_MMEnd_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 18);
-}
-
-static __inline tilepro_bundle_bits
-create_MMEnd_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 49);
-}
-
-static __inline tilepro_bundle_bits
-create_MMStart_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 23);
-}
-
-static __inline tilepro_bundle_bits
-create_MMStart_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 54);
-}
-
-static __inline tilepro_bundle_bits
-create_MT_Imm15_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilepro_bundle_bits)(n & 0x00003fc0)) << 37) |
- (((tilepro_bundle_bits)(n & 0x00004000)) << 44);
-}
-
-static __inline tilepro_bundle_bits
-create_Mode(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1)) << 63);
-}
-
-static __inline tilepro_bundle_bits
-create_NoRegOpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 10);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x7) << 28);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xf)) << 59);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 27);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xf)) << 59);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x7)) << 56);
-}
-
-static __inline tilepro_bundle_bits
-create_RROpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 4);
-}
-
-static __inline tilepro_bundle_bits
-create_RRROpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1ff) << 18);
-}
-
-static __inline tilepro_bundle_bits
-create_RRROpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1ff)) << 49);
-}
-
-static __inline tilepro_bundle_bits
-create_RRROpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 18);
-}
-
-static __inline tilepro_bundle_bits
-create_RRROpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3)) << 49);
-}
-
-static __inline tilepro_bundle_bits
-create_RouteOpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_S_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1) << 27);
-}
-
-static __inline tilepro_bundle_bits
-create_S_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1)) << 58);
-}
-
-static __inline tilepro_bundle_bits
-create_ShAmt_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_ShAmt_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_ShAmt_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_ShAmt_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x00000001) << 26) |
- (((tilepro_bundle_bits)(n & 0x0000003e)) << 50);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcBDest_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 20);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcB_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcB_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcB_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcB_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_Src_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_UnOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_UnOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_UnOpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_UnOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_UnShOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 17);
-}
-
-static __inline tilepro_bundle_bits
-create_UnShOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3ff)) << 48);
-}
-
-static __inline tilepro_bundle_bits
-create_UnShOpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x7) << 17);
-}
-
-static __inline tilepro_bundle_bits
-create_UnShOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x7)) << 48);
-}
-
-
-enum
-{
- ADDBS_U_SPECIAL_0_OPCODE_X0 = 98,
- ADDBS_U_SPECIAL_0_OPCODE_X1 = 68,
- ADDB_SPECIAL_0_OPCODE_X0 = 1,
- ADDB_SPECIAL_0_OPCODE_X1 = 1,
- ADDHS_SPECIAL_0_OPCODE_X0 = 99,
- ADDHS_SPECIAL_0_OPCODE_X1 = 69,
- ADDH_SPECIAL_0_OPCODE_X0 = 2,
- ADDH_SPECIAL_0_OPCODE_X1 = 2,
- ADDIB_IMM_0_OPCODE_X0 = 1,
- ADDIB_IMM_0_OPCODE_X1 = 1,
- ADDIH_IMM_0_OPCODE_X0 = 2,
- ADDIH_IMM_0_OPCODE_X1 = 2,
- ADDI_IMM_0_OPCODE_X0 = 3,
- ADDI_IMM_0_OPCODE_X1 = 3,
- ADDI_IMM_1_OPCODE_SN = 1,
- ADDI_OPCODE_Y0 = 9,
- ADDI_OPCODE_Y1 = 7,
- ADDLIS_OPCODE_X0 = 1,
- ADDLIS_OPCODE_X1 = 2,
- ADDLI_OPCODE_X0 = 2,
- ADDLI_OPCODE_X1 = 3,
- ADDS_SPECIAL_0_OPCODE_X0 = 96,
- ADDS_SPECIAL_0_OPCODE_X1 = 66,
- ADD_SPECIAL_0_OPCODE_X0 = 3,
- ADD_SPECIAL_0_OPCODE_X1 = 3,
- ADD_SPECIAL_0_OPCODE_Y0 = 0,
- ADD_SPECIAL_0_OPCODE_Y1 = 0,
- ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4,
- ADIFFH_SPECIAL_0_OPCODE_X0 = 5,
- ANDI_IMM_0_OPCODE_X0 = 1,
- ANDI_IMM_0_OPCODE_X1 = 4,
- ANDI_OPCODE_Y0 = 10,
- ANDI_OPCODE_Y1 = 8,
- AND_SPECIAL_0_OPCODE_X0 = 6,
- AND_SPECIAL_0_OPCODE_X1 = 4,
- AND_SPECIAL_2_OPCODE_Y0 = 0,
- AND_SPECIAL_2_OPCODE_Y1 = 0,
- AULI_OPCODE_X0 = 3,
- AULI_OPCODE_X1 = 4,
- AVGB_U_SPECIAL_0_OPCODE_X0 = 7,
- AVGH_SPECIAL_0_OPCODE_X0 = 8,
- BBNST_BRANCH_OPCODE_X1 = 15,
- BBNS_BRANCH_OPCODE_X1 = 14,
- BBNS_OPCODE_SN = 63,
- BBST_BRANCH_OPCODE_X1 = 13,
- BBS_BRANCH_OPCODE_X1 = 12,
- BBS_OPCODE_SN = 62,
- BGEZT_BRANCH_OPCODE_X1 = 7,
- BGEZ_BRANCH_OPCODE_X1 = 6,
- BGEZ_OPCODE_SN = 61,
- BGZT_BRANCH_OPCODE_X1 = 5,
- BGZ_BRANCH_OPCODE_X1 = 4,
- BGZ_OPCODE_SN = 58,
- BITX_UN_0_SHUN_0_OPCODE_X0 = 1,
- BITX_UN_0_SHUN_0_OPCODE_Y0 = 1,
- BLEZT_BRANCH_OPCODE_X1 = 11,
- BLEZ_BRANCH_OPCODE_X1 = 10,
- BLEZ_OPCODE_SN = 59,
- BLZT_BRANCH_OPCODE_X1 = 9,
- BLZ_BRANCH_OPCODE_X1 = 8,
- BLZ_OPCODE_SN = 60,
- BNZT_BRANCH_OPCODE_X1 = 3,
- BNZ_BRANCH_OPCODE_X1 = 2,
- BNZ_OPCODE_SN = 57,
- BPT_NOREG_RR_IMM_0_OPCODE_SN = 1,
- BRANCH_OPCODE_X1 = 5,
- BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2,
- BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2,
- BZT_BRANCH_OPCODE_X1 = 1,
- BZ_BRANCH_OPCODE_X1 = 0,
- BZ_OPCODE_SN = 56,
- CLZ_UN_0_SHUN_0_OPCODE_X0 = 3,
- CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3,
- CRC32_32_SPECIAL_0_OPCODE_X0 = 9,
- CRC32_8_SPECIAL_0_OPCODE_X0 = 10,
- CTZ_UN_0_SHUN_0_OPCODE_X0 = 4,
- CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4,
- DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1,
- DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2,
- DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95,
- FINV_UN_0_SHUN_0_OPCODE_X1 = 3,
- FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4,
- FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3,
- FNOP_UN_0_SHUN_0_OPCODE_X0 = 5,
- FNOP_UN_0_SHUN_0_OPCODE_X1 = 5,
- FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5,
- FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1,
- HALT_NOREG_RR_IMM_0_OPCODE_SN = 0,
- ICOH_UN_0_SHUN_0_OPCODE_X1 = 6,
- ILL_UN_0_SHUN_0_OPCODE_X1 = 7,
- ILL_UN_0_SHUN_0_OPCODE_Y1 = 2,
- IMM_0_OPCODE_SN = 0,
- IMM_0_OPCODE_X0 = 4,
- IMM_0_OPCODE_X1 = 6,
- IMM_1_OPCODE_SN = 1,
- IMM_OPCODE_0_X0 = 5,
- INTHB_SPECIAL_0_OPCODE_X0 = 11,
- INTHB_SPECIAL_0_OPCODE_X1 = 5,
- INTHH_SPECIAL_0_OPCODE_X0 = 12,
- INTHH_SPECIAL_0_OPCODE_X1 = 6,
- INTLB_SPECIAL_0_OPCODE_X0 = 13,
- INTLB_SPECIAL_0_OPCODE_X1 = 7,
- INTLH_SPECIAL_0_OPCODE_X0 = 14,
- INTLH_SPECIAL_0_OPCODE_X1 = 8,
- INV_UN_0_SHUN_0_OPCODE_X1 = 8,
- IRET_UN_0_SHUN_0_OPCODE_X1 = 9,
- JALB_OPCODE_X1 = 13,
- JALF_OPCODE_X1 = 12,
- JALRP_SPECIAL_0_OPCODE_X1 = 9,
- JALRR_IMM_1_OPCODE_SN = 3,
- JALR_RR_IMM_0_OPCODE_SN = 5,
- JALR_SPECIAL_0_OPCODE_X1 = 10,
- JB_OPCODE_X1 = 11,
- JF_OPCODE_X1 = 10,
- JRP_SPECIAL_0_OPCODE_X1 = 11,
- JRR_IMM_1_OPCODE_SN = 2,
- JR_RR_IMM_0_OPCODE_SN = 4,
- JR_SPECIAL_0_OPCODE_X1 = 12,
- LBADD_IMM_0_OPCODE_X1 = 22,
- LBADD_U_IMM_0_OPCODE_X1 = 23,
- LB_OPCODE_Y2 = 0,
- LB_UN_0_SHUN_0_OPCODE_X1 = 10,
- LB_U_OPCODE_Y2 = 1,
- LB_U_UN_0_SHUN_0_OPCODE_X1 = 11,
- LHADD_IMM_0_OPCODE_X1 = 24,
- LHADD_U_IMM_0_OPCODE_X1 = 25,
- LH_OPCODE_Y2 = 2,
- LH_UN_0_SHUN_0_OPCODE_X1 = 12,
- LH_U_OPCODE_Y2 = 3,
- LH_U_UN_0_SHUN_0_OPCODE_X1 = 13,
- LNK_SPECIAL_0_OPCODE_X1 = 13,
- LWADD_IMM_0_OPCODE_X1 = 26,
- LWADD_NA_IMM_0_OPCODE_X1 = 27,
- LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24,
- LW_OPCODE_Y2 = 4,
- LW_UN_0_SHUN_0_OPCODE_X1 = 14,
- MAXB_U_SPECIAL_0_OPCODE_X0 = 15,
- MAXB_U_SPECIAL_0_OPCODE_X1 = 14,
- MAXH_SPECIAL_0_OPCODE_X0 = 16,
- MAXH_SPECIAL_0_OPCODE_X1 = 15,
- MAXIB_U_IMM_0_OPCODE_X0 = 4,
- MAXIB_U_IMM_0_OPCODE_X1 = 5,
- MAXIH_IMM_0_OPCODE_X0 = 5,
- MAXIH_IMM_0_OPCODE_X1 = 6,
- MFSPR_IMM_0_OPCODE_X1 = 7,
- MF_UN_0_SHUN_0_OPCODE_X1 = 15,
- MINB_U_SPECIAL_0_OPCODE_X0 = 17,
- MINB_U_SPECIAL_0_OPCODE_X1 = 16,
- MINH_SPECIAL_0_OPCODE_X0 = 18,
- MINH_SPECIAL_0_OPCODE_X1 = 17,
- MINIB_U_IMM_0_OPCODE_X0 = 6,
- MINIB_U_IMM_0_OPCODE_X1 = 8,
- MINIH_IMM_0_OPCODE_X0 = 7,
- MINIH_IMM_0_OPCODE_X1 = 9,
- MM_OPCODE_X0 = 6,
- MM_OPCODE_X1 = 7,
- MNZB_SPECIAL_0_OPCODE_X0 = 19,
- MNZB_SPECIAL_0_OPCODE_X1 = 18,
- MNZH_SPECIAL_0_OPCODE_X0 = 20,
- MNZH_SPECIAL_0_OPCODE_X1 = 19,
- MNZ_SPECIAL_0_OPCODE_X0 = 21,
- MNZ_SPECIAL_0_OPCODE_X1 = 20,
- MNZ_SPECIAL_1_OPCODE_Y0 = 0,
- MNZ_SPECIAL_1_OPCODE_Y1 = 1,
- MOVEI_IMM_1_OPCODE_SN = 0,
- MOVE_RR_IMM_0_OPCODE_SN = 8,
- MTSPR_IMM_0_OPCODE_X1 = 10,
- MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22,
- MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0,
- MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23,
- MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24,
- MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1,
- MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25,
- MULHH_SS_SPECIAL_0_OPCODE_X0 = 26,
- MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0,
- MULHH_SU_SPECIAL_0_OPCODE_X0 = 27,
- MULHH_UU_SPECIAL_0_OPCODE_X0 = 28,
- MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1,
- MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29,
- MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30,
- MULHLA_US_SPECIAL_0_OPCODE_X0 = 31,
- MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32,
- MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33,
- MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0,
- MULHL_SS_SPECIAL_0_OPCODE_X0 = 34,
- MULHL_SU_SPECIAL_0_OPCODE_X0 = 35,
- MULHL_US_SPECIAL_0_OPCODE_X0 = 36,
- MULHL_UU_SPECIAL_0_OPCODE_X0 = 37,
- MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38,
- MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2,
- MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39,
- MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40,
- MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3,
- MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41,
- MULLL_SS_SPECIAL_0_OPCODE_X0 = 42,
- MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2,
- MULLL_SU_SPECIAL_0_OPCODE_X0 = 43,
- MULLL_UU_SPECIAL_0_OPCODE_X0 = 44,
- MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3,
- MVNZ_SPECIAL_0_OPCODE_X0 = 45,
- MVNZ_SPECIAL_1_OPCODE_Y0 = 1,
- MVZ_SPECIAL_0_OPCODE_X0 = 46,
- MVZ_SPECIAL_1_OPCODE_Y0 = 2,
- MZB_SPECIAL_0_OPCODE_X0 = 47,
- MZB_SPECIAL_0_OPCODE_X1 = 21,
- MZH_SPECIAL_0_OPCODE_X0 = 48,
- MZH_SPECIAL_0_OPCODE_X1 = 22,
- MZ_SPECIAL_0_OPCODE_X0 = 49,
- MZ_SPECIAL_0_OPCODE_X1 = 23,
- MZ_SPECIAL_1_OPCODE_Y0 = 3,
- MZ_SPECIAL_1_OPCODE_Y1 = 2,
- NAP_UN_0_SHUN_0_OPCODE_X1 = 16,
- NOP_NOREG_RR_IMM_0_OPCODE_SN = 2,
- NOP_UN_0_SHUN_0_OPCODE_X0 = 6,
- NOP_UN_0_SHUN_0_OPCODE_X1 = 17,
- NOP_UN_0_SHUN_0_OPCODE_Y0 = 6,
- NOP_UN_0_SHUN_0_OPCODE_Y1 = 3,
- NOREG_RR_IMM_0_OPCODE_SN = 0,
- NOR_SPECIAL_0_OPCODE_X0 = 50,
- NOR_SPECIAL_0_OPCODE_X1 = 24,
- NOR_SPECIAL_2_OPCODE_Y0 = 1,
- NOR_SPECIAL_2_OPCODE_Y1 = 1,
- ORI_IMM_0_OPCODE_X0 = 8,
- ORI_IMM_0_OPCODE_X1 = 11,
- ORI_OPCODE_Y0 = 11,
- ORI_OPCODE_Y1 = 9,
- OR_SPECIAL_0_OPCODE_X0 = 51,
- OR_SPECIAL_0_OPCODE_X1 = 25,
- OR_SPECIAL_2_OPCODE_Y0 = 2,
- OR_SPECIAL_2_OPCODE_Y1 = 2,
- PACKBS_U_SPECIAL_0_OPCODE_X0 = 103,
- PACKBS_U_SPECIAL_0_OPCODE_X1 = 73,
- PACKHB_SPECIAL_0_OPCODE_X0 = 52,
- PACKHB_SPECIAL_0_OPCODE_X1 = 26,
- PACKHS_SPECIAL_0_OPCODE_X0 = 102,
- PACKHS_SPECIAL_0_OPCODE_X1 = 72,
- PACKLB_SPECIAL_0_OPCODE_X0 = 53,
- PACKLB_SPECIAL_0_OPCODE_X1 = 27,
- PCNT_UN_0_SHUN_0_OPCODE_X0 = 7,
- PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7,
- RLI_SHUN_0_OPCODE_X0 = 1,
- RLI_SHUN_0_OPCODE_X1 = 1,
- RLI_SHUN_0_OPCODE_Y0 = 1,
- RLI_SHUN_0_OPCODE_Y1 = 1,
- RL_SPECIAL_0_OPCODE_X0 = 54,
- RL_SPECIAL_0_OPCODE_X1 = 28,
- RL_SPECIAL_3_OPCODE_Y0 = 0,
- RL_SPECIAL_3_OPCODE_Y1 = 0,
- RR_IMM_0_OPCODE_SN = 0,
- S1A_SPECIAL_0_OPCODE_X0 = 55,
- S1A_SPECIAL_0_OPCODE_X1 = 29,
- S1A_SPECIAL_0_OPCODE_Y0 = 1,
- S1A_SPECIAL_0_OPCODE_Y1 = 1,
- S2A_SPECIAL_0_OPCODE_X0 = 56,
- S2A_SPECIAL_0_OPCODE_X1 = 30,
- S2A_SPECIAL_0_OPCODE_Y0 = 2,
- S2A_SPECIAL_0_OPCODE_Y1 = 2,
- S3A_SPECIAL_0_OPCODE_X0 = 57,
- S3A_SPECIAL_0_OPCODE_X1 = 31,
- S3A_SPECIAL_5_OPCODE_Y0 = 1,
- S3A_SPECIAL_5_OPCODE_Y1 = 1,
- SADAB_U_SPECIAL_0_OPCODE_X0 = 58,
- SADAH_SPECIAL_0_OPCODE_X0 = 59,
- SADAH_U_SPECIAL_0_OPCODE_X0 = 60,
- SADB_U_SPECIAL_0_OPCODE_X0 = 61,
- SADH_SPECIAL_0_OPCODE_X0 = 62,
- SADH_U_SPECIAL_0_OPCODE_X0 = 63,
- SBADD_IMM_0_OPCODE_X1 = 28,
- SB_OPCODE_Y2 = 5,
- SB_SPECIAL_0_OPCODE_X1 = 32,
- SEQB_SPECIAL_0_OPCODE_X0 = 64,
- SEQB_SPECIAL_0_OPCODE_X1 = 33,
- SEQH_SPECIAL_0_OPCODE_X0 = 65,
- SEQH_SPECIAL_0_OPCODE_X1 = 34,
- SEQIB_IMM_0_OPCODE_X0 = 9,
- SEQIB_IMM_0_OPCODE_X1 = 12,
- SEQIH_IMM_0_OPCODE_X0 = 10,
- SEQIH_IMM_0_OPCODE_X1 = 13,
- SEQI_IMM_0_OPCODE_X0 = 11,
- SEQI_IMM_0_OPCODE_X1 = 14,
- SEQI_OPCODE_Y0 = 12,
- SEQI_OPCODE_Y1 = 10,
- SEQ_SPECIAL_0_OPCODE_X0 = 66,
- SEQ_SPECIAL_0_OPCODE_X1 = 35,
- SEQ_SPECIAL_5_OPCODE_Y0 = 2,
- SEQ_SPECIAL_5_OPCODE_Y1 = 2,
- SHADD_IMM_0_OPCODE_X1 = 29,
- SHL8II_IMM_0_OPCODE_SN = 3,
- SHLB_SPECIAL_0_OPCODE_X0 = 67,
- SHLB_SPECIAL_0_OPCODE_X1 = 36,
- SHLH_SPECIAL_0_OPCODE_X0 = 68,
- SHLH_SPECIAL_0_OPCODE_X1 = 37,
- SHLIB_SHUN_0_OPCODE_X0 = 2,
- SHLIB_SHUN_0_OPCODE_X1 = 2,
- SHLIH_SHUN_0_OPCODE_X0 = 3,
- SHLIH_SHUN_0_OPCODE_X1 = 3,
- SHLI_SHUN_0_OPCODE_X0 = 4,
- SHLI_SHUN_0_OPCODE_X1 = 4,
- SHLI_SHUN_0_OPCODE_Y0 = 2,
- SHLI_SHUN_0_OPCODE_Y1 = 2,
- SHL_SPECIAL_0_OPCODE_X0 = 69,
- SHL_SPECIAL_0_OPCODE_X1 = 38,
- SHL_SPECIAL_3_OPCODE_Y0 = 1,
- SHL_SPECIAL_3_OPCODE_Y1 = 1,
- SHR1_RR_IMM_0_OPCODE_SN = 9,
- SHRB_SPECIAL_0_OPCODE_X0 = 70,
- SHRB_SPECIAL_0_OPCODE_X1 = 39,
- SHRH_SPECIAL_0_OPCODE_X0 = 71,
- SHRH_SPECIAL_0_OPCODE_X1 = 40,
- SHRIB_SHUN_0_OPCODE_X0 = 5,
- SHRIB_SHUN_0_OPCODE_X1 = 5,
- SHRIH_SHUN_0_OPCODE_X0 = 6,
- SHRIH_SHUN_0_OPCODE_X1 = 6,
- SHRI_SHUN_0_OPCODE_X0 = 7,
- SHRI_SHUN_0_OPCODE_X1 = 7,
- SHRI_SHUN_0_OPCODE_Y0 = 3,
- SHRI_SHUN_0_OPCODE_Y1 = 3,
- SHR_SPECIAL_0_OPCODE_X0 = 72,
- SHR_SPECIAL_0_OPCODE_X1 = 41,
- SHR_SPECIAL_3_OPCODE_Y0 = 2,
- SHR_SPECIAL_3_OPCODE_Y1 = 2,
- SHUN_0_OPCODE_X0 = 7,
- SHUN_0_OPCODE_X1 = 8,
- SHUN_0_OPCODE_Y0 = 13,
- SHUN_0_OPCODE_Y1 = 11,
- SH_OPCODE_Y2 = 6,
- SH_SPECIAL_0_OPCODE_X1 = 42,
- SLTB_SPECIAL_0_OPCODE_X0 = 73,
- SLTB_SPECIAL_0_OPCODE_X1 = 43,
- SLTB_U_SPECIAL_0_OPCODE_X0 = 74,
- SLTB_U_SPECIAL_0_OPCODE_X1 = 44,
- SLTEB_SPECIAL_0_OPCODE_X0 = 75,
- SLTEB_SPECIAL_0_OPCODE_X1 = 45,
- SLTEB_U_SPECIAL_0_OPCODE_X0 = 76,
- SLTEB_U_SPECIAL_0_OPCODE_X1 = 46,
- SLTEH_SPECIAL_0_OPCODE_X0 = 77,
- SLTEH_SPECIAL_0_OPCODE_X1 = 47,
- SLTEH_U_SPECIAL_0_OPCODE_X0 = 78,
- SLTEH_U_SPECIAL_0_OPCODE_X1 = 48,
- SLTE_SPECIAL_0_OPCODE_X0 = 79,
- SLTE_SPECIAL_0_OPCODE_X1 = 49,
- SLTE_SPECIAL_4_OPCODE_Y0 = 0,
- SLTE_SPECIAL_4_OPCODE_Y1 = 0,
- SLTE_U_SPECIAL_0_OPCODE_X0 = 80,
- SLTE_U_SPECIAL_0_OPCODE_X1 = 50,
- SLTE_U_SPECIAL_4_OPCODE_Y0 = 1,
- SLTE_U_SPECIAL_4_OPCODE_Y1 = 1,
- SLTH_SPECIAL_0_OPCODE_X0 = 81,
- SLTH_SPECIAL_0_OPCODE_X1 = 51,
- SLTH_U_SPECIAL_0_OPCODE_X0 = 82,
- SLTH_U_SPECIAL_0_OPCODE_X1 = 52,
- SLTIB_IMM_0_OPCODE_X0 = 12,
- SLTIB_IMM_0_OPCODE_X1 = 15,
- SLTIB_U_IMM_0_OPCODE_X0 = 13,
- SLTIB_U_IMM_0_OPCODE_X1 = 16,
- SLTIH_IMM_0_OPCODE_X0 = 14,
- SLTIH_IMM_0_OPCODE_X1 = 17,
- SLTIH_U_IMM_0_OPCODE_X0 = 15,
- SLTIH_U_IMM_0_OPCODE_X1 = 18,
- SLTI_IMM_0_OPCODE_X0 = 16,
- SLTI_IMM_0_OPCODE_X1 = 19,
- SLTI_OPCODE_Y0 = 14,
- SLTI_OPCODE_Y1 = 12,
- SLTI_U_IMM_0_OPCODE_X0 = 17,
- SLTI_U_IMM_0_OPCODE_X1 = 20,
- SLTI_U_OPCODE_Y0 = 15,
- SLTI_U_OPCODE_Y1 = 13,
- SLT_SPECIAL_0_OPCODE_X0 = 83,
- SLT_SPECIAL_0_OPCODE_X1 = 53,
- SLT_SPECIAL_4_OPCODE_Y0 = 2,
- SLT_SPECIAL_4_OPCODE_Y1 = 2,
- SLT_U_SPECIAL_0_OPCODE_X0 = 84,
- SLT_U_SPECIAL_0_OPCODE_X1 = 54,
- SLT_U_SPECIAL_4_OPCODE_Y0 = 3,
- SLT_U_SPECIAL_4_OPCODE_Y1 = 3,
- SNEB_SPECIAL_0_OPCODE_X0 = 85,
- SNEB_SPECIAL_0_OPCODE_X1 = 55,
- SNEH_SPECIAL_0_OPCODE_X0 = 86,
- SNEH_SPECIAL_0_OPCODE_X1 = 56,
- SNE_SPECIAL_0_OPCODE_X0 = 87,
- SNE_SPECIAL_0_OPCODE_X1 = 57,
- SNE_SPECIAL_5_OPCODE_Y0 = 3,
- SNE_SPECIAL_5_OPCODE_Y1 = 3,
- SPECIAL_0_OPCODE_X0 = 0,
- SPECIAL_0_OPCODE_X1 = 1,
- SPECIAL_0_OPCODE_Y0 = 1,
- SPECIAL_0_OPCODE_Y1 = 1,
- SPECIAL_1_OPCODE_Y0 = 2,
- SPECIAL_1_OPCODE_Y1 = 2,
- SPECIAL_2_OPCODE_Y0 = 3,
- SPECIAL_2_OPCODE_Y1 = 3,
- SPECIAL_3_OPCODE_Y0 = 4,
- SPECIAL_3_OPCODE_Y1 = 4,
- SPECIAL_4_OPCODE_Y0 = 5,
- SPECIAL_4_OPCODE_Y1 = 5,
- SPECIAL_5_OPCODE_Y0 = 6,
- SPECIAL_5_OPCODE_Y1 = 6,
- SPECIAL_6_OPCODE_Y0 = 7,
- SPECIAL_7_OPCODE_Y0 = 8,
- SRAB_SPECIAL_0_OPCODE_X0 = 88,
- SRAB_SPECIAL_0_OPCODE_X1 = 58,
- SRAH_SPECIAL_0_OPCODE_X0 = 89,
- SRAH_SPECIAL_0_OPCODE_X1 = 59,
- SRAIB_SHUN_0_OPCODE_X0 = 8,
- SRAIB_SHUN_0_OPCODE_X1 = 8,
- SRAIH_SHUN_0_OPCODE_X0 = 9,
- SRAIH_SHUN_0_OPCODE_X1 = 9,
- SRAI_SHUN_0_OPCODE_X0 = 10,
- SRAI_SHUN_0_OPCODE_X1 = 10,
- SRAI_SHUN_0_OPCODE_Y0 = 4,
- SRAI_SHUN_0_OPCODE_Y1 = 4,
- SRA_SPECIAL_0_OPCODE_X0 = 90,
- SRA_SPECIAL_0_OPCODE_X1 = 60,
- SRA_SPECIAL_3_OPCODE_Y0 = 3,
- SRA_SPECIAL_3_OPCODE_Y1 = 3,
- SUBBS_U_SPECIAL_0_OPCODE_X0 = 100,
- SUBBS_U_SPECIAL_0_OPCODE_X1 = 70,
- SUBB_SPECIAL_0_OPCODE_X0 = 91,
- SUBB_SPECIAL_0_OPCODE_X1 = 61,
- SUBHS_SPECIAL_0_OPCODE_X0 = 101,
- SUBHS_SPECIAL_0_OPCODE_X1 = 71,
- SUBH_SPECIAL_0_OPCODE_X0 = 92,
- SUBH_SPECIAL_0_OPCODE_X1 = 62,
- SUBS_SPECIAL_0_OPCODE_X0 = 97,
- SUBS_SPECIAL_0_OPCODE_X1 = 67,
- SUB_SPECIAL_0_OPCODE_X0 = 93,
- SUB_SPECIAL_0_OPCODE_X1 = 63,
- SUB_SPECIAL_0_OPCODE_Y0 = 3,
- SUB_SPECIAL_0_OPCODE_Y1 = 3,
- SWADD_IMM_0_OPCODE_X1 = 30,
- SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18,
- SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19,
- SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20,
- SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21,
- SW_OPCODE_Y2 = 7,
- SW_SPECIAL_0_OPCODE_X1 = 64,
- TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8,
- TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8,
- TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9,
- TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9,
- TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10,
- TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10,
- TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11,
- TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11,
- TNS_UN_0_SHUN_0_OPCODE_X1 = 22,
- UN_0_SHUN_0_OPCODE_X0 = 11,
- UN_0_SHUN_0_OPCODE_X1 = 11,
- UN_0_SHUN_0_OPCODE_Y0 = 5,
- UN_0_SHUN_0_OPCODE_Y1 = 5,
- WH64_UN_0_SHUN_0_OPCODE_X1 = 23,
- XORI_IMM_0_OPCODE_X0 = 2,
- XORI_IMM_0_OPCODE_X1 = 21,
- XOR_SPECIAL_0_OPCODE_X0 = 94,
- XOR_SPECIAL_0_OPCODE_X1 = 65,
- XOR_SPECIAL_2_OPCODE_Y0 = 3,
- XOR_SPECIAL_2_OPCODE_Y1 = 3
-};
-
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* __ARCH_OPCODE_H__ */
diff --git a/arch/tile/include/uapi/arch/sim.h b/arch/tile/include/uapi/arch/sim.h
deleted file mode 100644
index c4183dcd2ea7..000000000000
--- a/arch/tile/include/uapi/arch/sim.h
+++ /dev/null
@@ -1,644 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file
- *
- * Provides an API for controlling the simulator at runtime.
- */
-
-/**
- * @addtogroup arch_sim
- * @{
- *
- * An API for controlling the simulator at runtime.
- *
- * The simulator's behavior can be modified while it is running.
- * For example, human-readable trace output can be enabled and disabled
- * around code of interest.
- *
- * There are two ways to modify simulator behavior:
- * programmatically, by calling various sim_* functions, and
- * interactively, by entering commands like "sim set functional true"
- * at the tile-monitor prompt. Typing "sim help" at that prompt provides
- * a list of interactive commands.
- *
- * All interactive commands can also be executed programmatically by
- * passing a string to the sim_command function.
- */
-
-#ifndef __ARCH_SIM_H__
-#define __ARCH_SIM_H__
-
-#include <arch/sim_def.h>
-#include <arch/abi.h>
-
-#ifndef __ASSEMBLER__
-
-#include <arch/spr_def.h>
-
-
-/**
- * Return true if the current program is running under a simulator,
- * rather than on real hardware. If running on hardware, other "sim_xxx()"
- * calls have no useful effect.
- */
-static inline int
-sim_is_simulator(void)
-{
- return __insn_mfspr(SPR_SIM_CONTROL) != 0;
-}
-
-
-/**
- * Checkpoint the simulator state to a checkpoint file.
- *
- * The checkpoint file name is either the default or the name specified
- * on the command line with "--checkpoint-file".
- */
-static __inline void
-sim_checkpoint(void)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_CHECKPOINT);
-}
-
-
-/**
- * Report whether or not various kinds of simulator tracing are enabled.
- *
- * @return The bitwise OR of these values:
- *
- * SIM_TRACE_CYCLES (--trace-cycles),
- * SIM_TRACE_ROUTER (--trace-router),
- * SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
- * SIM_TRACE_DISASM (--trace-disasm),
- * SIM_TRACE_STALL_INFO (--trace-stall-info)
- * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
- * SIM_TRACE_L2_CACHE (--trace-l2)
- * SIM_TRACE_LINES (--trace-lines)
- */
-static __inline unsigned int
-sim_get_tracing(void)
-{
- return __insn_mfspr(SPR_SIM_CONTROL) & SIM_TRACE_FLAG_MASK;
-}
-
-
-/**
- * Turn on or off different kinds of simulator tracing.
- *
- * @param mask Either one of these special values:
- *
- * SIM_TRACE_NONE (turns off tracing),
- * SIM_TRACE_ALL (turns on all possible tracing).
- *
- * or the bitwise OR of these values:
- *
- * SIM_TRACE_CYCLES (--trace-cycles),
- * SIM_TRACE_ROUTER (--trace-router),
- * SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
- * SIM_TRACE_DISASM (--trace-disasm),
- * SIM_TRACE_STALL_INFO (--trace-stall-info)
- * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
- * SIM_TRACE_L2_CACHE (--trace-l2)
- * SIM_TRACE_LINES (--trace-lines)
- */
-static __inline void
-sim_set_tracing(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_TRACE_SPR_ARG(mask));
-}
-
-
-/**
- * Request dumping of different kinds of simulator state.
- *
- * @param mask Either this special value:
- *
- * SIM_DUMP_ALL (dump all known state)
- *
- * or the bitwise OR of these values:
- *
- * SIM_DUMP_REGS (the register file),
- * SIM_DUMP_SPRS (the SPRs),
- * SIM_DUMP_ITLB (the iTLB),
- * SIM_DUMP_DTLB (the dTLB),
- * SIM_DUMP_L1I (the L1 I-cache),
- * SIM_DUMP_L1D (the L1 D-cache),
- * SIM_DUMP_L2 (the L2 cache),
- * SIM_DUMP_SNREGS (the switch register file),
- * SIM_DUMP_SNITLB (the switch iTLB),
- * SIM_DUMP_SNL1I (the switch L1 I-cache),
- * SIM_DUMP_BACKTRACE (the current backtrace)
- */
-static __inline void
-sim_dump(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_DUMP_SPR_ARG(mask));
-}
-
-
-/**
- * Print a string to the simulator stdout.
- *
- * @param str The string to be written.
- */
-static __inline void
-sim_print(const char* str)
-{
- for ( ; *str != '\0'; str++)
- {
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
- (*str << _SIM_CONTROL_OPERATOR_BITS));
- }
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
- (SIM_PUTC_FLUSH_BINARY << _SIM_CONTROL_OPERATOR_BITS));
-}
-
-
-/**
- * Print a string to the simulator stdout.
- *
- * @param str The string to be written (a newline is automatically added).
- */
-static __inline void
-sim_print_string(const char* str)
-{
- for ( ; *str != '\0'; str++)
- {
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
- (*str << _SIM_CONTROL_OPERATOR_BITS));
- }
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
- (SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS));
-}
-
-
-/**
- * Execute a simulator command string.
- *
- * Type 'sim help' at the tile-monitor prompt to learn what commands
- * are available. Note the use of the tile-monitor "sim" command to
- * pass commands to the simulator.
- *
- * The argument to sim_command() does not include the leading "sim"
- * prefix used at the tile-monitor prompt; for example, you might call
- * sim_command("trace disasm").
- */
-static __inline void
-sim_command(const char* str)
-{
- int c;
- do
- {
- c = *str++;
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_COMMAND |
- (c << _SIM_CONTROL_OPERATOR_BITS));
- }
- while (c);
-}
-
-
-
-#ifndef __DOXYGEN__
-
-/**
- * The underlying implementation of "_sim_syscall()".
- *
- * We use extra "and" instructions to ensure that all the values
- * we are passing to the simulator are actually valid in the registers
- * (i.e. returned from memory) prior to the SIM_CONTROL spr.
- */
-static __inline long _sim_syscall0(int val)
-{
- long result;
- __asm__ __volatile__ ("mtspr SIM_CONTROL, r0"
- : "=R00" (result) : "R00" (val));
- return result;
-}
-
-static __inline long _sim_syscall1(int val, long arg1)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result) : "R00" (val), "R01" (arg1));
- return result;
-}
-
-static __inline long _sim_syscall2(int val, long arg1, long arg2)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result)
- : "R00" (val), "R01" (arg1), "R02" (arg2));
- return result;
-}
-
-/* Note that _sim_syscall3() and higher are technically at risk of
- receiving an interrupt right before the mtspr bundle, in which case
- the register values for arguments 3 and up may still be in flight
- to the core from a stack frame reload. */
-
-static __inline long _sim_syscall3(int val, long arg1, long arg2, long arg3)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r3, r3 };"
- "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result)
- : "R00" (val), "R01" (arg1), "R02" (arg2),
- "R03" (arg3));
- return result;
-}
-
-static __inline long _sim_syscall4(int val, long arg1, long arg2, long arg3,
- long arg4)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r3, r4 };"
- "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result)
- : "R00" (val), "R01" (arg1), "R02" (arg2),
- "R03" (arg3), "R04" (arg4));
- return result;
-}
-
-static __inline long _sim_syscall5(int val, long arg1, long arg2, long arg3,
- long arg4, long arg5)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r3, r4; and zero, r5, r5 };"
- "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result)
- : "R00" (val), "R01" (arg1), "R02" (arg2),
- "R03" (arg3), "R04" (arg4), "R05" (arg5));
- return result;
-}
-
-/**
- * Make a special syscall to the simulator itself, if running under
- * simulation. This is used as the implementation of other functions
- * and should not be used outside this file.
- *
- * @param syscall_num The simulator syscall number.
- * @param nr The number of additional arguments provided.
- *
- * @return Varies by syscall.
- */
-#define _sim_syscall(syscall_num, nr, args...) \
- _sim_syscall##nr( \
- ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, \
- ##args)
-
-
-/* Values for the "access_mask" parameters below. */
-#define SIM_WATCHPOINT_READ 1
-#define SIM_WATCHPOINT_WRITE 2
-#define SIM_WATCHPOINT_EXECUTE 4
-
-
-static __inline int
-sim_add_watchpoint(unsigned int process_id,
- unsigned long address,
- unsigned long size,
- unsigned int access_mask,
- unsigned long user_data)
-{
- return _sim_syscall(SIM_SYSCALL_ADD_WATCHPOINT, 5, process_id,
- address, size, access_mask, user_data);
-}
-
-
-static __inline int
-sim_remove_watchpoint(unsigned int process_id,
- unsigned long address,
- unsigned long size,
- unsigned int access_mask,
- unsigned long user_data)
-{
- return _sim_syscall(SIM_SYSCALL_REMOVE_WATCHPOINT, 5, process_id,
- address, size, access_mask, user_data);
-}
-
-
-/**
- * Return value from sim_query_watchpoint.
- */
-struct SimQueryWatchpointStatus
-{
- /**
- * 0 if a watchpoint fired, 1 if no watchpoint fired, or -1 for
- * error (meaning a bad process_id).
- */
- int syscall_status;
-
- /**
- * The address of the watchpoint that fired (this is the address
- * passed to sim_add_watchpoint, not an address within that range
- * that actually triggered the watchpoint).
- */
- unsigned long address;
-
- /** The arbitrary user_data installed by sim_add_watchpoint. */
- unsigned long user_data;
-};
-
-
-static __inline struct SimQueryWatchpointStatus
-sim_query_watchpoint(unsigned int process_id)
-{
- struct SimQueryWatchpointStatus status;
- long val = SIM_CONTROL_SYSCALL |
- (SIM_SYSCALL_QUERY_WATCHPOINT << _SIM_CONTROL_OPERATOR_BITS);
- __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
- : "=R00" (status.syscall_status),
- "=R01" (status.address),
- "=R02" (status.user_data)
- : "R00" (val), "R01" (process_id));
- return status;
-}
-
-
-/* On the simulator, confirm lines have been evicted everywhere. */
-static __inline void
-sim_validate_lines_evicted(unsigned long long pa, unsigned long length)
-{
-#ifdef __LP64__
- _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 2, pa, length);
-#else
- _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 4,
- 0 /* dummy */, (long)(pa), (long)(pa >> 32), length);
-#endif
-}
-
-
-/* Return the current CPU speed in cycles per second. */
-static __inline long
-sim_query_cpu_speed(void)
-{
- return _sim_syscall(SIM_SYSCALL_QUERY_CPU_SPEED, 0);
-}
-
-#endif /* !__DOXYGEN__ */
-
-
-
-
-/**
- * Modify the shaping parameters of a shim.
- *
- * @param shim The shim to modify. One of:
- * SIM_CONTROL_SHAPING_GBE_0
- * SIM_CONTROL_SHAPING_GBE_1
- * SIM_CONTROL_SHAPING_GBE_2
- * SIM_CONTROL_SHAPING_GBE_3
- * SIM_CONTROL_SHAPING_XGBE_0
- * SIM_CONTROL_SHAPING_XGBE_1
- *
- * @param type The type of shaping. This should be the same type of
- * shaping that is already in place on the shim. One of:
- * SIM_CONTROL_SHAPING_MULTIPLIER
- * SIM_CONTROL_SHAPING_PPS
- * SIM_CONTROL_SHAPING_BPS
- *
- * @param units The magnitude of the rate. One of:
- * SIM_CONTROL_SHAPING_UNITS_SINGLE
- * SIM_CONTROL_SHAPING_UNITS_KILO
- * SIM_CONTROL_SHAPING_UNITS_MEGA
- * SIM_CONTROL_SHAPING_UNITS_GIGA
- *
- * @param rate The rate to which to change it. This must fit in
- * SIM_CONTROL_SHAPING_RATE_BITS bits or a warning is issued and
- * the shaping is not changed.
- *
- * @return 0 if no problems were detected in the arguments to sim_set_shaping
- * or 1 if problems were detected (for example, rate does not fit in 17 bits).
- */
-static __inline int
-sim_set_shaping(unsigned shim,
- unsigned type,
- unsigned units,
- unsigned rate)
-{
- if ((rate & ~((1 << SIM_CONTROL_SHAPING_RATE_BITS) - 1)) != 0)
- return 1;
-
- __insn_mtspr(SPR_SIM_CONTROL, SIM_SHAPING_SPR_ARG(shim, type, units, rate));
- return 0;
-}
-
-#ifdef __tilegx__
-
-/** Enable a set of mPIPE links. Pass a -1 link_mask to enable all links. */
-static __inline void
-sim_enable_mpipe_links(unsigned mpipe, unsigned long link_mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL,
- (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
- (mpipe << 8) | (1 << 16) | ((uint_reg_t)link_mask << 32)));
-}
-
-/** Disable a set of mPIPE links. Pass a -1 link_mask to disable all links. */
-static __inline void
-sim_disable_mpipe_links(unsigned mpipe, unsigned long link_mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL,
- (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
- (mpipe << 8) | (0 << 16) | ((uint_reg_t)link_mask << 32)));
-}
-
-#endif /* __tilegx__ */
-
-
-/*
- * An API for changing "functional" mode.
- */
-
-#ifndef __DOXYGEN__
-
-#define sim_enable_functional() \
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_ENABLE_FUNCTIONAL)
-
-#define sim_disable_functional() \
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_DISABLE_FUNCTIONAL)
-
-#endif /* __DOXYGEN__ */
-
-
-/*
- * Profiler support.
- */
-
-/**
- * Turn profiling on for the current task.
- *
- * Note that this has no effect if run in an environment without
- * profiling support (thus, the proper flags to the simulator must
- * be supplied).
- */
-static __inline void
-sim_profiler_enable(void)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_ENABLE);
-}
-
-
-/** Turn profiling off for the current task. */
-static __inline void
-sim_profiler_disable(void)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_DISABLE);
-}
-
-
-/**
- * Turn profiling on or off for the current task.
- *
- * @param enabled If true, turns on profiling. If false, turns it off.
- *
- * Note that this has no effect if run in an environment without
- * profiling support (thus, the proper flags to the simulator must
- * be supplied).
- */
-static __inline void
-sim_profiler_set_enabled(int enabled)
-{
- int val =
- enabled ? SIM_CONTROL_PROFILER_ENABLE : SIM_CONTROL_PROFILER_DISABLE;
- __insn_mtspr(SPR_SIM_CONTROL, val);
-}
-
-
-/**
- * Return true if and only if profiling is currently enabled
- * for the current task.
- *
- * This returns false even if sim_profiler_enable() was called
- * if the current execution environment does not support profiling.
- */
-static __inline int
-sim_profiler_is_enabled(void)
-{
- return ((__insn_mfspr(SPR_SIM_CONTROL) & SIM_PROFILER_ENABLED_MASK) != 0);
-}
-
-
-/**
- * Reset profiling counters to zero for the current task.
- *
- * Resetting can be done while profiling is enabled. It does not affect
- * the chip-wide profiling counters.
- */
-static __inline void
-sim_profiler_clear(void)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_CLEAR);
-}
-
-
-/**
- * Enable specified chip-level profiling counters.
- *
- * Does not affect the per-task profiling counters.
- *
- * @param mask Either this special value:
- *
- * SIM_CHIP_ALL (enables all chip-level components).
- *
- * or the bitwise OR of these values:
- *
- * SIM_CHIP_MEMCTL (enable all memory controllers)
- * SIM_CHIP_XAUI (enable all XAUI controllers)
- * SIM_CHIP_MPIPE (enable all MPIPE controllers)
- */
-static __inline void
-sim_profiler_chip_enable(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask));
-}
-
-
-/**
- * Disable specified chip-level profiling counters.
- *
- * Does not affect the per-task profiling counters.
- *
- * @param mask Either this special value:
- *
- * SIM_CHIP_ALL (disables all chip-level components).
- *
- * or the bitwise OR of these values:
- *
- * SIM_CHIP_MEMCTL (disable all memory controllers)
- * SIM_CHIP_XAUI (disable all XAUI controllers)
- * SIM_CHIP_MPIPE (disable all MPIPE controllers)
- */
-static __inline void
-sim_profiler_chip_disable(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask));
-}
-
-
-/**
- * Reset specified chip-level profiling counters to zero.
- *
- * Does not affect the per-task profiling counters.
- *
- * @param mask Either this special value:
- *
- * SIM_CHIP_ALL (clears all chip-level components).
- *
- * or the bitwise OR of these values:
- *
- * SIM_CHIP_MEMCTL (clear all memory controllers)
- * SIM_CHIP_XAUI (clear all XAUI controllers)
- * SIM_CHIP_MPIPE (clear all MPIPE controllers)
- */
-static __inline void
-sim_profiler_chip_clear(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask));
-}
-
-
-/*
- * Event support.
- */
-
-#ifndef __DOXYGEN__
-
-static __inline void
-sim_event_begin(unsigned int x)
-{
-#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
- __insn_mtspr(SPR_EVENT_BEGIN, x);
-#endif
-}
-
-static __inline void
-sim_event_end(unsigned int x)
-{
-#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
- __insn_mtspr(SPR_EVENT_END, x);
-#endif
-}
-
-#endif /* !__DOXYGEN__ */
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* !__ARCH_SIM_H__ */
-
-/** @} */
diff --git a/arch/tile/include/uapi/arch/sim_def.h b/arch/tile/include/uapi/arch/sim_def.h
deleted file mode 100644
index f74f9943770d..000000000000
--- a/arch/tile/include/uapi/arch/sim_def.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file
- *
- * Some low-level simulator definitions.
- */
-
-#ifndef __ARCH_SIM_DEF_H__
-#define __ARCH_SIM_DEF_H__
-
-
-/**
- * Internal: the low bits of the SIM_CONTROL_* SPR values specify
- * the operation to perform, and the remaining bits are
- * an operation-specific parameter (often unused).
- */
-#define _SIM_CONTROL_OPERATOR_BITS 8
-
-
-/*
- * Values which can be written to SPR_SIM_CONTROL.
- */
-
-/** If written to SPR_SIM_CONTROL, stops profiling. */
-#define SIM_CONTROL_PROFILER_DISABLE 0
-
-/** If written to SPR_SIM_CONTROL, starts profiling. */
-#define SIM_CONTROL_PROFILER_ENABLE 1
-
-/** If written to SPR_SIM_CONTROL, clears profiling counters. */
-#define SIM_CONTROL_PROFILER_CLEAR 2
-
-/** If written to SPR_SIM_CONTROL, checkpoints the simulator. */
-#define SIM_CONTROL_CHECKPOINT 3
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
- * sets the tracing mask to the given mask. See "sim_set_tracing()".
- */
-#define SIM_CONTROL_SET_TRACING 4
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
- * dumps the requested items of machine state to the log.
- */
-#define SIM_CONTROL_DUMP 5
-
-/** If written to SPR_SIM_CONTROL, clears chip-level profiling counters. */
-#define SIM_CONTROL_PROFILER_CHIP_CLEAR 6
-
-/** If written to SPR_SIM_CONTROL, disables chip-level profiling. */
-#define SIM_CONTROL_PROFILER_CHIP_DISABLE 7
-
-/** If written to SPR_SIM_CONTROL, enables chip-level profiling. */
-#define SIM_CONTROL_PROFILER_CHIP_ENABLE 8
-
-/** If written to SPR_SIM_CONTROL, enables chip-level functional mode */
-#define SIM_CONTROL_ENABLE_FUNCTIONAL 9
-
-/** If written to SPR_SIM_CONTROL, disables chip-level functional mode. */
-#define SIM_CONTROL_DISABLE_FUNCTIONAL 10
-
-/**
- * If written to SPR_SIM_CONTROL, enables chip-level functional mode.
- * All tiles must perform this write for functional mode to be enabled.
- * Ignored in naked boot mode unless --functional is specified.
- * WARNING: Only the hypervisor startup code should use this!
- */
-#define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * writes a string directly to the simulator output. Written to once for
- * each character in the string, plus a final NUL. Instead of NUL,
- * you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY".
- */
-/* ISSUE: Document the meaning of "newline", and the handling of NUL. */
-#define SIM_CONTROL_PUTC 12
-
-/**
- * If written to SPR_SIM_CONTROL, clears the --grind-coherence state for
- * this core. This is intended to be used before a loop that will
- * invalidate the cache by loading new data and evicting all current data.
- * Generally speaking, this API should only be used by system code.
- */
-#define SIM_CONTROL_GRINDER_CLEAR 13
-
-/** If written to SPR_SIM_CONTROL, shuts down the simulator. */
-#define SIM_CONTROL_SHUTDOWN 14
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
- * indicates that a fork syscall just created the given process.
- */
-#define SIM_CONTROL_OS_FORK 15
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
- * indicates that an exit syscall was just executed by the given process.
- */
-#define SIM_CONTROL_OS_EXIT 16
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
- * indicates that the OS just switched to the given process.
- */
-#define SIM_CONTROL_OS_SWITCH 17
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * indicates that an exec syscall was just executed. Written to once for
- * each character in the executable name, plus a final NUL.
- */
-#define SIM_CONTROL_OS_EXEC 18
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * indicates that an interpreter (PT_INTERP) was loaded. Written to once
- * for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a
- * hex load address starting with "0x", and "PATH" is the executable name.
- */
-#define SIM_CONTROL_OS_INTERP 19
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * indicates that a dll was loaded. Written to once for each character
- * in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load
- * address starting with "0x", and "PATH" is the executable name.
- */
-#define SIM_CONTROL_DLOPEN 20
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * indicates that a dll was unloaded. Written to once for each character
- * in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load
- * address starting with "0x".
- */
-#define SIM_CONTROL_DLCLOSE 21
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8),
- * indicates whether to allow data reads to remotely-cached
- * dirty cache lines to be cached locally without grinder warnings or
- * assertions (used by Linux kernel fast memcpy).
- */
-#define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22
-
-/** If written to SPR_SIM_CONTROL, enables memory tracing. */
-#define SIM_CONTROL_ENABLE_MEM_LOGGING 23
-
-/** If written to SPR_SIM_CONTROL, disables memory tracing. */
-#define SIM_CONTROL_DISABLE_MEM_LOGGING 24
-
-/**
- * If written to SPR_SIM_CONTROL, changes the shaping parameters of one of
- * the gbe or xgbe shims. Must specify the shim id, the type, the units, and
- * the rate, as defined in SIM_SHAPING_SPR_ARG.
- */
-#define SIM_CONTROL_SHAPING 25
-
-/**
- * If written to SPR_SIM_CONTROL, combined with character (shifted by 8),
- * requests that a simulator command be executed. Written to once for each
- * character in the command, plus a final NUL.
- */
-#define SIM_CONTROL_COMMAND 26
-
-/**
- * If written to SPR_SIM_CONTROL, indicates that the simulated system
- * is panicking, to allow debugging via --debug-on-panic.
- */
-#define SIM_CONTROL_PANIC 27
-
-/**
- * If written to SPR_SIM_CONTROL, triggers a simulator syscall.
- * See "sim_syscall()" for more info.
- */
-#define SIM_CONTROL_SYSCALL 32
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
- * provides the pid that subsequent SIM_CONTROL_OS_FORK writes should
- * use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH.
- */
-#define SIM_CONTROL_OS_FORK_PARENT 33
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
- * (shifted by 8), clears the pending magic data section. The cleared
- * pending magic data section and any subsequently appended magic bytes
- * will only take effect when the classifier blast programmer is run.
- */
-#define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
- * (shifted by 8) and a byte of data (shifted by 16), appends that byte
- * to the shim's pending magic data section. The pending magic data
- * section takes effect when the classifier blast programmer is run.
- */
-#define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
- * (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a
- * mask of links (shifted by 32), enable or disable the corresponding
- * mPIPE links.
- */
-#define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36
-
-
-/*
- * Syscall numbers for use with "sim_syscall()".
- */
-
-/** Syscall number for sim_add_watchpoint(). */
-#define SIM_SYSCALL_ADD_WATCHPOINT 2
-
-/** Syscall number for sim_remove_watchpoint(). */
-#define SIM_SYSCALL_REMOVE_WATCHPOINT 3
-
-/** Syscall number for sim_query_watchpoint(). */
-#define SIM_SYSCALL_QUERY_WATCHPOINT 4
-
-/**
- * Syscall number that asserts that the cache lines whose 64-bit PA
- * is passed as the second argument to sim_syscall(), and over a
- * range passed as the third argument, are no longer in cache.
- * The simulator raises an error if this is not the case.
- */
-#define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5
-
-/** Syscall number for sim_query_cpu_speed(). */
-#define SIM_SYSCALL_QUERY_CPU_SPEED 6
-
-
-/*
- * Bit masks which can be shifted by 8, combined with
- * SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL.
- */
-
-/**
- * @addtogroup arch_sim
- * @{
- */
-
-/** Enable --trace-cycle when passed to simulator_set_tracing(). */
-#define SIM_TRACE_CYCLES 0x01
-
-/** Enable --trace-router when passed to simulator_set_tracing(). */
-#define SIM_TRACE_ROUTER 0x02
-
-/** Enable --trace-register-writes when passed to simulator_set_tracing(). */
-#define SIM_TRACE_REGISTER_WRITES 0x04
-
-/** Enable --trace-disasm when passed to simulator_set_tracing(). */
-#define SIM_TRACE_DISASM 0x08
-
-/** Enable --trace-stall-info when passed to simulator_set_tracing(). */
-#define SIM_TRACE_STALL_INFO 0x10
-
-/** Enable --trace-memory-controller when passed to simulator_set_tracing(). */
-#define SIM_TRACE_MEMORY_CONTROLLER 0x20
-
-/** Enable --trace-l2 when passed to simulator_set_tracing(). */
-#define SIM_TRACE_L2_CACHE 0x40
-
-/** Enable --trace-lines when passed to simulator_set_tracing(). */
-#define SIM_TRACE_LINES 0x80
-
-/** Turn off all tracing when passed to simulator_set_tracing(). */
-#define SIM_TRACE_NONE 0
-
-/** Turn on all tracing when passed to simulator_set_tracing(). */
-#define SIM_TRACE_ALL (-1)
-
-/** @} */
-
-/** Computes the value to write to SPR_SIM_CONTROL to set tracing flags. */
-#define SIM_TRACE_SPR_ARG(mask) \
- (SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-
-/*
- * Bit masks which can be shifted by 8, combined with
- * SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL.
- */
-
-/**
- * @addtogroup arch_sim
- * @{
- */
-
-/** Dump the general-purpose registers. */
-#define SIM_DUMP_REGS 0x001
-
-/** Dump the SPRs. */
-#define SIM_DUMP_SPRS 0x002
-
-/** Dump the ITLB. */
-#define SIM_DUMP_ITLB 0x004
-
-/** Dump the DTLB. */
-#define SIM_DUMP_DTLB 0x008
-
-/** Dump the L1 I-cache. */
-#define SIM_DUMP_L1I 0x010
-
-/** Dump the L1 D-cache. */
-#define SIM_DUMP_L1D 0x020
-
-/** Dump the L2 cache. */
-#define SIM_DUMP_L2 0x040
-
-/** Dump the switch registers. */
-#define SIM_DUMP_SNREGS 0x080
-
-/** Dump the switch ITLB. */
-#define SIM_DUMP_SNITLB 0x100
-
-/** Dump the switch L1 I-cache. */
-#define SIM_DUMP_SNL1I 0x200
-
-/** Dump the current backtrace. */
-#define SIM_DUMP_BACKTRACE 0x400
-
-/** Only dump valid lines in caches. */
-#define SIM_DUMP_VALID_LINES 0x800
-
-/** Dump everything that is dumpable. */
-#define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES)
-
-/** @} */
-
-/** Computes the value to write to SPR_SIM_CONTROL to dump machine state. */
-#define SIM_DUMP_SPR_ARG(mask) \
- (SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-
-/*
- * Bit masks which can be shifted by 8, combined with
- * SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL.
- */
-
-/**
- * @addtogroup arch_sim
- * @{
- */
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the memory controllers. */
-#define SIM_CHIP_MEMCTL 0x001
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */
-#define SIM_CHIP_XAUI 0x002
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */
-#define SIM_CHIP_PCIE 0x004
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */
-#define SIM_CHIP_MPIPE 0x008
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */
-#define SIM_CHIP_TRIO 0x010
-
-/** Reference all chip devices. */
-#define SIM_CHIP_ALL (-1)
-
-/** @} */
-
-/** Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. */
-#define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \
- (SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-/** Computes the value to write to SPR_SIM_CONTROL to disable chip statistics.*/
-#define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \
- (SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-/** Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. */
-#define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \
- (SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-
-
-/* Shim bitrate controls. */
-
-/** The number of bits used to store the shim id. */
-#define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3
-
-/**
- * @addtogroup arch_sim
- * @{
- */
-
-/** Change the gbe 0 bitrate. */
-#define SIM_CONTROL_SHAPING_GBE_0 0x0
-
-/** Change the gbe 1 bitrate. */
-#define SIM_CONTROL_SHAPING_GBE_1 0x1
-
-/** Change the gbe 2 bitrate. */
-#define SIM_CONTROL_SHAPING_GBE_2 0x2
-
-/** Change the gbe 3 bitrate. */
-#define SIM_CONTROL_SHAPING_GBE_3 0x3
-
-/** Change the xgbe 0 bitrate. */
-#define SIM_CONTROL_SHAPING_XGBE_0 0x4
-
-/** Change the xgbe 1 bitrate. */
-#define SIM_CONTROL_SHAPING_XGBE_1 0x5
-
-/** The type of shaping to do. */
-#define SIM_CONTROL_SHAPING_TYPE_BITS 2
-
-/** Control the multiplier. */
-#define SIM_CONTROL_SHAPING_MULTIPLIER 0
-
-/** Control the PPS. */
-#define SIM_CONTROL_SHAPING_PPS 1
-
-/** Control the BPS. */
-#define SIM_CONTROL_SHAPING_BPS 2
-
-/** The number of bits for the units for the shaping parameter. */
-#define SIM_CONTROL_SHAPING_UNITS_BITS 2
-
-/** Provide a number in single units. */
-#define SIM_CONTROL_SHAPING_UNITS_SINGLE 0
-
-/** Provide a number in kilo units. */
-#define SIM_CONTROL_SHAPING_UNITS_KILO 1
-
-/** Provide a number in mega units. */
-#define SIM_CONTROL_SHAPING_UNITS_MEGA 2
-
-/** Provide a number in giga units. */
-#define SIM_CONTROL_SHAPING_UNITS_GIGA 3
-
-/** @} */
-
-/** How many bits are available for the rate. */
-#define SIM_CONTROL_SHAPING_RATE_BITS \
- (32 - (_SIM_CONTROL_OPERATOR_BITS + \
- SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
- SIM_CONTROL_SHAPING_TYPE_BITS + \
- SIM_CONTROL_SHAPING_UNITS_BITS))
-
-/** Computes the value to write to SPR_SIM_CONTROL to change a bitrate. */
-#define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \
- (SIM_CONTROL_SHAPING | \
- ((shim) | \
- ((type) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS)) | \
- ((units) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
- SIM_CONTROL_SHAPING_TYPE_BITS)) | \
- ((rate) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
- SIM_CONTROL_SHAPING_TYPE_BITS + \
- SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS)
-
-
-/*
- * Values returned when reading SPR_SIM_CONTROL.
- * ISSUE: These names should share a longer common prefix.
- */
-
-/**
- * When reading SPR_SIM_CONTROL, the mask of simulator tracing bits
- * (SIM_TRACE_xxx values).
- */
-#define SIM_TRACE_FLAG_MASK 0xFFFF
-
-/** When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. */
-#define SIM_PROFILER_ENABLED_MASK 0x10000
-
-
-/*
- * Special arguments for "SIM_CONTROL_PUTC".
- */
-
-/**
- * Flag value for forcing a PUTC string-flush, including
- * coordinate/cycle prefix and newline.
- */
-#define SIM_PUTC_FLUSH_STRING 0x100
-
-/**
- * Flag value for forcing a PUTC binary-data-flush, which skips the
- * prefix and does not append a newline.
- */
-#define SIM_PUTC_FLUSH_BINARY 0x101
-
-
-#endif /* __ARCH_SIM_DEF_H__ */
diff --git a/arch/tile/include/uapi/arch/spr_def.h b/arch/tile/include/uapi/arch/spr_def.h
deleted file mode 100644
index 743428615cda..000000000000
--- a/arch/tile/include/uapi/arch/spr_def.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _UAPI__ARCH_SPR_DEF_H__
-#define _UAPI__ARCH_SPR_DEF_H__
-
-/* Include the proper base SPR definition file. */
-#ifdef __tilegx__
-#include <arch/spr_def_64.h>
-#else
-#include <arch/spr_def_32.h>
-#endif
-
-
-#endif /* _UAPI__ARCH_SPR_DEF_H__ */
diff --git a/arch/tile/include/uapi/arch/spr_def_32.h b/arch/tile/include/uapi/arch/spr_def_32.h
deleted file mode 100644
index 64122d6160e1..000000000000
--- a/arch/tile/include/uapi/arch/spr_def_32.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __DOXYGEN__
-
-#ifndef __ARCH_SPR_DEF_32_H__
-#define __ARCH_SPR_DEF_32_H__
-
-#define SPR_AUX_PERF_COUNT_0 0x6005
-#define SPR_AUX_PERF_COUNT_1 0x6006
-#define SPR_AUX_PERF_COUNT_CTL 0x6007
-#define SPR_AUX_PERF_COUNT_STS 0x6008
-#define SPR_CYCLE_HIGH 0x4e06
-#define SPR_CYCLE_LOW 0x4e07
-#define SPR_DMA_BYTE 0x3900
-#define SPR_DMA_CHUNK_SIZE 0x3901
-#define SPR_DMA_CTR 0x3902
-#define SPR_DMA_CTR__REQUEST_MASK 0x1
-#define SPR_DMA_CTR__SUSPEND_MASK 0x2
-#define SPR_DMA_DST_ADDR 0x3903
-#define SPR_DMA_DST_CHUNK_ADDR 0x3904
-#define SPR_DMA_SRC_ADDR 0x3905
-#define SPR_DMA_SRC_CHUNK_ADDR 0x3906
-#define SPR_DMA_STATUS__DONE_MASK 0x1
-#define SPR_DMA_STATUS__BUSY_MASK 0x2
-#define SPR_DMA_STATUS__RUNNING_MASK 0x10
-#define SPR_DMA_STRIDE 0x3907
-#define SPR_DMA_USER_STATUS 0x3908
-#define SPR_DONE 0x4e08
-#define SPR_EVENT_BEGIN 0x4e0d
-#define SPR_EVENT_END 0x4e0e
-#define SPR_EX_CONTEXT_0_0 0x4a05
-#define SPR_EX_CONTEXT_0_1 0x4a06
-#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
-#define SPR_EX_CONTEXT_1_0 0x4805
-#define SPR_EX_CONTEXT_1_1 0x4806
-#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
-#define SPR_EX_CONTEXT_2_0 0x4605
-#define SPR_EX_CONTEXT_2_1 0x4606
-#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
-#define SPR_FAIL 0x4e09
-#define SPR_IDN_AVAIL_EN 0x3e05
-#define SPR_IDN_CA_DATA 0x0b00
-#define SPR_IDN_DATA_AVAIL 0x0b03
-#define SPR_IDN_DEADLOCK_TIMEOUT 0x3406
-#define SPR_IDN_DEMUX_CA_COUNT 0x0a05
-#define SPR_IDN_DEMUX_COUNT_0 0x0a06
-#define SPR_IDN_DEMUX_COUNT_1 0x0a07
-#define SPR_IDN_DEMUX_CTL 0x0a08
-#define SPR_IDN_DEMUX_QUEUE_SEL 0x0a0a
-#define SPR_IDN_DEMUX_STATUS 0x0a0b
-#define SPR_IDN_DEMUX_WRITE_FIFO 0x0a0c
-#define SPR_IDN_DIRECTION_PROTECT 0x2e05
-#define SPR_IDN_PENDING 0x0a0e
-#define SPR_IDN_REFILL_EN 0x0e05
-#define SPR_IDN_SP_FIFO_DATA 0x0a0f
-#define SPR_IDN_SP_FIFO_SEL 0x0a10
-#define SPR_IDN_SP_FREEZE 0x0a11
-#define SPR_IDN_SP_FREEZE__SP_FRZ_MASK 0x1
-#define SPR_IDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2
-#define SPR_IDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4
-#define SPR_IDN_SP_STATE 0x0a12
-#define SPR_IDN_TAG_0 0x0a13
-#define SPR_IDN_TAG_1 0x0a14
-#define SPR_IDN_TAG_VALID 0x0a15
-#define SPR_IDN_TILE_COORD 0x0a16
-#define SPR_INTCTRL_0_STATUS 0x4a07
-#define SPR_INTCTRL_1_STATUS 0x4807
-#define SPR_INTCTRL_2_STATUS 0x4607
-#define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a
-#define SPR_INTERRUPT_MASK_0_0 0x4a08
-#define SPR_INTERRUPT_MASK_0_1 0x4a09
-#define SPR_INTERRUPT_MASK_1_0 0x4809
-#define SPR_INTERRUPT_MASK_1_1 0x480a
-#define SPR_INTERRUPT_MASK_2_0 0x4608
-#define SPR_INTERRUPT_MASK_2_1 0x4609
-#define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a
-#define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b
-#define SPR_INTERRUPT_MASK_RESET_1_0 0x480b
-#define SPR_INTERRUPT_MASK_RESET_1_1 0x480c
-#define SPR_INTERRUPT_MASK_RESET_2_0 0x460a
-#define SPR_INTERRUPT_MASK_RESET_2_1 0x460b
-#define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c
-#define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d
-#define SPR_INTERRUPT_MASK_SET_1_0 0x480d
-#define SPR_INTERRUPT_MASK_SET_1_1 0x480e
-#define SPR_INTERRUPT_MASK_SET_2_0 0x460c
-#define SPR_INTERRUPT_MASK_SET_2_1 0x460d
-#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x6000
-#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x6001
-#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x6002
-#define SPR_MPL_DMA_CPL_SET_0 0x5800
-#define SPR_MPL_DMA_CPL_SET_1 0x5801
-#define SPR_MPL_DMA_CPL_SET_2 0x5802
-#define SPR_MPL_DMA_NOTIFY_SET_0 0x3800
-#define SPR_MPL_DMA_NOTIFY_SET_1 0x3801
-#define SPR_MPL_DMA_NOTIFY_SET_2 0x3802
-#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
-#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
-#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
-#define SPR_MPL_IDN_AVAIL_SET_0 0x3e00
-#define SPR_MPL_IDN_AVAIL_SET_1 0x3e01
-#define SPR_MPL_IDN_AVAIL_SET_2 0x3e02
-#define SPR_MPL_IDN_CA_SET_0 0x3a00
-#define SPR_MPL_IDN_CA_SET_1 0x3a01
-#define SPR_MPL_IDN_CA_SET_2 0x3a02
-#define SPR_MPL_IDN_COMPLETE_SET_0 0x1200
-#define SPR_MPL_IDN_COMPLETE_SET_1 0x1201
-#define SPR_MPL_IDN_COMPLETE_SET_2 0x1202
-#define SPR_MPL_IDN_FIREWALL_SET_0 0x2e00
-#define SPR_MPL_IDN_FIREWALL_SET_1 0x2e01
-#define SPR_MPL_IDN_FIREWALL_SET_2 0x2e02
-#define SPR_MPL_IDN_REFILL_SET_0 0x0e00
-#define SPR_MPL_IDN_REFILL_SET_1 0x0e01
-#define SPR_MPL_IDN_REFILL_SET_2 0x0e02
-#define SPR_MPL_IDN_TIMER_SET_0 0x3400
-#define SPR_MPL_IDN_TIMER_SET_1 0x3401
-#define SPR_MPL_IDN_TIMER_SET_2 0x3402
-#define SPR_MPL_INTCTRL_0_SET_0 0x4a00
-#define SPR_MPL_INTCTRL_0_SET_1 0x4a01
-#define SPR_MPL_INTCTRL_0_SET_2 0x4a02
-#define SPR_MPL_INTCTRL_1_SET_0 0x4800
-#define SPR_MPL_INTCTRL_1_SET_1 0x4801
-#define SPR_MPL_INTCTRL_1_SET_2 0x4802
-#define SPR_MPL_INTCTRL_2_SET_0 0x4600
-#define SPR_MPL_INTCTRL_2_SET_1 0x4601
-#define SPR_MPL_INTCTRL_2_SET_2 0x4602
-#define SPR_MPL_PERF_COUNT_SET_0 0x4200
-#define SPR_MPL_PERF_COUNT_SET_1 0x4201
-#define SPR_MPL_PERF_COUNT_SET_2 0x4202
-#define SPR_MPL_SN_ACCESS_SET_0 0x0800
-#define SPR_MPL_SN_ACCESS_SET_1 0x0801
-#define SPR_MPL_SN_ACCESS_SET_2 0x0802
-#define SPR_MPL_SN_CPL_SET_0 0x5a00
-#define SPR_MPL_SN_CPL_SET_1 0x5a01
-#define SPR_MPL_SN_CPL_SET_2 0x5a02
-#define SPR_MPL_SN_FIREWALL_SET_0 0x2c00
-#define SPR_MPL_SN_FIREWALL_SET_1 0x2c01
-#define SPR_MPL_SN_FIREWALL_SET_2 0x2c02
-#define SPR_MPL_SN_NOTIFY_SET_0 0x2a00
-#define SPR_MPL_SN_NOTIFY_SET_1 0x2a01
-#define SPR_MPL_SN_NOTIFY_SET_2 0x2a02
-#define SPR_MPL_UDN_ACCESS_SET_0 0x0c00
-#define SPR_MPL_UDN_ACCESS_SET_1 0x0c01
-#define SPR_MPL_UDN_ACCESS_SET_2 0x0c02
-#define SPR_MPL_UDN_AVAIL_SET_0 0x4000
-#define SPR_MPL_UDN_AVAIL_SET_1 0x4001
-#define SPR_MPL_UDN_AVAIL_SET_2 0x4002
-#define SPR_MPL_UDN_CA_SET_0 0x3c00
-#define SPR_MPL_UDN_CA_SET_1 0x3c01
-#define SPR_MPL_UDN_CA_SET_2 0x3c02
-#define SPR_MPL_UDN_COMPLETE_SET_0 0x1400
-#define SPR_MPL_UDN_COMPLETE_SET_1 0x1401
-#define SPR_MPL_UDN_COMPLETE_SET_2 0x1402
-#define SPR_MPL_UDN_FIREWALL_SET_0 0x3000
-#define SPR_MPL_UDN_FIREWALL_SET_1 0x3001
-#define SPR_MPL_UDN_FIREWALL_SET_2 0x3002
-#define SPR_MPL_UDN_REFILL_SET_0 0x1000
-#define SPR_MPL_UDN_REFILL_SET_1 0x1001
-#define SPR_MPL_UDN_REFILL_SET_2 0x1002
-#define SPR_MPL_UDN_TIMER_SET_0 0x3600
-#define SPR_MPL_UDN_TIMER_SET_1 0x3601
-#define SPR_MPL_UDN_TIMER_SET_2 0x3602
-#define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00
-#define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01
-#define SPR_MPL_WORLD_ACCESS_SET_2 0x4e02
-#define SPR_PASS 0x4e0b
-#define SPR_PERF_COUNT_0 0x4205
-#define SPR_PERF_COUNT_1 0x4206
-#define SPR_PERF_COUNT_CTL 0x4207
-#define SPR_PERF_COUNT_DN_CTL 0x4210
-#define SPR_PERF_COUNT_STS 0x4208
-#define SPR_PROC_STATUS 0x4f00
-#define SPR_SIM_CONTROL 0x4e0c
-#define SPR_SNCTL 0x0805
-#define SPR_SNCTL__FRZFABRIC_MASK 0x1
-#define SPR_SNSTATIC 0x080c
-#define SPR_SYSTEM_SAVE_0_0 0x4b00
-#define SPR_SYSTEM_SAVE_0_1 0x4b01
-#define SPR_SYSTEM_SAVE_0_2 0x4b02
-#define SPR_SYSTEM_SAVE_0_3 0x4b03
-#define SPR_SYSTEM_SAVE_1_0 0x4900
-#define SPR_SYSTEM_SAVE_1_1 0x4901
-#define SPR_SYSTEM_SAVE_1_2 0x4902
-#define SPR_SYSTEM_SAVE_1_3 0x4903
-#define SPR_SYSTEM_SAVE_2_0 0x4700
-#define SPR_SYSTEM_SAVE_2_1 0x4701
-#define SPR_SYSTEM_SAVE_2_2 0x4702
-#define SPR_SYSTEM_SAVE_2_3 0x4703
-#define SPR_TILE_COORD 0x4c17
-#define SPR_TILE_RTF_HWM 0x4e10
-#define SPR_TILE_TIMER_CONTROL 0x3205
-#define SPR_TILE_WRITE_PENDING 0x4e0f
-#define SPR_UDN_AVAIL_EN 0x4005
-#define SPR_UDN_CA_DATA 0x0d00
-#define SPR_UDN_DATA_AVAIL 0x0d03
-#define SPR_UDN_DEADLOCK_TIMEOUT 0x3606
-#define SPR_UDN_DEMUX_CA_COUNT 0x0c05
-#define SPR_UDN_DEMUX_COUNT_0 0x0c06
-#define SPR_UDN_DEMUX_COUNT_1 0x0c07
-#define SPR_UDN_DEMUX_COUNT_2 0x0c08
-#define SPR_UDN_DEMUX_COUNT_3 0x0c09
-#define SPR_UDN_DEMUX_CTL 0x0c0a
-#define SPR_UDN_DEMUX_QUEUE_SEL 0x0c0c
-#define SPR_UDN_DEMUX_STATUS 0x0c0d
-#define SPR_UDN_DEMUX_WRITE_FIFO 0x0c0e
-#define SPR_UDN_DIRECTION_PROTECT 0x3005
-#define SPR_UDN_PENDING 0x0c10
-#define SPR_UDN_REFILL_EN 0x1005
-#define SPR_UDN_SP_FIFO_DATA 0x0c11
-#define SPR_UDN_SP_FIFO_SEL 0x0c12
-#define SPR_UDN_SP_FREEZE 0x0c13
-#define SPR_UDN_SP_FREEZE__SP_FRZ_MASK 0x1
-#define SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2
-#define SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4
-#define SPR_UDN_SP_STATE 0x0c14
-#define SPR_UDN_TAG_0 0x0c15
-#define SPR_UDN_TAG_1 0x0c16
-#define SPR_UDN_TAG_2 0x0c17
-#define SPR_UDN_TAG_3 0x0c18
-#define SPR_UDN_TAG_VALID 0x0c19
-#define SPR_UDN_TILE_COORD 0x0c1a
-#define SPR_WATCH_CTL 0x4209
-#define SPR_WATCH_MASK 0x420a
-#define SPR_WATCH_VAL 0x420b
-
-#endif /* !defined(__ARCH_SPR_DEF_32_H__) */
-
-#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/uapi/arch/spr_def_64.h b/arch/tile/include/uapi/arch/spr_def_64.h
deleted file mode 100644
index d183cbb31aa7..000000000000
--- a/arch/tile/include/uapi/arch/spr_def_64.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __DOXYGEN__
-
-#ifndef __ARCH_SPR_DEF_64_H__
-#define __ARCH_SPR_DEF_64_H__
-
-#define SPR_AUX_PERF_COUNT_0 0x2105
-#define SPR_AUX_PERF_COUNT_1 0x2106
-#define SPR_AUX_PERF_COUNT_CTL 0x2107
-#define SPR_AUX_PERF_COUNT_STS 0x2108
-#define SPR_CMPEXCH_VALUE 0x2780
-#define SPR_CYCLE 0x2781
-#define SPR_DONE 0x2705
-#define SPR_DSTREAM_PF 0x2706
-#define SPR_EVENT_BEGIN 0x2782
-#define SPR_EVENT_END 0x2783
-#define SPR_EX_CONTEXT_0_0 0x2580
-#define SPR_EX_CONTEXT_0_1 0x2581
-#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
-#define SPR_EX_CONTEXT_1_0 0x2480
-#define SPR_EX_CONTEXT_1_1 0x2481
-#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
-#define SPR_EX_CONTEXT_2_0 0x2380
-#define SPR_EX_CONTEXT_2_1 0x2381
-#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
-#define SPR_FAIL 0x2707
-#define SPR_IDN_AVAIL_EN 0x1a05
-#define SPR_IDN_DATA_AVAIL 0x0a80
-#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806
-#define SPR_IDN_DEMUX_COUNT_0 0x0a05
-#define SPR_IDN_DEMUX_COUNT_1 0x0a06
-#define SPR_IDN_DIRECTION_PROTECT 0x1405
-#define SPR_IDN_PENDING 0x0a08
-#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
-#define SPR_INTCTRL_0_STATUS 0x2505
-#define SPR_INTCTRL_1_STATUS 0x2405
-#define SPR_INTCTRL_2_STATUS 0x2305
-#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
-#define SPR_INTERRUPT_MASK_0 0x2506
-#define SPR_INTERRUPT_MASK_1 0x2406
-#define SPR_INTERRUPT_MASK_2 0x2306
-#define SPR_INTERRUPT_MASK_RESET_0 0x2507
-#define SPR_INTERRUPT_MASK_RESET_1 0x2407
-#define SPR_INTERRUPT_MASK_RESET_2 0x2307
-#define SPR_INTERRUPT_MASK_SET_0 0x2508
-#define SPR_INTERRUPT_MASK_SET_1 0x2408
-#define SPR_INTERRUPT_MASK_SET_2 0x2308
-#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
-#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
-#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
-#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
-#define SPR_IPI_EVENT_0 0x1f05
-#define SPR_IPI_EVENT_1 0x1e05
-#define SPR_IPI_EVENT_2 0x1d05
-#define SPR_IPI_EVENT_RESET_0 0x1f06
-#define SPR_IPI_EVENT_RESET_1 0x1e06
-#define SPR_IPI_EVENT_RESET_2 0x1d06
-#define SPR_IPI_EVENT_SET_0 0x1f07
-#define SPR_IPI_EVENT_SET_1 0x1e07
-#define SPR_IPI_EVENT_SET_2 0x1d07
-#define SPR_IPI_MASK_0 0x1f08
-#define SPR_IPI_MASK_1 0x1e08
-#define SPR_IPI_MASK_2 0x1d08
-#define SPR_IPI_MASK_RESET_0 0x1f09
-#define SPR_IPI_MASK_RESET_1 0x1e09
-#define SPR_IPI_MASK_RESET_2 0x1d09
-#define SPR_IPI_MASK_SET_0 0x1f0a
-#define SPR_IPI_MASK_SET_1 0x1e0a
-#define SPR_IPI_MASK_SET_2 0x1d0a
-#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100
-#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101
-#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102
-#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
-#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
-#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
-#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
-#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
-#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
-#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00
-#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01
-#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02
-#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500
-#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501
-#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502
-#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400
-#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401
-#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402
-#define SPR_MPL_IDN_TIMER_SET_0 0x1800
-#define SPR_MPL_IDN_TIMER_SET_1 0x1801
-#define SPR_MPL_IDN_TIMER_SET_2 0x1802
-#define SPR_MPL_INTCTRL_0_SET_0 0x2500
-#define SPR_MPL_INTCTRL_0_SET_1 0x2501
-#define SPR_MPL_INTCTRL_0_SET_2 0x2502
-#define SPR_MPL_INTCTRL_1_SET_0 0x2400
-#define SPR_MPL_INTCTRL_1_SET_1 0x2401
-#define SPR_MPL_INTCTRL_1_SET_2 0x2402
-#define SPR_MPL_INTCTRL_2_SET_0 0x2300
-#define SPR_MPL_INTCTRL_2_SET_1 0x2301
-#define SPR_MPL_INTCTRL_2_SET_2 0x2302
-#define SPR_MPL_IPI_0 0x1f04
-#define SPR_MPL_IPI_0_SET_0 0x1f00
-#define SPR_MPL_IPI_0_SET_1 0x1f01
-#define SPR_MPL_IPI_0_SET_2 0x1f02
-#define SPR_MPL_IPI_1 0x1e04
-#define SPR_MPL_IPI_1_SET_0 0x1e00
-#define SPR_MPL_IPI_1_SET_1 0x1e01
-#define SPR_MPL_IPI_1_SET_2 0x1e02
-#define SPR_MPL_IPI_2 0x1d04
-#define SPR_MPL_IPI_2_SET_0 0x1d00
-#define SPR_MPL_IPI_2_SET_1 0x1d01
-#define SPR_MPL_IPI_2_SET_2 0x1d02
-#define SPR_MPL_PERF_COUNT_SET_0 0x2000
-#define SPR_MPL_PERF_COUNT_SET_1 0x2001
-#define SPR_MPL_PERF_COUNT_SET_2 0x2002
-#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
-#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
-#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
-#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
-#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
-#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
-#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
-#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
-#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
-#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
-#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
-#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
-#define SPR_MPL_UDN_TIMER_SET_0 0x1900
-#define SPR_MPL_UDN_TIMER_SET_1 0x1901
-#define SPR_MPL_UDN_TIMER_SET_2 0x1902
-#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
-#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
-#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
-#define SPR_PASS 0x2709
-#define SPR_PERF_COUNT_0 0x2005
-#define SPR_PERF_COUNT_1 0x2006
-#define SPR_PERF_COUNT_CTL 0x2007
-#define SPR_PERF_COUNT_DN_CTL 0x2008
-#define SPR_PERF_COUNT_STS 0x2009
-#define SPR_PROC_STATUS 0x2784
-#define SPR_SIM_CONTROL 0x2785
-#define SPR_SINGLE_STEP_CONTROL_0 0x0405
-#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
-#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
-#define SPR_SINGLE_STEP_CONTROL_1 0x0305
-#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
-#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
-#define SPR_SINGLE_STEP_CONTROL_2 0x0205
-#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
-#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
-#define SPR_SINGLE_STEP_EN_0_0 0x250a
-#define SPR_SINGLE_STEP_EN_0_1 0x240a
-#define SPR_SINGLE_STEP_EN_0_2 0x230a
-#define SPR_SINGLE_STEP_EN_1_0 0x250b
-#define SPR_SINGLE_STEP_EN_1_1 0x240b
-#define SPR_SINGLE_STEP_EN_1_2 0x230b
-#define SPR_SINGLE_STEP_EN_2_0 0x250c
-#define SPR_SINGLE_STEP_EN_2_1 0x240c
-#define SPR_SINGLE_STEP_EN_2_2 0x230c
-#define SPR_SYSTEM_SAVE_0_0 0x2582
-#define SPR_SYSTEM_SAVE_0_1 0x2583
-#define SPR_SYSTEM_SAVE_0_2 0x2584
-#define SPR_SYSTEM_SAVE_0_3 0x2585
-#define SPR_SYSTEM_SAVE_1_0 0x2482
-#define SPR_SYSTEM_SAVE_1_1 0x2483
-#define SPR_SYSTEM_SAVE_1_2 0x2484
-#define SPR_SYSTEM_SAVE_1_3 0x2485
-#define SPR_SYSTEM_SAVE_2_0 0x2382
-#define SPR_SYSTEM_SAVE_2_1 0x2383
-#define SPR_SYSTEM_SAVE_2_2 0x2384
-#define SPR_SYSTEM_SAVE_2_3 0x2385
-#define SPR_TILE_COORD 0x270b
-#define SPR_TILE_RTF_HWM 0x270c
-#define SPR_TILE_TIMER_CONTROL 0x1605
-#define SPR_UDN_AVAIL_EN 0x1b05
-#define SPR_UDN_DATA_AVAIL 0x0b80
-#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
-#define SPR_UDN_DEMUX_COUNT_0 0x0b05
-#define SPR_UDN_DEMUX_COUNT_1 0x0b06
-#define SPR_UDN_DEMUX_COUNT_2 0x0b07
-#define SPR_UDN_DEMUX_COUNT_3 0x0b08
-#define SPR_UDN_DIRECTION_PROTECT 0x1505
-#define SPR_UDN_PENDING 0x0b0a
-#define SPR_WATCH_MASK 0x200a
-#define SPR_WATCH_VAL 0x200b
-
-#endif /* !defined(__ARCH_SPR_DEF_64_H__) */
-
-#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/uapi/asm/Kbuild b/arch/tile/include/uapi/asm/Kbuild
deleted file mode 100644
index cc439612bcd5..000000000000
--- a/arch/tile/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,24 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += bpf_perf_event.h
-generic-y += errno.h
-generic-y += fcntl.h
-generic-y += ioctl.h
-generic-y += ioctls.h
-generic-y += ipcbuf.h
-generic-y += msgbuf.h
-generic-y += param.h
-generic-y += poll.h
-generic-y += posix_types.h
-generic-y += resource.h
-generic-y += sembuf.h
-generic-y += shmbuf.h
-generic-y += shmparam.h
-generic-y += socket.h
-generic-y += sockios.h
-generic-y += statfs.h
-generic-y += termbits.h
-generic-y += termios.h
-generic-y += types.h
-generic-y += ucontext.h
diff --git a/arch/tile/include/uapi/asm/auxvec.h b/arch/tile/include/uapi/asm/auxvec.h
deleted file mode 100644
index 922383ce8f4f..000000000000
--- a/arch/tile/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_AUXVEC_H
-#define _ASM_TILE_AUXVEC_H
-
-/* The vDSO location. */
-#define AT_SYSINFO_EHDR 33
-
-#define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */
-
-#endif /* _ASM_TILE_AUXVEC_H */
diff --git a/arch/tile/include/uapi/asm/bitsperlong.h b/arch/tile/include/uapi/asm/bitsperlong.h
deleted file mode 100644
index 57cca78c0fbb..000000000000
--- a/arch/tile/include/uapi/asm/bitsperlong.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_BITSPERLONG_H
-#define _ASM_TILE_BITSPERLONG_H
-
-#ifdef __LP64__
-# define __BITS_PER_LONG 64
-#else
-# define __BITS_PER_LONG 32
-#endif
-
-#include <asm-generic/bitsperlong.h>
-
-#endif /* _ASM_TILE_BITSPERLONG_H */
diff --git a/arch/tile/include/uapi/asm/byteorder.h b/arch/tile/include/uapi/asm/byteorder.h
deleted file mode 100644
index d508e61c1e56..000000000000
--- a/arch/tile/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#if defined (__BIG_ENDIAN__)
-#include <linux/byteorder/big_endian.h>
-#else
-#include <linux/byteorder/little_endian.h>
-#endif
diff --git a/arch/tile/include/uapi/asm/cachectl.h b/arch/tile/include/uapi/asm/cachectl.h
deleted file mode 100644
index ed8bac28a1b9..000000000000
--- a/arch/tile/include/uapi/asm/cachectl.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_CACHECTL_H
-#define _ASM_TILE_CACHECTL_H
-
-/*
- * Options for cacheflush system call.
- *
- * The ICACHE flush is performed on all cores currently running the
- * current process's address space. The intent is for user
- * applications to be able to modify code, invoke the system call,
- * then allow arbitrary other threads in the same address space to see
- * the newly-modified code. Passing a length of CHIP_L1I_CACHE_SIZE()
- * or more invalidates the entire icache on all cores in the address
- * spaces. (Note: currently this option invalidates the entire icache
- * regardless of the requested address and length, but we may choose
- * to honor the arguments at some point.)
- *
- * Flush and invalidation of memory can normally be performed with the
- * __insn_flush() and __insn_finv() instructions from userspace.
- * The DCACHE option to the system call allows userspace
- * to flush the entire L1+L2 data cache from the core. In this case,
- * the address and length arguments are not used. The DCACHE flush is
- * restricted to the current core, not all cores in the address space.
- */
-#define ICACHE (1<<0) /* invalidate L1 instruction cache */
-#define DCACHE (1<<1) /* flush and invalidate data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-#endif /* _ASM_TILE_CACHECTL_H */
diff --git a/arch/tile/include/uapi/asm/hardwall.h b/arch/tile/include/uapi/asm/hardwall.h
deleted file mode 100644
index f02e9132ae71..000000000000
--- a/arch/tile/include/uapi/asm/hardwall.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Provide methods for access control of per-cpu resources like
- * UDN, IDN, or IPI.
- */
-
-#ifndef _UAPI_ASM_TILE_HARDWALL_H
-#define _UAPI_ASM_TILE_HARDWALL_H
-
-#include <arch/chip.h>
-#include <linux/ioctl.h>
-
-#define HARDWALL_IOCTL_BASE 0xa2
-
-/*
- * The HARDWALL_CREATE() ioctl is a macro with a "size" argument.
- * The resulting ioctl value is passed to the kernel in conjunction
- * with a pointer to a standard kernel bitmask of cpus.
- * For network resources (UDN or IDN) the bitmask must physically
- * represent a rectangular configuration on the chip.
- * The "size" is the number of bytes of cpu mask data.
- */
-#define _HARDWALL_CREATE 1
-#define HARDWALL_CREATE(size) \
- _IOC(_IOC_READ, HARDWALL_IOCTL_BASE, _HARDWALL_CREATE, (size))
-
-#define _HARDWALL_ACTIVATE 2
-#define HARDWALL_ACTIVATE \
- _IO(HARDWALL_IOCTL_BASE, _HARDWALL_ACTIVATE)
-
-#define _HARDWALL_DEACTIVATE 3
-#define HARDWALL_DEACTIVATE \
- _IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE)
-
-#define _HARDWALL_GET_ID 4
-#define HARDWALL_GET_ID \
- _IO(HARDWALL_IOCTL_BASE, _HARDWALL_GET_ID)
-
-
-#endif /* _UAPI_ASM_TILE_HARDWALL_H */
diff --git a/arch/tile/include/uapi/asm/kvm_para.h b/arch/tile/include/uapi/asm/kvm_para.h
deleted file mode 100644
index baacc4996d18..000000000000
--- a/arch/tile/include/uapi/asm/kvm_para.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/kvm_para.h>
diff --git a/arch/tile/include/uapi/asm/mman.h b/arch/tile/include/uapi/asm/mman.h
deleted file mode 100644
index 9b7add95926b..000000000000
--- a/arch/tile/include/uapi/asm/mman.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_MMAN_H
-#define _ASM_TILE_MMAN_H
-
-#include <asm-generic/mman-common.h>
-#include <arch/chip.h>
-
-/* Standard Linux flags */
-
-#define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */
-#define MAP_NONBLOCK 0x0080 /* do not block on IO */
-#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
-#define MAP_STACK MAP_GROWSDOWN /* provide convenience alias */
-#define MAP_LOCKED 0x0200 /* pages are locked */
-#define MAP_NORESERVE 0x0400 /* don't check for reservations */
-#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
-#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
-#define MAP_HUGETLB 0x4000 /* create a huge page mapping */
-
-
-/*
- * Flags for mlockall
- */
-#define MCL_CURRENT 1 /* lock all current mappings */
-#define MCL_FUTURE 2 /* lock all future mappings */
-#define MCL_ONFAULT 4 /* lock all pages that are faulted in */
-
-
-#endif /* _ASM_TILE_MMAN_H */
diff --git a/arch/tile/include/uapi/asm/ptrace.h b/arch/tile/include/uapi/asm/ptrace.h
deleted file mode 100644
index 667ed742f4dd..000000000000
--- a/arch/tile/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _UAPI_ASM_TILE_PTRACE_H
-#define _UAPI_ASM_TILE_PTRACE_H
-
-#include <arch/chip.h>
-#include <arch/abi.h>
-
-/* These must match struct pt_regs, below. */
-#if CHIP_WORD_SIZE() == 32
-#define PTREGS_OFFSET_REG(n) ((n)*4)
-#else
-#define PTREGS_OFFSET_REG(n) ((n)*8)
-#endif
-#define PTREGS_OFFSET_BASE 0
-#define PTREGS_OFFSET_TP PTREGS_OFFSET_REG(53)
-#define PTREGS_OFFSET_SP PTREGS_OFFSET_REG(54)
-#define PTREGS_OFFSET_LR PTREGS_OFFSET_REG(55)
-#define PTREGS_NR_GPRS 56
-#define PTREGS_OFFSET_PC PTREGS_OFFSET_REG(56)
-#define PTREGS_OFFSET_EX1 PTREGS_OFFSET_REG(57)
-#define PTREGS_OFFSET_FAULTNUM PTREGS_OFFSET_REG(58)
-#define PTREGS_OFFSET_ORIG_R0 PTREGS_OFFSET_REG(59)
-#define PTREGS_OFFSET_FLAGS PTREGS_OFFSET_REG(60)
-#if CHIP_HAS_CMPEXCH()
-#define PTREGS_OFFSET_CMPEXCH PTREGS_OFFSET_REG(61)
-#endif
-#define PTREGS_SIZE PTREGS_OFFSET_REG(64)
-
-
-#ifndef __ASSEMBLY__
-
-#ifndef __KERNEL__
-/* Provide appropriate length type to userspace regardless of -m32/-m64. */
-typedef uint_reg_t pt_reg_t;
-#endif
-
-/*
- * This struct defines the way the registers are stored on the stack during a
- * system call or exception. "struct sigcontext" has the same shape.
- */
-struct pt_regs {
- union {
- /* Saved main processor registers; 56..63 are special. */
- pt_reg_t regs[56];
- struct {
- pt_reg_t __regs[53];
- pt_reg_t tp; /* aliases regs[TREG_TP] */
- pt_reg_t sp; /* aliases regs[TREG_SP] */
- pt_reg_t lr; /* aliases regs[TREG_LR] */
- };
- };
-
- /* Saved special registers. */
- pt_reg_t pc; /* stored in EX_CONTEXT_K_0 */
- pt_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
- pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
- pt_reg_t orig_r0; /* r0 at syscall entry, else zero */
- pt_reg_t flags; /* flags (see below) */
-#if !CHIP_HAS_CMPEXCH()
- pt_reg_t pad[3];
-#else
- pt_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
- pt_reg_t pad[2];
-#endif
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-
-/* Support TILE-specific ptrace options, with events starting at 16. */
-#define PTRACE_EVENT_MIGRATE 16
-#define PTRACE_O_TRACEMIGRATE (1 << PTRACE_EVENT_MIGRATE)
-
-/*
- * Flag bits in pt_regs.flags that are part of the ptrace API.
- * We start our numbering higher up to avoid confusion with the
- * non-ABI kernel-internal values that use the low 16 bits.
- */
-#define PT_FLAGS_COMPAT 0x10000 /* process is an -m32 compat process */
-
-#endif /* _UAPI_ASM_TILE_PTRACE_H */
diff --git a/arch/tile/include/uapi/asm/setup.h b/arch/tile/include/uapi/asm/setup.h
deleted file mode 100644
index 6d1dfdddad6c..000000000000
--- a/arch/tile/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _UAPI_ASM_TILE_SETUP_H
-#define _UAPI_ASM_TILE_SETUP_H
-
-#define COMMAND_LINE_SIZE 2048
-
-
-#endif /* _UAPI_ASM_TILE_SETUP_H */
diff --git a/arch/tile/include/uapi/asm/sigcontext.h b/arch/tile/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 4003d5cc9202..000000000000
--- a/arch/tile/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SIGCONTEXT_H
-#define _ASM_TILE_SIGCONTEXT_H
-
-/* Don't pollute the namespace since <signal.h> includes this file. */
-#define __need_int_reg_t
-#include <arch/abi.h>
-
-/*
- * struct sigcontext has the same shape as struct pt_regs,
- * but is simplified since we know the fault is from userspace.
- */
-struct sigcontext {
- __extension__ union {
- /* General-purpose registers. */
- __uint_reg_t gregs[56];
- __extension__ struct {
- __uint_reg_t __gregs[53];
- __uint_reg_t tp; /* Aliases gregs[TREG_TP]. */
- __uint_reg_t sp; /* Aliases gregs[TREG_SP]. */
- __uint_reg_t lr; /* Aliases gregs[TREG_LR]. */
- };
- };
- __uint_reg_t pc; /* Program counter. */
- __uint_reg_t ics; /* In Interrupt Critical Section? */
- __uint_reg_t faultnum; /* Fault number. */
- __uint_reg_t pad[5];
-};
-
-#endif /* _ASM_TILE_SIGCONTEXT_H */
diff --git a/arch/tile/include/uapi/asm/siginfo.h b/arch/tile/include/uapi/asm/siginfo.h
deleted file mode 100644
index a812fcbf4267..000000000000
--- a/arch/tile/include/uapi/asm/siginfo.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SIGINFO_H
-#define _ASM_TILE_SIGINFO_H
-
-#define __ARCH_SI_TRAPNO
-
-#ifdef __LP64__
-# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
-#endif
-
-#include <asm-generic/siginfo.h>
-
-#endif /* _ASM_TILE_SIGINFO_H */
diff --git a/arch/tile/include/uapi/asm/signal.h b/arch/tile/include/uapi/asm/signal.h
deleted file mode 100644
index 7b3c814e00f0..000000000000
--- a/arch/tile/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _UAPI_ASM_TILE_SIGNAL_H
-#define _UAPI_ASM_TILE_SIGNAL_H
-
-/* Do not notify a ptracer when this signal is handled. */
-#define SA_NOPTRACE 0x02000000u
-
-/* Used in earlier Tilera releases, so keeping for binary compatibility. */
-#define SA_RESTORER 0x04000000u
-
-#include <asm-generic/signal.h>
-
-
-#endif /* _UAPI_ASM_TILE_SIGNAL_H */
diff --git a/arch/tile/include/uapi/asm/stat.h b/arch/tile/include/uapi/asm/stat.h
deleted file mode 100644
index ea03de7d67aa..000000000000
--- a/arch/tile/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
-#define __ARCH_WANT_STAT64 /* Used for compat_sys_stat64() etc. */
-#endif
-#include <asm-generic/stat.h>
diff --git a/arch/tile/include/uapi/asm/swab.h b/arch/tile/include/uapi/asm/swab.h
deleted file mode 100644
index 36952353a31d..000000000000
--- a/arch/tile/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SWAB_H
-#define _ASM_TILE_SWAB_H
-
-/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */
-#define __arch_swab32(x) __builtin_bswap32(x)
-#define __arch_swab64(x) __builtin_bswap64(x)
-#define __arch_swab16(x) (__builtin_bswap32(x) >> 16)
-
-#endif /* _ASM_TILE_SWAB_H */
diff --git a/arch/tile/include/uapi/asm/unistd.h b/arch/tile/include/uapi/asm/unistd.h
deleted file mode 100644
index 1a169ec92ef8..000000000000
--- a/arch/tile/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#define __ARCH_WANT_RENAMEAT
-#if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
-/* Use the flavor of this syscall that matches the 32-bit API better. */
-#define __ARCH_WANT_SYNC_FILE_RANGE2
-#endif
-
-/* Use the standard ABI for syscalls. */
-#include <asm-generic/unistd.h>
-
-#define NR_syscalls __NR_syscalls
-
-/* Additional Tilera-specific syscalls. */
-#define __NR_cacheflush (__NR_arch_specific_syscall + 1)
-__SYSCALL(__NR_cacheflush, sys_cacheflush)
-
-#ifndef __tilegx__
-/* "Fast" syscalls provide atomic support for 32-bit chips. */
-#define __NR_FAST_cmpxchg -1
-#define __NR_FAST_atomic_update -2
-#define __NR_FAST_cmpxchg64 -3
-#define __NR_cmpxchg_badaddr (__NR_arch_specific_syscall + 0)
-__SYSCALL(__NR_cmpxchg_badaddr, sys_cmpxchg_badaddr)
-#endif