diff options
Diffstat (limited to 'arch/x86/kernel')
| -rw-r--r-- | arch/x86/kernel/cpu/resctrl/core.c | 10 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/resctrl/rdtgroup.c | 9 |
2 files changed, 18 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 755118a9ef38..9f8be5ee5e8a 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -363,7 +363,7 @@ static void rdt_get_cdp_config(int level, int type) struct rdt_resource *r = &rdt_resources_all[type].r_resctrl; struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); - hw_res->num_closid = hw_res_l->num_closid / 2; + hw_res->num_closid = hw_res_l->num_closid; r->cache.cbm_len = r_l->cache.cbm_len; r->default_ctrl = r_l->default_ctrl; r->cache.shareable_bits = r_l->cache.shareable_bits; @@ -549,6 +549,14 @@ static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d) m.low = 0; m.high = hw_res->num_closid; + + /* + * temporary: the array is full-size, but cat_wrmsr() still re-maps + * the index. + */ + if (hw_res->conf_type != CDP_NONE) + m.high /= 2; + hw_res->msr_update(d, &m, r); return 0; } diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 61037b239327..299af12c9fe4 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2154,6 +2154,8 @@ static int schemata_list_create(void) s->res = r; s->conf_type = resctrl_to_arch_res(r)->conf_type; s->num_closid = resctrl_arch_get_num_closid(r); + if (resctrl_arch_get_cdp_enabled(r->rid)) + s->num_closid /= 2; ret = snprintf(s->name, sizeof(s->name), r->name); if (ret >= sizeof(s->name)) { @@ -2377,6 +2379,13 @@ static int reset_all_ctrls(struct rdt_resource *r) msr_param.high = hw_res->num_closid; /* + * temporary: the array is full-sized, but cat_wrmsr() still re-maps + * the index. + */ + if (hw_res->cdp_enabled) + msr_param.high /= 2; + + /* * Disable resource control for this resource by setting all * CBMs in all domains to the maximum mask value. Pick one CPU * from each domain to update the MSRs below. |