diff options
Diffstat (limited to 'drivers/clk/imx')
34 files changed, 279 insertions, 535 deletions
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index db0253fa3d64..3b393cb07295 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -1,40 +1,102 @@ # SPDX-License-Identifier: GPL-2.0 # common clock support for NXP i.MX SoC family. config MXC_CLK - bool - def_bool ARCH_MXC + tristate "IMX clock" + depends on ARCH_MXC || COMPILE_TEST config MXC_CLK_SCU - bool - depends on IMX_SCU + tristate "IMX SCU clock" + depends on ARCH_MXC || COMPILE_TEST + depends on IMX_SCU && HAVE_ARM_SMCCC + +config CLK_IMX1 + def_bool SOC_IMX1 + select MXC_CLK + +config CLK_IMX25 + def_bool SOC_IMX25 + select MXC_CLK + +config CLK_IMX27 + def_bool SOC_IMX27 + select MXC_CLK + +config CLK_IMX31 + def_bool SOC_IMX31 + select MXC_CLK + +config CLK_IMX35 + def_bool SOC_IMX35 + select MXC_CLK + +config CLK_IMX5 + def_bool SOC_IMX5 + select MXC_CLK + +config CLK_IMX6Q + def_bool SOC_IMX6Q + select MXC_CLK + +config CLK_IMX6SL + def_bool SOC_IMX6SL + select MXC_CLK + +config CLK_IMX6SLL + def_bool SOC_IMX6SLL + select MXC_CLK + +config CLK_IMX6SX + def_bool SOC_IMX6SX + select MXC_CLK + +config CLK_IMX6UL + def_bool SOC_IMX6UL + select MXC_CLK + +config CLK_IMX7D + def_bool SOC_IMX7D + select MXC_CLK + +config CLK_IMX7ULP + def_bool SOC_IMX7ULP + select MXC_CLK + +config CLK_VF610 + def_bool SOC_VF610 + select MXC_CLK config CLK_IMX8MM - bool "IMX8MM CCM Clock Driver" - depends on ARCH_MXC + tristate "IMX8MM CCM Clock Driver" + depends on ARCH_MXC || COMPILE_TEST + select MXC_CLK help Build the driver for i.MX8MM CCM Clock Driver config CLK_IMX8MN - bool "IMX8MN CCM Clock Driver" - depends on ARCH_MXC + tristate "IMX8MN CCM Clock Driver" + depends on ARCH_MXC || COMPILE_TEST + select MXC_CLK help Build the driver for i.MX8MN CCM Clock Driver config CLK_IMX8MP - bool "IMX8MP CCM Clock Driver" - depends on ARCH_MXC + tristate "IMX8MP CCM Clock Driver" + depends on ARCH_MXC || COMPILE_TEST + select MXC_CLK help Build the driver for i.MX8MP CCM Clock Driver config CLK_IMX8MQ - bool "IMX8MQ CCM Clock Driver" - depends on ARCH_MXC + tristate "IMX8MQ CCM Clock Driver" + depends on ARCH_MXC || COMPILE_TEST + select MXC_CLK help Build the driver for i.MX8MQ CCM Clock Driver config CLK_IMX8QXP - bool "IMX8QXP SCU Clock" - depends on ARCH_MXC && IMX_SCU && ARM64 + tristate "IMX8QXP SCU Clock" + depends on (ARCH_MXC && ARM64) || COMPILE_TEST + depends on IMX_SCU && HAVE_ARM_SMCCC select MXC_CLK_SCU help Build the driver for IMX8QXP SCU based clocks. diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 928f874c73d2..dd6a737d060b 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -1,48 +1,46 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_MXC_CLK) += \ - clk.o \ - clk-busy.o \ - clk-composite-8m.o \ - clk-cpu.o \ - clk-composite-7ulp.o \ - clk-divider-gate.o \ - clk-fixup-div.o \ - clk-fixup-mux.o \ - clk-frac-pll.o \ - clk-gate-exclusive.o \ - clk-gate2.o \ - clk-pfd.o \ - clk-pfdv2.o \ - clk-pllv1.o \ - clk-pllv2.o \ - clk-pllv3.o \ - clk-pllv4.o \ - clk-sscg-pll.o \ - clk-pll14xx.o - -obj-$(CONFIG_MXC_CLK_SCU) += \ - clk-scu.o \ - clk-lpcg-scu.o +mxc-clk-objs += clk.o +mxc-clk-objs += clk-busy.o +mxc-clk-objs += clk-composite-7ulp.o +mxc-clk-objs += clk-composite-8m.o +mxc-clk-objs += clk-cpu.o +mxc-clk-objs += clk-divider-gate.o +mxc-clk-objs += clk-fixup-div.o +mxc-clk-objs += clk-fixup-mux.o +mxc-clk-objs += clk-frac-pll.o +mxc-clk-objs += clk-gate2.o +mxc-clk-objs += clk-gate-exclusive.o +mxc-clk-objs += clk-pfd.o +mxc-clk-objs += clk-pfdv2.o +mxc-clk-objs += clk-pllv1.o +mxc-clk-objs += clk-pllv2.o +mxc-clk-objs += clk-pllv3.o +mxc-clk-objs += clk-pllv4.o +mxc-clk-objs += clk-pll14xx.o +mxc-clk-objs += clk-sscg-pll.o +obj-$(CONFIG_MXC_CLK) += mxc-clk.o obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o -obj-$(CONFIG_CLK_IMX8QXP) += clk-imx8qxp.o clk-imx8qxp-lpcg.o -obj-$(CONFIG_SOC_IMX1) += clk-imx1.o -obj-$(CONFIG_SOC_IMX21) += clk-imx21.o -obj-$(CONFIG_SOC_IMX25) += clk-imx25.o -obj-$(CONFIG_SOC_IMX27) += clk-imx27.o -obj-$(CONFIG_SOC_IMX31) += clk-imx31.o -obj-$(CONFIG_SOC_IMX35) += clk-imx35.o -obj-$(CONFIG_SOC_IMX5) += clk-imx5.o -obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o -obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o -obj-$(CONFIG_SOC_IMX6SLL) += clk-imx6sll.o -obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o -obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o -obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o -obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o -obj-$(CONFIG_SOC_VF610) += clk-vf610.o +obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o +clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o +clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o + +obj-$(CONFIG_CLK_IMX1) += clk-imx1.o +obj-$(CONFIG_CLK_IMX25) += clk-imx25.o +obj-$(CONFIG_CLK_IMX27) += clk-imx27.o +obj-$(CONFIG_CLK_IMX31) += clk-imx31.o +obj-$(CONFIG_CLK_IMX35) += clk-imx35.o +obj-$(CONFIG_CLK_IMX5) += clk-imx5.o +obj-$(CONFIG_CLK_IMX6Q) += clk-imx6q.o +obj-$(CONFIG_CLK_IMX6SL) += clk-imx6sl.o +obj-$(CONFIG_CLK_IMX6SLL) += clk-imx6sll.o +obj-$(CONFIG_CLK_IMX6SX) += clk-imx6sx.o +obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o +obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o +obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o +obj-$(CONFIG_CLK_VF610) += clk-vf610.o diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c index 25c863da32c7..6f17311647f3 100644 --- a/drivers/clk/imx/clk-busy.c +++ b/drivers/clk/imx/clk-busy.c @@ -4,6 +4,7 @@ * Copyright 2012 Linaro Ltd. */ +#include <linux/bits.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/io.h> diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c index b9efcc8a855d..7c4f31b31eb0 100644 --- a/drivers/clk/imx/clk-composite-7ulp.c +++ b/drivers/clk/imx/clk-composite-7ulp.c @@ -5,6 +5,7 @@ * */ +#include <linux/bits.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/slab.h> diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index d2b5af826f2c..2c309e3dc8e3 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -5,6 +5,7 @@ #include <linux/clk-provider.h> #include <linux/errno.h> +#include <linux/export.h> #include <linux/io.h> #include <linux/slab.h> @@ -215,6 +216,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, div->width = PCG_PREDIV_WIDTH; divider_ops = &imx8m_clk_composite_divider_ops; mux_ops = &clk_mux_ops; + flags |= CLK_SET_PARENT_GATE; } div->lock = &imx_ccm_lock; @@ -243,3 +245,4 @@ fail: kfree(mux); return ERR_CAST(hw); } +EXPORT_SYMBOL_GPL(imx8m_clk_hw_composite_flags); diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c index cb182bec79ba..cb6ca4cf0535 100644 --- a/drivers/clk/imx/clk-cpu.c +++ b/drivers/clk/imx/clk-cpu.c @@ -5,6 +5,7 @@ #include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/export.h> #include <linux/slab.h> #include "clk.h" @@ -104,3 +105,4 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, return hw; } +EXPORT_SYMBOL_GPL(imx_clk_hw_cpu); diff --git a/drivers/clk/imx/clk-fixup-mux.c b/drivers/clk/imx/clk-fixup-mux.c index 58a67630bb6a..c82401570c84 100644 --- a/drivers/clk/imx/clk-fixup-mux.c +++ b/drivers/clk/imx/clk-fixup-mux.c @@ -3,6 +3,7 @@ * Copyright (C) 2013 Freescale Semiconductor, Inc. */ +#include <linux/bits.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c index 101e0a300376..c703056fae85 100644 --- a/drivers/clk/imx/clk-frac-pll.c +++ b/drivers/clk/imx/clk-frac-pll.c @@ -10,6 +10,7 @@ #include <linux/clk-provider.h> #include <linux/err.h> +#include <linux/export.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/slab.h> @@ -233,3 +234,4 @@ struct clk_hw *imx_clk_hw_frac_pll(const char *name, return hw; } +EXPORT_SYMBOL_GPL(imx_clk_hw_frac_pll); diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index b87ab3c3ba1e..7eed7083f46e 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -7,6 +7,7 @@ */ #include <linux/clk-provider.h> +#include <linux/export.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/io.h> @@ -15,7 +16,7 @@ #include "clk.h" /** - * DOC: basic gatable clock which can gate and ungate it's ouput + * DOC: basic gateable clock which can gate and ungate its output * * Traits of this clock: * prepare - clk_(un)prepare only ensures parent is (un)prepared @@ -177,3 +178,4 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, return hw; } +EXPORT_SYMBOL_GPL(clk_hw_register_gate2); diff --git a/drivers/clk/imx/clk-imx21.c b/drivers/clk/imx/clk-imx21.c deleted file mode 100644 index 077b4a7123ce..000000000000 --- a/drivers/clk/imx/clk-imx21.c +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com - */ - -#include <linux/clk-provider.h> -#include <linux/clkdev.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <dt-bindings/clock/imx21-clock.h> -#include <soc/imx/timer.h> -#include <asm/irq.h> - -#include "clk.h" - -#define MX21_CCM_BASE_ADDR 0x10027000 -#define MX21_GPT1_BASE_ADDR 0x10003000 -#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) - -static void __iomem *ccm __initdata; - -/* Register offsets */ -#define CCM_CSCR (ccm + 0x00) -#define CCM_MPCTL0 (ccm + 0x04) -#define CCM_SPCTL0 (ccm + 0x0c) -#define CCM_PCDR0 (ccm + 0x18) -#define CCM_PCDR1 (ccm + 0x1c) -#define CCM_PCCR0 (ccm + 0x20) -#define CCM_PCCR1 (ccm + 0x24) - -static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", }; -static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; -static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; -static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", }; - -static struct clk *clk[IMX21_CLK_MAX]; -static struct clk_onecell_data clk_data; - -static void __init _mx21_clocks_init(unsigned long lref, unsigned long href) -{ - BUG_ON(!ccm); - - clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0); - clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref); - clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href); - clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); - clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); - - clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); - clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); - clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2); - clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); - clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); - clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1); - clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4); - clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); - clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks)); - clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); - clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); - clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3); - clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3); - - clk[IMX21_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "mpll", "mpll_sel", CCM_MPCTL0); - - clk[IMX21_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "spll", "spll_sel", CCM_SPCTL0); - - clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4); - clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); - clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); - - clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6); - clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6); - clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6); - clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6); - - clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0); - clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1); - clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2); - clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3); - clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4); - clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5); - clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6); - clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7); - clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9); - clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10); - clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11); - clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12); - clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13); - clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14); - clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15); - clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16); - clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17); - clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18); - clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19); - clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21); - clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22); - clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23); - clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24); - clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25); - clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26); - clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27); - clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28); - clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30); - clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31); - - clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23); - clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24); - clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25); - clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26); - clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27); - clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28); - clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29); - clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30); - clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31); - - imx_check_clocks(clk, ARRAY_SIZE(clk)); -} - -int __init mx21_clocks_init(unsigned long lref, unsigned long href) -{ - ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K); - - _mx21_clocks_init(lref, href); - - clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0"); - clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1"); - clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2"); - clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3"); - clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0"); - clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0"); - clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0"); - clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1"); - clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1"); - clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2"); - clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2"); - clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0"); - clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); - clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0"); - clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0"); - clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0"); - clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0"); - clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma"); - clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma"); - clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0"); - - mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1, GPT_TYPE_IMX21); - - return 0; -} - -static void __init mx21_clocks_init_dt(struct device_node *np) -{ - ccm = of_iomap(np, 0); - - _mx21_clocks_init(32768, 26000000); - - clk_data.clks = clk; - clk_data.clk_num = ARRAY_SIZE(clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -} -CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt); diff --git a/drivers/clk/imx/clk-imx27.c b/drivers/clk/imx/clk-imx27.c index a3753067fc12..5585ded8b8c6 100644 --- a/drivers/clk/imx/clk-imx27.c +++ b/drivers/clk/imx/clk-imx27.c @@ -181,79 +181,6 @@ static void __init _mx27_clocks_init(unsigned long fref) imx_print_silicon_rev("i.MX27", mx27_revision()); } -int __init mx27_clocks_init(unsigned long fref) -{ - ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K); - - _mx27_clocks_init(fref); - - clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0"); - clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1"); - clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2"); - clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3"); - clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4"); - clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5"); - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5"); - clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0"); - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0"); - clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0"); - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1"); - clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1"); - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2"); - clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2"); - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0"); - clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0"); - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1"); - clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1"); - clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2"); - clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2"); - clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0"); - clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); - clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0"); - clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0"); - clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0"); - clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27"); - clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27"); - clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27"); - clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); - clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0"); - clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0"); - clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0"); - clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma"); - clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma"); - clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0"); - clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0"); - clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0"); - clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad"); - clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0"); - clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0"); - clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); - clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); - - mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1, GPT_TYPE_IMX21); - - return 0; -} - static void __init mx27_clocks_init_dt(struct device_node *np) { struct device_node *refnp; diff --git a/drivers/clk/imx/clk-imx31.c b/drivers/clk/imx/clk-imx31.c index 4bb05e440cdd..7b13fb57d842 100644 --- a/drivers/clk/imx/clk-imx31.c +++ b/drivers/clk/imx/clk-imx31.c @@ -132,77 +132,6 @@ static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref) clk_disable_unprepare(clk[iim_gate]); } -int __init mx31_clocks_init(unsigned long fref) -{ - void __iomem *base; - - base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K); - if (!base) - panic("%s: failed to map registers\n", __func__); - - _mx31_clocks_init(base, fref); - - clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); - clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0"); - clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1"); - clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2"); - clk_register_clkdev(clk[pwm_gate], "pwm", NULL); - clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[ckil], "ref", "imx21-rtc"); - clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); - clk_register_clkdev(clk[epit1_gate], "epit", NULL); - clk_register_clkdev(clk[epit2_gate], "epit", NULL); - clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0"); - clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); - clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); - clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); - clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27"); - clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27"); - clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); - clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); - /* i.mx31 has the i.mx21 type uart */ - clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4"); - clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0"); - clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0"); - clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1"); - clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); - clk_register_clkdev(clk[firi_gate], "firi", NULL); - clk_register_clkdev(clk[ata_gate], NULL, "pata_imx"); - clk_register_clkdev(clk[rtic_gate], "rtic", NULL); - clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga"); - clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); - clk_register_clkdev(clk[iim_gate], "iim", NULL); - - - imx_register_uart_clocks(uart_clks); - mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31); - - return 0; -} - static void __init mx31_clocks_init_dt(struct device_node *np) { struct device_node *osc_np; diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c index e595f559907f..c1df03665c09 100644 --- a/drivers/clk/imx/clk-imx35.c +++ b/drivers/clk/imx/clk-imx35.c @@ -248,74 +248,6 @@ static void __init _mx35_clocks_init(void) imx_print_silicon_rev("i.MX35", mx35_revision()); } -int __init mx35_clocks_init(void) -{ - _mx35_clocks_init(); - - clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); - clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); - clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1"); - clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0"); - clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0"); - clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1"); - clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1"); - clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0"); - clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1"); - clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0"); - clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0"); - clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0"); - clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1"); - clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1"); - clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1"); - clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2"); - clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2"); - clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2"); - /* i.mx35 has the i.mx27 type fec */ - clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); - clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); - clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); - clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); - clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); - clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); - clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); - clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); - /* i.mx35 has the i.mx21 type uart */ - clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); - /* i.mx35 has the i.mx21 type rtc */ - clk_register_clkdev(clk[ckil], "ref", "imx21-rtc"); - clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); - clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); - clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27"); - clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); - clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); - clk_register_clkdev(clk[admux_gate], "audmux", NULL); - - mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31); - - return 0; -} - static void __init mx35_clocks_init_dt(struct device_node *ccm_node) { _mx35_clocks_init(); diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index ba33c79158de..b2ff187cedab 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -6,6 +6,7 @@ #include <linux/init.h> #include <linux/types.h> +#include <linux/bits.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h> diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c index 0f647d148abf..2f9361946a0e 100644 --- a/drivers/clk/imx/clk-imx6sl.c +++ b/drivers/clk/imx/clk-imx6sl.c @@ -3,6 +3,7 @@ * Copyright 2013-2014 Freescale Semiconductor, Inc. */ +#include <linux/bits.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/err.h> @@ -14,19 +15,19 @@ #include "clk.h" #define CCSR 0xc -#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) +#define BM_CCSR_PLL1_SW_CLK_SEL BIT(2) #define CACRR 0x10 #define CDHIPR 0x48 -#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define BM_CDHIPR_ARM_PODF_BUSY BIT(16) #define ARM_WAIT_DIV_396M 2 #define ARM_WAIT_DIV_792M 4 #define ARM_WAIT_DIV_996M 6 #define PLL_ARM 0x0 -#define BM_PLL_ARM_DIV_SELECT (0x7f << 0) -#define BM_PLL_ARM_POWERDOWN (1 << 12) -#define BM_PLL_ARM_ENABLE (1 << 13) -#define BM_PLL_ARM_LOCK (1 << 31) +#define BM_PLL_ARM_DIV_SELECT 0x7f +#define BM_PLL_ARM_POWERDOWN BIT(12) +#define BM_PLL_ARM_ENABLE BIT(13) +#define BM_PLL_ARM_LOCK BIT(31) #define PLL_ARM_DIV_792M 66 static const char *step_sels[] = { "osc", "pll2_pfd2", }; @@ -145,7 +146,7 @@ static void imx6sl_enable_pll_arm(bool enable) val |= BM_PLL_ARM_ENABLE; val &= ~BM_PLL_ARM_POWERDOWN; writel_relaxed(val, anatop_base + PLL_ARM); - while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) + while (!(readl_relaxed(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) ; } else { writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 89ba71271e5c..20dcce526d07 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/imx6sx-clock.h> +#include <linux/bits.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h> diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index b2057bd42e25..22d24a6a05e7 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/imx7d-clock.h> +#include <linux/bits.h> #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk-provider.h> @@ -505,72 +506,73 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) hws[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_hw_mux2("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel)); hws[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_hw_mux2("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel)); hws[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_hw_mux2("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel)); - hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel)); - hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel)); hws[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_hw_mux2("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel)); - hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel)); - hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); - hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel)); - hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); - hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel)); - hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel)); - hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel)); - hws[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_hw_mux2("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel)); - hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel)); - hws[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_hw_mux2("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel)); - hws[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_hw_mux2("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel)); - hws[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_hw_mux2("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel)); - hws[IMX7D_SAI1_ROOT_SRC] = imx_clk_hw_mux2("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel)); - hws[IMX7D_SAI2_ROOT_SRC] = imx_clk_hw_mux2("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel)); - hws[IMX7D_SAI3_ROOT_SRC] = imx_clk_hw_mux2("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel)); - hws[IMX7D_SPDIF_ROOT_SRC] = imx_clk_hw_mux2("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel)); - hws[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_hw_mux2("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel)); - hws[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_hw_mux2("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel)); - hws[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_hw_mux2("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel)); - hws[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_hw_mux2("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel)); - hws[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_hw_mux2("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel)); - hws[IMX7D_EIM_ROOT_SRC] = imx_clk_hw_mux2("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel)); - hws[IMX7D_NAND_ROOT_SRC] = imx_clk_hw_mux2("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel)); - hws[IMX7D_QSPI_ROOT_SRC] = imx_clk_hw_mux2("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel)); - hws[IMX7D_USDHC1_ROOT_SRC] = imx_clk_hw_mux2("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel)); - hws[IMX7D_USDHC2_ROOT_SRC] = imx_clk_hw_mux2("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel)); - hws[IMX7D_USDHC3_ROOT_SRC] = imx_clk_hw_mux2("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel)); - hws[IMX7D_CAN1_ROOT_SRC] = imx_clk_hw_mux2("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel)); - hws[IMX7D_CAN2_ROOT_SRC] = imx_clk_hw_mux2("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel)); - hws[IMX7D_I2C1_ROOT_SRC] = imx_clk_hw_mux2("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel)); - hws[IMX7D_I2C2_ROOT_SRC] = imx_clk_hw_mux2("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel)); - hws[IMX7D_I2C3_ROOT_SRC] = imx_clk_hw_mux2("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel)); - hws[IMX7D_I2C4_ROOT_SRC] = imx_clk_hw_mux2("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel)); - hws[IMX7D_UART1_ROOT_SRC] = imx_clk_hw_mux2("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel)); - hws[IMX7D_UART2_ROOT_SRC] = imx_clk_hw_mux2("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel)); - hws[IMX7D_UART3_ROOT_SRC] = imx_clk_hw_mux2("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel)); - hws[IMX7D_UART4_ROOT_SRC] = imx_clk_hw_mux2("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel)); - hws[IMX7D_UART5_ROOT_SRC] = imx_clk_hw_mux2("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel)); - hws[IMX7D_UART6_ROOT_SRC] = imx_clk_hw_mux2("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel)); - hws[IMX7D_UART7_ROOT_SRC] = imx_clk_hw_mux2("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel)); - hws[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_hw_mux2("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel)); - hws[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_hw_mux2("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel)); - hws[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_hw_mux2("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel)); - hws[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_hw_mux2("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel)); - hws[IMX7D_PWM1_ROOT_SRC] = imx_clk_hw_mux2("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel)); - hws[IMX7D_PWM2_ROOT_SRC] = imx_clk_hw_mux2("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel)); - hws[IMX7D_PWM3_ROOT_SRC] = imx_clk_hw_mux2("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel)); - hws[IMX7D_PWM4_ROOT_SRC] = imx_clk_hw_mux2("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel)); - hws[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_hw_mux2("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel)); - hws[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_hw_mux2("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel)); - hws[IMX7D_SIM1_ROOT_SRC] = imx_clk_hw_mux2("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel)); - hws[IMX7D_SIM2_ROOT_SRC] = imx_clk_hw_mux2("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel)); - hws[IMX7D_GPT1_ROOT_SRC] = imx_clk_hw_mux2("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel)); - hws[IMX7D_GPT2_ROOT_SRC] = imx_clk_hw_mux2("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel)); - hws[IMX7D_GPT3_ROOT_SRC] = imx_clk_hw_mux2("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel)); - hws[IMX7D_GPT4_ROOT_SRC] = imx_clk_hw_mux2("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel)); - hws[IMX7D_TRACE_ROOT_SRC] = imx_clk_hw_mux2("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel)); - hws[IMX7D_WDOG_ROOT_SRC] = imx_clk_hw_mux2("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel)); - hws[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_hw_mux2("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel)); - hws[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_hw_mux2("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel)); - hws[IMX7D_WRCLK_ROOT_SRC] = imx_clk_hw_mux2("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel)); - hws[IMX7D_CLKO1_ROOT_SRC] = imx_clk_hw_mux2("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel)); - hws[IMX7D_CLKO2_ROOT_SRC] = imx_clk_hw_mux2("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel)); + + hws[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_hw_mux2_flags("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_hw_mux2_flags("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_hw_mux2_flags("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_hw_mux2_flags("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_hw_mux2_flags("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_SAI1_ROOT_SRC] = imx_clk_hw_mux2_flags("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_SAI2_ROOT_SRC] = imx_clk_hw_mux2_flags("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_SAI3_ROOT_SRC] = imx_clk_hw_mux2_flags("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_SPDIF_ROOT_SRC] = imx_clk_hw_mux2_flags("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_hw_mux2_flags("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_hw_mux2_flags("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_hw_mux2_flags("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_hw_mux2_flags("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_hw_mux2_flags("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_EIM_ROOT_SRC] = imx_clk_hw_mux2_flags("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_NAND_ROOT_SRC] = imx_clk_hw_mux2_flags("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_QSPI_ROOT_SRC] = imx_clk_hw_mux2_flags("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_USDHC1_ROOT_SRC] = imx_clk_hw_mux2_flags("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_USDHC2_ROOT_SRC] = imx_clk_hw_mux2_flags("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_USDHC3_ROOT_SRC] = imx_clk_hw_mux2_flags("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_CAN1_ROOT_SRC] = imx_clk_hw_mux2_flags("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_CAN2_ROOT_SRC] = imx_clk_hw_mux2_flags("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_I2C1_ROOT_SRC] = imx_clk_hw_mux2_flags("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_I2C2_ROOT_SRC] = imx_clk_hw_mux2_flags("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_I2C3_ROOT_SRC] = imx_clk_hw_mux2_flags("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_I2C4_ROOT_SRC] = imx_clk_hw_mux2_flags("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_UART1_ROOT_SRC] = imx_clk_hw_mux2_flags("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_UART2_ROOT_SRC] = imx_clk_hw_mux2_flags("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_UART3_ROOT_SRC] = imx_clk_hw_mux2_flags("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_UART4_ROOT_SRC] = imx_clk_hw_mux2_flags("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_UART5_ROOT_SRC] = imx_clk_hw_mux2_flags("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_UART6_ROOT_SRC] = imx_clk_hw_mux2_flags("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_UART7_ROOT_SRC] = imx_clk_hw_mux2_flags("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_hw_mux2_flags("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_hw_mux2_flags("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_hw_mux2_flags("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_hw_mux2_flags("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_PWM1_ROOT_SRC] = imx_clk_hw_mux2_flags("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_PWM2_ROOT_SRC] = imx_clk_hw_mux2_flags("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_PWM3_ROOT_SRC] = imx_clk_hw_mux2_flags("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_PWM4_ROOT_SRC] = imx_clk_hw_mux2_flags("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_hw_mux2_flags("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_hw_mux2_flags("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_SIM1_ROOT_SRC] = imx_clk_hw_mux2_flags("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_SIM2_ROOT_SRC] = imx_clk_hw_mux2_flags("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_GPT1_ROOT_SRC] = imx_clk_hw_mux2_flags("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_GPT2_ROOT_SRC] = imx_clk_hw_mux2_flags("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_GPT3_ROOT_SRC] = imx_clk_hw_mux2_flags("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_GPT4_ROOT_SRC] = imx_clk_hw_mux2_flags("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_TRACE_ROOT_SRC] = imx_clk_hw_mux2_flags("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_WDOG_ROOT_SRC] = imx_clk_hw_mux2_flags("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_hw_mux2_flags("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_hw_mux2_flags("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_WRCLK_ROOT_SRC] = imx_clk_hw_mux2_flags("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_CLKO1_ROOT_SRC] = imx_clk_hw_mux2_flags("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel), CLK_SET_PARENT_GATE); + hws[IMX7D_CLKO2_ROOT_SRC] = imx_clk_hw_mux2_flags("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel), CLK_SET_PARENT_GATE); hws[IMX7D_ARM_A7_ROOT_CG] = imx_clk_hw_gate3("arm_a7_cg", "arm_a7_src", base + 0x8000, 28); hws[IMX7D_ARM_M4_ROOT_CG] = imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index b793264c21c6..0de0be0cf548 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -657,3 +657,7 @@ static struct platform_driver imx8mm_clk_driver = { }, }; module_platform_driver(imx8mm_clk_driver); + +MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>"); +MODULE_DESCRIPTION("NXP i.MX8MM clock driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 213cc37b3173..e984de543f0b 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -608,3 +608,7 @@ static struct platform_driver imx8mn_clk_driver = { }, }; module_platform_driver(imx8mn_clk_driver); + +MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>"); +MODULE_DESCRIPTION("NXP i.MX8MN clock driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index ca747712400f..12ce4770f702 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] = {"osc_24m", "sys_pll2_200m", "sys "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; -static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", - "sys_pll3_out", "audio_pll1_out", "video_pll1_out", - "audio_pll2_out", "sys_pll1_133m", }; - static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", "sys_pll1_400m", }; @@ -375,15 +371,14 @@ static const char * const imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_2 "sys_pll3_out", "audio_pll2_out", "video_pll1_out", }; -static const char * const imx8mp_media_mipi_phy2_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", - "sys_pll1_800m", "sys_pll2_1000m", - "clk_ext2", "audio_pll2_out", - "video_pll1_out", }; +static const char * const imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", + "sys_pll1_800m", "sys_pll2_1000m", + "clk_ext2", "audio_pll2_out", + "video_pll1_out", }; -static const char * const imx8mp_media_mipi_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", - "sys_pll1_800m", "sys_pll2_1000m", - "sys_pll3_out", "clk_ext3", - "audio_pll2_out", }; +static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "clk_ext3", "audio_pll2_out", }; static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", @@ -590,7 +585,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180); hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200); hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280); - hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite("memrepair", imx8mp_memrepair_sels, ccm_base + 0xa300); hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", imx8mp_pcie_phy_sels, ccm_base + 0xa380); hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400); hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480); @@ -647,8 +641,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80); hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, ccm_base + 0xbe00); hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80); - hws[IMX8MP_CLK_MEDIA_MIPI_PHY2_REF] = imx8m_clk_hw_composite("media_mipi_phy2_ref", imx8mp_media_mipi_phy2_ref_sels, ccm_base + 0xbf00); - hws[IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC] = imx8m_clk_hw_composite("media_mipi_csi2_esc", imx8mp_media_mipi_csi2_esc_sels, ccm_base + 0xbf80); + hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00); + hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80); hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000); hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", imx8mp_pcie2_phy_sels, ccm_base + 0xc080); hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100); @@ -773,3 +767,7 @@ static struct platform_driver imx8mp_clk_driver = { }, }; module_platform_driver(imx8mp_clk_driver); + +MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>"); +MODULE_DESCRIPTION("NXP i.MX8MP clock driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index a64aace213c2..8265d1d48af4 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -157,10 +157,10 @@ static const char * const imx8mq_qspi_sels[] = {"osc_25m", "sys1_pll_400m", "sys "audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", }; static const char * const imx8mq_usdhc1_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", - "audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", }; + "sys3_pll_out", "sys1_pll_266m", "audio_pll2_out", "sys1_pll_100m", }; static const char * const imx8mq_usdhc2_sels[] = {"osc_25m", "sys1_pll_400m", "sys1_pll_800m", "sys2_pll_500m", - "audio_pll2_out", "sys1_pll_266m", "sys3_pll_out", "sys1_pll_100m", }; + "sys3_pll_out", "sys1_pll_266m", "audio_pll2_out", "sys1_pll_100m", }; static const char * const imx8mq_i2c1_sels[] = {"osc_25m", "sys1_pll_160m", "sys2_pll_50m", "sys3_pll_out", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", "sys1_pll_133m", }; @@ -643,3 +643,7 @@ static struct platform_driver imx8mq_clk_driver = { }, }; module_platform_driver(imx8mq_clk_driver); + +MODULE_AUTHOR("Abel Vesa <abel.vesa@nxp.com>"); +MODULE_DESCRIPTION("NXP i.MX8MQ clock driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index 04c8ee35e14c..e947a70054ac 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -232,3 +232,7 @@ static struct platform_driver imx8qxp_lpcg_clk_driver = { }; builtin_platform_driver(imx8qxp_lpcg_clk_driver); + +MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>"); +MODULE_DESCRIPTION("NXP i.MX8QXP LPCG clock driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 5e2903efc488..d650ca33cdc8 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -152,3 +152,7 @@ static struct platform_driver imx8qxp_clk_driver = { .probe = imx8qxp_clk_probe, }; builtin_platform_driver(imx8qxp_clk_driver); + +MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>"); +MODULE_DESCRIPTION("NXP i.MX8QXP clock driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c index a73a799fb777..1f0e44f921ae 100644 --- a/drivers/clk/imx/clk-lpcg-scu.c +++ b/drivers/clk/imx/clk-lpcg-scu.c @@ -4,6 +4,7 @@ * Dong Aisheng <aisheng.dong@nxp.com> */ +#include <linux/bits.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index 50b7c30296f7..5d2a9a3be95e 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -12,7 +12,7 @@ /** * struct clk_pfd - IMX PFD clock - * @clk_hw: clock source + * @hw: clock source * @reg: PFD register address * @idx: the index of PFD encoded in the register * diff --git a/drivers/clk/imx/clk-pfdv2.c b/drivers/clk/imx/clk-pfdv2.c index 78e1f7641aaa..6b744c84278e 100644 --- a/drivers/clk/imx/clk-pfdv2.c +++ b/drivers/clk/imx/clk-pfdv2.c @@ -17,7 +17,7 @@ /** * struct clk_pfdv2 - IMX PFD clock - * @clk_hw: clock source + * @hw: clock source * @reg: PFD register address * @gate_bit: Gate bit offset * @vld_bit: Valid bit offset diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index f9eb189b93c0..aba36e4217d2 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -3,9 +3,10 @@ * Copyright 2017-2018 NXP. */ -#include <linux/bitops.h> +#include <linux/bits.h> #include <linux/clk-provider.h> #include <linux/err.h> +#include <linux/export.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/slab.h> @@ -68,6 +69,7 @@ struct imx_pll14xx_clk imx_1443x_pll = { .rate_table = imx_pll1443x_tbl, .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), }; +EXPORT_SYMBOL_GPL(imx_1443x_pll); struct imx_pll14xx_clk imx_1443x_dram_pll = { .type = PLL_1443X, @@ -75,12 +77,14 @@ struct imx_pll14xx_clk imx_1443x_dram_pll = { .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), .flags = CLK_GET_RATE_NOCACHE, }; +EXPORT_SYMBOL_GPL(imx_1443x_dram_pll); struct imx_pll14xx_clk imx_1416x_pll = { .type = PLL_1416X, .rate_table = imx_pll1416x_tbl, .rate_count = ARRAY_SIZE(imx_pll1416x_tbl), }; +EXPORT_SYMBOL_GPL(imx_1416x_pll); static const struct imx_pll14xx_rate_table *imx_get_pll_settings( struct clk_pll14xx *pll, unsigned long rate) @@ -436,3 +440,4 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return hw; } +EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); diff --git a/drivers/clk/imx/clk-pllv1.c b/drivers/clk/imx/clk-pllv1.c index de4f8a41a7d0..36ffb0525735 100644 --- a/drivers/clk/imx/clk-pllv1.c +++ b/drivers/clk/imx/clk-pllv1.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include <linux/bits.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/slab.h> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index b20cdea3e9cc..20ee9611ba6e 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -30,12 +30,15 @@ /** * struct clk_pllv3 - IMX PLL clock version 3 - * @clk_hw: clock source + * @hw: clock source * @base: base address of PLL registers * @power_bit: pll power bit mask * @powerup_set: set power_bit to power up the PLL * @div_mask: mask of divider bits * @div_shift: shift of divider bits + * @ref_clock: reference clock rate + * @num_offset: num register offset + * @denom_offset: denom register offset * * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 * is actually a multiplier, and always sits at bit 0. diff --git a/drivers/clk/imx/clk-pllv4.c b/drivers/clk/imx/clk-pllv4.c index a49450431855..8ec703f27417 100644 --- a/drivers/clk/imx/clk-pllv4.c +++ b/drivers/clk/imx/clk-pllv4.c @@ -7,6 +7,7 @@ * */ +#include <linux/bits.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> diff --git a/drivers/clk/imx/clk-sscg-pll.c b/drivers/clk/imx/clk-sscg-pll.c index 773d8a545cdf..9d6cdff0537f 100644 --- a/drivers/clk/imx/clk-sscg-pll.c +++ b/drivers/clk/imx/clk-sscg-pll.c @@ -10,6 +10,7 @@ #include <linux/clk-provider.h> #include <linux/err.h> +#include <linux/export.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/slab.h> @@ -537,3 +538,4 @@ struct clk_hw *imx_clk_hw_sscg_pll(const char *name, return hw; } +EXPORT_SYMBOL_GPL(imx_clk_hw_sscg_pll); diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c index 5129ef8e1d6e..9e11f1c7c397 100644 --- a/drivers/clk/imx/clk-vf610.c +++ b/drivers/clk/imx/clk-vf610.c @@ -4,6 +4,7 @@ */ #include <linux/of_address.h> +#include <linux/bits.h> #include <linux/clk.h> #include <linux/syscore_ops.h> #include <dt-bindings/clock/vf610-clock.h> @@ -328,6 +329,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); + clk[VF610_CLK_CRC] = imx_clk_gate2("crc", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(3)); clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4); diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index 87ab8db3d282..47882c51cb85 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 +#include <linux/bits.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/module.h> #include <linux/of.h> #include <linux/slab.h> #include <linux/spinlock.h> @@ -13,6 +15,7 @@ #define CCDR_MMDC_CH1_MASK BIT(16) DEFINE_SPINLOCK(imx_ccm_lock); +EXPORT_SYMBOL_GPL(imx_ccm_lock); void imx_unregister_clocks(struct clk *clks[], unsigned int count) { @@ -29,8 +32,9 @@ void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count) for (i = 0; i < count; i++) clk_hw_unregister(hws[i]); } +EXPORT_SYMBOL_GPL(imx_unregister_hw_clocks); -void __init imx_mmdc_mask_handshake(void __iomem *ccm_base, +void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn) { unsigned int reg; @@ -59,8 +63,9 @@ void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count) pr_err("i.MX clk %u: register failed with %ld\n", i, PTR_ERR(clks[i])); } +EXPORT_SYMBOL_GPL(imx_check_clk_hws); -static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) +static struct clk *imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; struct clk *clk = ERR_PTR(-ENODEV); @@ -80,7 +85,7 @@ static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) return clk; } -struct clk * __init imx_obtain_fixed_clock( +struct clk *imx_obtain_fixed_clock( const char *name, unsigned long rate) { struct clk *clk; @@ -91,7 +96,7 @@ struct clk * __init imx_obtain_fixed_clock( return clk; } -struct clk_hw * __init imx_obtain_fixed_clock_hw( +struct clk_hw *imx_obtain_fixed_clock_hw( const char *name, unsigned long rate) { struct clk *clk; @@ -113,6 +118,7 @@ struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np, return __clk_get_hw(clk); } +EXPORT_SYMBOL_GPL(imx_obtain_fixed_clk_hw); /* * This fixups the register CCM_CSCMR1 write value. @@ -140,6 +146,7 @@ void imx_cscmr1_fixup(u32 *val) return; } +#ifndef MODULE static int imx_keep_uart_clocks; static struct clk ** const *imx_uart_clocks; @@ -177,3 +184,6 @@ static int __init imx_clk_disable_uart(void) return 0; } late_initcall_sync(imx_clk_disable_uart); +#endif + +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 16adbc34e05f..3b796b3da249 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -2,6 +2,7 @@ #ifndef __MACH_IMX_CLK_H #define __MACH_IMX_CLK_H +#include <linux/bits.h> #include <linux/spinlock.h> #include <linux/clk-provider.h> @@ -11,7 +12,13 @@ extern spinlock_t imx_ccm_lock; void imx_check_clocks(struct clk *clks[], unsigned int count); void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); +#ifndef MODULE void imx_register_uart_clocks(struct clk ** const clks[]); +#else +static inline void imx_register_uart_clocks(struct clk ** const clks[]) +{ +} +#endif void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn); void imx_unregister_clocks(struct clk *clks[], unsigned int count); void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count); |