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path: root/drivers/clk/qcom/dispcc-sc7180.c
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Diffstat (limited to 'drivers/clk/qcom/dispcc-sc7180.c')
-rw-r--r--drivers/clk/qcom/dispcc-sc7180.c45
1 files changed, 15 insertions, 30 deletions
diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c
index 30c1e25d3edb..dd7af41e47eb 100644
--- a/drivers/clk/qcom/dispcc-sc7180.c
+++ b/drivers/clk/qcom/dispcc-sc7180.c
@@ -76,40 +76,32 @@ static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = {
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .fw_name = "bi_tcxo" },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DP_PHY_PLL_LINK_CLK, 1 },
{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .fw_name = "bi_tcxo" },
- { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" },
- { .fw_name = "dp_phy_pll_vco_div_clk",
- .name = "dp_phy_pll_vco_div_clk"},
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+ { .fw_name = "dp_phy_pll_link_clk" },
+ { .fw_name = "dp_phy_pll_vco_div_clk" },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .fw_name = "bi_tcxo" },
- { .fw_name = "dsi0_phy_pll_out_byteclk",
- .name = "dsi0_phy_pll_out_byteclk" },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+ { .fw_name = "dsi0_phy_pll_out_byteclk" },
};
static const struct parent_map disp_cc_parent_map_3[] = {
@@ -117,7 +109,6 @@ static const struct parent_map disp_cc_parent_map_3[] = {
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_MAIN, 4 },
{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
@@ -125,32 +116,26 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .hw = &disp_cc_pll0.clkr.hw },
{ .fw_name = "gcc_disp_gpll0_clk_src" },
{ .hw = &disp_cc_pll0_out_even.clkr.hw },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 4 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "gcc_disp_gpll0_clk_src" },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data disp_cc_parent_data_5[] = {
{ .fw_name = "bi_tcxo" },
- { .fw_name = "dsi0_phy_pll_out_dsiclk",
- .name = "dsi0_phy_pll_out_dsiclk" },
- { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
+ { .fw_name = "dsi0_phy_pll_out_dsiclk" },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
@@ -169,7 +154,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_4,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
@@ -183,7 +168,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_2,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -203,7 +188,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk_src",
.parent_data = disp_cc_parent_data_0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -216,7 +201,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_data = disp_cc_parent_data_1,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -230,7 +215,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src",
.parent_data = disp_cc_parent_data_1,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -244,7 +229,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_data = disp_cc_parent_data_1,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops,
},
@@ -259,7 +244,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_2,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
@@ -282,7 +267,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_3,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -295,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_5,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
@@ -310,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_3,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops,
},
};
@@ -324,7 +309,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_0,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
generated by cgit (git 2.34.1) at 2024-05-22 06:14:00 +0000