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path: root/drivers/clk/qcom/mmcc-msm8960.c
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Diffstat (limited to 'drivers/clk/qcom/mmcc-msm8960.c')
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c93
1 files changed, 73 insertions, 20 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 50638ab341ec..20d1c43f35d9 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -37,6 +37,7 @@ enum {
P_DSI2_PLL_DSICLK,
P_DSI1_PLL_BYTECLK,
P_DSI2_PLL_BYTECLK,
+ P_LVDS_PLL,
};
#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
@@ -143,6 +144,20 @@ static const struct clk_parent_data mmcc_pxo_dsi2_dsi1[] = {
{ .fw_name = "dsi1pll", .name = "dsi1pll" },
};
+static const struct parent_map mmcc_pxo_dsi2_dsi1_lvds_map[] = {
+ { P_PXO, 0 },
+ { P_DSI2_PLL_DSICLK, 1 },
+ { P_LVDS_PLL, 2 },
+ { P_DSI1_PLL_DSICLK, 3 },
+};
+
+static const struct clk_parent_data mmcc_pxo_dsi2_dsi1_lvds[] = {
+ { .fw_name = "pxo", .name = "pxo_board" },
+ { .fw_name = "dsi2pll", .name = "dsi2pll" },
+ { .fw_name = "lvdspll", .name = "mpd4_lvds_pll" },
+ { .fw_name = "dsi1pll", .name = "dsi1pll" },
+};
+
static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
{ P_PXO, 0 },
{ P_DSI1_PLL_BYTECLK, 1 },
@@ -155,7 +170,7 @@ static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = {
{ .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" },
};
-static struct freq_tbl clk_tbl_cam[] = {
+static const struct freq_tbl clk_tbl_cam[] = {
{ 6000000, P_PLL8, 4, 1, 16 },
{ 8000000, P_PLL8, 4, 1, 12 },
{ 12000000, P_PLL8, 4, 1, 8 },
@@ -323,7 +338,7 @@ static struct clk_branch camclk2_clk = {
};
-static struct freq_tbl clk_tbl_csi[] = {
+static const struct freq_tbl clk_tbl_csi[] = {
{ 27000000, P_PXO, 1, 0, 0 },
{ 85330000, P_PLL8, 1, 2, 9 },
{ 177780000, P_PLL2, 1, 2, 9 },
@@ -715,7 +730,7 @@ static struct clk_pix_rdi csi_rdi2_clk = {
},
};
-static struct freq_tbl clk_tbl_csiphytimer[] = {
+static const struct freq_tbl clk_tbl_csiphytimer[] = {
{ 85330000, P_PLL8, 1, 2, 9 },
{ 177780000, P_PLL2, 1, 2, 9 },
{ }
@@ -808,7 +823,7 @@ static struct clk_branch csiphy2_timer_clk = {
},
};
-static struct freq_tbl clk_tbl_gfx2d[] = {
+static const struct freq_tbl clk_tbl_gfx2d[] = {
F_MN( 27000000, P_PXO, 1, 0),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54857000, P_PLL8, 1, 7),
@@ -948,7 +963,7 @@ static struct clk_branch gfx2d1_clk = {
},
};
-static struct freq_tbl clk_tbl_gfx3d[] = {
+static const struct freq_tbl clk_tbl_gfx3d[] = {
F_MN( 27000000, P_PXO, 1, 0),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54857000, P_PLL8, 1, 7),
@@ -968,7 +983,7 @@ static struct freq_tbl clk_tbl_gfx3d[] = {
{ }
};
-static struct freq_tbl clk_tbl_gfx3d_8064[] = {
+static const struct freq_tbl clk_tbl_gfx3d_8064[] = {
F_MN( 27000000, P_PXO, 0, 0),
F_MN( 48000000, P_PLL8, 1, 8),
F_MN( 54857000, P_PLL8, 1, 7),
@@ -1058,7 +1073,7 @@ static struct clk_branch gfx3d_clk = {
},
};
-static struct freq_tbl clk_tbl_vcap[] = {
+static const struct freq_tbl clk_tbl_vcap[] = {
F_MN( 27000000, P_PXO, 0, 0),
F_MN( 54860000, P_PLL8, 1, 7),
F_MN( 64000000, P_PLL8, 1, 6),
@@ -1149,7 +1164,7 @@ static struct clk_branch vcap_npl_clk = {
},
};
-static struct freq_tbl clk_tbl_ijpeg[] = {
+static const struct freq_tbl clk_tbl_ijpeg[] = {
{ 27000000, P_PXO, 1, 0, 0 },
{ 36570000, P_PLL8, 1, 2, 21 },
{ 54860000, P_PLL8, 7, 0, 0 },
@@ -1214,7 +1229,7 @@ static struct clk_branch ijpeg_clk = {
},
};
-static struct freq_tbl clk_tbl_jpegd[] = {
+static const struct freq_tbl clk_tbl_jpegd[] = {
{ 64000000, P_PLL8, 6 },
{ 76800000, P_PLL8, 5 },
{ 96000000, P_PLL8, 4 },
@@ -1264,7 +1279,7 @@ static struct clk_branch jpegd_clk = {
},
};
-static struct freq_tbl clk_tbl_mdp[] = {
+static const struct freq_tbl clk_tbl_mdp[] = {
{ 9600000, P_PLL8, 1, 1, 40 },
{ 13710000, P_PLL8, 1, 1, 28 },
{ 27000000, P_PXO, 1, 0, 0 },
@@ -1381,7 +1396,7 @@ static struct clk_branch mdp_vsync_clk = {
},
};
-static struct freq_tbl clk_tbl_rot[] = {
+static const struct freq_tbl clk_tbl_rot[] = {
{ 27000000, P_PXO, 1 },
{ 29540000, P_PLL8, 13 },
{ 32000000, P_PLL8, 12 },
@@ -1461,7 +1476,7 @@ static const struct clk_parent_data mmcc_pxo_hdmi[] = {
{ .fw_name = "hdmipll", .name = "hdmi_pll" },
};
-static struct freq_tbl clk_tbl_tv[] = {
+static const struct freq_tbl clk_tbl_tv[] = {
{ .src = P_HDMI_PLL, .pre_div = 1 },
{ }
};
@@ -1624,7 +1639,7 @@ static struct clk_branch hdmi_app_clk = {
},
};
-static struct freq_tbl clk_tbl_vcodec[] = {
+static const struct freq_tbl clk_tbl_vcodec[] = {
F_MN( 27000000, P_PXO, 1, 0),
F_MN( 32000000, P_PLL8, 1, 12),
F_MN( 48000000, P_PLL8, 1, 8),
@@ -1699,7 +1714,7 @@ static struct clk_branch vcodec_clk = {
},
};
-static struct freq_tbl clk_tbl_vpe[] = {
+static const struct freq_tbl clk_tbl_vpe[] = {
{ 27000000, P_PXO, 1 },
{ 34909000, P_PLL8, 11 },
{ 38400000, P_PLL8, 10 },
@@ -1752,7 +1767,7 @@ static struct clk_branch vpe_clk = {
},
};
-static struct freq_tbl clk_tbl_vfe[] = {
+static const struct freq_tbl clk_tbl_vfe[] = {
{ 13960000, P_PLL8, 1, 2, 55 },
{ 27000000, P_PXO, 1, 0, 0 },
{ 36570000, P_PLL8, 1, 2, 21 },
@@ -2439,26 +2454,42 @@ static struct clk_rcg dsi2_pixel_src = {
},
.s = {
.src_sel_shift = 0,
- .parent_map = mmcc_pxo_dsi2_dsi1_map,
+ .parent_map = mmcc_pxo_dsi2_dsi1_lvds_map,
},
.clkr = {
.enable_reg = 0x0094,
.enable_mask = BIT(2),
.hw.init = &(struct clk_init_data){
.name = "dsi2_pixel_src",
- .parent_data = mmcc_pxo_dsi2_dsi1,
- .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
+ .parent_data = mmcc_pxo_dsi2_dsi1_lvds,
+ .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1_lvds),
.ops = &clk_rcg_pixel_ops,
},
},
};
+static struct clk_branch dsi2_pixel_lvds_src = {
+ .clkr = {
+ .enable_reg = 0x0094,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "dsi2_pixel_lvds_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &dsi2_pixel_src.clkr.hw
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_simple_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
static struct clk_branch dsi2_pixel_clk = {
.halt_reg = 0x01d0,
.halt_bit = 19,
.clkr = {
.enable_reg = 0x0094,
- .enable_mask = BIT(0),
+ .enable_mask = 0,
.hw.init = &(struct clk_init_data){
.name = "mdp_pclk2_clk",
.parent_hws = (const struct clk_hw*[]){
@@ -2471,6 +2502,24 @@ static struct clk_branch dsi2_pixel_clk = {
},
};
+static struct clk_branch lvds_clk = {
+ .halt_reg = 0x024c,
+ .halt_bit = 6,
+ .clkr = {
+ .enable_reg = 0x0264,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "mdp_lvds_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &dsi2_pixel_lvds_src.clkr.hw
+ },
+ .num_parents = 1,
+ .ops = &clk_branch_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
static struct clk_branch gfx2d0_ahb_clk = {
.hwcg_reg = 0x0038,
.hwcg_bit = 28,
@@ -2799,6 +2848,8 @@ static struct clk_regmap *mmcc_msm8960_clks[] = {
[CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
[CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
[PLL2] = &pll2.clkr,
+ [DSI2_PIXEL_LVDS_SRC] = &dsi2_pixel_lvds_src.clkr,
+ [LVDS_CLK] = &lvds_clk.clkr,
};
static const struct qcom_reset_map mmcc_msm8960_resets[] = {
@@ -2983,6 +3034,8 @@ static struct clk_regmap *mmcc_apq8064_clks[] = {
[VCAP_CLK] = &vcap_clk.clkr,
[VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
[PLL15] = &pll15.clkr,
+ [DSI2_PIXEL_LVDS_SRC] = &dsi2_pixel_lvds_src.clkr,
+ [LVDS_CLK] = &lvds_clk.clkr,
};
static const struct qcom_reset_map mmcc_apq8064_resets[] = {
@@ -3122,7 +3175,7 @@ static int mmcc_msm8960_probe(struct platform_device *pdev)
clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
- return qcom_cc_really_probe(pdev, desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, desc, regmap);
}
static struct platform_driver mmcc_msm8960_driver = {
generated by cgit (git 2.34.1) at 2025-07-31 01:49:08 +0000