diff options
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_common.c')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu_common.c | 34 |
1 files changed, 30 insertions, 4 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c index 8babce55302f..88ed89658d45 100644 --- a/drivers/clk/sunxi-ng/ccu_common.c +++ b/drivers/clk/sunxi-ng/ccu_common.c @@ -37,19 +37,29 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock) WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000)); } -EXPORT_SYMBOL_NS_GPL(ccu_helper_wait_for_lock, SUNXI_CCU); +EXPORT_SYMBOL_NS_GPL(ccu_helper_wait_for_lock, "SUNXI_CCU"); bool ccu_is_better_rate(struct ccu_common *common, unsigned long target_rate, unsigned long current_rate, unsigned long best_rate) { + unsigned long min_rate, max_rate; + + clk_hw_get_rate_range(&common->hw, &min_rate, &max_rate); + + if (current_rate > max_rate) + return false; + + if (current_rate < min_rate) + return false; + if (common->features & CCU_FEATURE_CLOSEST_RATE) return abs(current_rate - target_rate) < abs(best_rate - target_rate); return current_rate <= target_rate && current_rate > best_rate; } -EXPORT_SYMBOL_NS_GPL(ccu_is_better_rate, SUNXI_CCU); +EXPORT_SYMBOL_NS_GPL(ccu_is_better_rate, "SUNXI_CCU"); /* * This clock notifier is called when the frequency of a PLL clock is @@ -97,7 +107,7 @@ int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb) return clk_notifier_register(pll_nb->common->hw.clk, &pll_nb->clk_nb); } -EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, SUNXI_CCU); +EXPORT_SYMBOL_NS_GPL(ccu_pll_notifier_register, "SUNXI_CCU"); static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev, struct device_node *node, void __iomem *reg, @@ -138,6 +148,21 @@ static int sunxi_ccu_probe(struct sunxi_ccu *ccu, struct device *dev, } } + for (i = 0; i < desc->num_ccu_clks; i++) { + struct ccu_common *cclk = desc->ccu_clks[i]; + + if (!cclk) + continue; + + if (cclk->max_rate) + clk_hw_set_rate_range(&cclk->hw, cclk->min_rate, + cclk->max_rate); + else + WARN(cclk->min_rate, + "No max_rate, ignoring min_rate of clock %d - %s\n", + i, clk_hw_get_name(&cclk->hw)); + } + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, desc->hw_clks); if (ret) @@ -209,7 +234,7 @@ int devm_sunxi_ccu_probe(struct device *dev, void __iomem *reg, return 0; } -EXPORT_SYMBOL_NS_GPL(devm_sunxi_ccu_probe, SUNXI_CCU); +EXPORT_SYMBOL_NS_GPL(devm_sunxi_ccu_probe, "SUNXI_CCU"); void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg, const struct sunxi_ccu_desc *desc) @@ -228,4 +253,5 @@ void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg, } } +MODULE_DESCRIPTION("Common clock support for Allwinner SoCs"); MODULE_LICENSE("GPL"); |