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Diffstat (limited to 'drivers/clk/tegra/clk-dfll.c')
-rw-r--r--drivers/clk/tegra/clk-dfll.c11
1 files changed, 1 insertions, 10 deletions
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 1fc71baae13b..f8688c2ddf1a 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* clk-dfll.c - Tegra DFLL clock source common code
*
@@ -6,15 +7,6 @@
* Aleksandr Frid <afrid@nvidia.com>
* Paul Walmsley <pwalmsley@nvidia.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
* This library is for the DVCO and DFLL IP blocks on the Tegra124
* SoC. These IP blocks together are also known at NVIDIA as
* "CL-DVFS". To try to avoid confusion, this code refers to them
@@ -34,7 +26,6 @@
* CPU cycle time will vary. This has implications for
* performance-measurement code and any code that relies on the CPU
* cycle time to delay for a certain length of time.
- *
*/
#include <linux/clk.h>