diff options
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos850.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index 568ac97c8120..4799771d09bc 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -426,11 +426,14 @@ CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top", #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014 +#define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc +#define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0 static const unsigned long apm_clk_regs[] __initconst = { PLL_CON0_MUX_CLKCMU_APM_BUS_USER, @@ -445,11 +448,14 @@ static const unsigned long apm_clk_regs[] __initconst = { CLK_CON_DIV_DIV_CLK_APM_I3C, CLK_CON_GAT_CLKCMU_CMGP_BUS, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, + CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, + CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, + CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, }; /* List of parent clocks for Muxes in CMU_APM */ @@ -512,6 +518,14 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = { CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0), GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus", CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0), + /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ + GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus", + CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, + 0), + GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", + CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), + GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", + CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), }; static const struct samsung_cmu_info apm_cmu_info __initconst = { @@ -541,6 +555,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = { #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c @@ -556,6 +571,7 @@ static const unsigned long cmgp_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, @@ -610,6 +626,9 @@ static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = { GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", "gout_clkcmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), + GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk", + "gout_clkcmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0), }; static const struct samsung_cmu_info cmgp_cmu_info __initconst = { @@ -910,10 +929,12 @@ CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri", #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040 +#define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c +#define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 static const unsigned long core_clk_regs[] __initconst = { PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, @@ -924,10 +945,12 @@ static const unsigned long core_clk_regs[] __initconst = { CLK_CON_DIV_DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, CLK_CON_GAT_GOUT_CORE_GIC_CLK, + CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, + CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, }; /* List of parent clocks for Muxes in CMU_CORE */ @@ -972,6 +995,12 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = { CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0), + /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ + GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk", + "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0), }; static const struct samsung_cmu_info core_cmu_info __initconst = { |