diff options
Diffstat (limited to 'drivers/clk')
251 files changed, 9791 insertions, 5283 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b6c5bf69a2b2..8f0fa6fdaa44 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -325,6 +325,15 @@ config COMMON_CLK_LOCHNAGAR This driver supports the clocking features of the Cirrus Logic Lochnagar audio development board. +config COMMON_CLK_LOONGSON2 + bool "Clock driver for Loongson-2 SoC" + depends on LOONGARCH || COMPILE_TEST + help + This driver provides support for clock controller on Loongson-2 SoC. + The clock controller can generates and supplies clock to various + peripherals within the SoC. + Say Y here to support Loongson-2 SoC clock driver. + config COMMON_CLK_NXP def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX) select REGMAP_MMIO if ARCH_LPC32XX @@ -367,6 +376,15 @@ config COMMON_CLK_RS9_PCIE This driver supports the Renesas 9-series PCIe clock generator models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ. +config COMMON_CLK_SI521XX + tristate "Clock driver for SkyWorks Si521xx PCIe clock generators" + depends on I2C + depends on OF + select REGMAP_I2C + help + This driver supports the SkyWorks Si521xx PCIe clock generator + models Si52144/Si52146/Si52147. + config COMMON_CLK_VC5 tristate "Clock driver for IDT VersaClock 5,6 devices" depends on I2C @@ -436,6 +454,16 @@ config COMMON_CLK_K210 help Support for the Canaan Kendryte K210 RISC-V SoC clocks. +config COMMON_CLK_SP7021 + tristate "Clock driver for Sunplus SP7021 SoC" + depends on SOC_SP7021 || COMPILE_TEST + default SOC_SP7021 + help + This driver supports the Sunplus SP7021 SoC clocks. + It implements SP7021 PLLs/gate. + Not all features of the PLL are currently supported + by the driver. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..9b7a414b5614 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -43,6 +43,8 @@ obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o obj-$(CONFIG_LMK04832) += clk-lmk04832.o obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o +obj-$(CONFIG_MACH_LOONGSON32) += clk-loongson1.o +obj-$(CONFIG_COMMON_CLK_LOONGSON2) += clk-loongson2.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o @@ -65,6 +67,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o +obj-$(CONFIG_COMMON_CLK_SP7021) += clk-sp7021.o obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o @@ -72,6 +75,7 @@ obj-$(CONFIG_COMMON_CLK_TPS68470) += clk-tps68470.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o +obj-$(CONFIG_COMMON_CLK_SI521XX) += clk-si521xx.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o @@ -93,7 +97,6 @@ obj-y += imx/ obj-y += ingenic/ obj-$(CONFIG_ARCH_K3) += keystone/ obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ -obj-$(CONFIG_MACH_LOONGSON32) += loongson1/ obj-y += mediatek/ obj-$(CONFIG_ARCH_MESON) += meson/ obj-y += microchip/ diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index d757003004cb..0882ed01d5c2 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -668,7 +668,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN, parent_rate, true); - if (ret <= 0) { + if (ret < 0) { hw = ERR_PTR(ret); goto free; } diff --git a/drivers/clk/axs10x/i2s_pll_clock.c b/drivers/clk/axs10x/i2s_pll_clock.c index e1fda6ad5cd5..2334e6c334cf 100644 --- a/drivers/clk/axs10x/i2s_pll_clock.c +++ b/drivers/clk/axs10x/i2s_pll_clock.c @@ -198,10 +198,9 @@ static int i2s_pll_clk_probe(struct platform_device *pdev) return of_clk_add_provider(node, of_clk_src_simple_get, clk); } -static int i2s_pll_clk_remove(struct platform_device *pdev) +static void i2s_pll_clk_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - return 0; } static const struct of_device_id i2s_pll_clk_id[] = { @@ -216,7 +215,7 @@ static struct platform_driver i2s_pll_clk_driver = { .of_match_table = i2s_pll_clk_id, }, .probe = i2s_pll_clk_probe, - .remove = i2s_pll_clk_remove, + .remove_new = i2s_pll_clk_remove, }; module_platform_driver(i2s_pll_clk_driver); diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c index 90fb0e6ff573..dbbfa12e530d 100644 --- a/drivers/clk/axs10x/pll_clock.c +++ b/drivers/clk/axs10x/pll_clock.c @@ -257,10 +257,9 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev) &pll_clk->hw); } -static int axs10x_pll_clk_remove(struct platform_device *pdev) +static void axs10x_pll_clk_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - return 0; } static void __init of_axs10x_pll_clk_setup(struct device_node *node) @@ -332,7 +331,7 @@ static struct platform_driver axs10x_pll_clk_driver = { .of_match_table = axs10x_pll_clk_id, }, .probe = axs10x_pll_clk_probe, - .remove = axs10x_pll_clk_remove, + .remove_new = axs10x_pll_clk_remove, }; builtin_platform_driver(axs10x_pll_clk_driver); diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig index 77266afb1c79..a972d763eb77 100644 --- a/drivers/clk/bcm/Kconfig +++ b/drivers/clk/bcm/Kconfig @@ -37,6 +37,15 @@ config CLK_BCM_63XX_GATE Enable common clock framework support for Broadcom BCM63xx DSL SoCs based on the MIPS architecture +config CLK_BCM63268_TIMER + bool "Broadcom BCM63268 timer clock and reset support" + depends on BMIPS_GENERIC || COMPILE_TEST + default BMIPS_GENERIC + select RESET_CONTROLLER + help + Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs + based on the MIPS architecture. + config CLK_BCM_KONA bool "Broadcom Kona CCU clock support" depends on ARCH_BCM_MOBILE || COMPILE_TEST diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile index edb66b44cb27..d0b6f4b1fb08 100644 --- a/drivers/clk/bcm/Makefile +++ b/drivers/clk/bcm/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o obj-$(CONFIG_CLK_BCM_63XX_GATE) += clk-bcm63xx-gate.o +obj-$(CONFIG_CLK_BCM63268_TIMER) += clk-bcm63268-timer.o obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o diff --git a/drivers/clk/bcm/clk-bcm2711-dvp.c b/drivers/clk/bcm/clk-bcm2711-dvp.c index e63a42618ac2..e4fbbf3c40fe 100644 --- a/drivers/clk/bcm/clk-bcm2711-dvp.c +++ b/drivers/clk/bcm/clk-bcm2711-dvp.c @@ -92,15 +92,13 @@ unregister_clk0: return ret; }; -static int clk_dvp_remove(struct platform_device *pdev) +static void clk_dvp_remove(struct platform_device *pdev) { struct clk_dvp *dvp = platform_get_drvdata(pdev); struct clk_hw_onecell_data *data = dvp->data; clk_hw_unregister_gate(data->hws[1]); clk_hw_unregister_gate(data->hws[0]); - - return 0; } static const struct of_device_id clk_dvp_dt_ids[] = { @@ -111,7 +109,7 @@ MODULE_DEVICE_TABLE(of, clk_dvp_dt_ids); static struct platform_driver clk_dvp_driver = { .probe = clk_dvp_probe, - .remove = clk_dvp_remove, + .remove_new = clk_dvp_remove, .driver = { .name = "brcm2711-dvp", .of_match_table = clk_dvp_dt_ids, diff --git a/drivers/clk/bcm/clk-bcm63268-timer.c b/drivers/clk/bcm/clk-bcm63268-timer.c new file mode 100644 index 000000000000..463710d272a1 --- /dev/null +++ b/drivers/clk/bcm/clk-bcm63268-timer.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * BCM63268 Timer Clock and Reset Controller Driver + * + * Copyright (C) 2023 Álvaro Fernández Rojas <noltari@gmail.com> + */ + +#include <linux/clk-provider.h> +#include <linux/container_of.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/spinlock.h> + +#include <dt-bindings/clock/bcm63268-clock.h> + +#define BCM63268_TIMER_RESET_SLEEP_MIN_US 10000 +#define BCM63268_TIMER_RESET_SLEEP_MAX_US 20000 + +struct bcm63268_tclkrst_hw { + void __iomem *regs; + spinlock_t lock; + + struct reset_controller_dev rcdev; + struct clk_hw_onecell_data data; +}; + +struct bcm63268_tclk_table_entry { + const char * const name; + u8 bit; +}; + +static const struct bcm63268_tclk_table_entry bcm63268_timer_clocks[] = { + { + .name = "ephy1", + .bit = BCM63268_TCLK_EPHY1, + }, { + .name = "ephy2", + .bit = BCM63268_TCLK_EPHY2, + }, { + .name = "ephy3", + .bit = BCM63268_TCLK_EPHY3, + }, { + .name = "gphy1", + .bit = BCM63268_TCLK_GPHY1, + }, { + .name = "dsl", + .bit = BCM63268_TCLK_DSL, + }, { + .name = "wakeon_ephy", + .bit = BCM63268_TCLK_WAKEON_EPHY, + }, { + .name = "wakeon_dsl", + .bit = BCM63268_TCLK_WAKEON_DSL, + }, { + .name = "fap1_pll", + .bit = BCM63268_TCLK_FAP1, + }, { + .name = "fap2_pll", + .bit = BCM63268_TCLK_FAP2, + }, { + .name = "uto_50", + .bit = BCM63268_TCLK_UTO_50, + }, { + .name = "uto_extin", + .bit = BCM63268_TCLK_UTO_EXTIN, + }, { + .name = "usb_ref", + .bit = BCM63268_TCLK_USB_REF, + }, { + /* sentinel */ + } +}; + +static inline struct bcm63268_tclkrst_hw * +to_bcm63268_timer_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev); +} + +static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev); + unsigned long flags; + uint32_t val; + + spin_lock_irqsave(&reset->lock, flags); + val = __raw_readl(reset->regs); + if (assert) + val &= ~BIT(id); + else + val |= BIT(id); + __raw_writel(val, reset->regs); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static int bcm63268_timer_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return bcm63268_timer_reset_update(rcdev, id, true); +} + +static int bcm63268_timer_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return bcm63268_timer_reset_update(rcdev, id, false); +} + +static int bcm63268_timer_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + bcm63268_timer_reset_update(rcdev, id, true); + usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US, + BCM63268_TIMER_RESET_SLEEP_MAX_US); + + bcm63268_timer_reset_update(rcdev, id, false); + /* + * Ensure component is taken out reset state by sleeping also after + * deasserting the reset. Otherwise, the component may not be ready + * for operation. + */ + usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US, + BCM63268_TIMER_RESET_SLEEP_MAX_US); + + return 0; +} + +static int bcm63268_timer_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev); + + return !(__raw_readl(reset->regs) & BIT(id)); +} + +static const struct reset_control_ops bcm63268_timer_reset_ops = { + .assert = bcm63268_timer_reset_assert, + .deassert = bcm63268_timer_reset_deassert, + .reset = bcm63268_timer_reset_reset, + .status = bcm63268_timer_reset_status, +}; + +static int bcm63268_tclk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct bcm63268_tclk_table_entry *entry; + struct bcm63268_tclkrst_hw *hw; + struct clk_hw *clk; + u8 maxbit = 0; + int i, ret; + + for (entry = bcm63268_timer_clocks; entry->name; entry++) + maxbit = max(maxbit, entry->bit); + maxbit++; + + hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit), + GFP_KERNEL); + if (!hw) + return -ENOMEM; + + platform_set_drvdata(pdev, hw); + + spin_lock_init(&hw->lock); + + hw->data.num = maxbit; + for (i = 0; i < maxbit; i++) + hw->data.hws[i] = ERR_PTR(-ENODEV); + + hw->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hw->regs)) + return PTR_ERR(hw->regs); + + for (entry = bcm63268_timer_clocks; entry->name; entry++) { + clk = devm_clk_hw_register_gate(dev, entry->name, NULL, 0, + hw->regs, entry->bit, + CLK_GATE_BIG_ENDIAN, + &hw->lock); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + hw->data.hws[entry->bit] = clk; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &hw->data); + if (ret) + return ret; + + hw->rcdev.of_node = dev->of_node; + hw->rcdev.ops = &bcm63268_timer_reset_ops; + + ret = devm_reset_controller_register(dev, &hw->rcdev); + if (ret) + dev_err(dev, "Failed to register reset controller\n"); + + return 0; +} + +static const struct of_device_id bcm63268_tclk_dt_ids[] = { + { .compatible = "brcm,bcm63268-timer-clocks" }, + { /* sentinel */ } +}; + +static struct platform_driver bcm63268_tclk = { + .probe = bcm63268_tclk_probe, + .driver = { + .name = "bcm63268-timer-clock", + .of_match_table = bcm63268_tclk_dt_ids, + }, +}; +builtin_platform_driver(bcm63268_tclk); diff --git a/drivers/clk/bcm/clk-bcm63xx-gate.c b/drivers/clk/bcm/clk-bcm63xx-gate.c index 89297c57881e..0769f98767da 100644 --- a/drivers/clk/bcm/clk-bcm63xx-gate.c +++ b/drivers/clk/bcm/clk-bcm63xx-gate.c @@ -541,7 +541,7 @@ out_err: return ret; } -static int clk_bcm63xx_remove(struct platform_device *pdev) +static void clk_bcm63xx_remove(struct platform_device *pdev) { struct clk_bcm63xx_hw *hw = platform_get_drvdata(pdev); int i; @@ -552,8 +552,6 @@ static int clk_bcm63xx_remove(struct platform_device *pdev) if (!IS_ERR(hw->data.hws[i])) clk_hw_unregister_gate(hw->data.hws[i]); } - - return 0; } static const struct of_device_id clk_bcm63xx_dt_ids[] = { @@ -570,7 +568,7 @@ static const struct of_device_id clk_bcm63xx_dt_ids[] = { static struct platform_driver clk_bcm63xx = { .probe = clk_bcm63xx_probe, - .remove = clk_bcm63xx_remove, + .remove_new = clk_bcm63xx_remove, .driver = { .name = "bcm63xx-clock", .of_match_table = clk_bcm63xx_dt_ids, diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c index ce2f93479736..eb399a4d141b 100644 --- a/drivers/clk/bcm/clk-raspberrypi.c +++ b/drivers/clk/bcm/clk-raspberrypi.c @@ -439,13 +439,11 @@ static int raspberrypi_clk_probe(struct platform_device *pdev) return 0; } -static int raspberrypi_clk_remove(struct platform_device *pdev) +static void raspberrypi_clk_remove(struct platform_device *pdev) { struct raspberrypi_clk *rpi = platform_get_drvdata(pdev); platform_device_unregister(rpi->cpufreq); - - return 0; } static const struct of_device_id raspberrypi_clk_match[] = { @@ -460,7 +458,7 @@ static struct platform_driver raspberrypi_clk_driver = { .of_match_table = raspberrypi_clk_match, }, .probe = raspberrypi_clk_probe, - .remove = raspberrypi_clk_remove, + .remove_new = raspberrypi_clk_remove, }; module_platform_driver(raspberrypi_clk_driver); diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index 9c3305bcb27a..a094a2601a37 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -15,7 +15,11 @@ #include "clk-aspeed.h" -#define ASPEED_G6_NUM_CLKS 71 +/* + * This includes the gates (configured from aspeed_g6_gates), plus the + * explicitly-configured clocks (ASPEED_CLK_HPLL and up). + */ +#define ASPEED_G6_NUM_CLKS 72 #define ASPEED_G6_SILICON_REV 0x014 #define CHIP_REVISION_ID GENMASK(23, 16) @@ -32,6 +36,20 @@ #define ASPEED_G6_CLK_SELECTION1 0x300 #define ASPEED_G6_CLK_SELECTION2 0x304 #define ASPEED_G6_CLK_SELECTION4 0x310 +#define ASPEED_G6_CLK_SELECTION5 0x314 +#define I3C_CLK_SELECTION_SHIFT 31 +#define I3C_CLK_SELECTION BIT(31) +#define I3C_CLK_SELECT_HCLK (0 << I3C_CLK_SELECTION_SHIFT) +#define I3C_CLK_SELECT_APLL_DIV (1 << I3C_CLK_SELECTION_SHIFT) +#define APLL_DIV_SELECTION_SHIFT 28 +#define APLL_DIV_SELECTION GENMASK(30, 28) +#define APLL_DIV_2 (0b001 << APLL_DIV_SELECTION_SHIFT) +#define APLL_DIV_3 (0b010 << APLL_DIV_SELECTION_SHIFT) +#define APLL_DIV_4 (0b011 << APLL_DIV_SELECTION_SHIFT) +#define APLL_DIV_5 (0b100 << APLL_DIV_SELECTION_SHIFT) +#define APLL_DIV_6 (0b101 << APLL_DIV_SELECTION_SHIFT) +#define APLL_DIV_7 (0b110 << APLL_DIV_SELECTION_SHIFT) +#define APLL_DIV_8 (0b111 << APLL_DIV_SELECTION_SHIFT) #define ASPEED_HPLL_PARAM 0x200 #define ASPEED_APLL_PARAM 0x210 @@ -55,6 +73,27 @@ static void __iomem *scu_g6_base; static u8 soc_rev; /* + * The majority of the clocks in the system are gates paired with a reset + * controller that holds the IP in reset; this is represented by the @reset_idx + * member of entries here. + * + * This borrows from clk_hw_register_gate, but registers two 'gates', one + * to control the clock enable register and the other to control the reset + * IP. This allows us to enforce the ordering: + * + * 1. Place IP in reset + * 2. Enable clock + * 3. Delay + * 4. Release reset + * + * Consequently, if reset_idx is set, reset control is implicit: the clock + * consumer does not need its own reset handling, as enabling the clock will + * also deassert reset. + * + * There are some gates that do not have an associated reset; these are + * handled by using -1 as the index for the reset, and the consumer must + * explictly assert/deassert reset lines as required. + * * Clocks marked with CLK_IS_CRITICAL: * * ref0 and ref1 are essential for the SoC to operate @@ -97,14 +136,13 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = { [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ /* Reserved 38 RSA: no longer used */ /* Reserved 39 */ - [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */ - [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */ - [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */ - [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */ - [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */ - [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */ - [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */ - [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */ + [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", "i3cclk", 0 }, /* I3C0 */ + [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", "i3cclk", 0 }, /* I3C1 */ + [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", "i3cclk", 0 }, /* I3C2 */ + [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", "i3cclk", 0 }, /* I3C3 */ + [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", "i3cclk", 0 }, /* I3C4 */ + [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", "i3cclk", 0 }, /* I3C5 */ + /* Reserved: 46 & 47 */ [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ @@ -652,6 +690,9 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) const struct aspeed_gate_data *gd = &aspeed_g6_gates[i]; u32 gate_flags; + if (!gd->name) + continue; + /* * Special case: the USB port 1 clock (bit 14) is always * working the opposite way from the other ones. @@ -772,6 +813,14 @@ static void __init aspeed_g6_cc(struct regmap *map) /* USB 2.0 port1 phy 40MHz clock */ hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000); aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw; + + /* i3c clock: source from apll, divide by 8 */ + regmap_update_bits(map, ASPEED_G6_CLK_SELECTION5, + I3C_CLK_SELECTION | APLL_DIV_SELECTION, + I3C_CLK_SELECT_APLL_DIV | APLL_DIV_8); + + hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "apll", 0, 1, 8); + aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw; }; static void __init aspeed_g6_cc_init(struct device_node *np) diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c index ac6ff736ac8f..671bee55ceb3 100644 --- a/drivers/clk/clk-axi-clkgen.c +++ b/drivers/clk/clk-axi-clkgen.c @@ -557,11 +557,9 @@ static int axi_clkgen_probe(struct platform_device *pdev) &axi_clkgen->clk_hw); } -static int axi_clkgen_remove(struct platform_device *pdev) +static void axi_clkgen_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - - return 0; } static const struct of_device_id axi_clkgen_ids[] = { @@ -583,7 +581,7 @@ static struct platform_driver axi_clkgen_driver = { .of_match_table = axi_clkgen_ids, }, .probe = axi_clkgen_probe, - .remove = axi_clkgen_remove, + .remove_new = axi_clkgen_remove, }; module_platform_driver(axi_clkgen_driver); diff --git a/drivers/clk/clk-axm5516.c b/drivers/clk/clk-axm5516.c index 07e80fe8c310..1dff2017ad9d 100644 --- a/drivers/clk/clk-axm5516.c +++ b/drivers/clk/clk-axm5516.c @@ -572,15 +572,14 @@ static int axmclk_probe(struct platform_device *pdev) return of_clk_add_hw_provider(dev->of_node, of_clk_axmclk_get, NULL); } -static int axmclk_remove(struct platform_device *pdev) +static void axmclk_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - return 0; } static struct platform_driver axmclk_driver = { .probe = axmclk_probe, - .remove = axmclk_remove, + .remove_new = axmclk_remove, .driver = { .name = "clk-axm5516", .of_match_table = axmclk_match_table, diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index f734e34735a9..b3e66202b942 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -297,14 +297,12 @@ void __init of_fixed_factor_clk_setup(struct device_node *node) CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock", of_fixed_factor_clk_setup); -static int of_fixed_factor_clk_remove(struct platform_device *pdev) +static void of_fixed_factor_clk_remove(struct platform_device *pdev) { struct clk_hw *clk = platform_get_drvdata(pdev); of_clk_del_provider(pdev->dev.of_node); clk_hw_unregister_fixed_factor(clk); - - return 0; } static int of_fixed_factor_clk_probe(struct platform_device *pdev) @@ -336,7 +334,7 @@ static struct platform_driver of_fixed_factor_clk_driver = { .of_match_table = of_fixed_factor_clk_ids, }, .probe = of_fixed_factor_clk_probe, - .remove = of_fixed_factor_clk_remove, + .remove_new = of_fixed_factor_clk_remove, }; builtin_platform_driver(of_fixed_factor_clk_driver); #endif diff --git a/drivers/clk/clk-fixed-mmio.c b/drivers/clk/clk-fixed-mmio.c index 5225d17d6b3f..7435055670d2 100644 --- a/drivers/clk/clk-fixed-mmio.c +++ b/drivers/clk/clk-fixed-mmio.c @@ -71,14 +71,12 @@ static int of_fixed_mmio_clk_probe(struct platform_device *pdev) return 0; } -static int of_fixed_mmio_clk_remove(struct platform_device *pdev) +static void of_fixed_mmio_clk_remove(struct platform_device *pdev) { struct clk_hw *clk = platform_get_drvdata(pdev); of_clk_del_provider(pdev->dev.of_node); clk_hw_unregister_fixed_rate(clk); - - return 0; } static const struct of_device_id of_fixed_mmio_clk_ids[] = { @@ -93,7 +91,7 @@ static struct platform_driver of_fixed_mmio_clk_driver = { .of_match_table = of_fixed_mmio_clk_ids, }, .probe = of_fixed_mmio_clk_probe, - .remove = of_fixed_mmio_clk_remove, + .remove_new = of_fixed_mmio_clk_remove, }; module_platform_driver(of_fixed_mmio_clk_driver); diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c index 7d775954e26d..3481eb8cdeb3 100644 --- a/drivers/clk/clk-fixed-rate.c +++ b/drivers/clk/clk-fixed-rate.c @@ -196,14 +196,12 @@ void __init of_fixed_clk_setup(struct device_node *node) } CLK_OF_DECLARE(fixed_clk, "fixed-clock", of_fixed_clk_setup); -static int of_fixed_clk_remove(struct platform_device *pdev) +static void of_fixed_clk_remove(struct platform_device *pdev) { struct clk_hw *hw = platform_get_drvdata(pdev); of_clk_del_provider(pdev->dev.of_node); clk_hw_unregister_fixed_rate(hw); - - return 0; } static int of_fixed_clk_probe(struct platform_device *pdev) @@ -234,7 +232,7 @@ static struct platform_driver of_fixed_clk_driver = { .of_match_table = of_fixed_clk_ids, }, .probe = of_fixed_clk_probe, - .remove = of_fixed_clk_remove, + .remove_new = of_fixed_clk_remove, }; builtin_platform_driver(of_fixed_clk_driver); #endif diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c index 60007b508590..766e139972fe 100644 --- a/drivers/clk/clk-hsdk-pll.c +++ b/drivers/clk/clk-hsdk-pll.c @@ -350,10 +350,9 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev) &pll_clk->hw); } -static int hsdk_pll_clk_remove(struct platform_device *pdev) +static void hsdk_pll_clk_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - return 0; } static void __init of_hsdk_pll_clk_setup(struct device_node *node) @@ -432,6 +431,6 @@ static struct platform_driver hsdk_pll_clk_driver = { .of_match_table = hsdk_pll_clk_id, }, .probe = hsdk_pll_clk_probe, - .remove = hsdk_pll_clk_remove, + .remove_new = hsdk_pll_clk_remove, }; builtin_platform_driver(hsdk_pll_clk_driver); diff --git a/drivers/clk/clk-loongson1.c b/drivers/clk/clk-loongson1.c new file mode 100644 index 000000000000..a3467aa6790f --- /dev/null +++ b/drivers/clk/clk-loongson1.c @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Clock driver for Loongson-1 SoC + * + * Copyright (C) 2012-2023 Keguang Zhang <keguang.zhang@gmail.com> + */ + +#include <linux/bits.h> +#include <linux/clk-provider.h> +#include <linux/container_of.h> +#include <linux/io.h> +#include <linux/of_address.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/printk.h> + +#include <dt-bindings/clock/loongson,ls1x-clk.h> + +/* Loongson 1 Clock Register Definitions */ +#define CLK_PLL_FREQ 0x0 +#define CLK_PLL_DIV 0x4 + +static DEFINE_SPINLOCK(ls1x_clk_div_lock); + +struct ls1x_clk_pll_data { + u32 fixed; + u8 shift; + u8 int_shift; + u8 int_width; + u8 frac_shift; + u8 frac_width; +}; + +struct ls1x_clk_div_data { + u8 shift; + u8 width; + unsigned long flags; + const struct clk_div_table *table; + u8 bypass_shift; + u8 bypass_inv; + spinlock_t *lock; /* protect access to DIV registers */ +}; + +struct ls1x_clk { + void __iomem *reg; + unsigned int offset; + struct clk_hw hw; + const void *data; +}; + +#define to_ls1x_clk(_hw) container_of(_hw, struct ls1x_clk, hw) + +static inline unsigned long ls1x_pll_rate_part(unsigned int val, + unsigned int shift, + unsigned int width) +{ + return (val & GENMASK(shift + width, shift)) >> shift; +} + +static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw); + const struct ls1x_clk_pll_data *d = ls1x_clk->data; + u32 val, rate; + + val = readl(ls1x_clk->reg); + rate = d->fixed; + rate += ls1x_pll_rate_part(val, d->int_shift, d->int_width); + if (d->frac_width) + rate += ls1x_pll_rate_part(val, d->frac_shift, d->frac_width); + rate *= parent_rate; + rate >>= d->shift; + + return rate; +} + +static const struct clk_ops ls1x_pll_clk_ops = { + .recalc_rate = ls1x_pll_recalc_rate, +}; + +static unsigned long ls1x_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw); + const struct ls1x_clk_div_data *d = ls1x_clk->data; + unsigned int val; + + val = readl(ls1x_clk->reg) >> d->shift; + val &= clk_div_mask(d->width); + + return divider_recalc_rate(hw, parent_rate, val, d->table, + d->flags, d->width); +} + +static long ls1x_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw); + const struct ls1x_clk_div_data *d = ls1x_clk->data; + + return divider_round_rate(hw, rate, prate, d->table, + d->width, d->flags); +} + +static int ls1x_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw); + const struct ls1x_clk_div_data *d = ls1x_clk->data; + int val, div_val; + unsigned long flags = 0; + + div_val = divider_get_val(rate, parent_rate, d->table, + d->width, d->flags); + if (div_val < 0) + return div_val; + + spin_lock_irqsave(d->lock, flags); + + /* Bypass the clock */ + val = readl(ls1x_clk->reg); + if (d->bypass_inv) + val &= ~BIT(d->bypass_shift); + else + val |= BIT(d->bypass_shift); + writel(val, ls1x_clk->reg); + + val = readl(ls1x_clk->reg); + val &= ~(clk_div_mask(d->width) << d->shift); + val |= (u32)div_val << d->shift; + writel(val, ls1x_clk->reg); + + /* Restore the clock */ + val = readl(ls1x_clk->reg); + if (d->bypass_inv) + val |= BIT(d->bypass_shift); + else + val &= ~BIT(d->bypass_shift); + writel(val, ls1x_clk->reg); + + spin_unlock_irqrestore(d->lock, flags); + + return 0; +} + +static const struct clk_ops ls1x_clk_divider_ops = { + .recalc_rate = ls1x_divider_recalc_rate, + .round_rate = ls1x_divider_round_rate, + .set_rate = ls1x_divider_set_rate, +}; + +#define LS1X_CLK_PLL(_name, _offset, _fixed, _shift, \ + f_shift, f_width, i_shift, i_width) \ +struct ls1x_clk _name = { \ + .offset = (_offset), \ + .data = &(const struct ls1x_clk_pll_data) { \ + .fixed = (_fixed), \ + .shift = (_shift), \ + .int_shift = (i_shift), \ + .int_width = (i_width), \ + .frac_shift = (f_shift), \ + .frac_width = (f_width), \ + }, \ + .hw.init = &(const struct clk_init_data) { \ + .name = #_name, \ + .ops = &ls1x_pll_clk_ops, \ + .parent_data = &(const struct clk_parent_data) { \ + .fw_name = "xtal", \ + .name = "xtal", \ + .index = -1, \ + }, \ + .num_parents = 1, \ + }, \ +} + +#define LS1X_CLK_DIV(_name, _pname, _offset, _shift, _width, \ + _table, _bypass_shift, _bypass_inv, _flags) \ +struct ls1x_clk _name = { \ + .offset = (_offset), \ + .data = &(const struct ls1x_clk_div_data){ \ + .shift = (_shift), \ + .width = (_width), \ + .table = (_table), \ + .flags = (_flags), \ + .bypass_shift = (_bypass_shift), \ + .bypass_inv = (_bypass_inv), \ + .lock = &ls1x_clk_div_lock, \ + }, \ + .hw.init = &(const struct clk_init_data) { \ + .name = #_name, \ + .ops = &ls1x_clk_divider_ops, \ + .parent_hws = (const struct clk_hw *[]) { _pname }, \ + .num_parents = 1, \ + .flags = CLK_GET_RATE_NOCACHE, \ + }, \ +} + +static LS1X_CLK_PLL(ls1b_clk_pll, CLK_PLL_FREQ, 12, 1, 0, 5, 0, 0); +static LS1X_CLK_DIV(ls1b_clk_cpu, &ls1b_clk_pll.hw, CLK_PLL_DIV, + 20, 4, NULL, 8, 0, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST); +static LS1X_CLK_DIV(ls1b_clk_dc, &ls1b_clk_pll.hw, CLK_PLL_DIV, + 26, 4, NULL, 12, 0, CLK_DIVIDER_ONE_BASED); +static LS1X_CLK_DIV(ls1b_clk_ahb, &ls1b_clk_pll.hw, CLK_PLL_DIV, + 14, 4, NULL, 10, 0, CLK_DIVIDER_ONE_BASED); +static CLK_FIXED_FACTOR(ls1b_clk_apb, "ls1b_clk_apb", "ls1b_clk_ahb", 2, 1, + CLK_SET_RATE_PARENT); + +static struct clk_hw_onecell_data ls1b_clk_hw_data = { + .hws = { + [LS1X_CLKID_PLL] = &ls1b_clk_pll.hw, + [LS1X_CLKID_CPU] = &ls1b_clk_cpu.hw, + [LS1X_CLKID_DC] = &ls1b_clk_dc.hw, + [LS1X_CLKID_AHB] = &ls1b_clk_ahb.hw, + [LS1X_CLKID_APB] = &ls1b_clk_apb.hw, + }, + .num = CLK_NR_CLKS, +}; + +static const struct clk_div_table ls1c_ahb_div_table[] = { + [0] = { .val = 0, .div = 2 }, + [1] = { .val = 1, .div = 4 }, + [2] = { .val = 2, .div = 3 }, + [3] = { .val = 3, .div = 3 }, + [4] = { /* sentinel */ } +}; + +static LS1X_CLK_PLL(ls1c_clk_pll, CLK_PLL_FREQ, 0, 2, 8, 8, 16, 8); +static LS1X_CLK_DIV(ls1c_clk_cpu, &ls1c_clk_pll.hw, CLK_PLL_DIV, + 8, 7, NULL, 0, 1, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLOSEST); +static LS1X_CLK_DIV(ls1c_clk_dc, &ls1c_clk_pll.hw, CLK_PLL_DIV, + 24, 7, NULL, 4, 1, CLK_DIVIDER_ONE_BASED); +static LS1X_CLK_DIV(ls1c_clk_ahb, &ls1c_clk_cpu.hw, CLK_PLL_FREQ, + 0, 2, ls1c_ahb_div_table, 0, 0, CLK_DIVIDER_ALLOW_ZERO); +static CLK_FIXED_FACTOR(ls1c_clk_apb, "ls1c_clk_apb", "ls1c_clk_ahb", 1, 1, + CLK_SET_RATE_PARENT); + +static struct clk_hw_onecell_data ls1c_clk_hw_data = { + .hws = { + [LS1X_CLKID_PLL] = &ls1c_clk_pll.hw, + [LS1X_CLKID_CPU] = &ls1c_clk_cpu.hw, + [LS1X_CLKID_DC] = &ls1c_clk_dc.hw, + [LS1X_CLKID_AHB] = &ls1c_clk_ahb.hw, + [LS1X_CLKID_APB] = &ls1c_clk_apb.hw, + }, + .num = CLK_NR_CLKS, +}; + +static void __init ls1x_clk_init(struct device_node *np, + struct clk_hw_onecell_data *hw_data) +{ + struct ls1x_clk *ls1x_clk; + void __iomem *reg; + int i, ret; + + reg = of_iomap(np, 0); + if (!reg) { + pr_err("Unable to map base for %pOF\n", np); + return; + } + + for (i = 0; i < hw_data->num; i++) { + /* array might be sparse */ + if (!hw_data->hws[i]) + continue; + + if (i != LS1X_CLKID_APB) { + ls1x_clk = to_ls1x_clk(hw_data->hws[i]); + ls1x_clk->reg = reg + ls1x_clk->offset; + } + + ret = of_clk_hw_register(np, hw_data->hws[i]); + if (ret) + goto err; + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, hw_data); + if (!ret) + return; + +err: + pr_err("Failed to register %pOF\n", np); + + while (--i >= 0) + clk_hw_unregister(hw_data->hws[i]); + + iounmap(reg); +} + +static void __init ls1b_clk_init(struct device_node *np) +{ + return ls1x_clk_init(np, &ls1b_clk_hw_data); +} + +static void __init ls1c_clk_init(struct device_node *np) +{ + return ls1x_clk_init(np, &ls1c_clk_hw_data); +} + +CLK_OF_DECLARE(ls1b_clk, "loongson,ls1b-clk", ls1b_clk_init); +CLK_OF_DECLARE(ls1c_clk, "loongson,ls1c-clk", ls1c_clk_init); diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c new file mode 100644 index 000000000000..70ae1dd2e474 --- /dev/null +++ b/drivers/clk/clk-loongson2.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: Yinbo Zhu <zhuyinbo@loongson.cn> + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/clk-provider.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <dt-bindings/clock/loongson,ls2k-clk.h> + +#define LOONGSON2_PLL_MULT_SHIFT 32 +#define LOONGSON2_PLL_MULT_WIDTH 10 +#define LOONGSON2_PLL_DIV_SHIFT 26 +#define LOONGSON2_PLL_DIV_WIDTH 6 +#define LOONGSON2_APB_FREQSCALE_SHIFT 20 +#define LOONGSON2_APB_FREQSCALE_WIDTH 3 +#define LOONGSON2_USB_FREQSCALE_SHIFT 16 +#define LOONGSON2_USB_FREQSCALE_WIDTH 3 +#define LOONGSON2_SATA_FREQSCALE_SHIFT 12 +#define LOONGSON2_SATA_FREQSCALE_WIDTH 3 +#define LOONGSON2_BOOT_FREQSCALE_SHIFT 8 +#define LOONGSON2_BOOT_FREQSCALE_WIDTH 3 + +static void __iomem *loongson2_pll_base; + +static const struct clk_parent_data pdata[] = { + { .fw_name = "ref_100m",}, +}; + +static struct clk_hw *loongson2_clk_register(struct device *dev, + const char *name, + const char *parent_name, + const struct clk_ops *ops, + unsigned long flags) +{ + int ret; + struct clk_hw *hw; + struct clk_init_data init; + + hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL); + if (!hw) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = ops; + init.flags = flags; + init.num_parents = 1; + + if (!parent_name) + init.parent_data = pdata; + else + init.parent_names = &parent_name; + + hw->init = &init; + + ret = devm_clk_hw_register(dev, hw); + if (ret) + hw = ERR_PTR(ret); + + return hw; +} + +static unsigned long loongson2_calc_pll_rate(int offset, unsigned long rate) +{ + u64 val; + u32 mult, div; + + val = readq(loongson2_pll_base + offset); + + mult = (val >> LOONGSON2_PLL_MULT_SHIFT) & + clk_div_mask(LOONGSON2_PLL_MULT_WIDTH); + div = (val >> LOONGSON2_PLL_DIV_SHIFT) & + clk_div_mask(LOONGSON2_PLL_DIV_WIDTH); + + return div_u64((u64)rate * mult, div); +} + +static unsigned long loongson2_node_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return loongson2_calc_pll_rate(0x0, parent_rate); +} + +static const struct clk_ops loongson2_node_clk_ops = { + .recalc_rate = loongson2_node_recalc_rate, +}; + +static unsigned long loongson2_ddr_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return loongson2_calc_pll_rate(0x10, parent_rate); +} + +static const struct clk_ops loongson2_ddr_clk_ops = { + .recalc_rate = loongson2_ddr_recalc_rate, +}; + +static unsigned long loongson2_dc_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return loongson2_calc_pll_rate(0x20, parent_rate); +} + +static const struct clk_ops loongson2_dc_clk_ops = { + .recalc_rate = loongson2_dc_recalc_rate, +}; + +static unsigned long loongson2_pix0_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return loongson2_calc_pll_rate(0x30, parent_rate); +} + +static const struct clk_ops loongson2_pix0_clk_ops = { + .recalc_rate = loongson2_pix0_recalc_rate, +}; + +static unsigned long loongson2_pix1_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return loongson2_calc_pll_rate(0x40, parent_rate); +} + +static const struct clk_ops loongson2_pix1_clk_ops = { + .recalc_rate = loongson2_pix1_recalc_rate, +}; + +static unsigned long loongson2_calc_rate(unsigned long rate, + int shift, int width) +{ + u64 val; + u32 mult; + + val = readq(loongson2_pll_base + 0x50); + + mult = (val >> shift) & clk_div_mask(width); + + return div_u64((u64)rate * (mult + 1), 8); +} + +static unsigned long loongson2_boot_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return loongson2_calc_rate(parent_rate, + LOONGSON2_BOOT_FREQSCALE_SHIFT, + LOONGSON2_BOOT_FREQSCALE_WIDTH); +} + +static const struct clk_ops loongson2_boot_clk_ops = { + .recalc_rate = loongson2_boot_recalc_rate, +}; + +static unsigned long loongson2_apb_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return loongson2_calc_rate(parent_rate, + LOONGSON2_APB_FREQSCALE_SHIFT, + LOONGSON2_APB_FREQSCALE_WIDTH); +} + +static const struct clk_ops loongson2_apb_clk_ops = { + .recalc_rate = loongson2_apb_recalc_rate, +}; + +static unsigned long loongson2_usb_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return loongson2_calc_rate(parent_rate, + LOONGSON2_USB_FREQSCALE_SHIFT, + LOONGSON2_USB_FREQSCALE_WIDTH); +} + +static const struct clk_ops loongson2_usb_clk_ops = { + .recalc_rate = loongson2_usb_recalc_rate, +}; + +static unsigned long loongson2_sata_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return loongson2_calc_rate(parent_rate, + LOONGSON2_SATA_FREQSCALE_SHIFT, + LOONGSON2_SATA_FREQSCALE_WIDTH); +} + +static const struct clk_ops loongson2_sata_clk_ops = { + .recalc_rate = loongson2_sata_recalc_rate, +}; + +static inline int loongson2_check_clk_hws(struct clk_hw *clks[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + if (IS_ERR(clks[i])) { + pr_err("Loongson2 clk %u: register failed with %ld\n", + i, PTR_ERR(clks[i])); + return PTR_ERR(clks[i]); + } + + return 0; +} + +static int loongson2_clk_probe(struct platform_device *pdev) +{ + int ret; + struct clk_hw **hws; + struct clk_hw_onecell_data *clk_hw_data; + spinlock_t loongson2_clk_lock; + struct device *dev = &pdev->dev; + + loongson2_pll_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(loongson2_pll_base)) + return PTR_ERR(loongson2_pll_base); + + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, LOONGSON2_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = LOONGSON2_CLK_END; + hws = clk_hw_data->hws; + + hws[LOONGSON2_NODE_PLL] = loongson2_clk_register(dev, "node_pll", + NULL, + &loongson2_node_clk_ops, 0); + + hws[LOONGSON2_DDR_PLL] = loongson2_clk_register(dev, "ddr_pll", + NULL, + &loongson2_ddr_clk_ops, 0); + + hws[LOONGSON2_DC_PLL] = loongson2_clk_register(dev, "dc_pll", + NULL, + &loongson2_dc_clk_ops, 0); + + hws[LOONGSON2_PIX0_PLL] = loongson2_clk_register(dev, "pix0_pll", + NULL, + &loongson2_pix0_clk_ops, 0); + + hws[LOONGSON2_PIX1_PLL] = loongson2_clk_register(dev, "pix1_pll", + NULL, + &loongson2_pix1_clk_ops, 0); + + hws[LOONGSON2_BOOT_CLK] = loongson2_clk_register(dev, "boot", + NULL, + &loongson2_boot_clk_ops, 0); + + hws[LOONGSON2_NODE_CLK] = devm_clk_hw_register_divider(dev, "node", + "node_pll", 0, + loongson2_pll_base + 0x8, 0, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + /* + * The hda clk divisor in the upper 32bits and the clk-prodiver + * layer code doesn't support 64bit io operation thus a conversion + * is required that subtract shift by 32 and add 4byte to the hda + * address + */ + hws[LOONGSON2_HDA_CLK] = devm_clk_hw_register_divider(dev, "hda", + "ddr_pll", 0, + loongson2_pll_base + 0x22, 12, + 7, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_GPU_CLK] = devm_clk_hw_register_divider(dev, "gpu", + "ddr_pll", 0, + loongson2_pll_base + 0x18, 22, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_DDR_CLK] = devm_clk_hw_register_divider(dev, "ddr", + "ddr_pll", 0, + loongson2_pll_base + 0x18, 0, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_GMAC_CLK] = devm_clk_hw_register_divider(dev, "gmac", + "dc_pll", 0, + loongson2_pll_base + 0x28, 22, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_DC_CLK] = devm_clk_hw_register_divider(dev, "dc", + "dc_pll", 0, + loongson2_pll_base + 0x28, 0, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_APB_CLK] = loongson2_clk_register(dev, "apb", + "gmac", + &loongson2_apb_clk_ops, 0); + + hws[LOONGSON2_USB_CLK] = loongson2_clk_register(dev, "usb", + "gmac", + &loongson2_usb_clk_ops, 0); + + hws[LOONGSON2_SATA_CLK] = loongson2_clk_register(dev, "sata", + "gmac", + &loongson2_sata_clk_ops, 0); + + hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0", + "pix0_pll", 0, + loongson2_pll_base + 0x38, 0, 6, + CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1", + "pix1_pll", 0, + loongson2_pll_base + 0x48, 0, 6, + CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + ret = loongson2_check_clk_hws(hws, LOONGSON2_CLK_END); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data); +} + +static const struct of_device_id loongson2_clk_match_table[] = { + { .compatible = "loongson,ls2k-clk" }, + { } +}; +MODULE_DEVICE_TABLE(of, loongson2_clk_match_table); + +static struct platform_driver loongson2_clk_driver = { + .probe = loongson2_clk_probe, + .driver = { + .name = "loongson2-clk", + .of_match_table = loongson2_clk_match_table, + }, +}; +module_platform_driver(loongson2_clk_driver); + +MODULE_DESCRIPTION("Loongson2 clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c index 80b9d78493bc..050fd4fb588f 100644 --- a/drivers/clk/clk-milbeaut.c +++ b/drivers/clk/clk-milbeaut.c @@ -560,14 +560,12 @@ static void m10v_reg_mux_pre(const struct m10v_clk_mux_factors *factors, static int m10v_clk_probe(struct platform_device *pdev) { int id; - struct resource *res; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; void __iomem *base; const char *parent_name; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(dev, res); + base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(base)) return PTR_ERR(base); diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c index b8c3d0da1918..74a241b1e1f4 100644 --- a/drivers/clk/clk-palmas.c +++ b/drivers/clk/clk-palmas.c @@ -271,10 +271,9 @@ static int palmas_clks_probe(struct platform_device *pdev) return ret; } -static int palmas_clks_remove(struct platform_device *pdev) +static void palmas_clks_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - return 0; } static struct platform_driver palmas_clks_driver = { @@ -283,7 +282,7 @@ static struct platform_driver palmas_clks_driver = { .of_match_table = palmas_clks_of_match, }, .probe = palmas_clks_probe, - .remove = palmas_clks_remove, + .remove_new = palmas_clks_remove, }; module_platform_driver(palmas_clks_driver); diff --git a/drivers/clk/clk-pwm.c b/drivers/clk/clk-pwm.c index da2c8eddfd9f..3dd2b83d0404 100644 --- a/drivers/clk/clk-pwm.c +++ b/drivers/clk/clk-pwm.c @@ -129,11 +129,9 @@ static int clk_pwm_probe(struct platform_device *pdev) return of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clk_pwm->hw); } -static int clk_pwm_remove(struct platform_device *pdev) +static void clk_pwm_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - - return 0; } static const struct of_device_id clk_pwm_dt_ids[] = { @@ -144,7 +142,7 @@ MODULE_DEVICE_TABLE(of, clk_pwm_dt_ids); static struct platform_driver clk_pwm_driver = { .probe = clk_pwm_probe, - .remove = clk_pwm_remove, + .remove_new = clk_pwm_remove, .driver = { .name = "pwm-clock", .of_match_table = clk_pwm_dt_ids, diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c index f91f30560820..6799fb0fa2d3 100644 --- a/drivers/clk/clk-renesas-pcie.c +++ b/drivers/clk/clk-renesas-pcie.c @@ -6,6 +6,7 @@ * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ * Currently supported: * - 9FGV0241 + * - 9FGV0441 * * Copyright (C) 2022 Marek Vasut <marex@denx.de> */ @@ -18,7 +19,6 @@ #include <linux/regmap.h> #define RS9_REG_OE 0x0 -#define RS9_REG_OE_DIF_OE(n) BIT((n) + 1) #define RS9_REG_SS 0x1 #define RS9_REG_SS_AMP_0V6 0x0 #define RS9_REG_SS_AMP_0V7 0x1 @@ -31,9 +31,6 @@ #define RS9_REG_SS_SSC_MASK (3 << 3) #define RS9_REG_SS_SSC_LOCK BIT(5) #define RS9_REG_SR 0x2 -#define RS9_REG_SR_2V0_DIF(n) 0 -#define RS9_REG_SR_3V0_DIF(n) BIT((n) + 1) -#define RS9_REG_SR_DIF_MASK(n) BIT((n) + 1) #define RS9_REG_REF 0x3 #define RS9_REG_REF_OE BIT(4) #define RS9_REG_REF_OD BIT(5) @@ -45,22 +42,31 @@ #define RS9_REG_DID 0x6 #define RS9_REG_BCP 0x7 +#define RS9_REG_VID_IDT 0x01 + +#define RS9_REG_DID_TYPE_FGV (0x0 << RS9_REG_DID_TYPE_SHIFT) +#define RS9_REG_DID_TYPE_DBV (0x1 << RS9_REG_DID_TYPE_SHIFT) +#define RS9_REG_DID_TYPE_DMV (0x2 << RS9_REG_DID_TYPE_SHIFT) +#define RS9_REG_DID_TYPE_SHIFT 0x6 + /* Supported Renesas 9-series models. */ enum rs9_model { RENESAS_9FGV0241, + RENESAS_9FGV0441, }; /* Structure to describe features of a particular 9-series model */ struct rs9_chip_info { const enum rs9_model model; unsigned int num_clks; + u8 did; }; struct rs9_driver_data { struct i2c_client *client; struct regmap *regmap; const struct rs9_chip_info *chip_info; - struct clk_hw *clk_dif[2]; + struct clk_hw *clk_dif[4]; u8 pll_amplitude; u8 pll_ssc; u8 clk_dif_sr; @@ -151,17 +157,29 @@ static const struct regmap_config rs9_regmap_config = { .reg_read = rs9_regmap_i2c_read, }; +static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx) +{ + enum rs9_model model = rs9->chip_info->model; + + if (model == RENESAS_9FGV0241) + return BIT(idx) + 1; + else if (model == RENESAS_9FGV0441) + return BIT(idx); + + return 0; +} + static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx) { struct i2c_client *client = rs9->client; + u8 dif = rs9_calc_dif(rs9, idx); unsigned char name[5] = "DIF0"; struct device_node *np; int ret; u32 sr; /* Set defaults */ - rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); - rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx); + rs9->clk_dif_sr |= dif; snprintf(name, 5, "DIF%d", idx); np = of_get_child_by_name(client->dev.of_node, name); @@ -173,11 +191,9 @@ static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx) of_node_put(np); if (!ret) { if (sr == 2000000) { /* 2V/ns */ - rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); - rs9->clk_dif_sr |= RS9_REG_SR_2V0_DIF(idx); + rs9->clk_dif_sr &= ~dif; } else if (sr == 3000000) { /* 3V/ns (default) */ - rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); - rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx); + rs9->clk_dif_sr |= dif; } else ret = dev_err_probe(&client->dev, -EINVAL, "Invalid renesas,slew-rate value\n"); @@ -248,11 +264,13 @@ static void rs9_update_config(struct rs9_driver_data *rs9) } for (i = 0; i < rs9->chip_info->num_clks; i++) { - if (rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i)) + u8 dif = rs9_calc_dif(rs9, i); + + if (rs9->clk_dif_sr & dif) continue; - regmap_update_bits(rs9->regmap, RS9_REG_SR, RS9_REG_SR_3V0_DIF(i), - rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i)); + regmap_update_bits(rs9->regmap, RS9_REG_SR, dif, + rs9->clk_dif_sr & dif); } } @@ -269,6 +287,7 @@ static int rs9_probe(struct i2c_client *client) { unsigned char name[5] = "DIF0"; struct rs9_driver_data *rs9; + unsigned int vid, did; struct clk_hw *hw; int i, ret; @@ -305,6 +324,20 @@ static int rs9_probe(struct i2c_client *client) if (ret < 0) return ret; + ret = regmap_read(rs9->regmap, RS9_REG_VID, &vid); + if (ret < 0) + return ret; + + ret = regmap_read(rs9->regmap, RS9_REG_DID, &did); + if (ret < 0) + return ret; + + if (vid != RS9_REG_VID_IDT || did != rs9->chip_info->did) + return dev_err_probe(&client->dev, -ENODEV, + "Incorrect VID/DID: %#02x, %#02x. Expected %#02x, %#02x\n", + vid, did, RS9_REG_VID_IDT, + rs9->chip_info->did); + /* Register clock */ for (i = 0; i < rs9->chip_info->num_clks; i++) { snprintf(name, 5, "DIF%d", i); @@ -348,16 +381,25 @@ static int __maybe_unused rs9_resume(struct device *dev) static const struct rs9_chip_info renesas_9fgv0241_info = { .model = RENESAS_9FGV0241, .num_clks = 2, + .did = RS9_REG_DID_TYPE_FGV | 0x02, +}; + +static const struct rs9_chip_info renesas_9fgv0441_info = { + .model = RENESAS_9FGV0441, + .num_clks = 4, + .did = RS9_REG_DID_TYPE_FGV | 0x04, }; static const struct i2c_device_id rs9_id[] = { { "9fgv0241", .driver_data = RENESAS_9FGV0241 }, + { "9fgv0441", .driver_data = RENESAS_9FGV0441 }, { } }; MODULE_DEVICE_TABLE(i2c, rs9_id); static const struct of_device_id clk_rs9_of_match[] = { { .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info }, + { .compatible = "renesas,9fgv0441", .data = &renesas_9fgv0441_info }, { } }; MODULE_DEVICE_TABLE(of, clk_rs9_of_match); diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c index a3e883a9f406..38c456540d1b 100644 --- a/drivers/clk/clk-s2mps11.c +++ b/drivers/clk/clk-s2mps11.c @@ -202,7 +202,7 @@ err_reg: return ret; } -static int s2mps11_clk_remove(struct platform_device *pdev) +static void s2mps11_clk_remove(struct platform_device *pdev) { struct s2mps11_clk *s2mps11_clks = platform_get_drvdata(pdev); int i; @@ -217,8 +217,6 @@ static int s2mps11_clk_remove(struct platform_device *pdev) continue; clkdev_drop(s2mps11_clks[i].lookup); } - - return 0; } static const struct platform_device_id s2mps11_clk_id[] = { @@ -265,7 +263,7 @@ static struct platform_driver s2mps11_clk_driver = { .name = "s2mps11-clk", }, .probe = s2mps11_clk_probe, - .remove = s2mps11_clk_remove, + .remove_new = s2mps11_clk_remove, .id_table = s2mps11_clk_id, }; module_platform_driver(s2mps11_clk_driver); diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c index a39af7616b13..3fb4003453ee 100644 --- a/drivers/clk/clk-scpi.c +++ b/drivers/clk/clk-scpi.c @@ -246,7 +246,7 @@ static int scpi_clk_add(struct device *dev, struct device_node *np, return of_clk_add_hw_provider(np, scpi_of_clk_src_get, clk_data); } -static int scpi_clocks_remove(struct platform_device *pdev) +static void scpi_clocks_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *child, *np = dev->of_node; @@ -258,7 +258,6 @@ static int scpi_clocks_remove(struct platform_device *pdev) for_each_available_child_of_node(np, child) of_clk_del_provider(np); - return 0; } static int scpi_clocks_probe(struct platform_device *pdev) @@ -305,7 +304,7 @@ static struct platform_driver scpi_clocks_driver = { .of_match_table = scpi_clocks_ids, }, .probe = scpi_clocks_probe, - .remove = scpi_clocks_remove, + .remove_new = scpi_clocks_remove, }; module_platform_driver(scpi_clocks_driver); diff --git a/drivers/clk/clk-si521xx.c b/drivers/clk/clk-si521xx.c new file mode 100644 index 000000000000..ac8d4c59cd3d --- /dev/null +++ b/drivers/clk/clk-si521xx.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for Skyworks Si521xx PCIe clock generator driver + * + * The following series can be supported: + * - Si52144 - 4x DIFF + * - Si52146 - 6x DIFF + * - Si52147 - 9x DIFF + * Currently tested: + * - Si52144 + * + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +#include <linux/bitfield.h> +#include <linux/bitrev.h> +#include <linux/clk-provider.h> +#include <linux/i2c.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regmap.h> + +/* OE1 and OE2 register */ +#define SI521XX_REG_OE(n) (((n) & 0x1) + 1) +#define SI521XX_REG_ID 0x3 +#define SI521XX_REG_ID_PROG GENMASK(7, 4) +#define SI521XX_REG_ID_VENDOR GENMASK(3, 0) +#define SI521XX_REG_BC 0x4 +#define SI521XX_REG_DA 0x5 +#define SI521XX_REG_DA_AMP_SEL BIT(7) +#define SI521XX_REG_DA_AMP_MASK GENMASK(6, 4) +#define SI521XX_REG_DA_AMP_MIN 300000 +#define SI521XX_REG_DA_AMP_DEFAULT 800000 +#define SI521XX_REG_DA_AMP_MAX 1000000 +#define SI521XX_REG_DA_AMP_STEP 100000 +#define SI521XX_REG_DA_AMP(UV) \ + FIELD_PREP(SI521XX_REG_DA_AMP_MASK, \ + ((UV) - SI521XX_REG_DA_AMP_MIN) / SI521XX_REG_DA_AMP_STEP) +#define SI521XX_REG_DA_UNKNOWN BIT(3) /* Always set */ + +/* Count of populated OE bits in control register ref, 1 and 2 */ +#define SI521XX_OE_MAP(cr1, cr2) (((cr2) << 8) | (cr1)) +#define SI521XX_OE_MAP_GET_OE(oe, map) (((map) >> (((oe) - 1) * 8)) & 0xff) + +#define SI521XX_DIFF_MULT 4 +#define SI521XX_DIFF_DIV 1 + +/* Supported Skyworks Si521xx models. */ +enum si521xx_model { + SI52144 = 0x44, + SI52146 = 0x46, + SI52147 = 0x47, +}; + +struct si521xx; + +struct si_clk { + struct clk_hw hw; + struct si521xx *si; + u8 reg; + u8 bit; +}; + +struct si521xx { + struct i2c_client *client; + struct regmap *regmap; + struct si_clk clk_dif[9]; + u16 chip_info; + u8 pll_amplitude; +}; + +/* + * Si521xx i2c regmap + */ +static const struct regmap_range si521xx_readable_ranges[] = { + regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_DA), +}; + +static const struct regmap_access_table si521xx_readable_table = { + .yes_ranges = si521xx_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(si521xx_readable_ranges), +}; + +static const struct regmap_range si521xx_writeable_ranges[] = { + regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_OE(1)), + regmap_reg_range(SI521XX_REG_BC, SI521XX_REG_DA), +}; + +static const struct regmap_access_table si521xx_writeable_table = { + .yes_ranges = si521xx_writeable_ranges, + .n_yes_ranges = ARRAY_SIZE(si521xx_writeable_ranges), +}; + +static int si521xx_regmap_i2c_write(void *context, unsigned int reg, + unsigned int val) +{ + struct i2c_client *i2c = context; + const u8 data[3] = { reg, 1, val }; + const int count = ARRAY_SIZE(data); + int ret; + + ret = i2c_master_send(i2c, data, count); + if (ret == count) + return 0; + else if (ret < 0) + return ret; + else + return -EIO; +} + +static int si521xx_regmap_i2c_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct i2c_client *i2c = context; + struct i2c_msg xfer[2]; + u8 txdata = reg; + u8 rxdata[2]; + int ret; + + xfer[0].addr = i2c->addr; + xfer[0].flags = 0; + xfer[0].len = 1; + xfer[0].buf = (void *)&txdata; + + xfer[1].addr = i2c->addr; + xfer[1].flags = I2C_M_RD; + xfer[1].len = 2; + xfer[1].buf = (void *)rxdata; + + ret = i2c_transfer(i2c->adapter, xfer, 2); + if (ret < 0) + return ret; + if (ret != 2) + return -EIO; + + /* + * Byte 0 is transfer length, which is always 1 due + * to BCP register programming to 1 in si521xx_probe(), + * ignore it and use data from Byte 1. + */ + *val = rxdata[1]; + return 0; +} + +static const struct regmap_config si521xx_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_NONE, + .max_register = SI521XX_REG_DA, + .rd_table = &si521xx_readable_table, + .wr_table = &si521xx_writeable_table, + .reg_write = si521xx_regmap_i2c_write, + .reg_read = si521xx_regmap_i2c_read, +}; + +static unsigned long si521xx_diff_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long long rate; + + rate = (unsigned long long)parent_rate * SI521XX_DIFF_MULT; + do_div(rate, SI521XX_DIFF_DIV); + return (unsigned long)rate; +} + +static long si521xx_diff_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long best_parent; + + best_parent = (rate / SI521XX_DIFF_MULT) * SI521XX_DIFF_DIV; + *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); + + return (*prate / SI521XX_DIFF_DIV) * SI521XX_DIFF_MULT; +} + +static int si521xx_diff_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + /* + * We must report success but we can do so unconditionally because + * si521xx_diff_round_rate returns values that ensure this call is a + * nop. + */ + + return 0; +} + +#define to_si521xx_clk(_hw) container_of(_hw, struct si_clk, hw) + +static int si521xx_diff_prepare(struct clk_hw *hw) +{ + struct si_clk *si_clk = to_si521xx_clk(hw); + struct si521xx *si = si_clk->si; + + regmap_set_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit); + + return 0; +} + +static void si521xx_diff_unprepare(struct clk_hw *hw) +{ + struct si_clk *si_clk = to_si521xx_clk(hw); + struct si521xx *si = si_clk->si; + + regmap_clear_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit); +} + +static const struct clk_ops si521xx_diff_clk_ops = { + .round_rate = si521xx_diff_round_rate, + .set_rate = si521xx_diff_set_rate, + .recalc_rate = si521xx_diff_recalc_rate, + .prepare = si521xx_diff_prepare, + .unprepare = si521xx_diff_unprepare, +}; + +static int si521xx_get_common_config(struct si521xx *si) +{ + struct i2c_client *client = si->client; + struct device_node *np = client->dev.of_node; + unsigned int amp; + int ret; + + /* Set defaults */ + si->pll_amplitude = SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT); + + /* Output clock amplitude */ + ret = of_property_read_u32(np, "skyworks,out-amplitude-microvolt", + &); + if (!ret) { + if (amp < SI521XX_REG_DA_AMP_MIN || amp > SI521XX_REG_DA_AMP_MAX || + amp % SI521XX_REG_DA_AMP_STEP) { + return dev_err_probe(&client->dev, -EINVAL, + "Invalid skyworks,out-amplitude-microvolt value\n"); + } + si->pll_amplitude = SI521XX_REG_DA_AMP(amp); + } + + return 0; +} + +static void si521xx_update_config(struct si521xx *si) +{ + /* If amplitude is non-default, update it. */ + if (si->pll_amplitude == SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT)) + return; + + regmap_update_bits(si->regmap, SI521XX_REG_DA, + SI521XX_REG_DA_AMP_MASK, si->pll_amplitude); +} + +static void si521xx_diff_idx_to_reg_bit(const u16 chip_info, const int idx, + struct si_clk *clk) +{ + unsigned long mask; + int oe, b, ctr = 0; + + for (oe = 1; oe <= 2; oe++) { + mask = bitrev8(SI521XX_OE_MAP_GET_OE(oe, chip_info)); + for_each_set_bit(b, &mask, 8) { + if (ctr++ != idx) + continue; + clk->reg = SI521XX_REG_OE(oe); + clk->bit = 7 - b; + return; + } + } +} + +static struct clk_hw * +si521xx_of_clk_get(struct of_phandle_args *clkspec, void *data) +{ + struct si521xx *si = data; + unsigned int idx = clkspec->args[0]; + + return &si->clk_dif[idx].hw; +} + +static int si521xx_probe(struct i2c_client *client) +{ + const u16 chip_info = (u16)(uintptr_t)device_get_match_data(&client->dev); + const struct clk_parent_data clk_parent_data = { .index = 0 }; + struct si521xx *si; + unsigned char name[6] = "DIFF0"; + struct clk_init_data init = {}; + int i, ret; + + if (!chip_info) + return -EINVAL; + + si = devm_kzalloc(&client->dev, sizeof(*si), GFP_KERNEL); + if (!si) + return -ENOMEM; + + i2c_set_clientdata(client, si); + si->client = client; + + /* Fetch common configuration from DT (if specified) */ + ret = si521xx_get_common_config(si); + if (ret) + return ret; + + si->regmap = devm_regmap_init(&client->dev, NULL, client, + &si521xx_regmap_config); + if (IS_ERR(si->regmap)) + return dev_err_probe(&client->dev, PTR_ERR(si->regmap), + "Failed to allocate register map\n"); + + /* Always read back 1 Byte via I2C */ + ret = regmap_write(si->regmap, SI521XX_REG_BC, 1); + if (ret < 0) + return ret; + + /* Register clock */ + for (i = 0; i < hweight16(chip_info); i++) { + memset(&init, 0, sizeof(init)); + snprintf(name, 6, "DIFF%d", i); + init.name = name; + init.ops = &si521xx_diff_clk_ops; + init.parent_data = &clk_parent_data; + init.num_parents = 1; + init.flags = CLK_SET_RATE_PARENT; + + si->clk_dif[i].hw.init = &init; + si->clk_dif[i].si = si; + + si521xx_diff_idx_to_reg_bit(chip_info, i, &si->clk_dif[i]); + + ret = devm_clk_hw_register(&client->dev, &si->clk_dif[i].hw); + if (ret) + return ret; + } + + ret = devm_of_clk_add_hw_provider(&client->dev, si521xx_of_clk_get, si); + if (!ret) + si521xx_update_config(si); + + return ret; +} + +static int __maybe_unused si521xx_suspend(struct device *dev) +{ + struct si521xx *si = dev_get_drvdata(dev); + + regcache_cache_only(si->regmap, true); + regcache_mark_dirty(si->regmap); + + return 0; +} + +static int __maybe_unused si521xx_resume(struct device *dev) +{ + struct si521xx *si = dev_get_drvdata(dev); + int ret; + + regcache_cache_only(si->regmap, false); + ret = regcache_sync(si->regmap); + if (ret) + dev_err(dev, "Failed to restore register map: %d\n", ret); + return ret; +} + +static const struct i2c_device_id si521xx_id[] = { + { "si52144", .driver_data = SI521XX_OE_MAP(0x5, 0xc0) }, + { "si52146", .driver_data = SI521XX_OE_MAP(0x15, 0xe0) }, + { "si52147", .driver_data = SI521XX_OE_MAP(0x17, 0xf8) }, + { } +}; +MODULE_DEVICE_TABLE(i2c, si521xx_id); + +static const struct of_device_id clk_si521xx_of_match[] = { + { .compatible = "skyworks,si52144", .data = (void *)SI521XX_OE_MAP(0x5, 0xc0) }, + { .compatible = "skyworks,si52146", .data = (void *)SI521XX_OE_MAP(0x15, 0xe0) }, + { .compatible = "skyworks,si52147", .data = (void *)SI521XX_OE_MAP(0x15, 0xf8) }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_si521xx_of_match); + +static SIMPLE_DEV_PM_OPS(si521xx_pm_ops, si521xx_suspend, si521xx_resume); + +static struct i2c_driver si521xx_driver = { + .driver = { + .name = "clk-si521xx", + .pm = &si521xx_pm_ops, + .of_match_table = clk_si521xx_of_match, + }, + .probe_new = si521xx_probe, + .id_table = si521xx_id, +}; +module_i2c_driver(si521xx_driver); + +MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); +MODULE_DESCRIPTION("Skyworks Si521xx PCIe clock generator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c new file mode 100644 index 000000000000..8fec14120105 --- /dev/null +++ b/drivers/clk/clk-sp7021.c @@ -0,0 +1,713 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#include <linux/module.h> +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/bitfield.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/sunplus,sp7021-clkc.h> + +/* speical div_width values for PLLTV/PLLA */ +#define DIV_TV 33 +#define DIV_A 34 + +/* PLLTV parameters */ +enum { + SEL_FRA, + SDM_MOD, + PH_SEL, + NFRA, + DIVR, + DIVN, + DIVM, + P_MAX +}; + +#define MASK_SEL_FRA GENMASK(1, 1) +#define MASK_SDM_MOD GENMASK(2, 2) +#define MASK_PH_SEL GENMASK(4, 4) +#define MASK_NFRA GENMASK(12, 6) +#define MASK_DIVR GENMASK(8, 7) +#define MASK_DIVN GENMASK(7, 0) +#define MASK_DIVM GENMASK(14, 8) + +/* HIWORD_MASK FIELD_PREP */ +#define HWM_FIELD_PREP(mask, value) \ +({ \ + u32 _m = mask; \ + (_m << 16) | FIELD_PREP(_m, value); \ +}) + +struct sp_pll { + struct clk_hw hw; + void __iomem *reg; + spinlock_t lock; /* lock for reg */ + int div_shift; + int div_width; + int pd_bit; /* power down bit idx */ + int bp_bit; /* bypass bit idx */ + unsigned long brate; /* base rate, TODO: replace brate with muldiv */ + u32 p[P_MAX]; /* for hold PLLTV/PLLA parameters */ +}; + +#define to_sp_pll(_hw) container_of(_hw, struct sp_pll, hw) + +struct sp_clk_gate_info { + u16 reg; /* reg_index_shift */ + u16 ext_parent; /* parent is extclk */ +}; + +static const struct sp_clk_gate_info sp_clk_gates[] = { + { 0x02 }, + { 0x05 }, + { 0x06 }, + { 0x07 }, + { 0x09 }, + { 0x0b, 1 }, + { 0x0f, 1 }, + { 0x14 }, + { 0x15 }, + { 0x16 }, + { 0x17 }, + { 0x18, 1 }, + { 0x19, 1 }, + { 0x1a, 1 }, + { 0x1b, 1 }, + { 0x1c, 1 }, + { 0x1d, 1 }, + { 0x1e }, + { 0x1f, 1 }, + { 0x20 }, + { 0x21 }, + { 0x22 }, + { 0x23 }, + { 0x24 }, + { 0x25 }, + { 0x26 }, + { 0x2a }, + { 0x2b }, + { 0x2d }, + { 0x2e }, + { 0x30 }, + { 0x31 }, + { 0x32 }, + { 0x33 }, + { 0x3d }, + { 0x3e }, + { 0x3f }, + { 0x42 }, + { 0x44 }, + { 0x4b }, + { 0x4c }, + { 0x4d }, + { 0x4e }, + { 0x4f }, + { 0x50 }, + { 0x55 }, + { 0x60 }, + { 0x61 }, + { 0x6a }, + { 0x73 }, + { 0x86 }, + { 0x8a }, + { 0x8b }, + { 0x8d }, + { 0x8e }, + { 0x8f }, + { 0x90 }, + { 0x92 }, + { 0x93 }, + { 0x95 }, + { 0x96 }, + { 0x97 }, + { 0x98 }, + { 0x99 }, +}; + +#define _M 1000000UL +#define F_27M (27 * _M) + +/*********************************** PLL_TV **********************************/ + +/* TODO: set proper FVCO range */ +#define FVCO_MIN (100 * _M) +#define FVCO_MAX (200 * _M) + +#define F_MIN (FVCO_MIN / 8) +#define F_MAX (FVCO_MAX) + +static long plltv_integer_div(struct sp_pll *clk, unsigned long freq) +{ + /* valid m values: 27M must be divisible by m */ + static const u32 m_table[] = { + 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 27, 30, 32 + }; + u32 m, n, r; + unsigned long fvco, nf; + long ret; + + freq = clamp(freq, F_MIN, F_MAX); + + /* DIVR 0~3 */ + for (r = 0; r <= 3; r++) { + fvco = freq << r; + if (fvco <= FVCO_MAX) + break; + } + + /* DIVM */ + for (m = 0; m < ARRAY_SIZE(m_table); m++) { + nf = fvco * m_table[m]; + n = nf / F_27M; + if ((n * F_27M) == nf) + break; + } + if (m >= ARRAY_SIZE(m_table)) { + ret = -EINVAL; + goto err_not_found; + } + + /* save parameters */ + clk->p[SEL_FRA] = 0; + clk->p[DIVR] = r; + clk->p[DIVN] = n; + clk->p[DIVM] = m_table[m]; + + return freq; + +err_not_found: + pr_err("%s: %s freq:%lu not found a valid setting\n", + __func__, clk_hw_get_name(&clk->hw), freq); + + return ret; +} + +/* parameters for PLLTV fractional divider */ +static const u32 pt[][5] = { + /* conventional fractional */ + { + 1, /* factor */ + 5, /* 5 * p0 (nint) */ + 1, /* 1 * p0 */ + F_27M, /* F_27M / p0 */ + 1, /* p0 / p2 */ + }, + /* phase rotation */ + { + 10, /* factor */ + 54, /* 5.4 * p0 (nint) */ + 2, /* 0.2 * p0 */ + F_27M / 10, /* F_27M / p0 */ + 5, /* p0 / p2 */ + }, +}; + +static const u32 sdm_mod_vals[] = { 91, 55 }; + +static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq) +{ + u32 m, r; + u32 nint, nfra; + u32 df_quotient_min = 210000000; + u32 df_remainder_min = 0; + unsigned long fvco, nf, f, fout = 0; + int sdm, ph; + + freq = clamp(freq, F_MIN, F_MAX); + + /* DIVR 0~3 */ + for (r = 0; r <= 3; r++) { + fvco = freq << r; + if (fvco <= FVCO_MAX) + break; + } + f = F_27M >> r; + + /* PH_SEL */ + for (ph = ARRAY_SIZE(pt) - 1; ph >= 0; ph--) { + const u32 *pp = pt[ph]; + + /* SDM_MOD */ + for (sdm = 0; sdm < ARRAY_SIZE(sdm_mod_vals); sdm++) { + u32 mod = sdm_mod_vals[sdm]; + + /* DIVM 1~32 */ + for (m = 1; m <= 32; m++) { + u32 df; /* diff freq */ + u32 df_quotient, df_remainder; + + nf = fvco * m; + nint = nf / pp[3]; + + if (nint < pp[1]) + continue; + if (nint > pp[1]) + break; + + nfra = (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M; + if (nfra) { + u32 df0 = f * (nint + pp[2]) / pp[0]; + u32 df1 = f * (mod - nfra) / mod / pp[4]; + + df = df0 - df1; + } else { + df = f * (nint) / pp[0]; + } + + df_quotient = df / m; + df_remainder = ((df % m) * 1000) / m; + + if (freq > df_quotient) { + df_quotient = freq - df_quotient - 1; + df_remainder = 1000 - df_remainder; + } else { + df_quotient = df_quotient - freq; + } + + if (df_quotient_min > df_quotient || + (df_quotient_min == df_quotient && + df_remainder_min > df_remainder)) { + /* found a closer freq, save parameters */ + clk->p[SEL_FRA] = 1; + clk->p[SDM_MOD] = sdm; + clk->p[PH_SEL] = ph; + clk->p[NFRA] = nfra; + clk->p[DIVR] = r; + clk->p[DIVM] = m; + + fout = df / m; + df_quotient_min = df_quotient; + df_remainder_min = df_remainder; + } + } + } + } + + if (!fout) { + pr_err("%s: %s freq:%lu not found a valid setting\n", + __func__, clk_hw_get_name(&clk->hw), freq); + return -EINVAL; + } + + return fout; +} + +static long plltv_div(struct sp_pll *clk, unsigned long freq) +{ + if (freq % 100) + return plltv_fractional_div(clk, freq); + + return plltv_integer_div(clk, freq); +} + +static int plltv_set_rate(struct sp_pll *clk) +{ + unsigned long flags; + u32 r0, r1, r2; + + r0 = BIT(clk->bp_bit + 16); + r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]); + r0 |= HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]); + r0 |= HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]); + r0 |= HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]); + + r1 = HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]); + + r2 = HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1); + r2 |= HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1); + + spin_lock_irqsave(&clk->lock, flags); + writel(r0, clk->reg); + writel(r1, clk->reg + 4); + writel(r2, clk->reg + 8); + spin_unlock_irqrestore(&clk->lock, flags); + + return 0; +} + +/*********************************** PLL_A ***********************************/ + +/* from Q628_PLLs_REG_setting.xlsx */ +static const struct { + u32 rate; + u32 regs[5]; +} pa[] = { + { + .rate = 135475200, + .regs = { + 0x4801, + 0x02df, + 0x248f, + 0x0211, + 0x33e9 + } + }, + { + .rate = 147456000, + .regs = { + 0x4801, + 0x1adf, + 0x2490, + 0x0349, + 0x33e9 + } + }, + { + .rate = 196608000, + .regs = { + 0x4801, + 0x42ef, + 0x2495, + 0x01c6, + 0x33e9 + } + }, +}; + +static int plla_set_rate(struct sp_pll *clk) +{ + const u32 *pp = pa[clk->p[0]].regs; + unsigned long flags; + int i; + + spin_lock_irqsave(&clk->lock, flags); + for (i = 0; i < ARRAY_SIZE(pa->regs); i++) + writel(0xffff0000 | pp[i], clk->reg + (i * 4)); + spin_unlock_irqrestore(&clk->lock, flags); + + return 0; +} + +static long plla_round_rate(struct sp_pll *clk, unsigned long rate) +{ + int i = ARRAY_SIZE(pa); + + while (--i) { + if (rate >= pa[i].rate) + break; + } + clk->p[0] = i; + + return pa[i].rate; +} + +/********************************** SP_PLL ***********************************/ + +static long sp_pll_calc_div(struct sp_pll *clk, unsigned long rate) +{ + u32 fbdiv; + u32 max = 1 << clk->div_width; + + fbdiv = DIV_ROUND_CLOSEST(rate, clk->brate); + if (fbdiv > max) + fbdiv = max; + + return fbdiv; +} + +static long sp_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct sp_pll *clk = to_sp_pll(hw); + long ret; + + if (rate == *prate) { + ret = *prate; /* bypass */ + } else if (clk->div_width == DIV_A) { + ret = plla_round_rate(clk, rate); + } else if (clk->div_width == DIV_TV) { + ret = plltv_div(clk, rate); + if (ret < 0) + ret = *prate; + } else { + ret = sp_pll_calc_div(clk, rate) * clk->brate; + } + + return ret; +} + +static unsigned long sp_pll_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct sp_pll *clk = to_sp_pll(hw); + u32 reg = readl(clk->reg); + unsigned long ret; + + if (reg & BIT(clk->bp_bit)) { + ret = prate; /* bypass */ + } else if (clk->div_width == DIV_A) { + ret = pa[clk->p[0]].rate; + } else if (clk->div_width == DIV_TV) { + u32 m, r, reg2; + + r = FIELD_GET(MASK_DIVR, readl(clk->reg + 4)); + reg2 = readl(clk->reg + 8); + m = FIELD_GET(MASK_DIVM, reg2) + 1; + + if (reg & MASK_SEL_FRA) { + /* fractional divider */ + u32 sdm = FIELD_GET(MASK_SDM_MOD, reg); + u32 ph = FIELD_GET(MASK_PH_SEL, reg); + u32 nfra = FIELD_GET(MASK_NFRA, reg); + const u32 *pp = pt[ph]; + unsigned long r0, r1; + + ret = prate >> r; + r0 = ret * (pp[1] + pp[2]) / pp[0]; + r1 = ret * (sdm_mod_vals[sdm] - nfra) / sdm_mod_vals[sdm] / pp[4]; + ret = (r0 - r1) / m; + } else { + /* integer divider */ + u32 n = FIELD_GET(MASK_DIVN, reg2) + 1; + + ret = (prate / m * n) >> r; + } + } else { + u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; + + ret = clk->brate * fbdiv; + } + + return ret; +} + +static int sp_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct sp_pll *clk = to_sp_pll(hw); + unsigned long flags; + u32 reg; + + reg = BIT(clk->bp_bit + 16); /* HIWORD_MASK */ + + if (rate == prate) { + reg |= BIT(clk->bp_bit); /* bypass */ + } else if (clk->div_width == DIV_A) { + return plla_set_rate(clk); + } else if (clk->div_width == DIV_TV) { + return plltv_set_rate(clk); + } else if (clk->div_width) { + u32 fbdiv = sp_pll_calc_div(clk, rate); + u32 mask = GENMASK(clk->div_shift + clk->div_width - 1, clk->div_shift); + + reg |= mask << 16; + reg |= ((fbdiv - 1) << clk->div_shift) & mask; + } + + spin_lock_irqsave(&clk->lock, flags); + writel(reg, clk->reg); + spin_unlock_irqrestore(&clk->lock, flags); + + return 0; +} + +static int sp_pll_enable(struct clk_hw *hw) +{ + struct sp_pll *clk = to_sp_pll(hw); + + writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg); + + return 0; +} + +static void sp_pll_disable(struct clk_hw *hw) +{ + struct sp_pll *clk = to_sp_pll(hw); + + writel(BIT(clk->pd_bit + 16), clk->reg); +} + +static int sp_pll_is_enabled(struct clk_hw *hw) +{ + struct sp_pll *clk = to_sp_pll(hw); + + return readl(clk->reg) & BIT(clk->pd_bit); +} + +static const struct clk_ops sp_pll_ops = { + .enable = sp_pll_enable, + .disable = sp_pll_disable, + .is_enabled = sp_pll_is_enabled, + .round_rate = sp_pll_round_rate, + .recalc_rate = sp_pll_recalc_rate, + .set_rate = sp_pll_set_rate +}; + +static const struct clk_ops sp_pll_sub_ops = { + .enable = sp_pll_enable, + .disable = sp_pll_disable, + .is_enabled = sp_pll_is_enabled, + .recalc_rate = sp_pll_recalc_rate, +}; + +static struct clk_hw *sp_pll_register(struct device *dev, const char *name, + const struct clk_parent_data *parent_data, + void __iomem *reg, int pd_bit, int bp_bit, + unsigned long brate, int shift, int width, + unsigned long flags) +{ + struct sp_pll *pll; + struct clk_hw *hw; + struct clk_init_data initd = { + .name = name, + .parent_data = parent_data, + .ops = (bp_bit >= 0) ? &sp_pll_ops : &sp_pll_sub_ops, + .num_parents = 1, + .flags = flags, + }; + int ret; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->hw.init = &initd; + pll->reg = reg; + pll->pd_bit = pd_bit; + pll->bp_bit = bp_bit; + pll->brate = brate; + pll->div_shift = shift; + pll->div_width = width; + spin_lock_init(&pll->lock); + + hw = &pll->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + return hw; +} + +#define PLLA_CTL (pll_base + 0x1c) +#define PLLE_CTL (pll_base + 0x30) +#define PLLF_CTL (pll_base + 0x34) +#define PLLTV_CTL (pll_base + 0x38) + +static int sp7021_clk_probe(struct platform_device *pdev) +{ + static const u32 sp_clken[] = { + 0x67ef, 0x03ff, 0xff03, 0xfff0, 0x0004, /* G0.1~5 */ + 0x0000, 0x8000, 0xffff, 0x0040, 0x0000, /* G0.6~10 */ + }; + static struct clk_parent_data pd_ext, pd_sys, pd_e; + struct device *dev = &pdev->dev; + void __iomem *clk_base, *pll_base, *sys_base; + struct clk_hw_onecell_data *clk_data; + struct clk_hw **hws; + int i; + + clk_base = devm_platform_ioremap_resource(pdev, 0); + if (!clk_base) + return -ENXIO; + pll_base = devm_platform_ioremap_resource(pdev, 1); + if (!pll_base) + return -ENXIO; + sys_base = devm_platform_ioremap_resource(pdev, 2); + if (!sys_base) + return -ENXIO; + + /* enable default clks */ + for (i = 0; i < ARRAY_SIZE(sp_clken); i++) + writel((sp_clken[i] << 16) | sp_clken[i], clk_base + i * 4); + + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, CLK_MAX), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + hws = clk_data->hws; + pd_ext.index = 0; + + /* PLLs */ + hws[PLL_A] = sp_pll_register(dev, "plla", &pd_ext, PLLA_CTL, + 11, 12, 27000000, 0, DIV_A, 0); + if (IS_ERR(hws[PLL_A])) + return PTR_ERR(hws[PLL_A]); + + hws[PLL_E] = sp_pll_register(dev, "plle", &pd_ext, PLLE_CTL, + 6, 2, 50000000, 0, 0, 0); + if (IS_ERR(hws[PLL_E])) + return PTR_ERR(hws[PLL_E]); + pd_e.hw = hws[PLL_E]; + hws[PLL_E_2P5] = sp_pll_register(dev, "plle_2p5", &pd_e, PLLE_CTL, + 13, -1, 2500000, 0, 0, 0); + if (IS_ERR(hws[PLL_E_2P5])) + return PTR_ERR(hws[PLL_E_2P5]); + hws[PLL_E_25] = sp_pll_register(dev, "plle_25", &pd_e, PLLE_CTL, + 12, -1, 25000000, 0, 0, 0); + if (IS_ERR(hws[PLL_E_25])) + return PTR_ERR(hws[PLL_E_25]); + hws[PLL_E_112P5] = sp_pll_register(dev, "plle_112p5", &pd_e, PLLE_CTL, + 11, -1, 112500000, 0, 0, 0); + if (IS_ERR(hws[PLL_E_112P5])) + return PTR_ERR(hws[PLL_E_112P5]); + + hws[PLL_F] = sp_pll_register(dev, "pllf", &pd_ext, PLLF_CTL, + 0, 10, 13500000, 1, 4, 0); + if (IS_ERR(hws[PLL_F])) + return PTR_ERR(hws[PLL_F]); + + hws[PLL_TV] = sp_pll_register(dev, "plltv", &pd_ext, PLLTV_CTL, + 0, 15, 27000000, 0, DIV_TV, 0); + if (IS_ERR(hws[PLL_TV])) + return PTR_ERR(hws[PLL_TV]); + hws[PLL_TV_A] = devm_clk_hw_register_divider(dev, "plltv_a", "plltv", 0, + PLLTV_CTL + 4, 5, 1, + CLK_DIVIDER_POWER_OF_TWO, + &to_sp_pll(hws[PLL_TV])->lock); + if (IS_ERR(hws[PLL_TV_A])) + return PTR_ERR(hws[PLL_TV_A]); + + /* system clock, should not be disabled */ + hws[PLL_SYS] = sp_pll_register(dev, "pllsys", &pd_ext, sys_base, + 10, 9, 13500000, 0, 4, CLK_IS_CRITICAL); + if (IS_ERR(hws[PLL_SYS])) + return PTR_ERR(hws[PLL_SYS]); + pd_sys.hw = hws[PLL_SYS]; + + /* gates */ + for (i = 0; i < ARRAY_SIZE(sp_clk_gates); i++) { + char name[10]; + u32 j = sp_clk_gates[i].reg; + struct clk_parent_data *pd = sp_clk_gates[i].ext_parent ? &pd_ext : &pd_sys; + + sprintf(name, "%02d_0x%02x", i, j); + hws[i] = devm_clk_hw_register_gate_parent_data(dev, name, pd, 0, + clk_base + (j >> 4) * 4, + j & 0x0f, + CLK_GATE_HIWORD_MASK, + NULL); + if (IS_ERR(hws[i])) + return PTR_ERR(hws[i]); + } + + clk_data->num = CLK_MAX; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); +} + +static const struct of_device_id sp7021_clk_dt_ids[] = { + { .compatible = "sunplus,sp7021-clkc" }, + { } +}; +MODULE_DEVICE_TABLE(of, sp7021_clk_dt_ids); + +static struct platform_driver sp7021_clk_driver = { + .probe = sp7021_clk_probe, + .driver = { + .name = "sp7021-clk", + .of_match_table = sp7021_clk_dt_ids, + }, +}; +module_platform_driver(sp7021_clk_driver); + +MODULE_AUTHOR("Sunplus Technology"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Clock driver for Sunplus SP7021 SoC"); diff --git a/drivers/clk/clk-stm32h7.c b/drivers/clk/clk-stm32h7.c index 1a701eada0c1..04c18a1d45d3 100644 --- a/drivers/clk/clk-stm32h7.c +++ b/drivers/clk/clk-stm32h7.c @@ -667,7 +667,6 @@ struct stm32_fractional_divider { void __iomem *mreg; u8 mshift; u8 mwidth; - u32 mmask; void __iomem *nreg; u8 nshift; diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 01e5a466897f..939779f66867 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -2434,15 +2434,13 @@ static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev) return ret; } -static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev) +static void stm32mp1_rcc_clocks_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *child, *np = dev_of_node(dev); for_each_available_child_of_node(np, child) of_clk_del_provider(child); - - return 0; } static struct platform_driver stm32mp1_rcc_clocks_driver = { @@ -2451,7 +2449,7 @@ static struct platform_driver stm32mp1_rcc_clocks_driver = { .of_match_table = stm32mp1_match_data, }, .probe = stm32mp1_rcc_clocks_probe, - .remove = stm32mp1_rcc_clocks_remove, + .remove_new = stm32mp1_rcc_clocks_remove, }; static int __init stm32mp1_clocks_init(void) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index ae07685c7588..27c30a533759 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1406,6 +1406,8 @@ static int __init clk_disable_unused(void) return 0; } + pr_info("clk: Disabling unused clocks\n"); + clk_prepare_lock(); hlist_for_each_entry(core, &clk_root_list, child_node) @@ -3194,7 +3196,7 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c, static int clk_summary_show(struct seq_file *s, void *data) { struct clk_core *c; - struct hlist_head **lists = (struct hlist_head **)s->private; + struct hlist_head **lists = s->private; seq_puts(s, " enable prepare protect duty hardware\n"); seq_puts(s, " clock count count count rate accuracy phase cycle enable\n"); @@ -3253,7 +3255,7 @@ static int clk_dump_show(struct seq_file *s, void *data) { struct clk_core *c; bool first_node = true; - struct hlist_head **lists = (struct hlist_head **)s->private; + struct hlist_head **lists = s->private; seq_putc(s, '{'); clk_prepare_lock(); @@ -4880,8 +4882,8 @@ static struct device_node *get_clk_provider_node(struct device *dev) np = dev->of_node; parent_np = dev->parent ? dev->parent->of_node : NULL; - if (!of_find_property(np, "#clock-cells", NULL)) - if (of_find_property(parent_np, "#clock-cells", NULL)) + if (!of_property_present(np, "#clock-cells")) + if (of_property_present(parent_np, "#clock-cells")) np = parent_np; return np; diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c index ad0c7f350cf0..b871872d9960 100644 --- a/drivers/clk/hisilicon/clk-hi3519.c +++ b/drivers/clk/hisilicon/clk-hi3519.c @@ -162,13 +162,12 @@ static int hi3519_clk_probe(struct platform_device *pdev) return 0; } -static int hi3519_clk_remove(struct platform_device *pdev) +static void hi3519_clk_remove(struct platform_device *pdev) { struct hi3519_crg_data *crg = platform_get_drvdata(pdev); hisi_reset_exit(crg->rstc); hi3519_clk_unregister(pdev); - return 0; } @@ -180,7 +179,7 @@ MODULE_DEVICE_TABLE(of, hi3519_clk_match_table); static struct platform_driver hi3519_clk_driver = { .probe = hi3519_clk_probe, - .remove = hi3519_clk_remove, + .remove_new = hi3519_clk_remove, .driver = { .name = "hi3519-clk", .of_match_table = hi3519_clk_match_table, diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c index 9ea1a80acbe8..4f97638809b7 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -810,18 +810,17 @@ static int hi3559av100_crg_probe(struct platform_device *pdev) return 0; } -static int hi3559av100_crg_remove(struct platform_device *pdev) +static void hi3559av100_crg_remove(struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); hisi_reset_exit(crg->rstc); crg->funcs->unregister_clks(pdev); - return 0; } static struct platform_driver hi3559av100_crg_driver = { .probe = hi3559av100_crg_probe, - .remove = hi3559av100_crg_remove, + .remove_new = hi3559av100_crg_remove, .driver = { .name = "hi3559av100-clock", .of_match_table = hi3559av100_crg_match_table, diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c index 5d4e61c7a429..fe1bd3e3f988 100644 --- a/drivers/clk/hisilicon/crg-hi3516cv300.c +++ b/drivers/clk/hisilicon/crg-hi3516cv300.c @@ -284,18 +284,17 @@ static int hi3516cv300_crg_probe(struct platform_device *pdev) return 0; } -static int hi3516cv300_crg_remove(struct platform_device *pdev) +static void hi3516cv300_crg_remove(struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); hisi_reset_exit(crg->rstc); crg->funcs->unregister_clks(pdev); - return 0; } static struct platform_driver hi3516cv300_crg_driver = { .probe = hi3516cv300_crg_probe, - .remove = hi3516cv300_crg_remove, + .remove_new = hi3516cv300_crg_remove, .driver = { .name = "hi3516cv300-crg", .of_match_table = hi3516cv300_crg_match_table, diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index 08a19ba776e6..a0b16be1e25d 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -367,18 +367,17 @@ static int hi3798cv200_crg_probe(struct platform_device *pdev) return 0; } -static int hi3798cv200_crg_remove(struct platform_device *pdev) +static void hi3798cv200_crg_remove(struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); hisi_reset_exit(crg->rstc); crg->funcs->unregister_clks(pdev); - return 0; } static struct platform_driver hi3798cv200_crg_driver = { .probe = hi3798cv200_crg_probe, - .remove = hi3798cv200_crg_remove, + .remove_new = hi3798cv200_crg_remove, .driver = { .name = "hi3798cv200-crg", .of_match_table = hi3798cv200_crg_match_table, diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c index d4b4e74e22da..910ecd58c4ca 100644 --- a/drivers/clk/keystone/sci-clk.c +++ b/drivers/clk/keystone/sci-clk.c @@ -689,16 +689,14 @@ static int ti_sci_clk_probe(struct platform_device *pdev) * via common clock framework. Any memory allocated for the device will * be free'd silently via the devm framework. Returns 0 always. */ -static int ti_sci_clk_remove(struct platform_device *pdev) +static void ti_sci_clk_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - - return 0; } static struct platform_driver ti_sci_clk_driver = { .probe = ti_sci_clk_probe, - .remove = ti_sci_clk_remove, + .remove_new = ti_sci_clk_remove, .driver = { .name = "ti-sci-clk", .of_match_table = of_match_ptr(ti_sci_clk_of_match), diff --git a/drivers/clk/loongson1/Makefile b/drivers/clk/loongson1/Makefile deleted file mode 100644 index 251d0fe9dcd1..000000000000 --- a/drivers/clk/loongson1/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y += clk.o -obj-$(CONFIG_LOONGSON1_LS1B) += clk-loongson1b.o -obj-$(CONFIG_LOONGSON1_LS1C) += clk-loongson1c.o diff --git a/drivers/clk/loongson1/clk-loongson1b.c b/drivers/clk/loongson1/clk-loongson1b.c deleted file mode 100644 index 13a2ca23a159..000000000000 --- a/drivers/clk/loongson1/clk-loongson1b.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com> - */ - -#include <linux/clkdev.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/err.h> - -#include <loongson1.h> -#include "clk.h" - -#define OSC (33 * 1000000) -#define DIV_APB 2 - -static DEFINE_SPINLOCK(_lock); - -static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - u32 pll, rate; - - pll = __raw_readl(LS1X_CLK_PLL_FREQ); - rate = 12 + (pll & GENMASK(5, 0)); - rate *= OSC; - rate >>= 1; - - return rate; -} - -static const struct clk_ops ls1x_pll_clk_ops = { - .recalc_rate = ls1x_pll_recalc_rate, -}; - -static const char *const cpu_parents[] = { "cpu_clk_div", "osc_clk", }; -static const char *const ahb_parents[] = { "ahb_clk_div", "osc_clk", }; -static const char *const dc_parents[] = { "dc_clk_div", "osc_clk", }; - -void __init ls1x_clk_init(void) -{ - struct clk_hw *hw; - - hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); - clk_hw_register_clkdev(hw, "osc_clk", NULL); - - /* clock derived from 33 MHz OSC clk */ - hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk", - &ls1x_pll_clk_ops, 0); - clk_hw_register_clkdev(hw, "pll_clk", NULL); - - /* clock derived from PLL clk */ - /* _____ - * _______________________| | - * OSC ___/ | MUX |___ CPU CLK - * \___ PLL ___ CPU DIV ___| | - * |_____| - */ - hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk", - CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV, - DIV_CPU_SHIFT, DIV_CPU_WIDTH, - CLK_DIVIDER_ONE_BASED | - CLK_DIVIDER_ROUND_CLOSEST, &_lock); - clk_hw_register_clkdev(hw, "cpu_clk_div", NULL); - hw = clk_hw_register_mux(NULL, "cpu_clk", cpu_parents, - ARRAY_SIZE(cpu_parents), - CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV, - BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock); - clk_hw_register_clkdev(hw, "cpu_clk", NULL); - - /* _____ - * _______________________| | - * OSC ___/ | MUX |___ DC CLK - * \___ PLL ___ DC DIV ___| | - * |_____| - */ - hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk", - 0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT, - DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_hw_register_clkdev(hw, "dc_clk_div", NULL); - hw = clk_hw_register_mux(NULL, "dc_clk", dc_parents, - ARRAY_SIZE(dc_parents), - CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV, - BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock); - clk_hw_register_clkdev(hw, "dc_clk", NULL); - - /* _____ - * _______________________| | - * OSC ___/ | MUX |___ DDR CLK - * \___ PLL ___ DDR DIV ___| | - * |_____| - */ - hw = clk_hw_register_divider(NULL, "ahb_clk_div", "pll_clk", - 0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT, - DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, - &_lock); - clk_hw_register_clkdev(hw, "ahb_clk_div", NULL); - hw = clk_hw_register_mux(NULL, "ahb_clk", ahb_parents, - ARRAY_SIZE(ahb_parents), - CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV, - BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock); - clk_hw_register_clkdev(hw, "ahb_clk", NULL); - clk_hw_register_clkdev(hw, "ls1x-dma", NULL); - clk_hw_register_clkdev(hw, "stmmaceth", NULL); - - /* clock derived from AHB clk */ - /* APB clk is always half of the AHB clk */ - hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, - DIV_APB); - clk_hw_register_clkdev(hw, "apb_clk", NULL); - clk_hw_register_clkdev(hw, "ls1x-ac97", NULL); - clk_hw_register_clkdev(hw, "ls1x-i2c", NULL); - clk_hw_register_clkdev(hw, "ls1x-nand", NULL); - clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL); - clk_hw_register_clkdev(hw, "ls1x-spi", NULL); - clk_hw_register_clkdev(hw, "ls1x-wdt", NULL); - clk_hw_register_clkdev(hw, "serial8250", NULL); -} diff --git a/drivers/clk/loongson1/clk-loongson1c.c b/drivers/clk/loongson1/clk-loongson1c.c deleted file mode 100644 index 1ebf740380ef..000000000000 --- a/drivers/clk/loongson1/clk-loongson1c.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com> - */ - -#include <linux/clkdev.h> -#include <linux/clk-provider.h> -#include <linux/io.h> - -#include <loongson1.h> -#include "clk.h" - -#define OSC (24 * 1000000) -#define DIV_APB 1 - -static DEFINE_SPINLOCK(_lock); - -static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - u32 pll, rate; - - pll = __raw_readl(LS1X_CLK_PLL_FREQ); - rate = ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff); - rate *= OSC; - rate >>= 2; - - return rate; -} - -static const struct clk_ops ls1x_pll_clk_ops = { - .recalc_rate = ls1x_pll_recalc_rate, -}; - -static const struct clk_div_table ahb_div_table[] = { - [0] = { .val = 0, .div = 2 }, - [1] = { .val = 1, .div = 4 }, - [2] = { .val = 2, .div = 3 }, - [3] = { .val = 3, .div = 3 }, - [4] = { /* sentinel */ } -}; - -void __init ls1x_clk_init(void) -{ - struct clk_hw *hw; - - hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); - clk_hw_register_clkdev(hw, "osc_clk", NULL); - - /* clock derived from 24 MHz OSC clk */ - hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk", - &ls1x_pll_clk_ops, 0); - clk_hw_register_clkdev(hw, "pll_clk", NULL); - - hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk", - CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV, - DIV_CPU_SHIFT, DIV_CPU_WIDTH, - CLK_DIVIDER_ONE_BASED | - CLK_DIVIDER_ROUND_CLOSEST, &_lock); - clk_hw_register_clkdev(hw, "cpu_clk_div", NULL); - hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "cpu_clk_div", - 0, 1, 1); - clk_hw_register_clkdev(hw, "cpu_clk", NULL); - - hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk", - 0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT, - DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); - clk_hw_register_clkdev(hw, "dc_clk_div", NULL); - hw = clk_hw_register_fixed_factor(NULL, "dc_clk", "dc_clk_div", - 0, 1, 1); - clk_hw_register_clkdev(hw, "dc_clk", NULL); - - hw = clk_hw_register_divider_table(NULL, "ahb_clk_div", "cpu_clk_div", - 0, LS1X_CLK_PLL_FREQ, DIV_DDR_SHIFT, - DIV_DDR_WIDTH, CLK_DIVIDER_ALLOW_ZERO, - ahb_div_table, &_lock); - clk_hw_register_clkdev(hw, "ahb_clk_div", NULL); - hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "ahb_clk_div", - 0, 1, 1); - clk_hw_register_clkdev(hw, "ahb_clk", NULL); - clk_hw_register_clkdev(hw, "ls1x-dma", NULL); - clk_hw_register_clkdev(hw, "stmmaceth", NULL); - - /* clock derived from AHB clk */ - hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, - DIV_APB); - clk_hw_register_clkdev(hw, "apb_clk", NULL); - clk_hw_register_clkdev(hw, "ls1x-ac97", NULL); - clk_hw_register_clkdev(hw, "ls1x-i2c", NULL); - clk_hw_register_clkdev(hw, "ls1x-nand", NULL); - clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL); - clk_hw_register_clkdev(hw, "ls1x-spi", NULL); - clk_hw_register_clkdev(hw, "ls1x-wdt", NULL); - clk_hw_register_clkdev(hw, "serial8250", NULL); -} diff --git a/drivers/clk/loongson1/clk.c b/drivers/clk/loongson1/clk.c deleted file mode 100644 index f336a3126d31..000000000000 --- a/drivers/clk/loongson1/clk.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com> - */ - -#include <linux/clk-provider.h> -#include <linux/slab.h> - -#include "clk.h" - -struct clk_hw *__init clk_hw_register_pll(struct device *dev, - const char *name, - const char *parent_name, - const struct clk_ops *ops, - unsigned long flags) -{ - int ret; - struct clk_hw *hw; - struct clk_init_data init; - - /* allocate the divider */ - hw = kzalloc(sizeof(*hw), GFP_KERNEL); - if (!hw) - return ERR_PTR(-ENOMEM); - - init.name = name; - init.ops = ops; - init.flags = flags; - init.parent_names = parent_name ? &parent_name : NULL; - init.num_parents = parent_name ? 1 : 0; - hw->init = &init; - - /* register the clock */ - ret = clk_hw_register(dev, hw); - if (ret) { - kfree(hw); - hw = ERR_PTR(ret); - } - - return hw; -} diff --git a/drivers/clk/loongson1/clk.h b/drivers/clk/loongson1/clk.h deleted file mode 100644 index 124642302b12..000000000000 --- a/drivers/clk/loongson1/clk.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com> - */ - -#ifndef __LOONGSON1_CLK_H -#define __LOONGSON1_CLK_H - -struct clk_hw *clk_hw_register_pll(struct device *dev, - const char *name, - const char *parent_name, - const struct clk_ops *ops, - unsigned long flags); - -#endif /* __LOONGSON1_CLK_H */ diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 2d14855dd37e..99e67c07e638 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -75,7 +75,7 @@ config COMMON_CLK_MT2701_G3DSYS This driver supports MediaTek MT2701 g3dsys clocks. config COMMON_CLK_MT2712 - bool "Clock driver for MediaTek MT2712" + tristate "Clock driver for MediaTek MT2712" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM64 @@ -83,43 +83,43 @@ config COMMON_CLK_MT2712 This driver supports MediaTek MT2712 basic clocks. config COMMON_CLK_MT2712_BDPSYS - bool "Clock driver for MediaTek MT2712 bdpsys" + tristate "Clock driver for MediaTek MT2712 bdpsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 bdpsys clocks. config COMMON_CLK_MT2712_IMGSYS - bool "Clock driver for MediaTek MT2712 imgsys" + tristate "Clock driver for MediaTek MT2712 imgsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 imgsys clocks. config COMMON_CLK_MT2712_JPGDECSYS - bool "Clock driver for MediaTek MT2712 jpgdecsys" + tristate "Clock driver for MediaTek MT2712 jpgdecsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 jpgdecsys clocks. config COMMON_CLK_MT2712_MFGCFG - bool "Clock driver for MediaTek MT2712 mfgcfg" + tristate "Clock driver for MediaTek MT2712 mfgcfg" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 mfgcfg clocks. config COMMON_CLK_MT2712_MMSYS - bool "Clock driver for MediaTek MT2712 mmsys" + tristate "Clock driver for MediaTek MT2712 mmsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 mmsys clocks. config COMMON_CLK_MT2712_VDECSYS - bool "Clock driver for MediaTek MT2712 vdecsys" + tristate "Clock driver for MediaTek MT2712 vdecsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 vdecsys clocks. config COMMON_CLK_MT2712_VENCSYS - bool "Clock driver for MediaTek MT2712 vencsys" + tristate "Clock driver for MediaTek MT2712 vencsys" depends on COMMON_CLK_MT2712 help This driver supports MediaTek MT2712 vencsys clocks. @@ -133,79 +133,79 @@ config COMMON_CLK_MT6765 This driver supports MediaTek MT6765 basic clocks. config COMMON_CLK_MT6765_AUDIOSYS - bool "Clock driver for MediaTek MT6765 audiosys" + tristate "Clock driver for MediaTek MT6765 audiosys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 audiosys clocks. config COMMON_CLK_MT6765_CAMSYS - bool "Clock driver for MediaTek MT6765 camsys" + tristate "Clock driver for MediaTek MT6765 camsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 camsys clocks. config COMMON_CLK_MT6765_GCESYS - bool "Clock driver for MediaTek MT6765 gcesys" + tristate "Clock driver for MediaTek MT6765 gcesys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 gcesys clocks. config COMMON_CLK_MT6765_MMSYS - bool "Clock driver for MediaTek MT6765 mmsys" + tristate "Clock driver for MediaTek MT6765 mmsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mmsys clocks. config COMMON_CLK_MT6765_IMGSYS - bool "Clock driver for MediaTek MT6765 imgsys" + tristate "Clock driver for MediaTek MT6765 imgsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 imgsys clocks. config COMMON_CLK_MT6765_VCODECSYS - bool "Clock driver for MediaTek MT6765 vcodecsys" + tristate "Clock driver for MediaTek MT6765 vcodecsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 vcodecsys clocks. config COMMON_CLK_MT6765_MFGSYS - bool "Clock driver for MediaTek MT6765 mfgsys" + tristate "Clock driver for MediaTek MT6765 mfgsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mfgsys clocks. config COMMON_CLK_MT6765_MIPI0ASYS - bool "Clock driver for MediaTek MT6765 mipi0asys" + tristate "Clock driver for MediaTek MT6765 mipi0asys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi0asys clocks. config COMMON_CLK_MT6765_MIPI0BSYS - bool "Clock driver for MediaTek MT6765 mipi0bsys" + tristate "Clock driver for MediaTek MT6765 mipi0bsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi0bsys clocks. config COMMON_CLK_MT6765_MIPI1ASYS - bool "Clock driver for MediaTek MT6765 mipi1asys" + tristate "Clock driver for MediaTek MT6765 mipi1asys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi1asys clocks. config COMMON_CLK_MT6765_MIPI1BSYS - bool "Clock driver for MediaTek MT6765 mipi1bsys" + tristate "Clock driver for MediaTek MT6765 mipi1bsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi1bsys clocks. config COMMON_CLK_MT6765_MIPI2ASYS - bool "Clock driver for MediaTek MT6765 mipi2asys" + tristate "Clock driver for MediaTek MT6765 mipi2asys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi2asys clocks. config COMMON_CLK_MT6765_MIPI2BSYS - bool "Clock driver for MediaTek MT6765 mipi2bsys" + tristate "Clock driver for MediaTek MT6765 mipi2bsys" depends on COMMON_CLK_MT6765 help This driver supports MediaTek MT6765 mipi2bsys clocks. @@ -270,6 +270,7 @@ config COMMON_CLK_MT6795 tristate "Clock driver for MediaTek MT6795" depends on ARCH_MEDIATEK || COMPILE_TEST select COMMON_CLK_MEDIATEK + select COMMON_CLK_MEDIATEK_FHCTL default ARCH_MEDIATEK help This driver supports MediaTek MT6795 basic clocks and clocks @@ -312,31 +313,31 @@ config COMMON_CLK_MT6797 This driver supports MediaTek MT6797 basic clocks. config COMMON_CLK_MT6797_MMSYS - bool "Clock driver for MediaTek MT6797 mmsys" + tristate "Clock driver for MediaTek MT6797 mmsys" depends on COMMON_CLK_MT6797 help This driver supports MediaTek MT6797 mmsys clocks. config COMMON_CLK_MT6797_IMGSYS - bool "Clock driver for MediaTek MT6797 imgsys" + tristate "Clock driver for MediaTek MT6797 imgsys" depends on COMMON_CLK_MT6797 help This driver supports MediaTek MT6797 imgsys clocks. config COMMON_CLK_MT6797_VDECSYS - bool "Clock driver for MediaTek MT6797 vdecsys" + tristate "Clock driver for MediaTek MT6797 vdecsys" depends on COMMON_CLK_MT6797 help This driver supports MediaTek MT6797 vdecsys clocks. config COMMON_CLK_MT6797_VENCSYS - bool "Clock driver for MediaTek MT6797 vencsys" + tristate "Clock driver for MediaTek MT6797 vencsys" depends on COMMON_CLK_MT6797 help This driver supports MediaTek MT6797 vencsys clocks. config COMMON_CLK_MT7622 - bool "Clock driver for MediaTek MT7622" + tristate "Clock driver for MediaTek MT7622" depends on ARCH_MEDIATEK || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK @@ -345,21 +346,21 @@ config COMMON_CLK_MT7622 required for various periperals found on MediaTek. config COMMON_CLK_MT7622_ETHSYS - bool "Clock driver for MediaTek MT7622 ETHSYS" + tristate "Clock driver for MediaTek MT7622 ETHSYS" depends on COMMON_CLK_MT7622 help This driver add support for clocks for Ethernet and SGMII required on MediaTek MT7622 SoC. config COMMON_CLK_MT7622_HIFSYS - bool "Clock driver for MediaTek MT7622 HIFSYS" + tristate "Clock driver for MediaTek MT7622 HIFSYS" depends on COMMON_CLK_MT7622 help This driver supports MediaTek MT7622 HIFSYS clocks providing to PCI-E and USB. config COMMON_CLK_MT7622_AUDSYS - bool "Clock driver for MediaTek MT7622 AUDSYS" + tristate "Clock driver for MediaTek MT7622 AUDSYS" depends on COMMON_CLK_MT7622 help This driver supports MediaTek MT7622 AUDSYS clocks providing @@ -406,7 +407,7 @@ config COMMON_CLK_MT7981_ETHSYS required on MediaTek MT7981 SoC. config COMMON_CLK_MT7986 - bool "Clock driver for MediaTek MT7986" + tristate "Clock driver for MediaTek MT7986" depends on ARCH_MEDIATEK || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK @@ -415,7 +416,7 @@ config COMMON_CLK_MT7986 required for various peripherals found on MediaTek. config COMMON_CLK_MT7986_ETHSYS - bool "Clock driver for MediaTek MT7986 ETHSYS" + tristate "Clock driver for MediaTek MT7986 ETHSYS" depends on COMMON_CLK_MT7986 default COMMON_CLK_MT7986 help @@ -423,7 +424,7 @@ config COMMON_CLK_MT7986_ETHSYS required on MediaTek MT7986 SoC. config COMMON_CLK_MT8135 - bool "Clock driver for MediaTek MT8135" + tristate "Clock driver for MediaTek MT8135" depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM @@ -431,7 +432,7 @@ config COMMON_CLK_MT8135 This driver supports MediaTek MT8135 clocks. config COMMON_CLK_MT8167 - bool "Clock driver for MediaTek MT8167" + tristate "Clock driver for MediaTek MT8167" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK @@ -439,35 +440,35 @@ config COMMON_CLK_MT8167 This driver supports MediaTek MT8167 basic clocks. config COMMON_CLK_MT8167_AUDSYS - bool "Clock driver for MediaTek MT8167 audsys" + tristate "Clock driver for MediaTek MT8167 audsys" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help This driver supports MediaTek MT8167 audsys clocks. config COMMON_CLK_MT8167_IMGSYS - bool "Clock driver for MediaTek MT8167 imgsys" + tristate "Clock driver for MediaTek MT8167 imgsys" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help This driver supports MediaTek MT8167 imgsys clocks. config COMMON_CLK_MT8167_MFGCFG - bool "Clock driver for MediaTek MT8167 mfgcfg" + tristate "Clock driver for MediaTek MT8167 mfgcfg" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help This driver supports MediaTek MT8167 mfgcfg clocks. config COMMON_CLK_MT8167_MMSYS - bool "Clock driver for MediaTek MT8167 mmsys" + tristate "Clock driver for MediaTek MT8167 mmsys" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help This driver supports MediaTek MT8167 mmsys clocks. config COMMON_CLK_MT8167_VDECSYS - bool "Clock driver for MediaTek MT8167 vdecsys" + tristate "Clock driver for MediaTek MT8167 vdecsys" depends on COMMON_CLK_MT8167 default COMMON_CLK_MT8167 help @@ -477,6 +478,7 @@ config COMMON_CLK_MT8173 tristate "Clock driver for MediaTek MT8173" depends on ARM64 || COMPILE_TEST select COMMON_CLK_MEDIATEK + select COMMON_CLK_MEDIATEK_FHCTL default ARCH_MEDIATEK help This driver supports MediaTek MT8173 basic clocks and clocks @@ -511,7 +513,7 @@ config COMMON_CLK_MT8173_VENCSYS This driver supports MediaTek MT8173 vencsys clocks. config COMMON_CLK_MT8183 - bool "Clock driver for MediaTek MT8183" + tristate "Clock driver for MediaTek MT8183" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK && ARM64 @@ -519,84 +521,84 @@ config COMMON_CLK_MT8183 This driver supports MediaTek MT8183 basic clocks. config COMMON_CLK_MT8183_AUDIOSYS - bool "Clock driver for MediaTek MT8183 audiosys" + tristate "Clock driver for MediaTek MT8183 audiosys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 audiosys clocks. config COMMON_CLK_MT8183_CAMSYS - bool "Clock driver for MediaTek MT8183 camsys" + tristate "Clock driver for MediaTek MT8183 camsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 camsys clocks. config COMMON_CLK_MT8183_IMGSYS - bool "Clock driver for MediaTek MT8183 imgsys" + tristate "Clock driver for MediaTek MT8183 imgsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 imgsys clocks. config COMMON_CLK_MT8183_IPU_CORE0 - bool "Clock driver for MediaTek MT8183 ipu_core0" + tristate "Clock driver for MediaTek MT8183 ipu_core0" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 ipu_core0 clocks. config COMMON_CLK_MT8183_IPU_CORE1 - bool "Clock driver for MediaTek MT8183 ipu_core1" + tristate "Clock driver for MediaTek MT8183 ipu_core1" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 ipu_core1 clocks. config COMMON_CLK_MT8183_IPU_ADL - bool "Clock driver for MediaTek MT8183 ipu_adl" + tristate "Clock driver for MediaTek MT8183 ipu_adl" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 ipu_adl clocks. config COMMON_CLK_MT8183_IPU_CONN - bool "Clock driver for MediaTek MT8183 ipu_conn" + tristate "Clock driver for MediaTek MT8183 ipu_conn" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 ipu_conn clocks. config COMMON_CLK_MT8183_MFGCFG - bool "Clock driver for MediaTek MT8183 mfgcfg" + tristate "Clock driver for MediaTek MT8183 mfgcfg" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 mfgcfg clocks. config COMMON_CLK_MT8183_MMSYS - bool "Clock driver for MediaTek MT8183 mmsys" + tristate "Clock driver for MediaTek MT8183 mmsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 mmsys clocks. config COMMON_CLK_MT8183_VDECSYS - bool "Clock driver for MediaTek MT8183 vdecsys" + tristate "Clock driver for MediaTek MT8183 vdecsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 vdecsys clocks. config COMMON_CLK_MT8183_VENCSYS - bool "Clock driver for MediaTek MT8183 vencsys" + tristate "Clock driver for MediaTek MT8183 vencsys" depends on COMMON_CLK_MT8183 default COMMON_CLK_MT8183 help This driver supports MediaTek MT8183 vencsys clocks. config COMMON_CLK_MT8186 - bool "Clock driver for MediaTek MT8186" + tristate "Clock driver for MediaTek MT8186" depends on ARM64 || COMPILE_TEST select COMMON_CLK_MEDIATEK select COMMON_CLK_MEDIATEK_FHCTL @@ -604,82 +606,246 @@ config COMMON_CLK_MT8186 help This driver supports MediaTek MT8186 clocks. +config COMMON_CLK_MT8186_CAMSYS + tristate "Clock driver for MediaTek MT8186 camsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 camsys and camsys_raw clocks. + +config COMMON_CLK_MT8186_IMGSYS + tristate "Clock driver for MediaTek MT8186 imgsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 imgsys and imgsys2 clocks. + +config COMMON_CLK_MT8186_IPESYS + tristate "Clock driver for MediaTek MT8186 ipesys" + depends on COMMON_CLK_MT8186_IMGSYS + default COMMON_CLK_MT8186_IMGSYS + help + This driver supports MediaTek MT8186 ipesys clocks. + +config COMMON_CLK_MT8186_WPESYS + tristate "Clock driver for MediaTek MT8186 wpesys" + depends on COMMON_CLK_MT8186_IMGSYS + default COMMON_CLK_MT8186_IMGSYS + help + This driver supports MediaTek MT8186 Warp Engine clocks. + +config COMMON_CLK_MT8186_IMP_IIC_WRAP + tristate "Clock driver for MediaTek MT8186 imp_iic_wrap" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 imp_iic_wrap clocks. + +config COMMON_CLK_MT8186_MCUSYS + tristate "Clock driver for MediaTek MT8186 mcusys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mcusys clocks. + +config COMMON_CLK_MT8186_MDPSYS + tristate "Clock driver for MediaTek MT8186 mdpsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mdpsys clocks. + +config COMMON_CLK_MT8186_MFGCFG + tristate "Clock driver for MediaTek MT8186 mfgcfg" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mfgcfg clocks. + +config COMMON_CLK_MT8186_MMSYS + tristate "Clock driver for MediaTek MT8186 mmsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mmsys clocks. + +config COMMON_CLK_MT8186_VDECSYS + tristate "Clock driver for MediaTek MT8186 vdecsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 vdecsys and vdecsys_soc clocks. + +config COMMON_CLK_MT8186_VENCSYS + tristate "Clock driver for MediaTek MT8186 vencsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 vencsys clocks. + +config COMMON_CLK_MT8188 + tristate "Clock driver for MediaTek MT8188" + depends on ARM64 || COMPILE_TEST + select COMMON_CLK_MEDIATEK + select COMMON_CLK_MEDIATEK_FHCTL + default ARCH_MEDIATEK + help + This driver supports MediaTek MT8188 clocks. + +config COMMON_CLK_MT8188_ADSP_AUDIO26M + tristate "Clock driver for MediaTek MT8188 adsp audio26m" + depends on COMMON_CLK_MT8188 + default COMMON_CLK_MT8188 + help + This driver supports MediaTek MT8188 adsp audio26m clocks. + +config COMMON_CLK_MT8188_CAMSYS + tristate "Clock driver for MediaTek MT8188 camsys" + depends on COMMON_CLK_MT8188_VPPSYS + default COMMON_CLK_MT8188_VPPSYS + help + This driver supports MediaTek MT8188 camsys and camsys_raw clocks. + +config COMMON_CLK_MT8188_IMGSYS + tristate "Clock driver for MediaTek MT8188 imgsys" + depends on COMMON_CLK_MT8188_VPPSYS + default COMMON_CLK_MT8188_VPPSYS + help + This driver supports MediaTek MT8188 imgsys and imgsys2 clocks. + +config COMMON_CLK_MT8188_IMP_IIC_WRAP + tristate "Clock driver for MediaTek MT8188 imp_iic_wrap" + depends on COMMON_CLK_MT8188 + default COMMON_CLK_MT8188 + help + This driver supports MediaTek MT8188 I2C/I3C clocks. + +config COMMON_CLK_MT8188_IPESYS + tristate "Clock driver for MediaTek MT8188 ipesys" + depends on COMMON_CLK_MT8188_IMGSYS + default COMMON_CLK_MT8188_IMGSYS + help + This driver supports MediaTek MT8188 ipesys clocks. + +config COMMON_CLK_MT8188_MFGCFG + tristate "Clock driver for MediaTek MT8188 mfgcfg" + depends on COMMON_CLK_MT8188 + default COMMON_CLK_MT8188 + help + This driver supports MediaTek MT8188 mfgcfg clocks. + +config COMMON_CLK_MT8188_VDECSYS + tristate "Clock driver for MediaTek MT8188 vdecsys" + depends on COMMON_CLK_MT8188_VPPSYS + default COMMON_CLK_MT8188_VPPSYS + help + This driver supports MediaTek MT8188 vdecsys and vdecsys_soc clocks. + +config COMMON_CLK_MT8188_VDOSYS + tristate "Clock driver for MediaTek MT8188 vdosys" + depends on COMMON_CLK_MT8188 + default COMMON_CLK_MT8188 + help + This driver supports MediaTek MT8188 vdosys0/1 (multimedia) clocks. + +config COMMON_CLK_MT8188_VENCSYS + tristate "Clock driver for MediaTek MT8188 vencsys" + depends on COMMON_CLK_MT8188_VPPSYS + default COMMON_CLK_MT8188_VPPSYS + help + This driver supports MediaTek MT8188 vencsys clocks. + +config COMMON_CLK_MT8188_VPPSYS + tristate "Clock driver for MediaTek MT8188 vppsys" + depends on COMMON_CLK_MT8188 + default COMMON_CLK_MT8188 + help + This driver supports MediaTek MT8188 vppsys0/1 clocks. + +config COMMON_CLK_MT8188_WPESYS + tristate "Clock driver for MediaTek MT8188 wpesys" + depends on COMMON_CLK_MT8188_IMGSYS + default COMMON_CLK_MT8188_IMGSYS + help + This driver supports MediaTek MT8188 Warp Engine clocks. + config COMMON_CLK_MT8192 - bool "Clock driver for MediaTek MT8192" + tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST select COMMON_CLK_MEDIATEK + select COMMON_CLK_MEDIATEK_FHCTL default ARM64 help This driver supports MediaTek MT8192 basic clocks. config COMMON_CLK_MT8192_AUDSYS - bool "Clock driver for MediaTek MT8192 audsys" + tristate "Clock driver for MediaTek MT8192 audsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 audsys clocks. config COMMON_CLK_MT8192_CAMSYS - bool "Clock driver for MediaTek MT8192 camsys" + tristate "Clock driver for MediaTek MT8192 camsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 camsys and camsys_raw clocks. config COMMON_CLK_MT8192_IMGSYS - bool "Clock driver for MediaTek MT8192 imgsys" + tristate "Clock driver for MediaTek MT8192 imgsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 imgsys and imgsys2 clocks. config COMMON_CLK_MT8192_IMP_IIC_WRAP - bool "Clock driver for MediaTek MT8192 imp_iic_wrap" + tristate "Clock driver for MediaTek MT8192 imp_iic_wrap" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 imp_iic_wrap clocks. config COMMON_CLK_MT8192_IPESYS - bool "Clock driver for MediaTek MT8192 ipesys" + tristate "Clock driver for MediaTek MT8192 ipesys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 ipesys clocks. config COMMON_CLK_MT8192_MDPSYS - bool "Clock driver for MediaTek MT8192 mdpsys" + tristate "Clock driver for MediaTek MT8192 mdpsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 mdpsys clocks. config COMMON_CLK_MT8192_MFGCFG - bool "Clock driver for MediaTek MT8192 mfgcfg" + tristate "Clock driver for MediaTek MT8192 mfgcfg" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 mfgcfg clocks. config COMMON_CLK_MT8192_MMSYS - bool "Clock driver for MediaTek MT8192 mmsys" + tristate "Clock driver for MediaTek MT8192 mmsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 mmsys clocks. config COMMON_CLK_MT8192_MSDC - bool "Clock driver for MediaTek MT8192 msdc" + tristate "Clock driver for MediaTek MT8192 msdc" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 msdc and msdc_top clocks. config COMMON_CLK_MT8192_SCP_ADSP - bool "Clock driver for MediaTek MT8192 scp_adsp" + tristate "Clock driver for MediaTek MT8192 scp_adsp" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 scp_adsp clocks. config COMMON_CLK_MT8192_VDECSYS - bool "Clock driver for MediaTek MT8192 vdecsys" + tristate "Clock driver for MediaTek MT8192 vdecsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 vdecsys and vdecsys_soc clocks. config COMMON_CLK_MT8192_VENCSYS - bool "Clock driver for MediaTek MT8192 vencsys" + tristate "Clock driver for MediaTek MT8192 vencsys" depends on COMMON_CLK_MT8192 help This driver supports MediaTek MT8192 vencsys clocks. @@ -688,10 +854,111 @@ config COMMON_CLK_MT8195 bool "Clock driver for MediaTek MT8195" depends on ARM64 || COMPILE_TEST select COMMON_CLK_MEDIATEK + select COMMON_CLK_MEDIATEK_FHCTL default ARCH_MEDIATEK help This driver supports MediaTek MT8195 clocks. +config COMMON_CLK_MT8195_APUSYS + tristate "Clock driver for MediaTek MT8195 apusys" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 AI Processor Unit System clocks. + +config COMMON_CLK_MT8195_AUDSYS + tristate "Clock driver for MediaTek MT8195 audsys" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 audsys clocks. + +config COMMON_CLK_MT8195_IMP_IIC_WRAP + tristate "Clock driver for MediaTek MT8195 imp_iic_wrap" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 I2C/I3C clocks. + +config COMMON_CLK_MT8195_MFGCFG + tristate "Clock driver for MediaTek MT8195 mfgcfg" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 mfgcfg clocks. + +config COMMON_CLK_MT8195_MSDC + tristate "Clock driver for MediaTek MT8195 msdc" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 MMC and SD Controller's + msdc and msdc_top clocks. + +config COMMON_CLK_MT8195_SCP_ADSP + tristate "Clock driver for MediaTek MT8195 scp_adsp" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 System Companion Processor + Audio DSP clocks. + +config COMMON_CLK_MT8195_VDOSYS + tristate "Clock driver for MediaTek MT8195 vdosys" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 vdosys0/1 (multimedia) clocks. + +config COMMON_CLK_MT8195_VPPSYS + tristate "Clock driver for MediaTek MT8195 vppsys" + depends on COMMON_CLK_MT8195 + default COMMON_CLK_MT8195 + help + This driver supports MediaTek MT8195 vppsys0/1 clocks. + +config COMMON_CLK_MT8195_CAMSYS + tristate "Clock driver for MediaTek MT8195 camsys" + depends on COMMON_CLK_MT8195_VPPSYS + default COMMON_CLK_MT8195_VPPSYS + help + This driver supports MediaTek MT8195 camsys and camsys_raw clocks. + +config COMMON_CLK_MT8195_IMGSYS + tristate "Clock driver for MediaTek MT8195 imgsys" + depends on COMMON_CLK_MT8195_VPPSYS + default COMMON_CLK_MT8195_VPPSYS + help + This driver supports MediaTek MT8195 imgsys and imgsys2 clocks. + +config COMMON_CLK_MT8195_IPESYS + tristate "Clock driver for MediaTek MT8195 ipesys" + depends on COMMON_CLK_MT8195_IMGSYS + default COMMON_CLK_MT8195_IMGSYS + help + This driver supports MediaTek MT8195 ipesys clocks. + +config COMMON_CLK_MT8195_WPESYS + tristate "Clock driver for MediaTek MT8195 wpesys" + depends on COMMON_CLK_MT8195_IMGSYS + default COMMON_CLK_MT8195_IMGSYS + help + This driver supports MediaTek MT8195 Warp Engine clocks. + +config COMMON_CLK_MT8195_VDECSYS + tristate "Clock driver for MediaTek MT8195 vdecsys" + depends on COMMON_CLK_MT8195_VPPSYS + default COMMON_CLK_MT8195_VPPSYS + help + This driver supports MediaTek MT8195 vdecsys and vdecsys_soc clocks. + +config COMMON_CLK_MT8195_VENCSYS + tristate "Clock driver for MediaTek MT8195 vencsys" + depends on COMMON_CLK_MT8195_VPPSYS + default COMMON_CLK_MT8195_VPPSYS + help + This driver supports MediaTek MT8195 vencsys clocks. + config COMMON_CLK_MT8365 tristate "Clock driver for MediaTek MT8365" depends on ARCH_MEDIATEK || COMPILE_TEST @@ -743,7 +1010,7 @@ config COMMON_CLK_MT8365_VENC This driver supports MediaTek MT8365 venc clocks. config COMMON_CLK_MT8516 - bool "Clock driver for MediaTek MT8516" + tristate "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK @@ -751,7 +1018,7 @@ config COMMON_CLK_MT8516 This driver supports MediaTek MT8516 clocks. config COMMON_CLK_MT8516_AUDSYS - bool "Clock driver for MediaTek MT8516 audsys" + tristate "Clock driver for MediaTek MT8516 audsys" depends on COMMON_CLK_MT8516 help This driver supports MediaTek MT8516 audsys clocks. diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e5d018270ed0..dbeaa5b41177 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -38,7 +38,7 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o -obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o +obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712-apmixedsys.o clk-mt2712.o obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o @@ -46,7 +46,8 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o -obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o +obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622-apmixedsys.o clk-mt7622.o \ + clk-mt7622-infracfg.o obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o @@ -61,8 +62,8 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o -obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o -obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o +obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135-apmixedsys.o clk-mt8135.o +obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) += clk-mt8167-img.o obj-$(CONFIG_COMMON_CLK_MT8167_MFGCFG) += clk-mt8167-mfgcfg.o @@ -74,7 +75,7 @@ obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o -obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o +obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183-apmixedsys.o clk-mt8183.o obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o obj-$(CONFIG_COMMON_CLK_MT8183_IMGSYS) += clk-mt8183-img.o @@ -86,12 +87,33 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o -obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \ - clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \ - clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \ - clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \ - clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o -obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o +obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-apmixedsys.o clk-mt8186-topckgen.o \ + clk-mt8186-infra_ao.o +obj-$(CONFIG_COMMON_CLK_MT8186_CAMSYS) += clk-mt8186-cam.o +obj-$(CONFIG_COMMON_CLK_MT8186_IMGSYS) += clk-mt8186-img.o +obj-$(CONFIG_COMMON_CLK_MT8186_IMP_IIC_WRAP) += clk-mt8186-imp_iic_wrap.o +obj-$(CONFIG_COMMON_CLK_MT8186_IPESYS) += clk-mt8186-ipe.o +obj-$(CONFIG_COMMON_CLK_MT8186_MCUSYS) += clk-mt8186-mcu.o +obj-$(CONFIG_COMMON_CLK_MT8186_MDPSYS) += clk-mt8186-mdp.o +obj-$(CONFIG_COMMON_CLK_MT8186_MFGCFG) += clk-mt8186-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8186_MMSYS) += clk-mt8186-mm.o +obj-$(CONFIG_COMMON_CLK_MT8186_VDECSYS) += clk-mt8186-vdec.o +obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) += clk-mt8186-venc.o +obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) += clk-mt8186-wpe.o +obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \ + clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o +obj-$(CONFIG_COMMON_CLK_MT8188_ADSP_AUDIO26M) += clk-mt8188-adsp_audio26m.o +obj-$(CONFIG_COMMON_CLK_MT8188_CAMSYS) += clk-mt8188-cam.o clk-mt8188-ccu.o +obj-$(CONFIG_COMMON_CLK_MT8188_IMGSYS) += clk-mt8188-img.o +obj-$(CONFIG_COMMON_CLK_MT8188_IMP_IIC_WRAP) += clk-mt8188-imp_iic_wrap.o +obj-$(CONFIG_COMMON_CLK_MT8188_IPESYS) += clk-mt8188-ipe.o +obj-$(CONFIG_COMMON_CLK_MT8188_MFGCFG) += clk-mt8188-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8188_VDECSYS) += clk-mt8188-vdec.o +obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o clk-mt8188-vdo1.o +obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o +obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o +obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o +obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o @@ -105,19 +127,25 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \ - clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o \ - clk-mt8195-cam.o clk-mt8195-ccu.o clk-mt8195-img.o \ - clk-mt8195-ipe.o clk-mt8195-mfg.o clk-mt8195-scp_adsp.o \ - clk-mt8195-vdec.o clk-mt8195-vdo0.o clk-mt8195-vdo1.o \ - clk-mt8195-venc.o clk-mt8195-vpp0.o clk-mt8195-vpp1.o \ - clk-mt8195-wpe.o clk-mt8195-imp_iic_wrap.o \ - clk-mt8195-apusys_pll.o -obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365.o + clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o +obj-$(CONFIG_COMMON_CLK_MT8195_APUSYS) += clk-mt8195-apusys_pll.o +obj-$(CONFIG_COMMON_CLK_MT8195_CAMSYS) += clk-mt8195-cam.o clk-mt8195-ccu.o +obj-$(CONFIG_COMMON_CLK_MT8195_IMGSYS) += clk-mt8195-img.o +obj-$(CONFIG_COMMON_CLK_MT8195_IMP_IIC_WRAP) += clk-mt8195-imp_iic_wrap.o +obj-$(CONFIG_COMMON_CLK_MT8195_IPESYS) += clk-mt8195-ipe.o +obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o +obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o +obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) += clk-mt8195-vdo0.o clk-mt8195-vdo1.o +obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o +obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o +obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o +obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o obj-$(CONFIG_COMMON_CLK_MT8365_MFG) += clk-mt8365-mfg.o obj-$(CONFIG_COMMON_CLK_MT8365_MMSYS) += clk-mt8365-mm.o obj-$(CONFIG_COMMON_CLK_MT8365_VDEC) += clk-mt8365-vdec.o obj-$(CONFIG_COMMON_CLK_MT8365_VENC) += clk-mt8365-venc.o -obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o +obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516-apmixedsys.o clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-fhctl.c b/drivers/clk/mediatek/clk-fhctl.c index 4f271acef5fe..33b6ad8fdc2e 100644 --- a/drivers/clk/mediatek/clk-fhctl.c +++ b/drivers/clk/mediatek/clk-fhctl.c @@ -14,7 +14,20 @@ #define PERCENT_TO_DDSLMT(dds, percent_m10) \ ((((dds) * (percent_m10)) >> 5) / 100) -static const struct fhctl_offset fhctl_offset = { +static const struct fhctl_offset fhctl_offset_v1 = { + .offset_hp_en = 0x0, + .offset_clk_con = 0x4, + .offset_rst_con = 0x8, + .offset_slope0 = 0xc, + .offset_slope1 = 0x10, + .offset_cfg = 0x0, + .offset_updnlmt = 0x4, + .offset_dds = 0x8, + .offset_dvfs = 0xc, + .offset_mon = 0x10, +}; + +static const struct fhctl_offset fhctl_offset_v2 = { .offset_hp_en = 0x0, .offset_clk_con = 0x8, .offset_rst_con = 0xc, @@ -27,9 +40,16 @@ static const struct fhctl_offset fhctl_offset = { .offset_mon = 0x10, }; -const struct fhctl_offset *fhctl_get_offset_table(void) +const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v) { - return &fhctl_offset; + switch (v) { + case FHCTL_PLLFH_V1: + return &fhctl_offset_v1; + case FHCTL_PLLFH_V2: + return &fhctl_offset_v2; + default: + return ERR_PTR(-EINVAL); + }; } static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs, diff --git a/drivers/clk/mediatek/clk-fhctl.h b/drivers/clk/mediatek/clk-fhctl.h index 51275febf086..bfa6d281a3ee 100644 --- a/drivers/clk/mediatek/clk-fhctl.h +++ b/drivers/clk/mediatek/clk-fhctl.h @@ -7,6 +7,13 @@ #ifndef __CLK_FHCTL_H #define __CLK_FHCTL_H +#include "clk-pllfh.h" + +enum fhctl_variant { + FHCTL_PLLFH_V1, + FHCTL_PLLFH_V2, +}; + struct fhctl_offset { u32 offset_hp_en; u32 offset_clk_con; @@ -19,7 +26,7 @@ struct fhctl_offset { u32 offset_dvfs; u32 offset_mon; }; -const struct fhctl_offset *fhctl_get_offset_table(void); +const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v); const struct fh_operation *fhctl_get_ops(void); void fhctl_hw_init(struct mtk_fh *fh); diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c index 1a32d8b7db84..5cd343b98685 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -15,41 +15,17 @@ #include <dt-bindings/clock/mt2701-clk.h> -#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -#define GATE_AUDIO2(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -#define GATE_AUDIO3(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio3_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) static const struct mtk_gate_regs audio0_cg_regs = { .set_ofs = 0x0, @@ -148,6 +124,7 @@ static const struct of_device_id of_match_clk_mt2701_aud[] = { { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_aud); static int clk_mt2701_aud_probe(struct platform_device *pdev) { @@ -187,5 +164,5 @@ static struct platform_driver clk_mt2701_aud_drv = { .of_match_table = of_match_clk_mt2701_aud, }, }; - -builtin_platform_driver(clk_mt2701_aud_drv); +module_platform_driver(clk_mt2701_aud_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/clk-mt2701-bdp.c index 435ed4819d56..4c5b70d48df9 100644 --- a/drivers/clk/mediatek/clk-mt2701-bdp.c +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs bdp1_cg_regs = { .sta_ofs = 0x0110, }; -#define GATE_BDP0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &bdp0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_BDP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &bdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) -#define GATE_BDP1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &bdp1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_BDP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate bdp_clks[] = { GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0), @@ -107,6 +95,7 @@ static const struct of_device_id of_match_clk_mt2701_bdp[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_bdp); static struct platform_driver clk_mt2701_bdp_drv = { .probe = mtk_clk_simple_probe, @@ -116,5 +105,5 @@ static struct platform_driver clk_mt2701_bdp_drv = { .of_match_table = of_match_clk_mt2701_bdp, }, }; - -builtin_platform_driver(clk_mt2701_bdp_drv); +module_platform_driver(clk_mt2701_bdp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index f3cb78e7f6e9..9a1fb0c93964 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -16,14 +16,8 @@ static const struct mtk_gate_regs eth_cg_regs = { .sta_ofs = 0x0030, }; -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = ð_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate eth_clks[] = { GATE_DUMMY(CLK_DUMMY, "eth_dummy"), @@ -55,6 +49,7 @@ static const struct of_device_id of_match_clk_mt2701_eth[] = { { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_eth); static struct platform_driver clk_mt2701_eth_drv = { .probe = mtk_clk_simple_probe, @@ -64,5 +59,5 @@ static struct platform_driver clk_mt2701_eth_drv = { .of_match_table = of_match_clk_mt2701_eth, }, }; - -builtin_platform_driver(clk_mt2701_eth_drv); +module_platform_driver(clk_mt2701_eth_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 499a170ba5f9..c0006861a317 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -16,14 +16,8 @@ #include <dt-bindings/clock/mt2701-clk.h> -#define GATE_G3D(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &g3d_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_G3D(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &g3d_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate_regs g3d_cg_regs = { .sta_ofs = 0x0, @@ -54,6 +48,7 @@ static const struct of_device_id of_match_clk_mt2701_g3d[] = { { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_g3d); static struct platform_driver clk_mt2701_g3d_drv = { .probe = mtk_clk_simple_probe, @@ -63,5 +58,5 @@ static struct platform_driver clk_mt2701_g3d_drv = { .of_match_table = of_match_clk_mt2701_g3d, }, }; - -builtin_platform_driver(clk_mt2701_g3d_drv); +module_platform_driver(clk_mt2701_g3d_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index d5465d782993..ff7c0b3228e4 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -16,14 +16,8 @@ static const struct mtk_gate_regs hif_cg_regs = { .sta_ofs = 0x0030, }; -#define GATE_HIF(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &hif_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_HIF(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate hif_clks[] = { GATE_DUMMY(CLK_DUMMY, "hif_dummy"), @@ -52,6 +46,7 @@ static const struct of_device_id of_match_clk_mt2701_hif[] = { { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_hif); static struct platform_driver clk_mt2701_hif_drv = { .probe = mtk_clk_simple_probe, @@ -61,5 +56,5 @@ static struct platform_driver clk_mt2701_hif_drv = { .of_match_table = of_match_clk_mt2701_hif, }, }; - -builtin_platform_driver(clk_mt2701_hif_drv); +module_platform_driver(clk_mt2701_hif_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-img.c b/drivers/clk/mediatek/clk-mt2701-img.c index 7e53deb7f990..baa1194eb01e 100644 --- a/drivers/clk/mediatek/clk-mt2701-img.c +++ b/drivers/clk/mediatek/clk-mt2701-img.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs img_cg_regs = { .sta_ofs = 0x0000, }; -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &img_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate img_clks[] = { GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0), @@ -49,6 +43,7 @@ static const struct of_device_id of_match_clk_mt2701_img[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_img); static struct platform_driver clk_mt2701_img_drv = { .probe = mtk_clk_simple_probe, @@ -58,5 +53,5 @@ static struct platform_driver clk_mt2701_img_drv = { .of_match_table = of_match_clk_mt2701_img, }, }; - -builtin_platform_driver(clk_mt2701_img_drv); +module_platform_driver(clk_mt2701_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/clk-mt2701-mm.c index 23d5ddcc1d37..c62c56fd2b7e 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs disp1_cg_regs = { .sta_ofs = 0x0110, }; -#define GATE_DISP0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &disp0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_DISP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &disp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_DISP1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &disp1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_DISP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mm_clks[] = { GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0), @@ -79,32 +67,24 @@ static const struct mtk_gate mm_clks[] = { GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14), }; -static int clk_mt2701_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; - return r; -} +static const struct platform_device_id clk_mt2701_mm_id_table[] = { + { .name = "clk-mt2701-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt2701_mm_id_table); static struct platform_driver clk_mt2701_mm_drv = { - .probe = clk_mt2701_mm_probe, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt2701-mm", }, + .id_table = clk_mt2701_mm_id_table, }; - -builtin_platform_driver(clk_mt2701_mm_drv); +module_platform_driver(clk_mt2701_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701-vdec.c b/drivers/clk/mediatek/clk-mt2701-vdec.c index d3089da0ab62..b7f97bc51c16 100644 --- a/drivers/clk/mediatek/clk-mt2701-vdec.c +++ b/drivers/clk/mediatek/clk-mt2701-vdec.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs vdec1_cg_regs = { .sta_ofs = 0x0008, }; -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &vdec0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &vdec1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate vdec_clks[] = { GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0), @@ -60,6 +48,7 @@ static const struct of_device_id of_match_clk_mt2701_vdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701_vdec); static struct platform_driver clk_mt2701_vdec_drv = { .probe = mtk_clk_simple_probe, @@ -69,5 +58,5 @@ static struct platform_driver clk_mt2701_vdec_drv = { .of_match_table = of_match_clk_mt2701_vdec, }, }; - -builtin_platform_driver(clk_mt2701_vdec_drv); +module_platform_driver(clk_mt2701_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 06ca81359d35..4a154da8a543 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -636,14 +636,8 @@ static const struct mtk_gate_regs top_aud_cg_regs = { .sta_ofs = 0x012C, }; -#define GATE_TOP_AUD(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top_aud_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top_aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) static const struct mtk_gate top_clks[] = { GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div", @@ -687,7 +681,7 @@ static int mtk_topckgen_init(struct platform_device *pdev) ARRAY_SIZE(top_muxes), base, &mt2701_clk_lock, clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), + mtk_clk_register_dividers(&pdev->dev, top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt2701_clk_lock, clk_data); mtk_clk_register_gates(&pdev->dev, node, top_clks, @@ -702,14 +696,8 @@ static const struct mtk_gate_regs infra_cg_regs = { .sta_ofs = 0x0048, }; -#define GATE_ICG(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &infra_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_ICG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate infra_clks[] = { GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0), @@ -823,23 +811,11 @@ static const struct mtk_gate_regs peri1_cg_regs = { .sta_ofs = 0x001c, }; -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate peri_clks[] = { GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31), @@ -1023,6 +999,7 @@ static const struct of_device_id of_match_clk_mt2701[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2701); static int clk_mt2701_probe(struct platform_device *pdev) { @@ -1056,3 +1033,4 @@ static int __init clk_mt2701_init(void) } arch_initcall(clk_mt2701_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-apmixedsys.c b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c new file mode 100644 index 000000000000..9d2fcda285fb --- /dev/null +++ b/drivers/clk/mediatek/clk-mt2712-apmixedsys.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017 MediaTek Inc. + * Weiyi Lu <weiyi.lu@mediatek.com> + * Copyright (c) 2023 Collabora Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "clk-pll.h" +#include "clk-mtk.h" + +#include <dt-bindings/clock/mt2712-clk.h> + +#define MT2712_PLL_FMAX (3000UL * MHZ) + +#define CON0_MT2712_RST_BAR BIT(24) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _div_table) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = CON0_MT2712_RST_BAR, \ + .fmax = MT2712_PLL_FMAX, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, \ + .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_table = _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \ + _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ + _pcw_shift, NULL) + +static const struct mtk_pll_div_table armca35pll_div_table[] = { + { .div = 0, .freq = MT2712_PLL_FMAX }, + { .div = 1, .freq = 1202500000 }, + { .div = 2, .freq = 500500000 }, + { .div = 3, .freq = 315250000 }, + { .div = 4, .freq = 157625000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_div_table armca72pll_div_table[] = { + { .div = 0, .freq = MT2712_PLL_FMAX }, + { .div = 1, .freq = 994500000 }, + { .div = 2, .freq = 520000000 }, + { .div = 3, .freq = 315250000 }, + { .div = 4, .freq = 157625000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_div_table mmpll_div_table[] = { + { .div = 0, .freq = MT2712_PLL_FMAX }, + { .div = 1, .freq = 1001000000 }, + { .div = 2, .freq = 601250000 }, + { .div = 3, .freq = 250250000 }, + { .div = 4, .freq = 125125000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100, + HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100, + HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0), + PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100, + 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0), + PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100, + 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0), + PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100, + 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100, + 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100, + 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0), + PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100, + 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100, + 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0), + PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100, + 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100, + 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100, + 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table), + PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100, + HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_table), + PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100, + 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table), + PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100, + 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), +}; + +static int clk_mt2712_apmixed_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (r) + goto free_clk_data; + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) { + dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r); + goto unregister_plls; + } + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; +} + +static int clk_mt2712_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static const struct of_device_id of_match_clk_mt2712_apmixed[] = { + { .compatible = "mediatek,mt2712-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_apmixed); + +static struct platform_driver clk_mt2712_apmixed_drv = { + .probe = clk_mt2712_apmixed_probe, + .remove = clk_mt2712_apmixed_remove, + .driver = { + .name = "clk-mt2712-apmixed", + .of_match_table = of_match_clk_mt2712_apmixed, + }, +}; +module_platform_driver(clk_mt2712_apmixed_drv) +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/clk-mt2712-bdp.c index 684d03e9f6de..f78e01819316 100644 --- a/drivers/clk/mediatek/clk-mt2712-bdp.c +++ b/drivers/clk/mediatek/clk-mt2712-bdp.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs bdp_cg_regs = { .sta_ofs = 0x100, }; -#define GATE_BDP(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &bdp_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_BDP(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &bdp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) static const struct mtk_gate bdp_clks[] = { GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0), @@ -71,6 +65,7 @@ static const struct of_device_id of_match_clk_mt2712_bdp[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_bdp); static struct platform_driver clk_mt2712_bdp_drv = { .probe = mtk_clk_simple_probe, @@ -80,5 +75,5 @@ static struct platform_driver clk_mt2712_bdp_drv = { .of_match_table = of_match_clk_mt2712_bdp, }, }; - -builtin_platform_driver(clk_mt2712_bdp_drv); +module_platform_driver(clk_mt2712_bdp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/clk-mt2712-img.c index 335049cdc856..fbe7084886a0 100644 --- a/drivers/clk/mediatek/clk-mt2712-img.c +++ b/drivers/clk/mediatek/clk-mt2712-img.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs img_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &img_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) static const struct mtk_gate img_clks[] = { GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0), @@ -49,6 +43,7 @@ static const struct of_device_id of_match_clk_mt2712_img[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_img); static struct platform_driver clk_mt2712_img_drv = { .probe = mtk_clk_simple_probe, @@ -58,5 +53,5 @@ static struct platform_driver clk_mt2712_img_drv = { .of_match_table = of_match_clk_mt2712_img, }, }; - -builtin_platform_driver(clk_mt2712_img_drv); +module_platform_driver(clk_mt2712_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediatek/clk-mt2712-jpgdec.c index 07ba7c5e80af..7e8c2ebcdee0 100644 --- a/drivers/clk/mediatek/clk-mt2712-jpgdec.c +++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs jpgdec_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_JPGDEC(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &jpgdec_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_JPGDEC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &jpgdec_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate jpgdec_clks[] = { GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0), @@ -45,6 +39,7 @@ static const struct of_device_id of_match_clk_mt2712_jpgdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_jpgdec); static struct platform_driver clk_mt2712_jpgdec_drv = { .probe = mtk_clk_simple_probe, @@ -54,5 +49,5 @@ static struct platform_driver clk_mt2712_jpgdec_drv = { .of_match_table = of_match_clk_mt2712_jpgdec, }, }; - -builtin_platform_driver(clk_mt2712_jpgdec_drv); +module_platform_driver(clk_mt2712_jpgdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/clk-mt2712-mfg.c index 42f8cf3ecf4c..932ea449d299 100644 --- a/drivers/clk/mediatek/clk-mt2712-mfg.c +++ b/drivers/clk/mediatek/clk-mt2712-mfg.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs mfg_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_MFG(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mfg_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mfg_clks[] = { GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0), @@ -44,6 +38,7 @@ static const struct of_device_id of_match_clk_mt2712_mfg[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_mfg); static struct platform_driver clk_mt2712_mfg_drv = { .probe = mtk_clk_simple_probe, @@ -53,5 +48,5 @@ static struct platform_driver clk_mt2712_mfg_drv = { .of_match_table = of_match_clk_mt2712_mfg, }, }; - -builtin_platform_driver(clk_mt2712_mfg_drv); +module_platform_driver(clk_mt2712_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/clk-mt2712-mm.c index 25b8af640c12..204a3eae08dc 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -30,32 +30,14 @@ static const struct mtk_gate_regs mm2_cg_regs = { .sta_ofs = 0x220, }; -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_MM2(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mm_clks[] = { /* MM0 */ @@ -126,32 +108,24 @@ static const struct mtk_gate mm_clks[] = { GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6), }; -static int clk_mt2712_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; - return r; -} +static const struct platform_device_id clk_mt2712_mm_id_table[] = { + { .name = "clk-mt2712-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt2712_mm_id_table); static struct platform_driver clk_mt2712_mm_drv = { - .probe = clk_mt2712_mm_probe, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt2712-mm", }, + .id_table = clk_mt2712_mm_id_table, }; - -builtin_platform_driver(clk_mt2712_mm_drv); +module_platform_driver(clk_mt2712_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/clk-mt2712-vdec.c index 6296ed5c5b55..2fc1f82ebf5d 100644 --- a/drivers/clk/mediatek/clk-mt2712-vdec.c +++ b/drivers/clk/mediatek/clk-mt2712-vdec.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs vdec1_cg_regs = { .sta_ofs = 0x8, }; -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &vdec0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &vdec1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate vdec_clks[] = { /* VDEC0 */ @@ -63,6 +51,7 @@ static const struct of_device_id of_match_clk_mt2712_vdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_vdec); static struct platform_driver clk_mt2712_vdec_drv = { .probe = mtk_clk_simple_probe, @@ -72,5 +61,5 @@ static struct platform_driver clk_mt2712_vdec_drv = { .of_match_table = of_match_clk_mt2712_vdec, }, }; - -builtin_platform_driver(clk_mt2712_vdec_drv); +module_platform_driver(clk_mt2712_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/clk-mt2712-venc.c index b9bfc35de629..6d053a00cf95 100644 --- a/drivers/clk/mediatek/clk-mt2712-venc.c +++ b/drivers/clk/mediatek/clk-mt2712-venc.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs venc_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &venc_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate venc_clks[] = { GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0), @@ -46,6 +40,7 @@ static const struct of_device_id of_match_clk_mt2712_venc[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712_venc); static struct platform_driver clk_mt2712_venc_drv = { .probe = mtk_clk_simple_probe, @@ -55,5 +50,5 @@ static struct platform_driver clk_mt2712_venc_drv = { .of_match_table = of_match_clk_mt2712_venc, }, }; - -builtin_platform_driver(clk_mt2712_venc_drv); +module_platform_driver(clk_mt2712_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 94f8fc2a4f7b..74c529f6163d 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -14,7 +14,6 @@ #include <linux/slab.h> #include "clk-gate.h" -#include "clk-pll.h" #include "clk-mtk.h" #include <dt-bindings/clock/mt2712-clk.h> @@ -36,188 +35,96 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000), }; -static const struct mtk_fixed_factor top_early_divs[] = { - FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, - 1), - FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, - 2), -}; - static const struct mtk_fixed_factor top_divs[] = { - FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, - 1), - FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, - 2), - FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, - 3), - FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, - 1), - FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, - 1), - FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, - 2), - FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, - 2), - FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, - 4), - FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, - 8), - FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, - 16), - FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, - 3), - FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, - 2), - FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, - 4), - FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, - 5), - FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, - 2), - FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, - 4), - FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, - 7), - FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, - 2), - FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, - 4), - FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, - 1), - FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, - 7), - FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, - 26), - FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, - 52), - FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, - 104), - FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, - 208), - FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, - 2), - FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, - 2), - FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, - 4), - FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, - 8), - FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, - 3), - FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, - 2), - FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, - 4), - FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, - 8), - FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, - 5), - FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, - 2), - FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, - 4), - FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, - 8), - FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, - 1), - FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, - 1), - FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, - 1), - FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, - 1), - FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, - 1), - FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, - 1), - FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, - 1), - FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, - 2), - FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, - 4), - FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, - 8), - FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, - 16), - FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, - 1), - FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, - 2), - FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, - 4), - FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, - 8), - FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, - 16), - FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, - 1), - FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, - 2), - FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, - 4), - FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, - 8), - FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, - 1), - FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, - 2), - FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, - 4), - FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, - 8), - FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, - 1), - FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, - 1), - FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, - 1), - FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, - 2), - FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, - 1), - FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, - 2), - FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, - 1), - FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, - 2), - FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, - 1), - FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, - 2), - FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, - 1), - FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, - 2), - FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, - 4), - FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, - 8), - FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, - 1), - FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, - 2), - FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, - 4), - FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, - 1), - FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, - 2), - FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, - 4), - FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, - 1), - FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, - 2), - FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, - 4), - FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, - 4), - FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, - 3), - FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, - 3), + FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, 1), + FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, 2), + FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, 1), + FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, 2), + FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, 3), + FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, 1), + FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2), + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, 3), + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, 5), + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, 7), + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), + FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1), + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 7), + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, 26), + FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, 52), + FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, 104), + FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, 208), + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2), + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 3), + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 5), + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), + FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, 1), + FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, 1), + FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, 1), + FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, 1), + FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, 1), + FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, 1), + FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), + FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), + FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), + FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, 16), + FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), + FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), + FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), + FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, 16), + FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1), + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, 2), + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, 4), + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, 8), + FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, 1), + FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, 2), + FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, 4), + FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, 8), + FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, 1), + FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, 1), + FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, 1), + FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, 2), + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2), + FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), + FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, 2), + FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 1), + FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, 2), + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4), + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8), + FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, 1), + FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, 2), + FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, 4), + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2), + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4), + FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), + FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, 2), + FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, 4), + FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, 4), + FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 3), + FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, 3), }; static const char * const axi_parents[] = { @@ -737,169 +644,118 @@ static const char * const audull_vtx_parents[] = { static struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3, - 7, CLK_IS_CRITICAL), + 7, CLK_IS_CRITICAL), MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1, - 15, CLK_IS_CRITICAL), - MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", - mm_parents, 0x040, 24, 3, 31), + 15, CLK_IS_CRITICAL), + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31), /* CLK_CFG_1 */ - MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", - pwm_parents, 0x050, 0, 2, 7), - MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", - vdec_parents, 0x050, 8, 4, 15), - MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", - venc_parents, 0x050, 16, 4, 23), - MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", - mfg_parents, 0x050, 24, 4, 31), + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7), + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15), + MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23), + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 24, 4, 31), /* CLK_CFG_2 */ - MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", - camtg_parents, 0x060, 0, 4, 7), - MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", - uart_parents, 0x060, 8, 1, 15), - MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", - spi_parents, 0x060, 16, 3, 23), - MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", - usb20_parents, 0x060, 24, 2, 31), + MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x060, 0, 4, 7), + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15), + MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 16, 3, 23), + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x060, 24, 2, 31), /* CLK_CFG_3 */ - MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", - usb30_parents, 0x070, 0, 2, 7), - MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", - msdc50_0_h_parents, 0x070, 8, 3, 15), - MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", - msdc50_0_parents, 0x070, 16, 4, 23), - MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", - msdc30_1_parents, 0x070, 24, 3, 31), + MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x070, 0, 2, 7), + MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, + 0x070, 8, 3, 15), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, + 0x070, 16, 4, 23), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, + 0x070, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", - msdc30_1_parents, 0x080, 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", - msdc30_3_parents, 0x080, 8, 4, 15), - MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", - audio_parents, 0x080, 16, 2, 23), - MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", - aud_intbus_parents, 0x080, 24, 3, 31), + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_parents, + 0x080, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, + 0x080, 8, 4, 15), + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, + 0x080, 16, 2, 23), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, + 0x080, 24, 3, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", - pmicspi_parents, 0x090, 0, 3, 7), - MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", - dpilvds1_parents, 0x090, 8, 3, 15), - MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", - atb_parents, 0x090, 16, 2, 23), - MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", - nr_parents, 0x090, 24, 3, 31), + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x090, 0, 3, 7), + MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", dpilvds1_parents, + 0x090, 8, 3, 15), + MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x090, 16, 2, 23), + MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_parents, 0x090, 24, 3, 31), /* CLK_CFG_6 */ - MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", - nfi2x_parents, 0x0a0, 0, 4, 7), - MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", - irda_parents, 0x0a0, 8, 2, 15), - MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", - cci400_parents, 0x0a0, 16, 3, 23), - MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", - aud_1_parents, 0x0a0, 24, 2, 31), + MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x0a0, 0, 4, 7), + MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0a0, 8, 2, 15), + MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x0a0, 16, 3, 23), + MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0a0, 24, 2, 31), /* CLK_CFG_7 */ - MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", - aud_2_parents, 0x0b0, 0, 2, 7), - MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", - mem_mfg_parents, 0x0b0, 8, 2, 15), - MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", - axi_mfg_parents, 0x0b0, 16, 2, 23), - MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", - scam_parents, 0x0b0, 24, 2, 31), + MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x0b0, 0, 2, 7), + MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", mem_mfg_parents, + 0x0b0, 8, 2, 15), + MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", axi_mfg_parents, + 0x0b0, 16, 2, 23), + MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x0b0, 24, 2, 31), /* CLK_CFG_8 */ - MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", - nfiecc_parents, 0x0c0, 0, 3, 7), - MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", - pe2_mac_p0_parents, 0x0c0, 8, 3, 15), - MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", - pe2_mac_p0_parents, 0x0c0, 16, 3, 23), - MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", - dpilvds_parents, 0x0c0, 24, 3, 31), + MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 0x0c0, 0, 3, 7), + MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", pe2_mac_p0_parents, + 0x0c0, 8, 3, 15), + MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", pe2_mac_p0_parents, + 0x0c0, 16, 3, 23), + MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0c0, 24, 3, 31), /* CLK_CFG_9 */ - MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", - msdc50_0_h_parents, 0x0d0, 0, 3, 7), - MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", - hdcp_parents, 0x0d0, 8, 2, 15), - MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", - hdcp_24m_parents, 0x0d0, 16, 2, 23), - MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2, - 31, CLK_IS_CRITICAL), + MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", msdc50_0_h_parents, + 0x0d0, 0, 3, 7), + MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x0d0, 8, 2, 15), + MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, + 0x0d0, 16, 2, 23), + MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, + 0x0d0, 24, 2, 31, CLK_IS_CRITICAL), /* CLK_CFG_10 */ - MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", - spinor_parents, 0x500, 0, 4, 7), - MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", - apll_parents, 0x500, 8, 4, 15), - MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", - apll_parents, 0x500, 16, 4, 23), - MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", - a1sys_hp_parents, 0x500, 24, 3, 31), + MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents, 0x500, 0, 4, 7), + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x500, 8, 4, 15), + MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", apll_parents, 0x500, 16, 4, 23), + MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, + 0x500, 24, 3, 31), /* CLK_CFG_11 */ - MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", - a2sys_hp_parents, 0x510, 0, 3, 7), - MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", - asm_l_parents, 0x510, 8, 2, 15), - MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", - asm_l_parents, 0x510, 16, 2, 23), - MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", - asm_l_parents, 0x510, 24, 2, 31), + MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a2sys_hp_parents, 0x510, 0, 3, 7), + MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, 0x510, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, 0x510, 16, 2, 23), + MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, 0x510, 24, 2, 31), /* CLK_CFG_12 */ - MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", - i2so1_parents, 0x520, 0, 2, 7), - MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", - i2so1_parents, 0x520, 8, 2, 15), - MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", - i2so1_parents, 0x520, 16, 2, 23), - MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", - i2so1_parents, 0x520, 24, 2, 31), + MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", i2so1_parents, 0x520, 0, 2, 7), + MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", i2so1_parents, 0x520, 8, 2, 15), + MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", i2so1_parents, 0x520, 16, 2, 23), + MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", i2so1_parents, 0x520, 24, 2, 31), /* CLK_CFG_13 */ - MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", - i2so1_parents, 0x530, 0, 2, 7), - MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", - i2so1_parents, 0x530, 8, 2, 15), - MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", - i2so1_parents, 0x530, 16, 2, 23), - MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", - i2so1_parents, 0x530, 24, 2, 31), + MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", i2so1_parents, 0x530, 0, 2, 7), + MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", i2so1_parents, 0x530, 8, 2, 15), + MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", i2so1_parents, 0x530, 16, 2, 23), + MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", i2so1_parents, 0x530, 24, 2, 31), /* CLK_CFG_14 */ - MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", - ether_125m_parents, 0x540, 0, 2, 7), - MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", - ether_50m_parents, 0x540, 8, 2, 15), - MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", - jpgdec_parents, 0x540, 16, 4, 23), - MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", - spislv_parents, 0x540, 24, 3, 31), + MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", ether_125m_parents, + 0x540, 0, 2, 7), + MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", ether_50m_parents, + 0x540, 8, 2, 15), + MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", jpgdec_parents, 0x540, 16, 4, 23), + MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", spislv_parents, 0x540, 24, 3, 31), /* CLK_CFG_15 */ - MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", - ether_parents, 0x550, 0, 2, 7), - MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", - camtg_parents, 0x550, 8, 4, 15), - MUX_GATE(CLK_TOP_DI_SEL, "di_sel", - di_parents, 0x550, 16, 3, 23), - MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", - tvd_parents, 0x550, 24, 2, 31), + MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", ether_parents, 0x550, 0, 2, 7), + MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", camtg_parents, 0x550, 8, 4, 15), + MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 0x550, 16, 3, 23), + MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", tvd_parents, 0x550, 24, 2, 31), /* CLK_CFG_16 */ - MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", - i2c_parents, 0x560, 0, 3, 7), - MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", - pwm_parents, 0x560, 8, 2, 15), - MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", - msdc0p_aes_parents, 0x560, 16, 2, 23), - MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", - cmsys_parents, 0x560, 24, 3, 31), + MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x560, 0, 3, 7), + MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", pwm_parents, 0x560, 8, 2, 15), + MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", msdc0p_aes_parents, + 0x560, 16, 2, 23), + MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 0x560, 24, 3, 31), /* CLK_CFG_17 */ - MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", - gcpu_parents, 0x570, 0, 3, 7), + MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x570, 0, 3, 7), /* CLK_AUDDIV_4 */ - MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", - aud_apll1_parents, 0x134, 0, 1), - MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", - aud_apll2_parents, 0x134, 1, 1), - MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", - audull_vtx_parents, 0x134, 31, 1), - MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel", - apll1_ref_parents, 0x134, 4, 3), - MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel", - apll1_ref_parents, 0x134, 7, 3), + MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", aud_apll1_parents, 0x134, 0, 1), + MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", aud_apll2_parents, 0x134, 1, 1), + MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", audull_vtx_parents, + 0x134, 31, 1), + MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel", apll1_ref_parents, 0x134, 4, 3), + MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel", apll1_ref_parents, 0x134, 7, 3), }; static const char * const mcu_mp0_parents[] = { @@ -926,13 +782,13 @@ static const char * const mcu_bus_parents[] = { static struct mtk_composite mcu_muxes[] = { /* mp0_pll_divider_cfg */ MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, - 9, 2, -1, CLK_IS_CRITICAL), + 9, 2, -1, CLK_IS_CRITICAL), /* mp2_pll_divider_cfg */ MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, - 9, 2, -1, CLK_IS_CRITICAL), + 9, 2, -1, CLK_IS_CRITICAL), /* bus_pll_divider_cfg */ MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, - 9, 2, -1, CLK_IS_CRITICAL), + 9, 2, -1, CLK_IS_CRITICAL), }; static const struct mtk_clk_divider top_adj_divs[] = { @@ -958,23 +814,11 @@ static const struct mtk_gate_regs top1_cg_regs = { .sta_ofs = 0x424, }; -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } - -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) + +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate top_clks[] = { /* TOP0 */ @@ -998,14 +842,8 @@ static const struct mtk_gate_regs infra_cg_regs = { .sta_ofs = 0x48, }; -#define GATE_INFRA(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &infra_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate infra_clks[] = { GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), @@ -1035,227 +873,65 @@ static const struct mtk_gate_regs peri2_cg_regs = { .sta_ofs = 0x42c, }; -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_PERI2(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_PERI2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate peri_clks[] = { /* PERI0 */ - GATE_PERI0(CLK_PERI_NFI, "per_nfi", - "axi_sel", 0), - GATE_PERI0(CLK_PERI_THERM, "per_therm", - "axi_sel", 1), - GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", - "pwm_sel", 2), - GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", - "pwm_sel", 3), - GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", - "pwm_sel", 4), - GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", - "pwm_sel", 5), - GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", - "pwm_sel", 6), - GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", - "pwm_sel", 7), - GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", - "pwm_sel", 8), - GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", - "pwm_sel", 9), - GATE_PERI0(CLK_PERI_PWM, "per_pwm", - "pwm_sel", 10), - GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", - "axi_sel", 13), - GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", - "msdc50_0_sel", 14), - GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", - "msdc30_1_sel", 15), - GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", - "msdc30_2_sel", 16), - GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", - "msdc30_3_sel", 17), - GATE_PERI0(CLK_PERI_UART0, "per_uart0", - "uart_sel", 20), - GATE_PERI0(CLK_PERI_UART1, "per_uart1", - "uart_sel", 21), - GATE_PERI0(CLK_PERI_UART2, "per_uart2", - "uart_sel", 22), - GATE_PERI0(CLK_PERI_UART3, "per_uart3", - "uart_sel", 23), - GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", - "axi_sel", 24), - GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", - "axi_sel", 25), - GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", - "axi_sel", 26), - GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", - "axi_sel", 27), - GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", - "axi_sel", 28), - GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", - "ltepll_fs26m", 29), - GATE_PERI0(CLK_PERI_SPI0, "per_spi0", - "spi_sel", 30), + GATE_PERI0(CLK_PERI_NFI, "per_nfi", "axi_sel", 0), + GATE_PERI0(CLK_PERI_THERM, "per_therm", "axi_sel", 1), + GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", "pwm_sel", 2), + GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", "pwm_sel", 3), + GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4), + GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", "pwm_sel", 5), + GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6), + GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7), + GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", "pwm_sel", 8), + GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", "pwm_sel", 9), + GATE_PERI0(CLK_PERI_PWM, "per_pwm", "pwm_sel", 10), + GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", "axi_sel", 13), + GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", "msdc50_0_sel", 14), + GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", "msdc30_1_sel", 15), + GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", "msdc30_2_sel", 16), + GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", "msdc30_3_sel", 17), + GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20), + GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21), + GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22), + GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23), + GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", "axi_sel", 24), + GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", "axi_sel", 25), + GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", "axi_sel", 26), + GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", "axi_sel", 27), + GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", "axi_sel", 28), + GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", "ltepll_fs26m", 29), + GATE_PERI0(CLK_PERI_SPI0, "per_spi0", "spi_sel", 30), /* PERI1 */ - GATE_PERI1(CLK_PERI_SPI, "per_spi", - "spinor_sel", 1), - GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", - "axi_sel", 3), - GATE_PERI1(CLK_PERI_SPI2, "per_spi2", - "spi_sel", 5), - GATE_PERI1(CLK_PERI_SPI3, "per_spi3", - "spi_sel", 6), - GATE_PERI1(CLK_PERI_SPI5, "per_spi5", - "spi_sel", 8), - GATE_PERI1(CLK_PERI_UART4, "per_uart4", - "uart_sel", 9), - GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", - "uart_sel", 11), - GATE_PERI1(CLK_PERI_GMAC, "per_gmac", - "uart_sel", 12), - GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", - "uart_sel", 14), - GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", - "uart_sel", 15), - GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", - "uart_sel", 16), + GATE_PERI1(CLK_PERI_SPI, "per_spi", "spinor_sel", 1), + GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", "axi_sel", 3), + GATE_PERI1(CLK_PERI_SPI2, "per_spi2", "spi_sel", 5), + GATE_PERI1(CLK_PERI_SPI3, "per_spi3", "spi_sel", 6), + GATE_PERI1(CLK_PERI_SPI5, "per_spi5", "spi_sel", 8), + GATE_PERI1(CLK_PERI_UART4, "per_uart4", "uart_sel", 9), + GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", "uart_sel", 11), + GATE_PERI1(CLK_PERI_GMAC, "per_gmac", "uart_sel", 12), + GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", "uart_sel", 14), + GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", "uart_sel", 15), + GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", "uart_sel", 16), /* PERI2 */ - GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", - "msdc50_0_sel", 0), - GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", - "msdc30_1_sel", 1), - GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", - "msdc30_2_sel", 2), - GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", - "msdc30_3_sel", 3), - GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", - "msdc50_0_h_sel", 4), - GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", - "msdc50_3_h_sel", 5), - GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q", - "axi_sel", 6), - GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", - "mem_sel", 7), -}; - -#define MT2712_PLL_FMAX (3000UL * MHZ) - -#define CON0_MT2712_RST_BAR BIT(24) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, \ - _div_table) { \ - .id = _id, \ - .name = _name, \ - .reg = _reg, \ - .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, \ - .flags = _flags, \ - .rst_bar_mask = CON0_MT2712_RST_BAR, \ - .fmax = MT2712_PLL_FMAX, \ - .pcwbits = _pcwbits, \ - .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, \ - .tuner_en_reg = _tuner_en_reg, \ - .tuner_en_bit = _tuner_en_bit, \ - .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, \ - .div_table = _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \ - _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ - _pcw_shift, NULL) - -static const struct mtk_pll_div_table armca35pll_div_table[] = { - { .div = 0, .freq = MT2712_PLL_FMAX }, - { .div = 1, .freq = 1202500000 }, - { .div = 2, .freq = 500500000 }, - { .div = 3, .freq = 315250000 }, - { .div = 4, .freq = 157625000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table armca72pll_div_table[] = { - { .div = 0, .freq = MT2712_PLL_FMAX }, - { .div = 1, .freq = 994500000 }, - { .div = 2, .freq = 520000000 }, - { .div = 3, .freq = 315250000 }, - { .div = 4, .freq = 157625000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table mmpll_div_table[] = { - { .div = 0, .freq = MT2712_PLL_FMAX }, - { .div = 1, .freq = 1001000000 }, - { .div = 2, .freq = 601250000 }, - { .div = 3, .freq = 250250000 }, - { .div = 4, .freq = 125125000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100, - HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100, - HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0), - PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100, - 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0), - PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100, - 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0), - PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100, - 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100, - 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100, - 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0), - PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100, - 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100, - 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0), - PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100, - 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100, - 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100, - 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, - mmpll_div_table), - PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100, - HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, - armca35pll_div_table), - PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100, - 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, - armca72pll_div_table), - PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100, - 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), + GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", "msdc50_0_sel", 0), + GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", "msdc30_1_sel", 1), + GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", "msdc30_2_sel", 2), + GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", "msdc30_3_sel", 3), + GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", "msdc50_0_h_sel", 4), + GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", "msdc50_3_h_sel", 5), + GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q", "axi_sel", 6), + GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", "mem_sel", 7), }; static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; @@ -1276,155 +952,25 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = { }, }; -static int clk_mt2712_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - return r; -} - -static struct clk_hw_onecell_data *top_clk_data; - -static void clk_mt2712_top_init_early(struct device_node *node) -{ - int r, i; - - if (!top_clk_data) { - top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - for (i = 0; i < CLK_TOP_NR_CLK; i++) - top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); - } - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} - -CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen", - clk_mt2712_top_init_early); - -static int clk_mt2712_top_probe(struct platform_device *pdev) -{ - int r, i; - struct device_node *node = pdev->dev.of_node; - void __iomem *base; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - pr_err("%s(): ioremap failed\n", __func__); - return PTR_ERR(base); - } - - if (!top_clk_data) { - top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - } else { - for (i = 0; i < CLK_TOP_NR_CLK; i++) { - if (top_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER)) - top_clk_data->hws[i] = ERR_PTR(-ENOENT); - } - } - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); - mtk_clk_register_composites(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), top_clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - return r; -} - -static int clk_mt2712_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - void __iomem *base; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - pr_err("%s(): ioremap failed\n", __func__); - return PTR_ERR(base); - } - - clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); - - r = mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - &mt2712_clk_lock, clk_data); - if (r) - dev_err(&pdev->dev, "Could not register composites: %d\n", r); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - return r; -} +static const struct mtk_clk_desc topck_desc = { + .clks = top_clks, + .num_clks = ARRAY_SIZE(top_clks), + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .composite_clks = top_muxes, + .num_composite_clks = ARRAY_SIZE(top_muxes), + .divider_clks = top_adj_divs, + .num_divider_clks = ARRAY_SIZE(top_adj_divs), + .clk_lock = &mt2712_clk_lock, +}; -static const struct of_device_id of_match_clk_mt2712[] = { - { - .compatible = "mediatek,mt2712-apmixedsys", - .data = clk_mt2712_apmixed_probe, - }, { - .compatible = "mediatek,mt2712-topckgen", - .data = clk_mt2712_top_probe, - }, { - .compatible = "mediatek,mt2712-mcucfg", - .data = clk_mt2712_mcu_probe, - }, { - /* sentinel */ - } -}; - -static int clk_mt2712_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *); - int r; - - clk_probe = of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r = clk_probe(pdev); - if (r != 0) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} +static const struct mtk_clk_desc mcu_desc = { + .composite_clks = mcu_muxes, + .num_composite_clks = ARRAY_SIZE(mcu_muxes), + .clk_lock = &mt2712_clk_lock, +}; static const struct mtk_clk_desc infra_desc = { .clks = infra_clks, @@ -1438,36 +984,22 @@ static const struct mtk_clk_desc peri_desc = { .rst_desc = &clk_rst_desc[1], }; -static const struct of_device_id of_match_clk_mt2712_simple[] = { +static const struct of_device_id of_match_clk_mt2712[] = { { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt2712-mcucfg", .data = &mcu_desc }, { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, + { .compatible = "mediatek,mt2712-topckgen", .data = &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt2712); -static struct platform_driver clk_mt2712_simple_drv = { +static struct platform_driver clk_mt2712_drv = { .probe = mtk_clk_simple_probe, .remove = mtk_clk_simple_remove, .driver = { - .name = "clk-mt2712-simple", - .of_match_table = of_match_clk_mt2712_simple, - }, -}; - -static struct platform_driver clk_mt2712_drv = { - .probe = clk_mt2712_probe, - .driver = { .name = "clk-mt2712", .of_match_table = of_match_clk_mt2712, }, }; - -static int __init clk_mt2712_init(void) -{ - int ret = platform_driver_register(&clk_mt2712_drv); - - if (ret) - return ret; - return platform_driver_register(&clk_mt2712_simple_drv); -} - -arch_initcall(clk_mt2712_init); +module_platform_driver(clk_mt2712_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c index 0aa6c0d352ca..9e98d6997329 100644 --- a/drivers/clk/mediatek/clk-mt6765-audio.c +++ b/drivers/clk/mediatek/clk-mt6765-audio.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs audio1_cg_regs = { .sta_ofs = 0x4, }; -#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) static const struct mtk_gate audio_clks[] = { /* AUDIO0 */ @@ -77,6 +65,7 @@ static const struct of_device_id of_match_clk_mt6765_audio[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_audio); static struct platform_driver clk_mt6765_audio_drv = { .probe = mtk_clk_simple_probe, @@ -86,5 +75,5 @@ static struct platform_driver clk_mt6765_audio_drv = { .of_match_table = of_match_clk_mt6765_audio, }, }; - -builtin_platform_driver(clk_mt6765_audio_drv); +module_platform_driver(clk_mt6765_audio_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-cam.c b/drivers/clk/mediatek/clk-mt6765-cam.c index 25f2bef38126..6f6b29d8b29a 100644 --- a/drivers/clk/mediatek/clk-mt6765-cam.c +++ b/drivers/clk/mediatek/clk-mt6765-cam.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs cam_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_CAM(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &cam_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_CAM(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate cam_clks[] = { GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "mm_ck", 0), @@ -52,6 +46,7 @@ static const struct of_device_id of_match_clk_mt6765_cam[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_cam); static struct platform_driver clk_mt6765_cam_drv = { .probe = mtk_clk_simple_probe, @@ -61,5 +56,5 @@ static struct platform_driver clk_mt6765_cam_drv = { .of_match_table = of_match_clk_mt6765_cam, }, }; - -builtin_platform_driver(clk_mt6765_cam_drv); +module_platform_driver(clk_mt6765_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-img.c b/drivers/clk/mediatek/clk-mt6765-img.c index a62303ef4f41..984201077a20 100644 --- a/drivers/clk/mediatek/clk-mt6765-img.c +++ b/drivers/clk/mediatek/clk-mt6765-img.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs img_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &img_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate img_clks[] = { GATE_IMG(CLK_IMG_LARB2, "img_larb2", "mm_ck", 0), @@ -48,6 +42,7 @@ static const struct of_device_id of_match_clk_mt6765_img[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_img); static struct platform_driver clk_mt6765_img_drv = { .probe = mtk_clk_simple_probe, @@ -57,5 +52,5 @@ static struct platform_driver clk_mt6765_img_drv = { .of_match_table = of_match_clk_mt6765_img, }, }; - -builtin_platform_driver(clk_mt6765_img_drv); +module_platform_driver(clk_mt6765_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-mipi0a.c b/drivers/clk/mediatek/clk-mt6765-mipi0a.c index 25c829fc3866..a47937f4efe5 100644 --- a/drivers/clk/mediatek/clk-mt6765-mipi0a.c +++ b/drivers/clk/mediatek/clk-mt6765-mipi0a.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs mipi0a_cg_regs = { .sta_ofs = 0x80, }; -#define GATE_MIPI0A(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mipi0a_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_MIPI0A(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mipi0a_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate mipi0a_clks[] = { GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A, @@ -45,6 +39,7 @@ static const struct of_device_id of_match_clk_mt6765_mipi0a[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mipi0a); static struct platform_driver clk_mt6765_mipi0a_drv = { .probe = mtk_clk_simple_probe, @@ -54,5 +49,5 @@ static struct platform_driver clk_mt6765_mipi0a_drv = { .of_match_table = of_match_clk_mt6765_mipi0a, }, }; - -builtin_platform_driver(clk_mt6765_mipi0a_drv); +module_platform_driver(clk_mt6765_mipi0a_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-mm.c b/drivers/clk/mediatek/clk-mt6765-mm.c index bda774668a36..2b8fc052558e 100644 --- a/drivers/clk/mediatek/clk-mt6765-mm.c +++ b/drivers/clk/mediatek/clk-mt6765-mm.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs mm_cg_regs = { .sta_ofs = 0x100, }; -#define GATE_MM(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mm_clks[] = { /* MM */ @@ -74,6 +68,7 @@ static const struct of_device_id of_match_clk_mt6765_mm[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_mm); static struct platform_driver clk_mt6765_mm_drv = { .probe = mtk_clk_simple_probe, @@ -83,5 +78,5 @@ static struct platform_driver clk_mt6765_mm_drv = { .of_match_table = of_match_clk_mt6765_mm, }, }; - -builtin_platform_driver(clk_mt6765_mm_drv); +module_platform_driver(clk_mt6765_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediatek/clk-mt6765-vcodec.c index 2bc1fbde87da..36df9615b1be 100644 --- a/drivers/clk/mediatek/clk-mt6765-vcodec.c +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs venc_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &venc_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate venc_clks[] = { GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "mm_ck", 0), @@ -47,6 +41,7 @@ static const struct of_device_id of_match_clk_mt6765_vcodec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765_vcodec); static struct platform_driver clk_mt6765_vcodec_drv = { .probe = mtk_clk_simple_probe, @@ -56,5 +51,5 @@ static struct platform_driver clk_mt6765_vcodec_drv = { .of_match_table = of_match_clk_mt6765_vcodec, }, }; - -builtin_platform_driver(clk_mt6765_vcodec_drv); +module_platform_driver(clk_mt6765_vcodec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c index 6f5c92a7f620..fa7948ef1e68 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -483,32 +483,14 @@ static const struct mtk_gate_regs top2_cg_regs = { .sta_ofs = 0x320, }; -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) -#define GATE_TOP2(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) static const struct mtk_gate top_clks[] = { /* TOP0 */ @@ -559,41 +541,17 @@ static const struct mtk_gate_regs ifr5_cg_regs = { .sta_ofs = 0xc8, }; -#define GATE_IFR2(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ifr2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_IFR3(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ifr3_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_IFR4(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ifr4_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR4(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_IFR5(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ifr5_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFR5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ifr5_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate ifr_clks[] = { /* INFRA_TOPAXI */ @@ -674,14 +632,8 @@ static const struct mtk_gate_regs apmixed_cg_regs = { .sta_ofs = 0x14, }; -#define GATE_APMIXED(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &apmixed_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate apmixed_clks[] = { /* AUDIO0 */ @@ -888,6 +840,7 @@ static const struct of_device_id of_match_clk_mt6765[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6765); static int clk_mt6765_probe(struct platform_device *pdev) { @@ -921,3 +874,4 @@ static int __init clk_mt6765_init(void) } arch_initcall(clk_mt6765_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/clk-mt6779-aud.c index 6e473ae1fd90..6e3280d3a2e6 100644 --- a/drivers/clk/mediatek/clk-mt6779-aud.c +++ b/drivers/clk/mediatek/clk-mt6779-aud.c @@ -102,6 +102,7 @@ static const struct of_device_id of_match_clk_mt6779_aud[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_aud); static struct platform_driver clk_mt6779_aud_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-cam.c b/drivers/clk/mediatek/clk-mt6779-cam.c index 7be3db90fa4a..b4c4c7248672 100644 --- a/drivers/clk/mediatek/clk-mt6779-cam.c +++ b/drivers/clk/mediatek/clk-mt6779-cam.c @@ -51,6 +51,7 @@ static const struct of_device_id of_match_clk_mt6779_cam[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_cam); static struct platform_driver clk_mt6779_cam_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-img.c b/drivers/clk/mediatek/clk-mt6779-img.c index 9bc51fc82dbd..b760a8af3462 100644 --- a/drivers/clk/mediatek/clk-mt6779-img.c +++ b/drivers/clk/mediatek/clk-mt6779-img.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt6779_img[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_img); static struct platform_driver clk_mt6779_img_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-ipe.c b/drivers/clk/mediatek/clk-mt6779-ipe.c index 92e9d1ade422..9285a792c59b 100644 --- a/drivers/clk/mediatek/clk-mt6779-ipe.c +++ b/drivers/clk/mediatek/clk-mt6779-ipe.c @@ -45,6 +45,7 @@ static const struct of_device_id of_match_clk_mt6779_ipe[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_ipe); static struct platform_driver clk_mt6779_ipe_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-mfg.c b/drivers/clk/mediatek/clk-mt6779-mfg.c index efc793a1969a..d20f32d4f827 100644 --- a/drivers/clk/mediatek/clk-mt6779-mfg.c +++ b/drivers/clk/mediatek/clk-mt6779-mfg.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt6779_mfg[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_mfg); static struct platform_driver clk_mt6779_mfg_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/clk-mt6779-mm.c index 2cccf62d3b36..c2f700ae6c2c 100644 --- a/drivers/clk/mediatek/clk-mt6779-mm.c +++ b/drivers/clk/mediatek/clk-mt6779-mm.c @@ -85,25 +85,24 @@ static const struct mtk_gate mm_clks[] = { GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16), }; -static int clk_mt6779_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct platform_device_id clk_mt6779_mm_id_table[] = { + { .name = "clk-mt6779-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt6779_mm_id_table); static struct platform_driver clk_mt6779_mm_drv = { - .probe = clk_mt6779_mm_probe, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt6779-mm", }, + .id_table = clk_mt6779_mm_id_table, }; module_platform_driver(clk_mt6779_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt6779-vdec.c b/drivers/clk/mediatek/clk-mt6779-vdec.c index 3209a6518d5b..e062ed5aa45f 100644 --- a/drivers/clk/mediatek/clk-mt6779-vdec.c +++ b/drivers/clk/mediatek/clk-mt6779-vdec.c @@ -52,6 +52,7 @@ static const struct of_device_id of_match_clk_mt6779_vdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_vdec); static struct platform_driver clk_mt6779_vdec_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779-venc.c b/drivers/clk/mediatek/clk-mt6779-venc.c index c25035c0f334..0ae8ac28f838 100644 --- a/drivers/clk/mediatek/clk-mt6779-venc.c +++ b/drivers/clk/mediatek/clk-mt6779-venc.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt6779_venc[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779_venc); static struct platform_driver clk_mt6779_venc_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 827025d127d9..1f5ea1508f61 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1299,6 +1299,7 @@ static const struct of_device_id of_match_clk_mt6779_infra[] = { { .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6779); static struct platform_driver clk_mt6779_infra_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c index 59761c72d3bc..8b30109f253c 100644 --- a/drivers/clk/mediatek/clk-mt6795-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6795-apmixedsys.c @@ -7,8 +7,10 @@ #include <dt-bindings/clock/mediatek,mt6795-clk.h> #include <linux/module.h> #include <linux/platform_device.h> +#include "clk-fhctl.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" #define REG_REF2USB 0x8 #define REG_AP_PLL_CON7 0x1c @@ -58,6 +60,56 @@ static const struct mtk_pll_data plls[] = { PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2bc, 0x2b8, 0), }; +enum fh_pll_id { + FH_CA53PLL_LL, + FH_CA53PLL_BL, + FH_MAINPLL, + FH_MPLL, + FH_MSDCPLL, + FH_MMPLL, + FH_VENCPLL, + FH_TVDPLL, + FH_VCODECPLL, + FH_NR_FH, +}; + +#define _FH(_pllid, _fhid, _slope, _offset) { \ + .data = { \ + .pll_id = _pllid, \ + .fh_id = _fhid, \ + .fh_ver = FHCTL_PLLFH_V1, \ + .fhx_offset = _offset, \ + .dds_mask = GENMASK(21, 0), \ + .slope0_value = _slope, \ + .slope1_value = _slope, \ + .sfstrx_en = BIT(2), \ + .frddsx_en = BIT(1), \ + .fhctlx_en = BIT(0), \ + .tgl_org = BIT(31), \ + .dvfs_tri = BIT(31), \ + .pcwchg = BIT(31), \ + .dt_val = 0x0, \ + .df_val = 0x9, \ + .updnlmt_shft = 16, \ + .msk_frddsx_dys = GENMASK(23, 20), \ + .msk_frddsx_dts = GENMASK(19, 16), \ + }, \ + } + +#define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset) +#define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset) + +static struct mtk_pllfh_data pllfhs[] = { + FH(CLK_APMIXED_ARMCA53PLL, FH_CA53PLL_BL, 0x38), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60), + FH_M(CLK_APMIXED_MPLL, FH_MPLL, 0x74), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c), + FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4), + FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8), +}; + static void clk_mt6795_apmixed_setup_md1(void __iomem *base) { void __iomem *reg = base + REG_AP_PLL_CON7; @@ -79,12 +131,14 @@ static const struct of_device_id of_match_clk_mt6795_apmixed[] = { { .compatible = "mediatek,mt6795-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_apmixed); static int clk_mt6795_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; + const u8 *fhctl_node = "mediatek,mt6795-fhctl"; void __iomem *base; struct clk_hw *hw; int ret; @@ -97,7 +151,9 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + ret = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (ret) goto free_clk_data; @@ -124,7 +180,8 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev) unregister_ref2usb: mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return ret; @@ -137,7 +194,8 @@ static int clk_mt6795_apmixed_remove(struct platform_device *pdev) of_clk_del_provider(node); mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); return 0; diff --git a/drivers/clk/mediatek/clk-mt6795-infracfg.c b/drivers/clk/mediatek/clk-mt6795-infracfg.c index 23d9fc057e61..086ea1438564 100644 --- a/drivers/clk/mediatek/clk-mt6795-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c @@ -81,6 +81,7 @@ static const struct of_device_id of_match_clk_mt6795_infracfg[] = { { .compatible = "mediatek,mt6795-infracfg" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_infracfg); static int clk_mt6795_infracfg_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt6795-mfg.c b/drivers/clk/mediatek/clk-mt6795-mfg.c index ee7aab24eb24..1d658bb19e82 100644 --- a/drivers/clk/mediatek/clk-mt6795-mfg.c +++ b/drivers/clk/mediatek/clk-mt6795-mfg.c @@ -35,6 +35,7 @@ static const struct of_device_id of_match_clk_mt6795_mfg[] = { { .compatible = "mediatek,mt6795-mfgcfg", .data = &mfg_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_mfg); static struct platform_driver clk_mt6795_mfg_drv = { .driver = { diff --git a/drivers/clk/mediatek/clk-mt6795-mm.c b/drivers/clk/mediatek/clk-mt6795-mm.c index eebb6143ada2..8acc9cad2875 100644 --- a/drivers/clk/mediatek/clk-mt6795-mm.c +++ b/drivers/clk/mediatek/clk-mt6795-mm.c @@ -76,56 +76,24 @@ static const struct mtk_gate mm_gates[] = { GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9), }; -static int clk_mt6795_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int ret; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret = mtk_clk_register_gates(&pdev->dev, node, mm_gates, - ARRAY_SIZE(mm_gates), clk_data); - if (ret) - goto free_clk_data; - - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return 0; - -unregister_gates: - mtk_clk_unregister_gates(mm_gates, ARRAY_SIZE(mm_gates), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return ret; -} - -static int clk_mt6795_mm_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(mm_gates, ARRAY_SIZE(mm_gates), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc mm_desc = { + .clks = mm_gates, + .num_clks = ARRAY_SIZE(mm_gates), +}; - return 0; -} +static const struct platform_device_id clk_mt6795_mm_id_table[] = { + { .name = "clk-mt6795-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt6795_mm_id_table); static struct platform_driver clk_mt6795_mm_drv = { .driver = { .name = "clk-mt6795-mm", }, - .probe = clk_mt6795_mm_probe, - .remove = clk_mt6795_mm_remove, + .id_table = clk_mt6795_mm_id_table, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, }; module_platform_driver(clk_mt6795_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt6795-pericfg.c b/drivers/clk/mediatek/clk-mt6795-pericfg.c index 08aaa9b09c36..62cc19eee2c7 100644 --- a/drivers/clk/mediatek/clk-mt6795-pericfg.c +++ b/drivers/clk/mediatek/clk-mt6795-pericfg.c @@ -89,6 +89,7 @@ static const struct of_device_id of_match_clk_mt6795_pericfg[] = { { .compatible = "mediatek,mt6795-pericfg" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_pericfg); static int clk_mt6795_pericfg_probe(struct platform_device *pdev) { diff --git a/drivers/clk/mediatek/clk-mt6795-topckgen.c b/drivers/clk/mediatek/clk-mt6795-topckgen.c index e80fa588e309..9c6d63a80b19 100644 --- a/drivers/clk/mediatek/clk-mt6795-topckgen.c +++ b/drivers/clk/mediatek/clk-mt6795-topckgen.c @@ -539,6 +539,7 @@ static const struct of_device_id of_match_clk_mt6795_topckgen[] = { { .compatible = "mediatek,mt6795-topckgen", .data = &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_topckgen); static struct platform_driver clk_mt6795_topckgen_drv = { .driver = { diff --git a/drivers/clk/mediatek/clk-mt6795-vdecsys.c b/drivers/clk/mediatek/clk-mt6795-vdecsys.c index d85d04e0d016..f2968f859dca 100644 --- a/drivers/clk/mediatek/clk-mt6795-vdecsys.c +++ b/drivers/clk/mediatek/clk-mt6795-vdecsys.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt6795_vdecsys[] = { { .compatible = "mediatek,mt6795-vdecsys", .data = &vdec_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vdecsys); static struct platform_driver clk_mt6795_vdecsys_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt6795-vencsys.c b/drivers/clk/mediatek/clk-mt6795-vencsys.c index de40a982ca96..2f8d48da1a85 100644 --- a/drivers/clk/mediatek/clk-mt6795-vencsys.c +++ b/drivers/clk/mediatek/clk-mt6795-vencsys.c @@ -35,6 +35,7 @@ static const struct of_device_id of_match_clk_mt6795_vencsys[] = { { .compatible = "mediatek,mt6795-vencsys", .data = &venc_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vencsys); static struct platform_driver clk_mt6795_vencsys_drv = { .driver = { diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/clk-mt6797-img.c index 7c6a53fbb8be..00fc0a03e646 100644 --- a/drivers/clk/mediatek/clk-mt6797-img.c +++ b/drivers/clk/mediatek/clk-mt6797-img.c @@ -16,14 +16,8 @@ static const struct mtk_gate_regs img_cg_regs = { .sta_ofs = 0x0000, }; -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &img_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate img_clks[] = { GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11), @@ -45,6 +39,7 @@ static const struct of_device_id of_match_clk_mt6797_img[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_img); static struct platform_driver clk_mt6797_img_drv = { .probe = mtk_clk_simple_probe, @@ -54,5 +49,5 @@ static struct platform_driver clk_mt6797_img_drv = { .of_match_table = of_match_clk_mt6797_img, }, }; - -builtin_platform_driver(clk_mt6797_img_drv); +module_platform_driver(clk_mt6797_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/clk-mt6797-mm.c index deb16a6b16a5..caacfa40a5bc 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -23,23 +23,11 @@ static const struct mtk_gate_regs mm1_cg_regs = { .sta_ofs = 0x0110, }; -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ -} +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ -} +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mm_clks[] = { GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), @@ -92,32 +80,24 @@ static const struct mtk_gate mm_clks[] = { "clk26m", 3), }; -static int clk_mt6797_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; - return r; -} +static const struct platform_device_id clk_mt6797_mm_id_table[] = { + { .name = "clk-mt6797-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt6797_mm_id_table); static struct platform_driver clk_mt6797_mm_drv = { - .probe = clk_mt6797_mm_probe, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt6797-mm", }, + .id_table = clk_mt6797_mm_id_table, }; - -builtin_platform_driver(clk_mt6797_mm_drv); +module_platform_driver(clk_mt6797_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/clk-mt6797-vdec.c index 6120fccc859f..447fe6fa8e15 100644 --- a/drivers/clk/mediatek/clk-mt6797-vdec.c +++ b/drivers/clk/mediatek/clk-mt6797-vdec.c @@ -24,23 +24,11 @@ static const struct mtk_gate_regs vdec1_cg_regs = { .sta_ofs = 0x0008, }; -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &vdec0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ -} +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &vdec1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ -} +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate vdec_clks[] = { GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8), @@ -62,6 +50,7 @@ static const struct of_device_id of_match_clk_mt6797_vdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_vdec); static struct platform_driver clk_mt6797_vdec_drv = { .probe = mtk_clk_simple_probe, @@ -71,5 +60,5 @@ static struct platform_driver clk_mt6797_vdec_drv = { .of_match_table = of_match_clk_mt6797_vdec, }, }; - -builtin_platform_driver(clk_mt6797_vdec_drv); +module_platform_driver(clk_mt6797_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/clk-mt6797-venc.c index 834d3834d2bb..95b89ff8fd19 100644 --- a/drivers/clk/mediatek/clk-mt6797-venc.c +++ b/drivers/clk/mediatek/clk-mt6797-venc.c @@ -18,14 +18,8 @@ static const struct mtk_gate_regs venc_cg_regs = { .sta_ofs = 0x0000, }; -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &venc_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate venc_clks[] = { GATE_VENC(CLK_VENC_0, "venc_0", "mm_sel", 0), @@ -47,6 +41,7 @@ static const struct of_device_id of_match_clk_mt6797_venc[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6797_venc); static struct platform_driver clk_mt6797_venc_drv = { .probe = mtk_clk_simple_probe, @@ -56,5 +51,5 @@ static struct platform_driver clk_mt6797_venc_drv = { .of_match_table = of_match_clk_mt6797_venc, }, }; - -builtin_platform_driver(clk_mt6797_venc_drv); +module_platform_driver(clk_mt6797_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c index 105a512857b3..4c87c0348e5f 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -421,40 +421,22 @@ static const struct mtk_gate_regs infra2_cg_regs = { .sta_ofs = 0x00b0, }; -#define GATE_ICG0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &infra0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ -} +#define GATE_ICG0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_ICG1(_id, _name, _parent, _shift) \ - GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0) +#define GATE_ICG1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &infra1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - .flags = _flags, \ -} +#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) -#define GATE_ICG2(_id, _name, _parent, _shift) \ - GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0) +#define GATE_ICG2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &infra2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - .flags = _flags, \ -} +#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) /* * Clock gates dramc and dramc_b are needed by the DRAM controller. @@ -688,6 +670,7 @@ static const struct of_device_id of_match_clk_mt6797[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6797); static int clk_mt6797_probe(struct platform_device *pdev) { @@ -721,3 +704,4 @@ static int __init clk_mt6797_init(void) } arch_initcall(clk_mt6797_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-apmixedsys.c b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c new file mode 100644 index 000000000000..a36808d074d6 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7622-apmixedsys.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017 MediaTek Inc. + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#include <dt-bindings/clock/mt7622-clk.h> +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" + +#define MT7622_PLL_FMAX (2500UL * MHZ) +#define CON0_MT7622_RST_BAR BIT(27) + +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift, _div_table, _parent_name) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = CON0_MT7622_RST_BAR, \ + .fmax = MT7622_PLL_FMAX, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_table = _div_table, \ + .parent_name = _parent_name, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift) \ + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + NULL, "clkxtal") + +static const struct mtk_gate_regs apmixed_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x8, + .sta_ofs = 0x8, +}; + +#define GATE_APMIXED_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr_inv, CLK_IS_CRITICAL) + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0, + PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0, + HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0, + HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), + PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0, + 0, 21, 0x0300, 1, 0, 0x0304, 0), + PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0, + 0, 21, 0x0314, 1, 0, 0x0318, 0), + PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0, + 0, 31, 0x0324, 1, 0, 0x0328, 0), + PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0, + 0, 31, 0x0334, 1, 0, 0x0338, 0), + PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0, + 0, 21, 0x0344, 1, 0, 0x0348, 0), + PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0, + 0, 21, 0x0358, 1, 0, 0x035C, 0), +}; + +static const struct mtk_gate apmixed_clks[] = { + GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), +}; + +static int clk_mt7622_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + if (ret) + goto unregister_plls; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_gates; + + return 0; + +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static int clk_mt7622_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static const struct of_device_id of_match_clk_mt7622_apmixed[] = { + { .compatible = "mediatek,mt7622-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_apmixed); + +static struct platform_driver clk_mt7622_apmixed_drv = { + .probe = clk_mt7622_apmixed_probe, + .remove = clk_mt7622_apmixed_remove, + .driver = { + .name = "clk-mt7622-apmixed", + .of_match_table = of_match_clk_mt7622_apmixed, + }, +}; +module_platform_driver(clk_mt7622_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT7622 apmixedsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c index b8aabfeb1cba..dd1799dd8435 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -16,41 +16,17 @@ #include <dt-bindings/clock/mt7622-clk.h> -#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -#define GATE_AUDIO2(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -#define GATE_AUDIO3(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &audio3_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUDIO3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &audio3_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) static const struct mtk_gate_regs audio0_cg_regs = { .set_ofs = 0x0, @@ -169,6 +145,7 @@ static const struct of_device_id of_match_clk_mt7622_aud[] = { { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_aud); static struct platform_driver clk_mt7622_aud_drv = { .probe = clk_mt7622_aud_probe, @@ -178,5 +155,5 @@ static struct platform_driver clk_mt7622_aud_drv = { .of_match_table = of_match_clk_mt7622_aud, }, }; - -builtin_platform_driver(clk_mt7622_aud_drv); +module_platform_driver(clk_mt7622_aud_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index aee583fa77d0..f96b36737029 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -16,14 +16,8 @@ #include <dt-bindings/clock/mt7622-clk.h> -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = ð_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate_regs eth_cg_regs = { .set_ofs = 0x30, @@ -45,14 +39,8 @@ static const struct mtk_gate_regs sgmii_cg_regs = { .sta_ofs = 0xE4, }; -#define GATE_SGMII(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &sgmii_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate sgmii_clks[] = { GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", @@ -89,6 +77,7 @@ static const struct of_device_id of_match_clk_mt7622_eth[] = { { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_eth); static struct platform_driver clk_mt7622_eth_drv = { .probe = mtk_clk_simple_probe, @@ -98,5 +87,5 @@ static struct platform_driver clk_mt7622_eth_drv = { .of_match_table = of_match_clk_mt7622_eth, }, }; - -builtin_platform_driver(clk_mt7622_eth_drv); +module_platform_driver(clk_mt7622_eth_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index ab5cad0c2b1c..f440943f0d46 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -16,23 +16,11 @@ #include <dt-bindings/clock/mt7622-clk.h> -#define GATE_PCIE(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &pcie_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_PCIE(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) -#define GATE_SSUSB(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ssusb_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SSUSB(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate_regs pcie_cg_regs = { .set_ofs = 0x30, @@ -101,6 +89,7 @@ static const struct of_device_id of_match_clk_mt7622_hif[] = { { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_hif); static struct platform_driver clk_mt7622_hif_drv = { .probe = mtk_clk_simple_probe, @@ -110,5 +99,5 @@ static struct platform_driver clk_mt7622_hif_drv = { .of_match_table = of_match_clk_mt7622_hif, }, }; - -builtin_platform_driver(clk_mt7622_hif_drv); +module_platform_driver(clk_mt7622_hif_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622-infracfg.c b/drivers/clk/mediatek/clk-mt7622-infracfg.c new file mode 100644 index 000000000000..9dc05526f287 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7622-infracfg.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017 MediaTek Inc. + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#include <dt-bindings/clock/mt7622-clk.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include "clk-cpumux.h" +#include "clk-gate.h" +#include "clk-mtk.h" +#include "reset.h" + +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate_regs infra_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +static const char * const infra_mux1_parents[] = { + "clkxtal", + "armpll", + "main_core_en", + "armpll" +}; + +static const struct mtk_composite cpu_muxes[] = { + MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2), +}; + +static const struct mtk_gate infra_clks[] = { + GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0), + GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2), + GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5), + GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16), + GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18), + GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22), +}; + +static u16 infrasys_rst_ofs[] = { 0x30 }; + +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), +}; + +static const struct of_device_id of_match_clk_mt7622_infracfg[] = { + { .compatible = "mediatek,mt7622-infracfg" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_infracfg); + +static int clk_mt7622_infracfg_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + void __iomem *base; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); + if (ret) + goto free_clk_data; + + ret = mtk_clk_register_gates(&pdev->dev, node, infra_clks, + ARRAY_SIZE(infra_clks), clk_data); + if (ret) + goto free_clk_data; + + ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, + ARRAY_SIZE(cpu_muxes), clk_data); + if (ret) + goto unregister_gates; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_cpumuxes; + + return 0; + +unregister_cpumuxes: + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); +unregister_gates: + mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return ret; +} + +static int clk_mt7622_infracfg_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); + mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static struct platform_driver clk_mt7622_infracfg_drv = { + .driver = { + .name = "clk-mt7622-infracfg", + .of_match_table = of_match_clk_mt7622_infracfg, + }, + .probe = clk_mt7622_infracfg_probe, + .remove = clk_mt7622_infracfg_remove, +}; +module_platform_driver(clk_mt7622_infracfg_drv); + +MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 5a82c2270bfb..274895264427 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -14,104 +14,27 @@ #include "clk-cpumux.h" #include "clk-gate.h" #include "clk-mtk.h" -#include "clk-pll.h" #include <dt-bindings/clock/mt7622-clk.h> #include <linux/clk.h> /* for consumer */ -#define MT7622_PLL_FMAX (2500UL * MHZ) -#define CON0_MT7622_RST_BAR BIT(27) - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift, _div_table, _parent_name) { \ - .id = _id, \ - .name = _name, \ - .reg = _reg, \ - .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, \ - .flags = _flags, \ - .rst_bar_mask = CON0_MT7622_RST_BAR, \ - .fmax = MT7622_PLL_FMAX, \ - .pcwbits = _pcwbits, \ - .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, \ - .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, \ - .div_table = _div_table, \ - .parent_name = _parent_name, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - NULL, "clkxtal") - -#define GATE_APMIXED(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &apmixed_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -#define GATE_INFRA(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &infra_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } - -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } - -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -static DEFINE_SPINLOCK(mt7622_clk_lock); +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -static const char * const infra_mux1_parents[] = { - "clkxtal", - "armpll", - "main_core_en", - "armpll" -}; +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_PERI0_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) + +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static DEFINE_SPINLOCK(mt7622_clk_lock); static const char * const axi_parents[] = { "clkxtal", @@ -292,18 +215,6 @@ static const char * const peribus_ck_parents[] = { "syspll1_d4" }; -static const struct mtk_gate_regs apmixed_cg_regs = { - .set_ofs = 0x8, - .clr_ofs = 0x8, - .sta_ofs = 0x8, -}; - -static const struct mtk_gate_regs infra_cg_regs = { - .set_ofs = 0x40, - .clr_ofs = 0x44, - .sta_ofs = 0x48, -}; - static const struct mtk_gate_regs top0_cg_regs = { .set_ofs = 0x120, .clr_ofs = 0x120, @@ -328,40 +239,6 @@ static const struct mtk_gate_regs peri1_cg_regs = { .sta_ofs = 0x1C, }; -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0, - PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0, - HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), - PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0, - HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), - PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0, - 0, 21, 0x0300, 1, 0, 0x0304, 0), - PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0, - 0, 21, 0x0314, 1, 0, 0x0318, 0), - PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0, - 0, 31, 0x0324, 1, 0, 0x0328, 0), - PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0, - 0, 31, 0x0334, 1, 0, 0x0338, 0), - PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0, - 0, 21, 0x0344, 1, 0, 0x0348, 0), - PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0, - 0, 21, 0x0358, 1, 0, 0x035C, 0), -}; - -static const struct mtk_gate apmixed_clks[] = { - GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), -}; - -static const struct mtk_gate infra_clks[] = { - GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0), - GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2), - GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5), - GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16), - GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18), - GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22), -}; - static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", 31250000), @@ -485,7 +362,7 @@ static const struct mtk_gate peri_clks[] = { GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12), GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13), GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14), - GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), + GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18), GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19), GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20), @@ -506,19 +383,14 @@ static const struct mtk_gate peri_clks[] = { GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2), }; -static struct mtk_composite infra_muxes[] = { - MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, - 0x000, 2, 2), -}; - static struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, - 0x040, 0, 3, 7), - MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, - 0x040, 8, 1, 15), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, - 0x040, 16, 1, 23), + MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, + 0x040, 0, 3, 7, CLK_IS_CRITICAL), + MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, + 0x040, 8, 1, 15, CLK_IS_CRITICAL), + MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, + 0x040, 16, 1, 23, CLK_IS_CRITICAL), MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x040, 24, 3, 31), @@ -610,182 +482,53 @@ static struct mtk_composite peri_muxes[] = { MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), }; -static u16 infrasys_rst_ofs[] = { 0x30, }; static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; -static const struct mtk_clk_rst_desc clk_rst_desc[] = { - /* infrasys */ - { - .version = MTK_RST_SIMPLE, - .rst_bank_ofs = infrasys_rst_ofs, - .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), - }, - /* pericfg */ - { - .version = MTK_RST_SIMPLE, - .rst_bank_ofs = pericfg_rst_ofs, - .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), - }, +static const struct mtk_clk_rst_desc clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = pericfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), }; -static int mtk_topckgen_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - struct device_node *node = pdev->dev.of_node; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), - clk_data); - - mtk_clk_register_composites(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt7622_clk_lock, clk_data); - - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt7622_clk_lock, clk_data); - - mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), clk_data); - - clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static int mtk_infrasys_init(struct platform_device *pdev) -{ - struct device_node *node = pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - - mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, - ARRAY_SIZE(infra_muxes), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - clk_data); - if (r) - return r; - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); - - return 0; -} - -static int mtk_apmixedsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), - clk_data); - - mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); - clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static int mtk_pericfg_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - struct device_node *node = pdev->dev.of_node; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - - mtk_clk_register_composites(&pdev->dev, peri_muxes, - ARRAY_SIZE(peri_muxes), base, - &mt7622_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - return r; - - clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); +static const struct mtk_clk_desc topck_desc = { + .clks = top_clks, + .num_clks = ARRAY_SIZE(top_clks), + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .composite_clks = top_muxes, + .num_composite_clks = ARRAY_SIZE(top_muxes), + .divider_clks = top_adj_divs, + .num_divider_clks = ARRAY_SIZE(top_adj_divs), + .clk_lock = &mt7622_clk_lock, +}; - return 0; -} +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), + .composite_clks = peri_muxes, + .num_composite_clks = ARRAY_SIZE(peri_muxes), + .rst_desc = &clk_rst_desc, + .clk_lock = &mt7622_clk_lock, +}; static const struct of_device_id of_match_clk_mt7622[] = { - { - .compatible = "mediatek,mt7622-apmixedsys", - .data = mtk_apmixedsys_init, - }, { - .compatible = "mediatek,mt7622-infracfg", - .data = mtk_infrasys_init, - }, { - .compatible = "mediatek,mt7622-topckgen", - .data = mtk_topckgen_init, - }, { - .compatible = "mediatek,mt7622-pericfg", - .data = mtk_pericfg_init, - }, { - /* sentinel */ - } -}; - -static int clk_mt7622_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} + { .compatible = "mediatek,mt7622-topckgen", .data = &topck_desc }, + { .compatible = "mediatek,mt7622-pericfg", .data = &peri_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7622); static struct platform_driver clk_mt7622_drv = { - .probe = clk_mt7622_probe, .driver = { .name = "clk-mt7622", .of_match_table = of_match_clk_mt7622, }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, }; +module_platform_driver(clk_mt7622_drv) -static int clk_mt7622_init(void) -{ - return platform_driver_register(&clk_mt7622_drv); -} - -arch_initcall(clk_mt7622_init); +MODULE_DESCRIPTION("MediaTek MT7622 clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index a4ae7d6c7a71..1e1c77cc14ba 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -16,14 +16,8 @@ #include <dt-bindings/clock/mt7629-clk.h> -#define GATE_ETH(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = ð_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate_regs eth_cg_regs = { .set_ofs = 0x30, @@ -45,14 +39,8 @@ static const struct mtk_gate_regs sgmii_cg_regs = { .sta_ofs = 0xE4, }; -#define GATE_SGMII(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &sgmii_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate sgmii_clks[2][4] = { { @@ -138,6 +126,7 @@ static const struct of_device_id of_match_clk_mt7629_eth[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_eth); static int clk_mt7629_eth_probe(struct platform_device *pdev) { @@ -166,3 +155,4 @@ static struct platform_driver clk_mt7629_eth_drv = { }; builtin_platform_driver(clk_mt7629_eth_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index c3eb09ea6036..c89036bee9a7 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -16,23 +16,11 @@ #include <dt-bindings/clock/mt7629-clk.h> -#define GATE_PCIE(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &pcie_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_PCIE(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &pcie_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) -#define GATE_SSUSB(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ssusb_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SSUSB(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ssusb_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) static const struct mtk_gate_regs pcie_cg_regs = { .set_ofs = 0x30, @@ -96,6 +84,7 @@ static const struct of_device_id of_match_clk_mt7629_hif[] = { { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_hif); static struct platform_driver clk_mt7629_hif_drv = { .probe = mtk_clk_simple_probe, @@ -105,5 +94,5 @@ static struct platform_driver clk_mt7629_hif_drv = { .of_match_table = of_match_clk_mt7629_hif, }, }; - -builtin_platform_driver(clk_mt7629_hif_drv); +module_platform_driver(clk_mt7629_hif_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index cf062d4a7ecc..0893fbbb68cc 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -50,41 +50,17 @@ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ NULL, "clk20m") -#define GATE_APMIXED(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &apmixed_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) -#define GATE_INFRA(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &infra_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static DEFINE_SPINLOCK(mt7629_clk_lock); @@ -684,6 +660,7 @@ static const struct of_device_id of_match_clk_mt7629[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7629); static int clk_mt7629_probe(struct platform_device *pdev) { @@ -717,3 +694,4 @@ static int clk_mt7629_init(void) } arch_initcall(clk_mt7629_init); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-apmixed.c b/drivers/clk/mediatek/clk-mt7981-apmixed.c index 52b7123232bf..875813d8b4a9 100644 --- a/drivers/clk/mediatek/clk-mt7981-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c @@ -66,6 +66,7 @@ static const struct of_device_id of_match_clk_mt7981_apmixed[] = { { .compatible = "mediatek,mt7981-apmixedsys", }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_apmixed); static int clk_mt7981_apmixed_probe(struct platform_device *pdev) { @@ -100,3 +101,4 @@ static struct platform_driver clk_mt7981_apmixed_drv = { }, }; builtin_platform_driver(clk_mt7981_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-eth.c b/drivers/clk/mediatek/clk-mt7981-eth.c index 773350911be2..b1f256b5ed4e 100644 --- a/drivers/clk/mediatek/clk-mt7981-eth.c +++ b/drivers/clk/mediatek/clk-mt7981-eth.c @@ -105,6 +105,7 @@ static const struct of_device_id of_match_clk_mt7981_eth[] = { { .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_eth); static struct platform_driver clk_mt7981_eth_drv = { .probe = mtk_clk_simple_probe, @@ -115,4 +116,4 @@ static struct platform_driver clk_mt7981_eth_drv = { }, }; module_platform_driver(clk_mt7981_eth_drv); -MODULE_LICENSE("GPL v2"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-infracfg.c b/drivers/clk/mediatek/clk-mt7981-infracfg.c index 8cf5057419e8..293261ef71e6 100644 --- a/drivers/clk/mediatek/clk-mt7981-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c @@ -195,6 +195,7 @@ static const struct of_device_id of_match_clk_mt7981_infracfg[] = { { .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_infracfg); static struct platform_driver clk_mt7981_infracfg_drv = { .probe = mtk_clk_simple_probe, @@ -204,4 +205,5 @@ static struct platform_driver clk_mt7981_infracfg_drv = { .of_match_table = of_match_clk_mt7981_infracfg, }, }; -builtin_platform_driver(clk_mt7981_infracfg_drv); +module_platform_driver(clk_mt7981_infracfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7981-topckgen.c b/drivers/clk/mediatek/clk-mt7981-topckgen.c index 74634d65f5f6..3aba1a9b9a36 100644 --- a/drivers/clk/mediatek/clk-mt7981-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c @@ -410,6 +410,7 @@ static const struct of_device_id of_match_clk_mt7981_topckgen[] = { { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7981_topckgen); static struct platform_driver clk_mt7981_topckgen_drv = { .probe = mtk_clk_simple_probe, @@ -419,4 +420,5 @@ static struct platform_driver clk_mt7981_topckgen_drv = { .of_match_table = of_match_clk_mt7981_topckgen, }, }; -builtin_platform_driver(clk_mt7981_topckgen_drv); +module_platform_driver(clk_mt7981_topckgen_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c index 62080ee4dbe3..6767e9c43886 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -42,7 +42,7 @@ "clkxtal") static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32, + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32, 0x0200, 4, 0, 0x0204, 0), PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32, 0x0210, 4, 0, 0x0214, 0), @@ -62,8 +62,9 @@ static const struct mtk_pll_data plls[] = { static const struct of_device_id of_match_clk_mt7986_apmixed[] = { { .compatible = "mediatek,mt7986-apmixedsys", }, - {} + { } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_apmixed); static int clk_mt7986_apmixed_probe(struct platform_device *pdev) { @@ -77,8 +78,6 @@ static int clk_mt7986_apmixed_probe(struct platform_device *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { pr_err("%s(): could not register clock provider: %d\n", @@ -100,3 +99,4 @@ static struct platform_driver clk_mt7986_apmixed_drv = { }, }; builtin_platform_driver(clk_mt7986_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/clk-mt7986-eth.c index 703872239ecc..0681988960cc 100644 --- a/drivers/clk/mediatek/clk-mt7986-eth.c +++ b/drivers/clk/mediatek/clk-mt7986-eth.c @@ -22,14 +22,10 @@ static const struct mtk_gate_regs sgmii0_cg_regs = { .sta_ofs = 0xe4, }; -#define GATE_SGMII0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii0_clks[] __initconst = { +#define GATE_SGMII0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +static const struct mtk_gate sgmii0_clks[] = { GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2), GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3), GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4), @@ -42,14 +38,10 @@ static const struct mtk_gate_regs sgmii1_cg_regs = { .sta_ofs = 0xe4, }; -#define GATE_SGMII1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_SGMII1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &sgmii1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) -static const struct mtk_gate sgmii1_clks[] __initconst = { +static const struct mtk_gate sgmii1_clks[] = { GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2), GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3), GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4), @@ -62,14 +54,10 @@ static const struct mtk_gate_regs eth_cg_regs = { .sta_ofs = 0x30, }; -#define GATE_ETH(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ð_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } +#define GATE_ETH(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) -static const struct mtk_gate eth_clks[] __initconst = { +static const struct mtk_gate eth_clks[] = { GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6), GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7), GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8), @@ -77,56 +65,38 @@ static const struct mtk_gate eth_clks[] __initconst = { GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15), }; -static void __init mtk_sgmiisys_0_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - - mtk_clk_register_gates(NULL, node, sgmii0_clks, - ARRAY_SIZE(sgmii0_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0", - mtk_sgmiisys_0_init); - -static void __init mtk_sgmiisys_1_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - - mtk_clk_register_gates(NULL, node, sgmii1_clks, - ARRAY_SIZE(sgmii1_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1", - mtk_sgmiisys_1_init); - -static void __init mtk_ethsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; +static const struct mtk_clk_desc eth_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(eth_clks), +}; - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); +static const struct mtk_clk_desc sgmii0_desc = { + .clks = sgmii0_clks, + .num_clks = ARRAY_SIZE(sgmii0_clks), +}; - mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); +static const struct mtk_clk_desc sgmii1_desc = { + .clks = sgmii1_clks, + .num_clks = ARRAY_SIZE(sgmii1_clks), +}; - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct of_device_id of_match_clk_mt7986_eth[] = { + { .compatible = "mediatek,mt7986-ethsys", .data = ð_desc }, + { .compatible = "mediatek,mt7986-sgmiisys_0", .data = &sgmii0_desc }, + { .compatible = "mediatek,mt7986-sgmiisys_1", .data = &sgmii1_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_eth); + +static struct platform_driver clk_mt7986_eth_drv = { + .driver = { + .name = "clk-mt7986-eth", + .of_match_table = of_match_clk_mt7986_eth, + }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, +}; +module_platform_driver(clk_mt7986_eth_drv); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init); +MODULE_DESCRIPTION("MediaTek MT7986 Ethernet clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/mediatek/clk-mt7986-infracfg.c index e80c92167c8f..b7efa70c2d6c 100644 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -87,26 +87,14 @@ static const struct mtk_gate_regs infra2_cg_regs = { .sta_ofs = 0x68, }; -#define GATE_INFRA0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_INFRA2(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra2_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_INFRA0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_INFRA1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_INFRA2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate infra_clks[] = { /* INFRA0 */ @@ -169,57 +157,31 @@ static const struct mtk_gate infra_clks[] = { GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15), }; -static int clk_mt7986_infracfg_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) + - ARRAY_SIZE(infra_clks); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - mtk_clk_register_muxes(&pdev->dev, infra_muxes, - ARRAY_SIZE(infra_muxes), node, - &mt7986_clk_lock, clk_data); - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_infracfg_data; - } - return r; - -free_infracfg_data: - mtk_free_clk_data(clk_data); - return r; - -} +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .factor_clks = infra_divs, + .num_factor_clks = ARRAY_SIZE(infra_divs), + .mux_clks = infra_muxes, + .num_mux_clks = ARRAY_SIZE(infra_muxes), + .clk_lock = &mt7986_clk_lock, +}; static const struct of_device_id of_match_clk_mt7986_infracfg[] = { - { .compatible = "mediatek,mt7986-infracfg", }, - {} + { .compatible = "mediatek,mt7986-infracfg", .data = &infra_desc }, + { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_infracfg); static struct platform_driver clk_mt7986_infracfg_drv = { - .probe = clk_mt7986_infracfg_probe, .driver = { .name = "clk-mt7986-infracfg", .of_match_table = of_match_clk_mt7986_infracfg, }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, }; -builtin_platform_driver(clk_mt7986_infracfg_drv); +module_platform_driver(clk_mt7986_infracfg_drv); + +MODULE_DESCRIPTION("MediaTek MT7986 infracfg clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/mediatek/clk-mt7986-topckgen.c index dff9976fa689..fbca3feded8f 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -304,6 +304,7 @@ static const struct of_device_id of_match_clk_mt7986_topckgen[] = { { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt7986_topckgen); static struct platform_driver clk_mt7986_topckgen_drv = { .probe = mtk_clk_simple_probe, @@ -313,4 +314,5 @@ static struct platform_driver clk_mt7986_topckgen_drv = { .of_match_table = of_match_clk_mt7986_topckgen, }, }; -builtin_platform_driver(clk_mt7986_topckgen_drv); +module_platform_driver(clk_mt7986_topckgen_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8135-apmixedsys.c b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c new file mode 100644 index 000000000000..744aae092281 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8135-apmixedsys.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * James Liao <jamesjj.liao@mediatek.com> + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#include <dt-bindings/clock/mt8135-clk.h> +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-pll.h" + +#define MT8135_PLL_FMAX (2000 * MHZ) +#define CON0_MT8135_RST_BAR BIT(27) + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = CON0_MT8135_RST_BAR, \ + .fmax = MT8135_PLL_FMAX, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + } + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0), + PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), + PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0), + PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0), +}; + +static int clk_mt8135_apmixed_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int ret; + + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_plls; + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static int clk_mt8135_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static const struct of_device_id of_match_clk_mt8135_apmixed[] = { + { .compatible = "mediatek,mt8135-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8135_apmixed); + +static struct platform_driver clk_mt8135_apmixed_drv = { + .probe = clk_mt8135_apmixed_probe, + .remove = clk_mt8135_apmixed_remove, + .driver = { + .name = "clk-mt8135-apmixed", + .of_match_table = of_match_clk_mt8135_apmixed, + }, +}; +module_platform_driver(clk_mt8135_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT8135 apmixedsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index 2b9c925c2a2b..084e48a554c2 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -5,8 +5,10 @@ */ #include <linux/clk.h> +#include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/platform_device.h> #include <linux/slab.h> #include <linux/mfd/syscon.h> #include <dt-bindings/clock/mt8135-clk.h> @@ -17,14 +19,13 @@ static DEFINE_SPINLOCK(mt8135_clk_lock); -static const struct mtk_fixed_factor root_clk_alias[] __initconst = { +static const struct mtk_fixed_factor top_divs[] = { + FACTOR(CLK_DUMMY, "top_divs_dummy", "clk_null", 1, 1), FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), -}; -static const struct mtk_fixed_factor top_divs[] __initconst = { FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2), FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3), FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5), @@ -100,7 +101,7 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), }; -static const char * const axi_parents[] __initconst = { +static const char * const axi_parents[] = { "clk26m", "syspll_d3", "syspll_d4", @@ -110,7 +111,7 @@ static const char * const axi_parents[] __initconst = { "syspll_d3p5" }; -static const char * const smi_parents[] __initconst = { +static const char * const smi_parents[] = { "clk26m", "clkph_mck", "syspll_d2p5", @@ -128,7 +129,7 @@ static const char * const smi_parents[] __initconst = { "lvdspll" }; -static const char * const mfg_parents[] __initconst = { +static const char * const mfg_parents[] = { "clk26m", "univpll1_d4", "syspll_d2", @@ -144,13 +145,13 @@ static const char * const mfg_parents[] __initconst = { "mmpll_d7" }; -static const char * const irda_parents[] __initconst = { +static const char * const irda_parents[] = { "clk26m", "univpll2_d8", "univpll1_d6" }; -static const char * const cam_parents[] __initconst = { +static const char * const cam_parents[] = { "clk26m", "syspll_d3", "syspll_d3p5", @@ -161,13 +162,13 @@ static const char * const cam_parents[] __initconst = { "univpll1_d4" }; -static const char * const aud_intbus_parents[] __initconst = { +static const char * const aud_intbus_parents[] = { "clk26m", "syspll_d6", "univpll_d10" }; -static const char * const jpg_parents[] __initconst = { +static const char * const jpg_parents[] = { "clk26m", "syspll_d5", "syspll_d4", @@ -177,7 +178,7 @@ static const char * const jpg_parents[] __initconst = { "univpll_d5" }; -static const char * const disp_parents[] __initconst = { +static const char * const disp_parents[] = { "clk26m", "syspll_d3p5", "syspll_d3", @@ -188,7 +189,7 @@ static const char * const disp_parents[] __initconst = { "vdecpll" }; -static const char * const msdc30_parents[] __initconst = { +static const char * const msdc30_parents[] = { "clk26m", "syspll_d6", "syspll_d5", @@ -197,13 +198,13 @@ static const char * const msdc30_parents[] __initconst = { "msdcpll" }; -static const char * const usb20_parents[] __initconst = { +static const char * const usb20_parents[] = { "clk26m", "univpll2_d6", "univpll1_d10" }; -static const char * const venc_parents[] __initconst = { +static const char * const venc_parents[] = { "clk26m", "syspll_d3", "syspll_d8", @@ -214,7 +215,7 @@ static const char * const venc_parents[] __initconst = { "mmpll_d6" }; -static const char * const spi_parents[] __initconst = { +static const char * const spi_parents[] = { "clk26m", "syspll_d6", "syspll_d8", @@ -223,17 +224,17 @@ static const char * const spi_parents[] __initconst = { "univpll1_d8" }; -static const char * const uart_parents[] __initconst = { +static const char * const uart_parents[] = { "clk26m", "univpll2_d8" }; -static const char * const mem_parents[] __initconst = { +static const char * const mem_parents[] = { "clk26m", "clkph_mck" }; -static const char * const camtg_parents[] __initconst = { +static const char * const camtg_parents[] = { "clk26m", "univpll_d26", "univpll1_d6", @@ -241,12 +242,12 @@ static const char * const camtg_parents[] __initconst = { "syspll_d8" }; -static const char * const audio_parents[] __initconst = { +static const char * const audio_parents[] = { "clk26m", "syspll_d24" }; -static const char * const fix_parents[] __initconst = { +static const char * const fix_parents[] = { "rtc32k", "clk26m", "univpll_d5", @@ -257,7 +258,7 @@ static const char * const fix_parents[] __initconst = { "univpll1_d8" }; -static const char * const vdec_parents[] __initconst = { +static const char * const vdec_parents[] = { "clk26m", "vdecpll", "clkph_mck", @@ -276,13 +277,13 @@ static const char * const vdec_parents[] __initconst = { "lvdspll" }; -static const char * const ddrphycfg_parents[] __initconst = { +static const char * const ddrphycfg_parents[] = { "clk26m", "axi_sel", "syspll_d12" }; -static const char * const dpilvds_parents[] __initconst = { +static const char * const dpilvds_parents[] = { "clk26m", "lvdspll", "lvdspll_d2", @@ -290,7 +291,7 @@ static const char * const dpilvds_parents[] __initconst = { "lvdspll_d8" }; -static const char * const pmicspi_parents[] __initconst = { +static const char * const pmicspi_parents[] = { "clk26m", "univpll2_d6", "syspll_d8", @@ -301,14 +302,14 @@ static const char * const pmicspi_parents[] __initconst = { "syspll_d24" }; -static const char * const smi_mfg_as_parents[] __initconst = { +static const char * const smi_mfg_as_parents[] = { "clk26m", "smi_sel", "mfg_sel", "mem_sel" }; -static const char * const gcpu_parents[] __initconst = { +static const char * const gcpu_parents[] = { "clk26m", "syspll_d4", "univpll_d7", @@ -316,14 +317,14 @@ static const char * const gcpu_parents[] __initconst = { "syspll_d6" }; -static const char * const dpi1_parents[] __initconst = { +static const char * const dpi1_parents[] = { "clk26m", "tvhdmi_h_ck", "tvhdmi_d2", "tvhdmi_d4" }; -static const char * const cci_parents[] __initconst = { +static const char * const cci_parents[] = { "clk26m", "mainpll_537p3m", "univpll_d3", @@ -332,7 +333,7 @@ static const char * const cci_parents[] __initconst = { "syspll_d5" }; -static const char * const apll_parents[] __initconst = { +static const char * const apll_parents[] = { "clk26m", "apll_ck", "apll_d4", @@ -341,14 +342,14 @@ static const char * const apll_parents[] __initconst = { "apll_d24" }; -static const char * const hdmipll_parents[] __initconst = { +static const char * const hdmipll_parents[] = { "clk26m", "hdmitx_clkdig_cts", "hdmitx_clkdig_d2", "hdmitx_clkdig_d3" }; -static const struct mtk_composite top_muxes[] __initconst = { +static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0140, 0, 3, INVALID_MUX_GATE_BIT), @@ -390,7 +391,7 @@ static const struct mtk_composite top_muxes[] __initconst = { MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31), /* CLK_CFG_9 */ MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7), - MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15), + MUX_GATE_FLAGS(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15, CLK_IS_CRITICAL), MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23), MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31), }; @@ -401,23 +402,22 @@ static const struct mtk_gate_regs infra_cg_regs = { .sta_ofs = 0x0048, }; -#define GATE_ICG(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &infra_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_ICG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_ICG_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) -static const struct mtk_gate infra_clks[] __initconst = { +static const struct mtk_gate infra_clks[] = { + GATE_DUMMY(CLK_DUMMY, "infra_dummy"), GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21), GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20), GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15), - GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), + GATE_ICG_AO(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7), GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6), GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5), @@ -438,25 +438,14 @@ static const struct mtk_gate_regs peri1_cg_regs = { .sta_ofs = 0x001c, }; -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &peri1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -static const struct mtk_gate peri_gates[] __initconst = { +static const struct mtk_gate peri_gates[] = { + GATE_DUMMY(CLK_DUMMY, "peri_dummy"), /* PERI0 */ GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31), GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30), @@ -502,12 +491,12 @@ static const struct mtk_gate peri_gates[] __initconst = { GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0), }; -static const char * const uart_ck_sel_parents[] __initconst = { +static const char * const uart_ck_sel_parents[] = { "clk26m", "uart_sel", }; -static const struct mtk_composite peri_clks[] __initconst = { +static const struct mtk_composite peri_clks[] = { MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), @@ -532,127 +521,46 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = { } }; -static void __init mtk_topckgen_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_composites(NULL, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt8135_clk_lock, clk_data); - - clk_prepare_enable(clk_data->hws[CLK_TOP_CCI_SEL]->clk); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init); - -static void __init mtk_infrasys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(NULL, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - - clk_prepare_enable(clk_data->hws[CLK_INFRA_M4U]->clk); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc[0], +}; - mtk_register_reset_controller(node, &clk_rst_desc[0]); -} -CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); +static const struct mtk_clk_desc peri_desc = { + .clks = peri_gates, + .num_clks = ARRAY_SIZE(peri_gates), + .composite_clks = peri_clks, + .num_composite_clks = ARRAY_SIZE(peri_clks), + .clk_lock = &mt8135_clk_lock, + .rst_desc = &clk_rst_desc[1], +}; -static void __init mtk_pericfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; +static const struct mtk_clk_desc topck_desc = { + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .composite_clks = top_muxes, + .num_composite_clks = ARRAY_SIZE(top_muxes), + .clk_lock = &mt8135_clk_lock, +}; - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } +static const struct of_device_id of_match_clk_mt8135[] = { + { .compatible = "mediatek,mt8135-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt8135-pericfg", .data = &peri_desc }, + { .compatible = "mediatek,mt8135-topckgen", .data = &topck_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8135); - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(NULL, node, peri_gates, - ARRAY_SIZE(peri_gates), clk_data); - mtk_clk_register_composites(NULL, peri_clks, - ARRAY_SIZE(peri_clks), base, - &mt8135_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller(node, &clk_rst_desc[1]); -} -CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); - -#define MT8135_PLL_FMAX (2000 * MHZ) -#define CON0_MT8135_RST_BAR BIT(27) - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ - .id = _id, \ - .name = _name, \ - .reg = _reg, \ - .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, \ - .flags = _flags, \ - .rst_bar_mask = CON0_MT8135_RST_BAR, \ - .fmax = MT8135_PLL_FMAX, \ - .pcwbits = _pcwbits, \ - .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, \ - .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, \ - } +static struct platform_driver clk_mt8135_drv = { + .driver = { + .name = "clk-mt8135", + .of_match_table = of_match_clk_mt8135, + }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, +}; +module_platform_driver(clk_mt8135_drv); -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0), - PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), - PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0), - PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0), -}; - -static void __init mtk_apmixedsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - - clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); -} -CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys", - mtk_apmixedsys_init); +MODULE_DESCRIPTION("MediaTek MT8135 clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-apmixedsys.c b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c new file mode 100644 index 000000000000..fca41f50d6ba --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8167-apmixedsys.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020 BayLibre, SAS + * Copyright (c) 2023 Collabora, Ltd. + */ + +#include <dt-bindings/clock/mt8167-clk.h> +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "clk-pll.h" +#include "clk-mtk.h" + +static DEFINE_SPINLOCK(mt8167_apmixed_clk_lock); + +#define MT8167_PLL_FMAX (2500UL * MHZ) + +#define CON0_MT8167_RST_BAR BIT(27) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift, _div_table) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = CON0_MT8167_RST_BAR, \ + .fmax = MT8167_PLL_FMAX, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_table = _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + NULL) + +static const struct mtk_pll_div_table mmpll_div_table[] = { + { .div = 0, .freq = MT8167_PLL_FMAX }, + { .div = 1, .freq = 1000000000 }, + { .div = 2, .freq = 604500000 }, + { .div = 3, .freq = 253500000 }, + { .div = 4, .freq = 126750000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, + 21, 0x0104, 24, 0, 0x0104, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, + HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, + HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, + 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), + PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, + 31, 0x0180, 1, 0x0194, 0x0184, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, + 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0, + 21, 0x01C4, 24, 0, 0x01C4, 0), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0, + 21, 0x01E4, 24, 0, 0x01E4, 0), +}; + +#define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .div_reg = _reg, \ + .div_shift = _shift, \ + .div_width = _width, \ + .clk_divider_flags = _flag, \ +} + +static const struct mtk_clk_divider adj_divs[] = { + DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", + 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO), +}; + +static int clk_mt8167_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_devm_alloc_clk_data(dev, MT8167_CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret = mtk_clk_register_dividers(dev, adj_divs, ARRAY_SIZE(adj_divs), base, + &mt8167_apmixed_clk_lock, clk_data); + if (ret) + goto unregister_plls; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_dividers; + + return 0; + +unregister_dividers: + mtk_clk_unregister_dividers(adj_divs, ARRAY_SIZE(adj_divs), clk_data); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt8167_apmixed[] = { + { .compatible = "mediatek,mt8167-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_apmixed); + +static struct platform_driver clk_mt8167_apmixed_drv = { + .probe = clk_mt8167_apmixed_probe, + .driver = { + .name = "clk-mt8167-apmixed", + .of_match_table = of_match_clk_mt8167_apmixed, + }, +}; +builtin_platform_driver(clk_mt8167_apmixed_drv) +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/clk-mt8167-aud.c index f6bea6e9e6a4..86125635c8a6 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -23,16 +23,11 @@ static const struct mtk_gate_regs aud_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_AUD(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &aud_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -static const struct mtk_gate aud_clks[] __initconst = { + +static const struct mtk_gate aud_clks[] = { GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6), GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8), @@ -48,19 +43,24 @@ static const struct mtk_gate aud_clks[] __initconst = { GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27), }; -static void __init mtk_audsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); - - mtk_clk_register_gates(NULL, node, aud_clks, ARRAY_SIZE(aud_clks), clk_data); +static const struct mtk_clk_desc aud_desc = { + .clks = aud_clks, + .num_clks = ARRAY_SIZE(aud_clks), +}; - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_audsys[] = { + { .compatible = "mediatek,mt8167-audsys", .data = &aud_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_audsys); -} -CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8167-audsys", mtk_audsys_init); +static struct platform_driver clk_mt8167_audsys_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8167-audsys", + .of_match_table = of_match_clk_mt8167_audsys, + }, +}; +module_platform_driver(clk_mt8167_audsys_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/clk-mt8167-img.c index 77db13b177fc..315b7f64bad6 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -23,16 +23,10 @@ static const struct mtk_gate_regs img_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &img_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate img_clks[] __initconst = { +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate img_clks[] = { GATE_IMG(CLK_IMG_LARB1_SMI, "img_larb1_smi", "smi_mm", 0), GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "smi_mm", 5), GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "smi_mm", 6), @@ -41,20 +35,24 @@ static const struct mtk_gate img_clks[] __initconst = { GATE_IMG(CLK_IMG_VENC, "img_venc", "smi_mm", 9), }; -static void __init mtk_imgsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); - - mtk_clk_register_gates(NULL, node, img_clks, ARRAY_SIZE(img_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct mtk_clk_desc img_desc = { + .clks = img_clks, + .num_clks = ARRAY_SIZE(img_clks), +}; -} -CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8167-imgsys", mtk_imgsys_init); +static const struct of_device_id of_match_clk_mt8167_imgsys[] = { + { .compatible = "mediatek,mt8167-imgsys", .data = &img_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_imgsys); + +static struct platform_driver clk_mt8167_imgsys_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8167-imgsys", + .of_match_table = of_match_clk_mt8167_imgsys, + }, +}; +module_platform_driver(clk_mt8167_imgsys_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c index 3c23591b02f7..4851f5bf3a90 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -23,36 +23,34 @@ static const struct mtk_gate_regs mfg_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_MFG(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mfg_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate mfg_clks[] __initconst = { +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate mfg_clks[] = { GATE_MFG(CLK_MFG_BAXI, "mfg_baxi", "ahb_infra_sel", 0), GATE_MFG(CLK_MFG_BMEM, "mfg_bmem", "gfmux_emi1x_sel", 1), GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_mm", 2), GATE_MFG(CLK_MFG_B26M, "mfg_b26m", "clk26m_ck", 3), }; -static void __init mtk_mfgcfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK); - - mtk_clk_register_gates(NULL, node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct mtk_clk_desc mfg_desc = { + .clks = mfg_clks, + .num_clks = ARRAY_SIZE(mfg_clks), +}; -} -CLK_OF_DECLARE(mtk_mfgcfg, "mediatek,mt8167-mfgcfg", mtk_mfgcfg_init); +static const struct of_device_id of_match_clk_mt8167_mfgcfg[] = { + { .compatible = "mediatek,mt8167-mfgcfg", .data = &mfg_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_mfgcfg); + +static struct platform_driver clk_mt8167_mfgcfg_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8167-mfgcfg", + .of_match_table = of_match_clk_mt8167_mfgcfg, + }, +}; +module_platform_driver(clk_mt8167_mfgcfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/clk-mt8167-mm.c index c0b44104c765..4e053c61315d 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -29,23 +29,11 @@ static const struct mtk_gate_regs mm1_cg_regs = { .sta_ofs = 0x110, }; -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mm_clks[] = { /* MM0 */ @@ -86,47 +74,24 @@ static const struct mtk_gate mm_clks[] = { GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21), }; -struct clk_mt8167_mm_driver_data { - const struct mtk_gate *gates_clk; - int gates_num; +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), }; -static const struct clk_mt8167_mm_driver_data mt8167_mmsys_driver_data = { - .gates_clk = mm_clks, - .gates_num = ARRAY_SIZE(mm_clks), +static const struct platform_device_id clk_mt8167_mm_id_table[] = { + { .name = "clk-mt8167-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } }; +MODULE_DEVICE_TABLE(platform, clk_mt8167_mm_id_table); -static int clk_mt8167_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - const struct clk_mt8167_mm_driver_data *data; - struct clk_hw_onecell_data *clk_data; - int ret; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - data = &mt8167_mmsys_driver_data; - - ret = mtk_clk_register_gates(&pdev->dev, node, data->gates_clk, - data->gates_num, clk_data); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - return ret; - - return 0; -} - -static struct platform_driver clk_mt8173_mm_drv = { +static struct platform_driver clk_mt8167_mm_drv = { + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt8167-mm", }, - .probe = clk_mt8167_mm_probe, + .id_table = clk_mt8167_mm_id_table, }; - -builtin_platform_driver(clk_mt8173_mm_drv); +module_platform_driver(clk_mt8167_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/clk-mt8167-vdec.c index 759e5791599f..76900f393d31 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -29,46 +29,37 @@ static const struct mtk_gate_regs vdec1_cg_regs = { .sta_ofs = 0x8, }; -#define GATE_VDEC0_I(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &vdec0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC0_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) -#define GATE_VDEC1_I(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &vdec1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } +#define GATE_VDEC1_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) -static const struct mtk_gate vdec_clks[] __initconst = { +static const struct mtk_gate vdec_clks[] = { /* VDEC0 */ GATE_VDEC0_I(CLK_VDEC_CKEN, "vdec_cken", "rg_vdec", 0), /* VDEC1 */ GATE_VDEC1_I(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "smi_mm", 0), }; -static void __init mtk_vdecsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK); - - mtk_clk_register_gates(NULL, node, vdec_clks, ARRAY_SIZE(vdec_clks), - clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct mtk_clk_desc vdec_desc = { + .clks = vdec_clks, + .num_clks = ARRAY_SIZE(vdec_clks), +}; - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167_vdec[] = { + { .compatible = "mediatek,mt8167-vdecsys", .data = &vdec_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167_vdec); -} -CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8167-vdecsys", mtk_vdecsys_init); +static struct platform_driver clk_mt8167_vdec_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8167-vdecsys", + .of_match_table = of_match_clk_mt8167_vdec, + }, +}; +module_platform_driver(clk_mt8167_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c index 91669ebafaf9..b9041f79cbbd 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -11,16 +11,16 @@ #include <linux/of_address.h> #include <linux/slab.h> #include <linux/mfd/syscon.h> +#include <linux/platform_device.h> #include "clk-gate.h" #include "clk-mtk.h" -#include "clk-pll.h" #include <dt-bindings/clock/mt8167-clk.h> static DEFINE_SPINLOCK(mt8167_clk_lock); -static const struct mtk_fixed_clk fixed_clks[] __initconst = { +static const struct mtk_fixed_clk fixed_clks[] = { FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000), FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000), @@ -29,7 +29,7 @@ static const struct mtk_fixed_clk fixed_clks[] __initconst = { FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 52500000), }; -static const struct mtk_fixed_factor top_divs[] __initconst = { +static const struct mtk_fixed_factor top_divs[] = { FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2), FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), @@ -85,22 +85,22 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2), }; -static const char * const uart0_parents[] __initconst = { +static const char * const uart0_parents[] = { "clk26m_ck", "univpll_d24" }; -static const char * const gfmux_emi1x_parents[] __initconst = { +static const char * const gfmux_emi1x_parents[] = { "clk26m_ck", "dmpll_ck" }; -static const char * const emi_ddrphy_parents[] __initconst = { +static const char * const emi_ddrphy_parents[] = { "gfmux_emi1x_sel", "gfmux_emi1x_sel" }; -static const char * const ahb_infra_parents[] __initconst = { +static const char * const ahb_infra_parents[] = { "clk_null", "clk26m_ck", "mainpll_d11", @@ -116,7 +116,7 @@ static const char * const ahb_infra_parents[] __initconst = { "mainpll_d10" }; -static const char * const csw_mux_mfg_parents[] __initconst = { +static const char * const csw_mux_mfg_parents[] = { "clk_null", "clk_null", "univpll_d3", @@ -127,7 +127,7 @@ static const char * const csw_mux_mfg_parents[] __initconst = { "mmpll380m" }; -static const char * const msdc0_parents[] __initconst = { +static const char * const msdc0_parents[] = { "clk26m_ck", "univpll_d6", "mainpll_d8", @@ -138,7 +138,7 @@ static const char * const msdc0_parents[] __initconst = { "mmpll_d2" }; -static const char * const camtg_mm_parents[] __initconst = { +static const char * const camtg_mm_parents[] = { "clk_null", "clk26m_ck", "usb_phy48m_ck", @@ -146,17 +146,17 @@ static const char * const camtg_mm_parents[] __initconst = { "univpll_d6" }; -static const char * const pwm_mm_parents[] __initconst = { +static const char * const pwm_mm_parents[] = { "clk26m_ck", "univpll_d12" }; -static const char * const uart1_parents[] __initconst = { +static const char * const uart1_parents[] = { "clk26m_ck", "univpll_d24" }; -static const char * const msdc1_parents[] __initconst = { +static const char * const msdc1_parents[] = { "clk26m_ck", "univpll_d6", "mainpll_d8", @@ -167,24 +167,24 @@ static const char * const msdc1_parents[] __initconst = { "mmpll_d2" }; -static const char * const spm_52m_parents[] __initconst = { +static const char * const spm_52m_parents[] = { "clk26m_ck", "univpll_d24" }; -static const char * const pmicspi_parents[] __initconst = { +static const char * const pmicspi_parents[] = { "univpll_d20", "usb_phy48m_ck", "univpll_d16", "clk26m_ck" }; -static const char * const qaxi_aud26m_parents[] __initconst = { +static const char * const qaxi_aud26m_parents[] = { "clk26m_ck", "ahb_infra_sel" }; -static const char * const aud_intbus_parents[] __initconst = { +static const char * const aud_intbus_parents[] = { "clk_null", "clk26m_ck", "mainpll_d22", @@ -192,7 +192,7 @@ static const char * const aud_intbus_parents[] __initconst = { "mainpll_d11" }; -static const char * const nfi2x_pad_parents[] __initconst = { +static const char * const nfi2x_pad_parents[] = { "clk_null", "clk_null", "clk_null", @@ -280,12 +280,12 @@ static const char * const nfi2x_pad_parents[] __initconst = { "mainpll_d5" }; -static const char * const nfi1x_pad_parents[] __initconst = { +static const char * const nfi1x_pad_parents[] = { "ahb_infra_sel", "nfi1x_ck" }; -static const char * const mfg_mm_parents[] __initconst = { +static const char * const mfg_mm_parents[] = { "clk_null", "clk_null", "clk_null", @@ -325,12 +325,12 @@ static const char * const mfg_mm_parents[] __initconst = { "mainpll_d14" }; -static const char * const ddrphycfg_parents[] __initconst = { +static const char * const ddrphycfg_parents[] = { "clk26m_ck", "mainpll_d16" }; -static const char * const smi_mm_parents[] __initconst = { +static const char * const smi_mm_parents[] = { "clk26m_ck", "clk_null", "clk_null", @@ -346,7 +346,7 @@ static const char * const smi_mm_parents[] __initconst = { "mainpll_d14" }; -static const char * const usb_78m_parents[] __initconst = { +static const char * const usb_78m_parents[] = { "clk_null", "clk26m_ck", "univpll_d16", @@ -354,7 +354,7 @@ static const char * const usb_78m_parents[] __initconst = { "mainpll_d20" }; -static const char * const scam_mm_parents[] __initconst = { +static const char * const scam_mm_parents[] = { "clk_null", "clk26m_ck", "mainpll_d14", @@ -362,7 +362,7 @@ static const char * const scam_mm_parents[] __initconst = { "mainpll_d12" }; -static const char * const spinor_parents[] __initconst = { +static const char * const spinor_parents[] = { "clk26m_d2", "clk26m_ck", "mainpll_d40", @@ -373,7 +373,7 @@ static const char * const spinor_parents[] __initconst = { "univpll_d12" }; -static const char * const msdc2_parents[] __initconst = { +static const char * const msdc2_parents[] = { "clk26m_ck", "univpll_d6", "mainpll_d8", @@ -384,7 +384,7 @@ static const char * const msdc2_parents[] __initconst = { "mmpll_d2" }; -static const char * const eth_parents[] __initconst = { +static const char * const eth_parents[] = { "clk26m_ck", "mainpll_d40", "univpll_d24", @@ -392,7 +392,7 @@ static const char * const eth_parents[] __initconst = { "mainpll_d20" }; -static const char * const vdec_mm_parents[] __initconst = { +static const char * const vdec_mm_parents[] = { "clk26m_ck", "univpll_d4", "mainpll_d4", @@ -401,7 +401,7 @@ static const char * const vdec_mm_parents[] __initconst = { "mainpll_d6" }; -static const char * const dpi0_mm_parents[] __initconst = { +static const char * const dpi0_mm_parents[] = { "clk26m_ck", "lvdspll_ck", "lvdspll_d2", @@ -409,7 +409,7 @@ static const char * const dpi0_mm_parents[] __initconst = { "lvdspll_d8" }; -static const char * const dpi1_mm_parents[] __initconst = { +static const char * const dpi1_mm_parents[] = { "clk26m_ck", "tvdpll_d2", "tvdpll_d4", @@ -417,85 +417,85 @@ static const char * const dpi1_mm_parents[] __initconst = { "tvdpll_d16" }; -static const char * const axi_mfg_in_parents[] __initconst = { +static const char * const axi_mfg_in_parents[] = { "clk26m_ck", "mainpll_d11", "univpll_d24", "mmpll380m" }; -static const char * const slow_mfg_parents[] __initconst = { +static const char * const slow_mfg_parents[] = { "clk26m_ck", "univpll_d12", "univpll_d24" }; -static const char * const aud1_parents[] __initconst = { +static const char * const aud1_parents[] = { "clk26m_ck", "apll1_ck" }; -static const char * const aud2_parents[] __initconst = { +static const char * const aud2_parents[] = { "clk26m_ck", "apll2_ck" }; -static const char * const aud_engen1_parents[] __initconst = { +static const char * const aud_engen1_parents[] = { "clk26m_ck", "rg_apll1_d2_en", "rg_apll1_d4_en", "rg_apll1_d8_en" }; -static const char * const aud_engen2_parents[] __initconst = { +static const char * const aud_engen2_parents[] = { "clk26m_ck", "rg_apll2_d2_en", "rg_apll2_d4_en", "rg_apll2_d8_en" }; -static const char * const i2c_parents[] __initconst = { +static const char * const i2c_parents[] = { "clk26m_ck", "univpll_d20", "univpll_d16", "univpll_d12" }; -static const char * const aud_i2s0_m_parents[] __initconst = { +static const char * const aud_i2s0_m_parents[] = { "rg_aud1", "rg_aud2" }; -static const char * const pwm_parents[] __initconst = { +static const char * const pwm_parents[] = { "clk26m_ck", "univpll_d12" }; -static const char * const spi_parents[] __initconst = { +static const char * const spi_parents[] = { "clk26m_ck", "univpll_d12", "univpll_d8", "univpll_d6" }; -static const char * const aud_spdifin_parents[] __initconst = { +static const char * const aud_spdifin_parents[] = { "clk26m_ck", "univpll_d2" }; -static const char * const uart2_parents[] __initconst = { +static const char * const uart2_parents[] = { "clk26m_ck", "univpll_d24" }; -static const char * const bsi_parents[] __initconst = { +static const char * const bsi_parents[] = { "clk26m_ck", "mainpll_d10", "mainpll_d12", "mainpll_d20" }; -static const char * const dbg_atclk_parents[] __initconst = { +static const char * const dbg_atclk_parents[] = { "clk_null", "clk26m_ck", "mainpll_d5", @@ -503,7 +503,7 @@ static const char * const dbg_atclk_parents[] __initconst = { "univpll_d5" }; -static const char * const csw_nfiecc_parents[] __initconst = { +static const char * const csw_nfiecc_parents[] = { "clk_null", "mainpll_d7", "mainpll_d6", @@ -511,7 +511,7 @@ static const char * const csw_nfiecc_parents[] __initconst = { "mainpll_d5" }; -static const char * const nfiecc_parents[] __initconst = { +static const char * const nfiecc_parents[] = { "clk_null", "nfi2x_pad_sel", "mainpll_d4", @@ -625,24 +625,24 @@ static struct mtk_composite top_muxes[] __initdata = { 0x07c, 13, 3), }; -static const char * const ifr_mux1_parents[] __initconst = { +static const char * const ifr_mux1_parents[] = { "clk26m_ck", "armpll", "univpll", "mainpll_d2" }; -static const char * const ifr_eth_25m_parents[] __initconst = { +static const char * const ifr_eth_25m_parents[] = { "eth_d2_ck", "rg_eth" }; -static const char * const ifr_i2c0_parents[] __initconst = { +static const char * const ifr_i2c0_parents[] = { "ahb_infra_d2", "rg_i2c" }; -static const struct mtk_composite ifr_muxes[] __initconst = { +static const struct mtk_composite ifr_muxes[] = { MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000, 2, 2), MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080, @@ -685,21 +685,6 @@ static const struct mtk_clk_divider top_adj_divs[] = { 0x0078, 0, 8), }; -#define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .div_reg = _reg, \ - .div_shift = _shift, \ - .div_width = _width, \ - .clk_divider_flags = _flag, \ -} - -static const struct mtk_clk_divider apmixed_adj_divs[] = { - DIV_ADJ_FLAG(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", - 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO), -}; - static const struct mtk_gate_regs top0_cg_regs = { .set_ofs = 0x50, .clr_ofs = 0x80, @@ -736,79 +721,31 @@ static const struct mtk_gate_regs top5_cg_regs = { .sta_ofs = 0x44, }; -#define GATE_TOP0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_TOP0_I(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } - -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_TOP2(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_TOP2_I(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } - -#define GATE_TOP3(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top3_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_TOP4_I(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top4_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } - -#define GATE_TOP5(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top5_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } - -static const struct mtk_gate top_clks[] __initconst = { +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_TOP0_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_TOP2_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_TOP3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_TOP4_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_TOP5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) + +static const struct mtk_gate top_clks[] = { /* TOP0 */ GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0), GATE_TOP0(CLK_TOP_CAM_MM, "cam_mm", "camtg_mm_sel", 1), @@ -921,145 +858,40 @@ static const struct mtk_gate top_clks[] __initconst = { GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8), }; -static void __init mtk_topckgen_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data = mtk_alloc_clk_data(MT8167_CLK_TOP_NR_CLK); - - mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), - clk_data); - mtk_clk_register_gates(NULL, node, top_clks, ARRAY_SIZE(top_clks), clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_composites(NULL, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt8167_clk_lock, clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt8167_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init); - -static void __init mtk_infracfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); - - mtk_clk_register_composites(NULL, ifr_muxes, - ARRAY_SIZE(ifr_muxes), base, - &mt8167_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8167-infracfg", mtk_infracfg_init); - -#define MT8167_PLL_FMAX (2500UL * MHZ) - -#define CON0_MT8167_RST_BAR BIT(27) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift, _div_table) { \ - .id = _id, \ - .name = _name, \ - .reg = _reg, \ - .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, \ - .flags = _flags, \ - .rst_bar_mask = CON0_MT8167_RST_BAR, \ - .fmax = MT8167_PLL_FMAX, \ - .pcwbits = _pcwbits, \ - .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, \ - .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, \ - .div_table = _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - NULL) - -static const struct mtk_pll_div_table mmpll_div_table[] = { - { .div = 0, .freq = MT8167_PLL_FMAX }, - { .div = 1, .freq = 1000000000 }, - { .div = 2, .freq = 604500000 }, - { .div = 3, .freq = 253500000 }, - { .div = 4, .freq = 126750000 }, - { } /* sentinel */ +static const struct mtk_clk_desc topck_desc = { + .clks = top_clks, + .num_clks = ARRAY_SIZE(top_clks), + .fixed_clks = fixed_clks, + .num_fixed_clks = ARRAY_SIZE(fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .composite_clks = top_muxes, + .num_composite_clks = ARRAY_SIZE(top_muxes), + .divider_clks = top_adj_divs, + .num_divider_clks = ARRAY_SIZE(top_adj_divs), + .clk_lock = &mt8167_clk_lock, }; -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, - 21, 0x0104, 24, 0, 0x0104, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, - HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, - HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, - 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), - PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, - 31, 0x0180, 1, 0x0194, 0x0184, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, - 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0, - 21, 0x01C4, 24, 0, 0x01C4, 0), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0, - 21, 0x01E4, 24, 0, 0x01E4, 0), +static const struct mtk_clk_desc infra_desc = { + .composite_clks = ifr_muxes, + .num_composite_clks = ARRAY_SIZE(ifr_muxes), + .clk_lock = &mt8167_clk_lock, }; -static void __init mtk_apmixedsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data = mtk_alloc_clk_data(MT8167_CLK_APMIXED_NR_CLK); - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs), - base, &mt8167_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static const struct of_device_id of_match_clk_mt8167[] = { + { .compatible = "mediatek,mt8167-topckgen", .data = &topck_desc }, + { .compatible = "mediatek,mt8167-infracfg", .data = &infra_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8167); -} -CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8167-apmixedsys", - mtk_apmixedsys_init); +static struct platform_driver clk_mt8167_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8167", + .of_match_table = of_match_clk_mt8167, + }, +}; +module_platform_driver(clk_mt8167_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c index a56c5845d07a..8c2aa8b0f39e 100644 --- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c @@ -9,8 +9,10 @@ #include <linux/of_address.h> #include <linux/module.h> #include <linux/platform_device.h> +#include "clk-fhctl.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" #define REGOFF_REF2USB 0x8 #define REGOFF_HDMI_REF 0x40 @@ -77,13 +79,67 @@ static const struct mtk_pll_data plls[] = { PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0), }; +enum fh_pll_id { + FH_ARMCA7PLL, + FH_ARMCA15PLL, + FH_MAINPLL, + FH_MPLL, + FH_MSDCPLL, + FH_MMPLL, + FH_VENCPLL, + FH_TVDPLL, + FH_VCODECPLL, + FH_LVDSPLL, + FH_MSDC2PLL, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data = { \ + .pll_id = _pllid, \ + .fh_id = _fhid, \ + .fh_ver = FHCTL_PLLFH_V1, \ + .fhx_offset = _offset, \ + .dds_mask = GENMASK(21, 0), \ + .slope0_value = 0x6003c97, \ + .slope1_value = 0x6003c97, \ + .sfstrx_en = BIT(2), \ + .frddsx_en = BIT(1), \ + .fhctlx_en = BIT(0), \ + .tgl_org = BIT(31), \ + .dvfs_tri = BIT(31), \ + .pcwchg = BIT(31), \ + .dt_val = 0x0, \ + .df_val = 0x9, \ + .updnlmt_shft = 16, \ + .msk_frddsx_dys = GENMASK(23, 20), \ + .msk_frddsx_dts = GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] = { + FH(CLK_APMIXED_ARMCA7PLL, FH_ARMCA7PLL, 0x38), + FH(CLK_APMIXED_ARMCA15PLL, FH_ARMCA15PLL, 0x4c), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60), + FH(CLK_APMIXED_MPLL, FH_MPLL, 0x74), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c), + FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4), + FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8), + FH(CLK_APMIXED_LVDSPLL, FH_LVDSPLL, 0xec), + FH(CLK_APMIXED_MSDCPLL2, FH_MSDC2PLL, 0x100), +}; + static const struct of_device_id of_match_clk_mt8173_apmixed[] = { { .compatible = "mediatek,mt8173-apmixedsys" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_apmixed); static int clk_mt8173_apmixed_probe(struct platform_device *pdev) { + const u8 *fhctl_node = "mediatek,mt8173-fhctl"; struct device_node *node = pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; void __iomem *base; @@ -98,7 +154,9 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev) if (IS_ERR_OR_NULL(clk_data)) return -ENOMEM; - r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_clk_data; @@ -124,7 +182,8 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev) unregister_ref2usb: mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return r; @@ -137,7 +196,8 @@ static int clk_mt8173_apmixed_remove(struct platform_device *pdev) of_clk_del_provider(node); mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); return 0; diff --git a/drivers/clk/mediatek/clk-mt8173-img.c b/drivers/clk/mediatek/clk-mt8173-img.c index 7b50ffb7a8a5..6db2b9ab2bc9 100644 --- a/drivers/clk/mediatek/clk-mt8173-img.c +++ b/drivers/clk/mediatek/clk-mt8173-img.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8173_imgsys[] = { { .compatible = "mediatek,mt8173-imgsys", .data = &img_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_imgsys); static struct platform_driver clk_mt8173_vdecsys_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/mediatek/clk-mt8173-infracfg.c index 729b3c408c7b..4ed5043076ec 100644 --- a/drivers/clk/mediatek/clk-mt8173-infracfg.c +++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c @@ -74,6 +74,7 @@ static const struct of_device_id of_match_clk_mt8173_infracfg[] = { { .compatible = "mediatek,mt8173-infracfg" }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_infracfg); static void clk_mt8173_infra_init_early(struct device_node *node) { diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/clk-mt8173-mm.c index 315430ad1581..18e466dbf610 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -25,25 +25,14 @@ static const struct mtk_gate_regs mm1_cg_regs = { .sta_ofs = 0x0110, }; -#define GATE_MM0(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm0_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) -#define GATE_MM1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &mm1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mt8173_mm_clks[] = { + GATE_DUMMY(CLK_DUMMY, "mm_dummy"), /* MM0 */ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), @@ -100,65 +89,26 @@ static const struct mtk_gate mt8173_mm_clks[] = { GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20), }; -struct clk_mt8173_mm_driver_data { - const struct mtk_gate *gates_clk; - int gates_num; +static const struct mtk_clk_desc mm_desc = { + .clks = mt8173_mm_clks, + .num_clks = ARRAY_SIZE(mt8173_mm_clks), }; -static const struct clk_mt8173_mm_driver_data mt8173_mmsys_driver_data = { - .gates_clk = mt8173_mm_clks, - .gates_num = ARRAY_SIZE(mt8173_mm_clks), +static const struct platform_device_id clk_mt8173_mm_id_table[] = { + { .name = "clk-mt8173-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } }; - -static int clk_mt8173_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - const struct clk_mt8173_mm_driver_data *data; - struct clk_hw_onecell_data *clk_data; - int ret; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - data = &mt8173_mmsys_driver_data; - - ret = mtk_clk_register_gates(&pdev->dev, node, data->gates_clk, - data->gates_num, clk_data); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - return ret; - - return 0; -} - -static int clk_mt8173_mm_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - const struct clk_mt8173_mm_driver_data *data = &mt8173_mmsys_driver_data; - - of_clk_del_provider(node); - mtk_clk_unregister_gates(data->gates_clk, data->gates_num, clk_data); - mtk_free_clk_data(clk_data); - - return 0; -} +MODULE_DEVICE_TABLE(platform, clk_mt8173_mm_id_table); static struct platform_driver clk_mt8173_mm_drv = { .driver = { .name = "clk-mt8173-mm", }, - .probe = clk_mt8173_mm_probe, - .remove = clk_mt8173_mm_remove, + .id_table = clk_mt8173_mm_id_table, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, }; - -builtin_platform_driver(clk_mt8173_mm_drv); +module_platform_driver(clk_mt8173_mm_drv); MODULE_DESCRIPTION("MediaTek MT8173 MultiMedia clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8173-pericfg.c b/drivers/clk/mediatek/clk-mt8173-pericfg.c index e87294b72c2c..bebda74d0f43 100644 --- a/drivers/clk/mediatek/clk-mt8173-pericfg.c +++ b/drivers/clk/mediatek/clk-mt8173-pericfg.c @@ -107,6 +107,7 @@ static const struct of_device_id of_match_clk_mt8173_pericfg[] = { { .compatible = "mediatek,mt8173-pericfg", .data = &peri_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_pericfg); static struct platform_driver clk_mt8173_pericfg_drv = { .driver = { diff --git a/drivers/clk/mediatek/clk-mt8173-topckgen.c b/drivers/clk/mediatek/clk-mt8173-topckgen.c index 257961528fe2..baa8fd6cb312 100644 --- a/drivers/clk/mediatek/clk-mt8173-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8173-topckgen.c @@ -638,6 +638,7 @@ static const struct of_device_id of_match_clk_mt8173_topckgen[] = { { .compatible = "mediatek,mt8173-topckgen", .data = &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_topckgen); static struct platform_driver clk_mt8173_topckgen_drv = { .driver = { diff --git a/drivers/clk/mediatek/clk-mt8173-vdecsys.c b/drivers/clk/mediatek/clk-mt8173-vdecsys.c index 5105b8e0969d..625ca0b09cc2 100644 --- a/drivers/clk/mediatek/clk-mt8173-vdecsys.c +++ b/drivers/clk/mediatek/clk-mt8173-vdecsys.c @@ -42,6 +42,7 @@ static const struct of_device_id of_match_clk_mt8173_vdecsys[] = { { .compatible = "mediatek,mt8173-vdecsys", .data = &vdec_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_vdecsys); static struct platform_driver clk_mt8173_vdecsys_drv = { .probe = mtk_clk_simple_probe, diff --git a/drivers/clk/mediatek/clk-mt8173-vencsys.c b/drivers/clk/mediatek/clk-mt8173-vencsys.c index ff4f1cb735de..87755dd1a337 100644 --- a/drivers/clk/mediatek/clk-mt8173-vencsys.c +++ b/drivers/clk/mediatek/clk-mt8173-vencsys.c @@ -49,6 +49,7 @@ static const struct of_device_id of_match_clk_mt8173_vencsys[] = { { .compatible = "mediatek,mt8173-vencltsys", .data = &venc_lt_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_vencsys); static struct platform_driver clk_mt8173_vencsys_drv = { .driver = { diff --git a/drivers/clk/mediatek/clk-mt8183-apmixedsys.c b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c new file mode 100644 index 000000000000..2b261c0e2b61 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8183-apmixedsys.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Weiyi Lu <weiyi.lu@mediatek.com> + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#include <dt-bindings/clock/mt8183-clk.h> +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" + +static const struct mtk_gate_regs apmixed_cg_regs = { + .set_ofs = 0x20, + .clr_ofs = 0x20, + .sta_ofs = 0x20, +}; + +#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ + _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) + +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) + +/* + * CRITICAL CLOCK: + * apmixed_appll26m is the toppest clock gate of all PLLs. + */ +static const struct mtk_gate apmixed_clks[] = { + /* AUDIO0 */ + GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", "f_f26m_ck", 4), + GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", + "f_f26m_ck", 5, CLK_IS_CRITICAL), + GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck", 6), + GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", "f_f26m_ck", 7), + GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", "f_f26m_ck", 8), + GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", "f_f26m_ck", 9), + GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck", 11), + GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", "f_f26m_ck", 13), + GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", "f_f26m_ck", 14), + GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck", 16), + GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", "f_f26m_ck", 17), +}; + +#define MT8183_PLL_FMAX (3800UL * MHZ) +#define MT8183_PLL_FMIN (1500UL * MHZ) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ + _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _pcw_chg_reg, _div_table) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8183_PLL_FMAX, \ + .fmin = MT8183_PLL_FMIN, \ + .pcwbits = _pcwbits, \ + .pcwibits = _pcwibits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, \ + .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + .div_table = _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ + _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _pcw_chg_reg) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ + _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, \ + _pcw_chg_reg, NULL) + +static const struct mtk_pll_div_table armpll_div_table[] = { + { .div = 0, .freq = MT8183_PLL_FMAX }, + { .div = 1, .freq = 1500 * MHZ }, + { .div = 2, .freq = 750 * MHZ }, + { .div = 3, .freq = 375 * MHZ }, + { .div = 4, .freq = 187500000 }, + { /* sentinel */ } +}; + +static const struct mtk_pll_div_table mfgpll_div_table[] = { + { .div = 0, .freq = MT8183_PLL_FMAX }, + { .div = 1, .freq = 1600 * MHZ }, + { .div = 2, .freq = 800 * MHZ }, + { .div = 3, .freq = 400 * MHZ }, + { .div = 4, .freq = 200 * MHZ }, + { /* sentinel */ } +}; + +static const struct mtk_pll_data plls[] = { + PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0, + HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, + 0x0204, 0, 0, armpll_div_table), + PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0, + HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, + 0x0214, 0, 0, armpll_div_table), + PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0, + HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, + 0x0294, 0, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, + 0x0224, 0, 0), + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0, + HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, + 0x0234, 0, 0), + PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0, + 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, + mfgpll_div_table), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0, + 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0, + 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0, + HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, + 0x0274, 0, 0), + PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0, + 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0, + 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), +}; + +static int clk_mt8183_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + if (ret) + goto unregister_plls; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_gates; + + return 0; + +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt8183_apmixed[] = { + { .compatible = "mediatek,mt8183-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_apmixed); + +static struct platform_driver clk_mt8183_apmixed_drv = { + .probe = clk_mt8183_apmixed_probe, + .driver = { + .name = "clk-mt8183-apmixed", + .of_match_table = of_match_clk_mt8183_apmixed, + }, +}; +builtin_platform_driver(clk_mt8183_apmixed_drv) +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c index 3f1630290b93..9938c6466e76 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -97,6 +97,7 @@ static const struct of_device_id of_match_clk_mt8183_audio[] = { { .compatible = "mediatek,mt8183-audiosys", .data = &audio_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_audio); static struct platform_driver clk_mt8183_audio_drv = { .probe = clk_mt8183_audio_probe, @@ -106,5 +107,5 @@ static struct platform_driver clk_mt8183_audio_drv = { .of_match_table = of_match_clk_mt8183_audio, }, }; - -builtin_platform_driver(clk_mt8183_audio_drv); +module_platform_driver(clk_mt8183_audio_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-cam.c b/drivers/clk/mediatek/clk-mt8183-cam.c index 6907b1a6a824..c0719624004f 100644 --- a/drivers/clk/mediatek/clk-mt8183-cam.c +++ b/drivers/clk/mediatek/clk-mt8183-cam.c @@ -47,6 +47,7 @@ static const struct of_device_id of_match_clk_mt8183_cam[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_cam); static struct platform_driver clk_mt8183_cam_drv = { .probe = mtk_clk_simple_probe, @@ -56,5 +57,5 @@ static struct platform_driver clk_mt8183_cam_drv = { .of_match_table = of_match_clk_mt8183_cam, }, }; - -builtin_platform_driver(clk_mt8183_cam_drv); +module_platform_driver(clk_mt8183_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-img.c b/drivers/clk/mediatek/clk-mt8183-img.c index 8d884425d79f..55fc80615724 100644 --- a/drivers/clk/mediatek/clk-mt8183-img.c +++ b/drivers/clk/mediatek/clk-mt8183-img.c @@ -47,6 +47,7 @@ static const struct of_device_id of_match_clk_mt8183_img[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_img); static struct platform_driver clk_mt8183_img_drv = { .probe = mtk_clk_simple_probe, @@ -56,5 +57,5 @@ static struct platform_driver clk_mt8183_img_drv = { .of_match_table = of_match_clk_mt8183_img, }, }; - -builtin_platform_driver(clk_mt8183_img_drv); +module_platform_driver(clk_mt8183_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu0.c b/drivers/clk/mediatek/clk-mt8183-ipu0.c index 953a8a33d048..59255eab6fe2 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu0.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu0.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_core0); static struct platform_driver clk_mt8183_ipu_core0_drv = { .probe = mtk_clk_simple_probe, @@ -49,5 +50,5 @@ static struct platform_driver clk_mt8183_ipu_core0_drv = { .of_match_table = of_match_clk_mt8183_ipu_core0, }, }; - -builtin_platform_driver(clk_mt8183_ipu_core0_drv); +module_platform_driver(clk_mt8183_ipu_core0_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu1.c b/drivers/clk/mediatek/clk-mt8183-ipu1.c index 221d12265974..c4baa052c809 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu1.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu1.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_core1); static struct platform_driver clk_mt8183_ipu_core1_drv = { .probe = mtk_clk_simple_probe, @@ -49,5 +50,5 @@ static struct platform_driver clk_mt8183_ipu_core1_drv = { .of_match_table = of_match_clk_mt8183_ipu_core1, }, }; - -builtin_platform_driver(clk_mt8183_ipu_core1_drv); +module_platform_driver(clk_mt8183_ipu_core1_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c index 8c4fd96df821..74866e9c50d7 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_adl.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_adl.c @@ -38,6 +38,7 @@ static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_adl); static struct platform_driver clk_mt8183_ipu_adl_drv = { .probe = mtk_clk_simple_probe, @@ -47,5 +48,5 @@ static struct platform_driver clk_mt8183_ipu_adl_drv = { .of_match_table = of_match_clk_mt8183_ipu_adl, }, }; - -builtin_platform_driver(clk_mt8183_ipu_adl_drv); +module_platform_driver(clk_mt8183_ipu_adl_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c index 14a4c3ff82a1..bd7303105357 100644 --- a/drivers/clk/mediatek/clk-mt8183-ipu_conn.c +++ b/drivers/clk/mediatek/clk-mt8183-ipu_conn.c @@ -107,6 +107,7 @@ static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_ipu_conn); static struct platform_driver clk_mt8183_ipu_conn_drv = { .probe = mtk_clk_simple_probe, @@ -116,5 +117,5 @@ static struct platform_driver clk_mt8183_ipu_conn_drv = { .of_match_table = of_match_clk_mt8183_ipu_conn, }, }; - -builtin_platform_driver(clk_mt8183_ipu_conn_drv); +module_platform_driver(clk_mt8183_ipu_conn_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c index 730c9ae5ea12..816ecf1191ee 100644 --- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8183_mfg[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_mfg); static struct platform_driver clk_mt8183_mfg_drv = { .probe = mtk_clk_simple_probe, @@ -48,5 +49,5 @@ static struct platform_driver clk_mt8183_mfg_drv = { .of_match_table = of_match_clk_mt8183_mfg, }, }; - -builtin_platform_driver(clk_mt8183_mfg_drv); +module_platform_driver(clk_mt8183_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/clk-mt8183-mm.c index 358031530913..2f99828bff1b 100644 --- a/drivers/clk/mediatek/clk-mt8183-mm.c +++ b/drivers/clk/mediatek/clk-mt8183-mm.c @@ -82,25 +82,24 @@ static const struct mtk_gate mm_clks[] = { GATE_MM1(CLK_MM_DBI_IF, "mm_dbi_if", "dpi0_sel", 13), }; -static int clk_mt8183_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - - mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct platform_device_id clk_mt8183_mm_id_table[] = { + { .name = "clk-mt8183-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8183_mm_id_table); static struct platform_driver clk_mt8183_mm_drv = { - .probe = clk_mt8183_mm_probe, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt8183-mm", }, + .id_table = clk_mt8183_mm_id_table, }; - -builtin_platform_driver(clk_mt8183_mm_drv); +module_platform_driver(clk_mt8183_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/clk-mt8183-vdec.c index c294e50b96b7..513b7956cbea 100644 --- a/drivers/clk/mediatek/clk-mt8183-vdec.c +++ b/drivers/clk/mediatek/clk-mt8183-vdec.c @@ -51,6 +51,7 @@ static const struct of_device_id of_match_clk_mt8183_vdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_vdec); static struct platform_driver clk_mt8183_vdec_drv = { .probe = mtk_clk_simple_probe, @@ -60,5 +61,5 @@ static struct platform_driver clk_mt8183_vdec_drv = { .of_match_table = of_match_clk_mt8183_vdec, }, }; - -builtin_platform_driver(clk_mt8183_vdec_drv); +module_platform_driver(clk_mt8183_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183-venc.c b/drivers/clk/mediatek/clk-mt8183-venc.c index 0051c5d92fc5..532f6e12a561 100644 --- a/drivers/clk/mediatek/clk-mt8183-venc.c +++ b/drivers/clk/mediatek/clk-mt8183-venc.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt8183_venc[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183_venc); static struct platform_driver clk_mt8183_venc_drv = { .probe = mtk_clk_simple_probe, @@ -52,5 +53,5 @@ static struct platform_driver clk_mt8183_venc_drv = { .of_match_table = of_match_clk_mt8183_venc, }, }; - -builtin_platform_driver(clk_mt8183_venc_drv); +module_platform_driver(clk_mt8183_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 722d913f0b4d..2336a1b69c09 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -14,7 +14,6 @@ #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-pll.h" #include <dt-bindings/clock/mt8183-clk.h> @@ -26,11 +25,14 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), }; -static const struct mtk_fixed_factor top_early_divs[] = { - FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), -}; - +/* + * To retain compatibility with older devicetrees, we keep CLK_TOP_CLK13M + * valid, but renamed from "clk13m" (defined as fixed clock in the new + * devicetrees) to "clk26m_d2", satisfying the older clock assignments. + * This means that on new devicetrees "clk26m_d2" is unused. + */ static const struct mtk_fixed_factor top_divs[] = { + FACTOR(CLK_TOP_CLK13M, "clk26m_d2", "clk26m", 1, 2), FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2), FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0), FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0), @@ -449,138 +451,97 @@ static const char * const aud_2_parents[] = { static const struct mtk_mux top_muxes[] = { /* CLK_CFG_0 */ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", - axi_parents, 0x40, - 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), + axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel", - mm_parents, 0x40, - 0x44, 0x48, 8, 3, 15, 0x004, 1), + mm_parents, 0x40, 0x44, 0x48, 8, 3, 15, 0x004, 1), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel", - img_parents, 0x40, - 0x44, 0x48, 16, 3, 23, 0x004, 2), + img_parents, 0x40, 0x44, 0x48, 16, 3, 23, 0x004, 2), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel", - cam_parents, 0x40, - 0x44, 0x48, 24, 4, 31, 0x004, 3), + cam_parents, 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 3), /* CLK_CFG_1 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel", - dsp_parents, 0x50, - 0x54, 0x58, 0, 4, 7, 0x004, 4), + dsp_parents, 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 4), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel", - dsp1_parents, 0x50, - 0x54, 0x58, 8, 4, 15, 0x004, 5), + dsp1_parents, 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 5), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel", - dsp2_parents, 0x50, - 0x54, 0x58, 16, 4, 23, 0x004, 6), + dsp2_parents, 0x50, 0x54, 0x58, 16, 4, 23, 0x004, 6), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel", - ipu_if_parents, 0x50, - 0x54, 0x58, 24, 4, 31, 0x004, 7), + ipu_if_parents, 0x50, 0x54, 0x58, 24, 4, 31, 0x004, 7), /* CLK_CFG_2 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel", - mfg_parents, 0x60, - 0x64, 0x68, 0, 2, 7, 0x004, 8), + mfg_parents, 0x60, 0x64, 0x68, 0, 2, 7, 0x004, 8), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel", - f52m_mfg_parents, 0x60, - 0x64, 0x68, 8, 2, 15, 0x004, 9), + f52m_mfg_parents, 0x60, 0x64, 0x68, 8, 2, 15, 0x004, 9), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel", - camtg_parents, 0x60, - 0x64, 0x68, 16, 3, 23, 0x004, 10), + camtg_parents, 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 10), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel", - camtg2_parents, 0x60, - 0x64, 0x68, 24, 3, 31, 0x004, 11), + camtg2_parents, 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 11), /* CLK_CFG_3 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel", - camtg3_parents, 0x70, - 0x74, 0x78, 0, 3, 7, 0x004, 12), + camtg3_parents, 0x70, 0x74, 0x78, 0, 3, 7, 0x004, 12), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel", - camtg4_parents, 0x70, - 0x74, 0x78, 8, 3, 15, 0x004, 13), + camtg4_parents, 0x70, 0x74, 0x78, 8, 3, 15, 0x004, 13), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel", - uart_parents, 0x70, - 0x74, 0x78, 16, 1, 23, 0x004, 14), + uart_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x004, 14), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel", - spi_parents, 0x70, - 0x74, 0x78, 24, 2, 31, 0x004, 15), + spi_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x004, 15), /* CLK_CFG_4 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel", - msdc50_hclk_parents, 0x80, - 0x84, 0x88, 0, 2, 7, 0x004, 16), + msdc50_hclk_parents, 0x80, 0x84, 0x88, 0, 2, 7, 0x004, 16), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", - msdc50_0_parents, 0x80, - 0x84, 0x88, 8, 3, 15, 0x004, 17), + msdc50_0_parents, 0x80, 0x84, 0x88, 8, 3, 15, 0x004, 17), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", - msdc30_1_parents, 0x80, - 0x84, 0x88, 16, 3, 23, 0x004, 18), + msdc30_1_parents, 0x80, 0x84, 0x88, 16, 3, 23, 0x004, 18), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", - msdc30_2_parents, 0x80, - 0x84, 0x88, 24, 3, 31, 0x004, 19), + msdc30_2_parents, 0x80, 0x84, 0x88, 24, 3, 31, 0x004, 19), /* CLK_CFG_5 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel", - audio_parents, 0x90, - 0x94, 0x98, 0, 2, 7, 0x004, 20), + audio_parents, 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 20), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", - aud_intbus_parents, 0x90, - 0x94, 0x98, 8, 2, 15, 0x004, 21), + aud_intbus_parents, 0x90, 0x94, 0x98, 8, 2, 15, 0x004, 21), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", - pmicspi_parents, 0x90, - 0x94, 0x98, 16, 2, 23, 0x004, 22), + pmicspi_parents, 0x90, 0x94, 0x98, 16, 2, 23, 0x004, 22), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel", - fpwrap_ulposc_parents, 0x90, - 0x94, 0x98, 24, 2, 31, 0x004, 23), + fpwrap_ulposc_parents, 0x90, 0x94, 0x98, 24, 2, 31, 0x004, 23), /* CLK_CFG_6 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel", - atb_parents, 0xa0, - 0xa4, 0xa8, 0, 2, 7, 0x004, 24), + atb_parents, 0xa0, 0xa4, 0xa8, 0, 2, 7, 0x004, 24), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel", - dpi0_parents, 0xa0, - 0xa4, 0xa8, 16, 4, 23, 0x004, 26), + dpi0_parents, 0xa0, 0xa4, 0xa8, 16, 4, 23, 0x004, 26), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel", - scam_parents, 0xa0, - 0xa4, 0xa8, 24, 1, 31, 0x004, 27), + scam_parents, 0xa0, 0xa4, 0xa8, 24, 1, 31, 0x004, 27), /* CLK_CFG_7 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel", - disppwm_parents, 0xb0, - 0xb4, 0xb8, 0, 3, 7, 0x004, 28), + disppwm_parents, 0xb0, 0xb4, 0xb8, 0, 3, 7, 0x004, 28), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel", - usb_top_parents, 0xb0, - 0xb4, 0xb8, 8, 2, 15, 0x004, 29), + usb_top_parents, 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x004, 29), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel", - ssusb_top_xhci_parents, 0xb0, - 0xb4, 0xb8, 16, 2, 23, 0x004, 30), + ssusb_top_xhci_parents, 0xb0, 0xb4, 0xb8, 16, 2, 23, 0x004, 30), MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel", - spm_parents, 0xb0, - 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), + spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL), /* CLK_CFG_8 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel", - i2c_parents, 0xc0, - 0xc4, 0xc8, 0, 2, 7, 0x008, 1), + i2c_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 1), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel", - scp_parents, 0xc0, - 0xc4, 0xc8, 8, 3, 15, 0x008, 2), + scp_parents, 0xc0, 0xc4, 0xc8, 8, 3, 15, 0x008, 2), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel", - seninf_parents, 0xc0, - 0xc4, 0xc8, 16, 2, 23, 0x008, 3), + seninf_parents, 0xc0, 0xc4, 0xc8, 16, 2, 23, 0x008, 3), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel", - dxcc_parents, 0xc0, - 0xc4, 0xc8, 24, 2, 31, 0x008, 4), + dxcc_parents, 0xc0, 0xc4, 0xc8, 24, 2, 31, 0x008, 4), /* CLK_CFG_9 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel", - aud_engen1_parents, 0xd0, - 0xd4, 0xd8, 0, 2, 7, 0x008, 5), + aud_engen1_parents, 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 5), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel", - aud_engen2_parents, 0xd0, - 0xd4, 0xd8, 8, 2, 15, 0x008, 6), + aud_engen2_parents, 0xd0, 0xd4, 0xd8, 8, 2, 15, 0x008, 6), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel", - faes_ufsfde_parents, 0xd0, - 0xd4, 0xd8, 16, 3, 23, 0x008, 7), + faes_ufsfde_parents, 0xd0, 0xd4, 0xd8, 16, 3, 23, 0x008, 7), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel", - fufs_parents, 0xd0, - 0xd4, 0xd8, 24, 2, 31, 0x008, 8), + fufs_parents, 0xd0, 0xd4, 0xd8, 24, 2, 31, 0x008, 8), /* CLK_CFG_10 */ MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel", - aud_1_parents, 0xe0, - 0xe4, 0xe8, 0, 1, 7, 0x008, 9), + aud_1_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x008, 9), MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel", - aud_2_parents, 0xe0, - 0xe4, 0xe8, 8, 1, 15, 0x008, 10), + aud_2_parents, 0xe0, 0xe4, 0xe8, 8, 1, 15, 0x008, 10), }; static const char * const apll_i2s0_parents[] = { @@ -644,30 +605,18 @@ static struct mtk_composite mcu_muxes[] = { }; static struct mtk_composite top_aud_comp[] = { - MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, - 0x320, 8, 1), - MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, - 0x320, 9, 1), - MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, - 0x320, 10, 1), - MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, - 0x320, 11, 1), - MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, - 0x320, 12, 1), - MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, - 0x328, 20, 1), - DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", - 0x320, 2, 0x324, 8, 0), - DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", - 0x320, 3, 0x324, 8, 8), - DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", - 0x320, 4, 0x324, 8, 16), - DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", - 0x320, 5, 0x324, 8, 24), - DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", - 0x320, 6, 0x328, 8, 0), - DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", - 0x320, 7, 0x328, 8, 8), + MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, 0x320, 8, 1), + MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, 0x320, 9, 1), + MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, 0x320, 10, 1), + MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, 0x320, 11, 1), + MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, 0x320, 12, 1), + MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, 0x328, 20, 1), + DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 0x320, 2, 0x324, 8, 0), + DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 0x320, 3, 0x324, 8, 8), + DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel", 0x320, 4, 0x324, 8, 16), + DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel", 0x320, 5, 0x324, 8, 24), + DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel", 0x320, 6, 0x328, 8, 0), + DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 7, 0x328, 8, 8), }; static const struct mtk_gate_regs top_cg_regs = { @@ -728,203 +677,106 @@ static const struct mtk_gate_regs infra3_cg_regs = { static const struct mtk_gate infra_clks[] = { /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", - "axi_sel", 0), - GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", - "axi_sel", 1), - GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", - "axi_sel", 2), - GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", - "axi_sel", 3), - GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", - "scp_sel", 4), - GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", - "f_f26m_ck", 5), - GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", - "axi_sel", 6), - GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", - "axi_sel", 8), - GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", - "axi_sel", 9), - GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", - "axi_sel", 10), - GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", - "i2c_sel", 11), - GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", - "i2c_sel", 12), - GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", - "i2c_sel", 13), - GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", - "i2c_sel", 14), - GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", - "axi_sel", 15), - GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", - "i2c_sel", 16), - GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", - "i2c_sel", 17), - GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", - "i2c_sel", 18), - GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", - "i2c_sel", 19), - GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", - "i2c_sel", 21), - GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", - "uart_sel", 22), - GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", - "uart_sel", 23), - GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", - "uart_sel", 24), - GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", - "uart_sel", 25), - GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", - "axi_sel", 27), - GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", - "axi_sel", 28), - GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", - "axi_sel", 31), + GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0), + GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "axi_sel", 1), + GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "axi_sel", 2), + GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "axi_sel", 3), + GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp", "scp_sel", 4), + GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "f_f26m_ck", 5), + GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), + GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb", "axi_sel", 8), + GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9), + GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), + GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), + GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1", "i2c_sel", 12), + GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), + GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), + GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15), + GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "i2c_sel", 16), + GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "i2c_sel", 17), + GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "i2c_sel", 18), + GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "i2c_sel", 19), + GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "i2c_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), + GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), + GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), + GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), + GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), + GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc", "axi_sel", 28), + GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", - "spi_sel", 1), - GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", - "msdc50_hclk_sel", 2), - GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", - "axi_sel", 4), - GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", - "axi_sel", 5), - GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", - "msdc50_0_sel", 6), - GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", - "f_f26m_ck", 7), - GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", - "axi_sel", 8), - GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", - "axi_sel", 9), - GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", - "f_f26m_ck", 10), - GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", - "axi_sel", 11), - GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", - "axi_sel", 12), - GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", - "axi_sel", 13), - GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", - "f_f26m_ck", 14), - GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", - "msdc30_1_sel", 16), - GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", - "msdc30_2_sel", 17), - GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", - "axi_sel", 18), - GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", - "axi_sel", 19), - GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", - "axi_sel", 20), - GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", - "axi_sel", 23), - GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", - "axi_sel", 24), - GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", - "axi_sel", 25), - GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", - "axi_sel", 26), - GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", - "dxcc_sel", 27), - GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", - "dxcc_sel", 28), - GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", - "axi_sel", 30), - GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", - "f_f26m_ck", 31), + GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), + GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_hclk_sel", 2), + GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "axi_sel", 4), + GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "axi_sel", 5), + GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck", "msdc50_0_sel", 6), + GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc", "f_f26m_ck", 7), + GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), + GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), + GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "f_f26m_ck", 10), + GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), + GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), + GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), + GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "f_f26m_ck", 14), + GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck", "msdc30_1_sel", 16), + GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck", "msdc30_2_sel", 17), + GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma", "axi_sel", 18), + GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu", "axi_sel", 19), + GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20), + GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), + GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), + GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), + GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), + GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), + GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), + GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk", "axi_sel", 30), + GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "f_f26m_ck", 31), /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", - "f_f26m_ck", 0), - GATE_INFRA2(CLK_INFRA_USB, "infra_usb", - "usb_top_sel", 1), - GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", - "axi_sel", 2), - GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", - "axi_sel", 3), - GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", - "f_f26m_ck", 4), - GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", - "spi_sel", 6), - GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", - "i2c_sel", 7), - GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", - "f_f26m_ck", 8), - GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", - "spi_sel", 9), - GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", - "spi_sel", 10), - GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", - "ssusb_top_xhci_sel", 11), - GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", - "fufs_sel", 12), - GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", - "fufs_sel", 13), - GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", - "axi_sel", 14), - GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", - "axi_sel", 16), - GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", - "i2c_sel", 18), - GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", - "i2c_sel", 19), - GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", - "i2c_sel", 20), - GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", - "i2c_sel", 21), - GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", - "i2c_sel", 22), - GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", - "i2c_sel", 23), - GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", - "i2c_sel", 24), - GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", - "spi_sel", 25), - GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", - "spi_sel", 26), - GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", - "axi_sel", 27), - GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", - "fufs_sel", 28), - GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", - "faes_ufsfde_sel", 29), - GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", - "fufs_sel", 30), + GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "f_f26m_ck", 0), + GATE_INFRA2(CLK_INFRA_USB, "infra_usb", "usb_top_sel", 1), + GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm", "axi_sel", 2), + GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk", "axi_sel", 3), + GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk", "f_f26m_ck", 4), + GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), + GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), + GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share", "f_f26m_ck", 8), + GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), + GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), + GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck", "ssusb_top_xhci_sel", 11), + GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "fufs_sel", 12), + GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck", "fufs_sel", 13), + GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk", "axi_sel", 14), + GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), + GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), + GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), + GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), + GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), + GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), + GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), + GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), + GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), + GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), + GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma", "axi_sel", 27), + GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "fufs_sel", 28), + GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "faes_ufsfde_sel", 29), + GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "fufs_sel", 30), /* INFRA3 */ - GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", - "msdc50_0_sel", 0), - GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", - "msdc50_0_sel", 1), - GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", - "msdc50_0_sel", 2), - GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", - "axi_sel", 5), - GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", - "i2c_sel", 6), - GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", - "msdc50_hclk_sel", 7), - GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", - "msdc50_hclk_sel", 8), - GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", - "axi_sel", 16), - GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", - "axi_sel", 17), - GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", - "axi_sel", 18), - GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", - "axi_sel", 19), - GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", - "f_f26m_ck", 20), - GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", - "axi_sel", 21), - GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", - "i2c_sel", 22), - GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", - "i2c_sel", 23), - GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", - "msdc50_0_sel", 24), + GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), + GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), + GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), + GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), + GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), + GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_hclk_sel", 7), + GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_hclk_sel", 8), + GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), + GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), + GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), + GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), + GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "f_f26m_ck", 20), + GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk", "axi_sel", 21), + GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), + GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), + GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), }; static const struct mtk_gate_regs peri_cg_regs = { @@ -941,140 +793,6 @@ static const struct mtk_gate peri_clks[] = { GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31), }; -static const struct mtk_gate_regs apmixed_cg_regs = { - .set_ofs = 0x20, - .clr_ofs = 0x20, - .sta_ofs = 0x20, -}; - -#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ - GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \ - _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags) - -#define GATE_APMIXED(_id, _name, _parent, _shift) \ - GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0) - -/* - * CRITICAL CLOCK: - * apmixed_appll26m is the toppest clock gate of all PLLs. - */ -static const struct mtk_gate apmixed_clks[] = { - /* AUDIO0 */ - GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m", - "f_f26m_ck", 4), - GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m", - "f_f26m_ck", 5, CLK_IS_CRITICAL), - GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", - "f_f26m_ck", 6), - GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m", - "f_f26m_ck", 7), - GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m", - "f_f26m_ck", 8), - GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m", - "f_f26m_ck", 9), - GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", - "f_f26m_ck", 11), - GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m", - "f_f26m_ck", 13), - GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", - "f_f26m_ck", 14), - GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", - "f_f26m_ck", 16), - GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m", - "f_f26m_ck", 17), -}; - -#define MT8183_PLL_FMAX (3800UL * MHZ) -#define MT8183_PLL_FMIN (1500UL * MHZ) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ - _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, \ - _pcw_chg_reg, _div_table) { \ - .id = _id, \ - .name = _name, \ - .reg = _reg, \ - .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, \ - .flags = _flags, \ - .rst_bar_mask = _rst_bar_mask, \ - .fmax = MT8183_PLL_FMAX, \ - .fmin = MT8183_PLL_FMIN, \ - .pcwbits = _pcwbits, \ - .pcwibits = _pcwibits, \ - .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, \ - .tuner_en_reg = _tuner_en_reg, \ - .tuner_en_bit = _tuner_en_bit, \ - .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, \ - .pcw_chg_reg = _pcw_chg_reg, \ - .div_table = _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ - _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, \ - _pcw_chg_reg) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ - _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, \ - _pcw_chg_reg, NULL) - -static const struct mtk_pll_div_table armpll_div_table[] = { - { .div = 0, .freq = MT8183_PLL_FMAX }, - { .div = 1, .freq = 1500 * MHZ }, - { .div = 2, .freq = 750 * MHZ }, - { .div = 3, .freq = 375 * MHZ }, - { .div = 4, .freq = 187500000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table mfgpll_div_table[] = { - { .div = 0, .freq = MT8183_PLL_FMAX }, - { .div = 1, .freq = 1600 * MHZ }, - { .div = 2, .freq = 800 * MHZ }, - { .div = 3, .freq = 400 * MHZ }, - { .div = 4, .freq = 200 * MHZ }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] = { - PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0, - HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0, - 0x0204, 0, 0, armpll_div_table), - PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0, - HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0, - 0x0214, 0, 0, armpll_div_table), - PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0, - HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0, - 0x0294, 0, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0, - 0x0224, 0, 0), - PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0, - HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0, - 0x0234, 0, 0), - PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0, - 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0, - mfgpll_div_table), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0, - 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0, - 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0, - HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0, - 0x0274, 0, 0), - PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0, - 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0, - 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), -}; - static u16 infra_rst_ofs[] = { INFRA_RST0_SET_OFFSET, INFRA_RST1_SET_OFFSET, @@ -1088,41 +806,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), }; -static int clk_mt8183_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static struct clk_hw_onecell_data *top_clk_data; - -static void clk_mt8183_top_init_early(struct device_node *node) -{ - int i; - - top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - - for (i = 0; i < CLK_TOP_NR_CLK; i++) - top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - - of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); -} - -CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", - clk_mt8183_top_init_early); - /* Register mux notifier for MFG mux */ static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) { @@ -1145,137 +828,55 @@ static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } -static int clk_mt8183_top_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct device_node *node = pdev->dev.of_node; - int ret; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); - - mtk_clk_register_muxes(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), node, - &mt8183_clk_lock, top_clk_data); - - mtk_clk_register_composites(&pdev->dev, top_aud_comp, - ARRAY_SIZE(top_aud_comp), base, - &mt8183_clk_lock, top_clk_data); - - mtk_clk_register_gates(&pdev->dev, node, top_clks, - ARRAY_SIZE(top_clks), top_clk_data); - - ret = clk_mt8183_reg_mfg_mux_notifier(&pdev->dev, - top_clk_data->hws[CLK_TOP_MUX_MFG]->clk); - if (ret) - return ret; - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - top_clk_data); -} - -static int clk_mt8183_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - void __iomem *base; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); - - mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - &mt8183_clk_lock, clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - -static const struct of_device_id of_match_clk_mt8183[] = { - { - .compatible = "mediatek,mt8183-apmixedsys", - .data = clk_mt8183_apmixed_probe, - }, { - .compatible = "mediatek,mt8183-topckgen", - .data = clk_mt8183_top_probe, - }, { - .compatible = "mediatek,mt8183-mcucfg", - .data = clk_mt8183_mcu_probe, - }, { - /* sentinel */ - } -}; - -static int clk_mt8183_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int r; - - clk_probe = of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r = clk_probe(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static const struct mtk_clk_desc infra_desc = { .clks = infra_clks, .num_clks = ARRAY_SIZE(infra_clks), .rst_desc = &clk_rst_desc, }; +static const struct mtk_clk_desc mcu_desc = { + .composite_clks = mcu_muxes, + .num_composite_clks = ARRAY_SIZE(mcu_muxes), + .clk_lock = &mt8183_clk_lock, +}; + static const struct mtk_clk_desc peri_desc = { .clks = peri_clks, .num_clks = ARRAY_SIZE(peri_clks), }; -static const struct of_device_id of_match_clk_mt8183_simple[] = { +static const struct mtk_clk_desc topck_desc = { + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .mux_clks = top_muxes, + .num_mux_clks = ARRAY_SIZE(top_muxes), + .composite_clks = top_aud_comp, + .num_composite_clks = ARRAY_SIZE(top_aud_comp), + .clks = top_clks, + .num_clks = ARRAY_SIZE(top_clks), + .clk_lock = &mt8183_clk_lock, + .clk_notifier_func = clk_mt8183_reg_mfg_mux_notifier, + .mfg_clk_idx = CLK_TOP_MUX_MFG, +}; + +static const struct of_device_id of_match_clk_mt8183[] = { { .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt8183-mcucfg", .data = &mcu_desc }, { .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, }, + { .compatible = "mediatek,mt8183-topckgen", .data = &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8183); -static struct platform_driver clk_mt8183_simple_drv = { +static struct platform_driver clk_mt8183_drv = { .probe = mtk_clk_simple_probe, .remove = mtk_clk_simple_remove, .driver = { - .name = "clk-mt8183-simple", - .of_match_table = of_match_clk_mt8183_simple, - }, -}; - -static struct platform_driver clk_mt8183_drv = { - .probe = clk_mt8183_probe, - .driver = { .name = "clk-mt8183", .of_match_table = of_match_clk_mt8183, }, }; - -static int __init clk_mt8183_init(void) -{ - int ret = platform_driver_register(&clk_mt8183_drv); - - if (ret) - return ret; - return platform_driver_register(&clk_mt8183_simple_drv); -} - -arch_initcall(clk_mt8183_init); +module_platform_driver(clk_mt8183_drv) +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c index 1d673c6278a9..da7950d51c64 100644 --- a/drivers/clk/mediatek/clk-mt8186-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8186-apmixedsys.c @@ -7,6 +7,7 @@ #include <linux/platform_device.h> #include <dt-bindings/clock/mt8186-clk.h> +#include "clk-fhctl.h" #include "clk-mtk.h" #include "clk-pll.h" #include "clk-pllfh.h" @@ -98,6 +99,7 @@ enum fh_pll_id { .data = { \ .pll_id = _pllid, \ .fh_id = _fhid, \ + .fh_ver = FHCTL_PLLFH_V2, \ .fhx_offset = _offset, \ .dds_mask = GENMASK(21, 0), \ .slope0_value = 0x6003c97, \ @@ -134,6 +136,7 @@ static const struct of_device_id of_match_clk_mt8186_apmixed[] = { { .compatible = "mediatek,mt8186-apmixedsys", }, {} }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_apmixed); static int clk_mt8186_apmixed_probe(struct platform_device *pdev) { @@ -190,4 +193,5 @@ static struct platform_driver clk_mt8186_apmixed_drv = { .of_match_table = of_match_clk_mt8186_apmixed, }, }; -builtin_platform_driver(clk_mt8186_apmixed_drv); +module_platform_driver(clk_mt8186_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-cam.c b/drivers/clk/mediatek/clk-mt8186-cam.c index 9ec345a2ce66..656d9e6f3ee2 100644 --- a/drivers/clk/mediatek/clk-mt8186-cam.c +++ b/drivers/clk/mediatek/clk-mt8186-cam.c @@ -78,6 +78,7 @@ static const struct of_device_id of_match_clk_mt8186_cam[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_cam); static struct platform_driver clk_mt8186_cam_drv = { .probe = mtk_clk_simple_probe, @@ -87,4 +88,5 @@ static struct platform_driver clk_mt8186_cam_drv = { .of_match_table = of_match_clk_mt8186_cam, }, }; -builtin_platform_driver(clk_mt8186_cam_drv); +module_platform_driver(clk_mt8186_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-img.c b/drivers/clk/mediatek/clk-mt8186-img.c index 08a625475aee..754b27f03817 100644 --- a/drivers/clk/mediatek/clk-mt8186-img.c +++ b/drivers/clk/mediatek/clk-mt8186-img.c @@ -56,6 +56,7 @@ static const struct of_device_id of_match_clk_mt8186_img[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_img); static struct platform_driver clk_mt8186_img_drv = { .probe = mtk_clk_simple_probe, @@ -65,4 +66,5 @@ static struct platform_driver clk_mt8186_img_drv = { .of_match_table = of_match_clk_mt8186_img, }, }; -builtin_platform_driver(clk_mt8186_img_drv); +module_platform_driver(clk_mt8186_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c index 47f2e480a05e..7619c357b150 100644 --- a/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8186-imp_iic_wrap.c @@ -55,6 +55,7 @@ static const struct of_device_id of_match_clk_mt8186_imp_iic_wrap[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_imp_iic_wrap); static struct platform_driver clk_mt8186_imp_iic_wrap_drv = { .probe = mtk_clk_simple_probe, @@ -64,4 +65,5 @@ static struct platform_driver clk_mt8186_imp_iic_wrap_drv = { .of_match_table = of_match_clk_mt8186_imp_iic_wrap, }, }; -builtin_platform_driver(clk_mt8186_imp_iic_wrap_drv); +module_platform_driver(clk_mt8186_imp_iic_wrap_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-infra_ao.c b/drivers/clk/mediatek/clk-mt8186-infra_ao.c index df2a6bd1aefa..a907a5def5b8 100644 --- a/drivers/clk/mediatek/clk-mt8186-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8186-infra_ao.c @@ -227,6 +227,7 @@ static const struct of_device_id of_match_clk_mt8186_infra_ao[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_infra_ao); static struct platform_driver clk_mt8186_infra_ao_drv = { .probe = mtk_clk_simple_probe, @@ -236,4 +237,5 @@ static struct platform_driver clk_mt8186_infra_ao_drv = { .of_match_table = of_match_clk_mt8186_infra_ao, }, }; -builtin_platform_driver(clk_mt8186_infra_ao_drv); +module_platform_driver(clk_mt8186_infra_ao_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-ipe.c b/drivers/clk/mediatek/clk-mt8186-ipe.c index 8fca148effa6..50e340035aa7 100644 --- a/drivers/clk/mediatek/clk-mt8186-ipe.c +++ b/drivers/clk/mediatek/clk-mt8186-ipe.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt8186_ipe[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_ipe); static struct platform_driver clk_mt8186_ipe_drv = { .probe = mtk_clk_simple_probe, @@ -52,4 +53,5 @@ static struct platform_driver clk_mt8186_ipe_drv = { .of_match_table = of_match_clk_mt8186_ipe, }, }; -builtin_platform_driver(clk_mt8186_ipe_drv); +module_platform_driver(clk_mt8186_ipe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mcu.c b/drivers/clk/mediatek/clk-mt8186-mcu.c index e52a2d986c99..d1640e4dc2ad 100644 --- a/drivers/clk/mediatek/clk-mt8186-mcu.c +++ b/drivers/clk/mediatek/clk-mt8186-mcu.c @@ -43,67 +43,26 @@ static struct mtk_composite mcu_muxes[] = { MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2), }; -static const struct of_device_id of_match_clk_mt8186_mcu[] = { - { .compatible = "mediatek,mt8186-mcusys", }, - {} +static const struct mtk_clk_desc mcu_desc = { + .composite_clks = mcu_muxes, + .num_composite_clks = ARRAY_SIZE(mcu_muxes), }; -static int clk_mt8186_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); - if (!clk_data) - return -ENOMEM; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - r = PTR_ERR(base); - goto free_mcu_data; - } - - r = mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - NULL, clk_data); - if (r) - goto free_mcu_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_composite_muxes; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_composite_muxes: - mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data); -free_mcu_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8186_mcu_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - struct device_node *node = pdev->dev.of_node; - - of_clk_del_provider(node); - mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data); - mtk_free_clk_data(clk_data); - - return 0; -} +static const struct of_device_id of_match_clk_mt8186_mcu[] = { + { .compatible = "mediatek,mt8186-mcusys", .data = &mcu_desc }, + { /* sentinel */} +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mcu); static struct platform_driver clk_mt8186_mcu_drv = { - .probe = clk_mt8186_mcu_probe, - .remove = clk_mt8186_mcu_remove, .driver = { .name = "clk-mt8186-mcu", .of_match_table = of_match_clk_mt8186_mcu, }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, }; -builtin_platform_driver(clk_mt8186_mcu_drv); +module_platform_driver(clk_mt8186_mcu_drv); + +MODULE_DESCRIPTION("MediaTek MT8186 mcusys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mdp.c b/drivers/clk/mediatek/clk-mt8186-mdp.c index 05174088ef20..e1d19007e375 100644 --- a/drivers/clk/mediatek/clk-mt8186-mdp.c +++ b/drivers/clk/mediatek/clk-mt8186-mdp.c @@ -68,6 +68,7 @@ static const struct of_device_id of_match_clk_mt8186_mdp[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mdp); static struct platform_driver clk_mt8186_mdp_drv = { .probe = mtk_clk_simple_probe, @@ -77,4 +78,5 @@ static struct platform_driver clk_mt8186_mdp_drv = { .of_match_table = of_match_clk_mt8186_mdp, }, }; -builtin_platform_driver(clk_mt8186_mdp_drv); +module_platform_driver(clk_mt8186_mdp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mfg.c b/drivers/clk/mediatek/clk-mt8186-mfg.c index 0142d741053a..aeb098b54585 100644 --- a/drivers/clk/mediatek/clk-mt8186-mfg.c +++ b/drivers/clk/mediatek/clk-mt8186-mfg.c @@ -37,6 +37,7 @@ static const struct of_device_id of_match_clk_mt8186_mfg[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_mfg); static struct platform_driver clk_mt8186_mfg_drv = { .probe = mtk_clk_simple_probe, @@ -46,4 +47,5 @@ static struct platform_driver clk_mt8186_mfg_drv = { .of_match_table = of_match_clk_mt8186_mfg, }, }; -builtin_platform_driver(clk_mt8186_mfg_drv); +module_platform_driver(clk_mt8186_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-mm.c b/drivers/clk/mediatek/clk-mt8186-mm.c index 0b72607777fa..fc3bb6d1f714 100644 --- a/drivers/clk/mediatek/clk-mt8186-mm.c +++ b/drivers/clk/mediatek/clk-mt8186-mm.c @@ -58,55 +58,24 @@ static const struct mtk_gate mm_clks[] = { GATE_MM1(CLK_MM_DISP_26M, "mm_disp_26m_ck", "top_disp", 10), }; -static int clk_mt8186_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - if (r) - goto free_mm_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data); -free_mm_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8186_mm_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; - return 0; -} +static const struct platform_device_id clk_mt8186_mm_id_table[] = { + { .name = "clk-mt8186-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8186_mm_id_table); static struct platform_driver clk_mt8186_mm_drv = { - .probe = clk_mt8186_mm_probe, - .remove = clk_mt8186_mm_remove, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt8186-mm", }, + .id_table = clk_mt8186_mm_id_table, }; -builtin_platform_driver(clk_mt8186_mm_drv); +module_platform_driver(clk_mt8186_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/mediatek/clk-mt8186-topckgen.c index c6786c8b315f..1a0340a20beb 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -721,6 +721,7 @@ static const struct of_device_id of_match_clk_mt8186_topck[] = { { .compatible = "mediatek,mt8186-topckgen", .data = &topck_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_topck); static struct platform_driver clk_mt8186_topck_drv = { .probe = mtk_clk_simple_probe, @@ -730,4 +731,5 @@ static struct platform_driver clk_mt8186_topck_drv = { .of_match_table = of_match_clk_mt8186_topck, }, }; -builtin_platform_driver(clk_mt8186_topck_drv); +module_platform_driver(clk_mt8186_topck_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-vdec.c b/drivers/clk/mediatek/clk-mt8186-vdec.c index 5ad7e1ae0bac..9bf3b8632870 100644 --- a/drivers/clk/mediatek/clk-mt8186-vdec.c +++ b/drivers/clk/mediatek/clk-mt8186-vdec.c @@ -76,6 +76,7 @@ static const struct of_device_id of_match_clk_mt8186_vdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_vdec); static struct platform_driver clk_mt8186_vdec_drv = { .probe = mtk_clk_simple_probe, @@ -85,4 +86,5 @@ static struct platform_driver clk_mt8186_vdec_drv = { .of_match_table = of_match_clk_mt8186_vdec, }, }; -builtin_platform_driver(clk_mt8186_vdec_drv); +module_platform_driver(clk_mt8186_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-venc.c b/drivers/clk/mediatek/clk-mt8186-venc.c index f5519f794c45..0c1bc94e84cf 100644 --- a/drivers/clk/mediatek/clk-mt8186-venc.c +++ b/drivers/clk/mediatek/clk-mt8186-venc.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8186_venc[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_venc); static struct platform_driver clk_mt8186_venc_drv = { .probe = mtk_clk_simple_probe, @@ -48,4 +49,5 @@ static struct platform_driver clk_mt8186_venc_drv = { .of_match_table = of_match_clk_mt8186_venc, }, }; -builtin_platform_driver(clk_mt8186_venc_drv); +module_platform_driver(clk_mt8186_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8186-wpe.c b/drivers/clk/mediatek/clk-mt8186-wpe.c index 8db3e9178a1e..c4727b1cb64d 100644 --- a/drivers/clk/mediatek/clk-mt8186-wpe.c +++ b/drivers/clk/mediatek/clk-mt8186-wpe.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8186_wpe[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_wpe); static struct platform_driver clk_mt8186_wpe_drv = { .probe = mtk_clk_simple_probe, @@ -48,4 +49,5 @@ static struct platform_driver clk_mt8186_wpe_drv = { .of_match_table = of_match_clk_mt8186_wpe, }, }; -builtin_platform_driver(clk_mt8186_wpe_drv); +module_platform_driver(clk_mt8186_wpe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c new file mode 100644 index 000000000000..808f2ad3b7ee --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-adsp_audio26m.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs adsp_audio26m_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x80, + .sta_ofs = 0x80, +}; + +#define GATE_ADSP_FLAGS(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &adsp_audio26m_cg_regs, _shift, \ + &mtk_clk_gate_ops_no_setclr) + +static const struct mtk_gate adsp_audio26m_clks[] = { + GATE_ADSP_FLAGS(CLK_AUDIODSP_AUDIO26M, "audiodsp_audio26m", "clk26m", 3), +}; + +static const struct mtk_clk_desc adsp_audio26m_desc = { + .clks = adsp_audio26m_clks, + .num_clks = ARRAY_SIZE(adsp_audio26m_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_adsp_audio26m[] = { + { .compatible = "mediatek,mt8188-adsp-audio26m", .data = &adsp_audio26m_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_adsp_audio26m); + +static struct platform_driver clk_mt8188_adsp_audio26m_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-adsp_audio26m", + .of_match_table = of_match_clk_mt8188_adsp_audio26m, + }, +}; +module_platform_driver(clk_mt8188_adsp_audio26m_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c new file mode 100644 index 000000000000..9d21da2d9aa7 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" + +static const struct mtk_gate_regs apmixed_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x8, + .sta_ofs = 0x8, +}; + +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +static const struct mtk_gate apmixed_clks[] = { + GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M_EN, "pll_ssusb26m_en", "clk26m", 1), +}; + +#define MT8188_PLL_FMAX (3800UL * MHZ) +#define MT8188_PLL_FMIN (1500UL * MHZ) +#define MT8188_INTEGER_BITS 8 + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, _pcw_chg_reg, \ + _en_reg, _pll_en_bit) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8188_PLL_FMAX, \ + .fmin = MT8188_PLL_FMIN, \ + .pcwbits = _pcwbits, \ + .pcwibits = MT8188_INTEGER_BITS, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, \ + .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + .en_reg = _en_reg, \ + .pll_en_bit = _pll_en_bit, \ + } + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0, + 0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0, + 0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9), + PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0, + 0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9), + PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0, + 0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548, 0, 0, 0, 9), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x0460, 24, 0, 0, 0, 0x0460, 0, 0, 0, 9), + PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0, + 0, 0, 22, 0x0558, 24, 0, 0, 0, 0x0558, 0, 0, 0, 9), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x0508, 24, 0, 0, 0, 0x0508, 0, 0, 0, 9), + PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0, + 0, 0, 22, 0x0430, 24, 0, 0, 0, 0x0430, 0, 0, 0, 9), + PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0, + 0, 0, 32, 0x0308, 24, 0x0034, 0x0000, 12, 0x030C, 0, 0, 0, 9), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0, + 0, 0, 32, 0x031C, 24, 0x0038, 0x0000, 13, 0x0320, 0, 0, 0, 9), + PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0, + 0, 0, 32, 0x0330, 24, 0x003C, 0x0000, 14, 0x0334, 0, 0, 0, 9), + PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0, + 0, 0, 32, 0x0408, 24, 0x0040, 0x0000, 15, 0x040C, 0, 0, 0, 9), + PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0, + 0, 0, 32, 0x041C, 24, 0x0044, 0x0000, 16, 0x0420, 0, 0, 0, 9), + PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x034C, 0, + 0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9), +}; + +static const struct of_device_id of_match_clk_mt8188_apmixed[] = { + { .compatible = "mediatek,mt8188-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_apmixed); + +static int clk_mt8188_apmixed_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (r) + goto free_apmixed_data; + + r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + if (r) + goto unregister_plls; + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_gates; + + platform_set_drvdata(pdev, clk_data); + + return 0; + +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); +free_apmixed_data: + mtk_free_clk_data(clk_data); + return r; +} + +static int clk_mt8188_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static struct platform_driver clk_mt8188_apmixed_drv = { + .probe = clk_mt8188_apmixed_probe, + .remove = clk_mt8188_apmixed_remove, + .driver = { + .name = "clk-mt8188-apmixed", + .of_match_table = of_match_clk_mt8188_apmixed, + }, +}; +module_platform_driver(clk_mt8188_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-cam.c b/drivers/clk/mediatek/clk-mt8188-cam.c new file mode 100644 index 000000000000..c5a3856bd223 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-cam.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs cam_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_CAM(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate cam_main_clks[] = { + GATE_CAM(CLK_CAM_MAIN_LARB13, "cam_main_larb13", "top_cam", 0), + GATE_CAM(CLK_CAM_MAIN_LARB14, "cam_main_larb14", "top_cam", 1), + GATE_CAM(CLK_CAM_MAIN_CAM, "cam_main_cam", "top_cam", 2), + GATE_CAM(CLK_CAM_MAIN_CAM_SUBA, "cam_main_cam_suba", "top_cam", 3), + GATE_CAM(CLK_CAM_MAIN_CAM_SUBB, "cam_main_cam_subb", "top_cam", 4), + GATE_CAM(CLK_CAM_MAIN_CAMTG, "cam_main_camtg", "top_cam", 7), + GATE_CAM(CLK_CAM_MAIN_SENINF, "cam_main_seninf", "top_cam", 8), + GATE_CAM(CLK_CAM_MAIN_GCAMSVA, "cam_main_gcamsva", "top_cam", 9), + GATE_CAM(CLK_CAM_MAIN_GCAMSVB, "cam_main_gcamsvb", "top_cam", 10), + GATE_CAM(CLK_CAM_MAIN_GCAMSVC, "cam_main_gcamsvc", "top_cam", 11), + GATE_CAM(CLK_CAM_MAIN_GCAMSVD, "cam_main_gcamsvd", "top_cam", 12), + GATE_CAM(CLK_CAM_MAIN_GCAMSVE, "cam_main_gcamsve", "top_cam", 13), + GATE_CAM(CLK_CAM_MAIN_GCAMSVF, "cam_main_gcamsvf", "top_cam", 14), + GATE_CAM(CLK_CAM_MAIN_GCAMSVG, "cam_main_gcamsvg", "top_cam", 15), + GATE_CAM(CLK_CAM_MAIN_GCAMSVH, "cam_main_gcamsvh", "top_cam", 16), + GATE_CAM(CLK_CAM_MAIN_GCAMSVI, "cam_main_gcamsvi", "top_cam", 17), + GATE_CAM(CLK_CAM_MAIN_GCAMSVJ, "cam_main_gcamsvj", "top_cam", 18), + GATE_CAM(CLK_CAM_MAIN_CAMSV_TOP, "cam_main_camsv", "top_cam", 19), + GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_A, "cam_main_camsv_cq_a", "top_cam", 20), + GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_B, "cam_main_camsv_cq_b", "top_cam", 21), + GATE_CAM(CLK_CAM_MAIN_CAMSV_CQ_C, "cam_main_camsv_cq_c", "top_cam", 22), + GATE_CAM(CLK_CAM_MAIN_FAKE_ENG, "cam_main_fake_eng", "top_cam", 28), + GATE_CAM(CLK_CAM_MAIN_CAM2MM0_GALS, "cam_main_cam2mm0_gals", "top_cam", 29), + GATE_CAM(CLK_CAM_MAIN_CAM2MM1_GALS, "cam_main_cam2mm1_gals", "top_cam", 30), + GATE_CAM(CLK_CAM_MAIN_CAM2SYS_GALS, "cam_main_cam2sys_gals", "top_cam", 31), +}; + +static const struct mtk_gate cam_rawa_clks[] = { + GATE_CAM(CLK_CAM_RAWA_LARBX, "cam_rawa_larbx", "top_cam", 0), + GATE_CAM(CLK_CAM_RAWA_CAM, "cam_rawa_cam", "top_cam", 1), + GATE_CAM(CLK_CAM_RAWA_CAMTG, "cam_rawa_camtg", "top_cam", 2), +}; + +static const struct mtk_gate cam_rawb_clks[] = { + GATE_CAM(CLK_CAM_RAWB_LARBX, "cam_rawb_larbx", "top_cam", 0), + GATE_CAM(CLK_CAM_RAWB_CAM, "cam_rawb_cam", "top_cam", 1), + GATE_CAM(CLK_CAM_RAWB_CAMTG, "cam_rawb_camtg", "top_cam", 2), +}; + +static const struct mtk_gate cam_yuva_clks[] = { + GATE_CAM(CLK_CAM_YUVA_LARBX, "cam_yuva_larbx", "top_cam", 0), + GATE_CAM(CLK_CAM_YUVA_CAM, "cam_yuva_cam", "top_cam", 1), + GATE_CAM(CLK_CAM_YUVA_CAMTG, "cam_yuva_camtg", "top_cam", 2), +}; + +static const struct mtk_gate cam_yuvb_clks[] = { + GATE_CAM(CLK_CAM_YUVB_LARBX, "cam_yuvb_larbx", "top_cam", 0), + GATE_CAM(CLK_CAM_YUVB_CAM, "cam_yuvb_cam", "top_cam", 1), + GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "top_cam", 2), +}; + +static const struct mtk_clk_desc cam_main_desc = { + .clks = cam_main_clks, + .num_clks = ARRAY_SIZE(cam_main_clks), +}; + +static const struct mtk_clk_desc cam_rawa_desc = { + .clks = cam_rawa_clks, + .num_clks = ARRAY_SIZE(cam_rawa_clks), +}; + +static const struct mtk_clk_desc cam_rawb_desc = { + .clks = cam_rawb_clks, + .num_clks = ARRAY_SIZE(cam_rawb_clks), +}; + +static const struct mtk_clk_desc cam_yuva_desc = { + .clks = cam_yuva_clks, + .num_clks = ARRAY_SIZE(cam_yuva_clks), +}; + +static const struct mtk_clk_desc cam_yuvb_desc = { + .clks = cam_yuvb_clks, + .num_clks = ARRAY_SIZE(cam_yuvb_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_cam[] = { + { .compatible = "mediatek,mt8188-camsys", .data = &cam_main_desc }, + { .compatible = "mediatek,mt8188-camsys-rawa", .data = &cam_rawa_desc }, + { .compatible = "mediatek,mt8188-camsys-rawb", .data = &cam_rawb_desc }, + { .compatible = "mediatek,mt8188-camsys-yuva", .data = &cam_yuva_desc }, + { .compatible = "mediatek,mt8188-camsys-yuvb", .data = &cam_yuvb_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_cam); + +static struct platform_driver clk_mt8188_cam_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-cam", + .of_match_table = of_match_clk_mt8188_cam, + }, +}; + +module_platform_driver(clk_mt8188_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-ccu.c b/drivers/clk/mediatek/clk-mt8188-ccu.c new file mode 100644 index 000000000000..ebc0d3aeee11 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-ccu.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs ccu_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_CCU(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate ccu_clks[] = { + GATE_CCU(CLK_CCU_LARB27, "ccu_larb27", "top_ccu", 0), + GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1), + GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2), +}; + +static const struct mtk_clk_desc ccu_desc = { + .clks = ccu_clks, + .num_clks = ARRAY_SIZE(ccu_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_ccu[] = { + { .compatible = "mediatek,mt8188-ccusys", .data = &ccu_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_ccu); + +static struct platform_driver clk_mt8188_ccu_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-ccu", + .of_match_table = of_match_clk_mt8188_ccu, + }, +}; + +module_platform_driver(clk_mt8188_ccu_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-img.c b/drivers/clk/mediatek/clk-mt8188-img.c new file mode 100644 index 000000000000..b4622875e14c --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-img.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs imgsys_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_IMGSYS(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &imgsys_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate imgsys_main_clks[] = { + GATE_IMGSYS(CLK_IMGSYS_MAIN_LARB9, "imgsys_main_larb9", "top_img", 0), + GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW0, "imgsys_main_traw0", "top_img", 1), + GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW1, "imgsys_main_traw1", "top_img", 2), + GATE_IMGSYS(CLK_IMGSYS_MAIN_VCORE_GALS, "imgsys_main_vcore_gals", "top_img", 3), + GATE_IMGSYS(CLK_IMGSYS_MAIN_DIP0, "imgsys_main_dip0", "top_img", 8), + GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE0, "imgsys_main_wpe0", "top_img", 9), + GATE_IMGSYS(CLK_IMGSYS_MAIN_IPE, "imgsys_main_ipe", "top_img", 10), + GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE1, "imgsys_main_wpe1", "top_img", 12), + GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE2, "imgsys_main_wpe2", "top_img", 13), + GATE_IMGSYS(CLK_IMGSYS_MAIN_GALS, "imgsys_main_gals", "top_img", 31), +}; + +static const struct mtk_gate imgsys_wpe1_clks[] = { + GATE_IMGSYS(CLK_IMGSYS_WPE1_LARB11, "imgsys_wpe1_larb11", "top_img", 0), + GATE_IMGSYS(CLK_IMGSYS_WPE1, "imgsys_wpe1", "top_img", 1), +}; + +static const struct mtk_gate imgsys_wpe2_clks[] = { + GATE_IMGSYS(CLK_IMGSYS_WPE2_LARB11, "imgsys_wpe2_larb11", "top_img", 0), + GATE_IMGSYS(CLK_IMGSYS_WPE2, "imgsys_wpe2", "top_img", 1), +}; + +static const struct mtk_gate imgsys_wpe3_clks[] = { + GATE_IMGSYS(CLK_IMGSYS_WPE3_LARB11, "imgsys_wpe3_larb11", "top_img", 0), + GATE_IMGSYS(CLK_IMGSYS_WPE3, "imgsys_wpe3", "top_img", 1), +}; + +static const struct mtk_gate imgsys1_dip_top_clks[] = { + GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_LARB10, "imgsys1_dip_larb10", "top_img", 0), + GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_DIP_TOP, "imgsys1_dip_dip_top", "top_img", 1), +}; + +static const struct mtk_gate imgsys1_dip_nr_clks[] = { + GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_LARB15, "imgsys1_dip_nr_larb15", "top_img", 0), + GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_DIP_NR, "imgsys1_dip_nr_dip_nr", "top_img", 1), +}; + +static const struct mtk_clk_desc imgsys_main_desc = { + .clks = imgsys_main_clks, + .num_clks = ARRAY_SIZE(imgsys_main_clks), +}; + +static const struct mtk_clk_desc imgsys_wpe1_desc = { + .clks = imgsys_wpe1_clks, + .num_clks = ARRAY_SIZE(imgsys_wpe1_clks), +}; + +static const struct mtk_clk_desc imgsys_wpe2_desc = { + .clks = imgsys_wpe2_clks, + .num_clks = ARRAY_SIZE(imgsys_wpe2_clks), +}; + +static const struct mtk_clk_desc imgsys_wpe3_desc = { + .clks = imgsys_wpe3_clks, + .num_clks = ARRAY_SIZE(imgsys_wpe3_clks), +}; + +static const struct mtk_clk_desc imgsys1_dip_top_desc = { + .clks = imgsys1_dip_top_clks, + .num_clks = ARRAY_SIZE(imgsys1_dip_top_clks), +}; + +static const struct mtk_clk_desc imgsys1_dip_nr_desc = { + .clks = imgsys1_dip_nr_clks, + .num_clks = ARRAY_SIZE(imgsys1_dip_nr_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_imgsys_main[] = { + { .compatible = "mediatek,mt8188-imgsys", .data = &imgsys_main_desc }, + { .compatible = "mediatek,mt8188-imgsys-wpe1", .data = &imgsys_wpe1_desc }, + { .compatible = "mediatek,mt8188-imgsys-wpe2", .data = &imgsys_wpe2_desc }, + { .compatible = "mediatek,mt8188-imgsys-wpe3", .data = &imgsys_wpe3_desc }, + { .compatible = "mediatek,mt8188-imgsys1-dip-top", .data = &imgsys1_dip_top_desc }, + { .compatible = "mediatek,mt8188-imgsys1-dip-nr", .data = &imgsys1_dip_nr_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_imgsys_main); + +static struct platform_driver clk_mt8188_imgsys_main_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-imgsys_main", + .of_match_table = of_match_clk_mt8188_imgsys_main, + }, +}; + +module_platform_driver(clk_mt8188_imgsys_main_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c new file mode 100644 index 000000000000..da41a3c59919 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-imp_iic_wrap.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs imp_iic_wrap_cg_regs = { + .set_ofs = 0xe08, + .clr_ofs = 0xe04, + .sta_ofs = 0xe00, +}; + +#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) + +static const struct mtk_gate imp_iic_wrap_c_clks[] = { + GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0, + "imp_iic_wrap_c_ap_clock_i2c0", "top_i2c", 0), + GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2, + "imp_iic_wrap_c_ap_clock_i2c2", "top_i2c", 1), + GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3, + "imp_iic_wrap_c_ap_clock_i2c3", "top_i2c", 2), +}; + +static const struct mtk_gate imp_iic_wrap_w_clks[] = { + GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1, + "imp_iic_wrap_w_ap_clock_i2c1", "top_i2c", 0), + GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4, + "imp_iic_wrap_w_ap_clock_i2c4", "top_i2c", 1), +}; + +static const struct mtk_gate imp_iic_wrap_en_clks[] = { + GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5, + "imp_iic_wrap_en_ap_clock_i2c5", "top_i2c", 0), + GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6, + "imp_iic_wrap_en_ap_clock_i2c6", "top_i2c", 1), +}; + +static const struct mtk_clk_desc imp_iic_wrap_c_desc = { + .clks = imp_iic_wrap_c_clks, + .num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks), +}; + +static const struct mtk_clk_desc imp_iic_wrap_w_desc = { + .clks = imp_iic_wrap_w_clks, + .num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks), +}; + +static const struct mtk_clk_desc imp_iic_wrap_en_desc = { + .clks = imp_iic_wrap_en_clks, + .num_clks = ARRAY_SIZE(imp_iic_wrap_en_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_imp_iic_wrap[] = { + { .compatible = "mediatek,mt8188-imp-iic-wrap-c", .data = &imp_iic_wrap_c_desc }, + { .compatible = "mediatek,mt8188-imp-iic-wrap-w", .data = &imp_iic_wrap_w_desc }, + { .compatible = "mediatek,mt8188-imp-iic-wrap-en", .data = &imp_iic_wrap_en_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_imp_iic_wrap); + +static struct platform_driver clk_mt8188_imp_iic_wrap_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-imp_iic_wrap", + .of_match_table = of_match_clk_mt8188_imp_iic_wrap, + }, +}; + +module_platform_driver(clk_mt8188_imp_iic_wrap_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-infra_ao.c b/drivers/clk/mediatek/clk-mt8188-infra_ao.c new file mode 100644 index 000000000000..91c35db40b4e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-infra_ao.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs infra_ao0_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs infra_ao1_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs infra_ao2_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs infra_ao3_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +static const struct mtk_gate_regs infra_ao4_cg_regs = { + .set_ofs = 0xe0, + .clr_ofs = 0xe4, + .sta_ofs = 0xe8, +}; + +#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flag) + +#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ + GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0) + +#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flag) + +#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ + GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0) + +#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flag) + +#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flag) + +#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ + GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0) + +#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flag) + +#define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ + GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0) + +static const struct mtk_gate infra_ao_clks[] = { + /* INFRA_AO0 */ + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0), + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1), + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2), + GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3), + /* infra_ao_sej is main clock is for secure engine with JTAG support */ + GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ, "infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL), + GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6), + GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 8), + GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "top_axi", 9), + GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_h", "top_axi", 15), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19), + GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21), + GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22), + GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23), + GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24), + GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "top_uart", 25), + GATE_INFRA_AO0(CLK_INFRA_AO_UART4, "infra_ao_uart4", "top_uart", 26), + GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27), + GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "pad_fpc_ck", 28), + GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29), + /* INFRA_AO1 */ + GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0), + GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC2, "infra_ao_msdc2", "top_axi", 5), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 6), + /* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */ + GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC, "infra_ao_dvfsrc", + "clk26m", 7, CLK_IS_CRITICAL), + GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9), + GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10), + GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11), + GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_32K, "infra_ao_hdmi_32k", "clk32k", 12), + GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_HCLK, "infra_ao_cec_66m_hclk", "top_axi", 13), + GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_26M, "infra_ao_pcie_tl_26m", "clk26m", 15), + GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 16), + GATE_INFRA_AO1(CLK_INFRA_AO_CEC_66M_BCLK, "infra_ao_cec_66m_bclk", "top_axi", 17), + GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_96M, "infra_ao_pcie_tl_96m", "top_tl", 18), + /* infra_ao_dapc is for device access permission control module */ + GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC, "infra_ao_dapc", + "top_axi", 20, CLK_IS_CRITICAL), + GATE_INFRA_AO1(CLK_INFRA_AO_ECC_66M_HCLK, "infra_ao_ecc_66m_hclk", "top_axi", 23), + GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGSYS, "infra_ao_debugsys", "top_axi", 24), + GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25), + GATE_INFRA_AO1(CLK_INFRA_AO_PCIE_TL_32K, "infra_ao_pcie_tl_32k", "clk32k", 26), + GATE_INFRA_AO1(CLK_INFRA_AO_DBG_TRACE, "infra_ao_dbg_trace", "top_axi", 29), + GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31), + /* INFRA_AO2 */ + GATE_INFRA_AO2(CLK_INFRA_AO_IRTX, "infra_ao_irtx", "top_axi", 0), + GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm0", 2), + GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3), + GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10), + GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_FSSPM, "infra_ao_fsspm", + "top_sspm", 15, CLK_IS_CRITICAL), + GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM_BUS_HCLK, "infra_ao_sspm_hclk", + "top_axi", 17, CLK_IS_CRITICAL), + GATE_INFRA_AO2(CLK_INFRA_AO_APDMA_BCLK, "infra_ao_apdma_bclk", "top_axi", 18), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25), + GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26), + GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27), + /* INFRA_AO3 */ + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0), + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1sf", "top_msdc50_0", 1), + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2sf", "top_msdc50_0", 2), + GATE_INFRA_AO3(CLK_INFRA_AO_I2S_DMA, "infra_ao_i2s_dma", "top_axi", 5), + GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_msdc50_0", 7), + GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_msdc50_0", 8), + GATE_INFRA_AO3(CLK_INFRA_AO_MSDC30_2, "infra_ao_msdc30_2", "top_msdc30_2", 9), + GATE_INFRA_AO3(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_gcpu", 10), + GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_PERI_26M, "infra_ao_pcie_peri_26m", "clk26m", 15), + GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_66M_BCLK, "infra_ao_gcpu_66m_bclk", "top_axi", 16), + GATE_INFRA_AO3(CLK_INFRA_AO_GCPU_133M_BCLK, "infra_ao_gcpu_133m_bclk", "top_axi", 17), + GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM1, "infra_ao_disp_pwm1", "top_disp_pwm1", 20), + GATE_INFRA_AO3(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "top_msdc50_0", 24), + /* infra_ao_dapc_sync is for device access permission control module */ + GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_DEVICE_APC_SYNC, "infra_ao_dapc_sync", + "top_axi", 25, CLK_IS_CRITICAL), + GATE_INFRA_AO3(CLK_INFRA_AO_PCIE_P1_PERI_26M, "infra_ao_pcie_p1_peri_26m", "clk26m", 26), + /* INFRA_AO4 */ + /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */ + GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_133M_MCLK_CK, "infra_ao_133m_mclk_set", + "top_axi", 0, CLK_IS_CRITICAL), + GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_66M_MCLK_CK, "infra_ao_66m_mclk_set", + "top_axi", 1, CLK_IS_CRITICAL), + GATE_INFRA_AO4(CLK_INFRA_AO_PCIE_PL_P_250M_P0, "infra_ao_pcie_pl_p_250m_p0", + "pextp_pipe", 7), + GATE_INFRA_AO4(CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P, + "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), +}; + +static const struct mtk_clk_desc infra_ao_desc = { + .clks = infra_ao_clks, + .num_clks = ARRAY_SIZE(infra_ao_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_infra_ao[] = { + { .compatible = "mediatek,mt8188-infracfg-ao", .data = &infra_ao_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_infra_ao); + +static struct platform_driver clk_mt8188_infra_ao_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-infra_ao", + .of_match_table = of_match_clk_mt8188_infra_ao, + }, +}; +module_platform_driver(clk_mt8188_infra_ao_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-ipe.c b/drivers/clk/mediatek/clk-mt8188-ipe.c new file mode 100644 index 000000000000..c07afbd1429e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-ipe.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs ipe_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_IPE(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate ipe_clks[] = { + GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0), + GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1), + GATE_IPE(CLK_IPE_ME, "ipe_me", "top_ipe", 2), + GATE_IPE(CLK_IPESYS_TOP, "ipesys_top", "top_ipe", 3), + GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4), +}; + +static const struct mtk_clk_desc ipe_desc = { + .clks = ipe_clks, + .num_clks = ARRAY_SIZE(ipe_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_ipe[] = { + { .compatible = "mediatek,mt8188-ipesys", .data = &ipe_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_ipe); + +static struct platform_driver clk_mt8188_ipe_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-ipe", + .of_match_table = of_match_clk_mt8188_ipe, + }, +}; + +module_platform_driver(clk_mt8188_ipe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c b/drivers/clk/mediatek/clk-mt8188-mfg.c new file mode 100644 index 000000000000..e5a6eaf84672 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-mfg.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs mfgcfg_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT) + +static const struct mtk_gate mfgcfg_clks[] = { + GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "mfg_ck_fast_ref", 0), +}; + +static const struct mtk_clk_desc mfgcfg_desc = { + .clks = mfgcfg_clks, + .num_clks = ARRAY_SIZE(mfgcfg_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_mfgcfg[] = { + { .compatible = "mediatek,mt8188-mfgcfg", .data = &mfgcfg_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_mfgcfg); + +static struct platform_driver clk_mt8188_mfgcfg_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-mfgcfg", + .of_match_table = of_match_clk_mt8188_mfgcfg, + }, +}; + +module_platform_driver(clk_mt8188_mfgcfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-peri_ao.c b/drivers/clk/mediatek/clk-mt8188-peri_ao.c new file mode 100644 index 000000000000..b00e1ae8bd26 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-peri_ao.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs peri_ao_cg_regs = { + .set_ofs = 0x10, + .clr_ofs = 0x14, + .sta_ofs = 0x18, +}; + +#define GATE_PERI_AO(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri_ao_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate peri_ao_clks[] = { + GATE_PERI_AO(CLK_PERI_AO_ETHERNET, "peri_ao_ethernet", "top_axi", 0), + GATE_PERI_AO(CLK_PERI_AO_ETHERNET_BUS, "peri_ao_ethernet_bus", "top_axi", 1), + GATE_PERI_AO(CLK_PERI_AO_FLASHIF_BUS, "peri_ao_flashif_bus", "top_axi", 3), + GATE_PERI_AO(CLK_PERI_AO_FLASHIF_26M, "peri_ao_flashif_26m", "clk26m", 4), + GATE_PERI_AO(CLK_PERI_AO_FLASHIFLASHCK, "peri_ao_flashiflashck", "top_spinor", 5), + GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_BUS, "peri_ao_ssusb_2p_bus", "top_usb_top_2p", 9), + GATE_PERI_AO(CLK_PERI_AO_SSUSB_2P_XHCI, "peri_ao_ssusb_2p_xhci", "top_ssusb_xhci_2p", 10), + GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_BUS, "peri_ao_ssusb_3p_bus", "top_usb_top_3p", 11), + GATE_PERI_AO(CLK_PERI_AO_SSUSB_3P_XHCI, "peri_ao_ssusb_3p_xhci", "top_ssusb_xhci_3p", 12), + GATE_PERI_AO(CLK_PERI_AO_SSUSB_BUS, "peri_ao_ssusb_bus", "top_usb_top", 13), + GATE_PERI_AO(CLK_PERI_AO_SSUSB_XHCI, "peri_ao_ssusb_xhci", "top_ssusb_xhci", 14), + GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, "peri_ao_ethernet_mac_clk", "top_snps_eth_250m", 16), + GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_FMEM, "peri_ao_pcie_p0_fmem", "hd_466m_fmem_ck", 24), +}; + +static const struct mtk_clk_desc peri_ao_desc = { + .clks = peri_ao_clks, + .num_clks = ARRAY_SIZE(peri_ao_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_peri_ao[] = { + { .compatible = "mediatek,mt8188-pericfg-ao", .data = &peri_ao_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_peri_ao); + +static struct platform_driver clk_mt8188_peri_ao_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-peri_ao", + .of_match_table = of_match_clk_mt8188_peri_ao, + }, +}; +module_platform_driver(clk_mt8188_peri_ao_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c new file mode 100644 index 000000000000..c56ec42cb15f --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c @@ -0,0 +1,1350 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-mux.h" + +static DEFINE_SPINLOCK(mt8188_clk_lock); + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc_ck1", NULL, 260000000), + FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, "mphone_slave_bck", NULL, 49152000), + FIXED_CLK(CLK_TOP_PAD_FPC, "pad_fpc_ck", NULL, 50000000), + FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 533000000), + FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000), + FIXED_CLK(CLK_TOP_DSI_PHY, "dsi_phy", NULL, 500000000), +}; + +static const struct mtk_fixed_factor top_divs[] = { + FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), + FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), + FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2), + FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4), + FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8), + FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), + FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2), + FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4), + FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8), + FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), + FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2), + FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4), + FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8), + FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), + FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2), + FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4), + FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8), + FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9), + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), + FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), + FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2), + FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4), + FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8), + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), + FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2), + FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4), + FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8), + FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), + FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2), + FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4), + FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8), + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), + FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13), + FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4), + FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8), + FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll_192m", 1, 10), + FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16), + FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32), + FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3), + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), + FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3), + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), + FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4), + FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4), + FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4), + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), + FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), + FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), + FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), + FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4), + FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), + FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2), + FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), + FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9), + FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2), + FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4), + FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8), + FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16), + FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2), + FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4), + FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8), + FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16), + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), + FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16), + FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2), + FACTOR(CLK_TOP_ETHPLL_D4, "ethpll_d4", "ethpll", 1, 4), + FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8), + FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10), + FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2), + FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4), + FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8), + FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc_ck1", 1, 2), + FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc_ck1", 1, 4), + FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc_ck1", 1, 8), + FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc_ck1", 1, 7), + FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc_ck1", 1, 10), + FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc_ck1", 1, 16), +}; + +static const char * const axi_parents[] = { + "clk26m", + "mainpll_d4_d4", + "mainpll_d7_d2", + "mainpll_d4_d2", + "mainpll_d5_d2", + "mainpll_d6_d2", + "ulposc1_d4" +}; + +static const char * const spm_parents[] = { + "clk26m", + "ulposc1_d10", + "mainpll_d7_d4", + "clk32k" +}; + +static const char * const scp_parents[] = { + "clk26m", + "univpll_d4", + "mainpll_d6", + "univpll_d6", + "univpll_d4_d2", + "mainpll_d4_d2", + "univpll_d3", + "mainpll_d3" +}; + +static const char * const bus_aximem_parents[] = { + "clk26m", + "mainpll_d7_d2", + "mainpll_d4_d2", + "mainpll_d5_d2", + "mainpll_d6" +}; + +static const char * const vpp_parents[] = { + "clk26m", + "univpll_d6_d2", + "mainpll_d5_d2", + "mmpll_d6_d2", + "univpll_d5_d2", + "univpll_d4_d2", + "mmpll_d4_d2", + "mmpll_d7", + "univpll_d6", + "mainpll_d4", + "mmpll_d5", + "tvdpll1", + "tvdpll2", + "univpll_d4", + "mmpll_d4" +}; + +static const char * const ethdr_parents[] = { + "clk26m", + "univpll_d6_d2", + "mainpll_d5_d2", + "mmpll_d6_d2", + "univpll_d5_d2", + "univpll_d4_d2", + "mmpll_d4_d2", + "mmpll_d7", + "univpll_d6", + "mainpll_d4", + "mmpll_d5_d4", + "tvdpll1", + "tvdpll2", + "univpll_d4", + "mmpll_d4" +}; + +static const char * const ipe_parents[] = { + "clk26m", + "imgpll", + "mainpll_d4", + "mmpll_d6", + "univpll_d6", + "mainpll_d6", + "mmpll_d4_d2", + "univpll_d4_d2", + "mainpll_d4_d2", + "mmpll_d6_d2", + "univpll_d5_d2", + "mainpll_d7" +}; + +static const char * const cam_parents[] = { + "clk26m", + "tvdpll1", + "mainpll_d4", + "mmpll_d4", + "univpll_d4", + "univpll_d5", + "univpll_d6", + "mmpll_d7", + "univpll_d4_d2", + "mainpll_d4_d2", + "imgpll" +}; + +static const char * const ccu_parents[] = { + "clk26m", + "univpll_d6", + "mainpll_d4_d2", + "mainpll_d4", + "univpll_d5", + "mainpll_d6", + "mmpll_d6", + "mmpll_d7", + "univpll_d4_d2", + "univpll_d7" +}; + +static const char * const ccu_ahb_parents[] = { + "clk26m", + "univpll_d6", + "mainpll_d4_d2", + "mainpll_d4", + "univpll_d5", + "mainpll_d6", + "mmpll_d6", + "mmpll_d7", + "univpll_d4_d2", + "univpll_d7" +}; + +static const char * const img_parents[] = { + "clk26m", + "imgpll", + "univpll_d4", + "mainpll_d4", + "univpll_d5", + "mmpll_d6", + "mmpll_d7", + "univpll_d6", + "mainpll_d6", + "mmpll_d4_d2", + "univpll_d4_d2", + "mainpll_d4_d2", + "univpll_d5_d2" +}; + +static const char * const camtm_parents[] = { + "clk26m", + "univpll_d4_d4", + "univpll_d6_d2", + "univpll_d6_d4" +}; + +static const char * const dsp_parents[] = { + "clk26m", + "univpll_d6_d2", + "univpll_d4_d2", + "univpll_d5", + "univpll_d4", + "mmpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp1_parents[] = { + "clk26m", + "univpll_d6_d2", + "mainpll_d4_d2", + "univpll_d5", + "mmpll_d5", + "univpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp2_parents[] = { + "clk26m", + "univpll_d6_d2", + "mainpll_d4_d2", + "univpll_d5", + "mmpll_d5", + "univpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp3_parents[] = { + "clk26m", + "univpll_d6_d2", + "mainpll_d4_d2", + "univpll_d5", + "mmpll_d5", + "univpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp4_parents[] = { + "clk26m", + "univpll_d6_d2", + "univpll_d4_d2", + "mainpll_d4", + "univpll_d4", + "mmpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp5_parents[] = { + "clk26m", + "univpll_d6_d2", + "univpll_d4_d2", + "mainpll_d4", + "univpll_d4", + "mmpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp6_parents[] = { + "clk26m", + "univpll_d6_d2", + "univpll_d4_d2", + "mainpll_d4", + "univpll_d4", + "mmpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const dsp7_parents[] = { + "clk26m", + "univpll_d6_d2", + "univpll_d4_d2", + "univpll_d5", + "univpll_d4", + "mmpll_d4", + "mainpll_d3", + "univpll_d3" +}; + +static const char * const mfg_core_tmp_parents[] = { + "clk26m", + "mainpll_d5_d2", + "univpll_d6", + "univpll_d7" +}; + +static const char * const camtg_parents[] = { + "clk26m", + "univpll_192m_d8", + "univpll_d6_d8", + "univpll_192m_d4", + "univpll_192m_d10", + "clk13m", + "univpll_192m_d16", + "univpll_192m_d32" +}; + +static const char * const camtg2_parents[] = { + "clk26m", + "univpll_192m_d8", + "univpll_d6_d8", + "univpll_192m_d4", + "univpll_192m_d10", + "clk13m", + "univpll_192m_d16", + "univpll_192m_d32" +}; + +static const char * const camtg3_parents[] = { + "clk26m", + "univpll_192m_d8", + "univpll_d6_d8", + "univpll_192m_d4", + "univpll_192m_d10", + "clk13m", + "univpll_192m_d16", + "univpll_192m_d32" +}; + +static const char * const uart_parents[] = { + "clk26m", + "univpll_d6_d8" +}; + +static const char * const spi_parents[] = { + "clk26m", + "mainpll_d5_d4", + "mainpll_d6_d4", + "univpll_d6_d4", + "univpll_d6_d2", + "mainpll_d6_d2", + "mainpll_d4_d4", + "univpll_d5_d4" +}; + +static const char * const msdc5hclk_parents[] = { + "clk26m", + "mainpll_d4_d2", + "mainpll_d6_d2" +}; + +static const char * const msdc50_0_parents[] = { + "clk26m", + "msdcpll", + "msdcpll_d2", + "univpll_d4_d4", + "mainpll_d6_d2", + "univpll_d4_d2" +}; + +static const char * const msdc30_1_parents[] = { + "clk26m", + "univpll_d6_d2", + "mainpll_d6_d2", + "mainpll_d7_d2", + "msdcpll_d2" +}; + +static const char * const msdc30_2_parents[] = { + "clk26m", + "univpll_d6_d2", + "mainpll_d6_d2", + "mainpll_d7_d2", + "msdcpll_d2" +}; + +static const char * const intdir_parents[] = { + "clk26m", + "univpll_d6", + "mainpll_d4", + "univpll_d4" +}; + +static const char * const aud_intbus_parents[] = { + "clk26m", + "mainpll_d4_d4", + "mainpll_d7_d4" +}; + +static const char * const audio_h_parents[] = { + "clk26m", + "univpll_d7", + "apll1", + "apll2" +}; + +static const char * const pwrap_ulposc_parents[] = { + "clk26m", + "ulposc1_d10", + "ulposc1_d7", + "ulposc1_d8", + "ulposc1_d16", + "mainpll_d4_d8", + "univpll_d5_d8", + "tvdpll1_d16" +}; + +static const char * const atb_parents[] = { + "clk26m", + "mainpll_d4_d2", + "mainpll_d5_d2" +}; + +static const char * const sspm_parents[] = { + "clk26m", + "mainpll_d7_d2", + "mainpll_d6_d2", + "mainpll_d5_d2", + "mainpll_d9", + "mainpll_d4_d2" +}; + +static const char * const dp_parents[] = { + "clk26m", + "tvdpll1_d2", + "tvdpll2_d2", + "tvdpll1_d4", + "tvdpll2_d4", + "tvdpll1_d8", + "tvdpll2_d8", + "tvdpll1_d16", + "tvdpll2_d16" +}; + +static const char * const edp_parents[] = { + "clk26m", + "tvdpll1_d2", + "tvdpll2_d2", + "tvdpll1_d4", + "tvdpll2_d4", + "tvdpll1_d8", + "tvdpll2_d8", + "tvdpll1_d16", + "tvdpll2_d16" +}; + +static const char * const dpi_parents[] = { + "clk26m", + "tvdpll1_d2", + "tvdpll2_d2", + "tvdpll1_d4", + "tvdpll2_d4", + "tvdpll1_d8", + "tvdpll2_d8", + "tvdpll1_d16", + "tvdpll2_d16" +}; + +static const char * const disp_pwm0_parents[] = { + "clk26m", + "univpll_d6_d4", + "ulposc1_d2", + "ulposc1_d4", + "ulposc1_d16", + "ethpll_d4" +}; + +static const char * const disp_pwm1_parents[] = { + "clk26m", + "univpll_d6_d4", + "ulposc1_d2", + "ulposc1_d4", + "ulposc1_d16" +}; + +static const char * const usb_parents[] = { + "clk26m", + "univpll_d5_d4", + "univpll_d6_d4", + "univpll_d5_d2" +}; + +static const char * const ssusb_xhci_parents[] = { + "clk26m", + "univpll_d5_d4", + "univpll_d6_d4", + "univpll_d5_d2" +}; + +static const char * const usb_2p_parents[] = { + "clk26m", + "univpll_d5_d4", + "univpll_d6_d4", + "univpll_d5_d2" +}; + +static const char * const ssusb_xhci_2p_parents[] = { + "clk26m", + "univpll_d5_d4", + "univpll_d6_d4", + "univpll_d5_d2" +}; + +static const char * const usb_3p_parents[] = { + "clk26m", + "univpll_d5_d4", + "univpll_d6_d4", + "univpll_d5_d2" +}; + +static const char * const ssusb_xhci_3p_parents[] = { + "clk26m", + "univpll_d5_d4", + "univpll_d6_d4", + "univpll_d5_d2" +}; + +static const char * const i2c_parents[] = { + "clk26m", + "mainpll_d4_d8", + "univpll_d5_d4" +}; + +static const char * const seninf_parents[] = { + "clk26m", + "univpll_d4_d4", + "univpll_d6_d2", + "mainpll_d4_d2", + "univpll_d7", + "univpll_d6", + "mmpll_d6", + "univpll_d5" +}; + +static const char * const seninf1_parents[] = { + "clk26m", + "univpll_d4_d4", + "univpll_d6_d2", + "mainpll_d4_d2", + "univpll_d7", + "univpll_d6", + "mmpll_d6", + "univpll_d5" +}; + +static const char * const gcpu_parents[] = { + "clk26m", + "mainpll_d6", + "univpll_d4_d2", + "mmpll_d5_d2", + "univpll_d5_d2" +}; + +static const char * const venc_parents[] = { + "clk26m", + "mmpll_d4_d2", + "mainpll_d6", + "univpll_d4_d2", + "mainpll_d4_d2", + "univpll_d6", + "mmpll_d6", + "mainpll_d5_d2", + "mainpll_d6_d2", + "mmpll_d9", + "univpll_d4_d4", + "mainpll_d4", + "univpll_d4", + "univpll_d5", + "univpll_d5_d2", + "mainpll_d5" +}; + +static const char * const vdec_parents[] = { + "clk26m", + "mainpll_d5_d2", + "mmpll_d6_d2", + "univpll_d5_d2", + "univpll_d4_d2", + "mmpll_d4_d2", + "univpll_d6", + "mainpll_d5", + "univpll_d5", + "mmpll_d6", + "mainpll_d4", + "tvdpll2", + "univpll_d4", + "imgpll", + "univpll_d6_d2", + "mmpll_d9" +}; + +static const char * const pwm_parents[] = { + "clk32k", + "clk26m", + "univpll_d4_d8", + "univpll_d6_d4" +}; + +static const char * const mcupm_parents[] = { + "clk26m", + "mainpll_d6_d2", + "mainpll_d7_d4" +}; + +static const char * const spmi_p_mst_parents[] = { + "clk26m", + "clk13m", + "ulposc1_d8", + "ulposc1_d10", + "ulposc1_d16", + "ulposc1_d7", + "clk32k", + "mainpll_d7_d8", + "mainpll_d6_d8", + "mainpll_d5_d8" +}; + +static const char * const spmi_m_mst_parents[] = { + "clk26m", + "clk13m", + "ulposc1_d8", + "ulposc1_d10", + "ulposc1_d16", + "ulposc1_d7", + "clk32k", + "mainpll_d7_d8", + "mainpll_d6_d8", + "mainpll_d5_d8" +}; + +static const char * const dvfsrc_parents[] = { + "clk26m", + "ulposc1_d10", + "univpll_d6_d8", + "msdcpll_d16" +}; + +static const char * const tl_parents[] = { + "clk26m", + "univpll_d5_d4", + "mainpll_d4_d4" +}; + +static const char * const aes_msdcfde_parents[] = { + "clk26m", + "mainpll_d4_d2", + "mainpll_d6", + "mainpll_d4_d4", + "univpll_d4_d2", + "univpll_d6" +}; + +static const char * const dsi_occ_parents[] = { + "clk26m", + "univpll_d6_d2", + "univpll_d5_d2", + "univpll_d4_d2" +}; + +static const char * const wpe_vpp_parents[] = { + "clk26m", + "mainpll_d5_d2", + "mmpll_d6_d2", + "univpll_d5_d2", + "mainpll_d4_d2", + "univpll_d4_d2", + "mmpll_d4_d2", + "mainpll_d6", + "mmpll_d7", + "univpll_d6", + "mainpll_d5", + "univpll_d5", + "mainpll_d4", + "tvdpll1", + "univpll_d4" +}; + +static const char * const hdcp_parents[] = { + "clk26m", + "univpll_d4_d8", + "mainpll_d5_d8", + "univpll_d6_d4" +}; + +static const char * const hdcp_24m_parents[] = { + "clk26m", + "univpll_192m_d4", + "univpll_192m_d8", + "univpll_d6_d8" +}; + +static const char * const hdmi_apb_parents[] = { + "clk26m", + "univpll_d6_d4", + "msdcpll_d2" +}; + +static const char * const snps_eth_250m_parents[] = { + "clk26m", + "ethpll_d2" +}; + +static const char * const snps_eth_62p4m_ptp_parents[] = { + "apll2_d3", + "apll1_d3", + "clk26m", + "ethpll_d8" +}; + +static const char * const snps_eth_50m_rmii_parents[] = { + "clk26m", + "ethpll_d10" +}; + +static const char * const adsp_parents[] = { + "clk26m", + "clk13m", + "mainpll_d6", + "mainpll_d5_d2", + "univpll_d4_d4", + "univpll_d4", + "ulposc1_d2", + "ulposc1_ck1", + "adsppll", + "adsppll_d2", + "adsppll_d4", + "adsppll_d8" +}; + +static const char * const audio_local_bus_parents[] = { + "clk26m", + "clk13m", + "mainpll_d4_d4", + "mainpll_d7_d2", + "mainpll_d5_d2", + "mainpll_d4_d2", + "mainpll_d7", + "mainpll_d4", + "univpll_d6", + "ulposc1_ck1", + "ulposc1_d4", + "ulposc1_d2" +}; + +static const char * const asm_h_parents[] = { + "clk26m", + "univpll_d6_d4", + "univpll_d6_d2", + "mainpll_d5_d2" +}; + +static const char * const asm_l_parents[] = { + "clk26m", + "univpll_d6_d4", + "univpll_d6_d2", + "mainpll_d5_d2" +}; + +static const char * const apll1_parents[] = { + "clk26m", + "apll1_d4" +}; + +static const char * const apll2_parents[] = { + "clk26m", + "apll2_d4" +}; + +static const char * const apll3_parents[] = { + "clk26m", + "apll3_d4" +}; + +static const char * const apll4_parents[] = { + "clk26m", + "apll4_d4" +}; + +static const char * const apll5_parents[] = { + "clk26m", + "apll5_d4" +}; + +static const char * const i2so1_parents[] = { + "clk26m", + "apll1", + "apll2", + "apll3", + "apll4", + "apll5" +}; + +static const char * const i2so2_parents[] = { + "clk26m", + "apll1", + "apll2", + "apll3", + "apll4", + "apll5" +}; + +static const char * const i2si1_parents[] = { + "clk26m", + "apll1", + "apll2", + "apll3", + "apll4", + "apll5" +}; + +static const char * const i2si2_parents[] = { + "clk26m", + "apll1", + "apll2", + "apll3", + "apll4", + "apll5" +}; + +static const char * const dptx_parents[] = { + "clk26m", + "apll1", + "apll2", + "apll3", + "apll4", + "apll5" +}; + +static const char * const aud_iec_parents[] = { + "clk26m", + "apll1", + "apll2", + "apll3", + "apll4", + "apll5" +}; + +static const char * const a1sys_hp_parents[] = { + "clk26m", + "apll1_d4" +}; + +static const char * const a2sys_parents[] = { + "clk26m", + "apll2_d4" +}; + +static const char * const a3sys_parents[] = { + "clk26m", + "apll3_d4", + "apll4_d4", + "apll5_d4" +}; + +static const char * const a4sys_parents[] = { + "clk26m", + "apll3_d4", + "apll4_d4", + "apll5_d4" +}; + +static const char * const ecc_parents[] = { + "clk26m", + "mainpll_d4_d4", + "mainpll_d5_d2", + "mainpll_d4_d2", + "mainpll_d6", + "univpll_d6" +}; + +static const char * const spinor_parents[] = { + "clk26m", + "clk13m", + "mainpll_d7_d8", + "univpll_d6_d8" +}; + +static const char * const ulposc_parents[] = { + "ulposc_ck1", + "ethpll_d2", + "mainpll_d4_d2", + "ethpll_d10" +}; + +static const char * const srck_parents[] = { + "ulposc1_d10", + "clk26m" +}; + +static const char * const mfg_fast_ref_parents[] = { + "top_mfg_core_tmp", + "mfgpll" +}; + +static const struct mtk_mux top_mtk_muxes[] = { + /* + * CLK_CFG_0 + * axi_sel and bus_aximem_sel are bus clocks, should not be closed by Linux. + * spm_sel and scp_sel are main clocks in always-on co-processor. + */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents, + 0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents, + 0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents, + 0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", bus_aximem_parents, + 0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3, CLK_IS_CRITICAL), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp", + vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr", + ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe", + ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam", + cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu", + ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_AHB, "top_ccu_ahb", + ccu_ahb_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img", + img_parents, 0x038, 0x03C, 0x040, 16, 4, 23, 0x04, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm", + camtm_parents, 0x038, 0x03C, 0x040, 24, 4, 31, 0x04, 11), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp", + dsp_parents, 0x044, 0x048, 0x04C, 0, 4, 7, 0x04, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1", + dsp1_parents, 0x044, 0x048, 0x04C, 8, 4, 15, 0x04, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2", + dsp2_parents, 0x044, 0x048, 0x04C, 16, 4, 23, 0x04, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3", + dsp3_parents, 0x044, 0x048, 0x04C, 24, 4, 31, 0x04, 15), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4", + dsp4_parents, 0x050, 0x054, 0x058, 0, 4, 7, 0x04, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5", + dsp5_parents, 0x050, 0x054, 0x058, 8, 4, 15, 0x04, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6", + dsp6_parents, 0x050, 0x054, 0x058, 16, 4, 23, 0x04, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7", + dsp7_parents, 0x050, 0x054, 0x058, 24, 4, 31, 0x04, 19), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp", + mfg_core_tmp_parents, 0x05C, 0x060, 0x064, 0, 4, 7, 0x04, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg", + camtg_parents, 0x05C, 0x060, 0x064, 8, 4, 15, 0x04, 21), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2", + camtg2_parents, 0x05C, 0x060, 0x064, 16, 4, 23, 0x04, 22), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3", + camtg3_parents, 0x05C, 0x060, 0x064, 24, 4, 31, 0x04, 23), + /* CLK_CFG_6 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart", + uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi", + spi_parents, 0x068, 0x06C, 0x070, 8, 4, 15, 0x04, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk", + msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0", + msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1", + msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2", + msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir", + intdir_parents, 0x074, 0x078, 0x07C, 16, 4, 23, 0x04, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus", + aud_intbus_parents, 0x074, 0x078, 0x07C, 24, 4, 31, 0x04, 31), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h", + audio_h_parents, 0x080, 0x084, 0x088, 0, 4, 7, 0x08, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc", + pwrap_ulposc_parents, 0x080, 0x084, 0x088, 8, 4, 15, 0x08, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb", + atb_parents, 0x080, 0x084, 0x088, 16, 4, 23, 0x08, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm", + sspm_parents, 0x080, 0x084, 0x088, 24, 4, 31, 0x08, 3), + /* CLK_CFG_9 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp", + dp_parents, 0x08C, 0x090, 0x094, 0, 4, 7, 0x08, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp", + edp_parents, 0x08C, 0x090, 0x094, 8, 4, 15, 0x08, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi", + dpi_parents, 0x08C, 0x090, 0x094, 16, 4, 23, 0x08, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0", + disp_pwm0_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7), + /* CLK_CFG_10 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1", + disp_pwm1_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top", + usb_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci", + ssusb_xhci_parents, 0x098, 0x09C, 0x0A0, 16, 4, 23, 0x08, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p", + usb_2p_parents, 0x098, 0x09C, 0x0A0, 24, 4, 31, 0x08, 11), + /* CLK_CFG_11 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p", + ssusb_xhci_2p_parents, 0x0A4, 0x0A8, 0x0AC, 0, 4, 7, 0x08, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p", + usb_3p_parents, 0x0A4, 0x0A8, 0x0AC, 8, 4, 15, 0x08, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p", + ssusb_xhci_3p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 4, 23, 0x08, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c", + i2c_parents, 0x0A4, 0x0A8, 0x0AC, 24, 4, 31, 0x08, 15), + /* CLK_CFG_12 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf", + seninf_parents, 0x0B0, 0x0B4, 0x0B8, 0, 4, 7, 0x08, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1", + seninf1_parents, 0x0B0, 0x0B4, 0x0B8, 8, 4, 15, 0x08, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu", + gcpu_parents, 0x0B0, 0x0B4, 0x0B8, 16, 4, 23, 0x08, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc", + venc_parents, 0x0B0, 0x0B4, 0x0B8, 24, 4, 31, 0x08, 19), + /* + * CLK_CFG_13 + * top_mcupm is main clock in co-processor, should not be handled by Linux. + */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec", + vdec_parents, 0x0BC, 0x0C0, 0x0C4, 0, 4, 7, 0x08, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm", + pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", mcupm_parents, + 0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst", + spmi_p_mst_parents, 0x0BC, 0x0C0, 0x0C4, 24, 4, 31, 0x08, 23), + /* + * CLK_CFG_14 + * dvfsrc_sel is for internal DVFS usage, should not be handled by Linux. + */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst", + spmi_m_mst_parents, 0x0C8, 0x0CC, 0x0D0, 0, 4, 7, 0x08, 24), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents, + 0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl", + tl_parents, 0x0C8, 0x0CC, 0x0D0, 16, 4, 23, 0x08, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde", + aes_msdcfde_parents, 0x0C8, 0x0CC, 0x0D0, 24, 4, 31, 0x08, 27), + /* CLK_CFG_15 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ", + dsi_occ_parents, 0x0D4, 0x0D8, 0x0DC, 0, 4, 7, 0x08, 28), + MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp", + wpe_vpp_parents, 0x0D4, 0x0D8, 0x0DC, 8, 4, 15, 0x08, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp", + hdcp_parents, 0x0D4, 0x0D8, 0x0DC, 16, 4, 23, 0x08, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m", + hdcp_24m_parents, 0x0D4, 0x0D8, 0x0DC, 24, 4, 31, 0x08, 31), + /* CLK_CFG_16 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb", + hdmi_apb_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m", + snps_eth_250m_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp", + snps_eth_62p4m_ptp_parents, 0x0E0, 0x0E4, 0x0E8, 16, 4, 23, 0x0C, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii", + snps_eth_50m_rmii_parents, 0x0E0, 0x0E4, 0x0E8, 24, 4, 31, 0x0C, 3), + /* CLK_CFG_17 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp", + adsp_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus", + audio_local_bus_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h", + asm_h_parents, 0x0EC, 0x0F0, 0x0F4, 16, 4, 23, 0x0C, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l", + asm_l_parents, 0x0EC, 0x0F0, 0x0F4, 24, 4, 31, 0x0C, 7), + /* CLK_CFG_18 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1", + apll1_parents, 0x0F8, 0x0FC, 0x100, 0, 4, 7, 0x0C, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2", + apll2_parents, 0x0F8, 0x0FC, 0x100, 8, 4, 15, 0x0C, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3", + apll3_parents, 0x0F8, 0x0FC, 0x100, 16, 4, 23, 0x0C, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4", + apll4_parents, 0x0F8, 0x0FC, 0x100, 24, 4, 31, 0x0C, 11), + /* CLK_CFG_19 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5", + apll5_parents, 0x0104, 0x0108, 0x010C, 0, 4, 7, 0x0C, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1, "top_i2so1", + i2so1_parents, 0x0104, 0x0108, 0x010C, 8, 4, 15, 0x0C, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2, "top_i2so2", + i2so2_parents, 0x0104, 0x0108, 0x010C, 16, 4, 23, 0x0C, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1, "top_i2si1", + i2si1_parents, 0x0104, 0x0108, 0x010C, 24, 4, 31, 0x0C, 15), + /* CLK_CFG_20 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2, "top_i2si2", + i2si2_parents, 0x0110, 0x0114, 0x0118, 0, 4, 7, 0x0C, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX, "top_dptx", + dptx_parents, 0x0110, 0x0114, 0x0118, 8, 4, 15, 0x0C, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC, "top_aud_iec", + aud_iec_parents, 0x0110, 0x0114, 0x0118, 16, 4, 23, 0x0C, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp", + a1sys_hp_parents, 0x0110, 0x0114, 0x0118, 24, 4, 31, 0x0C, 19), + /* CLK_CFG_21 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS, "top_a2sys", + a2sys_parents, 0x011C, 0x0120, 0x0124, 0, 4, 7, 0x0C, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS, "top_a3sys", + a3sys_parents, 0x011C, 0x0120, 0x0124, 8, 4, 15, 0x0C, 21), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS, "top_a4sys", + a4sys_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc", + ecc_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23), + /* + * CLK_CFG_22 + * top_ulposc/top_srck are clock source of always on co-processor, + * should not be closed by Linux. + */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor", + spinor_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", ulposc_parents, + 0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents, + 0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26, CLK_IS_CRITICAL), +}; + +static const struct mtk_composite top_adj_divs[] = { + DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "top_i2si1", 0x0320, 0, 0x0328, 8, 0), + DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "top_i2si2", 0x0320, 1, 0x0328, 8, 8), + DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "top_i2so1", 0x0320, 2, 0x0328, 8, 16), + DIV_GATE(CLK_TOP_APLL12_CK_DIV3, "apll12_div3", "top_i2so2", 0x0320, 3, 0x0328, 8, 24), + DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "top_aud_iec", 0x0320, 4, 0x0334, 8, 0), + DIV_GATE(CLK_TOP_APLL12_CK_DIV9, "apll12_div9", "top_dptx", 0x0320, 9, 0x0338, 8, 8), +}; +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0x238, + .clr_ofs = 0x238, + .sta_ofs = 0x238, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x250, + .clr_ofs = 0x250, + .sta_ofs = 0x250, +}; + +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +static const struct mtk_gate top_clks[] = { + /* TOP0 */ + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, "cfgreg_clock_vpp0", "top_vpp", 0), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, "cfgreg_clock_vpp1", "top_vpp", 1), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, "cfgreg_clock_vdo0", "top_vpp", 2), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, "cfgreg_clock_vdo1", "top_vpp", 3), + GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, "cfgreg_clock_isp_axi_gals", "top_vpp", 4), + GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, "cfgreg_f26m_vpp0", "clk26m", 5), + GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, "cfgreg_f26m_vpp1", "clk26m", 6), + GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, "cfgreg_f26m_vdo0", "clk26m", 7), + GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, "cfgreg_f26m_vdo1", "clk26m", 8), + GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD, "cfgreg_aud_f26m_aud", "clk26m", 9), + GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, "cfgreg_unipll_ses", "univpll_d2", 15), + GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF, "cfgreg_f_pcie_phy_ref", "clk26m", 18), + /* TOP1 */ + GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, "ssusb_ref", "clk26m", 0), + GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, "ssusb_p1_ref", "clk26m", 2), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, "ssusb_p2_ref", "clk26m", 4), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5), + GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, "ssusb_p3_ref", "clk26m", 6), + GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7), +}; + +static const struct of_device_id of_match_clk_mt8188_topck[] = { + { .compatible = "mediatek,mt8188-topckgen" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_topck); + +/* Register mux notifier for MFG mux */ +static int clk_mt8188_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) +{ + struct mtk_mux_nb *mfg_mux_nb; + + mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); + if (!mfg_mux_nb) + return -ENOMEM; + + mfg_mux_nb->ops = &clk_mux_ops; + mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP */ + + return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); +} + +static int clk_mt8188_topck_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *top_clk_data; + struct device_node *node = pdev->dev.of_node; + struct clk_hw *hw; + int r; + void __iomem *base; + + top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); + if (!top_clk_data) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + r = PTR_ERR(base); + goto free_top_data; + } + + r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + top_clk_data); + if (r) + goto free_top_data; + + r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); + if (r) + goto unregister_fixed_clks; + + r = mtk_clk_register_muxes(&pdev->dev, top_mtk_muxes, + ARRAY_SIZE(top_mtk_muxes), node, + &mt8188_clk_lock, top_clk_data); + if (r) + goto unregister_factors; + + hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_ref_parents, + ARRAY_SIZE(mfg_fast_ref_parents), CLK_SET_RATE_PARENT, + (base + 0x250), 8, 1, 0, &mt8188_clk_lock); + if (IS_ERR(hw)) { + r = PTR_ERR(hw); + goto unregister_muxes; + } + top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw; + + r = clk_mt8188_reg_mfg_mux_notifier(&pdev->dev, + top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk); + if (r) + goto unregister_muxes; + + r = mtk_clk_register_composites(&pdev->dev, top_adj_divs, + ARRAY_SIZE(top_adj_divs), base, + &mt8188_clk_lock, top_clk_data); + if (r) + goto unregister_muxes; + + r = mtk_clk_register_gates(&pdev->dev, node, top_clks, + ARRAY_SIZE(top_clks), top_clk_data); + if (r) + goto unregister_composite_divs; + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); + if (r) + goto unregister_gates; + + platform_set_drvdata(pdev, top_clk_data); + + return r; + +unregister_gates: + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); +unregister_composite_divs: + mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data); +unregister_muxes: + mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data); +unregister_factors: + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); +unregister_fixed_clks: + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); +free_top_data: + mtk_free_clk_data(top_clk_data); + return r; +} + +static int clk_mt8188_topck_remove(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev); + struct device_node *node = pdev->dev.of_node; + + of_clk_del_provider(node); + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); + mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data); + mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data); + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); + mtk_free_clk_data(top_clk_data); + + return 0; +} + +static struct platform_driver clk_mt8188_topck_drv = { + .probe = clk_mt8188_topck_probe, + .remove = clk_mt8188_topck_remove, + .driver = { + .name = "clk-mt8188-topck", + .of_match_table = of_match_clk_mt8188_topck, + }, +}; +module_platform_driver(clk_mt8188_topck_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vdec.c b/drivers/clk/mediatek/clk-mt8188-vdec.c new file mode 100644 index 000000000000..8c3d76531753 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-vdec.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs vdec0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x4, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs vdec1_cg_regs = { + .set_ofs = 0x200, + .clr_ofs = 0x204, + .sta_ofs = 0x200, +}; + +static const struct mtk_gate_regs vdec2_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0xc, + .sta_ofs = 0x8, +}; + +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_VDEC2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate vdec1_clks[] = { + /* VDEC1_0 */ + GATE_VDEC0(CLK_VDEC1_SOC_VDEC, "vdec1_soc_vdec", "top_vdec", 0), + GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ACTIVE, "vdec1_soc_vdec_active", "top_vdec", 4), + GATE_VDEC0(CLK_VDEC1_SOC_VDEC_ENG, "vdec1_soc_vdec_eng", "top_vdec", 8), + /* VDEC1_1 */ + GATE_VDEC1(CLK_VDEC1_SOC_LAT, "vdec1_soc_lat", "top_vdec", 0), + GATE_VDEC1(CLK_VDEC1_SOC_LAT_ACTIVE, "vdec1_soc_lat_active", "top_vdec", 4), + GATE_VDEC1(CLK_VDEC1_SOC_LAT_ENG, "vdec1_soc_lat_eng", "top_vdec", 8), + /* VDEC1_2 */ + GATE_VDEC2(CLK_VDEC1_SOC_LARB1, "vdec1_soc_larb1", "top_vdec", 0), +}; + +static const struct mtk_gate vdec2_clks[] = { + /* VDEC2_0 */ + GATE_VDEC0(CLK_VDEC2_VDEC, "vdec2_vdec", "top_vdec", 0), + GATE_VDEC0(CLK_VDEC2_VDEC_ACTIVE, "vdec2_vdec_active", "top_vdec", 4), + GATE_VDEC0(CLK_VDEC2_VDEC_ENG, "vdec2_vdec_eng", "top_vdec", 8), + /* VDEC2_1 */ + GATE_VDEC1(CLK_VDEC2_LAT, "vdec2_lat", "top_vdec", 0), + /* VDEC2_2 */ + GATE_VDEC2(CLK_VDEC2_LARB1, "vdec2_larb1", "top_vdec", 0), +}; + +static const struct mtk_clk_desc vdec1_desc = { + .clks = vdec1_clks, + .num_clks = ARRAY_SIZE(vdec1_clks), +}; + +static const struct mtk_clk_desc vdec2_desc = { + .clks = vdec2_clks, + .num_clks = ARRAY_SIZE(vdec2_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_vdec[] = { + { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vdec1_desc }, + { .compatible = "mediatek,mt8188-vdecsys", .data = &vdec2_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_vdec); + +static struct platform_driver clk_mt8188_vdec_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-vdec", + .of_match_table = of_match_clk_mt8188_vdec, + }, +}; + +module_platform_driver(clk_mt8188_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vdo0.c b/drivers/clk/mediatek/clk-mt8188-vdo0.c new file mode 100644 index 000000000000..d2be44c2f3f5 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-vdo0.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs vdo0_0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs vdo0_1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +static const struct mtk_gate_regs vdo0_2_cg_regs = { + .set_ofs = 0x124, + .clr_ofs = 0x128, + .sta_ofs = 0x120, +}; + +#define GATE_VDO0_0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VDO0_1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VDO0_2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + +static const struct mtk_gate vdo0_clks[] = { + /* VDO0_0 */ + GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0), + GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 2), + GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4), + GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 6), + GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8), + GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10), + GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17), + GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19), + GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21), + GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22), + GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23), + GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24), + GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25), + GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 26), + GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0", "top_vpp", 27), + GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28), + GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 29), + GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0", "top_vpp", 30), + GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0", "top_vpp", 31), + /* VDO0_1 */ + GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0", "top_vpp", 0), + GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 1), + GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 5), + GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3", "top_vpp", 6), + GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4", "top_vpp", 7), + GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10), + GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11), + GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12), + GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13), + GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14), + GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15), + /* VDO0_2 */ + GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0), + GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8), + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", + "top_edp", 16, CLK_SET_RATE_PARENT), +}; + +static const struct mtk_clk_desc vdo0_desc = { + .clks = vdo0_clks, + .num_clks = ARRAY_SIZE(vdo0_clks), +}; + +static const struct platform_device_id clk_mt8188_vdo0_id_table[] = { + { .name = "clk-mt8188-vdo0", .driver_data = (kernel_ulong_t)&vdo0_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8188_vdo0_id_table); + +static struct platform_driver clk_mt8188_vdo0_drv = { + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, + .driver = { + .name = "clk-mt8188-vdo0", + }, + .id_table = clk_mt8188_vdo0_id_table, +}; +module_platform_driver(clk_mt8188_vdo0_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vdo1.c b/drivers/clk/mediatek/clk-mt8188-vdo1.c new file mode 100644 index 000000000000..2ef8cae2e16e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-vdo1.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs vdo1_0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs vdo1_1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +static const struct mtk_gate_regs vdo1_2_cg_regs = { + .set_ofs = 0x124, + .clr_ofs = 0x128, + .sta_ofs = 0x120, +}; + +static const struct mtk_gate_regs vdo1_3_cg_regs = { + .set_ofs = 0x134, + .clr_ofs = 0x138, + .sta_ofs = 0x130, +}; + +static const struct mtk_gate_regs vdo1_4_cg_regs = { + .set_ofs = 0x144, + .clr_ofs = 0x148, + .sta_ofs = 0x140, +}; + +#define GATE_VDO1_0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VDO1_1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VDO1_2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VDO1_3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VDO1_3_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_3_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + +#define GATE_VDO1_4(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate vdo1_clks[] = { + /* VDO1_0 */ + GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0), + GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3", "top_vpp", 1), + GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals", "top_vpp", 2), + GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0", "top_vpp", 3), + GATE_VDO1_0(CLK_VDO1_FAKE_ENG1, "vdo1_fake_eng1", "top_vpp", 4), + GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0", "top_vpp", 5), + GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1", "top_vpp", 6), + GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2", "top_vpp", 7), + GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3", "top_vpp", 8), + GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0", "top_vpp", 9), + GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1", "top_vpp", 10), + GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2", "top_vpp", 11), + /* VDO1_1 */ + GATE_VDO1_1(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3", "top_vpp", 0), + GATE_VDO1_1(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4", "top_vpp", 1), + GATE_VDO1_1(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async", "top_vpp", 2), + GATE_VDO1_1(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async", "top_vpp", 3), + GATE_VDO1_1(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex", "top_vpp", 4), + GATE_VDO1_1(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4", "top_vpp", 5), + GATE_VDO1_1(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5", "top_vpp", 6), + GATE_VDO1_1(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6", "top_vpp", 7), + GATE_VDO1_1(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7", "top_vpp", 8), + GATE_VDO1_1(CLK_VDO1_DP_INTF0_MMCK, "vdo1_dp_intf0_mmck", "top_vpp", 9), + GATE_VDO1_1(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm_ck", "top_vpp", 10), + GATE_VDO1_1(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm_ck", "top_vpp", 11), + GATE_VDO1_1(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async", "top_vpp", 13), + GATE_VDO1_1(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async", "top_vpp", 14), + GATE_VDO1_1(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async", "top_vpp", 15), + GATE_VDO1_1(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async", "top_vpp", 16), + GATE_VDO1_1(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async", "top_vpp", 17), + GATE_VDO1_1(CLK_VDO1_DSC_VDO1_DL_ASYNC, "vdo1_dsc_vdo1_dl_async", "top_vpp", 18), + GATE_VDO1_1(CLK_VDO1_MERGE_VDO1_DL_ASYNC, "vdo1_merge_vdo1_dl_async", "top_vpp", 19), + GATE_VDO1_1(CLK_VDO1_PADDING0, "vdo1_padding0", "top_vpp", 20), + GATE_VDO1_1(CLK_VDO1_PADDING1, "vdo1_padding1", "top_vpp", 21), + GATE_VDO1_1(CLK_VDO1_PADDING2, "vdo1_padding2", "top_vpp", 22), + GATE_VDO1_1(CLK_VDO1_PADDING3, "vdo1_padding3", "top_vpp", 23), + GATE_VDO1_1(CLK_VDO1_PADDING4, "vdo1_padding4", "top_vpp", 24), + GATE_VDO1_1(CLK_VDO1_PADDING5, "vdo1_padding5", "top_vpp", 25), + GATE_VDO1_1(CLK_VDO1_PADDING6, "vdo1_padding6", "top_vpp", 26), + GATE_VDO1_1(CLK_VDO1_PADDING7, "vdo1_padding7", "top_vpp", 27), + GATE_VDO1_1(CLK_VDO1_DISP_RSZ0, "vdo1_disp_rsz0", "top_vpp", 28), + GATE_VDO1_1(CLK_VDO1_DISP_RSZ1, "vdo1_disp_rsz1", "top_vpp", 29), + GATE_VDO1_1(CLK_VDO1_DISP_RSZ2, "vdo1_disp_rsz2", "top_vpp", 30), + GATE_VDO1_1(CLK_VDO1_DISP_RSZ3, "vdo1_disp_rsz3", "top_vpp", 31), + /* VDO1_2 */ + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0", "top_vpp", 0), + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0", "top_vpp", 1), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be", "top_vpp", 2), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1", "top_vpp", 16), + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1", "top_vpp", 17), + GATE_VDO1_2(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer", "top_vpp", 18), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async", "top_vpp", 19), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async", "top_vpp", 20), + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async", "top_vpp", 21), + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async", "top_vpp", 22), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async", "top_vpp", 23), + /* VDO1_3 */ + GATE_VDO1_3(CLK_VDO1_DPI0, "vdo1_dpi0_ck", "top_vpp", 0), + GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0_ck", "top_vpp", 1), + GATE_VDO1_3(CLK_VDO1_DPI1, "vdo1_dpi1_ck", "top_vpp", 8), + GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1_ck", "top_vpp", 9), + GATE_VDO1_3_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_RATE_PARENT), + GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf_ck", "top_vpp", 17), + /* VDO1_4 */ + GATE_VDO1_4(CLK_VDO1_26M_SLOW, "vdo1_26m_slow_ck", "clk26m", 8), +}; + +static const struct mtk_clk_desc vdo1_desc = { + .clks = vdo1_clks, + .num_clks = ARRAY_SIZE(vdo1_clks), +}; + +static const struct platform_device_id clk_mt8188_vdo1_id_table[] = { + { .name = "clk-mt8188-vdo1", .driver_data = (kernel_ulong_t)&vdo1_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8188_vdo1_id_table); + +static struct platform_driver clk_mt8188_vdo1_drv = { + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, + .driver = { + .name = "clk-mt8188-vdo1", + }, + .id_table = clk_mt8188_vdo1_id_table, +}; +module_platform_driver(clk_mt8188_vdo1_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-venc.c b/drivers/clk/mediatek/clk-mt8188-venc.c new file mode 100644 index 000000000000..245367f33fa5 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-venc.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs venc1_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_VENC1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate venc1_clks[] = { + GATE_VENC1(CLK_VENC1_LARB, "venc1_larb", "top_venc", 0), + GATE_VENC1(CLK_VENC1_VENC, "venc1_venc", "top_venc", 4), + GATE_VENC1(CLK_VENC1_JPGENC, "venc1_jpgenc", "top_venc", 8), + GATE_VENC1(CLK_VENC1_JPGDEC, "venc1_jpgdec", "top_venc", 12), + GATE_VENC1(CLK_VENC1_JPGDEC_C1, "venc1_jpgdec_c1", "top_venc", 16), + GATE_VENC1(CLK_VENC1_GALS, "venc1_gals", "top_venc", 28), + GATE_VENC1(CLK_VENC1_GALS_SRAM, "venc1_gals_sram", "top_venc", 31), +}; + +static const struct mtk_clk_desc venc1_desc = { + .clks = venc1_clks, + .num_clks = ARRAY_SIZE(venc1_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_venc1[] = { + { .compatible = "mediatek,mt8188-vencsys", .data = &venc1_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_venc1); + +static struct platform_driver clk_mt8188_venc1_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-venc1", + .of_match_table = of_match_clk_mt8188_venc1, + }, +}; + +module_platform_driver(clk_mt8188_venc1_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c b/drivers/clk/mediatek/clk-mt8188-vpp0.c new file mode 100644 index 000000000000..07bdedf6a21a --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs vpp0_0_cg_regs = { + .set_ofs = 0x24, + .clr_ofs = 0x28, + .sta_ofs = 0x20, +}; + +static const struct mtk_gate_regs vpp0_1_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x34, + .sta_ofs = 0x2c, +}; + +static const struct mtk_gate_regs vpp0_2_cg_regs = { + .set_ofs = 0x3c, + .clr_ofs = 0x40, + .sta_ofs = 0x38, +}; + +#define GATE_VPP0_0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VPP0_1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VPP0_2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate vpp0_clks[] = { + /* VPP0_0 */ + GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1), + GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2), + GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7), + GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8), + GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10), + GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11), + GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13), + GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay", "top_vpp", 14), + GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15), + GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16), + GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17), + GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18), + /* VPP0_1 */ + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, "vpp0_smi_common_mmsram", "top_vpp", 0), + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1), + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2), + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, "vpp0_gals_vencsys_mmsram", "top_vpp", 3), + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM, + "vpp0_gals_vencsys_core1_mmsram", "top_vpp", 4), + GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, "vpp0_gals_infra_mmsram", "top_vpp", 5), + GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, "vpp0_gals_camsys_mmsram", "top_vpp", 6), + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7), + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8), + GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, "vpp0_smi_reorder_mmsram", "top_vpp", 9), + GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10), + GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11), + GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12), + GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13), + GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16), + GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17), + GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18), + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19), + GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20), + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, "vpp0_gals_vpp1_wpesys", "top_vpp", 21), + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, + "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp", 22), + GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23), + GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24), + GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25), + GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26), + GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27), + GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma", "top_vpp", 28), + GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma", "top_vpp", 29), + GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp", 30), + /* VPP0_2 */ + GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0), + GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async", "top_wpe_vpp", 1), + GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2), + GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async", "top_wpe_vpp", 3), +}; + +static const struct mtk_clk_desc vpp0_desc = { + .clks = vpp0_clks, + .num_clks = ARRAY_SIZE(vpp0_clks), +}; + +static const struct platform_device_id clk_mt8188_vpp0_id_table[] = { + { .name = "clk-mt8188-vpp0", .driver_data = (kernel_ulong_t)&vpp0_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8188_vpp0_id_table); + +static struct platform_driver clk_mt8188_vpp0_drv = { + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, + .driver = { + .name = "clk-mt8188-vpp0", + }, + .id_table = clk_mt8188_vpp0_id_table, +}; +module_platform_driver(clk_mt8188_vpp0_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-vpp1.c b/drivers/clk/mediatek/clk-mt8188-vpp1.c new file mode 100644 index 000000000000..d4e66b240573 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-vpp1.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs vpp1_0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs vpp1_1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_VPP1_0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_VPP1_1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate vpp1_clks[] = { + /* VPP1_0 */ + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl", "top_vpp", 0), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc", "top_vpp", 1), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot", "top_vpp", 2), + GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad", "top_vpp", 3), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot", "top_vpp", 4), + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad", "top_vpp", 5), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot", "top_vpp", 6), + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad", "top_vpp", 7), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma", "top_vpp", 8), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg", "top_vpp", 9), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma", "top_vpp", 10), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg", "top_vpp", 11), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma", "top_vpp", 12), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg", "top_vpp", 13), + GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split", "top_vpp", 14), + GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay", "top_vpp", 15), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz", "top_vpp", 16), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp", "top_vpp", 17), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color", "top_vpp", 18), + GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay", "top_vpp", 19), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz", "top_vpp", 20), + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge", "top_vpp", 21), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp", "top_vpp", 22), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color", "top_vpp", 23), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz", "top_vpp", 24), + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge", "top_vpp", 25), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp", "top_vpp", 26), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color", "top_vpp", 27), + GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5", "top_vpp", 28), + GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6", "top_vpp", 29), + GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5", "top_vpp", 30), + GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6", "top_vpp", 31), + /* VPP1_1 */ + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr", "top_vpp", 0), + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal", "top_vpp", 1), + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr", "top_vpp", 2), + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal", "top_vpp", 3), + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr", "top_vpp", 4), + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal", "top_vpp", 5), + GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex", "top_vpp", 7), + GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay", "top_vpp", 8), + GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay", "top_vpp", 9), + GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async", "top_vpp", 10), + GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay", "top_vpp", 11), + GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng", "top_vpp", 12), + GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng", "top_vpp", 13), + GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta", "top_vpp", 16), + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi", "top_vpp", 17), + GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in", "top_vpp", 18), + GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out", "top_vpp", 19), + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi", "top_vpp", 20), + GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ", "top_vpp", 21), + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "top_vpp", 26), +}; + +static const struct mtk_clk_desc vpp1_desc = { + .clks = vpp1_clks, + .num_clks = ARRAY_SIZE(vpp1_clks), +}; + +static const struct platform_device_id clk_mt8188_vpp1_id_table[] = { + { .name = "clk-mt8188-vpp1", .driver_data = (kernel_ulong_t)&vpp1_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8188_vpp1_id_table); + +static struct platform_driver clk_mt8188_vpp1_drv = { + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, + .driver = { + .name = "clk-mt8188-vpp1", + }, + .id_table = clk_mt8188_vpp1_id_table, +}; +module_platform_driver(clk_mt8188_vpp1_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8188-wpe.c b/drivers/clk/mediatek/clk-mt8188-wpe.c new file mode 100644 index 000000000000..393ac38a2172 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8188-wpe.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Garmin Chang <garmin.chang@mediatek.com> + */ + +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/mediatek,mt8188-clk.h> + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs wpe_top_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs wpe_vpp0_0_cg_regs = { + .set_ofs = 0x58, + .clr_ofs = 0x58, + .sta_ofs = 0x58, +}; + +static const struct mtk_gate_regs wpe_vpp0_1_cg_regs = { + .set_ofs = 0x5c, + .clr_ofs = 0x5c, + .sta_ofs = 0x5c, +}; + +#define GATE_WPE_TOP(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &wpe_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +#define GATE_WPE_VPP0_0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &wpe_vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +#define GATE_WPE_VPP0_1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &wpe_vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +static const struct mtk_gate wpe_top_clks[] = { + GATE_WPE_TOP(CLK_WPE_TOP_WPE_VPP0, "wpe_wpe_vpp0", "top_wpe_vpp", 16), + GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7, "wpe_smi_larb7", "top_wpe_vpp", 18), + GATE_WPE_TOP(CLK_WPE_TOP_WPESYS_EVENT_TX, "wpe_wpesys_event_tx", "top_wpe_vpp", 20), + GATE_WPE_TOP(CLK_WPE_TOP_SMI_LARB7_PCLK_EN, "wpe_smi_larb7_p_en", "top_wpe_vpp", 24), +}; + +static const struct mtk_gate wpe_vpp0_clks[] = { + /* WPE_VPP00 */ + GATE_WPE_VPP0_0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen", "top_img", 0), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext", "top_img", 1), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc", "top_img", 2), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top", "top_img", 3), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma", "top_img", 4), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top", "top_img", 5), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma", "top_img", 6), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top", "top_img", 7), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma", "top_img", 8), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top", "top_img", 9), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma", "top_img", 10), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp", "top_img", 11), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2", "top_img", 12), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync", "top_img", 13), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24", "top_img", 14), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop", "top_img", 15), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop", "top_img", 16), + GATE_WPE_VPP0_0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top", "top_img", 17), + /* WPE_VPP0_1 */ + GATE_WPE_VPP0_1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci", "top_img", 0), + GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i", "top_img", 1), + GATE_WPE_VPP0_1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i", "top_img", 2), + GATE_WPE_VPP0_1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo", "top_img", 3), + GATE_WPE_VPP0_1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko", "top_img", 4), +}; + +static const struct mtk_clk_desc wpe_top_desc = { + .clks = wpe_top_clks, + .num_clks = ARRAY_SIZE(wpe_top_clks), +}; + +static const struct mtk_clk_desc wpe_vpp0_desc = { + .clks = wpe_vpp0_clks, + .num_clks = ARRAY_SIZE(wpe_vpp0_clks), +}; + +static const struct of_device_id of_match_clk_mt8188_wpe[] = { + { .compatible = "mediatek,mt8188-wpesys", .data = &wpe_top_desc }, + { .compatible = "mediatek,mt8188-wpesys-vpp0", .data = &wpe_vpp0_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_wpe); + +static struct platform_driver clk_mt8188_wpe_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8188-wpe", + .of_match_table = of_match_clk_mt8188_wpe, + }, +}; + +module_platform_driver(clk_mt8188_wpe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-apmixedsys.c b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c new file mode 100644 index 000000000000..eafd34297b9a --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-apmixedsys.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + * Chun-Jie Chen <chun-jie.chen@mediatek.com> + * Copyright (c) 2023 Collabora Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#include <dt-bindings/clock/mt8192-clk.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include "clk-fhctl.h" +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" +#include "clk-pllfh.h" + +static const struct mtk_gate_regs apmixed_cg_regs = { + .set_ofs = 0x14, + .clr_ofs = 0x14, + .sta_ofs = 0x14, +}; + +#define GATE_APMIXED(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +static const struct mtk_gate apmixed_clks[] = { + GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), +}; + +#define MT8192_PLL_FMAX (3800UL * MHZ) +#define MT8192_PLL_FMIN (1500UL * MHZ) +#define MT8192_INTEGER_BITS 8 + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, _pcw_chg_reg, \ + _en_reg, _pll_en_bit) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8192_PLL_FMAX, \ + .fmin = MT8192_PLL_FMIN, \ + .pcwbits = _pcwbits, \ + .pcwibits = MT8192_INTEGER_BITS, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, \ + .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + .en_reg = _en_reg, \ + .pll_en_bit = _pll_en_bit, \ + } + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift) \ + PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, 0, 0, 0) + +static const struct mtk_pll_data plls[] = { + PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), + PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), + PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, + 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), + PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000, + 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), + PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000, + HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), + PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000, + 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), + PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000, + 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), + PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000, + 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), + PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, + 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), +}; + +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL0, + FH_ARMPLL_BL1, + FH_ARMPLL_BL2, + FH_ARMPLL_BL3, + FH_CCIPLL, + FH_MFGPLL, + FH_MEMPLL, + FH_MPLL, + FH_MMPLL, + FH_MAINPLL, + FH_MSDCPLL, + FH_ADSPPLL, + FH_APUPLL, + FH_TVDPLL, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data = { \ + .pll_id = _pllid, \ + .fh_id = _fhid, \ + .fh_ver = FHCTL_PLLFH_V2, \ + .fhx_offset = _offset, \ + .dds_mask = GENMASK(21, 0), \ + .slope0_value = 0x6003c97, \ + .slope1_value = 0x6003c97, \ + .sfstrx_en = BIT(2), \ + .frddsx_en = BIT(1), \ + .fhctlx_en = BIT(0), \ + .tgl_org = BIT(31), \ + .dvfs_tri = BIT(31), \ + .pcwchg = BIT(31), \ + .dt_val = 0x0, \ + .df_val = 0x9, \ + .updnlmt_shft = 16, \ + .msk_frddsx_dys = GENMASK(23, 20), \ + .msk_frddsx_dts = GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] = { + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x12c), + FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x154), +}; + +static const struct of_device_id of_match_clk_mt8192_apmixed[] = { + { .compatible = "mediatek,mt8192-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_apmixed); + +static int clk_mt8192_apmixed_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + const u8 *fhctl_node = "mediatek,mt8192-fhctl"; + int r; + + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); + if (r) + goto free_clk_data; + + r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + if (r) + goto unregister_plls; + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_gates; + + return r; + +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); +unregister_plls: + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; +} + +static int clk_mt8192_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static struct platform_driver clk_mt8192_apmixed_drv = { + .driver = { + .name = "clk-mt8192-apmixed", + .of_match_table = of_match_clk_mt8192_apmixed, + }, + .probe = clk_mt8192_apmixed_probe, + .remove = clk_mt8192_apmixed_remove, +}; +module_platform_driver(clk_mt8192_apmixed_drv); +MODULE_DESCRIPTION("MediaTek MT8192 apmixed clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c index 29affb68e854..ee251492d4f1 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -107,6 +107,7 @@ static const struct of_device_id of_match_clk_mt8192_aud[] = { { .compatible = "mediatek,mt8192-audsys", .data = &aud_desc }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_aud); static struct platform_driver clk_mt8192_aud_drv = { .probe = clk_mt8192_aud_probe, @@ -116,5 +117,5 @@ static struct platform_driver clk_mt8192_aud_drv = { .of_match_table = of_match_clk_mt8192_aud, }, }; - -builtin_platform_driver(clk_mt8192_aud_drv); +module_platform_driver(clk_mt8192_aud_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-cam.c b/drivers/clk/mediatek/clk-mt8192-cam.c index 90b57d46eef7..7befd6ee8c79 100644 --- a/drivers/clk/mediatek/clk-mt8192-cam.c +++ b/drivers/clk/mediatek/clk-mt8192-cam.c @@ -95,6 +95,7 @@ static const struct of_device_id of_match_clk_mt8192_cam[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_cam); static struct platform_driver clk_mt8192_cam_drv = { .probe = mtk_clk_simple_probe, @@ -104,5 +105,5 @@ static struct platform_driver clk_mt8192_cam_drv = { .of_match_table = of_match_clk_mt8192_cam, }, }; - -builtin_platform_driver(clk_mt8192_cam_drv); +module_platform_driver(clk_mt8192_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-img.c b/drivers/clk/mediatek/clk-mt8192-img.c index da82d65a7650..a7505150a9d0 100644 --- a/drivers/clk/mediatek/clk-mt8192-img.c +++ b/drivers/clk/mediatek/clk-mt8192-img.c @@ -58,6 +58,7 @@ static const struct of_device_id of_match_clk_mt8192_img[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_img); static struct platform_driver clk_mt8192_img_drv = { .probe = mtk_clk_simple_probe, @@ -67,5 +68,5 @@ static struct platform_driver clk_mt8192_img_drv = { .of_match_table = of_match_clk_mt8192_img, }, }; - -builtin_platform_driver(clk_mt8192_img_drv); +module_platform_driver(clk_mt8192_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c index ff8e20bb44bb..cd5d00a7c54b 100644 --- a/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c @@ -107,6 +107,7 @@ static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_imp_iic_wrap); static struct platform_driver clk_mt8192_imp_iic_wrap_drv = { .probe = mtk_clk_simple_probe, @@ -116,5 +117,5 @@ static struct platform_driver clk_mt8192_imp_iic_wrap_drv = { .of_match_table = of_match_clk_mt8192_imp_iic_wrap, }, }; - -builtin_platform_driver(clk_mt8192_imp_iic_wrap_drv); +module_platform_driver(clk_mt8192_imp_iic_wrap_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/clk-mt8192-ipe.c index 0225abe4170a..dee671ae38e6 100644 --- a/drivers/clk/mediatek/clk-mt8192-ipe.c +++ b/drivers/clk/mediatek/clk-mt8192-ipe.c @@ -45,6 +45,7 @@ static const struct of_device_id of_match_clk_mt8192_ipe[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_ipe); static struct platform_driver clk_mt8192_ipe_drv = { .probe = mtk_clk_simple_probe, @@ -54,5 +55,5 @@ static struct platform_driver clk_mt8192_ipe_drv = { .of_match_table = of_match_clk_mt8192_ipe, }, }; - -builtin_platform_driver(clk_mt8192_ipe_drv); +module_platform_driver(clk_mt8192_ipe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-mdp.c b/drivers/clk/mediatek/clk-mt8192-mdp.c index 4675788d7816..f7b27264e378 100644 --- a/drivers/clk/mediatek/clk-mt8192-mdp.c +++ b/drivers/clk/mediatek/clk-mt8192-mdp.c @@ -70,6 +70,7 @@ static const struct of_device_id of_match_clk_mt8192_mdp[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_mdp); static struct platform_driver clk_mt8192_mdp_drv = { .probe = mtk_clk_simple_probe, @@ -79,5 +80,5 @@ static struct platform_driver clk_mt8192_mdp_drv = { .of_match_table = of_match_clk_mt8192_mdp, }, }; - -builtin_platform_driver(clk_mt8192_mdp_drv); +module_platform_driver(clk_mt8192_mdp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-mfg.c b/drivers/clk/mediatek/clk-mt8192-mfg.c index ec5b44ffa458..85f76a2bbac4 100644 --- a/drivers/clk/mediatek/clk-mt8192-mfg.c +++ b/drivers/clk/mediatek/clk-mt8192-mfg.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8192_mfg[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_mfg); static struct platform_driver clk_mt8192_mfg_drv = { .probe = mtk_clk_simple_probe, @@ -49,5 +50,5 @@ static struct platform_driver clk_mt8192_mfg_drv = { .of_match_table = of_match_clk_mt8192_mfg, }, }; - -builtin_platform_driver(clk_mt8192_mfg_drv); +module_platform_driver(clk_mt8192_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/clk-mt8192-mm.c index e9eb4cf8349a..47335d517714 100644 --- a/drivers/clk/mediatek/clk-mt8192-mm.c +++ b/drivers/clk/mediatek/clk-mt8192-mm.c @@ -80,30 +80,24 @@ static const struct mtk_gate mm_clks[] = { GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25), }; -static int clk_mt8192_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(&pdev->dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - if (r) - return r; +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} +static const struct platform_device_id clk_mt8192_mm_id_table[] = { + { .name = "clk-mt8192-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8192_mm_id_table); static struct platform_driver clk_mt8192_mm_drv = { - .probe = clk_mt8192_mm_probe, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt8192-mm", }, + .id_table = clk_mt8192_mm_id_table, }; - -builtin_platform_driver(clk_mt8192_mm_drv); +module_platform_driver(clk_mt8192_mm_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/clk-mt8192-msdc.c index a72e1b73fce8..60d65f96d39a 100644 --- a/drivers/clk/mediatek/clk-mt8192-msdc.c +++ b/drivers/clk/mediatek/clk-mt8192-msdc.c @@ -52,6 +52,7 @@ static const struct of_device_id of_match_clk_mt8192_msdc[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_msdc); static struct platform_driver clk_mt8192_msdc_drv = { .probe = mtk_clk_simple_probe, @@ -61,5 +62,5 @@ static struct platform_driver clk_mt8192_msdc_drv = { .of_match_table = of_match_clk_mt8192_msdc, }, }; - -builtin_platform_driver(clk_mt8192_msdc_drv); +module_platform_driver(clk_mt8192_msdc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c index 18a8679108b8..6aad57797c39 100644 --- a/drivers/clk/mediatek/clk-mt8192-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8192-scp_adsp.c @@ -38,6 +38,7 @@ static const struct of_device_id of_match_clk_mt8192_scp_adsp[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_scp_adsp); static struct platform_driver clk_mt8192_scp_adsp_drv = { .probe = mtk_clk_simple_probe, @@ -47,5 +48,5 @@ static struct platform_driver clk_mt8192_scp_adsp_drv = { .of_match_table = of_match_clk_mt8192_scp_adsp, }, }; - -builtin_platform_driver(clk_mt8192_scp_adsp_drv); +module_platform_driver(clk_mt8192_scp_adsp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-vdec.c b/drivers/clk/mediatek/clk-mt8192-vdec.c index e149962dbbf9..473afd58495c 100644 --- a/drivers/clk/mediatek/clk-mt8192-vdec.c +++ b/drivers/clk/mediatek/clk-mt8192-vdec.c @@ -82,6 +82,7 @@ static const struct of_device_id of_match_clk_mt8192_vdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_vdec); static struct platform_driver clk_mt8192_vdec_drv = { .probe = mtk_clk_simple_probe, @@ -91,5 +92,5 @@ static struct platform_driver clk_mt8192_vdec_drv = { .of_match_table = of_match_clk_mt8192_vdec, }, }; - -builtin_platform_driver(clk_mt8192_vdec_drv); +module_platform_driver(clk_mt8192_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192-venc.c b/drivers/clk/mediatek/clk-mt8192-venc.c index 80b8bb170996..57b1b16e2310 100644 --- a/drivers/clk/mediatek/clk-mt8192-venc.c +++ b/drivers/clk/mediatek/clk-mt8192-venc.c @@ -41,6 +41,7 @@ static const struct of_device_id of_match_clk_mt8192_venc[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_venc); static struct platform_driver clk_mt8192_venc_drv = { .probe = mtk_clk_simple_probe, @@ -50,5 +51,5 @@ static struct platform_driver clk_mt8192_venc_drv = { .of_match_table = of_match_clk_mt8192_venc, }, }; - -builtin_platform_driver(clk_mt8192_venc_drv); +module_platform_driver(clk_mt8192_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index 61299960d28a..aa11291463f7 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -15,7 +15,6 @@ #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-pll.h" #include <dt-bindings/clock/mt8192-clk.h> #include <dt-bindings/reset/mt8192-resets.h> @@ -712,19 +711,6 @@ static struct mtk_composite top_muxes[] = { DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16), }; -static const struct mtk_gate_regs apmixed_cg_regs = { - .set_ofs = 0x14, - .clr_ofs = 0x14, - .sta_ofs = 0x14, -}; - -#define GATE_APMIXED(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) - -static const struct mtk_gate apmixed_clks[] = { - GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), -}; - static const struct mtk_gate_regs infra0_cg_regs = { .set_ofs = 0x80, .clr_ofs = 0x84, @@ -978,70 +964,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), }; -#define MT8192_PLL_FMAX (3800UL * MHZ) -#define MT8192_PLL_FMIN (1500UL * MHZ) -#define MT8192_INTEGER_BITS 8 - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ - _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift, _pcw_chg_reg, \ - _en_reg, _pll_en_bit) { \ - .id = _id, \ - .name = _name, \ - .reg = _reg, \ - .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, \ - .flags = _flags, \ - .rst_bar_mask = _rst_bar_mask, \ - .fmax = MT8192_PLL_FMAX, \ - .fmin = MT8192_PLL_FMIN, \ - .pcwbits = _pcwbits, \ - .pcwibits = MT8192_INTEGER_BITS, \ - .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, \ - .tuner_en_reg = _tuner_en_reg, \ - .tuner_en_bit = _tuner_en_bit, \ - .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, \ - .pcw_chg_reg = _pcw_chg_reg, \ - .en_reg = _en_reg, \ - .pll_en_bit = _pll_en_bit, \ - } - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ - _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift) \ - PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ - _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift, 0, 0, 0) - -static const struct mtk_pll_data plls[] = { - PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000, - HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), - PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000, - HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), - PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, - 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), - PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000, - 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000, - HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), - PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000, - HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), - PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000, - 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), - PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000, - 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), - PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000, - 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), - PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, - 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), -}; - /* Register mux notifier for MFG mux */ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) { @@ -1064,60 +986,6 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } -static int clk_mt8192_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - if (r) - goto free_clk_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct of_device_id of_match_clk_mt8192[] = { - { - .compatible = "mediatek,mt8192-apmixedsys", - .data = clk_mt8192_apmixed_probe, - }, { - /* sentinel */ - } -}; - -static int clk_mt8192_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int r; - - clk_probe = of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r = clk_probe(pdev); - if (r) - dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); - - return r; -} - static const struct mtk_clk_desc infra_desc = { .clks = infra_clks, .num_clks = ARRAY_SIZE(infra_clks), @@ -1145,37 +1013,21 @@ static const struct mtk_clk_desc topck_desc = { .mfg_clk_idx = CLK_TOP_MFG_PLL_SEL, }; -static const struct of_device_id of_match_clk_mt8192_simple[] = { +static const struct of_device_id of_match_clk_mt8192[] = { { .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc }, { .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc }, { .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc }, { /* sentinel */ } }; - -static struct platform_driver clk_mt8192_simple_drv = { - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt8192-simple", - .of_match_table = of_match_clk_mt8192_simple, - }, -}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8192); static struct platform_driver clk_mt8192_drv = { - .probe = clk_mt8192_probe, .driver = { .name = "clk-mt8192", .of_match_table = of_match_clk_mt8192, }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, }; - -static int __init clk_mt8192_init(void) -{ - int ret = platform_driver_register(&clk_mt8192_drv); - - if (ret) - return ret; - return platform_driver_register(&clk_mt8192_simple_drv); -} - -arch_initcall(clk_mt8192_init); +module_platform_driver(clk_mt8192_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c index 1bc917f2667e..8b9b5d820286 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -3,9 +3,11 @@ // Copyright (c) 2021 MediaTek Inc. // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> +#include "clk-fhctl.h" #include "clk-gate.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" #include <dt-bindings/clock/mt8195-clk.h> #include <linux/of_device.h> @@ -105,22 +107,82 @@ static const struct mtk_pll_data plls[] = { 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9), }; +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL, + FH_MEMPLL, + FH_ADSPPLL, + FH_NNAPLL, + FH_CCIPLL, + FH_MFGPLL, + FH_TVDPLL2, + FH_MPLL, + FH_MMPLL, + FH_MAINPLL, + FH_MSDCPLL, + FH_IMGPLL, + FH_VDECPLL, + FH_TVDPLL1, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data = { \ + .pll_id = _pllid, \ + .fh_id = _fhid, \ + .fh_ver = FHCTL_PLLFH_V2, \ + .fhx_offset = _offset, \ + .dds_mask = GENMASK(21, 0), \ + .slope0_value = 0x6003c97, \ + .slope1_value = 0x6003c97, \ + .sfstrx_en = BIT(2), \ + .frddsx_en = BIT(1), \ + .fhctlx_en = BIT(0), \ + .tgl_org = BIT(31), \ + .dvfs_tri = BIT(31), \ + .pcwchg = BIT(31), \ + .dt_val = 0x0, \ + .df_val = 0x9, \ + .updnlmt_shft = 16, \ + .msk_frddsx_dys = GENMASK(23, 20), \ + .msk_frddsx_dts = GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] = { + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78), + FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c), + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), + FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c), + FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140), + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154), +}; + static const struct of_device_id of_match_clk_mt8195_apmixed[] = { { .compatible = "mediatek,mt8195-apmixedsys", }, {} }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apmixed); static int clk_mt8195_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; + const u8 *fhctl_node = "mediatek,mt8195-fhctl"; int r; clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) return -ENOMEM; - r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_apmixed_data; @@ -140,7 +202,8 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev) unregister_gates: mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_apmixed_data: mtk_free_clk_data(clk_data); return r; @@ -153,7 +216,8 @@ static int clk_mt8195_apmixed_remove(struct platform_device *pdev) of_clk_del_provider(node); mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); return 0; @@ -167,4 +231,5 @@ static struct platform_driver clk_mt8195_apmixed_drv = { .of_match_table = of_match_clk_mt8195_apmixed, }, }; -builtin_platform_driver(clk_mt8195_apmixed_drv); +module_platform_driver(clk_mt8195_apmixed_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c index 0b52f6a009c4..de04c087c8c3 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -101,6 +101,7 @@ static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = { { .compatible = "mediatek,mt8195-apusys_pll", }, {} }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apusys_pll); static struct platform_driver clk_mt8195_apusys_pll_drv = { .probe = clk_mt8195_apusys_pll_probe, @@ -110,4 +111,5 @@ static struct platform_driver clk_mt8195_apusys_pll_drv = { .of_match_table = of_match_clk_mt8195_apusys_pll, }, }; -builtin_platform_driver(clk_mt8195_apusys_pll_drv); +module_platform_driver(clk_mt8195_apusys_pll_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-cam.c b/drivers/clk/mediatek/clk-mt8195-cam.c index e4d00fe6e757..77e608be579a 100644 --- a/drivers/clk/mediatek/clk-mt8195-cam.c +++ b/drivers/clk/mediatek/clk-mt8195-cam.c @@ -131,6 +131,7 @@ static const struct of_device_id of_match_clk_mt8195_cam[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_cam); static struct platform_driver clk_mt8195_cam_drv = { .probe = mtk_clk_simple_probe, @@ -140,4 +141,5 @@ static struct platform_driver clk_mt8195_cam_drv = { .of_match_table = of_match_clk_mt8195_cam, }, }; -builtin_platform_driver(clk_mt8195_cam_drv); +module_platform_driver(clk_mt8195_cam_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-ccu.c b/drivers/clk/mediatek/clk-mt8195-ccu.c index 4e326b6301ba..bdc2e6f3e9ce 100644 --- a/drivers/clk/mediatek/clk-mt8195-ccu.c +++ b/drivers/clk/mediatek/clk-mt8195-ccu.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8195_ccu[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_ccu); static struct platform_driver clk_mt8195_ccu_drv = { .probe = mtk_clk_simple_probe, @@ -48,4 +49,5 @@ static struct platform_driver clk_mt8195_ccu_drv = { .of_match_table = of_match_clk_mt8195_ccu, }, }; -builtin_platform_driver(clk_mt8195_ccu_drv); +module_platform_driver(clk_mt8195_ccu_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-img.c b/drivers/clk/mediatek/clk-mt8195-img.c index 12f5c436d075..d853e0e63d87 100644 --- a/drivers/clk/mediatek/clk-mt8195-img.c +++ b/drivers/clk/mediatek/clk-mt8195-img.c @@ -85,6 +85,7 @@ static const struct of_device_id of_match_clk_mt8195_img[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_img); static struct platform_driver clk_mt8195_img_drv = { .probe = mtk_clk_simple_probe, @@ -94,4 +95,5 @@ static struct platform_driver clk_mt8195_img_drv = { .of_match_table = of_match_clk_mt8195_img, }, }; -builtin_platform_driver(clk_mt8195_img_drv); +module_platform_driver(clk_mt8195_img_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c index fbc809d05072..1d808876f5c5 100644 --- a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c @@ -55,6 +55,7 @@ static const struct of_device_id of_match_clk_mt8195_imp_iic_wrap[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_imp_iic_wrap); static struct platform_driver clk_mt8195_imp_iic_wrap_drv = { .probe = mtk_clk_simple_probe, @@ -64,4 +65,5 @@ static struct platform_driver clk_mt8195_imp_iic_wrap_drv = { .of_match_table = of_match_clk_mt8195_imp_iic_wrap, }, }; -builtin_platform_driver(clk_mt8195_imp_iic_wrap_drv); +module_platform_driver(clk_mt8195_imp_iic_wrap_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index fcd410461d3b..f3ee4390707d 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -229,6 +229,7 @@ static const struct of_device_id of_match_clk_mt8195_infra_ao[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_infra_ao); static struct platform_driver clk_mt8195_infra_ao_drv = { .probe = mtk_clk_simple_probe, @@ -238,4 +239,5 @@ static struct platform_driver clk_mt8195_infra_ao_drv = { .of_match_table = of_match_clk_mt8195_infra_ao, }, }; -builtin_platform_driver(clk_mt8195_infra_ao_drv); +module_platform_driver(clk_mt8195_infra_ao_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-ipe.c b/drivers/clk/mediatek/clk-mt8195-ipe.c index b0d745cf7752..4c47f6521275 100644 --- a/drivers/clk/mediatek/clk-mt8195-ipe.c +++ b/drivers/clk/mediatek/clk-mt8195-ipe.c @@ -40,6 +40,7 @@ static const struct of_device_id of_match_clk_mt8195_ipe[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_ipe); static struct platform_driver clk_mt8195_ipe_drv = { .probe = mtk_clk_simple_probe, @@ -49,4 +50,5 @@ static struct platform_driver clk_mt8195_ipe_drv = { .of_match_table = of_match_clk_mt8195_ipe, }, }; -builtin_platform_driver(clk_mt8195_ipe_drv); +module_platform_driver(clk_mt8195_ipe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/clk-mt8195-mfg.c index c94cb71bd9b9..038acf0b1167 100644 --- a/drivers/clk/mediatek/clk-mt8195-mfg.c +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c @@ -38,6 +38,7 @@ static const struct of_device_id of_match_clk_mt8195_mfg[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_mfg); static struct platform_driver clk_mt8195_mfg_drv = { .probe = mtk_clk_simple_probe, @@ -47,4 +48,5 @@ static struct platform_driver clk_mt8195_mfg_drv = { .of_match_table = of_match_clk_mt8195_mfg, }, }; -builtin_platform_driver(clk_mt8195_mfg_drv); +module_platform_driver(clk_mt8195_mfg_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-peri_ao.c b/drivers/clk/mediatek/clk-mt8195-peri_ao.c index 2f6b3bb657db..0de162593c01 100644 --- a/drivers/clk/mediatek/clk-mt8195-peri_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-peri_ao.c @@ -51,6 +51,7 @@ static const struct of_device_id of_match_clk_mt8195_peri_ao[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_peri_ao); static struct platform_driver clk_mt8195_peri_ao_drv = { .probe = mtk_clk_simple_probe, @@ -60,4 +61,5 @@ static struct platform_driver clk_mt8195_peri_ao_drv = { .of_match_table = of_match_clk_mt8195_peri_ao, }, }; -builtin_platform_driver(clk_mt8195_peri_ao_drv); +module_platform_driver(clk_mt8195_peri_ao_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c index e16c383f631b..d0d3e3b09780 100644 --- a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c @@ -36,6 +36,7 @@ static const struct of_device_id of_match_clk_mt8195_scp_adsp[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_scp_adsp); static struct platform_driver clk_mt8195_scp_adsp_drv = { .probe = mtk_clk_simple_probe, @@ -45,4 +46,5 @@ static struct platform_driver clk_mt8195_scp_adsp_drv = { .of_match_table = of_match_clk_mt8195_scp_adsp, }, }; -builtin_platform_driver(clk_mt8195_scp_adsp_drv); +module_platform_driver(clk_mt8195_scp_adsp_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index cf520f85de73..3c2174c3e742 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1219,6 +1219,7 @@ static const struct of_device_id of_match_clk_mt8195_topck[] = { { .compatible = "mediatek,mt8195-topckgen", }, {} }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_topck); /* Register mux notifier for MFG mux */ static int clk_mt8195_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) @@ -1340,4 +1341,5 @@ static struct platform_driver clk_mt8195_topck_drv = { .of_match_table = of_match_clk_mt8195_topck, }, }; -builtin_platform_driver(clk_mt8195_topck_drv); +module_platform_driver(clk_mt8195_topck_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vdec.c b/drivers/clk/mediatek/clk-mt8195-vdec.c index a1446b666385..2bcbceb10326 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdec.c +++ b/drivers/clk/mediatek/clk-mt8195-vdec.c @@ -93,6 +93,7 @@ static const struct of_device_id of_match_clk_mt8195_vdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_vdec); static struct platform_driver clk_mt8195_vdec_drv = { .probe = mtk_clk_simple_probe, @@ -102,4 +103,5 @@ static struct platform_driver clk_mt8195_vdec_drv = { .of_match_table = of_match_clk_mt8195_vdec, }, }; -builtin_platform_driver(clk_mt8195_vdec_drv); +module_platform_driver(clk_mt8195_vdec_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c index 839b730688ac..509780750e43 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -93,55 +93,24 @@ static const struct mtk_gate vdo0_clks[] = { "top_edp", 16, CLK_SET_RATE_PARENT), }; -static int clk_mt8195_vdo0_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(&pdev->dev, node, vdo0_clks, - ARRAY_SIZE(vdo0_clks), clk_data); - if (r) - goto free_vdo0_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); -free_vdo0_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8195_vdo0_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc vdo0_desc = { + .clks = vdo0_clks, + .num_clks = ARRAY_SIZE(vdo0_clks), +}; - return 0; -} +static const struct platform_device_id clk_mt8195_vdo0_id_table[] = { + { .name = "clk-mt8195-vdo0", .driver_data = (kernel_ulong_t)&vdo0_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8195_vdo0_id_table); static struct platform_driver clk_mt8195_vdo0_drv = { - .probe = clk_mt8195_vdo0_probe, - .remove = clk_mt8195_vdo0_remove, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt8195-vdo0", }, + .id_table = clk_mt8195_vdo0_id_table, }; -builtin_platform_driver(clk_mt8195_vdo0_drv); +module_platform_driver(clk_mt8195_vdo0_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c index 7df695b28925..0a5214a1ed25 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -120,55 +120,24 @@ static const struct mtk_gate vdo1_clks[] = { GATE_VDO1_4(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0), }; -static int clk_mt8195_vdo1_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_VDO1_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(&pdev->dev, node, vdo1_clks, - ARRAY_SIZE(vdo1_clks), clk_data); - if (r) - goto free_vdo1_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data); -free_vdo1_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8195_vdo1_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data); - mtk_free_clk_data(clk_data); - - return 0; -} +static const struct mtk_clk_desc vdo1_desc = { + .clks = vdo1_clks, + .num_clks = ARRAY_SIZE(vdo1_clks), +}; + +static const struct platform_device_id clk_mt8195_vdo1_id_table[] = { + { .name = "clk-mt8195-vdo1", .driver_data = (kernel_ulong_t)&vdo1_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8195_vdo1_id_table); static struct platform_driver clk_mt8195_vdo1_drv = { - .probe = clk_mt8195_vdo1_probe, - .remove = clk_mt8195_vdo1_remove, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt8195-vdo1", }, + .id_table = clk_mt8195_vdo1_id_table, }; -builtin_platform_driver(clk_mt8195_vdo1_drv); +module_platform_driver(clk_mt8195_vdo1_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/clk-mt8195-venc.c index 622f57804f96..0991a6968765 100644 --- a/drivers/clk/mediatek/clk-mt8195-venc.c +++ b/drivers/clk/mediatek/clk-mt8195-venc.c @@ -58,6 +58,7 @@ static const struct of_device_id of_match_clk_mt8195_venc[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_venc); static struct platform_driver clk_mt8195_venc_drv = { .probe = mtk_clk_simple_probe, @@ -67,4 +68,5 @@ static struct platform_driver clk_mt8195_venc_drv = { .of_match_table = of_match_clk_mt8195_venc, }, }; -builtin_platform_driver(clk_mt8195_venc_drv); +module_platform_driver(clk_mt8195_venc_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/clk-mt8195-vpp0.c index e19664af09b6..1a98fb9a25e8 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -86,54 +86,24 @@ static const struct mtk_gate vpp0_clks[] = { GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_wpe_vpp", 3), }; -static int clk_mt8195_vpp0_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(dev, node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data); - if (r) - goto free_vpp0_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data); -free_vpp0_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8195_vpp0_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc vpp0_desc = { + .clks = vpp0_clks, + .num_clks = ARRAY_SIZE(vpp0_clks), +}; - return 0; -} +static const struct platform_device_id clk_mt8195_vpp0_id_table[] = { + { .name = "clk-mt8195-vpp0", .driver_data = (kernel_ulong_t)&vpp0_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8195_vpp0_id_table); static struct platform_driver clk_mt8195_vpp0_drv = { - .probe = clk_mt8195_vpp0_probe, - .remove = clk_mt8195_vpp0_remove, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt8195-vpp0", }, + .id_table = clk_mt8195_vpp0_id_table, }; -builtin_platform_driver(clk_mt8195_vpp0_drv); +module_platform_driver(clk_mt8195_vpp0_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/clk-mt8195-vpp1.c index e6c458fc1531..c2d5b582f53a 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -84,54 +84,24 @@ static const struct mtk_gate vpp1_clks[] = { GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m", "clk26m", 26), }; -static int clk_mt8195_vpp1_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_VPP1_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(dev, node, vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data); - if (r) - goto free_vpp1_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_gates: - mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data); -free_vpp1_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8195_vpp1_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_gates(vpp1_clks, ARRAY_SIZE(vpp1_clks), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc vpp1_desc = { + .clks = vpp1_clks, + .num_clks = ARRAY_SIZE(vpp1_clks), +}; - return 0; -} +static const struct platform_device_id clk_mt8195_vpp1_id_table[] = { + { .name = "clk-mt8195-vpp1", .driver_data = (kernel_ulong_t)&vpp1_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8195_vpp1_id_table); static struct platform_driver clk_mt8195_vpp1_drv = { - .probe = clk_mt8195_vpp1_probe, - .remove = clk_mt8195_vpp1_remove, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt8195-vpp1", }, + .id_table = clk_mt8195_vpp1_id_table, }; -builtin_platform_driver(clk_mt8195_vpp1_drv); +module_platform_driver(clk_mt8195_vpp1_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8195-wpe.c b/drivers/clk/mediatek/clk-mt8195-wpe.c index b483fab10e18..289896cb2f6c 100644 --- a/drivers/clk/mediatek/clk-mt8195-wpe.c +++ b/drivers/clk/mediatek/clk-mt8195-wpe.c @@ -132,6 +132,7 @@ static const struct of_device_id of_match_clk_mt8195_wpe[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_wpe); static struct platform_driver clk_mt8195_wpe_drv = { .probe = mtk_clk_simple_probe, @@ -141,4 +142,5 @@ static struct platform_driver clk_mt8195_wpe_drv = { .of_match_table = of_match_clk_mt8195_wpe, }, }; -builtin_platform_driver(clk_mt8195_wpe_drv); +module_platform_driver(clk_mt8195_wpe_drv); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-apmixedsys.c b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c new file mode 100644 index 000000000000..9b0bc5daeac0 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8365-apmixedsys.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + * Copyright (c) 2023 Collabora Ltd. + */ + +#include <dt-bindings/clock/mediatek,mt8365-clk.h> +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "clk-pll.h" +#include "clk-mtk.h" + +#define MT8365_PLL_FMAX (3800UL * MHZ) +#define MT8365_PLL_FMIN (1500UL * MHZ) +#define CON0_MT8365_RST_BAR BIT(23) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ + _rst_bar_mask, _pcw_chg_reg) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = _rst_bar_mask, \ + .fmax = MT8365_PLL_FMAX, \ + .fmin = MT8365_PLL_FMIN, \ + .pcwbits = _pcwbits, \ + .pcwibits = 8, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, \ + .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + .div_table = _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, \ + _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ + _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _pcwbits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \ + _pcw_chg_reg) \ + +static const struct mtk_pll_div_table armpll_div_table[] = { + { .div = 0, .freq = MT8365_PLL_FMAX }, + { .div = 1, .freq = 1500 * MHZ }, + { .div = 2, .freq = 750 * MHZ }, + { .div = 3, .freq = 375 * MHZ }, + { .div = 4, .freq = 182500000 }, + { } /* sentinel */ +}; + +static const struct mtk_pll_div_table mfgpll_div_table[] = { + { .div = 0, .freq = MT8365_PLL_FMAX }, + { .div = 1, .freq = 1600 * MHZ }, + { .div = 2, .freq = 800 * MHZ }, + { .div = 3, .freq = 400 * MHZ }, + { .div = 4, .freq = 200 * MHZ }, + { } /* sentinel */ +}; + +static const struct mtk_pll_div_table dsppll_div_table[] = { + { .div = 0, .freq = MT8365_PLL_FMAX }, + { .div = 1, .freq = 1600 * MHZ }, + { .div = 2, .freq = 600 * MHZ }, + { .div = 3, .freq = 400 * MHZ }, + { .div = 4, .freq = 200 * MHZ }, + { } /* sentinel */ +}; + +static const struct mtk_pll_data plls[] = { + PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO, + 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001, + HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, CON0_MT8365_RST_BAR, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001, + HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, CON0_MT8365_RST_BAR, 0), + PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22, + 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22, + 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22, + 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0), + PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32, + 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32, + 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22, + 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0), + PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22, + 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0), + PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22, + 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0), +}; + +static int clk_mt8365_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct clk_hw *hw; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + hw = devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0, + base + 0x204, 0, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[CLK_APMIXED_UNIV_EN] = hw; + + hw = devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0, + base + 0x204, 1, 0, NULL); + if (IS_ERR(hw)) + return PTR_ERR(hw); + clk_data->hws[CLK_APMIXED_USB20_EN] = hw; + + ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_plls; + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt8365_apmixed[] = { + { .compatible = "mediatek,mt8365-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_apmixed); + +static struct platform_driver clk_mt8365_apmixed_drv = { + .probe = clk_mt8365_apmixed_probe, + .driver = { + .name = "clk-mt8365-apmixed", + .of_match_table = of_match_clk_mt8365_apmixed, + }, +}; +builtin_platform_driver(clk_mt8365_apmixed_drv) +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-apu.c b/drivers/clk/mediatek/clk-mt8365-apu.c index 91ffe89d9721..74f7fb22c87f 100644 --- a/drivers/clk/mediatek/clk-mt8365-apu.c +++ b/drivers/clk/mediatek/clk-mt8365-apu.c @@ -42,6 +42,7 @@ static const struct of_device_id of_match_clk_mt8365_apu[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_apu); static struct platform_driver clk_mt8365_apu_drv = { .probe = mtk_clk_simple_probe, @@ -51,5 +52,5 @@ static struct platform_driver clk_mt8365_apu_drv = { .of_match_table = of_match_clk_mt8365_apu, }, }; -builtin_platform_driver(clk_mt8365_apu_drv); +module_platform_driver(clk_mt8365_apu_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-cam.c b/drivers/clk/mediatek/clk-mt8365-cam.c index 31d5b5cd6de1..61516e19acd1 100644 --- a/drivers/clk/mediatek/clk-mt8365-cam.c +++ b/drivers/clk/mediatek/clk-mt8365-cam.c @@ -44,6 +44,7 @@ static const struct of_device_id of_match_clk_mt8365_cam[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_cam); static struct platform_driver clk_mt8365_cam_drv = { .probe = mtk_clk_simple_probe, @@ -53,5 +54,5 @@ static struct platform_driver clk_mt8365_cam_drv = { .of_match_table = of_match_clk_mt8365_cam, }, }; -builtin_platform_driver(clk_mt8365_cam_drv); +module_platform_driver(clk_mt8365_cam_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-mfg.c b/drivers/clk/mediatek/clk-mt8365-mfg.c index 587b49128b03..4c836c69db4f 100644 --- a/drivers/clk/mediatek/clk-mt8365-mfg.c +++ b/drivers/clk/mediatek/clk-mt8365-mfg.c @@ -50,6 +50,7 @@ static const struct of_device_id of_match_clk_mt8365_mfg[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_mfg); static struct platform_driver clk_mt8365_mfg_drv = { .probe = mtk_clk_simple_probe, @@ -59,5 +60,5 @@ static struct platform_driver clk_mt8365_mfg_drv = { .of_match_table = of_match_clk_mt8365_mfg, }, }; -builtin_platform_driver(clk_mt8365_mfg_drv); +module_platform_driver(clk_mt8365_mfg_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/clk-mt8365-mm.c index 22c75a03a645..44427120846f 100644 --- a/drivers/clk/mediatek/clk-mt8365-mm.c +++ b/drivers/clk/mediatek/clk-mt8365-mm.c @@ -72,40 +72,24 @@ static const struct mtk_gate mm_clks[] = { GATE_MM1(CLK_MM_LVDSTX_CTS, "mm_flvdstx_cts", "lvdstx_dig_cts", 3), }; -static int clk_mt8365_mm_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->parent->of_node; - struct clk_hw_onecell_data *clk_data; - int ret; - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - - ret = mtk_clk_register_gates(dev, node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data); - if (ret) - goto err_free_clk_data; - - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto err_unregister_gates; - - return 0; - -err_unregister_gates: - mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data); - -err_free_clk_data: - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc mm_desc = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; - return ret; -} +static const struct platform_device_id clk_mt8365_mm_id_table[] = { + { .name = "clk-mt8365-mm", .driver_data = (kernel_ulong_t)&mm_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, clk_mt8365_mm_id_table); static struct platform_driver clk_mt8365_mm_drv = { - .probe = clk_mt8365_mm_probe, + .probe = mtk_clk_pdev_probe, + .remove = mtk_clk_pdev_remove, .driver = { .name = "clk-mt8365-mm", }, + .id_table = clk_mt8365_mm_id_table, }; -builtin_platform_driver(clk_mt8365_mm_drv); +module_platform_driver(clk_mt8365_mm_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-vdec.c b/drivers/clk/mediatek/clk-mt8365-vdec.c index cdc678e8941c..b51571e9da00 100644 --- a/drivers/clk/mediatek/clk-mt8365-vdec.c +++ b/drivers/clk/mediatek/clk-mt8365-vdec.c @@ -50,6 +50,7 @@ static const struct of_device_id of_match_clk_mt8365_vdec[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_vdec); static struct platform_driver clk_mt8365_vdec_drv = { .probe = mtk_clk_simple_probe, @@ -59,5 +60,5 @@ static struct platform_driver clk_mt8365_vdec_drv = { .of_match_table = of_match_clk_mt8365_vdec, }, }; -builtin_platform_driver(clk_mt8365_vdec_drv); +module_platform_driver(clk_mt8365_vdec_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365-venc.c b/drivers/clk/mediatek/clk-mt8365-venc.c index 0e080c22119d..572344645c86 100644 --- a/drivers/clk/mediatek/clk-mt8365-venc.c +++ b/drivers/clk/mediatek/clk-mt8365-venc.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8365_venc[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_venc); static struct platform_driver clk_mt8365_venc_drv = { .probe = mtk_clk_simple_probe, @@ -48,5 +49,5 @@ static struct platform_driver clk_mt8365_venc_drv = { .of_match_table = of_match_clk_mt8365_venc, }, }; -builtin_platform_driver(clk_mt8365_venc_drv); +module_platform_driver(clk_mt8365_venc_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index c9faa07ec0a6..6b4e193f648d 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2022 MediaTek Inc. + * Copyright (C) 2023 Collabora Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> */ #include <dt-bindings/clock/mediatek,mt8365-clk.h> @@ -17,7 +19,6 @@ #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-pll.h" static DEFINE_SPINLOCK(mt8365_clk_lock); @@ -383,31 +384,23 @@ static const char * const mbist_diag_parents[] = { "univpll2_d8" }; -static const char * const apll_i2s0_parents[] = { +static const char * const apll_i2s_parents[] = { "aud_1_sel", "aud_2_sel" }; -static struct mtk_composite top_misc_mux_gates[] = { +static struct mtk_composite top_misc_muxes[] = { /* CLK_CFG_11 */ MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents, 0x0ec, 0, 2, 7), -}; - -struct mt8365_clk_audio_mux { - int id; - const char *name; - u8 shift; -}; - -static struct mt8365_clk_audio_mux top_misc_muxes[] = { - { CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", 11}, - { CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", 12}, - { CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", 13}, - { CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", 14}, - { CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", 15}, - { CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", 16}, - { CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", 17}, + /* Audio MUX */ + MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1), + MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1), + MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1), + MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1), + MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1), + MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1), + MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1), }; #define CLK_CFG_UPDATE 0x004 @@ -570,35 +563,56 @@ static const struct mtk_clk_divider top_adj_divs[] = { 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), }; -struct mtk_simple_gate { - int id; - const char *name; - const char *parent; - u32 reg; - u8 shift; - unsigned long gate_flags; -}; - -static const struct mtk_simple_gate top_clk_gates[] = { - { CLK_TOP_CONN_32K, "conn_32k", "clk32k", 0x0, 10, CLK_GATE_SET_TO_DISABLE }, - { CLK_TOP_CONN_26M, "conn_26m", "clk26m", 0x0, 11, CLK_GATE_SET_TO_DISABLE }, - { CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 0x0, 16, CLK_GATE_SET_TO_DISABLE }, - { CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 0x0, 17, CLK_GATE_SET_TO_DISABLE }, - { CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 0x104, 8, 0 }, - { CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 0x104, 9, 0 }, - { CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 0x104, 20, 0 }, - { CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 0x104, 21, 0 }, - { CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 0x104, 22, 0 }, - { CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 0x104, 23, 0 }, - { CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0x320, 0, 0 }, - { CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 0x320, 1, 0 }, - { CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 0x320, 2, 0 }, - { CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 0x320, 3, 0 }, - { CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 0x320, 4, 0 }, - { CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 0x320, 5, 0 }, - { CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 0x320, 6, 0 }, - { CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 0x320, 7, 0 }, - { CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 0x320, 8, 0 }, +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0, + .clr_ofs = 0, + .sta_ofs = 0, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x104, + .sta_ofs = 0x104, +}; + +static const struct mtk_gate_regs top2_cg_regs = { + .set_ofs = 0x320, + .clr_ofs = 0x320, + .sta_ofs = 0x320, +}; + +#define GATE_TOP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top0_cg_regs, \ + _shift, &mtk_clk_gate_ops_no_setclr_inv) + +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, \ + _shift, &mtk_clk_gate_ops_no_setclr) + +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, \ + _shift, &mtk_clk_gate_ops_no_setclr) + +static const struct mtk_gate top_clk_gates[] = { + GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10), + GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m", 11), + GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16), + GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 17), + GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8), + GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 9), + GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 20), + GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21), + GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 22), + GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 23), + GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0), + GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1), + GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2), + GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3), + GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4), + GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5), + GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6), + GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7), + GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8), }; static const struct mtk_gate_regs ifr2_cg_regs = { @@ -631,50 +645,24 @@ static const struct mtk_gate_regs ifr6_cg_regs = { .sta_ofs = 0xd8, }; -#define GATE_IFR2(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ifr2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_IFR3(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ifr3_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_IFR4(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ifr4_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_IFR5(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ifr5_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_IFR6(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &ifr6_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } +#define GATE_IFRX(_id, _name, _parent, _shift, _regs) \ + GATE_MTK(_id, _name, _parent, _regs, _shift, \ + &mtk_clk_gate_ops_setclr) + +#define GATE_IFR2(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs) + +#define GATE_IFR3(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs) + +#define GATE_IFR4(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs) + +#define GATE_IFR5(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs) + +#define GATE_IFR6(_id, _name, _parent, _shift) \ + GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs) static const struct mtk_gate ifr_clks[] = { /* IFR2 */ @@ -753,405 +741,65 @@ static const struct mtk_gate ifr_clks[] = { GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11), }; -static const struct mtk_simple_gate peri_clks[] = { - { CLK_PERIAXI, "periaxi", "axi_sel", 0x20c, 31, 0 }, -}; - -#define MT8365_PLL_FMAX (3800UL * MHZ) -#define MT8365_PLL_FMIN (1500UL * MHZ) -#define CON0_MT8365_RST_BAR BIT(23) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ - _rst_bar_mask, _pcw_chg_reg) { \ - .id = _id, \ - .name = _name, \ - .reg = _reg, \ - .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, \ - .flags = _flags, \ - .rst_bar_mask = _rst_bar_mask, \ - .fmax = MT8365_PLL_FMAX, \ - .fmin = MT8365_PLL_FMIN, \ - .pcwbits = _pcwbits, \ - .pcwibits = 8, \ - .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, \ - .tuner_en_reg = _tuner_en_reg, \ - .tuner_en_bit = _tuner_en_bit, \ - .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, \ - .pcw_chg_reg = _pcw_chg_reg, \ - .div_table = _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, \ - _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ - _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ - _pcwbits, _pd_reg, _pd_shift, \ - _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ - _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \ - _pcw_chg_reg) \ - -static const struct mtk_pll_div_table armpll_div_table[] = { - { .div = 0, .freq = MT8365_PLL_FMAX }, - { .div = 1, .freq = 1500 * MHZ }, - { .div = 2, .freq = 750 * MHZ }, - { .div = 3, .freq = 375 * MHZ }, - { .div = 4, .freq = 182500000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table mfgpll_div_table[] = { - { .div = 0, .freq = MT8365_PLL_FMAX }, - { .div = 1, .freq = 1600 * MHZ }, - { .div = 2, .freq = 800 * MHZ }, - { .div = 3, .freq = 400 * MHZ }, - { .div = 4, .freq = 200 * MHZ }, - { } /* sentinel */ -}; - -static const struct mtk_pll_div_table dsppll_div_table[] = { - { .div = 0, .freq = MT8365_PLL_FMAX }, - { .div = 1, .freq = 1600 * MHZ }, - { .div = 2, .freq = 600 * MHZ }, - { .div = 3, .freq = 400 * MHZ }, - { .div = 4, .freq = 200 * MHZ }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] = { - PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO, - 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001, - HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, - CON0_MT8365_RST_BAR, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001, - HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, - CON0_MT8365_RST_BAR, 0), - PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22, - 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22, - 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22, - 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0), - PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32, - 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32, - 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22, - 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0), - PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22, - 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0), - PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22, - 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0), -}; - -static int clk_mt8365_apmixed_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - struct device *dev = &pdev->dev; - struct clk_hw *hw; - int ret; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); - if (!clk_data) - return -ENOMEM; - - hw = devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0, - base + 0x204, 0, 0, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); - clk_data->hws[CLK_APMIXED_UNIV_EN] = hw; - - hw = devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0, - base + 0x204, 1, 0, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); - clk_data->hws[CLK_APMIXED_USB20_EN] = hw; - - ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_plls; - - return 0; - -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); - - return ret; -} - -static int -clk_mt8365_register_mtk_simple_gates(struct device *dev, void __iomem *base, - struct clk_hw_onecell_data *clk_data, - const struct mtk_simple_gate *gates, - unsigned int num_gates) -{ - unsigned int i; - - for (i = 0; i != num_gates; ++i) { - const struct mtk_simple_gate *gate = &gates[i]; - struct clk_hw *hw; - - hw = devm_clk_hw_register_gate(dev, gate->name, gate->parent, 0, - base + gate->reg, gate->shift, - gate->gate_flags, NULL); - if (IS_ERR(hw)) - return PTR_ERR(hw); - - clk_data->hws[gate->id] = hw; - } - - return 0; -} - -static int clk_mt8365_top_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - struct device *dev = &pdev->dev; - int ret; - int i; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret = mtk_clk_register_fixed_clks(top_fixed_clks, - ARRAY_SIZE(top_fixed_clks), clk_data); - if (ret) - goto free_clk_data; - - ret = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), - clk_data); - if (ret) - goto unregister_fixed_clks; - - ret = mtk_clk_register_muxes(&pdev->dev, top_muxes, - ARRAY_SIZE(top_muxes), node, - &mt8365_clk_lock, clk_data); - if (ret) - goto unregister_factors; - - ret = mtk_clk_register_composites(&pdev->dev, top_misc_mux_gates, - ARRAY_SIZE(top_misc_mux_gates), base, - &mt8365_clk_lock, clk_data); - if (ret) - goto unregister_muxes; - - for (i = 0; i != ARRAY_SIZE(top_misc_muxes); ++i) { - struct mt8365_clk_audio_mux *mux = &top_misc_muxes[i]; - struct clk_hw *hw; - - hw = devm_clk_hw_register_mux(dev, mux->name, apll_i2s0_parents, - ARRAY_SIZE(apll_i2s0_parents), - CLK_SET_RATE_PARENT, base + 0x320, - mux->shift, 1, 0, NULL); - if (IS_ERR(hw)) { - ret = PTR_ERR(hw); - goto unregister_composites; - } - - clk_data->hws[mux->id] = hw; - } - - ret = mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt8365_clk_lock, clk_data); - if (ret) - goto unregister_composites; - - ret = clk_mt8365_register_mtk_simple_gates(dev, base, clk_data, - top_clk_gates, - ARRAY_SIZE(top_clk_gates)); - if (ret) - goto unregister_dividers; - - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_dividers; - - return 0; -unregister_dividers: - mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - clk_data); -unregister_composites: - mtk_clk_unregister_composites(top_misc_mux_gates, - ARRAY_SIZE(top_misc_mux_gates), clk_data); -unregister_muxes: - mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); -unregister_factors: - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -unregister_fixed_clks: - mtk_clk_unregister_fixed_clks(top_fixed_clks, - ARRAY_SIZE(top_fixed_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - - return ret; -} - -static int clk_mt8365_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int ret; - - clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret = mtk_clk_register_gates(&pdev->dev, node, ifr_clks, - ARRAY_SIZE(ifr_clks), clk_data); - if (ret) - goto free_clk_data; - - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_gates; - - return 0; - -unregister_gates: - mtk_clk_unregister_gates(ifr_clks, ARRAY_SIZE(ifr_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - - return ret; -} - -static int clk_mt8365_peri_probe(struct platform_device *pdev) -{ - void __iomem *base; - struct clk_hw_onecell_data *clk_data; - struct device *dev = &pdev->dev; - struct device_node *node = dev->of_node; - int ret; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data = mtk_devm_alloc_clk_data(dev, CLK_PERI_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret = clk_mt8365_register_mtk_simple_gates(dev, base, clk_data, - peri_clks, - ARRAY_SIZE(peri_clks)); - if (ret) - return ret; - - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - return ret; -} - -static int clk_mt8365_mcu_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - void __iomem *base; - int ret; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); - if (!clk_data) - return -ENOMEM; +static const struct mtk_gate_regs peri_cg_regs = { + .set_ofs = 0x20c, + .clr_ofs = 0x20c, + .sta_ofs = 0x20c, +}; - ret = mtk_clk_register_composites(&pdev->dev, mcu_muxes, - ARRAY_SIZE(mcu_muxes), base, - &mt8365_clk_lock, clk_data); - if (ret) - goto free_clk_data; +static const struct mtk_gate peri_clks[] = { + GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31, + &mtk_clk_gate_ops_no_setclr), +}; - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_composites; +static const struct mtk_clk_desc topck_desc = { + .clks = top_clk_gates, + .num_clks = ARRAY_SIZE(top_clk_gates), + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .mux_clks = top_muxes, + .num_mux_clks = ARRAY_SIZE(top_muxes), + .composite_clks = top_misc_muxes, + .num_composite_clks = ARRAY_SIZE(top_misc_muxes), + .divider_clks = top_adj_divs, + .num_divider_clks = ARRAY_SIZE(top_adj_divs), + .clk_lock = &mt8365_clk_lock, +}; - return 0; +static const struct mtk_clk_desc infra_desc = { + .clks = ifr_clks, + .num_clks = ARRAY_SIZE(ifr_clks), +}; -unregister_composites: - mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), - clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), +}; - return ret; -} +static const struct mtk_clk_desc mcu_desc = { + .composite_clks = mcu_muxes, + .num_composite_clks = ARRAY_SIZE(mcu_muxes), + .clk_lock = &mt8365_clk_lock, +}; static const struct of_device_id of_match_clk_mt8365[] = { - { - .compatible = "mediatek,mt8365-apmixedsys", - .data = clk_mt8365_apmixed_probe, - }, { - .compatible = "mediatek,mt8365-topckgen", - .data = clk_mt8365_top_probe, - }, { - .compatible = "mediatek,mt8365-infracfg", - .data = clk_mt8365_infra_probe, - }, { - .compatible = "mediatek,mt8365-pericfg", - .data = clk_mt8365_peri_probe, - }, { - .compatible = "mediatek,mt8365-mcucfg", - .data = clk_mt8365_mcu_probe, - }, { - /* sentinel */ - } -}; - -static int clk_mt8365_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int ret; - - clk_probe = of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - ret = clk_probe(pdev); - if (ret) - dev_err(&pdev->dev, - "%s: could not register clock provider: %d\n", - pdev->name, ret); - - return ret; -} + { .compatible = "mediatek,mt8365-topckgen", .data = &topck_desc }, + { .compatible = "mediatek,mt8365-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt8365-pericfg", .data = &peri_desc }, + { .compatible = "mediatek,mt8365-mcucfg", .data = &mcu_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8365); static struct platform_driver clk_mt8365_drv = { - .probe = clk_mt8365_probe, .driver = { .name = "clk-mt8365", .of_match_table = of_match_clk_mt8365, }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, }; - -static int __init clk_mt8365_init(void) -{ - return platform_driver_register(&clk_mt8365_drv); -} -arch_initcall(clk_mt8365_init); +module_platform_driver(clk_mt8365_drv); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8516-apmixedsys.c b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c new file mode 100644 index 000000000000..edd9174d2f2f --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8516-apmixedsys.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019 MediaTek Inc. + * James Liao <jamesjj.liao@mediatek.com> + * Fabien Parent <fparent@baylibre.com> + * + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#include <dt-bindings/clock/mt8516-clk.h> +#include <linux/clk.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-pll.h" + +#define MT8516_PLL_FMAX (1502UL * MHZ) + +#define CON0_MT8516_RST_BAR BIT(27) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift, _div_table) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = CON0_MT8516_RST_BAR, \ + .fmax = MT8516_PLL_FMAX, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_table = _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + NULL) + +static const struct mtk_pll_div_table mmpll_div_table[] = { + { .div = 0, .freq = MT8516_PLL_FMAX }, + { .div = 1, .freq = 1000000000 }, + { .div = 2, .freq = 604500000 }, + { .div = 3, .freq = 253500000 }, + { .div = 4, .freq = 126750000 }, + { } /* sentinel */ +}; + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, + 21, 0x0104, 24, 0, 0x0104, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, + HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, + HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, + 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), + PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, + 31, 0x0180, 1, 0x0194, 0x0184, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, + 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), +}; + +static int clk_mt8516_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct clk_hw_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (ret) + goto unregister_plls; + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + + return ret; +} + +static const struct of_device_id of_match_clk_mt8516_apmixed[] = { + { .compatible = "mediatek,mt8516-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_apmixed); + +static struct platform_driver clk_mt8516_apmixed_drv = { + .probe = clk_mt8516_apmixed_probe, + .driver = { + .name = "clk-mt8516-apmixed", + .of_match_table = of_match_clk_mt8516_apmixed, + }, +}; +builtin_platform_driver(clk_mt8516_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT8516 apmixedsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/clk-mt8516-aud.c index 00f356fe7c7a..48340fc7430d 100644 --- a/drivers/clk/mediatek/clk-mt8516-aud.c +++ b/drivers/clk/mediatek/clk-mt8516-aud.c @@ -3,6 +3,7 @@ * Copyright (c) 2019 MediaTek Inc. * Author: James Liao <jamesjj.liao@mediatek.com> * Fabien Parent <fparent@baylibre.com> + * Copyright (c) 2023 Collabora Ltd. */ #include <linux/clk-provider.h> @@ -22,16 +23,10 @@ static const struct mtk_gate_regs aud_cg_regs = { .sta_ofs = 0x0, }; -#define GATE_AUD(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &aud_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_AUD(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) -static const struct mtk_gate aud_clks[] __initconst = { +static const struct mtk_gate aud_clks[] = { GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6), GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8), @@ -47,19 +42,26 @@ static const struct mtk_gate aud_clks[] __initconst = { GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27), }; -static void __init mtk_audsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); +static const struct mtk_clk_desc aud_desc = { + .clks = aud_clks, + .num_clks = ARRAY_SIZE(aud_clks), +}; - mtk_clk_register_gates(NULL, node, aud_clks, ARRAY_SIZE(aud_clks), clk_data); +static const struct of_device_id of_match_clk_mt8516_aud[] = { + { .compatible = "mediatek,mt8516-audsys", .data = &aud_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_aud); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static struct platform_driver clk_mt8516_aud_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8516-aud", + .of_match_table = of_match_clk_mt8516_aud, + }, +}; +module_platform_driver(clk_mt8516_aud_drv); -} -CLK_OF_DECLARE(mtk_audsys, "mediatek,mt8516-audsys", mtk_audsys_init); +MODULE_DESCRIPTION("MediaTek MT8516 audiosys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 2c0cae7b3bcf..21eb052b0a53 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -3,6 +3,7 @@ * Copyright (c) 2019 MediaTek Inc. * Author: James Liao <jamesjj.liao@mediatek.com> * Fabien Parent <fparent@baylibre.com> + * Copyright (c) 2023 Collabora Ltd. */ #include <linux/delay.h> @@ -10,10 +11,10 @@ #include <linux/of_address.h> #include <linux/slab.h> #include <linux/mfd/syscon.h> +#include <linux/platform_device.h> #include "clk-gate.h" #include "clk-mtk.h" -#include "clk-pll.h" #include <dt-bindings/clock/mt8516-clk.h> @@ -525,59 +526,23 @@ static const struct mtk_gate_regs top5_cg_regs = { .sta_ofs = 0x44, }; -#define GATE_TOP1(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top1_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_TOP2(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_TOP2_I(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top2_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } - -#define GATE_TOP3(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top3_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_TOP4_I(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top4_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr_inv, \ - } - -#define GATE_TOP5(_id, _name, _parent, _shift) { \ - .id = _id, \ - .name = _name, \ - .parent_name = _parent, \ - .regs = &top5_cg_regs, \ - .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr, \ - } +#define GATE_TOP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_TOP2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_TOP2_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_TOP3(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_TOP4_I(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_TOP5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate top_clks[] __initconst = { /* TOP1 */ @@ -675,139 +640,42 @@ static const struct mtk_gate top_clks[] __initconst = { GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8), }; -static void __init mtk_topckgen_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); +static const struct mtk_clk_desc topck_desc = { + .clks = top_clks, + .num_clks = ARRAY_SIZE(top_clks), + .fixed_clks = fixed_clks, + .num_fixed_clks = ARRAY_SIZE(fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .composite_clks = top_muxes, + .num_composite_clks = ARRAY_SIZE(top_muxes), + .divider_clks = top_adj_divs, + .num_divider_clks = ARRAY_SIZE(top_adj_divs), + .clk_lock = &mt8516_clk_lock, +}; - mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), - clk_data); - mtk_clk_register_gates(NULL, node, top_clks, ARRAY_SIZE(top_clks), clk_data); +static const struct mtk_clk_desc infra_desc = { + .composite_clks = ifr_muxes, + .num_composite_clks = ARRAY_SIZE(ifr_muxes), + .clk_lock = &mt8516_clk_lock, +}; - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_composites(NULL, top_muxes, - ARRAY_SIZE(top_muxes), base, - &mt8516_clk_lock, clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt8516_clk_lock, clk_data); +static const struct of_device_id of_match_clk_mt8516[] = { + { .compatible = "mediatek,mt8516-topckgen", .data = &topck_desc }, + { .compatible = "mediatek,mt8516-infracfg", .data = &infra_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8516); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init); - -static void __init mtk_infracfg_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); - - mtk_clk_register_composites(NULL, ifr_muxes, - ARRAY_SIZE(ifr_muxes), base, - &mt8516_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init); - -#define MT8516_PLL_FMAX (1502UL * MHZ) - -#define CON0_MT8516_RST_BAR BIT(27) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift, _div_table) { \ - .id = _id, \ - .name = _name, \ - .reg = _reg, \ - .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, \ - .flags = _flags, \ - .rst_bar_mask = CON0_MT8516_RST_BAR, \ - .fmax = MT8516_PLL_FMAX, \ - .pcwbits = _pcwbits, \ - .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, \ - .tuner_reg = _tuner_reg, \ - .pcw_reg = _pcw_reg, \ - .pcw_shift = _pcw_shift, \ - .div_table = _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - NULL) - -static const struct mtk_pll_div_table mmpll_div_table[] = { - { .div = 0, .freq = MT8516_PLL_FMAX }, - { .div = 1, .freq = 1000000000 }, - { .div = 2, .freq = 604500000 }, - { .div = 3, .freq = 253500000 }, - { .div = 4, .freq = 126750000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0, - 21, 0x0104, 24, 0, 0x0104, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0, - HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000, - HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0, - 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table), - PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0, - 31, 0x0180, 1, 0x0194, 0x0184, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0, - 31, 0x01A0, 1, 0x01B4, 0x01A4, 0), -}; - -static void __init mtk_apmixedsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } - - clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); +static struct platform_driver clk_mt8516_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8516", + .of_match_table = of_match_clk_mt8516, + }, +}; +module_platform_driver(clk_mt8516_drv); -} -CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8516-apmixedsys", - mtk_apmixedsys_init); +MODULE_DESCRIPTION("MediaTek MT8516 clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 14e8b64a32a3..fd2214c3242f 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -12,7 +12,6 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> @@ -394,7 +393,8 @@ void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_composites); -int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, +int mtk_clk_register_dividers(struct device *dev, + const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_hw_onecell_data *clk_data) { @@ -413,7 +413,7 @@ int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, continue; } - hw = clk_hw_register_divider(NULL, mcd->name, mcd->parent_name, + hw = clk_hw_register_divider(dev, mcd->name, mcd->parent_name, mcd->flags, base + mcd->div_reg, mcd->div_shift, mcd->div_width, mcd->clk_divider_flags, lock); @@ -463,17 +463,25 @@ void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_dividers); -int mtk_clk_simple_probe(struct platform_device *pdev) +static int __mtk_clk_simple_probe(struct platform_device *pdev, + struct device_node *node) { + const struct platform_device_id *id; const struct mtk_clk_desc *mcd; struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; void __iomem *base; int num_clks, r; - mcd = of_device_get_match_data(&pdev->dev); - if (!mcd) - return -EINVAL; + mcd = device_get_match_data(&pdev->dev); + if (!mcd) { + /* Clock driver wasn't registered from devicetree */ + id = platform_get_device_id(pdev); + if (id) + mcd = (const struct mtk_clk_desc *)id->driver_data; + + if (!mcd) + return -EINVAL; + } /* Composite clocks needs us to pass iomem pointer */ if (mcd->composite_clks) { @@ -489,7 +497,7 @@ int mtk_clk_simple_probe(struct platform_device *pdev) /* Calculate how many clk_hw_onecell_data entries to allocate */ num_clks = mcd->num_clks + mcd->num_composite_clks; num_clks += mcd->num_fixed_clks + mcd->num_factor_clks; - num_clks += mcd->num_mux_clks; + num_clks += mcd->num_mux_clks + mcd->num_divider_clks; clk_data = mtk_alloc_clk_data(num_clks); if (!clk_data) @@ -527,11 +535,20 @@ int mtk_clk_simple_probe(struct platform_device *pdev) goto unregister_muxes; } + if (mcd->divider_clks) { + r = mtk_clk_register_dividers(&pdev->dev, + mcd->divider_clks, + mcd->num_divider_clks, + base, mcd->clk_lock, clk_data); + if (r) + goto unregister_composites; + } + if (mcd->clks) { r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks, clk_data); if (r) - goto unregister_composites; + goto unregister_dividers; } if (mcd->clk_notifier_func) { @@ -560,6 +577,10 @@ int mtk_clk_simple_probe(struct platform_device *pdev) unregister_clks: if (mcd->clks) mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); +unregister_dividers: + if (mcd->divider_clks) + mtk_clk_unregister_dividers(mcd->divider_clks, + mcd->num_divider_clks, clk_data); unregister_composites: if (mcd->composite_clks) mtk_clk_unregister_composites(mcd->composite_clks, @@ -582,17 +603,19 @@ free_data: iounmap(base); return r; } -EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); -int mtk_clk_simple_remove(struct platform_device *pdev) +static int __mtk_clk_simple_remove(struct platform_device *pdev, + struct device_node *node) { - const struct mtk_clk_desc *mcd = of_device_get_match_data(&pdev->dev); struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - struct device_node *node = pdev->dev.of_node; + const struct mtk_clk_desc *mcd = device_get_match_data(&pdev->dev); of_clk_del_provider(node); if (mcd->clks) mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); + if (mcd->divider_clks) + mtk_clk_unregister_dividers(mcd->divider_clks, + mcd->num_divider_clks, clk_data); if (mcd->composite_clks) mtk_clk_unregister_composites(mcd->composite_clks, mcd->num_composite_clks, clk_data); @@ -609,6 +632,37 @@ int mtk_clk_simple_remove(struct platform_device *pdev) return 0; } + +int mtk_clk_pdev_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->parent->of_node; + + return __mtk_clk_simple_probe(pdev, node); +} +EXPORT_SYMBOL_GPL(mtk_clk_pdev_probe); + +int mtk_clk_simple_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + + return __mtk_clk_simple_probe(pdev, node); +} +EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); + +int mtk_clk_pdev_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->parent->of_node; + + return __mtk_clk_simple_remove(pdev, node); +} +EXPORT_SYMBOL_GPL(mtk_clk_pdev_remove); + +int mtk_clk_simple_remove(struct platform_device *pdev) +{ + return __mtk_clk_simple_remove(pdev, pdev->dev.of_node); +} EXPORT_SYMBOL_GPL(mtk_clk_simple_remove); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 41f4fa3b0c21..b7a751861fce 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -202,7 +202,8 @@ struct mtk_clk_divider { .div_width = _width, \ } -int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, +int mtk_clk_register_dividers(struct device *dev, + const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_hw_onecell_data *clk_data); void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num, @@ -222,6 +223,8 @@ struct mtk_clk_desc { size_t num_clks; const struct mtk_composite *composite_clks; size_t num_composite_clks; + const struct mtk_clk_divider *divider_clks; + size_t num_divider_clks; const struct mtk_fixed_clk *fixed_clks; size_t num_fixed_clks; const struct mtk_fixed_factor *factor_clks; @@ -236,6 +239,8 @@ struct mtk_clk_desc { unsigned int mfg_clk_idx; }; +int mtk_clk_pdev_probe(struct platform_device *pdev); +int mtk_clk_pdev_remove(struct platform_device *pdev); int mtk_clk_simple_probe(struct platform_device *pdev); int mtk_clk_simple_remove(struct platform_device *pdev); diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c index f48780bec507..3a2b3f90be25 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -75,13 +75,13 @@ void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs, base = of_iomap(node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); - return; + goto out_node_put; } num_clocks = of_clk_get_parent_count(node); if (!num_clocks) { pr_err("%s(): failed to get clocks property\n", __func__); - return; + goto err; } for (i = 0; i < num_clocks; i++) { @@ -102,16 +102,26 @@ void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs, pllfh->state.ssc_rate = ssc_rate; pllfh->state.base = base; } + +out_node_put: + of_node_put(node); + return; +err: + iounmap(base); + goto out_node_put; } +EXPORT_SYMBOL_GPL(fhctl_parse_dt); -static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data) +static int pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data) { struct fh_pll_regs *regs = &fh->regs; const struct fhctl_offset *offset; void __iomem *base = pllfh_data->state.base; void __iomem *fhx_base = base + pllfh_data->data.fhx_offset; - offset = fhctl_get_offset_table(); + offset = fhctl_get_offset_table(pllfh_data->data.fh_ver); + if (IS_ERR(offset)) + return PTR_ERR(offset); regs->reg_hp_en = base + offset->offset_hp_en; regs->reg_clk_con = base + offset->offset_clk_con; @@ -129,6 +139,8 @@ static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data) fh->lock = &pllfh_lock; fh->ops = fhctl_get_ops(); + + return 0; } static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh) @@ -142,20 +154,29 @@ mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data, { struct clk_hw *hw; struct mtk_fh *fh; + int ret; fh = kzalloc(sizeof(*fh), GFP_KERNEL); if (!fh) return ERR_PTR(-ENOMEM); - pllfh_init(fh, pllfh_data); + ret = pllfh_init(fh, pllfh_data); + if (ret) { + hw = ERR_PTR(ret); + goto out; + } hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, &mtk_pllfh_ops); if (IS_ERR(hw)) + goto out; + + fhctl_hw_init(fh); + +out: + if (IS_ERR(hw)) kfree(fh); - else - fhctl_hw_init(fh); return hw; } @@ -234,6 +255,7 @@ err: return PTR_ERR(hw); } +EXPORT_SYMBOL_GPL(mtk_clk_register_pllfhs); void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls, struct mtk_pllfh_data *pllfhs, int num_fhs, @@ -273,3 +295,4 @@ void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls, iounmap(base); } +EXPORT_SYMBOL_GPL(mtk_clk_unregister_pllfhs); diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pllfh.h index c0a6e1537034..5f419c2ec01f 100644 --- a/drivers/clk/mediatek/clk-pllfh.h +++ b/drivers/clk/mediatek/clk-pllfh.h @@ -18,6 +18,7 @@ struct fh_pll_state { struct fh_pll_data { int pll_id; int fh_id; + int fh_ver; u32 fhx_offset; u32 dds_mask; u32 slope0_value; diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 4f0a19db7ed7..cc5d7dee59f0 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -374,14 +374,13 @@ static void mpfs_reset_unregister_adev(void *_adev) struct auxiliary_device *adev = _adev; auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); } static void mpfs_reset_adev_release(struct device *dev) { struct auxiliary_device *adev = to_auxiliary_dev(dev); - auxiliary_device_uninit(adev); - kfree(adev); } diff --git a/drivers/clk/mmp/clk-audio.c b/drivers/clk/mmp/clk-audio.c index 7aa7f4a9564f..6fb1aa9487b5 100644 --- a/drivers/clk/mmp/clk-audio.c +++ b/drivers/clk/mmp/clk-audio.c @@ -384,12 +384,10 @@ disable_pm_runtime: return ret; } -static int mmp2_audio_clk_remove(struct platform_device *pdev) +static void mmp2_audio_clk_remove(struct platform_device *pdev) { pm_clk_destroy(&pdev->dev); pm_runtime_disable(&pdev->dev); - - return 0; } #ifdef CONFIG_PM @@ -436,7 +434,7 @@ static struct platform_driver mmp2_audio_clk_driver = { .pm = &mmp2_audio_clk_pm_ops, }, .probe = mmp2_audio_clk_probe, - .remove = mmp2_audio_clk_remove, + .remove_new = mmp2_audio_clk_remove, }; module_platform_driver(mmp2_audio_clk_driver); diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index e3777ca65912..3ae6078f6ff7 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -781,7 +781,7 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev) return 0; } -static int armada_3700_periph_clock_remove(struct platform_device *pdev) +static void armada_3700_periph_clock_remove(struct platform_device *pdev) { struct clk_periph_driver_data *data = platform_get_drvdata(pdev); struct clk_hw_onecell_data *hw_data = data->hw_data; @@ -791,13 +791,11 @@ static int armada_3700_periph_clock_remove(struct platform_device *pdev) for (i = 0; i < hw_data->num; i++) clk_hw_unregister(hw_data->hws[i]); - - return 0; } static struct platform_driver armada_3700_periph_clock_driver = { .probe = armada_3700_periph_clock_probe, - .remove = armada_3700_periph_clock_remove, + .remove_new = armada_3700_periph_clock_remove, .driver = { .name = "marvell-armada-3700-periph-clock", .of_match_table = armada_3700_periph_clock_of_match, diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c index fc403ad735ad..eccc1aeefbaf 100644 --- a/drivers/clk/mvebu/armada-37xx-tbg.c +++ b/drivers/clk/mvebu/armada-37xx-tbg.c @@ -126,7 +126,7 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev) return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, hw_tbg_data); } -static int armada_3700_tbg_clock_remove(struct platform_device *pdev) +static void armada_3700_tbg_clock_remove(struct platform_device *pdev) { int i; struct clk_hw_onecell_data *hw_tbg_data = platform_get_drvdata(pdev); @@ -134,8 +134,6 @@ static int armada_3700_tbg_clock_remove(struct platform_device *pdev) of_clk_del_provider(pdev->dev.of_node); for (i = 0; i < hw_tbg_data->num; i++) clk_hw_unregister_fixed_factor(hw_tbg_data->hws[i]); - - return 0; } static const struct of_device_id armada_3700_tbg_clock_of_match[] = { @@ -145,7 +143,7 @@ static const struct of_device_id armada_3700_tbg_clock_of_match[] = { static struct platform_driver armada_3700_tbg_clock_driver = { .probe = armada_3700_tbg_clock_probe, - .remove = armada_3700_tbg_clock_remove, + .remove_new = armada_3700_tbg_clock_remove, .driver = { .name = "marvell-armada-3700-tbg-clock", .of_match_table = armada_3700_tbg_clock_of_match, diff --git a/drivers/clk/mvebu/armada-37xx-xtal.c b/drivers/clk/mvebu/armada-37xx-xtal.c index 41271351cf1f..0e2e7d00ae11 100644 --- a/drivers/clk/mvebu/armada-37xx-xtal.c +++ b/drivers/clk/mvebu/armada-37xx-xtal.c @@ -65,11 +65,9 @@ static int armada_3700_xtal_clock_probe(struct platform_device *pdev) return ret; } -static int armada_3700_xtal_clock_remove(struct platform_device *pdev) +static void armada_3700_xtal_clock_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - - return 0; } static const struct of_device_id armada_3700_xtal_clock_of_match[] = { @@ -79,7 +77,7 @@ static const struct of_device_id armada_3700_xtal_clock_of_match[] = { static struct platform_driver armada_3700_xtal_clock_driver = { .probe = armada_3700_xtal_clock_probe, - .remove = armada_3700_xtal_clock_remove, + .remove_new = armada_3700_xtal_clock_remove, .driver = { .name = "marvell-armada-3700-xtal-clock", .of_match_table = armada_3700_xtal_clock_of_match, diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index 0f59c84229a8..7e90e94c4b68 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = { DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), /* Core Clock Outputs */ + DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1), DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index 06f925aff407..aaa685ec35df 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -72,6 +72,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ + DEF_FIXED("z2", R8A77980_CLK_Z2, CLK_PLL2, 4, 1), DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -150,11 +151,27 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1), DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1), DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1), + DEF_MOD("vin15", 604, R8A77980_CLK_S2D1), + DEF_MOD("vin14", 605, R8A77980_CLK_S2D1), + DEF_MOD("vin13", 608, R8A77980_CLK_S2D1), + DEF_MOD("vin12", 612, R8A77980_CLK_S2D1), + DEF_MOD("vin11", 618, R8A77980_CLK_S2D1), DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1), + DEF_MOD("vin10", 625, R8A77980_CLK_S2D1), + DEF_MOD("vin9", 627, R8A77980_CLK_S2D1), + DEF_MOD("vin8", 628, R8A77980_CLK_S2D1), DEF_MOD("csi41", 715, R8A77980_CLK_CSI0), DEF_MOD("csi40", 716, R8A77980_CLK_CSI0), DEF_MOD("du0", 724, R8A77980_CLK_S2D1), DEF_MOD("lvds", 727, R8A77980_CLK_S2D1), + DEF_MOD("vin7", 804, R8A77980_CLK_S2D1), + DEF_MOD("vin6", 805, R8A77980_CLK_S2D1), + DEF_MOD("vin5", 806, R8A77980_CLK_S2D1), + DEF_MOD("vin4", 807, R8A77980_CLK_S2D1), + DEF_MOD("vin3", 808, R8A77980_CLK_S2D1), + DEF_MOD("vin2", 809, R8A77980_CLK_S2D1), + DEF_MOD("vin1", 810, R8A77980_CLK_S2D1), + DEF_MOD("vin0", 811, R8A77980_CLK_S2D1), DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2), DEF_MOD("gether", 813, R8A77980_CLK_S3D2), DEF_MOD("imp3", 824, R8A77980_CLK_S1D1), @@ -173,6 +190,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { DEF_MOD("gpio0", 912, R8A77980_CLK_CP), DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2), DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2), + DEF_MOD("i2c5", 919, R8A77980_CLK_S0D6), DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6), DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6), DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2), diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 24ba9093a72f..3a73f6f911dd 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { DEF_MOD("du0", 724, R8A77995_CLK_S1D1), DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), DEF_MOD("mlp", 802, R8A77995_CLK_S2D1), - DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), + DEF_MOD("vin4", 807, R8A77995_CLK_S3D1), DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4), diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index 7fca11204f74..7cc580d67362 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -146,6 +146,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1), DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1), DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), + DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880), DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1), DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884), @@ -165,6 +166,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC), DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2), + DEF_MOD("csi40", 331, R8A779G0_CLK_CSI), + DEF_MOD("csi41", 400, R8A779G0_CLK_CSI), DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2), DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2), DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2), @@ -181,6 +184,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER), DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER), DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M), + DEF_MOD("ispcs0", 612, R8A779G0_CLK_S0D2_VIO), + DEF_MOD("ispcs1", 613, R8A779G0_CLK_S0D2_VIO), DEF_MOD("msi0", 618, R8A779G0_CLK_MSO), DEF_MOD("msi1", 619, R8A779G0_CLK_MSO), DEF_MOD("msi2", 620, R8A779G0_CLK_MSO), @@ -202,6 +207,22 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2), DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4), + DEF_MOD("vin00", 730, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin01", 731, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin02", 800, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin03", 801, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin04", 802, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin05", 803, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin06", 804, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin07", 805, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin10", 806, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin11", 807, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin12", 808, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin13", 809, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin14", 810, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin15", 811, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin16", 812, R8A779G0_CLK_S0D4_VIO), + DEF_MOD("vin17", 813, R8A779G0_CLK_S0D4_VIO), DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2), DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2), DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R), @@ -213,6 +234,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M), DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M), DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M), + DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M), + DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER), + DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER), }; /* diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 087146f2ee06..40828616f723 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -29,69 +29,189 @@ #define R9A06G032_SYSCTRL_USB_H2MODE (1<<1) #define R9A06G032_SYSCTRL_DMAMUX 0xA0 +/** + * struct regbit - describe one bit in a register + * @reg: offset of register relative to base address, + * expressed in units of 32-bit words (not bytes), + * @bit: which bit (0 to 31) in the register + * + * This structure is used to compactly encode the location + * of a single bit in a register. Five bits are needed to + * encode the bit number. With uint16_t data type, this + * leaves 11 bits to encode a register offset up to 2047. + * + * Since registers are aligned on 32-bit boundaries, the + * offset will be specified in 32-bit words rather than bytes. + * This allows encoding an offset up to 0x1FFC (8188) bytes. + * + * Helper macro RB() takes care of converting the register + * offset from bytes to 32-bit words. + */ +struct regbit { + u16 bit:5; + u16 reg:11; +}; + +#define RB(_reg, _bit) ((struct regbit) { \ + .reg = (_reg) / 4, \ + .bit = (_bit) \ +}) + +/** + * struct r9a06g032_gate - clock-related control bits + * @gate: clock enable/disable + * @reset: clock module reset (active low) + * @ready: enables NoC forwarding of read/write requests to device, + * (eg. device is ready to handle read/write requests) + * @midle: request to idle the NoC interconnect + * + * Each of these fields describes a single bit in a register, + * which controls some aspect of clock gating. The @gate field + * is mandatory, this one enables/disables the clock. The + * other fields are optional, with zero indicating "not used". + * + * In most cases there is a @reset bit which needs to be + * de-asserted to bring the module out of reset. + * + * Modules may also need to signal when they are @ready to + * handle requests (read/writes) from the NoC interconnect. + * + * Similarly, the @midle bit is used to idle the master. + */ struct r9a06g032_gate { - u16 gate, reset, ready, midle, - scon, mirack, mistat; + struct regbit gate, reset, ready, midle; + /* Unused fields omitted to save space */ + /* struct regbit scon, mirack, mistat */; +}; + +enum gate_type { + K_GATE = 0, /* gate which enable/disable */ + K_FFC, /* fixed factor clock */ + K_DIV, /* divisor */ + K_BITSEL, /* special for UARTs */ + K_DUALGATE /* special for UARTs */ }; -/* This is used to describe a clock for instantiation */ +/** + * struct r9a06g032_clkdesc - describe a single clock + * @name: string describing this clock + * @managed: boolean indicating if this clock should be + * started/stopped as part of power management + * @type: see enum @gate_type + * @index: the ID of this clock element + * @source: the ID+1 of the parent clock element. + * Root clock uses ID of ~0 (PARENT_ID); + * @gate: clock enable/disable + * @div_min: smallest permitted clock divider + * @div_max: largest permitted clock divider + * @reg: clock divider register offset, in 32-bit words + * @div_table: optional list of fixed clock divider values; + * must be in ascending order, zero for unused + * @div: divisor for fixed-factor clock + * @mul: multiplier for fixed-factor clock + * @group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7 + * @sel: select either g1/r1 or g2/r2 as clock source + * @g1: 1st source gate (clock enable/disable) + * @r1: 1st source reset (module reset) + * @g2: 2nd source gate (clock enable/disable) + * @r2: 2nd source reset (module reset) + * + * Describes a single element in the clock tree hierarchy. + * As there are quite a large number of clock elements, this + * structure is packed tightly to conserve space. + */ struct r9a06g032_clkdesc { const char *name; - uint32_t managed: 1; - uint32_t type: 3; - uint32_t index: 8; - uint32_t source : 8; /* source index + 1 (0 == none) */ - /* these are used to populate the bitsel struct */ + uint32_t managed:1; + enum gate_type type:3; + uint32_t index:8; + uint32_t source:8; /* source index + 1 (0 == none) */ union { + /* type = K_GATE */ struct r9a06g032_gate gate; - /* for dividers */ + /* type = K_DIV */ struct { - unsigned int div_min : 10, div_max : 10, reg: 10; + unsigned int div_min:10, div_max:10, reg:10; u16 div_table[4]; }; - /* For fixed-factor ones */ + /* type = K_FFC */ struct { u16 div, mul; }; - /* for dual gate */ + /* type = K_DUALGATE */ struct { - uint16_t group : 1; - u16 sel, g1, r1, g2, r2; + uint16_t group:1; + struct regbit sel, g1, r1, g2, r2; } dual; }; }; -#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \ - { .gate = _clk, .reset = _rst, \ - .ready = _rdy, .midle = _midle, \ - .scon = _scon, .mirack = _mirack, .mistat = _mistat } -#define D_GATE(_idx, _n, _src, ...) \ - { .type = K_GATE, .index = R9A06G032_##_idx, \ - .source = 1 + R9A06G032_##_src, .name = _n, \ - .gate = I_GATE(__VA_ARGS__) } -#define D_MODULE(_idx, _n, _src, ...) \ - { .type = K_GATE, .index = R9A06G032_##_idx, \ - .source = 1 + R9A06G032_##_src, .name = _n, \ - .managed = 1, .gate = I_GATE(__VA_ARGS__) } -#define D_ROOT(_idx, _n, _mul, _div) \ - { .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \ - .div = _div, .mul = _mul } -#define D_FFC(_idx, _n, _src, _div) \ - { .type = K_FFC, .index = R9A06G032_##_idx, \ - .source = 1 + R9A06G032_##_src, .name = _n, \ - .div = _div, .mul = 1} -#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \ - { .type = K_DIV, .index = R9A06G032_##_idx, \ - .source = 1 + R9A06G032_##_src, .name = _n, \ - .reg = _reg, .div_min = _min, .div_max = _max, \ - .div_table = { __VA_ARGS__ } } -#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \ - { .type = K_DUALGATE, .index = R9A06G032_##_idx, \ - .source = 1 + R9A06G032_##_src, .name = _n, \ - .dual = { .group = _g, \ - .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, } - -enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE }; +/* + * The last three arguments are not currently used, + * but are kept in the r9a06g032_clocks table below. + */ +#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \ + .gate = _clk, \ + .reset = _rst, \ + .ready = _rdy, \ + .midle = _midle, \ + /* .scon = _scon, */ \ + /* .mirack = _mirack, */ \ + /* .mistat = _mistat */ \ +} +#define D_GATE(_idx, _n, _src, ...) { \ + .type = K_GATE, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .gate = I_GATE(__VA_ARGS__) \ +} +#define D_MODULE(_idx, _n, _src, ...) { \ + .type = K_GATE, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .managed = 1, \ + .gate = I_GATE(__VA_ARGS__) \ +} +#define D_ROOT(_idx, _n, _mul, _div) { \ + .type = K_FFC, \ + .index = R9A06G032_##_idx, \ + .name = _n, \ + .div = _div, \ + .mul = _mul \ +} +#define D_FFC(_idx, _n, _src, _div) { \ + .type = K_FFC, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .div = _div, \ + .mul = 1 \ +} +#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \ + .type = K_DIV, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .reg = _reg, \ + .div_min = _min, \ + .div_max = _max, \ + .div_table = { __VA_ARGS__ } \ +} +#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \ + .type = K_DUALGATE, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .dual = { \ + .group = _g, \ + .g1 = _g1, \ + .r1 = _r1, \ + .g2 = _g2, \ + .r2 = _r2 \ + }, \ +} /* Internal clock IDs */ #define R9A06G032_CLKOUT 0 @@ -160,58 +280,160 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128), D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40), D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128), - D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0), - D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0), - D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0), - D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0), - D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0), - D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0), - D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0), - D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0), - D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0), - D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0), - D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0), - D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0), - D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0), - D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0), - D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0), - D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0), - D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0), - D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0), - D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0), - D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0), - D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0), - D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0), - D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0), - D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0), - D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0), - D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0), - D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0), - D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0), - D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0), + D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9), + RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0), + RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12), + RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0), + RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15), + RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0), + RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18), + RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0), + RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21), + RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0), + RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10), + RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6), + RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8), + RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4), + RB(0x50, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20), + RB(0xec, 21), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2), + RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4), + RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6), + RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4), + RB(0x104, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6), + RB(0x104, 7), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0), + RB(0x114, 1), RB(0x114, 2), RB(0x00, 0), + RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3), + RB(0x114, 4), RB(0x114, 5), RB(0x00, 0), + RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6), + RB(0x114, 7), RB(0x114, 8), RB(0x00, 0), + RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9), + RB(0x114, 10), RB(0x114, 11), RB(0x00, 0), + RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4), + RB(0x54, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4), + RB(0x90, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0), + RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0), + RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2), + RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4), + RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6), + RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0), + RB(0x104, 1), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2), + RB(0x104, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2), + RB(0x130, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8), - D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441), - D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0), - D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461), - D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0), - D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0), - D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0), - D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0), - D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0), - D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103), - D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101), - D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0), - D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05), - D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0), + D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0), + RB(0x80, 1), RB(0x00, 0), RB(0x80, 2), + RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)), + D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0), + RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0), + RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0), + RB(0x84, 2), RB(0x00, 0), RB(0x84, 1), + RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)), + D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3), + RB(0x118, 4), RB(0x118, 5), RB(0x00, 0), + RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6), + RB(0x118, 7), RB(0x118, 8), RB(0x00, 0), + RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9), + RB(0x118, 10), RB(0x118, 11), RB(0x00, 0), + RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3), + RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0), + RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6), + RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0), + RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3), + RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4), + RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)), + D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0), + RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2), + RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)), + D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12), + RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14), + RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)), + D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9), + RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0), + RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)), D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4), D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4), D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2), @@ -219,67 +441,187 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8), D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2), D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4), - D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0), - D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0), - D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0), - D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0), - D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0), - D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0), - D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0), + D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3), + RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0), + RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6), + RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0), + RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15), + RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12), + RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0), + RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0), + RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0), + RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3), + RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640), - D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1), - D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0), - D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0), - D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0), - D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0), - D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0), - D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0), - D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0), - D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0), - D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141), - D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1), - D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2), - D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5), - D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2), - D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2), - D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0), - D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0), - D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0), - D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1), - D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0), - D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0), - D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0), - D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0), - D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182), - D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2), - D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25), - D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0), - D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0), - D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0), - D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0), - D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302), - D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2), - D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0), - D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0xa03, 0, 0xa02, 0, 0, 0), - D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82), - D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662), - D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0), - D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0), - D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0), - D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0), - D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0), - D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0), - D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0), - D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0), - D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0), - D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0), - D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0), - D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0), - D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0), - D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0), - D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0), - D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0), - D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0), + D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0), + RB(0x174, 1), RB(0x00, 0), RB(0x174, 2), + RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)), + D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3), + RB(0x64, 4), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3), + RB(0x80, 4), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4), + RB(0x90, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0), + RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4), + RB(0x84, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15), + RB(0x34, 16), RB(0x34, 17), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0), + RB(0x184, 1), RB(0x184, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3), + RB(0x24, 4), RB(0x24, 5), RB(0x00, 0), + RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0), + RB(0x24, 1), RB(0x00, 0), RB(0x24, 2), + RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)), + D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0), + RB(0x64, 2), RB(0x00, 0), RB(0x64, 1), + RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)), + D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0), + RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3), + RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)), + D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4), + RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7), + RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)), + D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0), + RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3), + RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)), + D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0), + RB(0x70, 1), RB(0x70, 2), RB(0x70, 3), + RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)), + D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18), + RB(0x40, 19), RB(0x40, 20), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21), + RB(0x40, 22), RB(0x40, 23), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9), + RB(0x44, 10), RB(0x44, 11), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0), + RB(0x90, 2), RB(0x00, 0), RB(0x90, 1), + RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)), + D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9), + RB(0x34, 10), RB(0x34, 11), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12), + RB(0x34, 13), RB(0x34, 14), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0), + RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0), + RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4), + RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0), + RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0), + RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3), + RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)), + D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0), + RB(0x50, 1), RB(0x50, 2), RB(0x50, 3), + RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)), + D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12), + RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14), + RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)), + D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12), + RB(0x44, 13), RB(0x44, 14), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15), + RB(0x44, 16), RB(0x44, 17), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6), + RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0), + RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9), + RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0), + RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0), + RB(0x54, 1), RB(0x54, 2), RB(0x54, 3), + RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)), + D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0), + RB(0x90, 1), RB(0x90, 2), RB(0x90, 3), + RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)), + D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0), + RB(0x154, 1), RB(0x154, 2), RB(0x00, 0), + RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0), + RB(0x140, 3), RB(0x00, 0), RB(0x140, 2), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0), + RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3), + RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)), + D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0), + RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3), + RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)), + D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3), + RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0), + RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0), + RB(0x40, 1), RB(0x40, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3), + RB(0x40, 4), RB(0x40, 5), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6), + RB(0x40, 7), RB(0x40, 8), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9), + RB(0x40, 10), RB(0x40, 11), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12), + RB(0x40, 13), RB(0x40, 14), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15), + RB(0x40, 16), RB(0x40, 17), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0), + RB(0x00, 0), RB(0x130, 1), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0), + RB(0x188, 1), RB(0x188, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0), + RB(0x34, 1), RB(0x34, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3), + RB(0x34, 4), RB(0x34, 5), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6), + RB(0x34, 7), RB(0x34, 8), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24), + RB(0x40, 25), RB(0x40, 26), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27), + RB(0x40, 28), RB(0x40, 29), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0), + RB(0x44, 1), RB(0x44, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3), + RB(0x44, 4), RB(0x44, 5), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6), + RB(0x44, 7), RB(0x44, 8), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), /* * These are not hardware clocks, but are needed to handle the special * case where we have a 'selector bit' that doesn't just change the @@ -291,7 +633,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .type = K_BITSEL, .source = 1 + R9A06G032_DIV_UART, /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ - .dual.sel = ((0x34 / 4) << 5) | 30, + .dual.sel = RB(0x34, 30), .dual.group = 0, }, { @@ -300,17 +642,25 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { .type = K_BITSEL, .source = 1 + R9A06G032_DIV_P2_PG, /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ - .dual.sel = ((0xec / 4) << 5) | 24, + .dual.sel = RB(0xec, 24), .dual.group = 1, }, - D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5), - D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9), - D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd), - D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763), - D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767), - D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b), - D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f), - D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773), + D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, + RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)), + D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, + RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)), + D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, + RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)), + D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, + RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)), + D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, + RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)), + D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, + RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)), + D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, + RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)), + D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, + RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)), }; struct r9a06g032_priv { @@ -343,26 +693,26 @@ int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val) } EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux); -/* register/bit pairs are encoded as an uint16_t */ -static void -clk_rdesc_set(struct r9a06g032_priv *clocks, - u16 one, unsigned int on) +static void clk_rdesc_set(struct r9a06g032_priv *clocks, + struct regbit rb, unsigned int on) { - u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); - u32 val = readl(reg); + u32 __iomem *reg = clocks->reg + (rb.reg * 4); + u32 val; - val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f)); + if (!rb.reg && !rb.bit) + return; + + val = readl(reg); + val = (val & ~BIT(rb.bit)) | ((!!on) << rb.bit); writel(val, reg); } -static int -clk_rdesc_get(struct r9a06g032_priv *clocks, - uint16_t one) +static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb) { - u32 __iomem *reg = clocks->reg + (4 * (one >> 5)); + u32 __iomem *reg = clocks->reg + (rb.reg * 4); u32 val = readl(reg); - return !!(val & (1U << (one & 0x1f))); + return !!(val & BIT(rb.bit)); } /* @@ -464,13 +814,12 @@ r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, { unsigned long flags; - WARN_ON(!g->gate); + WARN_ON(!g->gate.reg && !g->gate.bit); spin_lock_irqsave(&clocks->lock, flags); clk_rdesc_set(clocks, g->gate, on); /* De-assert reset */ - if (g->reset) - clk_rdesc_set(clocks, g->reset, 1); + clk_rdesc_set(clocks, g->reset, 1); spin_unlock_irqrestore(&clocks->lock, flags); /* Hardware manual recommends 5us delay after enabling clock & reset */ @@ -480,15 +829,12 @@ r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, * associated SLVRDY bit in the System Controller that needs to be set * so that the FlexWAY bus fabric passes on the read/write requests. */ - if (g->ready || g->midle) { - spin_lock_irqsave(&clocks->lock, flags); - if (g->ready) - clk_rdesc_set(clocks, g->ready, on); - /* Clear 'Master Idle Request' bit */ - if (g->midle) - clk_rdesc_set(clocks, g->midle, !on); - spin_unlock_irqrestore(&clocks->lock, flags); - } + spin_lock_irqsave(&clocks->lock, flags); + clk_rdesc_set(clocks, g->ready, on); + /* Clear 'Master Idle Request' bit */ + clk_rdesc_set(clocks, g->midle, !on); + spin_unlock_irqrestore(&clocks->lock, flags); + /* Note: We don't wait for FlexWAY Socket Connection signal */ } @@ -512,7 +858,7 @@ static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw) struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw); /* if clock is in reset, the gate might be on, and still not 'be' on */ - if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset)) + if (g->gate.reset.reg && !clk_rdesc_get(g->clocks, g->gate.reset)) return 0; return clk_rdesc_get(g->clocks, g->gate.gate); @@ -751,7 +1097,7 @@ struct r9a06g032_clk_bitsel { struct clk_hw hw; struct r9a06g032_priv *clocks; u16 index; - u16 selector; /* selector register + bit */ + struct regbit selector; /* selector register + bit */ }; #define to_clk_bitselect(_hw) \ @@ -820,7 +1166,7 @@ struct r9a06g032_clk_dualgate { struct clk_hw hw; struct r9a06g032_priv *clocks; u16 index; - u16 selector; /* selector register + bit */ + struct regbit selector; /* selector register + bit */ struct r9a06g032_gate gate[2]; }; @@ -873,7 +1219,7 @@ static struct clk * r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc, - uint16_t sel) + struct regbit sel) { struct r9a06g032_clk_dualgate *g; struct clk *clk; @@ -951,7 +1297,7 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) struct clk **clks; struct clk *mclk; unsigned int i; - u16 uart_group_sel[2]; + struct regbit uart_group_sel[2]; int error; clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL); diff --git a/drivers/clk/renesas/rcar-usb2-clock-sel.c b/drivers/clk/renesas/rcar-usb2-clock-sel.c index 684d8937965e..17c110978e33 100644 --- a/drivers/clk/renesas/rcar-usb2-clock-sel.c +++ b/drivers/clk/renesas/rcar-usb2-clock-sel.c @@ -125,15 +125,13 @@ static int rcar_usb2_clock_sel_resume(struct device *dev) return 0; } -static int rcar_usb2_clock_sel_remove(struct platform_device *pdev) +static void rcar_usb2_clock_sel_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; of_clk_del_provider(dev->of_node); pm_runtime_put(dev); pm_runtime_disable(dev); - - return 0; } static int rcar_usb2_clock_sel_probe(struct platform_device *pdev) @@ -215,7 +213,7 @@ static struct platform_driver rcar_usb2_clock_sel_driver = { .pm = &rcar_usb2_clock_sel_pm_ops, }, .probe = rcar_usb2_clock_sel_probe, - .remove = rcar_usb2_clock_sel_remove, + .remove_new = rcar_usb2_clock_sel_remove, }; builtin_platform_driver(rcar_usb2_clock_sel_driver); diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index b9f210437ddf..9927bc0dde97 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -61,7 +61,7 @@ static const u16 mstpsr_for_gen4[] = { 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C, 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C, 0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C, - 0x2E60, 0x2E64, 0x2E68, 0x2E6C, + 0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74, }; /* @@ -77,7 +77,7 @@ static const u16 mstpcr_for_gen4[] = { 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C, 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C, 0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C, - 0x2D60, 0x2D64, 0x2D68, 0x2D6C, + 0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74, }; /* @@ -103,7 +103,7 @@ static const u16 srcr_for_gen4[] = { 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C, 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C, 0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C, - 0x2C60, 0x2C64, 0x2C68, 0x2C6C, + 0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74, }; /* @@ -119,7 +119,7 @@ static const u16 srstclr_for_gen4[] = { 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C, 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC, 0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC, - 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, + 0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4, }; /** diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index b7fde0aadfcb..2322f634a910 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -2,8 +2,8 @@ menuconfig CLK_SIFIVE bool "SiFive SoC driver support" - depends on SOC_SIFIVE || COMPILE_TEST - default SOC_SIFIVE + depends on ARCH_SIFIVE || COMPILE_TEST + default ARCH_SIFIVE help SoC drivers for SiFive Linux-capable SoCs. @@ -11,7 +11,7 @@ if CLK_SIFIVE config CLK_SIFIVE_PRCI bool "PRCI driver for SiFive SoCs" - default SOC_SIFIVE + default ARCH_SIFIVE select RESET_CONTROLLER select RESET_SIMPLE select CLK_ANALOGBITS_WRPLL_CLN28HPC diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 7cdf2f07c79b..06f129c160bc 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -40,7 +40,7 @@ static struct clk_ops gateclk_ops = { }; static void __init __socfpga_gate_init(struct device_node *node, - const struct clk_ops *ops) + const struct clk_ops *ops) { u32 clk_gate[2]; u32 div_reg[3]; @@ -94,13 +94,25 @@ static void __init __socfpga_gate_init(struct device_node *node, socfpga_clk->hw.hw.init = &init; hw_clk = &socfpga_clk->hw.hw; - if (clk_hw_register(NULL, hw_clk)) { - kfree(socfpga_clk); - return; + rc = clk_hw_register(NULL, hw_clk); + if (rc) { + pr_err("Could not register clock:%s\n", clk_name); + goto err_clk_hw_register; } - rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); - if (WARN_ON(rc)) - return; + + rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk); + if (rc) { + pr_err("Could not register clock provider for node:%s\n", + clk_name); + goto err_of_clk_add_hw_provider; + } + + return; + +err_of_clk_add_hw_provider: + clk_hw_unregister(hw_clk); +err_clk_hw_register: + kfree(socfpga_clk); } void __init socfpga_a10_gate_init(struct device_node *node) diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 0c18c55edf8c..32ccda960f28 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -126,17 +126,14 @@ void __init socfpga_gate_init(struct device_node *node) struct clk_init_data init; struct clk_ops *ops; int rc; - int err; socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); if (WARN_ON(!socfpga_clk)) return; ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL); - if (WARN_ON(!ops)) { - kfree(socfpga_clk); - return; - } + if (WARN_ON(!ops)) + goto err_kmemdup; rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); if (rc) @@ -182,13 +179,25 @@ void __init socfpga_gate_init(struct device_node *node) hw_clk = &socfpga_clk->hw.hw; - err = clk_hw_register(NULL, hw_clk); - if (err) { - kfree(ops); - kfree(socfpga_clk); - return; + rc = clk_hw_register(NULL, hw_clk); + if (rc) { + pr_err("Could not register clock:%s\n", clk_name); + goto err_clk_hw_register; } - rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); - if (WARN_ON(rc)) - return; + + rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk); + if (rc) { + pr_err("Could not register clock provider for node:%s\n", + clk_name); + goto err_of_clk_add_hw_provider; + } + + return; + +err_of_clk_add_hw_provider: + clk_hw_unregister(hw_clk); +err_clk_hw_register: + kfree(ops); +err_kmemdup: + kfree(socfpga_clk); } diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c index b9cdde4b8441..64cc70b970b7 100644 --- a/drivers/clk/socfpga/clk-periph-a10.c +++ b/drivers/clk/socfpga/clk-periph-a10.c @@ -57,8 +57,8 @@ static const struct clk_ops periclk_ops = { .get_parent = clk_periclk_get_parent, }; -static __init void __socfpga_periph_init(struct device_node *node, - const struct clk_ops *ops) +static void __init __socfpga_periph_init(struct device_node *node, + const struct clk_ops *ops) { u32 reg; struct clk_hw *hw_clk; @@ -106,21 +106,25 @@ static __init void __socfpga_periph_init(struct device_node *node, hw_clk = &periph_clk->hw.hw; - if (clk_hw_register(NULL, hw_clk)) { - kfree(periph_clk); - return; + rc = clk_hw_register(NULL, hw_clk); + if (rc) { + pr_err("Could not register clock:%s\n", clk_name); + goto err_clk_hw_register; } - rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); - if (rc < 0) { + + rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk); + if (rc) { pr_err("Could not register clock provider for node:%s\n", clk_name); - goto err_clk; + goto err_of_clk_add_hw_provider; } return; -err_clk: +err_of_clk_add_hw_provider: clk_hw_unregister(hw_clk); +err_clk_hw_register: + kfree(periph_clk); } void __init socfpga_a10_periph_init(struct device_node *node) diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c index 43707e2d7248..6a4075147b9c 100644 --- a/drivers/clk/socfpga/clk-periph.c +++ b/drivers/clk/socfpga/clk-periph.c @@ -47,8 +47,8 @@ static const struct clk_ops periclk_ops = { .get_parent = clk_periclk_get_parent, }; -static __init void __socfpga_periph_init(struct device_node *node, - const struct clk_ops *ops) +static void __init __socfpga_periph_init(struct device_node *node, + const struct clk_ops *ops) { u32 reg; struct clk_hw *hw_clk; @@ -96,11 +96,25 @@ static __init void __socfpga_periph_init(struct device_node *node, periph_clk->hw.hw.init = &init; hw_clk = &periph_clk->hw.hw; - if (clk_hw_register(NULL, hw_clk)) { - kfree(periph_clk); - return; + rc = clk_hw_register(NULL, hw_clk); + if (rc) { + pr_err("Could not register clock:%s\n", clk_name); + goto err_clk_hw_register; + } + + rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk); + if (rc) { + pr_err("Could not register clock provider for node:%s\n", + clk_name); + goto err_of_clk_add_hw_provider; } - rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); + + return; + +err_of_clk_add_hw_provider: + clk_hw_unregister(hw_clk); +err_clk_hw_register: + kfree(periph_clk); } void __init socfpga_periph_init(struct device_node *node) diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index bee0f7da5b6e..b028f25c658a 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -63,8 +63,8 @@ static const struct clk_ops clk_pll_ops = { .get_parent = clk_pll_get_parent, }; -static struct clk_hw * __init __socfpga_pll_init(struct device_node *node, - const struct clk_ops *ops) +static void __init __socfpga_pll_init(struct device_node *node, + const struct clk_ops *ops) { u32 reg; struct clk_hw *hw_clk; @@ -73,13 +73,14 @@ static struct clk_hw * __init __socfpga_pll_init(struct device_node *node, const char *parent_name[SOCFGPA_MAX_PARENTS]; struct clk_init_data init; struct device_node *clkmgr_np; + int rc; int i = 0; of_property_read_u32(node, "reg", ®); pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); if (WARN_ON(!pll_clk)) - return NULL; + return; clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0); @@ -103,12 +104,25 @@ static struct clk_hw * __init __socfpga_pll_init(struct device_node *node, pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; hw_clk = &pll_clk->hw.hw; - if (clk_hw_register(NULL, hw_clk)) { - kfree(pll_clk); - return NULL; + rc = clk_hw_register(NULL, hw_clk); + if (rc) { + pr_err("Could not register clock:%s\n", clk_name); + goto err_clk_hw_register; } - of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); - return hw_clk; + + rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk); + if (rc) { + pr_err("Could not register clock provider for node:%s\n", + clk_name); + goto err_of_clk_add_hw_provider; + } + + return; + +err_of_clk_add_hw_provider: + clk_hw_unregister(hw_clk); +err_clk_hw_register: + kfree(pll_clk); } void __init socfpga_a10_pll_init(struct device_node *node) diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index 127cc849c5ee..9dcc1b2d2cc0 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -70,8 +70,8 @@ static const struct clk_ops clk_pll_ops = { .get_parent = clk_pll_get_parent, }; -static __init struct clk_hw *__socfpga_pll_init(struct device_node *node, - const struct clk_ops *ops) +static void __init __socfpga_pll_init(struct device_node *node, + const struct clk_ops *ops) { u32 reg; struct clk_hw *hw_clk; @@ -80,13 +80,13 @@ static __init struct clk_hw *__socfpga_pll_init(struct device_node *node, const char *parent_name[SOCFPGA_MAX_PARENTS]; struct clk_init_data init; struct device_node *clkmgr_np; - int err; + int rc; of_property_read_u32(node, "reg", ®); pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); if (WARN_ON(!pll_clk)) - return NULL; + return; clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); clk_mgr_base_addr = of_iomap(clkmgr_np, 0); @@ -108,13 +108,25 @@ static __init struct clk_hw *__socfpga_pll_init(struct device_node *node, hw_clk = &pll_clk->hw.hw; - err = clk_hw_register(NULL, hw_clk); - if (err) { - kfree(pll_clk); - return ERR_PTR(err); + rc = clk_hw_register(NULL, hw_clk); + if (rc) { + pr_err("Could not register clock:%s\n", clk_name); + goto err_clk_hw_register; } - of_clk_add_provider(node, of_clk_src_simple_get, hw_clk); - return hw_clk; + + rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk); + if (rc) { + pr_err("Could not register clock provider for node:%s\n", + clk_name); + goto err_of_clk_add_hw_provider; + } + + return; + +err_of_clk_add_hw_provider: + clk_hw_unregister(hw_clk); +err_clk_hw_register: + kfree(pll_clk); } void __init socfpga_pll_init(struct device_node *node) diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c index ce81e4087a8f..1a3795a61f81 100644 --- a/drivers/clk/sprd/common.c +++ b/drivers/clk/sprd/common.c @@ -44,7 +44,7 @@ int sprd_clk_regmap_init(struct platform_device *pdev, struct device_node *node = dev->of_node, *np; struct regmap *regmap; - if (of_find_property(node, "sprd,syscon", NULL)) { + if (of_property_present(node, "sprd,syscon")) { regmap = syscon_regmap_lookup_by_phandle(node, "sprd,syscon"); if (IS_ERR(regmap)) { pr_err("%s: failed to get syscon regmap\n", __func__); diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 1192eee8abe4..c4a737482fe5 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -1593,15 +1593,13 @@ static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev) return ret; } -static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev) +static void stm32mp1_rcc_clocks_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *child, *np = dev_of_node(dev); for_each_available_child_of_node(np, child) of_clk_del_provider(child); - - return 0; } static struct platform_driver stm32mp13_rcc_clocks_driver = { @@ -1610,7 +1608,7 @@ static struct platform_driver stm32mp13_rcc_clocks_driver = { .of_match_table = stm32mp13_match_data, }, .probe = stm32mp1_rcc_clocks_probe, - .remove = stm32mp1_rcc_clocks_remove, + .remove_new = stm32mp1_rcc_clocks_remove, }; static int __init stm32mp13_clocks_init(void) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index 41433927b55c..58fa5a59e0c7 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -2081,7 +2081,10 @@ struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev) { struct tegra_dfll *td = platform_get_drvdata(pdev); - /* Try to prevent removal while the DFLL is active */ + /* + * Note that exiting early here doesn't prevent unbinding the driver. + * Exiting early here only leaks some resources. + */ if (td->mode != DFLL_DISABLED) { dev_err(&pdev->dev, "must disable DFLL before removing driver\n"); diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 5e339ad0a97c..2a164e565c86 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -612,20 +612,19 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) return 0; } -static int tegra124_dfll_fcpu_remove(struct platform_device *pdev) +static void tegra124_dfll_fcpu_remove(struct platform_device *pdev) { struct tegra_dfll_soc_data *soc; + /* + * Note that exiting early here is dangerous as after this function + * returns *soc is freed. + */ soc = tegra_dfll_unregister(pdev); - if (IS_ERR(soc)) { - dev_err(&pdev->dev, "failed to unregister DFLL: %ld\n", - PTR_ERR(soc)); - return PTR_ERR(soc); - } + if (IS_ERR(soc)) + return; tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq); - - return 0; } static const struct dev_pm_ops tegra124_dfll_pm_ops = { @@ -636,7 +635,7 @@ static const struct dev_pm_ops tegra124_dfll_pm_ops = { static struct platform_driver tegra124_dfll_fcpu_driver = { .probe = tegra124_dfll_fcpu_probe, - .remove = tegra124_dfll_fcpu_remove, + .remove_new = tegra124_dfll_fcpu_remove, .driver = { .name = "tegra124-dfll", .of_match_table = tegra124_dfll_fcpu_of_match, diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 422d78247553..dcacc5064d33 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -21,24 +21,24 @@ #define MISC_CLK_ENB 0x48 #define OSC_CTRL 0x50 -#define OSC_CTRL_OSC_FREQ_MASK (3<<30) -#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) -#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) -#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) -#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) -#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) - -#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) -#define OSC_CTRL_PLL_REF_DIV_1 (0<<28) -#define OSC_CTRL_PLL_REF_DIV_2 (1<<28) -#define OSC_CTRL_PLL_REF_DIV_4 (2<<28) +#define OSC_CTRL_OSC_FREQ_MASK (3u<<30) +#define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30) +#define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30) +#define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30) +#define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30) +#define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK) + +#define OSC_CTRL_PLL_REF_DIV_MASK (3u<<28) +#define OSC_CTRL_PLL_REF_DIV_1 (0u<<28) +#define OSC_CTRL_PLL_REF_DIV_2 (1u<<28) +#define OSC_CTRL_PLL_REF_DIV_4 (2u<<28) #define OSC_FREQ_DET 0x58 -#define OSC_FREQ_DET_TRIG (1<<31) +#define OSC_FREQ_DET_TRIG (1u<<31) #define OSC_FREQ_DET_STATUS 0x5c -#define OSC_FREQ_DET_BUSY (1<<31) -#define OSC_FREQ_DET_CNT_MASK 0xFFFF +#define OSC_FREQ_DET_BUSYu (1<<31) +#define OSC_FREQ_DET_CNT_MASK 0xFFFFu #define TEGRA20_CLK_PERIPH_BANKS 3 diff --git a/drivers/clk/ti/adpll.c b/drivers/clk/ti/adpll.c index f5e7e2049241..6ecbba4342c5 100644 --- a/drivers/clk/ti/adpll.c +++ b/drivers/clk/ti/adpll.c @@ -931,13 +931,11 @@ free: return err; } -static int ti_adpll_remove(struct platform_device *pdev) +static void ti_adpll_remove(struct platform_device *pdev) { struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev); ti_adpll_free_resources(d); - - return 0; } static struct platform_driver ti_adpll_driver = { @@ -946,7 +944,7 @@ static struct platform_driver ti_adpll_driver = { .of_match_table = ti_adpll_match, }, .probe = ti_adpll_probe, - .remove = ti_adpll_remove, + .remove_new = ti_adpll_remove, }; static int __init ti_adpll_init(void) diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index f73f402ff7de..b6fce916967c 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -512,16 +512,16 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) struct clk_hw_omap *hw; struct clk *clk; struct omap_clkctrl_clk *clkctrl_clk = NULL; - const __be32 *addrp; bool legacy_naming; const char *clkctrl_name; u32 addr; int ret; char *c; u16 soc_mask = 0; + struct resource res; - addrp = of_get_address(node, 0, NULL, NULL); - addr = (u32)of_translate_address(node, addrp); + of_address_to_resource(node, 0, &res); + addr = (u32)res.start; #ifdef CONFIG_ARCH_OMAP4 if (of_machine_is_compatible("ti,omap4")) diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 46c66fac48e6..92f4ddc593db 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -91,11 +91,9 @@ static int uniphier_clk_probe(struct platform_device *pdev) hw_data); } -static int uniphier_clk_remove(struct platform_device *pdev) +static void uniphier_clk_remove(struct platform_device *pdev) { of_clk_del_provider(pdev->dev.of_node); - - return 0; } static const struct of_device_id uniphier_clk_match[] = { @@ -220,7 +218,7 @@ static const struct of_device_id uniphier_clk_match[] = { static struct platform_driver uniphier_clk_driver = { .probe = uniphier_clk_probe, - .remove = uniphier_clk_remove, + .remove_new = uniphier_clk_remove, .driver = { .name = "uniphier-clk", .of_match_table = uniphier_clk_match, diff --git a/drivers/clk/visconti/pll.h b/drivers/clk/visconti/pll.h index 16dae35ab370..01d07f1bf01b 100644 --- a/drivers/clk/visconti/pll.h +++ b/drivers/clk/visconti/pll.h @@ -15,7 +15,6 @@ struct visconti_pll_provider { void __iomem *reg_base; - struct regmap *regmap; struct clk_hw_onecell_data clk_data; struct device_node *node; }; diff --git a/drivers/clk/x86/clk-fch.c b/drivers/clk/x86/clk-fch.c index fdc060e75839..aed7d22fae63 100644 --- a/drivers/clk/x86/clk-fch.c +++ b/drivers/clk/x86/clk-fch.c @@ -92,14 +92,14 @@ static int fch_clk_probe(struct platform_device *pdev) return 0; } -static int fch_clk_remove(struct platform_device *pdev) +static void fch_clk_remove(struct platform_device *pdev) { int i, clks; struct pci_dev *rdev; rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); if (!rdev) - return -ENODEV; + return; clks = pci_match_id(fch_pci_ids, rdev) ? CLK_MAX_FIXED : ST_MAX_CLKS; @@ -107,7 +107,6 @@ static int fch_clk_remove(struct platform_device *pdev) clk_hw_unregister(hws[i]); pci_dev_put(rdev); - return 0; } static struct platform_driver fch_clk_driver = { @@ -116,6 +115,6 @@ static struct platform_driver fch_clk_driver = { .suppress_bind_attrs = true, }, .probe = fch_clk_probe, - .remove = fch_clk_remove, + .remove_new = fch_clk_remove, }; builtin_platform_driver(fch_clk_driver); diff --git a/drivers/clk/x86/clk-pmc-atom.c b/drivers/clk/x86/clk-pmc-atom.c index e746e3f8d05a..2974dd0ec6f4 100644 --- a/drivers/clk/x86/clk-pmc-atom.c +++ b/drivers/clk/x86/clk-pmc-atom.c @@ -367,7 +367,7 @@ err_unreg_clk_plt: return err; } -static int plt_clk_remove(struct platform_device *pdev) +static void plt_clk_remove(struct platform_device *pdev) { struct clk_plt_data *data; @@ -377,7 +377,6 @@ static int plt_clk_remove(struct platform_device *pdev) clkdev_drop(data->mclk_lookup); plt_clk_unregister_loop(data, PMC_CLK_NUM); plt_clk_unregister_parents(data); - return 0; } static struct platform_driver plt_clk_driver = { @@ -385,6 +384,6 @@ static struct platform_driver plt_clk_driver = { .name = "clk-pmc-atom", }, .probe = plt_clk_probe, - .remove = plt_clk_remove, + .remove_new = plt_clk_remove, }; builtin_platform_driver(plt_clk_driver); diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c index b7591ae019e7..e83f104fad02 100644 --- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c +++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c @@ -773,7 +773,7 @@ err_disable_clk: return ret; } -static int clk_wzrd_remove(struct platform_device *pdev) +static void clk_wzrd_remove(struct platform_device *pdev) { int i; struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev); @@ -791,8 +791,6 @@ static int clk_wzrd_remove(struct platform_device *pdev) } clk_disable_unprepare(clk_wzrd->axi_clk); - - return 0; } static const struct of_device_id clk_wzrd_ids[] = { @@ -810,7 +808,7 @@ static struct platform_driver clk_wzrd_driver = { .pm = &clk_wzrd_dev_pm_ops, }, .probe = clk_wzrd_probe, - .remove = clk_wzrd_remove, + .remove_new = clk_wzrd_remove, }; module_platform_driver(clk_wzrd_driver); diff --git a/drivers/clk/xilinx/xlnx_vcu.c b/drivers/clk/xilinx/xlnx_vcu.c index d66b1315114e..0786f15ebbe8 100644 --- a/drivers/clk/xilinx/xlnx_vcu.c +++ b/drivers/clk/xilinx/xlnx_vcu.c @@ -702,13 +702,11 @@ error_clk_provider: * Return: Returns 0 on success * Negative error code otherwise */ -static int xvcu_remove(struct platform_device *pdev) +static void xvcu_remove(struct platform_device *pdev) { struct xvcu_device *xvcu; xvcu = platform_get_drvdata(pdev); - if (!xvcu) - return -ENODEV; xvcu_unregister_clock_provider(xvcu); @@ -716,8 +714,6 @@ static int xvcu_remove(struct platform_device *pdev) regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); clk_disable_unprepare(xvcu->aclk); - - return 0; } static const struct of_device_id xvcu_of_id_table[] = { @@ -733,7 +729,7 @@ static struct platform_driver xvcu_driver = { .of_match_table = xvcu_of_id_table, }, .probe = xvcu_probe, - .remove = xvcu_remove, + .remove_new = xvcu_remove, }; module_platform_driver(xvcu_driver); |