diff options
Diffstat (limited to 'drivers/clk')
31 files changed, 3395 insertions, 1226 deletions
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 96c6b6bc8f0e..da44f8dc1d29 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -1424,7 +1424,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) base = of_iomap(np, 0); if (!base) { - pr_err("%s: unable to map resource", np->name); + pr_err("%s: unable to map resource\n", np->name); return; } diff --git a/drivers/clk/clk-stm32h7.c b/drivers/clk/clk-stm32h7.c index 61c3e40507d3..db2b162c0d4c 100644 --- a/drivers/clk/clk-stm32h7.c +++ b/drivers/clk/clk-stm32h7.c @@ -1,20 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) Gabriel Fernandez 2017 - * Author: Gabriel Fernandez <gabriel.fernandez@st.com> - * - * License terms: GPL V2.0. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. + * Copyright (C) STMicroelectronics 2017 + * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. */ #include <linux/clk.h> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 647d056df88c..3526bc068f30 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -62,6 +62,7 @@ struct clk_core { bool orphan; unsigned int enable_count; unsigned int prepare_count; + unsigned int protect_count; unsigned long min_rate; unsigned long max_rate; unsigned long accuracy; @@ -86,6 +87,7 @@ struct clk { const char *con_id; unsigned long min_rate; unsigned long max_rate; + unsigned int exclusive_count; struct hlist_node clks_node; }; @@ -170,6 +172,11 @@ static void clk_enable_unlock(unsigned long flags) spin_unlock_irqrestore(&enable_lock, flags); } +static bool clk_core_rate_is_protected(struct clk_core *core) +{ + return core->protect_count; +} + static bool clk_core_is_prepared(struct clk_core *core) { bool ret = false; @@ -381,6 +388,11 @@ bool clk_hw_is_prepared(const struct clk_hw *hw) return clk_core_is_prepared(hw->core); } +bool clk_hw_rate_is_protected(const struct clk_hw *hw) +{ + return clk_core_rate_is_protected(hw->core); +} + bool clk_hw_is_enabled(const struct clk_hw *hw) { return clk_core_is_enabled(hw->core); @@ -519,6 +531,139 @@ EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest); /*** clk api ***/ +static void clk_core_rate_unprotect(struct clk_core *core) +{ + lockdep_assert_held(&prepare_lock); + + if (!core) + return; + + if (WARN_ON(core->protect_count == 0)) + return; + + if (--core->protect_count > 0) + return; + + clk_core_rate_unprotect(core->parent); +} + +static int clk_core_rate_nuke_protect(struct clk_core *core) +{ + int ret; + + lockdep_assert_held(&prepare_lock); + + if (!core) + return -EINVAL; + + if (core->protect_count == 0) + return 0; + + ret = core->protect_count; + core->protect_count = 1; + clk_core_rate_unprotect(core); + + return ret; +} + +/** + * clk_rate_exclusive_put - release exclusivity over clock rate control + * @clk: the clk over which the exclusivity is released + * + * clk_rate_exclusive_put() completes a critical section during which a clock + * consumer cannot tolerate any other consumer making any operation on the + * clock which could result in a rate change or rate glitch. Exclusive clocks + * cannot have their rate changed, either directly or indirectly due to changes + * further up the parent chain of clocks. As a result, clocks up parent chain + * also get under exclusive control of the calling consumer. + * + * If exlusivity is claimed more than once on clock, even by the same consumer, + * the rate effectively gets locked as exclusivity can't be preempted. + * + * Calls to clk_rate_exclusive_put() must be balanced with calls to + * clk_rate_exclusive_get(). Calls to this function may sleep, and do not return + * error status. + */ +void clk_rate_exclusive_put(struct clk *clk) +{ + if (!clk) + return; + + clk_prepare_lock(); + + /* + * if there is something wrong with this consumer protect count, stop + * here before messing with the provider + */ + if (WARN_ON(clk->exclusive_count <= 0)) + goto out; + + clk_core_rate_unprotect(clk->core); + clk->exclusive_count--; +out: + clk_prepare_unlock(); +} +EXPORT_SYMBOL_GPL(clk_rate_exclusive_put); + +static void clk_core_rate_protect(struct clk_core *core) +{ + lockdep_assert_held(&prepare_lock); + + if (!core) + return; + + if (core->protect_count == 0) + clk_core_rate_protect(core->parent); + + core->protect_count++; +} + +static void clk_core_rate_restore_protect(struct clk_core *core, int count) +{ + lockdep_assert_held(&prepare_lock); + + if (!core) + return; + + if (count == 0) + return; + + clk_core_rate_protect(core); + core->protect_count = count; +} + +/** + * clk_rate_exclusive_get - get exclusivity over the clk rate control + * @clk: the clk over which the exclusity of rate control is requested + * + * clk_rate_exlusive_get() begins a critical section during which a clock + * consumer cannot tolerate any other consumer making any operation on the + * clock which could result in a rate change or rate glitch. Exclusive clocks + * cannot have their rate changed, either directly or indirectly due to changes + * further up the parent chain of clocks. As a result, clocks up parent chain + * also get under exclusive control of the calling consumer. + * + * If exlusivity is claimed more than once on clock, even by the same consumer, + * the rate effectively gets locked as exclusivity can't be preempted. + * + * Calls to clk_rate_exclusive_get() should be balanced with calls to + * clk_rate_exclusive_put(). Calls to this function may sleep. + * Returns 0 on success, -EERROR otherwise + */ +int clk_rate_exclusive_get(struct clk *clk) +{ + if (!clk) + return 0; + + clk_prepare_lock(); + clk_core_rate_protect(clk->core); + clk->exclusive_count++; + clk_prepare_unlock(); + + return 0; +} +EXPORT_SYMBOL_GPL(clk_rate_exclusive_get); + static void clk_core_unprepare(struct clk_core *core) { lockdep_assert_held(&prepare_lock); @@ -905,10 +1050,9 @@ static int clk_disable_unused(void) } late_initcall_sync(clk_disable_unused); -static int clk_core_round_rate_nolock(struct clk_core *core, - struct clk_rate_request *req) +static int clk_core_determine_round_nolock(struct clk_core *core, + struct clk_rate_request *req) { - struct clk_core *parent; long rate; lockdep_assert_held(&prepare_lock); @@ -916,16 +1060,15 @@ static int clk_core_round_rate_nolock(struct clk_core *core, if (!core) return 0; - parent = core->parent; - if (parent) { - req->best_parent_hw = parent->hw; - req->best_parent_rate = parent->rate; - } else { - req->best_parent_hw = NULL; - req->best_parent_rate = 0; - } - - if (core->ops->determine_rate) { + /* + * At this point, core protection will be disabled if + * - if the provider is not protected at all + * - if the calling consumer is the only one which has exclusivity + * over the provider + */ + if (clk_core_rate_is_protected(core)) { + req->rate = core->rate; + } else if (core->ops->determine_rate) { return core->ops->determine_rate(core->hw, req); } else if (core->ops->round_rate) { rate = core->ops->round_rate(core->hw, req->rate, @@ -934,15 +1077,58 @@ static int clk_core_round_rate_nolock(struct clk_core *core, return rate; req->rate = rate; - } else if (core->flags & CLK_SET_RATE_PARENT) { - return clk_core_round_rate_nolock(parent, req); } else { - req->rate = core->rate; + return -EINVAL; } return 0; } +static void clk_core_init_rate_req(struct clk_core * const core, + struct clk_rate_request *req) +{ + struct clk_core *parent; + + if (WARN_ON(!core || !req)) + return; + + parent = core->parent; + if (parent) { + req->best_parent_hw = parent->hw; + req->best_parent_rate = parent->rate; + } else { + req->best_parent_hw = NULL; + req->best_parent_rate = 0; + } +} + +static bool clk_core_can_round(struct clk_core * const core) +{ + if (core->ops->determine_rate || core->ops->round_rate) + return true; + + return false; +} + +static int clk_core_round_rate_nolock(struct clk_core *core, + struct clk_rate_request *req) +{ + lockdep_assert_held(&prepare_lock); + + if (!core) + return 0; + + clk_core_init_rate_req(core, req); + + if (clk_core_can_round(core)) + return clk_core_determine_round_nolock(core, req); + else if (core->flags & CLK_SET_RATE_PARENT) + return clk_core_round_rate_nolock(core->parent, req); + + req->rate = core->rate; + return 0; +} + /** * __clk_determine_rate - get the closest rate actually supported by a clock * @hw: determine the rate of this clock @@ -996,10 +1182,17 @@ long clk_round_rate(struct clk *clk, unsigned long rate) clk_prepare_lock(); + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); + clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate); req.rate = rate; ret = clk_core_round_rate_nolock(clk->core, &req); + + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); + clk_prepare_unlock(); if (ret) @@ -1432,34 +1625,23 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core, clk_core_get_boundaries(core, &min_rate, &max_rate); /* find the closest rate and parent clk/rate */ - if (core->ops->determine_rate) { + if (clk_core_can_round(core)) { struct clk_rate_request req; req.rate = rate; req.min_rate = min_rate; req.max_rate = max_rate; - if (parent) { - req.best_parent_hw = parent->hw; - req.best_parent_rate = parent->rate; - } else { - req.best_parent_hw = NULL; - req.best_parent_rate = 0; - } - ret = core->ops->determine_rate(core->hw, &req); + clk_core_init_rate_req(core, &req); + + ret = clk_core_determine_round_nolock(core, &req); if (ret < 0) return NULL; best_parent_rate = req.best_parent_rate; new_rate = req.rate; parent = req.best_parent_hw ? req.best_parent_hw->core : NULL; - } else if (core->ops->round_rate) { - ret = core->ops->round_rate(core->hw, rate, - &best_parent_rate); - if (ret < 0) - return NULL; - new_rate = ret; if (new_rate < min_rate || new_rate > max_rate) return NULL; } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) { @@ -1564,6 +1746,9 @@ static void clk_change_rate(struct clk_core *core) best_parent_rate = core->parent->rate; } + if (clk_pm_runtime_get(core)) + return; + if (core->flags & CLK_SET_RATE_UNGATE) { unsigned long flags; @@ -1634,27 +1819,62 @@ static void clk_change_rate(struct clk_core *core) /* handle the new child who might not be in core->children yet */ if (core->new_child) clk_change_rate(core->new_child); + + clk_pm_runtime_put(core); +} + +static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core, + unsigned long req_rate) +{ + int ret, cnt; + struct clk_rate_request req; + + lockdep_assert_held(&prepare_lock); + + if (!core) + return 0; + + /* simulate what the rate would be if it could be freely set */ + cnt = clk_core_rate_nuke_protect(core); + if (cnt < 0) + return cnt; + + clk_core_get_boundaries(core, &req.min_rate, &req.max_rate); + req.rate = req_rate; + + ret = clk_core_round_rate_nolock(core, &req); + + /* restore the protection */ + clk_core_rate_restore_protect(core, cnt); + + return ret ? 0 : req.rate; } static int clk_core_set_rate_nolock(struct clk_core *core, unsigned long req_rate) { struct clk_core *top, *fail_clk; - unsigned long rate = req_rate; + unsigned long rate; int ret = 0; if (!core) return 0; + rate = clk_core_req_round_rate_nolock(core, req_rate); + /* bail early if nothing to do */ if (rate == clk_core_get_rate_nolock(core)) return 0; + /* fail on a direct rate set of a protected provider */ + if (clk_core_rate_is_protected(core)) + return -EBUSY; + if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count) return -EBUSY; /* calculate new rates and get the topmost changed clock */ - top = clk_calc_new_rates(core, rate); + top = clk_calc_new_rates(core, req_rate); if (!top) return -EINVAL; @@ -1713,8 +1933,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate) /* prevent racing with updates to the clock topology */ clk_prepare_lock(); + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); + ret = clk_core_set_rate_nolock(clk->core, rate); + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); + clk_prepare_unlock(); return ret; @@ -1722,6 +1948,53 @@ int clk_set_rate(struct clk *clk, unsigned long rate) EXPORT_SYMBOL_GPL(clk_set_rate); /** + * clk_set_rate_exclusive - specify a new rate get exclusive control + * @clk: the clk whose rate is being changed + * @rate: the new rate for clk + * + * This is a combination of clk_set_rate() and clk_rate_exclusive_get() + * within a critical section + * + * This can be used initially to ensure that at least 1 consumer is + * statisfied when several consumers are competing for exclusivity over the + * same clock provider. + * + * The exclusivity is not applied if setting the rate failed. + * + * Calls to clk_rate_exclusive_get() should be balanced with calls to + * clk_rate_exclusive_put(). + * + * Returns 0 on success, -EERROR otherwise. + */ +int clk_set_rate_exclusive(struct clk *clk, unsigned long rate) +{ + int ret; + + if (!clk) + return 0; + + /* prevent racing with updates to the clock topology */ + clk_prepare_lock(); + + /* + * The temporary protection removal is not here, on purpose + * This function is meant to be used instead of clk_rate_protect, + * so before the consumer code path protect the clock provider + */ + + ret = clk_core_set_rate_nolock(clk->core, rate); + if (!ret) { + clk_core_rate_protect(clk->core); + clk->exclusive_count++; + } + + clk_prepare_unlock(); + + return ret; +} +EXPORT_SYMBOL_GPL(clk_set_rate_exclusive); + +/** * clk_set_rate_range - set a rate range for a clock source * @clk: clock source * @min: desired minimum clock rate in Hz, inclusive @@ -1732,6 +2005,7 @@ EXPORT_SYMBOL_GPL(clk_set_rate); int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) { int ret = 0; + unsigned long old_min, old_max, rate; if (!clk) return 0; @@ -1745,12 +2019,46 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) clk_prepare_lock(); - if (min != clk->min_rate || max != clk->max_rate) { - clk->min_rate = min; - clk->max_rate = max; - ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate); + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); + + /* Save the current values in case we need to rollback the change */ + old_min = clk->min_rate; + old_max = clk->max_rate; + clk->min_rate = min; + clk->max_rate = max; + + rate = clk_core_get_rate_nolock(clk->core); + if (rate < min || rate > max) { + /* + * FIXME: + * We are in bit of trouble here, current rate is outside the + * the requested range. We are going try to request appropriate + * range boundary but there is a catch. It may fail for the + * usual reason (clock broken, clock protected, etc) but also + * because: + * - round_rate() was not favorable and fell on the wrong + * side of the boundary + * - the determine_rate() callback does not really check for + * this corner case when determining the rate + */ + + if (rate < min) + rate = min; + else + rate = max; + + ret = clk_core_set_rate_nolock(clk->core, rate); + if (ret) { + /* rollback the changes */ + clk->min_rate = old_min; + clk->max_rate = old_max; + } } + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); + clk_prepare_unlock(); return ret; @@ -1871,32 +2179,31 @@ bool clk_has_parent(struct clk *clk, struct clk *parent) } EXPORT_SYMBOL_GPL(clk_has_parent); -static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent) +static int clk_core_set_parent_nolock(struct clk_core *core, + struct clk_core *parent) { int ret = 0; int p_index = 0; unsigned long p_rate = 0; + lockdep_assert_held(&prepare_lock); + if (!core) return 0; - /* prevent racing with updates to the clock topology */ - clk_prepare_lock(); - if (core->parent == parent) - goto out; + return 0; /* verify ops for for multi-parent clks */ - if ((core->num_parents > 1) && (!core->ops->set_parent)) { - ret = -ENOSYS; - goto out; - } + if (core->num_parents > 1 && !core->ops->set_parent) + return -EPERM; /* check that we are allowed to re-parent if the clock is in use */ - if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) { - ret = -EBUSY; - goto out; - } + if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) + return -EBUSY; + + if (clk_core_rate_is_protected(core)) + return -EBUSY; /* try finding the new parent index */ if (parent) { @@ -1904,15 +2211,14 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent) if (p_index < 0) { pr_debug("%s: clk %s can not be parent of clk %s\n", __func__, parent->name, core->name); - ret = p_index; - goto out; + return p_index; } p_rate = parent->rate; } ret = clk_pm_runtime_get(core); if (ret) - goto out; + return ret; /* propagate PRE_RATE_CHANGE notifications */ ret = __clk_speculate_rates(core, p_rate); @@ -1934,8 +2240,6 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent) runtime_put: clk_pm_runtime_put(core); -out: - clk_prepare_unlock(); return ret; } @@ -1959,13 +2263,50 @@ out: */ int clk_set_parent(struct clk *clk, struct clk *parent) { + int ret; + if (!clk) return 0; - return clk_core_set_parent(clk->core, parent ? parent->core : NULL); + clk_prepare_lock(); + + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); + + ret = clk_core_set_parent_nolock(clk->core, + parent ? parent->core : NULL); + + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); + + clk_prepare_unlock(); + + return ret; } EXPORT_SYMBOL_GPL(clk_set_parent); +static int clk_core_set_phase_nolock(struct clk_core *core, int degrees) +{ + int ret = -EINVAL; + + lockdep_assert_held(&prepare_lock); + + if (!core) + return 0; + + if (clk_core_rate_is_protected(core)) + return -EBUSY; + + trace_clk_set_phase(core, degrees); + + if (core->ops->set_phase) + ret = core->ops->set_phase(core->hw, degrees); + + trace_clk_set_phase_complete(core, degrees); + + return ret; +} + /** * clk_set_phase - adjust the phase shift of a clock signal * @clk: clock signal source @@ -1988,7 +2329,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent); */ int clk_set_phase(struct clk *clk, int degrees) { - int ret = -EINVAL; + int ret; if (!clk) return 0; @@ -2000,15 +2341,13 @@ int clk_set_phase(struct clk *clk, int degrees) clk_prepare_lock(); - trace_clk_set_phase(clk->core, degrees); - - if (clk->core->ops->set_phase) - ret = clk->core->ops->set_phase(clk->core->hw, degrees); + if (clk->exclusive_count) + clk_core_rate_unprotect(clk->core); - trace_clk_set_phase_complete(clk->core, degrees); + ret = clk_core_set_phase_nolock(clk->core, degrees); - if (!ret) - clk->core->phase = degrees; + if (clk->exclusive_count) + clk_core_rate_protect(clk->core); clk_prepare_unlock(); @@ -2096,11 +2435,12 @@ static void clk_summary_show_one(struct seq_file *s, struct clk_core *c, if (!c) return; - seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n", + seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %-3d\n", level * 3 + 1, "", 30 - level * 3, c->name, - c->enable_count, c->prepare_count, clk_core_get_rate(c), - clk_core_get_accuracy(c), clk_core_get_phase(c)); + c->enable_count, c->prepare_count, c->protect_count, + clk_core_get_rate(c), clk_core_get_accuracy(c), + clk_core_get_phase(c)); } static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c, @@ -2122,7 +2462,8 @@ static int clk_summary_show(struct seq_file *s, void *data) struct clk_core *c; struct hlist_head **lists = (struct hlist_head **)s->private; - seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n"); + seq_puts(s, " enable prepare protect \n"); + seq_puts(s, " clock count count count rate accuracy phase\n"); seq_puts(s, "----------------------------------------------------------------------------------------\n"); clk_prepare_lock(); @@ -2158,6 +2499,7 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level) seq_printf(s, "\"%s\": { ", c->name); seq_printf(s, "\"enable_count\": %d,", c->enable_count); seq_printf(s, "\"prepare_count\": %d,", c->prepare_count); + seq_printf(s, "\"protect_count\": %d,", c->protect_count); seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c)); seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c)); seq_printf(s, "\"phase\": %d", clk_core_get_phase(c)); @@ -2288,6 +2630,11 @@ static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) if (!d) goto err_out; + d = debugfs_create_u32("clk_protect_count", S_IRUGO, core->dentry, + (u32 *)&core->protect_count); + if (!d) + goto err_out; + d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry, (u32 *)&core->notifier_count); if (!d) @@ -2678,7 +3025,13 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw) ret = -ENOMEM; goto fail_name; } + + if (WARN_ON(!hw->init->ops)) { + ret = -EINVAL; + goto fail_ops; + } core->ops = hw->init->ops; + if (dev && pm_runtime_enabled(dev)) core->dev = dev; if (dev && dev->driver) @@ -2740,6 +3093,7 @@ fail_parent_names_copy: kfree_const(core->parent_names[i]); kfree(core->parent_names); fail_parent_names: +fail_ops: kfree_const(core->name); fail_name: kfree(core); @@ -2851,7 +3205,7 @@ void clk_unregister(struct clk *clk) /* Reparent all children to the orphan list. */ hlist_for_each_entry_safe(child, t, &clk->core->children, child_node) - clk_core_set_parent(child, NULL); + clk_core_set_parent_nolock(child, NULL); } hlist_del_init(&clk->core->child_node); @@ -2859,6 +3213,11 @@ void clk_unregister(struct clk *clk) if (clk->core->prepare_count) pr_warn("%s: unregistering prepared clock: %s\n", __func__, clk->core->name); + + if (clk->core->protect_count) + pr_warn("%s: unregistering protected clock: %s\n", + __func__, clk->core->name); + kref_put(&clk->core->ref, __clk_release); unlock: clk_prepare_unlock(); @@ -3017,6 +3376,18 @@ void __clk_put(struct clk *clk) clk_prepare_lock(); + /* + * Before calling clk_put, all calls to clk_rate_exclusive_get() from a + * given user should be balanced with calls to clk_rate_exclusive_put() + * and by that same consumer + */ + if (WARN_ON(clk->exclusive_count)) { + /* We voiced our concern, let's sanitize the situation */ + clk->core->protect_count -= (clk->exclusive_count - 1); + clk_core_rate_unprotect(clk->core); + clk->exclusive_count = 0; + } + hlist_del(&clk->clks_node); if (clk->min_rate > clk->core->req_rate || clk->max_rate < clk->core->req_rate) diff --git a/drivers/clk/h8300/clk-div.c b/drivers/clk/h8300/clk-div.c index 4ae624425e9d..d413ade95c99 100644 --- a/drivers/clk/h8300/clk-div.c +++ b/drivers/clk/h8300/clk-div.c @@ -24,13 +24,13 @@ static void __init h8300_div_clk_setup(struct device_node *node) num_parents = of_clk_get_parent_count(node); if (!num_parents) { - pr_err("%s: no parent found", clk_name); + pr_err("%s: no parent found\n", clk_name); return; } divcr = of_iomap(node, 0); if (divcr == NULL) { - pr_err("%s: failed to map divide register", clk_name); + pr_err("%s: failed to map divide register\n", clk_name); goto error; } offset = (unsigned long)divcr & 3; diff --git a/drivers/clk/h8300/clk-h8s2678.c b/drivers/clk/h8300/clk-h8s2678.c index fc24b0b55a3d..b68045d8b921 100644 --- a/drivers/clk/h8300/clk-h8s2678.c +++ b/drivers/clk/h8300/clk-h8s2678.c @@ -93,7 +93,7 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node) num_parents = of_clk_get_parent_count(node); if (!num_parents) { - pr_err("%s: no parent found", clk_name); + pr_err("%s: no parent found\n", clk_name); return; } @@ -104,13 +104,13 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node) pll_clock->sckcr = of_iomap(node, 0); if (pll_clock->sckcr == NULL) { - pr_err("%s: failed to map divide register", clk_name); + pr_err("%s: failed to map divide register\n", clk_name); goto free_clock; } pll_clock->pllcr = of_iomap(node, 1); if (pll_clock->pllcr == NULL) { - pr_err("%s: failed to map multiply register", clk_name); + pr_err("%s: failed to map multiply register\n", clk_name); goto unmap_sckcr; } diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index 7098bfd32b1b..1bd43550e4c8 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -49,3 +49,9 @@ config STUB_CLK_HI6220 default ARCH_HISI help Build the Hisilicon Hi6220 stub clock driver. + +config STUB_CLK_HI3660 + bool "Hi3660 Stub Clock Driver" + depends on COMMON_CLK_HI3660 && MAILBOX + help + Build the Hisilicon Hi3660 stub clock driver. diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index 0e55612112af..4806fc2cb4ac 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o +obj-$(CONFIG_STUB_CLK_HI3660) += clk-hi3660-stub.o diff --git a/drivers/clk/hisilicon/clk-hi3660-stub.c b/drivers/clk/hisilicon/clk-hi3660-stub.c new file mode 100644 index 000000000000..9b6c72bbddf9 --- /dev/null +++ b/drivers/clk/hisilicon/clk-hi3660-stub.c @@ -0,0 +1,185 @@ +/* + * Hisilicon clock driver + * + * Copyright (c) 2013-2017 Hisilicon Limited. + * Copyright (c) 2017 Linaro Limited. + * + * Author: Kai Zhao <zhaokai1@hisilicon.com> + * Tao Wang <kevin.wangtao@hisilicon.com> + * Leo Yan <leo.yan@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/mailbox_client.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <dt-bindings/clock/hi3660-clock.h> + +#define HI3660_STUB_CLOCK_DATA (0x70) +#define MHZ (1000 * 1000) + +#define DEFINE_CLK_STUB(_id, _cmd, _name) \ + { \ + .id = (_id), \ + .cmd = (_cmd), \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &hi3660_stub_clk_ops, \ + .num_parents = 0, \ + .flags = CLK_GET_RATE_NOCACHE, \ + }, \ + }, + +#define to_stub_clk(_hw) container_of(_hw, struct hi3660_stub_clk, hw) + +struct hi3660_stub_clk_chan { + struct mbox_client cl; + struct mbox_chan *mbox; +}; + +struct hi3660_stub_clk { + unsigned int id; + struct clk_hw hw; + unsigned int cmd; + unsigned int msg[8]; + unsigned int rate; +}; + +static void __iomem *freq_reg; +static struct hi3660_stub_clk_chan stub_clk_chan; + +static unsigned long hi3660_stub_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct hi3660_stub_clk *stub_clk = to_stub_clk(hw); + + /* + * LPM3 writes back the CPU frequency in shared SRAM so read + * back the frequency. + */ + stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; + return stub_clk->rate; +} + +static long hi3660_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + /* + * LPM3 handles rate rounding so just return whatever + * rate is requested. + */ + return rate; +} + +static int hi3660_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct hi3660_stub_clk *stub_clk = to_stub_clk(hw); + + stub_clk->msg[0] = stub_clk->cmd; + stub_clk->msg[1] = rate / MHZ; + + dev_dbg(stub_clk_chan.cl.dev, "set rate msg[0]=0x%x msg[1]=0x%x\n", + stub_clk->msg[0], stub_clk->msg[1]); + + mbox_send_message(stub_clk_chan.mbox, stub_clk->msg); + mbox_client_txdone(stub_clk_chan.mbox, 0); + + stub_clk->rate = rate; + return 0; +} + +static const struct clk_ops hi3660_stub_clk_ops = { + .recalc_rate = hi3660_stub_clk_recalc_rate, + .round_rate = hi3660_stub_clk_round_rate, + .set_rate = hi3660_stub_clk_set_rate, +}; + +static struct hi3660_stub_clk hi3660_stub_clks[HI3660_CLK_STUB_NUM] = { + DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER0, 0x0001030A, "cpu-cluster.0") + DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER1, 0x0002030A, "cpu-cluster.1") + DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d") + DEFINE_CLK_STUB(HI3660_CLK_STUB_DDR, 0x00040309, "clk-ddrc") +}; + +static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec, + void *data) +{ + unsigned int idx = clkspec->args[0]; + + if (idx >= HI3660_CLK_STUB_NUM) { + pr_err("%s: invalid index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + return &hi3660_stub_clks[idx].hw; +} + +static int hi3660_stub_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + unsigned int i; + int ret; + + /* Use mailbox client without blocking */ + stub_clk_chan.cl.dev = dev; + stub_clk_chan.cl.tx_done = NULL; + stub_clk_chan.cl.tx_block = false; + stub_clk_chan.cl.knows_txdone = false; + + /* Allocate mailbox channel */ + stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0); + if (IS_ERR(stub_clk_chan.mbox)) + return PTR_ERR(stub_clk_chan.mbox); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + freq_reg = devm_ioremap(dev, res->start, resource_size(res)); + if (!freq_reg) + return -ENOMEM; + + freq_reg += HI3660_STUB_CLOCK_DATA; + + for (i = 0; i < HI3660_CLK_STUB_NUM; i++) { + ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(&pdev->dev, hi3660_stub_clk_hw_get, + hi3660_stub_clks); +} + +static const struct of_device_id hi3660_stub_clk_of_match[] = { + { .compatible = "hisilicon,hi3660-stub-clk", }, + {} +}; + +static struct platform_driver hi3660_stub_clk_driver = { + .probe = hi3660_stub_clk_probe, + .driver = { + .name = "hi3660-stub-clk", + .of_match_table = hi3660_stub_clk_of_match, + }, +}; + +static int __init hi3660_stub_clk_init(void) +{ + return platform_driver_register(&hi3660_stub_clk_driver); +} +subsys_initcall(hi3660_stub_clk_init); diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c index 7b359afd620e..b669a5c10fee 100644 --- a/drivers/clk/nxp/clk-lpc32xx.c +++ b/drivers/clk/nxp/clk-lpc32xx.c @@ -526,7 +526,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, !(pll_is_valid(parent_rate, 1, 1000000, 20000000) && pll_is_valid(cco_rate, 1, 156000000, 320000000) && pll_is_valid(ref_rate, 1, 1000000, 27000000))) - pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu", + pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu\n", clk_hw_get_name(hw), parent_rate, cco_rate, ref_rate); @@ -1505,7 +1505,7 @@ static void __init lpc32xx_clk_init(struct device_node *np) return; } if (clk_get_rate(clk_32k) != 32768) { - pr_err("invalid clock rate of external 32KHz oscillator"); + pr_err("invalid clock rate of external 32KHz oscillator\n"); return; } diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9f6c278deead..20b5d6fd501d 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -196,3 +196,12 @@ config MSM_MMCC_8996 Support for the multimedia clock controller on msm8996 devices. Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. + +config SPMI_PMIC_CLKDIV + tristate "SPMI PMIC clkdiv Support" + depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST + help + This driver supports the clkdiv functionality on the Qualcomm + Technologies, Inc. SPMI PMIC. It configures the frequency of + clkdiv outputs of the PMIC. These clocks are typically wired + through alternate functions on GPIO pins. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 26410d31446b..602af3841522 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -34,3 +34,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o +obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 47a1da3739ce..6d04cd96482a 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -20,7 +20,7 @@ #include "clk-alpha-pll.h" #include "common.h" -#define PLL_MODE 0x00 +#define PLL_MODE(p) ((p)->offset + 0x0) # define PLL_OUTCTRL BIT(0) # define PLL_BYPASSNL BIT(1) # define PLL_RESET_N BIT(2) @@ -32,35 +32,87 @@ # define PLL_VOTE_FSM_ENA BIT(20) # define PLL_FSM_ENA BIT(20) # define PLL_VOTE_FSM_RESET BIT(21) +# define PLL_UPDATE BIT(22) +# define PLL_UPDATE_BYPASS BIT(23) # define PLL_OFFLINE_ACK BIT(28) +# define ALPHA_PLL_ACK_LATCH BIT(29) # define PLL_ACTIVE_FLAG BIT(30) # define PLL_LOCK_DET BIT(31) -#define PLL_L_VAL 0x04 -#define PLL_ALPHA_VAL 0x08 -#define PLL_ALPHA_VAL_U 0x0c +#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) +#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) +#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) -#define PLL_USER_CTL 0x10 +#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) # define PLL_POST_DIV_SHIFT 8 -# define PLL_POST_DIV_MASK 0xf +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) # define PLL_ALPHA_EN BIT(24) +# define PLL_ALPHA_MODE BIT(25) # define PLL_VCO_SHIFT 20 # define PLL_VCO_MASK 0x3 -#define PLL_USER_CTL_U 0x14 - -#define PLL_CONFIG_CTL 0x18 -#define PLL_CONFIG_CTL_U 0x20 -#define PLL_TEST_CTL 0x1c -#define PLL_TEST_CTL_U 0x20 -#define PLL_STATUS 0x24 +#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) + +#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) +#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) +#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) +#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) +#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) + +const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { + [CLK_ALPHA_PLL_TYPE_DEFAULT] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL_U] = 0x0c, + [PLL_OFF_USER_CTL] = 0x10, + [PLL_OFF_USER_CTL_U] = 0x14, + [PLL_OFF_CONFIG_CTL] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_TEST_CTL_U] = 0x20, + [PLL_OFF_STATUS] = 0x24, + }, + [CLK_ALPHA_PLL_TYPE_HUAYRA] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL] = 0x14, + [PLL_OFF_CONFIG_CTL_U] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_TEST_CTL_U] = 0x20, + [PLL_OFF_STATUS] = 0x24, + }, + [CLK_ALPHA_PLL_TYPE_BRAMMO] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL_U] = 0x0c, + [PLL_OFF_USER_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL] = 0x18, + [PLL_OFF_TEST_CTL] = 0x1c, + [PLL_OFF_STATUS] = 0x24, + }, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); /* * Even though 40 bits are present, use only 32 for ease of calculation. */ #define ALPHA_REG_BITWIDTH 40 -#define ALPHA_BITWIDTH 32 -#define ALPHA_16BIT_MASK 0xffff +#define ALPHA_REG_16BIT_WIDTH 16 +#define ALPHA_BITWIDTH 32U +#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) + +#define PLL_HUAYRA_M_WIDTH 8 +#define PLL_HUAYRA_M_SHIFT 8 +#define PLL_HUAYRA_M_MASK 0xff +#define PLL_HUAYRA_N_SHIFT 0 +#define PLL_HUAYRA_N_MASK 0xff +#define PLL_HUAYRA_ALPHA_WIDTH 16 + +#define pll_alpha_width(p) \ + ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ + ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) + +#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ struct clk_alpha_pll, clkr) @@ -71,18 +123,17 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, const char *action) { - u32 val, off; + u32 val; int count; int ret; const char *name = clk_hw_get_name(&pll->clkr.hw); - off = pll->offset; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; for (count = 100; count > 0; count--) { - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; if (inverse && !(val & mask)) @@ -109,16 +160,30 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, #define wait_for_pll_offline(pll) \ wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") +#define wait_for_pll_update(pll) \ + wait_for_pll(pll, PLL_UPDATE, 1, "update") + +#define wait_for_pll_update_ack_set(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") + +#define wait_for_pll_update_ack_clear(pll) \ + wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { u32 val, mask; - u32 off = pll->offset; - regmap_write(regmap, off + PLL_L_VAL, config->l); - regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha); - regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val); - regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val); + regmap_write(regmap, PLL_L_VAL(pll), config->l); + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); + regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); + + if (pll_has_64bit_config(pll)) + regmap_write(regmap, PLL_CONFIG_CTL_U(pll), + config->config_ctl_hi_val); + + if (pll_alpha_width(pll) > 32) + regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); val = config->main_output_mask; val |= config->aux_output_mask; @@ -127,6 +192,8 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, val |= config->pre_div_val; val |= config->post_div_val; val |= config->vco_val; + val |= config->alpha_en_mask; + val |= config->alpha_mode_mask; mask = config->main_output_mask; mask |= config->aux_output_mask; @@ -136,20 +203,19 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, mask |= config->post_div_mask; mask |= config->vco_mask; - regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val); + regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); if (pll->flags & SUPPORTS_FSM_MODE) - qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0); + qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); } static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) { int ret; - u32 val, off; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; - off = pll->offset; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; @@ -158,7 +224,7 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) if (pll->flags & SUPPORTS_OFFLINE_REQ) val &= ~PLL_OFFLINE_REQ; - ret = regmap_write(pll->clkr.regmap, off + PLL_MODE, val); + ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); if (ret) return ret; @@ -171,16 +237,15 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) { int ret; - u32 val, off; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; - off = pll->offset; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return; if (pll->flags & SUPPORTS_OFFLINE_REQ) { - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); if (ret) return; @@ -191,7 +256,7 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) } /* Disable hwfsm */ - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_FSM_ENA, 0); if (ret) return; @@ -202,11 +267,10 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) static int pll_is_enabled(struct clk_hw *hw, u32 mask) { int ret; - u32 val, off; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 val; - off = pll->offset; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; @@ -227,12 +291,10 @@ static int clk_alpha_pll_enable(struct clk_hw *hw) { int ret; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 val, mask, off; - - off = pll->offset; + u32 val, mask; mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return ret; @@ -248,7 +310,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw) if ((val & mask) == mask) return 0; - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); if (ret) return ret; @@ -260,7 +322,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw) mb(); udelay(5); - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); if (ret) return ret; @@ -269,7 +331,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw) if (ret) return ret; - ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, + ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); /* Ensure that the write above goes through before returning. */ @@ -281,11 +343,9 @@ static void clk_alpha_pll_disable(struct clk_hw *hw) { int ret; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 val, mask, off; - - off = pll->offset; + u32 val, mask; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return; @@ -296,23 +356,25 @@ static void clk_alpha_pll_disable(struct clk_hw *hw) } mask = PLL_OUTCTRL; - regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0); + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); /* Delay of 2 output clock ticks required until output is disabled */ mb(); udelay(1); mask = PLL_RESET_N | PLL_BYPASSNL; - regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0); + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); } -static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a) +static unsigned long +alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) { - return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH); + return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); } static unsigned long -alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a) +alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, + u32 alpha_width) { u64 remainder; u64 quotient; @@ -327,14 +389,15 @@ alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a) } /* Upper ALPHA_BITWIDTH bits of Alpha */ - quotient = remainder << ALPHA_BITWIDTH; + quotient = remainder << ALPHA_SHIFT(alpha_width); + remainder = do_div(quotient, prate); if (remainder) quotient++; *a = quotient; - return alpha_pll_calc_rate(prate, *l, *a); + return alpha_pll_calc_rate(prate, *l, *a, alpha_width); } static const struct pll_vco * @@ -356,71 +419,138 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) u32 l, low, high, ctl; u64 a = 0, prate = parent_rate; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 off = pll->offset; + u32 alpha_width = pll_alpha_width(pll); - regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l); + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); - regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl); + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); if (ctl & PLL_ALPHA_EN) { - regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low); - if (pll->flags & SUPPORTS_16BIT_ALPHA) { - a = low & ALPHA_16BIT_MASK; - } else { - regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); + if (alpha_width > 32) { + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), &high); a = (u64)high << 32 | low; - a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; + } else { + a = low & GENMASK(alpha_width - 1, 0); } + + if (alpha_width > ALPHA_BITWIDTH) + a >>= alpha_width - ALPHA_BITWIDTH; } - return alpha_pll_calc_rate(prate, l, a); + return alpha_pll_calc_rate(prate, l, a, alpha_width); } -static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long prate) +static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, + int (*is_enabled)(struct clk_hw *)) +{ + int ret; + u32 mode; + + if (!is_enabled(&pll->clkr.hw) || + !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) + return 0; + + regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); + + /* Latch the input to the PLL */ + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, + PLL_UPDATE); + + /* Wait for 2 reference cycle before checking ACK bit */ + udelay(1); + + /* + * PLL will latch the new L, Alpha and freq control word. + * PLL will respond by raising PLL_ACK_LATCH output when new programming + * has been latched in and PLL is being updated. When + * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared + * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. + */ + if (mode & PLL_UPDATE_BYPASS) { + ret = wait_for_pll_update_ack_set(pll); + if (ret) + return ret; + + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); + } else { + ret = wait_for_pll_update(pll); + if (ret) + return ret; + } + + ret = wait_for_pll_update_ack_clear(pll); + if (ret) + return ret; + + /* Wait for PLL output to stabilize */ + udelay(10); + + return 0; +} + +static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate, + int (*is_enabled)(struct clk_hw *)) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); const struct pll_vco *vco; - u32 l, off = pll->offset; + u32 l, alpha_width = pll_alpha_width(pll); u64 a; - rate = alpha_pll_round_rate(rate, prate, &l, &a); + rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); vco = alpha_pll_find_vco(pll, rate); - if (!vco) { + if (pll->vco_table && !vco) { pr_err("alpha pll not in a valid vco range\n"); return -EINVAL; } - regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l); + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); - if (pll->flags & SUPPORTS_16BIT_ALPHA) { - regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, - a & ALPHA_16BIT_MASK); - } else { - a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH); - regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32); + if (alpha_width > ALPHA_BITWIDTH) + a <<= alpha_width - ALPHA_BITWIDTH; + + if (alpha_width > 32) + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32); + + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + + if (vco) { + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_VCO_MASK << PLL_VCO_SHIFT, + vco->val << PLL_VCO_SHIFT); } - regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, - PLL_VCO_MASK << PLL_VCO_SHIFT, - vco->val << PLL_VCO_SHIFT); + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_ALPHA_EN, PLL_ALPHA_EN); - regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN, - PLL_ALPHA_EN); + return clk_alpha_pll_update_latch(pll, is_enabled); +} - return 0; +static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return __clk_alpha_pll_set_rate(hw, rate, prate, + clk_alpha_pll_is_enabled); +} + +static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + return __clk_alpha_pll_set_rate(hw, rate, prate, + clk_alpha_pll_hwfsm_is_enabled); } static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 l; + u32 l, alpha_width = pll_alpha_width(pll); u64 a; unsigned long min_freq, max_freq; - rate = alpha_pll_round_rate(rate, *prate, &l, &a); - if (alpha_pll_find_vco(pll, rate)) + rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width); + if (!pll->vco_table || alpha_pll_find_vco(pll, rate)) return rate; min_freq = pll->vco_table[0].min_freq; @@ -429,6 +559,158 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate, return clamp(rate, min_freq, max_freq); } +static unsigned long +alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) +{ + /* + * a contains 16 bit alpha_val in two’s compliment number in the range + * of [-0.5, 0.5). + */ + if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) + l -= 1; + + return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); +} + +static unsigned long +alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, + u32 *l, u32 *a) +{ + u64 remainder; + u64 quotient; + + quotient = rate; + remainder = do_div(quotient, prate); + *l = quotient; + + if (!remainder) { + *a = 0; + return rate; + } + + quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; + remainder = do_div(quotient, prate); + + if (remainder) + quotient++; + + /* + * alpha_val should be in two’s compliment number in the range + * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value + * since alpha value will be subtracted in this case. + */ + if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) + *l += 1; + + *a = quotient; + return alpha_huayra_pll_calc_rate(prate, *l, *a); +} + +static unsigned long +alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + u64 rate = parent_rate, tmp; + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l, alpha = 0, ctl, alpha_m, alpha_n; + + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); + + if (ctl & PLL_ALPHA_EN) { + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); + /* + * Depending upon alpha_mode, it can be treated as M/N value or + * as a two’s compliment number. When alpha_mode=1, + * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N + * + * Fout=FIN*(L+(M/N)) + * + * M is a signed number (-128 to 127) and N is unsigned + * (0 to 255). M/N has to be within +/-0.5. + * + * When alpha_mode=0, it is a two’s compliment number in the + * range [-0.5, 0.5). + * + * Fout=FIN*(L+(alpha_val)/2^16) + * + * where alpha_val is two’s compliment number. + */ + if (!(ctl & PLL_ALPHA_MODE)) + return alpha_huayra_pll_calc_rate(rate, l, alpha); + + alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; + alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; + + rate *= l; + tmp = parent_rate; + if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { + alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; + tmp *= alpha_m; + do_div(tmp, alpha_n); + rate -= tmp; + } else { + tmp *= alpha_m; + do_div(tmp, alpha_n); + rate += tmp; + } + + return rate; + } + + return alpha_huayra_pll_calc_rate(rate, l, alpha); +} + +static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 l, a, ctl, cur_alpha = 0; + + rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); + + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); + + if (ctl & PLL_ALPHA_EN) + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); + + /* + * Huayra PLL supports PLL dynamic programming. User can change L_VAL, + * without having to go through the power on sequence. + */ + if (clk_alpha_pll_is_enabled(hw)) { + if (cur_alpha != a) { + pr_err("clock needs to be gated %s\n", + clk_hw_get_name(hw)); + return -EBUSY; + } + + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + /* Ensure that the write above goes to detect L val change. */ + mb(); + return wait_for_pll_enable_lock(pll); + } + + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); + + if (a == 0) + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_ALPHA_EN, 0x0); + else + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); + + return 0; +} + +static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + u32 l, a; + + return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); +} + const struct clk_ops clk_alpha_pll_ops = { .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, @@ -439,13 +721,23 @@ const struct clk_ops clk_alpha_pll_ops = { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); +const struct clk_ops clk_alpha_pll_huayra_ops = { + .enable = clk_alpha_pll_enable, + .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, + .recalc_rate = alpha_pll_huayra_recalc_rate, + .round_rate = alpha_pll_huayra_round_rate, + .set_rate = alpha_pll_huayra_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); + const struct clk_ops clk_alpha_pll_hwfsm_ops = { .enable = clk_alpha_pll_hwfsm_enable, .disable = clk_alpha_pll_hwfsm_disable, .is_enabled = clk_alpha_pll_hwfsm_is_enabled, .recalc_rate = clk_alpha_pll_recalc_rate, .round_rate = clk_alpha_pll_round_rate, - .set_rate = clk_alpha_pll_set_rate, + .set_rate = clk_alpha_pll_hwfsm_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); @@ -455,10 +747,10 @@ clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); u32 ctl; - regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl); + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); ctl >>= PLL_POST_DIV_SHIFT; - ctl &= PLL_POST_DIV_MASK; + ctl &= PLL_POST_DIV_MASK(pll); return parent_rate >> fls(ctl); } @@ -472,16 +764,48 @@ static const struct clk_div_table clk_alpha_div_table[] = { { } }; +static const struct clk_div_table clk_alpha_2bit_div_table[] = { + { 0x0, 1 }, + { 0x1, 2 }, + { 0x3, 4 }, + { } +}; + static long clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + const struct clk_div_table *table; - return divider_round_rate(hw, rate, prate, clk_alpha_div_table, + if (pll->width == 2) + table = clk_alpha_2bit_div_table; + else + table = clk_alpha_div_table; + + return divider_round_rate(hw, rate, prate, table, pll->width, CLK_DIVIDER_POWER_OF_TWO); } +static long +clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); + u32 ctl, div; + + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); + + ctl >>= PLL_POST_DIV_SHIFT; + ctl &= BIT(pll->width) - 1; + div = 1 << fls(ctl); + + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) + *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate); + + return DIV_ROUND_UP_ULL((u64)*prate, div); +} + static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -491,8 +815,8 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; - return regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL, - PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT, + return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, div << PLL_POST_DIV_SHIFT); } @@ -502,3 +826,9 @@ const struct clk_ops clk_alpha_pll_postdiv_ops = { .set_rate = clk_alpha_pll_postdiv_set_rate, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); + +const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { + .round_rate = clk_alpha_pll_postdiv_round_ro_rate, + .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index d6e1ee2c7348..7593e8a56cf2 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -17,6 +17,30 @@ #include <linux/clk-provider.h> #include "clk-regmap.h" +/* Alpha PLL types */ +enum { + CLK_ALPHA_PLL_TYPE_DEFAULT, + CLK_ALPHA_PLL_TYPE_HUAYRA, + CLK_ALPHA_PLL_TYPE_BRAMMO, + CLK_ALPHA_PLL_TYPE_MAX, +}; + +enum { + PLL_OFF_L_VAL, + PLL_OFF_ALPHA_VAL, + PLL_OFF_ALPHA_VAL_U, + PLL_OFF_USER_CTL, + PLL_OFF_USER_CTL_U, + PLL_OFF_CONFIG_CTL, + PLL_OFF_CONFIG_CTL_U, + PLL_OFF_TEST_CTL, + PLL_OFF_TEST_CTL_U, + PLL_OFF_STATUS, + PLL_OFF_MAX_REGS +}; + +extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; + struct pll_vco { unsigned long min_freq; unsigned long max_freq; @@ -27,16 +51,18 @@ struct pll_vco { * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers * @vco_table: array of VCO settings + * @regs: alpha pll register map (see @clk_alpha_pll_regs) * @clkr: regmap clock handle */ struct clk_alpha_pll { u32 offset; + const u8 *regs; const struct pll_vco *vco_table; size_t num_vco; #define SUPPORTS_OFFLINE_REQ BIT(0) -#define SUPPORTS_16BIT_ALPHA BIT(1) #define SUPPORTS_FSM_MODE BIT(2) +#define SUPPORTS_DYNAMIC_UPDATE BIT(3) u8 flags; struct clk_regmap clkr; @@ -45,12 +71,14 @@ struct clk_alpha_pll { /** * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider * @offset: base address of registers + * @regs: alpha pll register map (see @clk_alpha_pll_regs) * @width: width of post-divider * @clkr: regmap clock handle */ struct clk_alpha_pll_postdiv { u32 offset; u8 width; + const u8 *regs; struct clk_regmap clkr; }; @@ -58,12 +86,15 @@ struct clk_alpha_pll_postdiv { struct alpha_pll_config { u32 l; u32 alpha; + u32 alpha_hi; u32 config_ctl_val; u32 config_ctl_hi_val; u32 main_output_mask; u32 aux_output_mask; u32 aux2_output_mask; u32 early_output_mask; + u32 alpha_en_mask; + u32 alpha_mode_mask; u32 pre_div_val; u32 pre_div_mask; u32 post_div_val; @@ -75,6 +106,8 @@ struct alpha_pll_config { extern const struct clk_ops clk_alpha_pll_ops; extern const struct clk_ops clk_alpha_pll_hwfsm_ops; extern const struct clk_ops clk_alpha_pll_postdiv_ops; +extern const struct clk_ops clk_alpha_pll_huayra_ops; +extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); diff --git a/drivers/clk/qcom/clk-spmi-pmic-div.c b/drivers/clk/qcom/clk-spmi-pmic-div.c new file mode 100644 index 000000000000..8672ab84746f --- /dev/null +++ b/drivers/clk/qcom/clk-spmi-pmic-div.c @@ -0,0 +1,302 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/log2.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <linux/types.h> + +#define REG_DIV_CTL1 0x43 +#define DIV_CTL1_DIV_FACTOR_MASK GENMASK(2, 0) + +#define REG_EN_CTL 0x46 +#define REG_EN_MASK BIT(7) + +struct clkdiv { + struct regmap *regmap; + u16 base; + spinlock_t lock; + + struct clk_hw hw; + unsigned int cxo_period_ns; +}; + +static inline struct clkdiv *to_clkdiv(struct clk_hw *hw) +{ + return container_of(hw, struct clkdiv, hw); +} + +static inline unsigned int div_factor_to_div(unsigned int div_factor) +{ + if (!div_factor) + div_factor = 1; + + return 1 << (div_factor - 1); +} + +static inline unsigned int div_to_div_factor(unsigned int div) +{ + return min(ilog2(div) + 1, 7); +} + +static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) +{ + unsigned int val = 0; + + regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); + + return val & REG_EN_MASK; +} + +static int +__spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, + unsigned int div_factor) +{ + int ret; + unsigned int ns = clkdiv->cxo_period_ns; + unsigned int div = div_factor_to_div(div_factor); + + ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL, + REG_EN_MASK, enable ? REG_EN_MASK : 0); + if (ret) + return ret; + + if (enable) + ndelay((2 + 3 * div) * ns); + else + ndelay(3 * div * ns); + + return 0; +} + +static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable) +{ + unsigned int div_factor; + + regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); + div_factor &= DIV_CTL1_DIV_FACTOR_MASK; + + return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor); +} + +static int clk_spmi_pmic_div_enable(struct clk_hw *hw) +{ + struct clkdiv *clkdiv = to_clkdiv(hw); + unsigned long flags; + int ret; + + spin_lock_irqsave(&clkdiv->lock, flags); + ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true); + spin_unlock_irqrestore(&clkdiv->lock, flags); + + return ret; +} + +static void clk_spmi_pmic_div_disable(struct clk_hw *hw) +{ + struct clkdiv *clkdiv = to_clkdiv(hw); + unsigned long flags; + + spin_lock_irqsave(&clkdiv->lock, flags); + spmi_pmic_clkdiv_set_enable_state(clkdiv, false); + spin_unlock_irqrestore(&clkdiv->lock, flags); +} + +static long clk_spmi_pmic_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned int div, div_factor; + + div = DIV_ROUND_UP(*parent_rate, rate); + div_factor = div_to_div_factor(div); + div = div_factor_to_div(div_factor); + + return *parent_rate / div; +} + +static unsigned long +clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clkdiv *clkdiv = to_clkdiv(hw); + unsigned int div_factor; + + regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); + div_factor &= DIV_CTL1_DIV_FACTOR_MASK; + + return parent_rate / div_factor_to_div(div_factor); +} + +static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clkdiv *clkdiv = to_clkdiv(hw); + unsigned int div_factor = div_to_div_factor(parent_rate / rate); + unsigned long flags; + bool enabled; + int ret; + + spin_lock_irqsave(&clkdiv->lock, flags); + enabled = is_spmi_pmic_clkdiv_enabled(clkdiv); + if (enabled) { + ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false); + if (ret) + goto unlock; + } + + ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, + DIV_CTL1_DIV_FACTOR_MASK, div_factor); + if (ret) + goto unlock; + + if (enabled) + ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true, + div_factor); + +unlock: + spin_unlock_irqrestore(&clkdiv->lock, flags); + + return ret; +} + +static const struct clk_ops clk_spmi_pmic_div_ops = { + .enable = clk_spmi_pmic_div_enable, + .disable = clk_spmi_pmic_div_disable, + .set_rate = clk_spmi_pmic_div_set_rate, + .recalc_rate = clk_spmi_pmic_div_recalc_rate, + .round_rate = clk_spmi_pmic_div_round_rate, +}; + +struct spmi_pmic_div_clk_cc { + int nclks; + struct clkdiv clks[]; +}; + +static struct clk_hw * +spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data) +{ + struct spmi_pmic_div_clk_cc *cc = data; + int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */ + + if (idx < 0 || idx >= cc->nclks) { + pr_err("%s: index value %u is invalid; allowed range [1, %d]\n", + __func__, clkspec->args[0], cc->nclks); + return ERR_PTR(-EINVAL); + } + + return &cc->clks[idx].hw; +} + +static int spmi_pmic_clkdiv_probe(struct platform_device *pdev) +{ + struct spmi_pmic_div_clk_cc *cc; + struct clk_init_data init = {}; + struct clkdiv *clkdiv; + struct clk *cxo; + struct regmap *regmap; + struct device *dev = &pdev->dev; + struct device_node *of_node = dev->of_node; + const char *parent_name; + int nclks, i, ret, cxo_hz; + char name[20]; + u32 start; + + ret = of_property_read_u32(of_node, "reg", &start); + if (ret < 0) { + dev_err(dev, "reg property reading failed\n"); + return ret; + } + + regmap = dev_get_regmap(dev->parent, NULL); + if (!regmap) { + dev_err(dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + ret = of_property_read_u32(of_node, "qcom,num-clkdivs", &nclks); + if (ret < 0) { + dev_err(dev, "qcom,num-clkdivs property reading failed, ret=%d\n", + ret); + return ret; + } + + if (!nclks) + return -EINVAL; + + cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*cc->clks) * nclks, + GFP_KERNEL); + if (!cc) + return -ENOMEM; + cc->nclks = nclks; + + cxo = clk_get(dev, "xo"); + if (IS_ERR(cxo)) { + ret = PTR_ERR(cxo); + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get xo clock\n"); + return ret; + } + cxo_hz = clk_get_rate(cxo); + clk_put(cxo); + + parent_name = of_clk_get_parent_name(of_node, 0); + if (!parent_name) { + dev_err(dev, "missing parent clock\n"); + return -ENODEV; + } + + init.name = name; + init.parent_names = &parent_name; + init.num_parents = 1; + init.ops = &clk_spmi_pmic_div_ops; + + for (i = 0, clkdiv = cc->clks; i < nclks; i++) { + snprintf(name, sizeof(name), "div_clk%d", i + 1); + + spin_lock_init(&clkdiv[i].lock); + clkdiv[i].base = start + i * 0x100; + clkdiv[i].regmap = regmap; + clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz; + clkdiv[i].hw.init = &init; + + ret = devm_clk_hw_register(dev, &clkdiv[i].hw); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(dev, spmi_pmic_div_clk_hw_get, cc); +} + +static const struct of_device_id spmi_pmic_clkdiv_match_table[] = { + { .compatible = "qcom,spmi-clkdiv" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table); + +static struct platform_driver spmi_pmic_clkdiv_driver = { + .driver = { + .name = "qcom,spmi-pmic-clkdiv", + .of_match_table = spmi_pmic_clkdiv_match_table, + }, + .probe = spmi_pmic_clkdiv_probe, +}; +module_platform_driver(spmi_pmic_clkdiv_driver); + +MODULE_DESCRIPTION("QCOM SPMI PMIC clkdiv driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 0f735d37690f..ed2d00f55378 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -52,6 +52,7 @@ static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { static struct clk_alpha_pll gpll0_main = { .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x0b000, .enable_mask = BIT(0), @@ -82,6 +83,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", .parent_names = (const char *[]){ diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c index 3410ee68d4bc..d6c7f50ba86a 100644 --- a/drivers/clk/qcom/gcc-msm8916.c +++ b/drivers/clk/qcom/gcc-msm8916.c @@ -1259,20 +1259,25 @@ static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = { }; static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = { + F(128000, P_XO, 10, 1, 15), F(256000, P_XO, 5, 1, 15), + F(384000, P_XO, 5, 1, 10), F(512000, P_XO, 5, 2, 15), + F(576000, P_XO, 5, 3, 20), F(705600, P_GPLL1, 16, 1, 80), F(768000, P_XO, 5, 1, 5), F(800000, P_XO, 5, 5, 24), - F(1024000, P_GPLL1, 14, 1, 63), + F(1024000, P_XO, 5, 4, 15), F(1152000, P_XO, 1, 3, 50), F(1411200, P_GPLL1, 16, 1, 40), F(1536000, P_XO, 1, 2, 25), F(1600000, P_XO, 12, 0, 0), - F(2048000, P_GPLL1, 9, 1, 49), + F(1728000, P_XO, 5, 9, 20), + F(2048000, P_XO, 5, 8, 15), + F(2304000, P_XO, 5, 3, 5), F(2400000, P_XO, 8, 0, 0), F(2822400, P_GPLL1, 16, 1, 20), - F(3072000, P_GPLL1, 14, 1, 21), + F(3072000, P_XO, 5, 4, 5), F(4096000, P_GPLL1, 9, 2, 49), F(4800000, P_XO, 4, 0, 0), F(5644800, P_GPLL1, 16, 1, 10), @@ -1431,6 +1436,7 @@ static struct clk_branch gcc_ultaudio_stc_xo_clk = { static const struct freq_tbl ftbl_codec_clk[] = { F(9600000, P_XO, 2, 0, 0), + F(12288000, P_XO, 1, 16, 25), F(19200000, P_XO, 1, 0, 0), F(11289600, P_EXT_MCLK, 1, 0, 0), { } @@ -1438,6 +1444,7 @@ static const struct freq_tbl ftbl_codec_clk[] = { static struct clk_rcg2 codec_digcodec_clk_src = { .cmd_rcgr = 0x1c09c, + .mnd_width = 8, .hid_width = 5, .parent_map = gcc_xo_gpll1_emclk_sleep_map, .freq_tbl = ftbl_codec_clk, diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 7983288d9141..1e38efc37180 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -73,6 +73,7 @@ static struct clk_fixed_factor xo = { static struct clk_alpha_pll gpll0_early = { .offset = 0x00000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x1480, .enable_mask = BIT(0), @@ -88,6 +89,7 @@ static struct clk_alpha_pll gpll0_early = { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x00000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data) { .name = "gpll0", @@ -99,6 +101,7 @@ static struct clk_alpha_pll_postdiv gpll0 = { static struct clk_alpha_pll gpll4_early = { .offset = 0x1dc0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x1480, .enable_mask = BIT(4), @@ -114,6 +117,7 @@ static struct clk_alpha_pll gpll4_early = { static struct clk_alpha_pll_postdiv gpll4 = { .offset = 0x1dc0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data) { .name = "gpll4", diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 7ddec886fcd3..5d7451209206 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -227,6 +227,7 @@ static struct clk_fixed_factor xo = { static struct clk_alpha_pll gpll0_early = { .offset = 0x00000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(0), @@ -252,6 +253,7 @@ static struct clk_fixed_factor gpll0_early_div = { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x00000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", .parent_names = (const char *[]){ "gpll0_early" }, @@ -262,6 +264,7 @@ static struct clk_alpha_pll_postdiv gpll0 = { static struct clk_alpha_pll gpll4_early = { .offset = 0x77000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr = { .enable_reg = 0x52000, .enable_mask = BIT(4), @@ -276,6 +279,7 @@ static struct clk_alpha_pll gpll4_early = { static struct clk_alpha_pll_postdiv gpll4 = { .offset = 0x77000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4", .parent_names = (const char *[]){ "gpll4_early" }, diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 352394d8fd8c..66a2fa4ec93c 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -267,6 +267,7 @@ static struct pll_vco mmpll_t_vco[] = { static struct clk_alpha_pll mmpll0_early = { .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_p_vco, .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr = { @@ -283,6 +284,7 @@ static struct clk_alpha_pll mmpll0_early = { static struct clk_alpha_pll_postdiv mmpll0 = { .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll0", @@ -295,6 +297,7 @@ static struct clk_alpha_pll_postdiv mmpll0 = { static struct clk_alpha_pll mmpll1_early = { .offset = 0x30, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_p_vco, .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr = { @@ -311,6 +314,7 @@ static struct clk_alpha_pll mmpll1_early = { static struct clk_alpha_pll_postdiv mmpll1 = { .offset = 0x30, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll1", @@ -323,6 +327,7 @@ static struct clk_alpha_pll_postdiv mmpll1 = { static struct clk_alpha_pll mmpll2_early = { .offset = 0x4100, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_gfx_vco, .num_vco = ARRAY_SIZE(mmpll_gfx_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -335,6 +340,7 @@ static struct clk_alpha_pll mmpll2_early = { static struct clk_alpha_pll_postdiv mmpll2 = { .offset = 0x4100, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll2", @@ -347,6 +353,7 @@ static struct clk_alpha_pll_postdiv mmpll2 = { static struct clk_alpha_pll mmpll3_early = { .offset = 0x60, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_p_vco, .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -359,6 +366,7 @@ static struct clk_alpha_pll mmpll3_early = { static struct clk_alpha_pll_postdiv mmpll3 = { .offset = 0x60, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll3", @@ -371,6 +379,7 @@ static struct clk_alpha_pll_postdiv mmpll3 = { static struct clk_alpha_pll mmpll4_early = { .offset = 0x90, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_t_vco, .num_vco = ARRAY_SIZE(mmpll_t_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -383,6 +392,7 @@ static struct clk_alpha_pll mmpll4_early = { static struct clk_alpha_pll_postdiv mmpll4 = { .offset = 0x90, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 2, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll4", @@ -395,6 +405,7 @@ static struct clk_alpha_pll_postdiv mmpll4 = { static struct clk_alpha_pll mmpll5_early = { .offset = 0xc0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_p_vco, .num_vco = ARRAY_SIZE(mmpll_p_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -407,6 +418,7 @@ static struct clk_alpha_pll mmpll5_early = { static struct clk_alpha_pll_postdiv mmpll5 = { .offset = 0xc0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll5", @@ -419,6 +431,7 @@ static struct clk_alpha_pll_postdiv mmpll5 = { static struct clk_alpha_pll mmpll8_early = { .offset = 0x4130, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_gfx_vco, .num_vco = ARRAY_SIZE(mmpll_gfx_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -431,6 +444,7 @@ static struct clk_alpha_pll mmpll8_early = { static struct clk_alpha_pll_postdiv mmpll8 = { .offset = 0x4130, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll8", @@ -443,6 +457,7 @@ static struct clk_alpha_pll_postdiv mmpll8 = { static struct clk_alpha_pll mmpll9_early = { .offset = 0x4200, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .vco_table = mmpll_t_vco, .num_vco = ARRAY_SIZE(mmpll_t_vco), .clkr.hw.init = &(struct clk_init_data){ @@ -455,6 +470,7 @@ static struct clk_alpha_pll mmpll9_early = { static struct clk_alpha_pll_postdiv mmpll9 = { .offset = 0x4200, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .width = 2, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll9", diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c index 229c96daece6..f5be02205ac6 100644 --- a/drivers/clk/spear/clk-frac-synth.c +++ b/drivers/clk/spear/clk-frac-synth.c @@ -131,7 +131,7 @@ struct clk *clk_register_frac(const char *name, const char *parent_name, struct clk *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { - pr_err("Invalid arguments passed"); + pr_err("Invalid arguments passed\n"); return ERR_PTR(-EINVAL); } diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c index 28262f422562..6ed406d943ba 100644 --- a/drivers/clk/spear/clk-gpt-synth.c +++ b/drivers/clk/spear/clk-gpt-synth.c @@ -120,7 +120,7 @@ struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned struct clk *clk; if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { - pr_err("Invalid arguments passed"); + pr_err("Invalid arguments passed\n"); return ERR_PTR(-EINVAL); } diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index 0e47d95faf49..612491a26070 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -19,98 +19,201 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clk/ti.h> +#include <dt-bindings/clock/am3.h> #include "clock.h" +static const char * const am3_gpio1_dbclk_parents[] __initconst = { + "l4_per_cm:clk:0138:0", + NULL, +}; + +static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = { + { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = { + { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = { + { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = { + { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" }, + { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP, "lcd_gclk", "lcdc_clkdm" }, + { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" }, + { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" }, + { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, + { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" }, + { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, + { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" }, + { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, + { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, + { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, + { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, + { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, + { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" }, + { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, + { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, + { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" }, + { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, + { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, + { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, + { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" }, + { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" }, + { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" }, + { 0 }, +}; + +static const char * const am3_gpio0_dbclk_parents[] __initconst = { + "gpio0_dbclk_mux_ck", + NULL, +}; + +static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = { + { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL }, + { 0 }, +}; + +static const char * const am3_dbg_sysclk_ck_parents[] __initconst = { + "sys_clkin_ck", + NULL, +}; + +static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = { + "l4_wkup_cm:clk:0010:19", + "l4_wkup_cm:clk:0010:30", + NULL, +}; + +static const char * const am3_trace_clk_div_ck_parents[] __initconst = { + "l4_wkup_cm:clk:0010:20", + NULL, +}; + +static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = { + .max_div = 64, + .flags = CLK_DIVIDER_POWER_OF_TWO, +}; + +static const char * const am3_stm_clk_div_ck_parents[] __initconst = { + "l4_wkup_cm:clk:0010:22", + NULL, +}; + +static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = { + .max_div = 64, + .flags = CLK_DIVIDER_POWER_OF_TWO, +}; + +static const char * const am3_dbg_clka_ck_parents[] __initconst = { + "dpll_core_m4_ck", + NULL, +}; + +static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = { + { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL }, + { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL }, + { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL }, + { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data }, + { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data }, + { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = { + { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, + { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, + { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, + { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" }, + { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" }, + { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, + { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, + { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" }, + { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" }, + { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" }, + { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" }, + { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = { + { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = { + { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = { + { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = { + { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" }, + { 0 }, +}; + +const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = { + { 0x44e00014, am3_l4_per_clkctrl_regs }, + { 0x44e00404, am3_l4_wkup_clkctrl_regs }, + { 0x44e00604, am3_mpu_clkctrl_regs }, + { 0x44e00800, am3_l4_rtc_clkctrl_regs }, + { 0x44e00904, am3_gfx_l3_clkctrl_regs }, + { 0x44e00a20, am3_l4_cefuse_clkctrl_regs }, + { 0 }, +}; + static struct ti_dt_clk am33xx_clks[] = { - DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), - DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), - DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), - DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), - DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), - DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), - DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), - DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), - DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), - DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), - DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), - DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), - DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), - DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), - DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), - DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), - DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), - DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"), - DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), - DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), - DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), - DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), - DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), - DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), - DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), - DT_CLK(NULL, "cefuse_fck", "cefuse_fck"), - DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), - DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), - DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), - DT_CLK("481cc000.d_can", NULL, "dcan0_fck"), - DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), - DT_CLK("481d0000.d_can", NULL, "dcan1_fck"), - DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), - DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), - DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), - DT_CLK(NULL, "mmu_fck", "mmu_fck"), - DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), - DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), - DT_CLK(NULL, "sha0_fck", "sha0_fck"), - DT_CLK(NULL, "aes0_fck", "aes0_fck"), - DT_CLK(NULL, "rng_fck", "rng_fck"), - DT_CLK(NULL, "timer1_fck", "timer1_fck"), - DT_CLK(NULL, "timer2_fck", "timer2_fck"), - DT_CLK(NULL, "timer3_fck", "timer3_fck"), - DT_CLK(NULL, "timer4_fck", "timer4_fck"), - DT_CLK(NULL, "timer5_fck", "timer5_fck"), - DT_CLK(NULL, "timer6_fck", "timer6_fck"), - DT_CLK(NULL, "timer7_fck", "timer7_fck"), - DT_CLK(NULL, "usbotg_fck", "usbotg_fck"), - DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"), - DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), - DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"), - DT_CLK(NULL, "l3_gclk", "l3_gclk"), - DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), - DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), - DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), - DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"), - DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), - DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), - DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"), - DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), - DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), - DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), - DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), - DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), - DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), - DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), - DT_CLK(NULL, "lcd_gclk", "lcd_gclk"), - DT_CLK(NULL, "mmc_clk", "mmc_clk"), - DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), - DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), - DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"), - DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"), - DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), + DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"), DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), - DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"), - DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"), - DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"), - DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"), - DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), - DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), - DT_CLK(NULL, "clkout2_ck", "clkout2_ck"), - DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), - DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), - DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), - DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"), - DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"), - DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"), + DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"), + DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"), + DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"), + DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"), + DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"), + DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"), + DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"), + DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"), + DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"), + DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"), + DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"), { .node_name = NULL }, }; @@ -133,6 +236,8 @@ int __init am33xx_dt_clk_init(void) omap2_clk_disable_autoidle_all(); + ti_clk_add_aliases(); + omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c index b1251cae98b8..8aa5f5793835 100644 --- a/drivers/clk/ti/clk-3xxx.c +++ b/drivers/clk/ti/clk-3xxx.c @@ -224,296 +224,43 @@ const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { }; static struct ti_dt_clk omap3xxx_clks[] = { - DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), - DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"), - DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"), - DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"), - DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), - DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), - DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"), - DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"), - DT_CLK("twl", "fck", "osc_sys_ck"), - DT_CLK(NULL, "sys_ck", "sys_ck"), - DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"), - DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"), - DT_CLK(NULL, "sys_altclk", "sys_altclk"), - DT_CLK(NULL, "sys_clkout1", "sys_clkout1"), - DT_CLK(NULL, "dpll1_ck", "dpll1_ck"), - DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"), - DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"), - DT_CLK(NULL, "dpll3_ck", "dpll3_ck"), - DT_CLK(NULL, "core_ck", "core_ck"), - DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"), - DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"), - DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"), - DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"), - DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"), - DT_CLK(NULL, "dpll4_ck", "dpll4_ck"), - DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"), - DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"), - DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"), - DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"), - DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"), - DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"), - DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"), - DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"), - DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"), - DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"), - DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"), - DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"), - DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"), - DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"), - DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"), - DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"), - DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"), - DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"), - DT_CLK(NULL, "sys_clkout2", "sys_clkout2"), - DT_CLK(NULL, "corex2_fck", "corex2_fck"), - DT_CLK(NULL, "dpll1_fck", "dpll1_fck"), - DT_CLK(NULL, "mpu_ck", "mpu_ck"), - DT_CLK(NULL, "arm_fck", "arm_fck"), - DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"), - DT_CLK(NULL, "l3_ick", "l3_ick"), - DT_CLK(NULL, "l4_ick", "l4_ick"), - DT_CLK(NULL, "rm_ick", "rm_ick"), - DT_CLK(NULL, "gpt10_fck", "gpt10_fck"), - DT_CLK(NULL, "gpt11_fck", "gpt11_fck"), - DT_CLK(NULL, "core_96m_fck", "core_96m_fck"), - DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"), - DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"), - DT_CLK(NULL, "i2c3_fck", "i2c3_fck"), - DT_CLK(NULL, "i2c2_fck", "i2c2_fck"), - DT_CLK(NULL, "i2c1_fck", "i2c1_fck"), - DT_CLK(NULL, "core_48m_fck", "core_48m_fck"), - DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"), - DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"), - DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"), - DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"), - DT_CLK(NULL, "uart2_fck", "uart2_fck"), - DT_CLK(NULL, "uart1_fck", "uart1_fck"), - DT_CLK(NULL, "core_12m_fck", "core_12m_fck"), - DT_CLK("omap_hdq.0", "fck", "hdq_fck"), - DT_CLK(NULL, "hdq_fck", "hdq_fck"), - DT_CLK(NULL, "core_l3_ick", "core_l3_ick"), - DT_CLK(NULL, "sdrc_ick", "sdrc_ick"), - DT_CLK(NULL, "gpmc_fck", "gpmc_fck"), - DT_CLK(NULL, "core_l4_ick", "core_l4_ick"), - DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"), - DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"), - DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"), - DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"), - DT_CLK("omap_hdq.0", "ick", "hdq_ick"), - DT_CLK(NULL, "hdq_ick", "hdq_ick"), - DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"), - DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"), - DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"), - DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"), - DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"), - DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"), - DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"), - DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"), - DT_CLK("omap_i2c.3", "ick", "i2c3_ick"), - DT_CLK("omap_i2c.2", "ick", "i2c2_ick"), - DT_CLK("omap_i2c.1", "ick", "i2c1_ick"), - DT_CLK(NULL, "i2c3_ick", "i2c3_ick"), - DT_CLK(NULL, "i2c2_ick", "i2c2_ick"), - DT_CLK(NULL, "i2c1_ick", "i2c1_ick"), - DT_CLK(NULL, "uart2_ick", "uart2_ick"), - DT_CLK(NULL, "uart1_ick", "uart1_ick"), - DT_CLK(NULL, "gpt11_ick", "gpt11_ick"), - DT_CLK(NULL, "gpt10_ick", "gpt10_ick"), - DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"), - DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"), - DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"), - DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"), - DT_CLK(NULL, "init_60m_fclk", "dummy_ck"), - DT_CLK(NULL, "gpt1_fck", "gpt1_fck"), - DT_CLK(NULL, "aes2_ick", "aes2_ick"), - DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"), - DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"), - DT_CLK(NULL, "sha12_ick", "sha12_ick"), - DT_CLK(NULL, "wdt2_fck", "wdt2_fck"), - DT_CLK("omap_wdt", "ick", "wdt2_ick"), - DT_CLK(NULL, "wdt2_ick", "wdt2_ick"), - DT_CLK(NULL, "wdt1_ick", "wdt1_ick"), - DT_CLK(NULL, "gpio1_ick", "gpio1_ick"), - DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"), - DT_CLK(NULL, "gpt12_ick", "gpt12_ick"), - DT_CLK(NULL, "gpt1_ick", "gpt1_ick"), - DT_CLK(NULL, "per_96m_fck", "per_96m_fck"), - DT_CLK(NULL, "per_48m_fck", "per_48m_fck"), - DT_CLK(NULL, "uart3_fck", "uart3_fck"), - DT_CLK(NULL, "gpt2_fck", "gpt2_fck"), - DT_CLK(NULL, "gpt3_fck", "gpt3_fck"), - DT_CLK(NULL, "gpt4_fck", "gpt4_fck"), - DT_CLK(NULL, "gpt5_fck", "gpt5_fck"), - DT_CLK(NULL, "gpt6_fck", "gpt6_fck"), - DT_CLK(NULL, "gpt7_fck", "gpt7_fck"), - DT_CLK(NULL, "gpt8_fck", "gpt8_fck"), - DT_CLK(NULL, "gpt9_fck", "gpt9_fck"), - DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"), - DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"), - DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"), - DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"), - DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"), - DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"), - DT_CLK(NULL, "wdt3_fck", "wdt3_fck"), - DT_CLK(NULL, "per_l4_ick", "per_l4_ick"), - DT_CLK(NULL, "gpio6_ick", "gpio6_ick"), - DT_CLK(NULL, "gpio5_ick", "gpio5_ick"), - DT_CLK(NULL, "gpio4_ick", "gpio4_ick"), - DT_CLK(NULL, "gpio3_ick", "gpio3_ick"), - DT_CLK(NULL, "gpio2_ick", "gpio2_ick"), - DT_CLK(NULL, "wdt3_ick", "wdt3_ick"), - DT_CLK(NULL, "uart3_ick", "uart3_ick"), - DT_CLK(NULL, "gpt9_ick", "gpt9_ick"), - DT_CLK(NULL, "gpt8_ick", "gpt8_ick"), - DT_CLK(NULL, "gpt7_ick", "gpt7_ick"), - DT_CLK(NULL, "gpt6_ick", "gpt6_ick"), - DT_CLK(NULL, "gpt5_ick", "gpt5_ick"), - DT_CLK(NULL, "gpt4_ick", "gpt4_ick"), - DT_CLK(NULL, "gpt3_ick", "gpt3_ick"), - DT_CLK(NULL, "gpt2_ick", "gpt2_ick"), - DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"), - DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"), - DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"), - DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"), - DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"), - DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"), - DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"), - DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"), - DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"), - DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"), - DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"), - DT_CLK("etb", "emu_src_ck", "emu_src_ck"), - DT_CLK(NULL, "emu_src_ck", "emu_src_ck"), - DT_CLK(NULL, "pclk_fck", "pclk_fck"), - DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"), - DT_CLK(NULL, "atclk_fck", "atclk_fck"), - DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"), - DT_CLK(NULL, "traceclk_fck", "traceclk_fck"), - DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"), - DT_CLK(NULL, "gpt12_fck", "gpt12_fck"), - DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"), DT_CLK(NULL, "timer_sys_ck", "sys_ck"), - DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"), - { .node_name = NULL }, -}; - -static struct ti_dt_clk omap34xx_omap36xx_clks[] = { - DT_CLK(NULL, "aes1_ick", "aes1_ick"), - DT_CLK("omap_rng", "ick", "rng_ick"), - DT_CLK("omap3-rom-rng", "ick", "rng_ick"), - DT_CLK(NULL, "sha11_ick", "sha11_ick"), - DT_CLK(NULL, "des1_ick", "des1_ick"), - DT_CLK(NULL, "cam_mclk", "cam_mclk"), - DT_CLK(NULL, "cam_ick", "cam_ick"), - DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"), - DT_CLK(NULL, "security_l3_ick", "security_l3_ick"), - DT_CLK(NULL, "pka_ick", "pka_ick"), - DT_CLK(NULL, "icr_ick", "icr_ick"), - DT_CLK("omap-aes", "ick", "aes2_ick"), - DT_CLK("omap-sham", "ick", "sha12_ick"), - DT_CLK(NULL, "des2_ick", "des2_ick"), - DT_CLK(NULL, "mspro_ick", "mspro_ick"), - DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"), - DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"), - DT_CLK(NULL, "sr1_fck", "sr1_fck"), - DT_CLK(NULL, "sr2_fck", "sr2_fck"), - DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"), - DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"), - DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"), - DT_CLK(NULL, "dpll2_fck", "dpll2_fck"), - DT_CLK(NULL, "iva2_ck", "iva2_ck"), - DT_CLK(NULL, "modem_fck", "modem_fck"), - DT_CLK(NULL, "sad2d_ick", "sad2d_ick"), - DT_CLK(NULL, "mad2d_ick", "mad2d_ick"), - DT_CLK(NULL, "mspro_fck", "mspro_fck"), - DT_CLK(NULL, "dpll2_ck", "dpll2_ck"), - DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"), { .node_name = NULL }, }; static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = { DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"), DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"), - DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"), DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"), DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"), - DT_CLK(NULL, "usim_fck", "usim_fck"), - DT_CLK(NULL, "usim_ick", "usim_ick"), { .node_name = NULL }, }; static struct ti_dt_clk omap3430es1_clks[] = { - DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"), - DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"), - DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"), - DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"), - DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"), - DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"), - DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"), DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"), DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"), - DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"), DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"), - DT_CLK(NULL, "fac_ick", "fac_ick"), DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"), - DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"), DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"), - DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"), DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"), { .node_name = NULL }, }; static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = { - DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"), - DT_CLK(NULL, "dpll5_ck", "dpll5_ck"), - DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"), - DT_CLK(NULL, "sgx_fck", "sgx_fck"), - DT_CLK(NULL, "sgx_ick", "sgx_ick"), - DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"), - DT_CLK(NULL, "ts_fck", "ts_fck"), - DT_CLK(NULL, "usbtll_fck", "usbtll_fck"), - DT_CLK(NULL, "usbtll_ick", "usbtll_ick"), - DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"), - DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"), - DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"), DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"), - DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"), DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"), - DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"), - DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"), - DT_CLK(NULL, "usbhost_ick", "usbhost_ick"), { .node_name = NULL }, }; static struct ti_dt_clk am35xx_clks[] = { - DT_CLK(NULL, "ipss_ick", "ipss_ick"), - DT_CLK(NULL, "rmii_ck", "rmii_ck"), - DT_CLK(NULL, "pclk_ck", "pclk_ck"), - DT_CLK(NULL, "emac_ick", "emac_ick"), - DT_CLK(NULL, "emac_fck", "emac_fck"), - DT_CLK("davinci_emac.0", NULL, "emac_ick"), - DT_CLK("davinci_mdio.0", NULL, "emac_fck"), - DT_CLK("vpfe-capture", "master", "vpfe_ick"), - DT_CLK("vpfe-capture", "slave", "vpfe_fck"), DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"), DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"), - DT_CLK(NULL, "hecc_ck", "hecc_ck"), DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"), DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"), { .node_name = NULL }, }; -static struct ti_dt_clk omap36xx_clks[] = { - DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"), - DT_CLK(NULL, "uart4_fck", "uart4_fck"), - DT_CLK(NULL, "uart4_ick", "uart4_ick"), - { .node_name = NULL }, -}; - static const char *enable_init_clks[] = { "sdrc_ick", "gpmc_fck", @@ -579,16 +326,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type) soc_type == OMAP3_SOC_OMAP3630) ti_dt_clocks_register(omap36xx_omap3430es2plus_clks); - if (soc_type == OMAP3_SOC_OMAP3430_ES1 || - soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS || - soc_type == OMAP3_SOC_OMAP3630) - ti_dt_clocks_register(omap34xx_omap36xx_clks); - - if (soc_type == OMAP3_SOC_OMAP3630) - ti_dt_clocks_register(omap36xx_clks); - omap2_clk_disable_autoidle_all(); + ti_clk_add_aliases(); + omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index e816a7500e43..2b7c2e017665 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -19,109 +19,208 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clk/ti.h> +#include <dt-bindings/clock/am4.h> #include "clock.h" +static const char * const am4_synctimer_32kclk_parents[] __initconst = { + "mux_synctimer32k_ck", + NULL, +}; + +static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = { + { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL }, + { 0 }, +}; + +static const char * const am4_gpio0_dbclk_parents[] __initconst = { + "gpio0_dbclk_mux_ck", + NULL, +}; + +static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = { + { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = { + { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" }, + { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" }, + { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" }, + { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" }, + { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" }, + { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" }, + { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" }, + { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" }, + { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" }, + { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" }, + { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" }, + { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = { + { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = { + { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = { + { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" }, + { 0 }, +}; + +static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = { + "dpll_per_clkdcoldo", + NULL, +}; + +static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = { + { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = { + { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL }, + { 0 }, +}; + +static const char * const am4_gpio1_dbclk_parents[] __initconst = { + "clkdiv32k_ick", + NULL, +}; + +static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = { + { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = { + { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = { + { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = { + { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = { + { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = { + { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" }, + { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" }, + { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" }, + { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, + { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" }, + { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, + { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" }, + { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" }, + { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" }, + { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, + { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, + { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, + { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" }, + { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, + { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, + { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" }, + { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, + { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, + { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, + { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, + { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, + { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, + { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, + { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, + { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, + { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" }, + { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" }, + { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" }, + { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" }, + { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, + { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, + { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" }, + { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "disp_clk", "dss_clkdm" }, + { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" }, + { 0 }, +}; + +const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = { + { 0x44df2820, am4_l4_wkup_clkctrl_regs }, + { 0x44df8320, am4_mpu_clkctrl_regs }, + { 0x44df8420, am4_gfx_l3_clkctrl_regs }, + { 0x44df8520, am4_l4_rtc_clkctrl_regs }, + { 0x44df8820, am4_l4_per_clkctrl_regs }, + { 0 }, +}; + +const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = { + { 0x44df2820, am4_l4_wkup_clkctrl_regs }, + { 0x44df8320, am4_mpu_clkctrl_regs }, + { 0x44df8420, am4_gfx_l3_clkctrl_regs }, + { 0x44df8820, am4_l4_per_clkctrl_regs }, + { 0 }, +}; + static struct ti_dt_clk am43xx_clks[] = { - DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), - DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), - DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), - DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), - DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), - DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), - DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), - DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), - DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), - DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), - DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), - DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), - DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), - DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), - DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), - DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), - DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), - DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"), - DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"), - DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), - DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), - DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"), - DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"), - DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"), - DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"), - DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"), - DT_CLK(NULL, "dcan0_fck", "dcan0_fck"), - DT_CLK(NULL, "dcan1_fck", "dcan1_fck"), - DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"), - DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"), - DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"), - DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"), - DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), - DT_CLK(NULL, "sha0_fck", "sha0_fck"), - DT_CLK(NULL, "aes0_fck", "aes0_fck"), - DT_CLK(NULL, "rng_fck", "rng_fck"), - DT_CLK(NULL, "timer1_fck", "timer1_fck"), - DT_CLK(NULL, "timer2_fck", "timer2_fck"), - DT_CLK(NULL, "timer3_fck", "timer3_fck"), - DT_CLK(NULL, "timer4_fck", "timer4_fck"), - DT_CLK(NULL, "timer5_fck", "timer5_fck"), - DT_CLK(NULL, "timer6_fck", "timer6_fck"), - DT_CLK(NULL, "timer7_fck", "timer7_fck"), - DT_CLK(NULL, "wdt1_fck", "wdt1_fck"), - DT_CLK(NULL, "l3_gclk", "l3_gclk"), - DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"), - DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"), - DT_CLK(NULL, "l3s_gclk", "l3s_gclk"), - DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"), - DT_CLK(NULL, "clk_24mhz", "clk_24mhz"), - DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), - DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), - DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"), - DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"), - DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"), - DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), - DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), - DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), - DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), - DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), - DT_CLK(NULL, "mmc_clk", "mmc_clk"), - DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"), - DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"), DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), - DT_CLK(NULL, "sysclk_div", "sysclk_div"), - DT_CLK(NULL, "disp_clk", "disp_clk"), - DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"), - DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"), - DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"), - DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"), - DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"), - DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"), - DT_CLK(NULL, "timer8_fck", "timer8_fck"), - DT_CLK(NULL, "timer9_fck", "timer9_fck"), - DT_CLK(NULL, "timer10_fck", "timer10_fck"), - DT_CLK(NULL, "timer11_fck", "timer11_fck"), - DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"), - DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"), - DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), - DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"), - DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"), - DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"), - DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"), - DT_CLK(NULL, "func_12m_clk", "func_12m_clk"), - DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"), - DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"), - DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"), - DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"), - DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"), - DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"), - DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"), - DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"), - DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"), - DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"), - DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"), - DT_CLK("48306200.pwm", "tbclk", "ehrpwm3_tbclk"), - DT_CLK("48308200.pwm", "tbclk", "ehrpwm4_tbclk"), - DT_CLK("4830a200.pwm", "tbclk", "ehrpwm5_tbclk"), + DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"), + DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"), + DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"), + DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"), + DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"), + DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"), + DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"), + DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"), + DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"), { .node_name = NULL }, }; @@ -133,6 +232,8 @@ int __init am43xx_dt_clk_init(void) omap2_clk_disable_autoidle_all(); + ti_clk_add_aliases(); + /* * cpsw_cpts_rft_clk has got the choice of 3 clocksources * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck. diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c index 2005f032c02f..339d30d64ebb 100644 --- a/drivers/clk/ti/clk-44xx.c +++ b/drivers/clk/ti/clk-44xx.c @@ -35,7 +35,7 @@ #define OMAP4_DPLL_USB_DEFFREQ 960000000 static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = { - { OMAP4_MPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_mpu_m2_ck" }, + { OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, { 0 }, }; @@ -59,7 +59,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = { }; static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = { - "dmic_sync_mux_ck", + "abe_cm:clk:0018:26", "pad_clks_ck", "slimbus_clk", NULL, @@ -79,7 +79,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = { }; static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = { - "mcasp_sync_mux_ck", + "abe_cm:clk:0020:26", "pad_clks_ck", "slimbus_clk", NULL, @@ -92,7 +92,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = { }; static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = { - "mcbsp1_sync_mux_ck", + "abe_cm:clk:0028:26", "pad_clks_ck", "slimbus_clk", NULL, @@ -105,7 +105,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = }; static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = { - "mcbsp2_sync_mux_ck", + "abe_cm:clk:0030:26", "pad_clks_ck", "slimbus_clk", NULL, @@ -118,7 +118,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = }; static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = { - "mcbsp3_sync_mux_ck", + "abe_cm:clk:0038:26", "pad_clks_ck", "slimbus_clk", NULL, @@ -186,18 +186,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = { { OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" }, - { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "aess_fclk" }, + { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" }, { OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, - { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "func_dmic_abe_gfclk" }, - { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "func_mcasp_abe_gfclk" }, - { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "func_mcbsp1_gfclk" }, - { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "func_mcbsp2_gfclk" }, - { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "func_mcbsp3_gfclk" }, - { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "slimbus1_fclk_0" }, - { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "timer5_sync_mux" }, - { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "timer6_sync_mux" }, - { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "timer7_sync_mux" }, - { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "timer8_sync_mux" }, + { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, + { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" }, + { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, + { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, + { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, + { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" }, + { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, + { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, + { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, + { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, { OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, { 0 }, }; @@ -280,6 +280,7 @@ static const char * const omap4_fdif_fck_parents[] __initconst = { static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = { .max_div = 4, + .flags = CLK_DIVIDER_POWER_OF_TWO, }; static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = { @@ -289,7 +290,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = { static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = { { OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" }, - { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "fdif_fck" }, + { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" }, { 0 }, }; @@ -322,7 +323,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst }; static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = { - { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "dss_dss_clk" }, + { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" }, { 0 }, }; @@ -338,7 +339,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = { }; static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = { - { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "sgx_clk_mux" }, + { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" }, { 0 }, }; @@ -365,6 +366,7 @@ static const char * const omap4_hsi_fck_parents[] __initconst = { static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = { .max_div = 4, + .flags = CLK_DIVIDER_POWER_OF_TWO, }; static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = { @@ -373,12 +375,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = { }; static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = { - "utmi_p1_gfclk", + "l3_init_cm:clk:0038:24", NULL, }; static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = { - "utmi_p2_gfclk", + "l3_init_cm:clk:0038:25", NULL, }; @@ -419,7 +421,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon }; static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = { - "otg_60m_gfclk", + "l3_init_cm:clk:0040:24", NULL, }; @@ -453,14 +455,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini }; static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = { - { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "hsmmc1_fclk" }, - { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "hsmmc2_fclk" }, - { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "hsi_fck" }, + { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" }, + { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" }, + { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" }, { OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" }, { OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" }, { OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" }, { OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" }, - { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "ocp2scp_usb_phy_phy_48m" }, + { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" }, { 0 }, }; @@ -531,7 +533,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = { }; static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = { - "mcbsp4_sync_mux_ck", + "l4_per_cm:clk:00c0:26", "pad_clks_ck", NULL, }; @@ -544,7 +546,7 @@ static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = { static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = { { 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL }, - { 25, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL }, + { 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL }, { 0 }, }; @@ -571,12 +573,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst }; static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = { - { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "cm2_dm10_mux" }, - { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "cm2_dm11_mux" }, - { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "cm2_dm2_mux" }, - { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "cm2_dm3_mux" }, - { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "cm2_dm4_mux" }, - { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "cm2_dm9_mux" }, + { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" }, + { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" }, + { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" }, + { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" }, + { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" }, + { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" }, { OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" }, { OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" }, { OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" }, @@ -589,14 +591,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons { OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, { OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, { OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" }, - { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "per_mcbsp4_gfclk" }, + { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" }, { OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, { OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, { OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, { OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, { OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, { OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, - { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "slimbus2_fclk_0" }, + { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" }, { OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, { OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, { OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, @@ -619,7 +621,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon { OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" }, { OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, { OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" }, - { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "dmt1_clk_mux" }, + { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" }, { OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" }, { OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, { 0 }, @@ -633,7 +635,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = { }; static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = { - "pmd_trace_clk_mux_ck", + "emu_sys_cm:clk:0000:22", NULL, }; @@ -651,12 +653,13 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init }; static const char * const omap4_stm_clk_div_ck_parents[] __initconst = { - "pmd_stm_clock_mux_ck", + "emu_sys_cm:clk:0000:20", NULL, }; static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = { .max_div = 64, + .flags = CLK_DIVIDER_POWER_OF_TWO, }; static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = { @@ -697,52 +700,79 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = { }; static struct ti_dt_clk omap44xx_clks[] = { - DT_CLK("smp_twd", NULL, "mpu_periphclk"), - DT_CLK("omapdss_dss", "ick", "dss_fck"), - DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"), - DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"), - DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"), - DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"), - DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"), - DT_CLK("omap_i2c.1", "ick", "dummy_ck"), - DT_CLK("omap_i2c.2", "ick", "dummy_ck"), - DT_CLK("omap_i2c.3", "ick", "dummy_ck"), - DT_CLK("omap_i2c.4", "ick", "dummy_ck"), - DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), - DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), - DT_CLK(NULL, "uart1_ick", "dummy_ck"), - DT_CLK(NULL, "uart2_ick", "dummy_ck"), - DT_CLK(NULL, "uart3_ick", "dummy_ck"), - DT_CLK(NULL, "uart4_ick", "dummy_ck"), - DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), - DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), - DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"), - DT_CLK("omap_wdt", "ick", "dummy_ck"), DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), - DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"), - DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"), - DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"), - DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"), - DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"), - DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"), - DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"), - DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"), - DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"), - DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"), - DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"), - DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"), + /* + * XXX: All the clock aliases below are only needed for legacy + * hwmod support. Once hwmod is removed, these can be removed + * also. + */ + DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"), + DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"), + DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"), + DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"), + DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"), + DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"), + DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"), + DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), + DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"), + DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"), + DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"), + DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"), + DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"), + DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"), + DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"), + DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"), + DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"), + DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"), + DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"), + DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"), + DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"), + DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"), + DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"), + DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"), + DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"), + DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"), + DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"), + DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"), + DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"), + DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"), + DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), + DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), + DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), + DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"), + DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"), + DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"), + DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"), + DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"), + DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"), + DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"), + DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"), + DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"), + DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"), + DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"), + DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"), + DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"), + DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"), + DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"), + DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"), + DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"), + DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"), + DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"), + DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"), + DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"), + DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"), + DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"), + DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"), + DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"), + DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"), + DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"), + DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"), + DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"), + DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"), { .node_name = NULL }, }; diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c index 294bc03ec067..a17b0c4646a1 100644 --- a/drivers/clk/ti/clk-54xx.c +++ b/drivers/clk/ti/clk-54xx.c @@ -16,6 +16,7 @@ #include <linux/clkdev.h> #include <linux/io.h> #include <linux/clk/ti.h> +#include <dt-bindings/clock/omap5.h> #include "clock.h" @@ -27,201 +28,511 @@ */ #define OMAP5_DPLL_USB_DEFFREQ 960000000 +static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = { + { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = { + { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" }, + { 0 }, +}; + +static const char * const omap5_dmic_gfclk_parents[] __initconst = { + "abe_cm:clk:0018:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +}; + +static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = { + "abe_24m_fclk", + "dss_syc_gfclk_div", + "func_24m_clk", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL }, + { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, + { 0 }, +}; + +static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = { + "abe_cm:clk:0028:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL }, + { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, + { 0 }, +}; + +static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = { + "abe_cm:clk:0030:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL }, + { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, + { 0 }, +}; + +static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = { + "abe_cm:clk:0038:26", + "pad_clks_ck", + "slimbus_clk", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL }, + { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, + { 0 }, +}; + +static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = { + "dss_syc_gfclk_div", + "sys_32k_ck", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = { + { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" }, + { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, + { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, + { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, + { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, + { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, + { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, + { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, + { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, + { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = { + { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = { + { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = { + { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = { + { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = { + { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, + { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = { + { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" }, + { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" }, + { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = { + { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { 0 }, +}; + +static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = { + "sys_clkin", + "sys_32k_ck", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const char * const omap5_gpio2_dbclk_parents[] __initconst = { + "sys_32k_ck", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = { + { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" }, + { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" }, + { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" }, + { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" }, + { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, + { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, + { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" }, + { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { 0 }, +}; + +static const char * const omap5_dss_dss_clk_parents[] __initconst = { + "dpll_per_h12x2_ck", + NULL, +}; + +static const char * const omap5_dss_48mhz_clk_parents[] __initconst = { + "func_48m_fclk", + NULL, +}; + +static const char * const omap5_dss_sys_clk_parents[] __initconst = { + "dss_syc_gfclk_div", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL }, + { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL }, + { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL }, + { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = { + { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, + { 0 }, +}; + +static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = { + "func_128m_clk", + "dpll_per_m2x2_ck", + NULL, +}; + +static const char * const omap5_mmc1_fclk_parents[] __initconst = { + "l3init_cm:clk:0008:24", + NULL, +}; + +static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = { + .max_div = 2, +}; + +static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, + { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data }, + { 0 }, +}; + +static const char * const omap5_mmc2_fclk_parents[] __initconst = { + "l3init_cm:clk:0010:24", + NULL, +}; + +static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = { + .max_div = 2, +}; + +static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, + { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data }, + { 0 }, +}; + +static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = { + "l3init_60m_fclk", + NULL, +}; + +static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = { + "dpll_usb_m2_ck", + NULL, +}; + +static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = { + "l3init_cm:clk:0038:24", + NULL, +}; + +static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = { + "l3init_cm:clk:0038:25", + NULL, +}; + +static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = { + "l3init_60m_fclk", + "xclk60mhsp1_ck", + NULL, +}; + +static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = { + "l3init_60m_fclk", + "xclk60mhsp2_ck", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = { + { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, + { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, + { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL }, + { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL }, + { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, + { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, + { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, + { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, + { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, + { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL }, + { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, + { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, + { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, + { 0 }, +}; + +static const char * const omap5_sata_ref_clk_parents[] __initconst = { + "sys_clkin", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL }, + { 0 }, +}; + +static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = { + "dpll_usb_clkdcoldo", + NULL, +}; + +static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = { + { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, + { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, + { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" }, + { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, + { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, + { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = { + { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = { + { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = { + { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, + { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, + { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, + { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, + { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { 0 }, +}; + +const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { + { 0x4a004320, omap5_mpu_clkctrl_regs }, + { 0x4a004420, omap5_dsp_clkctrl_regs }, + { 0x4a004520, omap5_abe_clkctrl_regs }, + { 0x4a008720, omap5_l3main1_clkctrl_regs }, + { 0x4a008820, omap5_l3main2_clkctrl_regs }, + { 0x4a008920, omap5_ipu_clkctrl_regs }, + { 0x4a008a20, omap5_dma_clkctrl_regs }, + { 0x4a008b20, omap5_emif_clkctrl_regs }, + { 0x4a008d20, omap5_l4cfg_clkctrl_regs }, + { 0x4a008e20, omap5_l3instr_clkctrl_regs }, + { 0x4a009020, omap5_l4per_clkctrl_regs }, + { 0x4a009420, omap5_dss_clkctrl_regs }, + { 0x4a009620, omap5_l3init_clkctrl_regs }, + { 0x4ae07920, omap5_wkupaon_clkctrl_regs }, + { 0 }, +}; + static struct ti_dt_clk omap54xx_clks[] = { - DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), - DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), - DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), - DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), - DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), - DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), - DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), - DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), - DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), - DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), - DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), - DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), - DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), - DT_CLK(NULL, "sys_clkin", "sys_clkin"), - DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"), - DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"), - DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), - DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), - DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), - DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), - DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), - DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), - DT_CLK(NULL, "abe_clk", "abe_clk"), - DT_CLK(NULL, "abe_iclk", "abe_iclk"), - DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), - DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), - DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), - DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), - DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"), - DT_CLK(NULL, "c2c_fclk", "c2c_fclk"), - DT_CLK(NULL, "c2c_iclk", "c2c_iclk"), - DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), - DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"), - DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), - DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), - DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), - DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), - DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), - DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), - DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), - DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"), - DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), - DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"), - DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"), - DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"), - DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), - DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), - DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), - DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), - DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), - DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), - DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), - DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), - DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), - DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"), - DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"), - DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"), - DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"), - DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"), - DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"), - DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"), - DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), - DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), - DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), - DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"), - DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), - DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), - DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), - DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), - DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), - DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), - DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"), - DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), - DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), - DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), - DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), - DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), - DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), - DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), - DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"), - DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), - DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), - DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), - DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), - DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), - DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), - DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), - DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), - DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"), - DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"), - DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"), - DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"), - DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), - DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"), - DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"), - DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"), - DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"), - DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"), - DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"), - DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"), - DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"), - DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"), - DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"), - DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"), - DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"), - DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"), - DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"), - DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"), - DT_CLK(NULL, "aess_fclk", "aess_fclk"), - DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"), - DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"), - DT_CLK(NULL, "fdif_fclk", "fdif_fclk"), - DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), - DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), - DT_CLK(NULL, "hsi_fclk", "hsi_fclk"), - DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"), - DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"), - DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"), - DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"), - DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"), - DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"), - DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"), - DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"), - DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), - DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"), - DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), - DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"), - DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), - DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), - DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), - DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), - DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), - DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), - DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), - DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), - DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), - DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), - DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), - DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"), - DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"), - DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"), - DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"), - DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"), - DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"), - DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"), - DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"), - DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"), - DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"), - DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"), - DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"), - DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"), - DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"), - DT_CLK("omap_i2c.1", "ick", "dummy_ck"), - DT_CLK("omap_i2c.2", "ick", "dummy_ck"), - DT_CLK("omap_i2c.3", "ick", "dummy_ck"), - DT_CLK("omap_i2c.4", "ick", "dummy_ck"), - DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), - DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), - DT_CLK(NULL, "uart1_ick", "dummy_ck"), - DT_CLK(NULL, "uart2_ick", "dummy_ck"), - DT_CLK(NULL, "uart3_ick", "dummy_ck"), - DT_CLK(NULL, "uart4_ick", "dummy_ck"), - DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), - DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), - DT_CLK("omap_wdt", "ick", "dummy_ck"), DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"), - DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin"), - DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin"), - DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin"), - DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin"), - DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin"), - DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin"), - DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin"), - DT_CLK("40138000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), - DT_CLK("4013a000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), - DT_CLK("4013c000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), - DT_CLK("4013e000.timer", "timer_sys_ck", "dss_syc_gfclk_div"), + DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"), + DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), + DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), + DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), + DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), + DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"), + DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), + DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"), + DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"), + DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"), + DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"), + DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"), + DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"), + DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"), + DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"), + DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), + DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"), + DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), + DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"), + DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), + DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"), + DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"), + DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), + DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"), + DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), + DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), + DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"), + DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"), + DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), + DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"), + DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"), + DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"), + DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"), + DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"), + DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"), + DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"), + DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"), + DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"), + DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"), + DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"), + DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"), + DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"), + DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"), + DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"), + DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"), + DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"), + DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"), + DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"), { .node_name = NULL }, }; @@ -234,6 +545,8 @@ int __init omap5xxx_dt_clk_init(void) omap2_clk_disable_autoidle_all(); + ti_clk_add_aliases(); + abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 9fd6043314eb..fb249a1637a5 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -15,297 +15,809 @@ #include <linux/clk.h> #include <linux/clkdev.h> #include <linux/clk/ti.h> +#include <dt-bindings/clock/dra7.h> #include "clock.h" #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 #define DRA7_DPLL_USB_DEFFREQ 960000000 +static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = { + { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, + { 0 }, +}; + +static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = { + "per_abe_x1_gfclk2_div", + "video1_clk2_div", + "video2_clk2_div", + "hdmi_clk2_div", + NULL, +}; + +static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = { + "abe_24m_fclk", + "abe_sys_clk_div", + "func_24m_clk", + "atl_clkin3_ck", + "atl_clkin2_ck", + "atl_clkin1_ck", + "atl_clkin0_ck", + "sys_clkin2", + "ref_clkin0_ck", + "ref_clkin1_ck", + "ref_clkin2_ck", + "ref_clkin3_ck", + "mlb_clk", + "mlbp_clk", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = { + { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 0 }, +}; + +static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = { + "timer_sys_clk_div", + "sys_32k_ck", + "sys_clkin2", + "ref_clkin0_ck", + "ref_clkin1_ck", + "ref_clkin2_ck", + "ref_clkin3_ck", + "abe_giclk_div", + "video1_div_clk", + "video2_div_clk", + "hdmi_div_clk", + "clkoutmux0_clk_mux", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = { + "func_48m_fclk", + "dpll_per_m2x2_ck", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = { + { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" }, + { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" }, + { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" }, + { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" }, + { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" }, + { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = { + { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { + { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, + { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = { + { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = { + { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = { + { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { 0 }, +}; + +static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = { + "sys_32k_ck", + "video1_clkin_ck", + "video2_clkin_ck", + "hdmi_clkin_ck", + NULL, +}; + +static const char * const dra7_atl_gfclk_mux_parents[] __initconst = { + "l3_iclk_div", + "dpll_abe_m2_ck", + "atl_cm:clk:0000:24", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL }, + { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = { + { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = { + { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = { + { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, + { 0 }, +}; + +static const char * const dra7_dss_dss_clk_parents[] __initconst = { + "dpll_per_h12x2_ck", + NULL, +}; + +static const char * const dra7_dss_48mhz_clk_parents[] __initconst = { + "func_48m_fclk", + NULL, +}; + +static const char * const dra7_dss_hdmi_clk_parents[] __initconst = { + "hdmi_dpll_clk_mux", + NULL, +}; + +static const char * const dra7_dss_32khz_clk_parents[] __initconst = { + "sys_32k_ck", + NULL, +}; + +static const char * const dra7_dss_video1_clk_parents[] __initconst = { + "video1_dpll_clk_mux", + NULL, +}; + +static const char * const dra7_dss_video2_clk_parents[] __initconst = { + "video2_dpll_clk_mux", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL }, + { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL }, + { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL }, + { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL }, + { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = { + { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, + { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" }, + { 0 }, +}; + +static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = { + "func_128m_clk", + "dpll_per_m2x2_ck", + NULL, +}; + +static const char * const dra7_mmc1_fclk_div_parents[] __initconst = { + "l3init_cm:clk:0008:24", + NULL, +}; + +static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = { + .max_div = 4, + .flags = CLK_DIVIDER_POWER_OF_TWO, +}; + +static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, + { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data }, + { 0 }, +}; + +static const char * const dra7_mmc2_fclk_div_parents[] __initconst = { + "l3init_cm:clk:0010:24", + NULL, +}; + +static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = { + .max_div = 4, + .flags = CLK_DIVIDER_POWER_OF_TWO, +}; + +static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, + { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data }, + { 0 }, +}; + +static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = { + "l3init_960m_gfclk", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, + { 0 }, +}; + +static const char * const dra7_sata_ref_clk_parents[] __initconst = { + "sys_clkin1", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL }, + { 0 }, +}; + +static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = { + "apll_pcie_ck", + NULL, +}; + +static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = { + "optfclk_pciephy_div", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, + { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, + { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, + { 0 }, +}; + +static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = { + "dpll_gmac_h11x2_ck", + "rmii_clk_ck", + NULL, +}; + +static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = { + "video1_clkin_ck", + "video2_clkin_ck", + "dpll_abe_m2_ck", + "hdmi_clkin_ck", + "l3_iclk_div", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL }, + { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = { + { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, + { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, + { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, + { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, + { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, + { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, + { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, + { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, + { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" }, + { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, + { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, + { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, + { 0 }, +}; + +static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = { + "timer_sys_clk_div", + "sys_32k_ck", + "sys_clkin2", + "ref_clkin0_ck", + "ref_clkin1_ck", + "ref_clkin2_ck", + "ref_clkin3_ck", + "abe_giclk_div", + "video1_div_clk", + "video2_div_clk", + "hdmi_div_clk", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 0 }, +}; + +static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = { + "l4per_cm:clk:0120:24", + NULL, +}; + +static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = { + .max_div = 4, + .flags = CLK_DIVIDER_POWER_OF_TWO, +}; + +static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data }, + { 0 }, +}; + +static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = { + "l4per_cm:clk:0128:24", + NULL, +}; + +static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = { + .max_div = 4, + .flags = CLK_DIVIDER_POWER_OF_TWO, +}; + +static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = { + "func_128m_clk", + "dpll_per_h13x2_ck", + NULL, +}; + +static const char * const dra7_qspi_gfclk_div_parents[] __initconst = { + "l4per_cm:clk:0138:24", + NULL, +}; + +static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = { + .max_div = 4, + .flags = CLK_DIVIDER_POWER_OF_TWO, +}; + +static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL }, + { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = { + { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = { + { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = { + { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = { + { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = { + { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = { + { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = { + { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, + { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = { + { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" }, + { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" }, + { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, + { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, + { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" }, + { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" }, + { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" }, + { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" }, + { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" }, + { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, + { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, + { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, + { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" }, + { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, + { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" }, + { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" }, + { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" }, + { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, + { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, + { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" }, + { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" }, + { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" }, + { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" }, + { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" }, + { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" }, + { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" }, + { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" }, + { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" }, + { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" }, + { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" }, + { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" }, + { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" }, + { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" }, + { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, + { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, + { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, + { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, + { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, + { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" }, + { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" }, + { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" }, + { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" }, + { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" }, + { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = { + { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, + { 0 }, +}; + +static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = { + "sys_clkin1", + "sys_clkin2", + NULL, +}; + +static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = { + { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = { + { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, + { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, + { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, + { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, + { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" }, + { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, + { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" }, + { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" }, + { 0 }, +}; + +const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { + { 0x4a005320, dra7_mpu_clkctrl_regs }, + { 0x4a005540, dra7_ipu_clkctrl_regs }, + { 0x4a005740, dra7_rtc_clkctrl_regs }, + { 0x4a008620, dra7_coreaon_clkctrl_regs }, + { 0x4a008720, dra7_l3main1_clkctrl_regs }, + { 0x4a008a20, dra7_dma_clkctrl_regs }, + { 0x4a008b20, dra7_emif_clkctrl_regs }, + { 0x4a008c00, dra7_atl_clkctrl_regs }, + { 0x4a008d20, dra7_l4cfg_clkctrl_regs }, + { 0x4a008e20, dra7_l3instr_clkctrl_regs }, + { 0x4a009120, dra7_dss_clkctrl_regs }, + { 0x4a009320, dra7_l3init_clkctrl_regs }, + { 0x4a009700, dra7_l4per_clkctrl_regs }, + { 0x4ae07820, dra7_wkupaon_clkctrl_regs }, + { 0 }, +}; + static struct ti_dt_clk dra7xx_clks[] = { - DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"), - DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"), - DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"), - DT_CLK(NULL, "atl_clkin3_ck", "atl_clkin3_ck"), - DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"), - DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"), - DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"), - DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"), - DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"), - DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"), - DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"), - DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"), - DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"), - DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"), - DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), - DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), - DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), - DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), - DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), - DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), - DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"), - DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), - DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), - DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), - DT_CLK(NULL, "sys_clkin1", "sys_clkin1"), - DT_CLK(NULL, "sys_clkin2", "sys_clkin2"), - DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"), - DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"), - DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"), - DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"), - DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"), - DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"), - DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), - DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), - DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), - DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), - DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), - DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), - DT_CLK(NULL, "abe_clk", "abe_clk"), - DT_CLK(NULL, "aess_fclk", "aess_fclk"), - DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"), - DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), - DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"), - DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"), - DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"), - DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"), - DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"), - DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"), - DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"), - DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"), - DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"), - DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"), - DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"), - DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"), - DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), - DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), - DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), - DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), - DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), - DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), - DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"), - DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"), - DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"), - DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"), - DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), - DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"), - DT_CLK(NULL, "iva_dclk", "iva_dclk"), - DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"), - DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"), - DT_CLK(NULL, "gpu_dclk", "gpu_dclk"), - DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), - DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"), - DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), - DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), - DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"), - DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"), - DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"), - DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"), - DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"), - DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"), - DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"), - DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), - DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), - DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"), - DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), - DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), - DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"), - DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"), - DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"), - DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"), - DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"), - DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"), - DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"), - DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"), - DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"), - DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"), - DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"), - DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"), - DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"), - DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"), - DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"), - DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), - DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), - DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), - DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), - DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), - DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), - DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), - DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"), - DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"), - DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"), - DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"), - DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"), - DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"), - DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"), - DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"), - DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), - DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), - DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), - DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"), - DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), - DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), - DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), - DT_CLK(NULL, "eve_clk", "eve_clk"), - DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), - DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), - DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), - DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), - DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), - DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"), - DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"), - DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"), - DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"), - DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), - DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), - DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), - DT_CLK(NULL, "mlb_clk", "mlb_clk"), - DT_CLK(NULL, "mlbp_clk", "mlbp_clk"), - DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"), - DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"), - DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"), - DT_CLK(NULL, "video1_div_clk", "video1_div_clk"), - DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"), - DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"), - DT_CLK(NULL, "video2_div_clk", "video2_div_clk"), - DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"), - DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), - DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), - DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), - DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), - DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"), - DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"), - DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"), - DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), - DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), - DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), - DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), - DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), - DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), - DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), - DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), - DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"), - DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"), - DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"), - DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"), - DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), - DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"), - DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"), - DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"), - DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"), - DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"), - DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"), - DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"), - DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"), - DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"), - DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), - DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), - DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"), - DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), - DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"), - DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"), - DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"), - DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"), - DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"), - DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"), - DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"), - DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"), - DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"), - DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"), - DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"), - DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"), - DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"), - DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"), - DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"), - DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"), - DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"), - DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"), - DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), - DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"), - DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), - DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"), - DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"), - DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"), - DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"), - DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"), - DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"), - DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"), - DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), - DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), - DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"), - DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"), - DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"), - DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"), - DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), - DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), - DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), - DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), - DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), - DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), - DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), - DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), - DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), - DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"), - DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"), - DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"), - DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"), - DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"), - DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"), - DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"), - DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"), - DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"), - DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"), - DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"), - DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"), - DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"), - DT_CLK("omap_i2c.1", "ick", "dummy_ck"), - DT_CLK("omap_i2c.2", "ick", "dummy_ck"), - DT_CLK("omap_i2c.3", "ick", "dummy_ck"), - DT_CLK("omap_i2c.4", "ick", "dummy_ck"), - DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), - DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), - DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), - DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), - DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), - DT_CLK(NULL, "uart1_ick", "dummy_ck"), - DT_CLK(NULL, "uart2_ick", "dummy_ck"), - DT_CLK(NULL, "uart3_ick", "dummy_ck"), - DT_CLK(NULL, "uart4_ick", "dummy_ck"), - DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), - DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), - DT_CLK("omap_wdt", "ick", "dummy_ck"), DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), - DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("48828000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("4882a000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"), - DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"), DT_CLK(NULL, "sys_clkin", "sys_clkin1"), - DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"), + DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"), + DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"), + DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"), + DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), + DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), + DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), + DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"), + DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"), + DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"), + DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"), + DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), + DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"), + DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"), + DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"), + DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"), + DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"), + DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"), + DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"), + DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"), + DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"), + DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"), + DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"), + DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"), + DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"), + DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"), + DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"), + DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"), + DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"), + DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"), + DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"), + DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"), + DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"), + DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"), + DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"), + DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"), + DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"), + DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"), + DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"), + DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), + DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"), + DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"), + DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), + DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"), + DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"), + DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"), + DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"), + DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"), + DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"), + DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"), + DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"), + DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"), + DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"), + DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"), + DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"), + DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"), + DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"), + DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"), + DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), + DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"), + DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"), + DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"), + DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"), + DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"), + DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"), + DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), + DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"), + DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"), + DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"), + DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"), + DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"), + DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"), + DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"), + DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"), + DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"), + DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"), + DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"), + DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"), + DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"), + DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"), + DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"), + DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"), + DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"), + DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"), + DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"), + DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"), { .node_name = NULL }, }; @@ -318,6 +830,8 @@ int __init dra7xx_dt_clk_init(void) omap2_clk_disable_autoidle_all(); + ti_clk_add_aliases(); + dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); if (rc) diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c index 52c6efc53731..f688fdd2cb59 100644 --- a/drivers/clk/ti/clk-814x.c +++ b/drivers/clk/ti/clk-814x.c @@ -9,23 +9,48 @@ #include <linux/clk-provider.h> #include <linux/clk/ti.h> #include <linux/of_platform.h> +#include <dt-bindings/clock/dm814.h> #include "clock.h" +static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = { + { DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = { + { DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, + { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" }, + { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" }, + { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, + { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" }, + { DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" }, + { DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" }, + { 0 }, +}; + +const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = { + { 0x48180500, dm814_default_clkctrl_regs }, + { 0x48181400, dm814_alwon_clkctrl_regs }, + { 0 }, +}; + static struct ti_dt_clk dm814_clks[] = { - DT_CLK(NULL, "devosc_ck", "devosc_ck"), - DT_CLK(NULL, "mpu_ck", "mpu_ck"), - DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"), - DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"), - DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"), - DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"), - DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"), - DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"), DT_CLK(NULL, "timer_sys_ck", "devosc_ck"), - DT_CLK(NULL, "timer1_fck", "timer1_fck"), - DT_CLK(NULL, "timer2_fck", "timer2_fck"), - DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"), - DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"), { .node_name = NULL }, }; @@ -83,6 +108,7 @@ int __init dm814x_dt_clk_init(void) { ti_dt_clocks_register(dm814_clks); omap2_clk_disable_autoidle_all(); + ti_clk_add_aliases(); omap2_clk_enable_init_clocks(NULL, 0); timer_clocks_initialized = true; diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c index 2a5d84fdddc5..7d215cdf9dda 100644 --- a/drivers/clk/ti/clk-816x.c +++ b/drivers/clk/ti/clk-816x.c @@ -13,30 +13,59 @@ #include <linux/list.h> #include <linux/clk-provider.h> #include <linux/clk/ti.h> +#include <dt-bindings/clock/dm816.h> #include "clock.h" +static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = { + { DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = { + { DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" }, + { DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, + { DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, + { DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, + { DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, + { DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, + { DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, + { DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, + { DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" }, + { DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" }, + { DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" }, + { DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, + { DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { 0 }, +}; + +const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = { + { 0x48180500, dm816_default_clkctrl_regs }, + { 0x48181400, dm816_alwon_clkctrl_regs }, + { 0 }, +}; + static struct ti_dt_clk dm816x_clks[] = { DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), - DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"), DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"), - DT_CLK(NULL, "mpu_ck", "mpu_ck"), - DT_CLK(NULL, "timer1_fck", "timer1_fck"), - DT_CLK(NULL, "timer2_fck", "timer2_fck"), - DT_CLK(NULL, "timer3_fck", "timer3_fck"), - DT_CLK(NULL, "timer4_fck", "timer4_fck"), - DT_CLK(NULL, "timer5_fck", "timer5_fck"), - DT_CLK(NULL, "timer6_fck", "timer6_fck"), - DT_CLK(NULL, "timer7_fck", "timer7_fck"), - DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"), - DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"), - DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"), - DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"), - DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"), - DT_CLK(NULL, "sysclk24_ck", "sysclk24_ck"), - DT_CLK("4a100000.ethernet", "sysclk24_ck", "sysclk24_ck"), { .node_name = NULL }, }; @@ -50,6 +79,7 @@ int __init dm816x_dt_clk_init(void) { ti_dt_clocks_register(dm816x_clks); omap2_clk_disable_autoidle_all(); + ti_clk_add_aliases(); omap2_clk_enable_init_clocks(enable_init_clks, ARRAY_SIZE(enable_init_clks)); diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 38dbcc1b7e2c..afa0d6bfc5c1 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -335,6 +335,9 @@ _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider, } mux->mask = num_parents; + if (!(mux->flags & CLK_MUX_INDEX_ONE)) + mux->mask--; + mux->mask = (1 << fls(mux->mask)) - 1; mux->shift = data->bit; @@ -354,6 +357,7 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider, { struct clk_omap_divider *div; const struct omap_clkctrl_div_data *div_data = data->data; + u8 div_flags = 0; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) @@ -361,9 +365,13 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider, div->reg.ptr = reg; div->shift = data->bit; + div->flags = div_data->flags; + + if (div->flags & CLK_DIVIDER_POWER_OF_TWO) + div_flags |= CLKF_INDEX_POWER_OF_TWO; - if (ti_clk_parse_divider_data((int *)div_data->dividers, - div_data->max_div, 0, 0, + if (ti_clk_parse_divider_data((int *)div_data->dividers, 0, + div_data->max_div, div_flags, &div->width, &div->table)) { pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__, node, offset, data->bit); @@ -414,6 +422,12 @@ _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider, } } +static void __init _clkctrl_add_provider(void *data, + struct device_node *np) +{ + of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data); +} + static void __init _ti_omap4_clkctrl_setup(struct device_node *node) { struct omap_clkctrl_provider *provider; @@ -425,6 +439,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) struct omap_clkctrl_clk *clkctrl_clk; const __be32 *addrp; u32 addr; + int ret; addrp = of_get_address(node, 0, NULL, NULL); addr = (u32)of_translate_address(node, addrp); @@ -433,6 +448,31 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) if (of_machine_is_compatible("ti,omap4")) data = omap4_clkctrl_data; #endif +#ifdef CONFIG_SOC_OMAP5 + if (of_machine_is_compatible("ti,omap5")) + data = omap5_clkctrl_data; +#endif +#ifdef CONFIG_SOC_DRA7XX + if (of_machine_is_compatible("ti,dra7")) + data = dra7_clkctrl_data; +#endif +#ifdef CONFIG_SOC_AM33XX + if (of_machine_is_compatible("ti,am33xx")) + data = am3_clkctrl_data; +#endif +#ifdef CONFIG_SOC_AM43XX + if (of_machine_is_compatible("ti,am4372")) + data = am4_clkctrl_data; + if (of_machine_is_compatible("ti,am438x")) + data = am438x_clkctrl_data; +#endif +#ifdef CONFIG_SOC_TI81XX + if (of_machine_is_compatible("ti,dm814")) + data = dm814_clkctrl_data; + + if (of_machine_is_compatible("ti,dm816")) + data = dm816_clkctrl_data; +#endif while (data->addr) { if (addr == data->addr) @@ -519,7 +559,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) reg_data++; } - of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider); + ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider); + if (ret == -EPROBE_DEFER) + ti_clk_retry_init(node, provider, _clkctrl_add_provider); + return; cleanup: diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 1654da96ad65..d9b43bfc2532 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -151,6 +151,7 @@ struct ti_dt_clk { struct omap_clkctrl_div_data { const int *dividers; int max_div; + u32 flags; }; struct omap_clkctrl_bit_data { @@ -174,6 +175,13 @@ struct omap_clkctrl_data { }; extern const struct omap_clkctrl_data omap4_clkctrl_data[]; +extern const struct omap_clkctrl_data omap5_clkctrl_data[]; +extern const struct omap_clkctrl_data dra7_clkctrl_data[]; +extern const struct omap_clkctrl_data am3_clkctrl_data[]; +extern const struct omap_clkctrl_data am4_clkctrl_data[]; +extern const struct omap_clkctrl_data am438x_clkctrl_data[]; +extern const struct omap_clkctrl_data dm814_clkctrl_data[]; +extern const struct omap_clkctrl_data dm816_clkctrl_data[]; #define CLKF_SW_SUP BIT(0) #define CLKF_HW_SUP BIT(1) |