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-rw-r--r--drivers/clocksource/Kconfig2
-rw-r--r--drivers/clocksource/Makefile2
-rw-r--r--drivers/clocksource/clksrc-of.c3
-rw-r--r--drivers/clocksource/sun4i_timer.c (renamed from drivers/clocksource/sunxi_timer.c)94
-rw-r--r--drivers/clocksource/vt8500_timer.c2
5 files changed, 46 insertions, 57 deletions
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e507ab7df60b..9002185a0a1a 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -25,7 +25,7 @@ config DW_APB_TIMER_OF
config ARMADA_370_XP_TIMER
bool
-config SUNXI_TIMER
+config SUN4I_TIMER
bool
config VT8500_TIMER
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 89c5adc498b3..98f220a7a92c 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
-obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
+obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
diff --git a/drivers/clocksource/clksrc-of.c b/drivers/clocksource/clksrc-of.c
index 3ef11fba781c..37f5325bec95 100644
--- a/drivers/clocksource/clksrc-of.c
+++ b/drivers/clocksource/clksrc-of.c
@@ -16,6 +16,7 @@
#include <linux/init.h>
#include <linux/of.h>
+#include <linux/clocksource.h>
extern struct of_device_id __clksrc_of_table[];
@@ -26,7 +27,7 @@ void __init clocksource_of_init(void)
{
struct device_node *np;
const struct of_device_id *match;
- void (*init_func)(struct device_node *);
+ clocksource_of_init_fn init_func;
for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
init_func = match->data;
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sun4i_timer.c
index 0ce85e29769b..d4674e78ef35 100644
--- a/drivers/clocksource/sunxi_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -22,66 +22,64 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <linux/sunxi_timer.h>
-#include <linux/clk/sunxi.h>
-#define TIMER_CTL_REG 0x00
-#define TIMER_CTL_ENABLE (1 << 0)
+#define TIMER_IRQ_EN_REG 0x00
+#define TIMER_IRQ_EN(val) (1 << val)
#define TIMER_IRQ_ST_REG 0x04
-#define TIMER0_CTL_REG 0x10
-#define TIMER0_CTL_ENABLE (1 << 0)
-#define TIMER0_CTL_AUTORELOAD (1 << 1)
-#define TIMER0_CTL_ONESHOT (1 << 7)
-#define TIMER0_INTVAL_REG 0x14
-#define TIMER0_CNTVAL_REG 0x18
+#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
+#define TIMER_CTL_ENABLE (1 << 0)
+#define TIMER_CTL_AUTORELOAD (1 << 1)
+#define TIMER_CTL_ONESHOT (1 << 7)
+#define TIMER_INTVAL_REG(val) (0x10 * val + 0x14)
+#define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18)
#define TIMER_SCAL 16
static void __iomem *timer_base;
-static void sunxi_clkevt_mode(enum clock_event_mode mode,
+static void sun4i_clkevt_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
- u32 u = readl(timer_base + TIMER0_CTL_REG);
+ u32 u = readl(timer_base + TIMER_CTL_REG(0));
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
- u &= ~(TIMER0_CTL_ONESHOT);
- writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
+ u &= ~(TIMER_CTL_ONESHOT);
+ writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
break;
case CLOCK_EVT_MODE_ONESHOT:
- writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
+ writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
- writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
+ writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
break;
}
}
-static int sunxi_clkevt_next_event(unsigned long evt,
+static int sun4i_clkevt_next_event(unsigned long evt,
struct clock_event_device *unused)
{
- u32 u = readl(timer_base + TIMER0_CTL_REG);
- writel(evt, timer_base + TIMER0_CNTVAL_REG);
- writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
- timer_base + TIMER0_CTL_REG);
+ u32 u = readl(timer_base + TIMER_CTL_REG(0));
+ writel(evt, timer_base + TIMER_CNTVAL_REG(0));
+ writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
+ timer_base + TIMER_CTL_REG(0));
return 0;
}
-static struct clock_event_device sunxi_clockevent = {
- .name = "sunxi_tick",
+static struct clock_event_device sun4i_clockevent = {
+ .name = "sun4i_tick",
.rating = 300,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_mode = sunxi_clkevt_mode,
- .set_next_event = sunxi_clkevt_next_event,
+ .set_mode = sun4i_clkevt_mode,
+ .set_next_event = sun4i_clkevt_next_event,
};
-static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = (struct clock_event_device *)dev_id;
@@ -91,30 +89,20 @@ static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static struct irqaction sunxi_timer_irq = {
- .name = "sunxi_timer0",
+static struct irqaction sun4i_timer_irq = {
+ .name = "sun4i_timer0",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = sunxi_timer_interrupt,
- .dev_id = &sunxi_clockevent,
-};
-
-static struct of_device_id sunxi_timer_dt_ids[] = {
- { .compatible = "allwinner,sunxi-timer" },
- { }
+ .handler = sun4i_timer_interrupt,
+ .dev_id = &sun4i_clockevent,
};
-void __init sunxi_timer_init(void)
+static void __init sun4i_timer_init(struct device_node *node)
{
- struct device_node *node;
unsigned long rate = 0;
struct clk *clk;
int ret, irq;
u32 val;
- node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
- if (!node)
- panic("No sunxi timer node");
-
timer_base = of_iomap(node, 0);
if (!timer_base)
panic("Can't map registers");
@@ -123,8 +111,6 @@ void __init sunxi_timer_init(void)
if (irq <= 0)
panic("Can't parse IRQ");
- sunxi_init_clocks();
-
clk = of_clk_get(node, 0);
if (IS_ERR(clk))
panic("Can't get timer clock");
@@ -132,29 +118,31 @@ void __init sunxi_timer_init(void)
rate = clk_get_rate(clk);
writel(rate / (TIMER_SCAL * HZ),
- timer_base + TIMER0_INTVAL_REG);
+ timer_base + TIMER_INTVAL_REG(0));
/* set clock source to HOSC, 16 pre-division */
- val = readl(timer_base + TIMER0_CTL_REG);
+ val = readl(timer_base + TIMER_CTL_REG(0));
val &= ~(0x07 << 4);
val &= ~(0x03 << 2);
val |= (4 << 4) | (1 << 2);
- writel(val, timer_base + TIMER0_CTL_REG);
+ writel(val, timer_base + TIMER_CTL_REG(0));
/* set mode to auto reload */
- val = readl(timer_base + TIMER0_CTL_REG);
- writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
+ val = readl(timer_base + TIMER_CTL_REG(0));
+ writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
- ret = setup_irq(irq, &sunxi_timer_irq);
+ ret = setup_irq(irq, &sun4i_timer_irq);
if (ret)
pr_warn("failed to setup irq %d\n", irq);
/* Enable timer0 interrupt */
- val = readl(timer_base + TIMER_CTL_REG);
- writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
+ val = readl(timer_base + TIMER_IRQ_EN_REG);
+ writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
- sunxi_clockevent.cpumask = cpumask_of(0);
+ sun4i_clockevent.cpumask = cpumask_of(0);
- clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL,
+ clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
0x1, 0xff);
}
+CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
+ sun4i_timer_init);
diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c
index 242255285597..64f553f04fa4 100644
--- a/drivers/clocksource/vt8500_timer.c
+++ b/drivers/clocksource/vt8500_timer.c
@@ -165,4 +165,4 @@ static void __init vt8500_timer_init(struct device_node *np)
4, 0xf0000000);
}
-CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init)
+CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init);