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-rw-r--r--drivers/gpio/Kconfig15
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/gpio/gpio-adp5588.c234
-rw-r--r--drivers/gpio/gpio-altera.c4
-rw-r--r--drivers/gpio/gpio-eic-sprd.c1
-rw-r--r--drivers/gpio/gpio-f7188x.c24
-rw-r--r--drivers/gpio/gpio-gw-pld.c137
-rw-r--r--drivers/gpio/gpio-hlwd.c192
-rw-r--r--drivers/gpio/gpio-mvebu.c11
-rw-r--r--drivers/gpio/gpio-pca953x.c103
-rw-r--r--drivers/gpio/gpio-pmic-eic-sprd.c1
-rw-r--r--drivers/gpio/gpio-rcar.c12
-rw-r--r--drivers/gpio/gpio-sama5d2-piobu.c20
-rw-r--r--drivers/gpio/gpio-tqmx86.c331
-rw-r--r--drivers/gpio/gpio-zynq.c24
-rw-r--r--drivers/gpio/gpiolib-acpi.c7
-rw-r--r--drivers/gpio/gpiolib.c37
17 files changed, 948 insertions, 207 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b5a2845347ec..486d9de2716a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -258,6 +258,7 @@ config GPIO_HLWD
tristate "Nintendo Wii (Hollywood) GPIO"
depends on OF_GPIO
select GPIO_GENERIC
+ select GPIOLIB_IRQCHIP
help
Select this to support the GPIO controller of the Nintendo Wii.
@@ -830,6 +831,13 @@ config GPIO_ADNP
enough to represent all pins, but the driver will assume a
register layout for 64 pins (8 registers).
+config GPIO_GW_PLD
+ tristate "Gateworks PLD GPIO Expander"
+ depends on OF_GPIO
+ help
+ Say yes here to provide access to the Gateworks I2C PLD GPIO
+ Expander. This is used at least on the Cambria GW2358-4.
+
config GPIO_MAX7300
tristate "Maxim MAX7300 GPIO expander"
select GPIO_MAX730X
@@ -1190,6 +1198,13 @@ config GPIO_TPS68470
of the TPS68470 must be available before dependent
drivers are loaded.
+config GPIO_TQMX86
+ tristate "TQ-Systems QTMX86 GPIO"
+ depends on MFD_TQMX86 || COMPILE_TEST
+ select GPIOLIB_IRQCHIP
+ help
+ This driver supports GPIO on the TQMX86 IO controller.
+
config GPIO_TWL4030
tristate "TWL4030, TWL5030, and TPS659x0 GPIOs"
depends on TWL4030_CORE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 37628f8dbf70..9655927a3dcf 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_GPIO_FTGPIO010) += gpio-ftgpio010.o
obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o
obj-$(CONFIG_GPIO_GPIO_MM) += gpio-gpio-mm.o
obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o
+obj-$(CONFIG_GPIO_GW_PLD) += gpio-gw-pld.o
obj-$(CONFIG_GPIO_HLWD) += gpio-hlwd.o
obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o
obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
@@ -135,6 +136,7 @@ obj-$(CONFIG_GPIO_TPS6586X) += gpio-tps6586x.o
obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o
obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o
obj-$(CONFIG_GPIO_TPS68470) += gpio-tps68470.o
+obj-$(CONFIG_GPIO_TQMX86) += gpio-tqmx86.o
obj-$(CONFIG_GPIO_TS4800) += gpio-ts4800.o
obj-$(CONFIG_GPIO_TS4900) += gpio-ts4900.o
obj-$(CONFIG_GPIO_TS5500) += gpio-ts5500.o
diff --git a/drivers/gpio/gpio-adp5588.c b/drivers/gpio/gpio-adp5588.c
index cc33d8986ad3..c4a5b499f53e 100644
--- a/drivers/gpio/gpio-adp5588.c
+++ b/drivers/gpio/gpio-adp5588.c
@@ -15,6 +15,7 @@
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/of_device.h>
#include <linux/platform_data/adp5588.h>
@@ -33,16 +34,13 @@ struct adp5588_gpio {
struct mutex lock; /* protect cached dir, dat_out */
/* protect serialized access to the interrupt controller bus */
struct mutex irq_lock;
- unsigned gpio_start;
- unsigned irq_base;
uint8_t dat_out[3];
uint8_t dir[3];
- uint8_t int_lvl[3];
+ uint8_t int_lvl_low[3];
+ uint8_t int_lvl_high[3];
uint8_t int_en[3];
uint8_t irq_mask[3];
- uint8_t irq_stat[3];
uint8_t int_input_en[3];
- uint8_t int_lvl_cached[3];
};
static int adp5588_gpio_read(struct i2c_client *client, u8 reg)
@@ -148,16 +146,11 @@ static int adp5588_gpio_direction_output(struct gpio_chip *chip,
}
#ifdef CONFIG_GPIO_ADP5588_IRQ
-static int adp5588_gpio_to_irq(struct gpio_chip *chip, unsigned off)
-{
- struct adp5588_gpio *dev = gpiochip_get_data(chip);
-
- return dev->irq_base + off;
-}
static void adp5588_irq_bus_lock(struct irq_data *d)
{
- struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct adp5588_gpio *dev = gpiochip_get_data(gc);
mutex_lock(&dev->irq_lock);
}
@@ -172,7 +165,8 @@ static void adp5588_irq_bus_lock(struct irq_data *d)
static void adp5588_irq_bus_sync_unlock(struct irq_data *d)
{
- struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct adp5588_gpio *dev = gpiochip_get_data(gc);
int i;
for (i = 0; i <= ADP5588_BANK(ADP5588_MAXGPIO); i++) {
@@ -185,15 +179,9 @@ static void adp5588_irq_bus_sync_unlock(struct irq_data *d)
mutex_unlock(&dev->lock);
}
- if (dev->int_lvl_cached[i] != dev->int_lvl[i]) {
- dev->int_lvl_cached[i] = dev->int_lvl[i];
- adp5588_gpio_write(dev->client, GPIO_INT_LVL1 + i,
- dev->int_lvl[i]);
- }
-
if (dev->int_en[i] ^ dev->irq_mask[i]) {
dev->int_en[i] = dev->irq_mask[i];
- adp5588_gpio_write(dev->client, GPIO_INT_EN1 + i,
+ adp5588_gpio_write(dev->client, GPI_EM1 + i,
dev->int_en[i]);
}
}
@@ -203,41 +191,38 @@ static void adp5588_irq_bus_sync_unlock(struct irq_data *d)
static void adp5588_irq_mask(struct irq_data *d)
{
- struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
- unsigned gpio = d->irq - dev->irq_base;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct adp5588_gpio *dev = gpiochip_get_data(gc);
- dev->irq_mask[ADP5588_BANK(gpio)] &= ~ADP5588_BIT(gpio);
+ dev->irq_mask[ADP5588_BANK(d->hwirq)] &= ~ADP5588_BIT(d->hwirq);
}
static void adp5588_irq_unmask(struct irq_data *d)
{
- struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
- unsigned gpio = d->irq - dev->irq_base;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct adp5588_gpio *dev = gpiochip_get_data(gc);
- dev->irq_mask[ADP5588_BANK(gpio)] |= ADP5588_BIT(gpio);
+ dev->irq_mask[ADP5588_BANK(d->hwirq)] |= ADP5588_BIT(d->hwirq);
}
static int adp5588_irq_set_type(struct irq_data *d, unsigned int type)
{
- struct adp5588_gpio *dev = irq_data_get_irq_chip_data(d);
- uint16_t gpio = d->irq - dev->irq_base;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct adp5588_gpio *dev = gpiochip_get_data(gc);
+ uint16_t gpio = d->hwirq;
unsigned bank, bit;
- if ((type & IRQ_TYPE_EDGE_BOTH)) {
- dev_err(&dev->client->dev, "irq %d: unsupported type %d\n",
- d->irq, type);
- return -EINVAL;
- }
-
bank = ADP5588_BANK(gpio);
bit = ADP5588_BIT(gpio);
- if (type & IRQ_TYPE_LEVEL_HIGH)
- dev->int_lvl[bank] |= bit;
- else if (type & IRQ_TYPE_LEVEL_LOW)
- dev->int_lvl[bank] &= ~bit;
- else
- return -EINVAL;
+ dev->int_lvl_low[bank] &= ~bit;
+ dev->int_lvl_high[bank] &= ~bit;
+
+ if (type & IRQ_TYPE_EDGE_BOTH || type & IRQ_TYPE_LEVEL_HIGH)
+ dev->int_lvl_high[bank] |= bit;
+
+ if (type & IRQ_TYPE_EDGE_BOTH || type & IRQ_TYPE_LEVEL_LOW)
+ dev->int_lvl_low[bank] |= bit;
dev->int_input_en[bank] |= bit;
@@ -253,40 +238,32 @@ static struct irq_chip adp5588_irq_chip = {
.irq_set_type = adp5588_irq_set_type,
};
-static int adp5588_gpio_read_intstat(struct i2c_client *client, u8 *buf)
-{
- int ret = i2c_smbus_read_i2c_block_data(client, GPIO_INT_STAT1, 3, buf);
-
- if (ret < 0)
- dev_err(&client->dev, "Read INT_STAT Error\n");
-
- return ret;
-}
-
static irqreturn_t adp5588_irq_handler(int irq, void *devid)
{
struct adp5588_gpio *dev = devid;
- unsigned status, bank, bit, pending;
- int ret;
- status = adp5588_gpio_read(dev->client, INT_STAT);
-
- if (status & ADP5588_GPI_INT) {
- ret = adp5588_gpio_read_intstat(dev->client, dev->irq_stat);
- if (ret < 0)
- memset(dev->irq_stat, 0, ARRAY_SIZE(dev->irq_stat));
-
- for (bank = 0, bit = 0; bank <= ADP5588_BANK(ADP5588_MAXGPIO);
- bank++, bit = 0) {
- pending = dev->irq_stat[bank] & dev->irq_mask[bank];
-
- while (pending) {
- if (pending & (1 << bit)) {
- handle_nested_irq(dev->irq_base +
- (bank << 3) + bit);
- pending &= ~(1 << bit);
-
- }
- bit++;
+ int status = adp5588_gpio_read(dev->client, INT_STAT);
+
+ if (status & ADP5588_KE_INT) {
+ int ev_cnt = adp5588_gpio_read(dev->client, KEY_LCK_EC_STAT);
+
+ if (ev_cnt > 0) {
+ int i;
+
+ for (i = 0; i < (ev_cnt & ADP5588_KEC); i++) {
+ int key = adp5588_gpio_read(dev->client,
+ Key_EVENTA + i);
+ /* GPIN events begin at 97,
+ * bit 7 indicates logic level
+ */
+ int gpio = (key & 0x7f) - 97;
+ int lvl = key & (1 << 7);
+ int bank = ADP5588_BANK(gpio);
+ int bit = ADP5588_BIT(gpio);
+
+ if ((lvl && dev->int_lvl_high[bank] & bit) ||
+ (!lvl && dev->int_lvl_low[bank] & bit))
+ handle_nested_irq(irq_find_mapping(
+ dev->gpio_chip.irq.domain, gpio));
}
}
}
@@ -299,53 +276,42 @@ static irqreturn_t adp5588_irq_handler(int irq, void *devid)
static int adp5588_irq_setup(struct adp5588_gpio *dev)
{
struct i2c_client *client = dev->client;
+ int ret;
struct adp5588_gpio_platform_data *pdata =
dev_get_platdata(&client->dev);
- unsigned gpio;
- int ret;
+ int irq_base = pdata ? pdata->irq_base : 0;
adp5588_gpio_write(client, CFG, ADP5588_AUTO_INC);
adp5588_gpio_write(client, INT_STAT, -1); /* status is W1C */
- adp5588_gpio_read_intstat(client, dev->irq_stat); /* read to clear */
- dev->irq_base = pdata->irq_base;
mutex_init(&dev->irq_lock);
- for (gpio = 0; gpio < dev->gpio_chip.ngpio; gpio++) {
- int irq = gpio + dev->irq_base;
- irq_set_chip_data(irq, dev);
- irq_set_chip_and_handler(irq, &adp5588_irq_chip,
- handle_level_irq);
- irq_set_nested_thread(irq, 1);
- irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE);
- }
-
- ret = request_threaded_irq(client->irq,
- NULL,
- adp5588_irq_handler,
- IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
- dev_name(&client->dev), dev);
+ ret = devm_request_threaded_irq(&client->dev, client->irq,
+ NULL, adp5588_irq_handler, IRQF_ONESHOT
+ | IRQF_TRIGGER_FALLING | IRQF_SHARED,
+ dev_name(&client->dev), dev);
if (ret) {
dev_err(&client->dev, "failed to request irq %d\n",
client->irq);
- goto out;
+ return ret;
}
+ ret = gpiochip_irqchip_add_nested(&dev->gpio_chip,
+ &adp5588_irq_chip, irq_base,
+ handle_simple_irq,
+ IRQ_TYPE_NONE);
+ if (ret) {
+ dev_err(&client->dev,
+ "could not connect irqchip to gpiochip\n");
+ return ret;
+ }
+ gpiochip_set_nested_irqchip(&dev->gpio_chip,
+ &adp5588_irq_chip,
+ client->irq);
- dev->gpio_chip.to_irq = adp5588_gpio_to_irq;
adp5588_gpio_write(client, CFG,
- ADP5588_AUTO_INC | ADP5588_INT_CFG | ADP5588_GPI_INT);
+ ADP5588_AUTO_INC | ADP5588_INT_CFG | ADP5588_KE_IEN);
return 0;
-
-out:
- dev->irq_base = 0;
- return ret;
-}
-
-static void adp5588_irq_teardown(struct adp5588_gpio *dev)
-{
- if (dev->irq_base)
- free_irq(dev->client->irq, dev);
}
#else
@@ -357,24 +323,16 @@ static int adp5588_irq_setup(struct adp5588_gpio *dev)
return 0;
}
-static void adp5588_irq_teardown(struct adp5588_gpio *dev)
-{
-}
#endif /* CONFIG_GPIO_ADP5588_IRQ */
-static int adp5588_gpio_probe(struct i2c_client *client,
- const struct i2c_device_id *id)
+static int adp5588_gpio_probe(struct i2c_client *client)
{
struct adp5588_gpio_platform_data *pdata =
dev_get_platdata(&client->dev);
struct adp5588_gpio *dev;
struct gpio_chip *gc;
int ret, i, revid;
-
- if (!pdata) {
- dev_err(&client->dev, "missing platform data\n");
- return -ENODEV;
- }
+ unsigned int pullup_dis_mask = 0;
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA)) {
@@ -394,18 +352,24 @@ static int adp5588_gpio_probe(struct i2c_client *client,
gc->get = adp5588_gpio_get_value;
gc->set = adp5588_gpio_set_value;
gc->can_sleep = true;
+ gc->base = -1;
+ gc->parent = &client->dev;
+
+ if (pdata) {
+ gc->base = pdata->gpio_start;
+ gc->names = pdata->names;
+ pullup_dis_mask = pdata->pullup_dis_mask;
+ }
- gc->base = pdata->gpio_start;
gc->ngpio = ADP5588_MAXGPIO;
gc->label = client->name;
gc->owner = THIS_MODULE;
- gc->names = pdata->names;
mutex_init(&dev->lock);
ret = adp5588_gpio_read(dev->client, DEV_ID);
if (ret < 0)
- goto err;
+ return ret;
revid = ret & ADP5588_DEVICE_ID_MASK;
@@ -414,30 +378,27 @@ static int adp5588_gpio_probe(struct i2c_client *client,
dev->dir[i] = adp5588_gpio_read(client, GPIO_DIR1 + i);
ret |= adp5588_gpio_write(client, KP_GPIO1 + i, 0);
ret |= adp5588_gpio_write(client, GPIO_PULL1 + i,
- (pdata->pullup_dis_mask >> (8 * i)) & 0xFF);
+ (pullup_dis_mask >> (8 * i)) & 0xFF);
ret |= adp5588_gpio_write(client, GPIO_INT_EN1 + i, 0);
if (ret)
- goto err;
+ return ret;
}
- if (pdata->irq_base) {
+ if (client->irq) {
if (WA_DELAYED_READOUT_REVID(revid)) {
dev_warn(&client->dev, "GPIO int not supported\n");
} else {
ret = adp5588_irq_setup(dev);
if (ret)
- goto err;
+ return ret;
}
}
ret = devm_gpiochip_add_data(&client->dev, &dev->gpio_chip, dev);
if (ret)
- goto err_irq;
+ return ret;
- dev_info(&client->dev, "IRQ Base: %d Rev.: %d\n",
- pdata->irq_base, revid);
-
- if (pdata->setup) {
+ if (pdata && pdata->setup) {
ret = pdata->setup(client, gc->base, gc->ngpio, pdata->context);
if (ret < 0)
dev_warn(&client->dev, "setup failed, %d\n", ret);
@@ -446,11 +407,6 @@ static int adp5588_gpio_probe(struct i2c_client *client,
i2c_set_clientdata(client, dev);
return 0;
-
-err_irq:
- adp5588_irq_teardown(dev);
-err:
- return ret;
}
static int adp5588_gpio_remove(struct i2c_client *client)
@@ -460,7 +416,7 @@ static int adp5588_gpio_remove(struct i2c_client *client)
struct adp5588_gpio *dev = i2c_get_clientdata(client);
int ret;
- if (pdata->teardown) {
+ if (pdata && pdata->teardown) {
ret = pdata->teardown(client,
dev->gpio_chip.base, dev->gpio_chip.ngpio,
pdata->context);
@@ -470,7 +426,7 @@ static int adp5588_gpio_remove(struct i2c_client *client)
}
}
- if (dev->irq_base)
+ if (dev->client->irq)
free_irq(dev->client->irq, dev);
return 0;
@@ -480,14 +436,22 @@ static const struct i2c_device_id adp5588_gpio_id[] = {
{DRV_NAME, 0},
{}
};
-
MODULE_DEVICE_TABLE(i2c, adp5588_gpio_id);
+#ifdef CONFIG_OF
+static const struct of_device_id adp5588_gpio_of_id[] = {
+ { .compatible = "adi," DRV_NAME, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, adp5588_gpio_of_id);
+#endif
+
static struct i2c_driver adp5588_gpio_driver = {
.driver = {
- .name = DRV_NAME,
- },
- .probe = adp5588_gpio_probe,
+ .name = DRV_NAME,
+ .of_match_table = of_match_ptr(adp5588_gpio_of_id),
+ },
+ .probe_new = adp5588_gpio_probe,
.remove = adp5588_gpio_remove,
.id_table = adp5588_gpio_id,
};
diff --git a/drivers/gpio/gpio-altera.c b/drivers/gpio/gpio-altera.c
index 8c3ff6e2366f..748fdd4e9a53 100644
--- a/drivers/gpio/gpio-altera.c
+++ b/drivers/gpio/gpio-altera.c
@@ -32,9 +32,9 @@
* struct altera_gpio_chip
* @mmchip : memory mapped chip structure.
* @gpio_lock : synchronization lock so that new irq/set/get requests
- will be blocked until the current one completes.
+* will be blocked until the current one completes.
* @interrupt_trigger : specifies the hardware configured IRQ trigger type
- (rising, falling, both, high)
+* (rising, falling, both, high)
* @mapped_irq : kernel mapped irq number.
*/
struct altera_gpio_chip {
diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c
index e0d6a0a7bc69..64cc87d91790 100644
--- a/drivers/gpio/gpio-eic-sprd.c
+++ b/drivers/gpio/gpio-eic-sprd.c
@@ -420,6 +420,7 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
default:
return -ENOTSUPP;
}
+ break;
default:
dev_err(chip->parent, "Unsupported EIC type.\n");
return -ENOTSUPP;
diff --git a/drivers/gpio/gpio-f7188x.c b/drivers/gpio/gpio-f7188x.c
index 13350c9d7f5e..0896c825b312 100644
--- a/drivers/gpio/gpio-f7188x.c
+++ b/drivers/gpio/gpio-f7188x.c
@@ -39,8 +39,10 @@
#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
#define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
+#define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for f81966 */
-enum chips { f71869, f71869a, f71882fg, f71889a, f71889f, f81866 };
+
+enum chips { f71869, f71869a, f71882fg, f71889a, f71889f, f81866, f81804 };
static const char * const f7188x_names[] = {
"f71869",
@@ -49,6 +51,7 @@ static const char * const f7188x_names[] = {
"f71889a",
"f71889f",
"f81866",
+ "f81804",
};
struct f7188x_sio {
@@ -223,6 +226,18 @@ static struct f7188x_gpio_bank f81866_gpio_bank[] = {
F7188X_GPIO_BANK(80, 8, 0x88),
};
+
+static struct f7188x_gpio_bank f81804_gpio_bank[] = {
+ F7188X_GPIO_BANK(0, 8, 0xF0),
+ F7188X_GPIO_BANK(10, 8, 0xE0),
+ F7188X_GPIO_BANK(20, 8, 0xD0),
+ F7188X_GPIO_BANK(50, 8, 0xA0),
+ F7188X_GPIO_BANK(60, 8, 0x90),
+ F7188X_GPIO_BANK(70, 8, 0x80),
+ F7188X_GPIO_BANK(90, 8, 0x98),
+};
+
+
static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
{
int err;
@@ -407,6 +422,10 @@ static int f7188x_gpio_probe(struct platform_device *pdev)
data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
data->bank = f81866_gpio_bank;
break;
+ case f81804:
+ data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
+ data->bank = f81804_gpio_bank;
+ break;
default:
return -ENODEV;
}
@@ -469,6 +488,9 @@ static int __init f7188x_find(int addr, struct f7188x_sio *sio)
case SIO_F81866_ID:
sio->type = f81866;
break;
+ case SIO_F81804_ID:
+ sio->type = f81804;
+ break;
default:
pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
goto err;
diff --git a/drivers/gpio/gpio-gw-pld.c b/drivers/gpio/gpio-gw-pld.c
new file mode 100644
index 000000000000..242112ff60ee
--- /dev/null
+++ b/drivers/gpio/gpio-gw-pld.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Gateworks I2C PLD GPIO expander
+//
+// Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
+//
+// Based on code and know-how from the OpenWrt driver:
+// Copyright (C) 2009 Gateworks Corporation
+// Authors: Chris Lang, Imre Kaloz
+
+#include <linux/bits.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/gpio/driver.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+
+/**
+ * struct gw_pld - State container for Gateworks PLD
+ * @chip: GPIO chip instance
+ * @client: I2C client
+ * @out: shadow register for the output bute
+ */
+struct gw_pld {
+ struct gpio_chip chip;
+ struct i2c_client *client;
+ u8 out;
+};
+
+/*
+ * The Gateworks I2C PLD chip only expose one read and one write register.
+ * Writing a "one" bit (to match the reset state) lets that pin be used as an
+ * input. It is an open-drain model.
+ */
+static int gw_pld_input8(struct gpio_chip *gc, unsigned offset)
+{
+ struct gw_pld *gw = gpiochip_get_data(gc);
+
+ gw->out |= BIT(offset);
+ return i2c_smbus_write_byte(gw->client, gw->out);
+}
+
+static int gw_pld_get8(struct gpio_chip *gc, unsigned offset)
+{
+ struct gw_pld *gw = gpiochip_get_data(gc);
+ s32 val;
+
+ val = i2c_smbus_read_byte(gw->client);
+
+ return (val < 0) ? 0 : !!(val & BIT(offset));
+}
+
+static int gw_pld_output8(struct gpio_chip *gc, unsigned offset, int value)
+{
+ struct gw_pld *gw = gpiochip_get_data(gc);
+
+ if (value)
+ gw->out |= BIT(offset);
+ else
+ gw->out &= ~BIT(offset);
+
+ return i2c_smbus_write_byte(gw->client, gw->out);
+}
+
+static void gw_pld_set8(struct gpio_chip *gc, unsigned offset, int value)
+{
+ gw_pld_output8(gc, offset, value);
+}
+
+static int gw_pld_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct device *dev = &client->dev;
+ struct device_node *np = dev->of_node;
+ struct gw_pld *gw;
+ int ret;
+
+ gw = devm_kzalloc(dev, sizeof(*gw), GFP_KERNEL);
+ if (!gw)
+ return -ENOMEM;
+
+ gw->chip.base = -1;
+ gw->chip.can_sleep = true;
+ gw->chip.parent = dev;
+ gw->chip.of_node = np;
+ gw->chip.owner = THIS_MODULE;
+ gw->chip.label = dev_name(dev);
+ gw->chip.ngpio = 8;
+ gw->chip.direction_input = gw_pld_input8;
+ gw->chip.get = gw_pld_get8;
+ gw->chip.direction_output = gw_pld_output8;
+ gw->chip.set = gw_pld_set8;
+ gw->client = client;
+
+ /*
+ * The Gateworks I2C PLD chip does not properly send the acknowledge
+ * bit at all times, but we can still use the standard i2c_smbus
+ * functions by simply ignoring this bit.
+ */
+ client->flags |= I2C_M_IGNORE_NAK;
+ gw->out = 0xFF;
+
+ i2c_set_clientdata(client, gw);
+
+ ret = devm_gpiochip_add_data(dev, &gw->chip, gw);
+ if (ret)
+ return ret;
+
+ dev_info(dev, "registered Gateworks PLD GPIO device\n");
+
+ return 0;
+}
+
+static const struct i2c_device_id gw_pld_id[] = {
+ { "gw-pld", },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, gw_pld_id);
+
+static const struct of_device_id gw_pld_dt_ids[] = {
+ { .compatible = "gateworks,pld-gpio", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, gw_pld_dt_ids);
+
+static struct i2c_driver gw_pld_driver = {
+ .driver = {
+ .name = "gw_pld",
+ .of_match_table = gw_pld_dt_ids,
+ },
+ .probe = gw_pld_probe,
+ .id_table = gw_pld_id,
+};
+module_i2c_driver(gw_pld_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
diff --git a/drivers/gpio/gpio-hlwd.c b/drivers/gpio/gpio-hlwd.c
index a63136a68ba3..a7b17897356e 100644
--- a/drivers/gpio/gpio-hlwd.c
+++ b/drivers/gpio/gpio-hlwd.c
@@ -48,9 +48,163 @@
struct hlwd_gpio {
struct gpio_chip gpioc;
+ struct irq_chip irqc;
void __iomem *regs;
+ int irq;
+ u32 edge_emulation;
+ u32 rising_edge, falling_edge;
};
+static void hlwd_gpio_irqhandler(struct irq_desc *desc)
+{
+ struct hlwd_gpio *hlwd =
+ gpiochip_get_data(irq_desc_get_handler_data(desc));
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long flags;
+ unsigned long pending;
+ int hwirq;
+ u32 emulated_pending;
+
+ spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
+ pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
+ pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
+
+ /* Treat interrupts due to edge trigger emulation separately */
+ emulated_pending = hlwd->edge_emulation & pending;
+ pending &= ~emulated_pending;
+ if (emulated_pending) {
+ u32 level, rising, falling;
+
+ level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
+ rising = level & emulated_pending;
+ falling = ~level & emulated_pending;
+
+ /* Invert the levels */
+ iowrite32be(level ^ emulated_pending,
+ hlwd->regs + HW_GPIOB_INTLVL);
+
+ /* Ack all emulated-edge interrupts */
+ iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
+
+ /* Signal interrupts only on the correct edge */
+ rising &= hlwd->rising_edge;
+ falling &= hlwd->falling_edge;
+
+ /* Mark emulated interrupts as pending */
+ pending |= rising | falling;
+ }
+ spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
+
+ chained_irq_enter(chip, desc);
+
+ for_each_set_bit(hwirq, &pending, 32) {
+ int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);
+
+ generic_handle_irq(irq);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static void hlwd_gpio_irq_ack(struct irq_data *data)
+{
+ struct hlwd_gpio *hlwd =
+ gpiochip_get_data(irq_data_get_irq_chip_data(data));
+
+ iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
+}
+
+static void hlwd_gpio_irq_mask(struct irq_data *data)
+{
+ struct hlwd_gpio *hlwd =
+ gpiochip_get_data(irq_data_get_irq_chip_data(data));
+ unsigned long flags;
+ u32 mask;
+
+ spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
+ mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
+ mask &= ~BIT(data->hwirq);
+ iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
+ spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
+}
+
+static void hlwd_gpio_irq_unmask(struct irq_data *data)
+{
+ struct hlwd_gpio *hlwd =
+ gpiochip_get_data(irq_data_get_irq_chip_data(data));
+ unsigned long flags;
+ u32 mask;
+
+ spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
+ mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
+ mask |= BIT(data->hwirq);
+ iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
+ spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
+}
+
+static void hlwd_gpio_irq_enable(struct irq_data *data)
+{
+ hlwd_gpio_irq_ack(data);
+ hlwd_gpio_irq_unmask(data);
+}
+
+static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
+ unsigned int flow_type)
+{
+ u32 level, state;
+
+ /* Set the trigger level to the inactive level */
+ level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
+ state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
+ level &= ~BIT(hwirq);
+ level |= state ^ BIT(hwirq);
+ iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
+
+ hlwd->edge_emulation |= BIT(hwirq);
+ hlwd->rising_edge &= ~BIT(hwirq);
+ hlwd->falling_edge &= ~BIT(hwirq);
+ if (flow_type & IRQ_TYPE_EDGE_RISING)
+ hlwd->rising_edge |= BIT(hwirq);
+ if (flow_type & IRQ_TYPE_EDGE_FALLING)
+ hlwd->falling_edge |= BIT(hwirq);
+}
+
+static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
+{
+ struct hlwd_gpio *hlwd =
+ gpiochip_get_data(irq_data_get_irq_chip_data(data));
+ unsigned long flags;
+ u32 level;
+
+ spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
+
+ hlwd->edge_emulation &= ~BIT(data->hwirq);
+
+ switch (flow_type) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
+ level |= BIT(data->hwirq);
+ iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
+ level &= ~BIT(data->hwirq);
+ iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ case IRQ_TYPE_EDGE_FALLING:
+ case IRQ_TYPE_EDGE_BOTH:
+ hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
+ break;
+ default:
+ spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
+ return -EINVAL;
+ }
+
+ spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
+ return 0;
+}
+
static int hlwd_gpio_probe(struct platform_device *pdev)
{
struct hlwd_gpio *hlwd;
@@ -92,7 +246,43 @@ static int hlwd_gpio_probe(struct platform_device *pdev)
ngpios = 32;
hlwd->gpioc.ngpio = ngpios;
- return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
+ res = devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
+ if (res)
+ return res;
+
+ /* Mask and ack all interrupts */
+ iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
+ iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
+
+ /*
+ * If this GPIO controller is not marked as an interrupt controller in
+ * the DT, return.
+ */
+ if (!of_property_read_bool(pdev->dev.of_node, "interrupt-controller"))
+ return 0;
+
+ hlwd->irq = platform_get_irq(pdev, 0);
+ if (hlwd->irq < 0) {
+ dev_info(&pdev->dev, "platform_get_irq returned %d\n",
+ hlwd->irq);
+ return hlwd->irq;
+ }
+
+ hlwd->irqc.name = dev_name(&pdev->dev);
+ hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;
+ hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;
+ hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;
+ hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;
+
+ res = gpiochip_irqchip_add(&hlwd->gpioc, &hlwd->irqc, 0,
+ handle_level_irq, IRQ_TYPE_NONE);
+ if (res)
+ return res;
+
+ gpiochip_set_chained_irqchip(&hlwd->gpioc, &hlwd->irqc,
+ hlwd->irq, hlwd_gpio_irqhandler);
+
+ return 0;
}
static const struct of_device_id hlwd_gpio_match[] = {
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 7d5c55494ccd..f97ed32b8beb 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -376,6 +376,16 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
return 0;
}
+static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
+{
+ struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
+ u32 u;
+
+ regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
+
+ return !!(u & BIT(pin));
+}
+
static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
{
struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
@@ -1130,6 +1140,7 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
mvchip->chip.parent = &pdev->dev;
mvchip->chip.request = gpiochip_generic_request;
mvchip->chip.free = gpiochip_generic_free;
+ mvchip->chip.get_direction = mvebu_gpio_get_direction;
mvchip->chip.direction_input = mvebu_gpio_direction_input;
mvchip->chip.get = mvebu_gpio_get;
mvchip->chip.direction_output = mvebu_gpio_direction_output;
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 4cace44b179c..1e5579acd275 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -150,6 +150,7 @@ struct pca953x_chip {
u8 irq_stat[MAX_BANK];
u8 irq_trig_raise[MAX_BANK];
u8 irq_trig_fall[MAX_BANK];
+ struct irq_chip irq_chip;
#endif
struct i2c_client *client;
@@ -656,16 +657,6 @@ static void pca953x_irq_shutdown(struct irq_data *d)
chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask;
}
-static struct irq_chip pca953x_irq_chip = {
- .name = "pca953x",
- .irq_mask = pca953x_irq_mask,
- .irq_unmask = pca953x_irq_unmask,
- .irq_bus_lock = pca953x_irq_bus_lock,
- .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
- .irq_set_type = pca953x_irq_set_type,
- .irq_shutdown = pca953x_irq_shutdown,
-};
-
static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
{
u8 cur_stat[MAX_BANK];
@@ -761,56 +752,64 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
int irq_base)
{
struct i2c_client *client = chip->client;
+ struct irq_chip *irq_chip = &chip->irq_chip;
int reg_direction[MAX_BANK];
int ret, i;
- if (client->irq && irq_base != -1
- && (chip->driver_data & PCA_INT)) {
- ret = pca953x_read_regs(chip,
- chip->regs->input, chip->irq_stat);
- if (ret)
- return ret;
+ if (!client->irq)
+ return 0;
- /*
- * There is no way to know which GPIO line generated the
- * interrupt. We have to rely on the previous read for
- * this purpose.
- */
- regmap_bulk_read(chip->regmap, chip->regs->direction,
- reg_direction, NBANK(chip));
- for (i = 0; i < NBANK(chip); i++)
- chip->irq_stat[i] &= reg_direction[i];
- mutex_init(&chip->irq_lock);
-
- ret = devm_request_threaded_irq(&client->dev,
- client->irq,
- NULL,
- pca953x_irq_handler,
- IRQF_TRIGGER_LOW | IRQF_ONESHOT |
- IRQF_SHARED,
- dev_name(&client->dev), chip);
- if (ret) {
- dev_err(&client->dev, "failed to request irq %d\n",
- client->irq);
- return ret;
- }
+ if (irq_base == -1)
+ return 0;
- ret = gpiochip_irqchip_add_nested(&chip->gpio_chip,
- &pca953x_irq_chip,
- irq_base,
- handle_simple_irq,
- IRQ_TYPE_NONE);
- if (ret) {
- dev_err(&client->dev,
- "could not connect irqchip to gpiochip\n");
- return ret;
- }
+ if (!(chip->driver_data & PCA_INT))
+ return 0;
- gpiochip_set_nested_irqchip(&chip->gpio_chip,
- &pca953x_irq_chip,
- client->irq);
+ ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat);
+ if (ret)
+ return ret;
+
+ /*
+ * There is no way to know which GPIO line generated the
+ * interrupt. We have to rely on the previous read for
+ * this purpose.
+ */
+ regmap_bulk_read(chip->regmap, chip->regs->direction, reg_direction,
+ NBANK(chip));
+ for (i = 0; i < NBANK(chip); i++)
+ chip->irq_stat[i] &= reg_direction[i];
+ mutex_init(&chip->irq_lock);
+
+ ret = devm_request_threaded_irq(&client->dev, client->irq,
+ NULL, pca953x_irq_handler,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT |
+ IRQF_SHARED,
+ dev_name(&client->dev), chip);
+ if (ret) {
+ dev_err(&client->dev, "failed to request irq %d\n",
+ client->irq);
+ return ret;
}
+ irq_chip->name = dev_name(&chip->client->dev);
+ irq_chip->irq_mask = pca953x_irq_mask;
+ irq_chip->irq_unmask = pca953x_irq_unmask;
+ irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
+ irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
+ irq_chip->irq_set_type = pca953x_irq_set_type;
+ irq_chip->irq_shutdown = pca953x_irq_shutdown;
+
+ ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip,
+ irq_base, handle_simple_irq,
+ IRQ_TYPE_NONE);
+ if (ret) {
+ dev_err(&client->dev,
+ "could not connect irqchip to gpiochip\n");
+ return ret;
+ }
+
+ gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq);
+
return 0;
}
diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
index 29e044ff4b17..ac573da040bb 100644
--- a/drivers/gpio/gpio-pmic-eic-sprd.c
+++ b/drivers/gpio/gpio-pmic-eic-sprd.c
@@ -322,7 +322,6 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev)
ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,
sprd_pmic_eic_irq_handler,
- IRQF_TRIGGER_LOW |
IRQF_ONESHOT | IRQF_NO_SUSPEND,
dev_name(&pdev->dev), pmic_eic);
if (ret) {
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 068ce25ffd28..500a3596aaf4 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -40,6 +40,7 @@ struct gpio_rcar_priv {
struct irq_chip irq_chip;
unsigned int irq_parent;
atomic_t wakeup_path;
+ bool has_outdtsel;
bool has_both_edge_trigger;
struct gpio_rcar_bank_info bank_info;
};
@@ -55,6 +56,7 @@ struct gpio_rcar_priv {
#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
#define EDGLEVEL 0x24 /* Edge/level Select Register */
#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
+#define OUTDTSEL 0x40 /* Output Data Select Register */
#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
#define RCAR_MAX_GPIO_PER_BANK 32
@@ -235,6 +237,10 @@ static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
/* Select Input Mode or Output Mode in INOUTSEL */
gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
+ /* Select General Output Register to output data in OUTDTSEL */
+ if (p->has_outdtsel && output)
+ gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
+
spin_unlock_irqrestore(&p->lock, flags);
}
@@ -336,14 +342,17 @@ static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
}
struct gpio_rcar_info {
+ bool has_outdtsel;
bool has_both_edge_trigger;
};
static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
+ .has_outdtsel = false,
.has_both_edge_trigger = false,
};
static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
+ .has_outdtsel = true,
.has_both_edge_trigger = true,
};
@@ -403,10 +412,11 @@ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
int ret;
info = of_device_get_match_data(p->dev);
+ p->has_outdtsel = info->has_outdtsel;
+ p->has_both_edge_trigger = info->has_both_edge_trigger;
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
- p->has_both_edge_trigger = info->has_both_edge_trigger;
if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
diff --git a/drivers/gpio/gpio-sama5d2-piobu.c b/drivers/gpio/gpio-sama5d2-piobu.c
index 03a000659fa1..7d718557092e 100644
--- a/drivers/gpio/gpio-sama5d2-piobu.c
+++ b/drivers/gpio/gpio-sama5d2-piobu.c
@@ -109,16 +109,6 @@ static int sama5d2_piobu_read_value(struct gpio_chip *chip, unsigned int pin,
}
/**
- * sama5d2_piobu_set_direction() - mark pin as input or output
- */
-static int sama5d2_piobu_set_direction(struct gpio_chip *chip,
- unsigned int direction,
- unsigned int pin)
-{
- return sama5d2_piobu_write_value(chip, pin, PIOBU_DIRECTION, direction);
-}
-
-/**
* sama5d2_piobu_get_direction() - gpiochip get_direction
*/
static int sama5d2_piobu_get_direction(struct gpio_chip *chip,
@@ -138,7 +128,7 @@ static int sama5d2_piobu_get_direction(struct gpio_chip *chip,
static int sama5d2_piobu_direction_input(struct gpio_chip *chip,
unsigned int pin)
{
- return sama5d2_piobu_set_direction(chip, PIOBU_IN, pin);
+ return sama5d2_piobu_write_value(chip, pin, PIOBU_DIRECTION, PIOBU_IN);
}
/**
@@ -147,7 +137,13 @@ static int sama5d2_piobu_direction_input(struct gpio_chip *chip,
static int sama5d2_piobu_direction_output(struct gpio_chip *chip,
unsigned int pin, int value)
{
- return sama5d2_piobu_set_direction(chip, PIOBU_OUT, pin);
+ unsigned int val = PIOBU_OUT;
+
+ if (value)
+ val |= PIOBU_HIGH;
+
+ return sama5d2_piobu_write_value(chip, pin, PIOBU_DIRECTION | PIOBU_SOD,
+ val);
}
/**
diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c
new file mode 100644
index 000000000000..33dbe483f92f
--- /dev/null
+++ b/drivers/gpio/gpio-tqmx86.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TQ-Systems TQMx86 PLD GPIO driver
+ *
+ * Based on vendor driver by:
+ * Vadim V.Vlasov <vvlasov@dev.rtsoft.ru>
+ */
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+
+#define TQMX86_NGPIO 8
+#define TQMX86_NGPO 4 /* 0-3 - output */
+#define TQMX86_NGPI 4 /* 4-7 - input */
+#define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
+
+#define TQMX86_GPIODD 0 /* GPIO Data Direction Register */
+#define TQMX86_GPIOD 1 /* GPIO Data Register */
+#define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */
+#define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */
+
+#define TQMX86_GPII_FALLING BIT(0)
+#define TQMX86_GPII_RISING BIT(1)
+#define TQMX86_GPII_MASK (BIT(0) | BIT(1))
+#define TQMX86_GPII_BITS 2
+
+struct tqmx86_gpio_data {
+ struct gpio_chip chip;
+ struct irq_chip irq_chip;
+ void __iomem *io_base;
+ int irq;
+ raw_spinlock_t spinlock;
+ u8 irq_type[TQMX86_NGPI];
+};
+
+static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg)
+{
+ return ioread8(gd->io_base + reg);
+}
+
+static void tqmx86_gpio_write(struct tqmx86_gpio_data *gd, u8 val,
+ unsigned int reg)
+{
+ iowrite8(val, gd->io_base + reg);
+}
+
+static int tqmx86_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+ struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
+
+ return !!(tqmx86_gpio_read(gpio, TQMX86_GPIOD) & BIT(offset));
+}
+
+static void tqmx86_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int value)
+{
+ struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
+ unsigned long flags;
+ u8 val;
+
+ raw_spin_lock_irqsave(&gpio->spinlock, flags);
+ val = tqmx86_gpio_read(gpio, TQMX86_GPIOD);
+ if (value)
+ val |= BIT(offset);
+ else
+ val &= ~BIT(offset);
+ tqmx86_gpio_write(gpio, val, TQMX86_GPIOD);
+ raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
+}
+
+static int tqmx86_gpio_direction_input(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ /* Direction cannot be changed. Validate is an input. */
+ if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
+ return 0;
+ else
+ return -EINVAL;
+}
+
+static int tqmx86_gpio_direction_output(struct gpio_chip *chip,
+ unsigned int offset,
+ int value)
+{
+ /* Direction cannot be changed, validate is an output */
+ if (BIT(offset) & TQMX86_DIR_INPUT_MASK)
+ return -EINVAL;
+ else
+ return 0;
+}
+
+static int tqmx86_gpio_get_direction(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ return !!(TQMX86_DIR_INPUT_MASK & BIT(offset));
+}
+
+static void tqmx86_gpio_irq_mask(struct irq_data *data)
+{
+ unsigned int offset = (data->hwirq - TQMX86_NGPO);
+ struct tqmx86_gpio_data *gpio = gpiochip_get_data(
+ irq_data_get_irq_chip_data(data));
+ unsigned long flags;
+ u8 gpiic, mask;
+
+ mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
+
+ raw_spin_lock_irqsave(&gpio->spinlock, flags);
+ gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
+ gpiic &= ~mask;
+ tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
+ raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
+}
+
+static void tqmx86_gpio_irq_unmask(struct irq_data *data)
+{
+ unsigned int offset = (data->hwirq - TQMX86_NGPO);
+ struct tqmx86_gpio_data *gpio = gpiochip_get_data(
+ irq_data_get_irq_chip_data(data));
+ unsigned long flags;
+ u8 gpiic, mask;
+
+ mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
+
+ raw_spin_lock_irqsave(&gpio->spinlock, flags);
+ gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
+ gpiic &= ~mask;
+ gpiic |= gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS);
+ tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
+ raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
+}
+
+static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct tqmx86_gpio_data *gpio = gpiochip_get_data(
+ irq_data_get_irq_chip_data(data));
+ unsigned int offset = (data->hwirq - TQMX86_NGPO);
+ unsigned int edge_type = type & IRQF_TRIGGER_MASK;
+ unsigned long flags;
+ u8 new_type, gpiic;
+
+ switch (edge_type) {
+ case IRQ_TYPE_EDGE_RISING:
+ new_type = TQMX86_GPII_RISING;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ new_type = TQMX86_GPII_FALLING;
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ new_type = TQMX86_GPII_FALLING | TQMX86_GPII_RISING;
+ break;
+ default:
+ return -EINVAL; /* not supported */
+ }
+
+ gpio->irq_type[offset] = new_type;
+
+ raw_spin_lock_irqsave(&gpio->spinlock, flags);
+ gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
+ gpiic &= ~((TQMX86_GPII_MASK) << (offset * TQMX86_GPII_BITS));
+ gpiic |= new_type << (offset * TQMX86_GPII_BITS);
+ tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
+ raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
+
+ return 0;
+}
+
+static void tqmx86_gpio_irq_handler(struct irq_desc *desc)
+{
+ struct gpio_chip *chip = irq_desc_get_handler_data(desc);
+ struct tqmx86_gpio_data *gpio = gpiochip_get_data(chip);
+ struct irq_chip *irq_chip = irq_desc_get_chip(desc);
+ unsigned long irq_bits;
+ int i = 0, child_irq;
+ u8 irq_status;
+
+ chained_irq_enter(irq_chip, desc);
+
+ irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
+ tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
+
+ irq_bits = irq_status;
+ for_each_set_bit(i, &irq_bits, TQMX86_NGPI) {
+ child_irq = irq_find_mapping(gpio->chip.irq.domain,
+ i + TQMX86_NGPO);
+ generic_handle_irq(child_irq);
+ }
+
+ chained_irq_exit(irq_chip, desc);
+}
+
+/* Minimal runtime PM is needed by the IRQ subsystem */
+static int __maybe_unused tqmx86_gpio_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int __maybe_unused tqmx86_gpio_runtime_resume(struct device *dev)
+{
+ return 0;
+}
+
+static const struct dev_pm_ops tqmx86_gpio_dev_pm_ops = {
+ SET_RUNTIME_PM_OPS(tqmx86_gpio_runtime_suspend,
+ tqmx86_gpio_runtime_resume, NULL)
+};
+
+static int tqmx86_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct tqmx86_gpio_data *gpio;
+ struct gpio_chip *chip;
+ void __iomem *io_base;
+ struct resource *res;
+ int ret, irq;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ res = platform_get_resource(pdev, IORESOURCE_IO, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Cannot get I/O\n");
+ return -ENODEV;
+ }
+
+ io_base = devm_ioport_map(&pdev->dev, res->start, resource_size(res));
+ if (!io_base)
+ return -ENOMEM;
+
+ gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
+ if (!gpio)
+ return -ENOMEM;
+
+ raw_spin_lock_init(&gpio->spinlock);
+ gpio->io_base = io_base;
+
+ tqmx86_gpio_write(gpio, (u8)~TQMX86_DIR_INPUT_MASK, TQMX86_GPIODD);
+
+ platform_set_drvdata(pdev, gpio);
+
+ chip = &gpio->chip;
+ chip->label = "gpio-tqmx86";
+ chip->owner = THIS_MODULE;
+ chip->can_sleep = false;
+ chip->base = -1;
+ chip->direction_input = tqmx86_gpio_direction_input;
+ chip->direction_output = tqmx86_gpio_direction_output;
+ chip->get_direction = tqmx86_gpio_get_direction;
+ chip->get = tqmx86_gpio_get;
+ chip->set = tqmx86_gpio_set;
+ chip->ngpio = TQMX86_NGPIO;
+ chip->irq.need_valid_mask = true;
+ chip->parent = pdev->dev.parent;
+
+ pm_runtime_enable(&pdev->dev);
+
+ ret = devm_gpiochip_add_data(dev, chip, gpio);
+ if (ret) {
+ dev_err(dev, "Could not register GPIO chip\n");
+ goto out_pm_dis;
+ }
+
+ if (irq) {
+ struct irq_chip *irq_chip = &gpio->irq_chip;
+ u8 irq_status;
+
+ irq_chip->name = chip->label;
+ irq_chip->parent_device = &pdev->dev;
+ irq_chip->irq_mask = tqmx86_gpio_irq_mask;
+ irq_chip->irq_unmask = tqmx86_gpio_irq_unmask;
+ irq_chip->irq_set_type = tqmx86_gpio_irq_set_type;
+
+ /* Mask all interrupts */
+ tqmx86_gpio_write(gpio, 0, TQMX86_GPIIC);
+
+ /* Clear all pending interrupts */
+ irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS);
+ tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS);
+
+ ret = gpiochip_irqchip_add(chip, irq_chip,
+ 0, handle_simple_irq,
+ IRQ_TYPE_EDGE_BOTH);
+ if (ret) {
+ dev_err(dev, "Could not add irq chip\n");
+ goto out_pm_dis;
+ }
+
+ gpiochip_set_chained_irqchip(chip, irq_chip,
+ irq, tqmx86_gpio_irq_handler);
+ }
+
+ /* Only GPIOs 4-7 are valid for interrupts. Clear the others */
+ clear_bit(0, chip->irq.valid_mask);
+ clear_bit(1, chip->irq.valid_mask);
+ clear_bit(2, chip->irq.valid_mask);
+ clear_bit(3, chip->irq.valid_mask);
+
+ dev_info(dev, "GPIO functionality initialized with %d pins\n",
+ chip->ngpio);
+
+ return 0;
+
+out_pm_dis:
+ pm_runtime_disable(&pdev->dev);
+
+ return ret;
+}
+
+static struct platform_driver tqmx86_gpio_driver = {
+ .driver = {
+ .name = "tqmx86-gpio",
+ .pm = &tqmx86_gpio_dev_pm_ops,
+ },
+ .probe = tqmx86_gpio_probe,
+};
+
+module_platform_driver(tqmx86_gpio_driver);
+
+MODULE_DESCRIPTION("TQMx86 PLD GPIO Driver");
+MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:tqmx86-gpio");
diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c
index b3b4edcdffe0..00ff7b1fa8a1 100644
--- a/drivers/gpio/gpio-zynq.c
+++ b/drivers/gpio/gpio-zynq.c
@@ -555,6 +555,26 @@ static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
return 0;
}
+static int zynq_gpio_irq_reqres(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ int ret;
+
+ ret = pm_runtime_get_sync(chip->parent);
+ if (ret < 0)
+ return ret;
+
+ return gpiochip_reqres_irq(chip, d->hwirq);
+}
+
+static void zynq_gpio_irq_relres(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+
+ gpiochip_relres_irq(chip, d->hwirq);
+ pm_runtime_put(chip->parent);
+}
+
/* irq chip descriptor */
static struct irq_chip zynq_gpio_level_irqchip = {
.name = DRIVER_NAME,
@@ -564,6 +584,8 @@ static struct irq_chip zynq_gpio_level_irqchip = {
.irq_unmask = zynq_gpio_irq_unmask,
.irq_set_type = zynq_gpio_set_irq_type,
.irq_set_wake = zynq_gpio_set_wake,
+ .irq_request_resources = zynq_gpio_irq_reqres,
+ .irq_release_resources = zynq_gpio_irq_relres,
.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
IRQCHIP_MASK_ON_SUSPEND,
};
@@ -576,6 +598,8 @@ static struct irq_chip zynq_gpio_edge_irqchip = {
.irq_unmask = zynq_gpio_irq_unmask,
.irq_set_type = zynq_gpio_set_irq_type,
.irq_set_wake = zynq_gpio_set_wake,
+ .irq_request_resources = zynq_gpio_irq_reqres,
+ .irq_release_resources = zynq_gpio_irq_relres,
.flags = IRQCHIP_MASK_ON_SUSPEND,
};
diff --git a/drivers/gpio/gpiolib-acpi.c b/drivers/gpio/gpiolib-acpi.c
index 48534bda73d3..3401823427f6 100644
--- a/drivers/gpio/gpiolib-acpi.c
+++ b/drivers/gpio/gpiolib-acpi.c
@@ -29,7 +29,7 @@
* @irq: Linux IRQ number for the event, for request_ / free_irq
* @irqflags: flags to pass to request_irq when requesting the IRQ
* @irq_is_wake: If the ACPI flags indicate the IRQ is a wakeup source
- * @is_requested: True if request_irq has been done
+ * @irq_requested:True if request_irq has been done
* @desc: gpio_desc for the GPIO pin for this event
*/
struct acpi_gpio_event {
@@ -474,6 +474,9 @@ acpi_gpio_to_gpiod_flags(const struct acpi_resource_gpio *agpio)
static int
__acpi_gpio_update_gpiod_flags(enum gpiod_flags *flags, enum gpiod_flags update)
{
+ const enum gpiod_flags mask =
+ GPIOD_FLAGS_BIT_DIR_SET | GPIOD_FLAGS_BIT_DIR_OUT |
+ GPIOD_FLAGS_BIT_DIR_VAL;
int ret = 0;
/*
@@ -494,7 +497,7 @@ __acpi_gpio_update_gpiod_flags(enum gpiod_flags *flags, enum gpiod_flags update)
if (((*flags & GPIOD_FLAGS_BIT_DIR_SET) && (diff & GPIOD_FLAGS_BIT_DIR_OUT)) ||
((*flags & GPIOD_FLAGS_BIT_DIR_OUT) && (diff & GPIOD_FLAGS_BIT_DIR_VAL)))
ret = -EINVAL;
- *flags = update;
+ *flags = (*flags & ~mask) | (update & mask);
}
return ret;
}
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 22d8b37f5319..9be4c9401172 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1775,6 +1775,43 @@ static const struct irq_domain_ops gpiochip_domain_ops = {
.xlate = irq_domain_xlate_twocell,
};
+/**
+ * gpiochip_irq_domain_activate() - Lock a GPIO to be used as an IRQ
+ * @domain: The IRQ domain used by this IRQ chip
+ * @data: Outermost irq_data associated with the IRQ
+ * @reserve: If set, only reserve an interrupt vector instead of assigning one
+ *
+ * This function is a wrapper that calls gpiochip_lock_as_irq() and is to be
+ * used as the activate function for the &struct irq_domain_ops. The host_data
+ * for the IRQ domain must be the &struct gpio_chip.
+ */
+int gpiochip_irq_domain_activate(struct irq_domain *domain,
+ struct irq_data *data, bool reserve)
+{
+ struct gpio_chip *chip = domain->host_data;
+
+ return gpiochip_lock_as_irq(chip, data->hwirq);
+}
+EXPORT_SYMBOL_GPL(gpiochip_irq_domain_activate);
+
+/**
+ * gpiochip_irq_domain_deactivate() - Unlock a GPIO used as an IRQ
+ * @domain: The IRQ domain used by this IRQ chip
+ * @data: Outermost irq_data associated with the IRQ
+ *
+ * This function is a wrapper that will call gpiochip_unlock_as_irq() and is to
+ * be used as the deactivate function for the &struct irq_domain_ops. The
+ * host_data for the IRQ domain must be the &struct gpio_chip.
+ */
+void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
+ struct irq_data *data)
+{
+ struct gpio_chip *chip = domain->host_data;
+
+ return gpiochip_unlock_as_irq(chip, data->hwirq);
+}
+EXPORT_SYMBOL_GPL(gpiochip_irq_domain_deactivate);
+
static int gpiochip_to_irq(struct gpio_chip *chip, unsigned offset)
{
if (!gpiochip_irqchip_irq_valid(chip, offset))
generated by cgit (git 2.34.1) at 2024-06-04 17:10:15 +0000