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path: root/drivers/gpu/drm/amd/amdgpu/cz_ih.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cz_ih.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_ih.c53
1 files changed, 35 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 80d508e64a86..bc751bfbcae2 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -250,15 +250,18 @@ static void cz_ih_set_rptr(struct amdgpu_device *adev)
WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
}
-static int cz_ih_early_init(struct amdgpu_device *adev)
+static int cz_ih_early_init(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
cz_ih_set_interrupt_funcs(adev);
return 0;
}
-static int cz_ih_sw_init(struct amdgpu_device *adev)
+static int cz_ih_sw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
if (r)
@@ -269,17 +272,20 @@ static int cz_ih_sw_init(struct amdgpu_device *adev)
return r;
}
-static int cz_ih_sw_fini(struct amdgpu_device *adev)
+static int cz_ih_sw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
amdgpu_irq_fini(adev);
amdgpu_ih_ring_fini(adev);
return 0;
}
-static int cz_ih_hw_init(struct amdgpu_device *adev)
+static int cz_ih_hw_init(void *handle)
{
int r;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
r = cz_ih_irq_init(adev);
if (r)
@@ -288,25 +294,32 @@ static int cz_ih_hw_init(struct amdgpu_device *adev)
return 0;
}
-static int cz_ih_hw_fini(struct amdgpu_device *adev)
+static int cz_ih_hw_fini(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
cz_ih_irq_disable(adev);
return 0;
}
-static int cz_ih_suspend(struct amdgpu_device *adev)
+static int cz_ih_suspend(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return cz_ih_hw_fini(adev);
}
-static int cz_ih_resume(struct amdgpu_device *adev)
+static int cz_ih_resume(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
return cz_ih_hw_init(adev);
}
-static bool cz_ih_is_idle(struct amdgpu_device *adev)
+static bool cz_ih_is_idle(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
@@ -315,10 +328,11 @@ static bool cz_ih_is_idle(struct amdgpu_device *adev)
return true;
}
-static int cz_ih_wait_for_idle(struct amdgpu_device *adev)
+static int cz_ih_wait_for_idle(void *handle)
{
unsigned i;
u32 tmp;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
for (i = 0; i < adev->usec_timeout; i++) {
/* read MC_STATUS */
@@ -330,8 +344,10 @@ static int cz_ih_wait_for_idle(struct amdgpu_device *adev)
return -ETIMEDOUT;
}
-static void cz_ih_print_status(struct amdgpu_device *adev)
+static void cz_ih_print_status(void *handle)
{
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
dev_info(adev->dev, "CZ IH registers\n");
dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(mmSRBM_STATUS));
@@ -357,9 +373,10 @@ static void cz_ih_print_status(struct amdgpu_device *adev)
RREG32(mmIH_RB_WPTR));
}
-static int cz_ih_soft_reset(struct amdgpu_device *adev)
+static int cz_ih_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
@@ -367,7 +384,7 @@ static int cz_ih_soft_reset(struct amdgpu_device *adev)
SOFT_RESET_IH, 1);
if (srbm_soft_reset) {
- cz_ih_print_status(adev);
+ cz_ih_print_status((void *)adev);
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
@@ -384,27 +401,27 @@ static int cz_ih_soft_reset(struct amdgpu_device *adev)
/* Wait a little for things to settle down */
udelay(50);
- cz_ih_print_status(adev);
+ cz_ih_print_status((void *)adev);
}
return 0;
}
-static int cz_ih_set_clockgating_state(struct amdgpu_device *adev,
- enum amdgpu_clockgating_state state)
+static int cz_ih_set_clockgating_state(void *handle,
+ enum amd_clockgating_state state)
{
// TODO
return 0;
}
-static int cz_ih_set_powergating_state(struct amdgpu_device *adev,
- enum amdgpu_powergating_state state)
+static int cz_ih_set_powergating_state(void *handle,
+ enum amd_powergating_state state)
{
// TODO
return 0;
}
-const struct amdgpu_ip_funcs cz_ih_ip_funcs = {
+const struct amd_ip_funcs cz_ih_ip_funcs = {
.early_init = cz_ih_early_init,
.late_init = NULL,
.sw_init = cz_ih_sw_init,