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path: root/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_hw_types.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_hw_types.h7
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 100d62162b71..9649934ea186 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -769,9 +769,6 @@ struct dc_crtc_timing_flags {
uint32_t LTE_340MCSC_SCRAMBLE:1;
uint32_t DSC : 1; /* Use DSC with this timing */
-#ifndef TRIM_FSFT
- uint32_t FAST_TRANSPORT: 1;
-#endif
uint32_t VBLANK_SYNCHRONIZABLE: 1;
};
@@ -950,10 +947,6 @@ struct dc_crtc_timing {
enum dc_aspect_ratio aspect_ratio;
enum scanning_type scan_type;
-#ifndef TRIM_FSFT
- uint32_t fast_transport_output_rate_100hz;
-#endif
-
struct dc_crtc_timing_flags flags;
uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
struct dc_dsc_config dsc_cfg;