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path: root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index db766689af58..aaf6c981fd9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -189,6 +189,15 @@ struct dcn_optc_registers {
uint32_t OTG_M_CONST_DTO1;
uint32_t OTG_DRR_V_TOTAL_CHANGE;
uint32_t OTG_GLOBAL_CONTROL4;
+ uint32_t OTG_CRC0_WINDOWA_X_CONTROL_READBACK;
+ uint32_t OTG_CRC0_WINDOWA_Y_CONTROL_READBACK;
+ uint32_t OTG_CRC0_WINDOWB_X_CONTROL_READBACK;
+ uint32_t OTG_CRC0_WINDOWB_Y_CONTROL_READBACK;
+ uint32_t OTG_CRC1_WINDOWA_X_CONTROL_READBACK;
+ uint32_t OTG_CRC1_WINDOWA_Y_CONTROL_READBACK;
+ uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK;
+ uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK;
+ uint32_t OPTC_CLOCK_CONTROL;
};
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -554,14 +563,35 @@ struct dcn_optc_registers {
type OTG_H_TIMING_DIV_MODE_MANUAL;
+#define TG_REG_FIELD_LIST_DCN3_5(type) \
+ type OTG_CRC0_WINDOWA_X_START_READBACK;\
+ type OTG_CRC0_WINDOWA_X_END_READBACK;\
+ type OTG_CRC0_WINDOWA_Y_START_READBACK;\
+ type OTG_CRC0_WINDOWA_Y_END_READBACK;\
+ type OTG_CRC0_WINDOWB_X_START_READBACK;\
+ type OTG_CRC0_WINDOWB_X_END_READBACK;\
+ type OTG_CRC0_WINDOWB_Y_START_READBACK;\
+ type OTG_CRC0_WINDOWB_Y_END_READBACK; \
+ type OTG_CRC1_WINDOWA_X_START_READBACK;\
+ type OTG_CRC1_WINDOWA_X_END_READBACK;\
+ type OTG_CRC1_WINDOWA_Y_START_READBACK;\
+ type OTG_CRC1_WINDOWA_Y_END_READBACK;\
+ type OTG_CRC1_WINDOWB_X_START_READBACK;\
+ type OTG_CRC1_WINDOWB_X_END_READBACK;\
+ type OTG_CRC1_WINDOWB_Y_START_READBACK;\
+ type OTG_CRC1_WINDOWB_Y_END_READBACK;\
+ type OPTC_FGCG_REP_DIS;
+
struct dcn_optc_shift {
TG_REG_FIELD_LIST(uint8_t)
TG_REG_FIELD_LIST_DCN3_2(uint8_t)
+ TG_REG_FIELD_LIST_DCN3_5(uint8_t)
};
struct dcn_optc_mask {
TG_REG_FIELD_LIST(uint32_t)
TG_REG_FIELD_LIST_DCN3_2(uint32_t)
+ TG_REG_FIELD_LIST_DCN3_5(uint32_t)
};
struct optc {