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path: root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ad82f19fe36a..5ac85df158b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1840,8 +1840,16 @@ void dcn20_program_front_end_for_ctx(
dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) {
struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg;
- if (tg->funcs->enable_crtc)
+ if (tg->funcs->enable_crtc) {
+ if (dc->hwss.blank_phantom) {
+ int main_pipe_width, main_pipe_height;
+
+ main_pipe_width = dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.paired_stream->dst.width;
+ main_pipe_height = dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.paired_stream->dst.height;
+ dc->hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height);
+ }
tg->funcs->enable_crtc(tg);
+ }
}
}
/* OTG blank before disabling all front ends */