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path: root/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h18
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index cff5fd55a0ad..6f4c97543c14 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -73,7 +73,7 @@ enum dentist_divider_range {
clk_mgr->base.ctx
#define DC_LOGGER \
- clk_mgr->base.ctx->logger
+ dc->ctx->logger
@@ -163,7 +163,13 @@ enum dentist_divider_range {
CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \
CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \
CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \
- CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL)
+ CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL), \
+ CLK_SR_DCN32(CLK1_CLK0_CURRENT_CNT), \
+ CLK_SR_DCN32(CLK1_CLK1_CURRENT_CNT), \
+ CLK_SR_DCN32(CLK1_CLK2_CURRENT_CNT), \
+ CLK_SR_DCN32(CLK1_CLK3_CURRENT_CNT), \
+ CLK_SR_DCN32(CLK1_CLK4_CURRENT_CNT), \
+ CLK_SR_DCN32(CLK4_CLK0_CURRENT_CNT)
#define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
@@ -222,6 +228,8 @@ struct clk_mgr_registers {
uint32_t CLK4_CLK2_CURRENT_CNT;
uint32_t CLK4_CLK_PLL_REQ;
+ uint32_t CLK4_CLK0_CURRENT_CNT;
+
uint32_t CLK3_CLK2_DFS_CNTL;
uint32_t CLK3_CLK_PLL_REQ;
@@ -235,6 +243,12 @@ struct clk_mgr_registers {
uint32_t CLK1_CLK3_DFS_CNTL;
uint32_t CLK1_CLK4_DFS_CNTL;
+ uint32_t CLK1_CLK0_CURRENT_CNT;
+ uint32_t CLK1_CLK1_CURRENT_CNT;
+ uint32_t CLK1_CLK2_CURRENT_CNT;
+ uint32_t CLK1_CLK3_CURRENT_CNT;
+ uint32_t CLK1_CLK4_CURRENT_CNT;
+
uint32_t CLK0_CLK0_DFS_CNTL;
uint32_t CLK0_CLK1_DFS_CNTL;
uint32_t CLK0_CLK3_DFS_CNTL;