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path: root/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h')
-rw-r--r--drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h17
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
index d58a1e4b9f1c..b0cd8d29402f 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h
@@ -107,6 +107,12 @@ struct dmub_srv;
DMUB_SR(DMCUB_SCRATCH15) \
DMUB_SR(DMCUB_SCRATCH16) \
DMUB_SR(DMCUB_SCRATCH17) \
+ DMUB_SR(DMCUB_SCRATCH18) \
+ DMUB_SR(DMCUB_SCRATCH19) \
+ DMUB_SR(DMCUB_SCRATCH20) \
+ DMUB_SR(DMCUB_SCRATCH21) \
+ DMUB_SR(DMCUB_SCRATCH22) \
+ DMUB_SR(DMCUB_SCRATCH23) \
DMUB_SR(DMCUB_GPINT_DATAIN0) \
DMUB_SR(DMCUB_GPINT_DATAIN1) \
DMUB_SR(DMCUB_GPINT_DATAOUT) \
@@ -178,13 +184,11 @@ struct dmub_srv_dcn32_reg_mask {
};
struct dmub_srv_dcn32_regs {
- const struct dmub_srv_dcn32_reg_offset offset;
- const struct dmub_srv_dcn32_reg_mask mask;
- const struct dmub_srv_dcn32_reg_shift shift;
+ struct dmub_srv_dcn32_reg_offset offset;
+ struct dmub_srv_dcn32_reg_mask mask;
+ struct dmub_srv_dcn32_reg_shift shift;
};
-extern const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs;
-
void dmub_dcn32_reset(struct dmub_srv *dmub);
void dmub_dcn32_reset_release(struct dmub_srv *dmub);
@@ -255,5 +259,8 @@ void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub);
void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub);
uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);
+void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);
+
+void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
#endif /* _DMUB_DCN32_H_ */