diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h | 359 |
1 files changed, 359 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h new file mode 100644 index 000000000000..920de67dd1e8 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h @@ -0,0 +1,359 @@ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * + */ +#ifndef _mp_14_0_0_OFFSET_HEADER +#define _mp_14_0_0_OFFSET_HEADER + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define regMP1_SMN_C2PMSG_0 0x0240 +#define regMP1_SMN_C2PMSG_0_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_1 0x0241 +#define regMP1_SMN_C2PMSG_1_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_2 0x0242 +#define regMP1_SMN_C2PMSG_2_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_3 0x0243 +#define regMP1_SMN_C2PMSG_3_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_4 0x0244 +#define regMP1_SMN_C2PMSG_4_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_5 0x0245 +#define regMP1_SMN_C2PMSG_5_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_6 0x0246 +#define regMP1_SMN_C2PMSG_6_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_7 0x0247 +#define regMP1_SMN_C2PMSG_7_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_8 0x0248 +#define regMP1_SMN_C2PMSG_8_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_9 0x0249 +#define regMP1_SMN_C2PMSG_9_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_10 0x024a +#define regMP1_SMN_C2PMSG_10_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_11 0x024b +#define regMP1_SMN_C2PMSG_11_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_12 0x024c +#define regMP1_SMN_C2PMSG_12_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_13 0x024d +#define regMP1_SMN_C2PMSG_13_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_14 0x024e +#define regMP1_SMN_C2PMSG_14_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_15 0x024f +#define regMP1_SMN_C2PMSG_15_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_16 0x0250 +#define regMP1_SMN_C2PMSG_16_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_17 0x0251 +#define regMP1_SMN_C2PMSG_17_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_18 0x0252 +#define regMP1_SMN_C2PMSG_18_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_19 0x0253 +#define regMP1_SMN_C2PMSG_19_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_20 0x0254 +#define regMP1_SMN_C2PMSG_20_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_21 0x0255 +#define regMP1_SMN_C2PMSG_21_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_22 0x0256 +#define regMP1_SMN_C2PMSG_22_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_23 0x0257 +#define regMP1_SMN_C2PMSG_23_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_24 0x0258 +#define regMP1_SMN_C2PMSG_24_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_25 0x0259 +#define regMP1_SMN_C2PMSG_25_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_26 0x025a +#define regMP1_SMN_C2PMSG_26_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_27 0x025b +#define regMP1_SMN_C2PMSG_27_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_28 0x025c +#define regMP1_SMN_C2PMSG_28_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_29 0x025d +#define regMP1_SMN_C2PMSG_29_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_30 0x025e +#define regMP1_SMN_C2PMSG_30_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_31 0x025f +#define regMP1_SMN_C2PMSG_31_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_32 0x0260 +#define regMP1_SMN_C2PMSG_32_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_33 0x0261 +#define regMP1_SMN_C2PMSG_33_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_34 0x0262 +#define regMP1_SMN_C2PMSG_34_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_35 0x0263 +#define regMP1_SMN_C2PMSG_35_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_36 0x0264 +#define regMP1_SMN_C2PMSG_36_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_37 0x0265 +#define regMP1_SMN_C2PMSG_37_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_38 0x0266 +#define regMP1_SMN_C2PMSG_38_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_39 0x0267 +#define regMP1_SMN_C2PMSG_39_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_40 0x0268 +#define regMP1_SMN_C2PMSG_40_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_41 0x0269 +#define regMP1_SMN_C2PMSG_41_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_42 0x026a +#define regMP1_SMN_C2PMSG_42_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_43 0x026b +#define regMP1_SMN_C2PMSG_43_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_44 0x026c +#define regMP1_SMN_C2PMSG_44_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_45 0x026d +#define regMP1_SMN_C2PMSG_45_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_46 0x026e +#define regMP1_SMN_C2PMSG_46_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_47 0x026f +#define regMP1_SMN_C2PMSG_47_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_48 0x0270 +#define regMP1_SMN_C2PMSG_48_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_49 0x0271 +#define regMP1_SMN_C2PMSG_49_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_50 0x0272 +#define regMP1_SMN_C2PMSG_50_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_51 0x0273 +#define regMP1_SMN_C2PMSG_51_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_52 0x0274 +#define regMP1_SMN_C2PMSG_52_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_53 0x0275 +#define regMP1_SMN_C2PMSG_53_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_54 0x0276 +#define regMP1_SMN_C2PMSG_54_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_55 0x0277 +#define regMP1_SMN_C2PMSG_55_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_56 0x0278 +#define regMP1_SMN_C2PMSG_56_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_57 0x0279 +#define regMP1_SMN_C2PMSG_57_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_58 0x027a +#define regMP1_SMN_C2PMSG_58_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_59 0x027b +#define regMP1_SMN_C2PMSG_59_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_60 0x027c +#define regMP1_SMN_C2PMSG_60_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_61 0x027d +#define regMP1_SMN_C2PMSG_61_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_62 0x027e +#define regMP1_SMN_C2PMSG_62_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_63 0x027f +#define regMP1_SMN_C2PMSG_63_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_64 0x0280 +#define regMP1_SMN_C2PMSG_64_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_65 0x0281 +#define regMP1_SMN_C2PMSG_65_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_66 0x0282 +#define regMP1_SMN_C2PMSG_66_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_67 0x0283 +#define regMP1_SMN_C2PMSG_67_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_68 0x0284 +#define regMP1_SMN_C2PMSG_68_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_69 0x0285 +#define regMP1_SMN_C2PMSG_69_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_70 0x0286 +#define regMP1_SMN_C2PMSG_70_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_71 0x0287 +#define regMP1_SMN_C2PMSG_71_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_72 0x0288 +#define regMP1_SMN_C2PMSG_72_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_73 0x0289 +#define regMP1_SMN_C2PMSG_73_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_74 0x028a +#define regMP1_SMN_C2PMSG_74_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_75 0x028b +#define regMP1_SMN_C2PMSG_75_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_76 0x028c +#define regMP1_SMN_C2PMSG_76_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_77 0x028d +#define regMP1_SMN_C2PMSG_77_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_78 0x028e +#define regMP1_SMN_C2PMSG_78_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_79 0x028f +#define regMP1_SMN_C2PMSG_79_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_80 0x0290 +#define regMP1_SMN_C2PMSG_80_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_81 0x0291 +#define regMP1_SMN_C2PMSG_81_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_82 0x0292 +#define regMP1_SMN_C2PMSG_82_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_83 0x0293 +#define regMP1_SMN_C2PMSG_83_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_84 0x0294 +#define regMP1_SMN_C2PMSG_84_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_85 0x0295 +#define regMP1_SMN_C2PMSG_85_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_86 0x0296 +#define regMP1_SMN_C2PMSG_86_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_87 0x0297 +#define regMP1_SMN_C2PMSG_87_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_88 0x0298 +#define regMP1_SMN_C2PMSG_88_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_89 0x0299 +#define regMP1_SMN_C2PMSG_89_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_90 0x029a +#define regMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_91 0x029b +#define regMP1_SMN_C2PMSG_91_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_92 0x029c +#define regMP1_SMN_C2PMSG_92_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_93 0x029d +#define regMP1_SMN_C2PMSG_93_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_94 0x029e +#define regMP1_SMN_C2PMSG_94_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_95 0x029f +#define regMP1_SMN_C2PMSG_95_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_96 0x02a0 +#define regMP1_SMN_C2PMSG_96_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_97 0x02a1 +#define regMP1_SMN_C2PMSG_97_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_98 0x02a2 +#define regMP1_SMN_C2PMSG_98_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_99 0x02a3 +#define regMP1_SMN_C2PMSG_99_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_100 0x02a4 +#define regMP1_SMN_C2PMSG_100_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_101 0x02a5 +#define regMP1_SMN_C2PMSG_101_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_102 0x02a6 +#define regMP1_SMN_C2PMSG_102_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_103 0x02a7 +#define regMP1_SMN_C2PMSG_103_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_104 0x02a8 +#define regMP1_SMN_C2PMSG_104_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_105 0x02a9 +#define regMP1_SMN_C2PMSG_105_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_106 0x02aa +#define regMP1_SMN_C2PMSG_106_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_107 0x02ab +#define regMP1_SMN_C2PMSG_107_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_108 0x02ac +#define regMP1_SMN_C2PMSG_108_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_109 0x02ad +#define regMP1_SMN_C2PMSG_109_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_110 0x02ae +#define regMP1_SMN_C2PMSG_110_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_111 0x02af +#define regMP1_SMN_C2PMSG_111_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_112 0x02b0 +#define regMP1_SMN_C2PMSG_112_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_113 0x02b1 +#define regMP1_SMN_C2PMSG_113_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_114 0x02b2 +#define regMP1_SMN_C2PMSG_114_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_115 0x02b3 +#define regMP1_SMN_C2PMSG_115_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_116 0x02b4 +#define regMP1_SMN_C2PMSG_116_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_117 0x02b5 +#define regMP1_SMN_C2PMSG_117_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_118 0x02b6 +#define regMP1_SMN_C2PMSG_118_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_119 0x02b7 +#define regMP1_SMN_C2PMSG_119_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_120 0x02b8 +#define regMP1_SMN_C2PMSG_120_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_121 0x02b9 +#define regMP1_SMN_C2PMSG_121_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_122 0x02ba +#define regMP1_SMN_C2PMSG_122_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_123 0x02bb +#define regMP1_SMN_C2PMSG_123_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_124 0x02bc +#define regMP1_SMN_C2PMSG_124_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_125 0x02bd +#define regMP1_SMN_C2PMSG_125_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_126 0x02be +#define regMP1_SMN_C2PMSG_126_BASE_IDX 0 +#define regMP1_SMN_C2PMSG_127 0x02bf +#define regMP1_SMN_C2PMSG_127_BASE_IDX 0 +#define regMP1_SMN_IH_CREDIT 0x0340 +#define regMP1_SMN_IH_CREDIT_BASE_IDX 0 +#define regMP1_SMN_IH_SW_INT 0x0341 +#define regMP1_SMN_IH_SW_INT_BASE_IDX 0 +#define regMP1_SMN_IH_SW_INT_CTRL 0x0342 +#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +#define regMP1_SMN_FPS_CNT 0x0343 +#define regMP1_SMN_FPS_CNT_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH0 0x03c0 +#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH1 0x03c1 +#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH2 0x03c2 +#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH3 0x03c3 +#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH4 0x03c4 +#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH5 0x03c5 +#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH6 0x03c6 +#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH7 0x03c7 +#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH8 0x03c8 +#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH9 0x03c9 +#define regMP1_SMN_EXT_SCRATCH9_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH10 0x03ca +#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH11 0x03cb +#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH12 0x03cc +#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH13 0x03cd +#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH14 0x03ce +#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH15 0x03cf +#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH16 0x03d0 +#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH17 0x03d1 +#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH18 0x03d2 +#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH19 0x03d3 +#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH20 0x03d4 +#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH21 0x03d5 +#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH22 0x03d6 +#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH23 0x03d7 +#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH24 0x03d8 +#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH25 0x03d9 +#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH26 0x03da +#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH27 0x03db +#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH28 0x03dc +#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH29 0x03dd +#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH30 0x03de +#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 0 +#define regMP1_SMN_EXT_SCRATCH31 0x03df +#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 0 + + +#endif |