diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/kgd_pp_interface.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/kgd_pp_interface.h | 165 |
1 files changed, 164 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 84c5224d994c..3201808c2dd8 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -28,6 +28,7 @@ extern const struct amdgpu_ip_block_version pp_smu_ip_block; extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; +extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; enum smu_event_type { SMU_EVENT_RESET_COMPLETE = 0, @@ -113,6 +114,11 @@ enum pp_clock_type { OD_RANGE, OD_VDDGFX_OFFSET, OD_CCLK, + OD_FAN_CURVE, + OD_ACOUSTIC_LIMIT, + OD_ACOUSTIC_TARGET, + OD_FAN_TARGET_TEMPERATURE, + OD_FAN_MINIMUM_PWM, }; enum amd_pp_sensors { @@ -186,7 +192,12 @@ enum PP_OD_DPM_TABLE_COMMAND { PP_OD_EDIT_VDDC_CURVE, PP_OD_RESTORE_DEFAULT_TABLE, PP_OD_COMMIT_DPM_TABLE, - PP_OD_EDIT_VDDGFX_OFFSET + PP_OD_EDIT_VDDGFX_OFFSET, + PP_OD_EDIT_FAN_CURVE, + PP_OD_EDIT_ACOUSTIC_LIMIT, + PP_OD_EDIT_ACOUSTIC_TARGET, + PP_OD_EDIT_FAN_TARGET_TEMPERATURE, + PP_OD_EDIT_FAN_MINIMUM_PWM, }; struct pp_states_info { @@ -255,6 +266,14 @@ enum pp_power_type PP_PWR_TYPE_FAST, }; +enum pp_xgmi_plpd_mode { + XGMI_PLPD_NONE = -1, + XGMI_PLPD_DISALLOW, + XGMI_PLPD_DEFAULT, + XGMI_PLPD_OPTIMIZED, + XGMI_PLPD_COUNT, +}; + #define PP_GROUP_MASK 0xF0000000 #define PP_GROUP_SHIFT 28 @@ -295,6 +314,10 @@ enum pp_power_type #define XGMI_MODE_PSTATE_D0 1 #define NUM_HBM_INSTANCES 4 +#define NUM_XGMI_LINKS 8 +#define MAX_GFX_CLKS 8 +#define MAX_CLKS 4 +#define NUM_VCN 4 struct seq_file; enum amd_pp_clock_type; @@ -678,6 +701,78 @@ struct gpu_metrics_v1_3 { uint64_t indep_throttle_status; }; +struct gpu_metrics_v1_4 { + struct metrics_table_header common_header; + + /* Temperature (Celsius) */ + uint16_t temperature_hotspot; + uint16_t temperature_mem; + uint16_t temperature_vrsoc; + + /* Power (Watts) */ + uint16_t curr_socket_power; + + /* Utilization (%) */ + uint16_t average_gfx_activity; + uint16_t average_umc_activity; // memory controller + uint16_t vcn_activity[NUM_VCN]; + + /* Energy (15.259uJ (2^-16) units) */ + uint64_t energy_accumulator; + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Throttle status */ + uint32_t throttle_status; + + /* Clock Lock Status. Each bit corresponds to clock instance */ + uint32_t gfxclk_lock_status; + + /* Link width (number of lanes) and speed (in 0.1 GT/s) */ + uint16_t pcie_link_width; + uint16_t pcie_link_speed; + + /* XGMI bus width and bitrate (in Gbps) */ + uint16_t xgmi_link_width; + uint16_t xgmi_link_speed; + + /* Utilization Accumulated (%) */ + uint32_t gfx_activity_acc; + uint32_t mem_activity_acc; + + /*PCIE accumulated bandwidth (GB/sec) */ + uint64_t pcie_bandwidth_acc; + + /*PCIE instantaneous bandwidth (GB/sec) */ + uint64_t pcie_bandwidth_inst; + + /* PCIE L0 to recovery state transition accumulated count */ + uint64_t pcie_l0_to_recov_count_acc; + + /* PCIE replay accumulated count */ + uint64_t pcie_replay_count_acc; + + /* PCIE replay rollover accumulated count */ + uint64_t pcie_replay_rover_count_acc; + + /* XGMI accumulated data transfer size(KiloBytes) */ + uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; + uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; + + /* PMFW attached timestamp (10ns resolution) */ + uint64_t firmware_timestamp; + + /* Current clocks (Mhz) */ + uint16_t current_gfxclk[MAX_GFX_CLKS]; + uint16_t current_socclk[MAX_CLKS]; + uint16_t current_vclk0[MAX_CLKS]; + uint16_t current_dclk0[MAX_CLKS]; + uint16_t current_uclk; + + uint16_t padding; +}; + /* * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v2_1 or later instead. @@ -962,4 +1057,72 @@ struct gpu_metrics_v2_4 { uint16_t average_soc_current; uint16_t average_gfx_current; }; + +struct gpu_metrics_v3_0 { + struct metrics_table_header common_header; + + /* Temperature */ + /* gfx temperature on APUs */ + uint16_t temperature_gfx; + /* soc temperature on APUs */ + uint16_t temperature_soc; + /* CPU core temperature on APUs */ + uint16_t temperature_core[16]; + /* skin temperature on APUs */ + uint16_t temperature_skin; + + /* Utilization */ + /* time filtered GFX busy % [0-100] */ + uint16_t average_gfx_activity; + /* time filtered VCN busy % [0-100] */ + uint16_t average_vcn_activity; + /* time filtered IPU per-column busy % [0-100] */ + uint16_t average_ipu_activity[8]; + /* time filtered per-core C0 residency % [0-100]*/ + uint16_t average_core_c0_activity[16]; + /* time filtered DRAM read bandwidth [GB/sec] */ + uint16_t average_dram_reads; + /* time filtered DRAM write bandwidth [GB/sec] */ + uint16_t average_dram_writes; + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Power/Energy */ + /* average dGPU + APU power on A + A platform */ + uint32_t average_socket_power; + /* average IPU power [W] */ + uint16_t average_ipu_power; + /* average APU power [W] */ + uint32_t average_apu_power; + /* average dGPU power [W] */ + uint32_t average_dgpu_power; + /* sum of core power across all cores in the socket [W] */ + uint32_t average_core_power; + /* calculated core power [W] */ + uint16_t core_power[16]; + /* maximum IRM defined STAPM power limit [W] */ + uint16_t stapm_power_limit; + /* time filtered STAPM power limit [W] */ + uint16_t current_stapm_power_limit; + + /* Average clocks */ + uint16_t average_gfxclk_frequency; + uint16_t average_socclk_frequency; + uint16_t average_vpeclk_frequency; + uint16_t average_ipuclk_frequency; + uint16_t average_fclk_frequency; + uint16_t average_vclk_frequency; + + /* Current clocks */ + /* target core frequency */ + uint16_t current_coreclk[16]; + /* CCLK frequency limit enforced on classic cores [MHz] */ + uint16_t current_core_maxfreq; + /* GFXCLK frequency limit enforced on GFX [MHz] */ + uint16_t current_gfx_maxfreq; + + /* Metrics table alpha filter time constant [us] */ + uint32_t time_filter_alphavalue; +}; #endif |