diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_types.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_types.h | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 01eb6e4e6049..860e867586f4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -33,6 +33,7 @@ #include <drm/display/drm_dp_dual_mode_helper.h> #include <drm/display/drm_dp_mst_helper.h> +#include <drm/display/drm_dp_tunnel.h> #include <drm/display/drm_dsc.h> #include <drm/drm_atomic.h> #include <drm/drm_crtc.h> @@ -327,7 +328,6 @@ struct intel_vbt_panel_data { struct edp_power_seq pps; u8 drrs_msa_timing_delay; bool low_vswing; - bool initialized; bool hobl; } edp; @@ -499,15 +499,15 @@ struct intel_hdcp_shim { struct intel_connector *connector); /* Detects panel's hdcp capability. This is optional for HDMI. */ - int (*hdcp_capable)(struct intel_digital_port *dig_port, - bool *hdcp_capable); + int (*hdcp_get_capability)(struct intel_digital_port *dig_port, + bool *hdcp_capable); /* HDCP adaptation(DP/HDMI) required on the port */ enum hdcp_wired_protocol protocol; /* Detects whether sink is HDCP2.2 capable */ - int (*hdcp_2_2_capable)(struct intel_connector *connector, - bool *capable); + int (*hdcp_2_2_get_capability)(struct intel_connector *connector, + bool *capable); /* Write HDCP2.2 messages */ int (*write_2_2_msg)(struct intel_connector *connector, @@ -532,6 +532,10 @@ struct intel_hdcp_shim { /* HDCP2.2 Link Integrity Check */ int (*check_2_2_link)(struct intel_digital_port *dig_port, struct intel_connector *connector); + + /* HDCP remote sink cap */ + int (*get_remote_hdcp_capability)(struct intel_connector *connector, + bool *hdcp_capable, bool *hdcp2_capable); }; struct intel_hdcp { @@ -626,6 +630,8 @@ struct intel_connector { struct intel_dp *mst_port; + bool force_bigjoiner_enable; + struct { struct drm_dp_aux *dsc_decompression_aux; u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; @@ -677,6 +683,8 @@ struct intel_atomic_state { struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; + struct intel_dp_tunnel_inherited_state *inherited_dp_tunnels; + /* * Current watermarks can't be trusted during hardware readout, so * don't bother calculating intermediate watermarks. @@ -1374,6 +1382,9 @@ struct intel_crtc_state { struct drm_dsc_config config; } dsc; + /* DP tunnel used for BW allocation. */ + struct drm_dp_tunnel_ref dp_tunnel_ref; + /* HSW+ linetime watermarks */ u16 linetime; u16 ips_linetime; @@ -1784,6 +1795,9 @@ struct intel_dp { /* connector directly attached - won't be use for modeset in mst world */ struct intel_connector *attached_connector; + struct drm_dp_tunnel *tunnel; + bool tunnel_suspended:1; + /* mst connector list */ struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; struct drm_dp_mst_topology_mgr mst_mgr; |