diff options
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_lvds.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_lvds.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index c6c7c0b9989b..f31a368f34c5 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -136,12 +136,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, pipe_config->hw.adjusted_mode.flags |= flags; - if (INTEL_GEN(dev_priv) < 5) + if (DISPLAY_VER(dev_priv) < 5) pipe_config->gmch_pfit.lvds_border_bits = tmp & LVDS_BORDER_ENABLE; /* gen2/3 store dither state in pfit control, needs to match */ - if (INTEL_GEN(dev_priv) < 4) { + if (DISPLAY_VER(dev_priv) < 4) { tmp = intel_de_read(dev_priv, PFIT_CONTROL); pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; @@ -179,7 +179,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, /* Convert from 100ms to 100us units */ pps->t4 = val * 1000; - if (INTEL_GEN(dev_priv) <= 4 && + if (DISPLAY_VER(dev_priv) <= 4 && pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { drm_dbg_kms(&dev_priv->drm, "Panel power timings uninitialized, " @@ -280,7 +280,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state, * special lvds dither control bit on pch-split platforms, dithering is * only controlled through the PIPECONF reg. */ - if (IS_GEN(dev_priv, 4)) { + if (IS_DISPLAY_VER(dev_priv, 4)) { /* * Bspec wording suggests that LVDS port dithering only exists * for 18bpp panels. @@ -415,7 +415,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, int ret; /* Should never happen!! */ - if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { + if (DISPLAY_VER(dev_priv) < 4 && intel_crtc->pipe == 0) { drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n"); return -EINVAL; } @@ -915,7 +915,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; intel_encoder->port = PORT_NONE; intel_encoder->cloneable = 0; - if (INTEL_GEN(dev_priv) < 4) + if (DISPLAY_VER(dev_priv) < 4) intel_encoder->pipe_mask = BIT(PIPE_B); else intel_encoder->pipe_mask = ~0; |