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Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_request.h')
-rw-r--r--drivers/gpu/drm/i915/i915_gem_request.h33
1 files changed, 21 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h
index 0d6d39f19506..2236e9188c5c 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -245,18 +245,6 @@ i915_gem_request_put(struct drm_i915_gem_request *req)
dma_fence_put(&req->fence);
}
-static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
- struct drm_i915_gem_request *src)
-{
- if (src)
- i915_gem_request_get(src);
-
- if (*pdst)
- i915_gem_request_put(*pdst);
-
- *pdst = src;
-}
-
/**
* i915_gem_request_global_seqno - report the current global seqno
* @request - the request
@@ -341,6 +329,27 @@ i915_gem_request_completed(const struct drm_i915_gem_request *req)
return __i915_gem_request_completed(req, seqno);
}
+static inline bool
+i915_gem_request_started(const struct drm_i915_gem_request *req)
+{
+ u32 seqno;
+
+ seqno = i915_gem_request_global_seqno(req);
+ if (!seqno)
+ return false;
+
+ return i915_seqno_passed(intel_engine_get_seqno(req->engine),
+ seqno - 1);
+}
+
+static inline bool i915_priotree_signaled(const struct i915_priotree *pt)
+{
+ const struct drm_i915_gem_request *rq =
+ container_of(pt, const struct drm_i915_gem_request, priotree);
+
+ return i915_gem_request_completed(rq);
+}
+
/* We treat requests as fences. This is not be to confused with our
* "fence registers" but pipeline synchronisation objects ala GL_ARB_sync.
* We use the fences to synchronize access from the CPU with activity on the