diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_clock_gating.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_clock_gating.c | 60 |
1 files changed, 2 insertions, 58 deletions
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 81a4d32734e9..9c21ce69bd98 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -349,41 +349,6 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *i915, intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl); } -static void icl_init_clock_gating(struct drm_i915_private *i915) -{ - /* Wa_1409120013:icl,ehl */ - intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), - DPFC_CHICKEN_COMP_DUMMY_PIXEL); - - /*Wa_14010594013:icl, ehl */ - intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, - 0, ICL_DELAY_PMRSP); -} - -static void gen12lp_init_clock_gating(struct drm_i915_private *i915) -{ - /* Wa_1409120013 */ - if (DISPLAY_VER(i915) == 12) - intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), - DPFC_CHICKEN_COMP_DUMMY_PIXEL); - - /* Wa_14013723622:tgl,rkl,dg1,adl-s */ - if (DISPLAY_VER(i915) == 12) - intel_uncore_rmw(&i915->uncore, CLKREQ_POLICY, - CLKREQ_POLICY_MEM_UP_OVRD, 0); -} - -static void adlp_init_clock_gating(struct drm_i915_private *i915) -{ - gen12lp_init_clock_gating(i915); - - /* Wa_22011091694:adlp */ - intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); - - /* Bspec/49189 Initialize Sequence */ - intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); -} - static void xehpsdv_init_clock_gating(struct drm_i915_private *i915) { /* Wa_22010146351:xehpsdv */ @@ -396,14 +361,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915) /* Wa_22010954014:dg2 */ intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS); - - /* - * Wa_14010733611:dg2_g10 - * Wa_22010146351:dg2_g10 - */ - if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) - intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, - SGR_DIS | SGGI_DIS); } static void pvc_init_clock_gating(struct drm_i915_private *i915) @@ -808,9 +765,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = CG_FUNCS(pvc); CG_FUNCS(dg2); CG_FUNCS(xehpsdv); -CG_FUNCS(adlp); -CG_FUNCS(gen12lp); -CG_FUNCS(icl); CG_FUNCS(cfl); CG_FUNCS(skl); CG_FUNCS(kbl); @@ -843,20 +797,12 @@ CG_FUNCS(nop); */ void intel_clock_gating_hooks_init(struct drm_i915_private *i915) { - if (IS_METEORLAKE(i915)) - i915->clock_gating_funcs = &nop_clock_gating_funcs; - else if (IS_PONTEVECCHIO(i915)) + if (IS_PONTEVECCHIO(i915)) i915->clock_gating_funcs = &pvc_clock_gating_funcs; else if (IS_DG2(i915)) i915->clock_gating_funcs = &dg2_clock_gating_funcs; else if (IS_XEHPSDV(i915)) i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs; - else if (IS_ALDERLAKE_P(i915)) - i915->clock_gating_funcs = &adlp_clock_gating_funcs; - else if (GRAPHICS_VER(i915) == 12) - i915->clock_gating_funcs = &gen12lp_clock_gating_funcs; - else if (GRAPHICS_VER(i915) == 11) - i915->clock_gating_funcs = &icl_clock_gating_funcs; else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) i915->clock_gating_funcs = &cfl_clock_gating_funcs; else if (IS_SKYLAKE(i915)) @@ -893,8 +839,6 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915) i915->clock_gating_funcs = &i85x_clock_gating_funcs; else if (GRAPHICS_VER(i915) == 2) i915->clock_gating_funcs = &i830_clock_gating_funcs; - else { - MISSING_CASE(INTEL_DEVID(i915)); + else i915->clock_gating_funcs = &nop_clock_gating_funcs; - } } |