diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 60 |
1 files changed, 18 insertions, 42 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index b860784ade72..6c9634209e9f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -29,23 +29,9 @@ #define MAX_XIN_COUNT 16 /** - * Supported UBWC feature versions - */ -enum { - DPU_HW_UBWC_VER_10 = 0x100, - DPU_HW_UBWC_VER_20 = 0x200, - DPU_HW_UBWC_VER_30 = 0x300, - DPU_HW_UBWC_VER_40 = 0x400, -}; - -/** * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats - * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. - * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth - * compression initial revision - * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results * in a failure * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register @@ -56,9 +42,6 @@ enum { enum { DPU_MDP_PANIC_PER_PIPE = 0x1, DPU_MDP_10BIT_SUPPORT, - DPU_MDP_BWC, - DPU_MDP_UBWC_1_0, - DPU_MDP_UBWC_1_5, DPU_MDP_AUDIO_SELECT, DPU_MDP_PERIPH_0_REMOVED, DPU_MDP_VSYNC_SEL, @@ -181,7 +164,6 @@ enum { * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register - * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register * @DPU_INTF_MAX */ enum { @@ -189,7 +171,6 @@ enum { DPU_INTF_TE, DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, - DPU_INTF_DATA_COMPRESS, DPU_INTF_MAX }; @@ -505,19 +486,6 @@ struct dpu_mdp_cfg { struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; }; -/** - * struct dpu_ubwc_cfg - UBWC and memory configuration - * - * @ubwc_version UBWC feature version (0x0 for not supported) - * @highest_bank_bit: UBWC parameter - * @ubwc_swizzle: ubwc default swizzle setting - */ -struct dpu_ubwc_cfg { - u32 ubwc_version; - u32 highest_bank_bit; - u32 ubwc_swizzle; -}; - /* struct dpu_ctl_cfg : MDP CTL instance info * @id: index identifying this block * @base: register base offset to mdss @@ -554,14 +522,14 @@ struct dpu_sspp_cfg { * @features bit mask identifying sub-blocks/features * @sblk: LM Sub-blocks information * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported - * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL + * @lm_pair: ID of LM that can be controlled by same CTL */ struct dpu_lm_cfg { DPU_HW_BLK_INFO; const struct dpu_lm_sub_blks *sblk; u32 pingpong; u32 dspp; - unsigned long lm_pair_mask; + unsigned long lm_pair; }; /** @@ -747,6 +715,16 @@ struct dpu_perf_cdp_cfg { }; /** + * struct dpu_mdss_version - DPU's major and minor versions + * @core_major_ver: DPU core's major version + * @core_minor_ver: DPU core's minor version + */ +struct dpu_mdss_version { + u8 core_major_ver; + u8 core_minor_ver; +}; + +/** * struct dpu_perf_cfg - performance control settings * @max_bw_low low threshold of maximum bandwidth (kbps) * @max_bw_high high threshold of maximum bandwidth (kbps) @@ -796,20 +774,19 @@ struct dpu_perf_cfg { /** * struct dpu_mdss_cfg - information of MDSS HW * This is the main catalog data structure representing - * this HW version. Contains number of instances, - * register offsets, capabilities of the all MDSS HW sub-blocks. + * this HW version. Contains dpu's major and minor versions, + * number of instances, register offsets, capabilities of the + * all MDSS HW sub-blocks. * * @dma_formats Supported formats for dma pipe * @cursor_formats Supported formats for cursor pipe * @vig_formats Supported formats for vig pipe - * @mdss_irqs: Bitmap with the irqs supported by the target */ struct dpu_mdss_cfg { - const struct dpu_caps *caps; + const struct dpu_mdss_version *mdss_ver; - const struct dpu_ubwc_cfg *ubwc; + const struct dpu_caps *caps; - u32 mdp_count; const struct dpu_mdp_cfg *mdp; u32 ctl_count; @@ -850,8 +827,6 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *dma_formats; const struct dpu_format_extended *cursor_formats; const struct dpu_format_extended *vig_formats; - - unsigned long mdss_irqs; }; extern const struct dpu_mdss_cfg dpu_msm8998_cfg; @@ -861,6 +836,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_sm6125_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; extern const struct dpu_mdss_cfg dpu_sm6375_cfg; |