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path: root/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
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Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c')
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c793
1 files changed, 694 insertions, 99 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 5c521de71567..48c96b812126 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -25,6 +25,9 @@
#define MDP_AD4_INTR_EN_OFF 0x41c
#define MDP_AD4_INTR_CLEAR_OFF 0x424
#define MDP_AD4_INTR_STATUS_OFF 0x420
+#define MDP_INTF_0_OFF_REV_7xxx 0x34000
+#define MDP_INTF_1_OFF_REV_7xxx 0x35000
+#define MDP_INTF_5_OFF_REV_7xxx 0x39000
/**
* WB interrupt status bit definitions
@@ -69,10 +72,12 @@
#define DPU_INTR_INTF_1_UNDERRUN BIT(26)
#define DPU_INTR_INTF_2_UNDERRUN BIT(28)
#define DPU_INTR_INTF_3_UNDERRUN BIT(30)
+#define DPU_INTR_INTF_5_UNDERRUN BIT(22)
#define DPU_INTR_INTF_0_VSYNC BIT(25)
#define DPU_INTR_INTF_1_VSYNC BIT(27)
#define DPU_INTR_INTF_2_VSYNC BIT(29)
#define DPU_INTR_INTF_3_VSYNC BIT(31)
+#define DPU_INTR_INTF_5_VSYNC BIT(23)
/**
* Pingpong Secondary interrupt status bit definitions
@@ -242,7 +247,22 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF,
MDP_AD4_1_OFF + MDP_AD4_INTR_EN_OFF,
MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF,
- }
+ },
+ {
+ MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_CLEAR,
+ MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_EN,
+ MDP_INTF_0_OFF_REV_7xxx+INTF_INTR_STATUS
+ },
+ {
+ MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_CLEAR,
+ MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,
+ MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS
+ },
+ {
+ MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,
+ MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
+ MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS
+ },
};
/*
@@ -308,24 +328,59 @@ static const struct dpu_irq_type dpu_irq_map[] = {
{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0},
{ DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0},
{ DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0},
-
- /* BEGIN MAP_RANGE: 32-64, INTR2 */
- /* irq_idx: 32-35 */
+ /* irq_idx:32-33 */
+ { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0},
+ { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0},
+ /* irq_idx:34-63 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 0},
+ /* BEGIN MAP_RANGE: 64-95, INTR2 */
+ /* irq_idx: 64-67 */
{ DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0,
DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
- /* irq_idx: 36-39 */
+ /* irq_idx: 68-71 */
{ DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0,
DPU_INTR_PING_PONG_S0_WR_PTR, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
- /* irq_idx: 40 */
+ /* irq_idx: 72 */
{ DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
DPU_INTR_PING_PONG_S0_RD_PTR, 1},
- /* irq_idx: 41-45 */
+ /* irq_idx: 73-77 */
{ DPU_IRQ_TYPE_CTL_START, CTL_0,
DPU_INTR_CTL_0_START, 1},
{ DPU_IRQ_TYPE_CTL_START, CTL_1,
@@ -336,10 +391,10 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_CTL_3_START, 1},
{ DPU_IRQ_TYPE_CTL_START, CTL_4,
DPU_INTR_CTL_4_START, 1},
- /* irq_idx: 46-47 */
+ /* irq_idx: 78-79 */
{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1},
{ DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1},
- /* irq_idx: 48-51 */
+ /* irq_idx: 80-83 */
{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0,
DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1},
{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1,
@@ -348,13 +403,13 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1},
{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3,
DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1},
- /* irq_idx: 52-55 */
+ /* irq_idx: 84-87 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
{ DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0,
DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
- /* irq_idx: 56-59 */
+ /* irq_idx: 88-91 */
{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0,
DPU_INTR_PING_PONG_0_TE_DETECTED, 1},
{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1,
@@ -363,65 +418,129 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_PING_PONG_2_TE_DETECTED, 1},
{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3,
DPU_INTR_PING_PONG_3_TE_DETECTED, 1},
- /* irq_idx: 60-63 */
+ /* irq_idx: 92-95 */
{ DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0,
DPU_INTR_PING_PONG_S0_TE_DETECTED, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
-
- /* BEGIN MAP_RANGE: 64-95 HIST */
- /* irq_idx: 64-67 */
+ /* irq_idx: 96-127 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 1},
+ /* BEGIN MAP_RANGE: 128-159 HIST */
+ /* irq_idx: 128-131 */
{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2},
{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0,
DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
- /* irq_idx: 68-71 */
+ /* irq_idx: 132-135 */
{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2},
{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1,
DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
- /* irq_idx: 72-75 */
+ /* irq_idx: 136-139 */
{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2},
{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2,
DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2},
{ DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2},
{ DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3,
DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2},
- /* irq_idx: 76-79 */
+ /* irq_idx: 140-143 */
{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2},
{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0,
DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
- /* irq_idx: 80-83 */
+ /* irq_idx: 144-147 */
{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2},
{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1,
DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
- /* irq_idx: 84-87 */
+ /* irq_idx: 148-151 */
{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2},
{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2,
DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2},
{ DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2},
{ DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3,
DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2},
- /* irq_idx: 88-91 */
+ /* irq_idx: 152-155 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
- /* irq_idx: 92-95 */
+ /* irq_idx: 156-159 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
-
- /* BEGIN MAP_RANGE: 96-127 INTF_0_INTR */
- /* irq_idx: 96-99 */
+ /* irq_idx: 160-191 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 2},
+ /* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */
+ /* irq_idx: 192-195 */
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
DPU_INTR_VIDEO_INTO_STATIC, 3},
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
@@ -430,7 +549,7 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_0_INTO_STATIC, 3},
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
DPU_INTR_DSICMD_0_OUTOF_STATIC, 3},
- /* irq_idx: 100-103 */
+ /* irq_idx: 196-199 */
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
DPU_INTR_DSICMD_1_INTO_STATIC, 3},
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
@@ -439,39 +558,71 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_2_INTO_STATIC, 3},
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
DPU_INTR_DSICMD_2_OUTOF_STATIC, 3},
- /* irq_idx: 104-107 */
+ /* irq_idx: 200-203 */
{ DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
- /* irq_idx: 108-111 */
+ /* irq_idx: 204-207 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ /* irq_idx: 208-211 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
- /* irq_idx: 112-115 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ /* irq_idx: 212-215 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
- /* irq_idx: 116-119 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ /* irq_idx: 216-219 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
- /* irq_idx: 120-123 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ /* irq_idx: 220-223 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
- /* irq_idx: 124-127 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ /* irq_idx: 224-255 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
-
- /* BEGIN MAP_RANGE: 128-159 INTF_1_INTR */
- /* irq_idx: 128-131 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 3},
+ /* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */
+ /* irq_idx: 256-259 */
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
DPU_INTR_VIDEO_INTO_STATIC, 4},
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
@@ -480,7 +631,7 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_0_INTO_STATIC, 4},
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
DPU_INTR_DSICMD_0_OUTOF_STATIC, 4},
- /* irq_idx: 132-135 */
+ /* irq_idx: 260-263 */
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
DPU_INTR_DSICMD_1_INTO_STATIC, 4},
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
@@ -489,39 +640,71 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_2_INTO_STATIC, 4},
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
DPU_INTR_DSICMD_2_OUTOF_STATIC, 4},
- /* irq_idx: 136-139 */
+ /* irq_idx: 264-267 */
{ DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
- /* irq_idx: 140-143 */
+ /* irq_idx: 268-271 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
- /* irq_idx: 144-147 */
+ /* irq_idx: 272-275 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
- /* irq_idx: 148-151 */
+ /* irq_idx: 276-279 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
- /* irq_idx: 152-155 */
+ /* irq_idx: 280-283 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
- /* irq_idx: 156-159 */
+ /* irq_idx: 284-287 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
-
- /* BEGIN MAP_RANGE: 160-191 INTF_2_INTR */
- /* irq_idx: 160-163 */
+ /* irq_idx: 288-319 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 4},
+ /* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */
+ /* irq_idx: 320-323 */
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2,
DPU_INTR_VIDEO_INTO_STATIC, 5},
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2,
@@ -530,7 +713,7 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_0_INTO_STATIC, 5},
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2,
DPU_INTR_DSICMD_0_OUTOF_STATIC, 5},
- /* irq_idx: 164-167 */
+ /* irq_idx: 324-327 */
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2,
DPU_INTR_DSICMD_1_INTO_STATIC, 5},
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2,
@@ -539,39 +722,71 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_2_INTO_STATIC, 5},
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2,
DPU_INTR_DSICMD_2_OUTOF_STATIC, 5},
- /* irq_idx: 168-171 */
+ /* irq_idx: 328-331 */
{ DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
- /* irq_idx: 172-175 */
+ /* irq_idx: 332-335 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
- /* irq_idx: 176-179 */
+ /* irq_idx: 336-339 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
- /* irq_idx: 180-183 */
+ /* irq_idx: 340-343 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
- /* irq_idx: 184-187 */
+ /* irq_idx: 344-347 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
- /* irq_idx: 188-191 */
+ /* irq_idx: 348-351 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
-
- /* BEGIN MAP_RANGE: 192-223 INTF_3_INTR */
- /* irq_idx: 192-195 */
+ /* irq_idx: 352-383 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 5},
+ /* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */
+ /* irq_idx: 384-387 */
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3,
DPU_INTR_VIDEO_INTO_STATIC, 6},
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3,
@@ -580,7 +795,7 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_0_INTO_STATIC, 6},
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3,
DPU_INTR_DSICMD_0_OUTOF_STATIC, 6},
- /* irq_idx: 196-199 */
+ /* irq_idx: 388-391 */
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3,
DPU_INTR_DSICMD_1_INTO_STATIC, 6},
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3,
@@ -589,39 +804,71 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_2_INTO_STATIC, 6},
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3,
DPU_INTR_DSICMD_2_OUTOF_STATIC, 6},
- /* irq_idx: 200-203 */
+ /* irq_idx: 392-395 */
{ DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
- /* irq_idx: 204-207 */
+ /* irq_idx: 396-399 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
- /* irq_idx: 208-211 */
+ /* irq_idx: 400-403 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
- /* irq_idx: 212-215 */
+ /* irq_idx: 404-407 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
- /* irq_idx: 216-219 */
+ /* irq_idx: 408-411 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
- /* irq_idx: 220-223 */
+ /* irq_idx: 412-415 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
-
- /* BEGIN MAP_RANGE: 224-255 INTF_4_INTR */
- /* irq_idx: 224-227 */
+ /* irq_idx: 416-447*/
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 6},
+ /* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */
+ /* irq_idx: 448-451 */
{ DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4,
DPU_INTR_VIDEO_INTO_STATIC, 7},
{ DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4,
@@ -630,7 +877,7 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_0_INTO_STATIC, 7},
{ DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4,
DPU_INTR_DSICMD_0_OUTOF_STATIC, 7},
- /* irq_idx: 228-231 */
+ /* irq_idx: 452-455 */
{ DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4,
DPU_INTR_DSICMD_1_INTO_STATIC, 7},
{ DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4,
@@ -639,130 +886,474 @@ static const struct dpu_irq_type dpu_irq_map[] = {
DPU_INTR_DSICMD_2_INTO_STATIC, 7},
{ DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4,
DPU_INTR_DSICMD_2_OUTOF_STATIC, 7},
- /* irq_idx: 232-235 */
+ /* irq_idx: 456-459 */
{ DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
- /* irq_idx: 236-239 */
+ /* irq_idx: 460-463 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
- /* irq_idx: 240-243 */
+ /* irq_idx: 464-467 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
- /* irq_idx: 244-247 */
+ /* irq_idx: 468-471 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
- /* irq_idx: 248-251 */
+ /* irq_idx: 472-475 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
- /* irq_idx: 252-255 */
+ /* irq_idx: 476-479 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
-
- /* BEGIN MAP_RANGE: 256-287 AD4_0_INTR */
- /* irq_idx: 256-259 */
+ /* irq_idx: 480-511 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 7},
+ /* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */
+ /* irq_idx: 512-515 */
{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
- /* irq_idx: 260-263 */
+ /* irq_idx: 516-519 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
- /* irq_idx: 264-267 */
+ /* irq_idx: 520-523 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
- /* irq_idx: 268-271 */
+ /* irq_idx: 524-527 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
- /* irq_idx: 272-275 */
+ /* irq_idx: 528-531 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
- /* irq_idx: 276-279 */
+ /* irq_idx: 532-535 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
- /* irq_idx: 280-283 */
+ /* irq_idx: 536-539 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
- /* irq_idx: 284-287 */
+ /* irq_idx: 540-543 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
-
- /* BEGIN MAP_RANGE: 288-319 AD4_1_INTR */
- /* irq_idx: 288-291 */
+ /* irq_idx: 544-575*/
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 8},
+ /* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */
+ /* irq_idx: 576-579 */
{ DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
- /* irq_idx: 292-295 */
+ /* irq_idx: 580-583 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ /* irq_idx: 584-587 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
- /* irq_idx: 296-299 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ /* irq_idx: 588-591 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
- /* irq_idx: 300-303 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ /* irq_idx: 592-595 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
- /* irq_idx: 304-307 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ /* irq_idx: 596-599 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
- /* irq_idx: 308-311 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ /* irq_idx: 600-603 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
- /* irq_idx: 312-315 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ /* irq_idx: 604-607 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
- /* irq_idx: 315-319 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ /* irq_idx: 608-639 */
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
{ DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 9},
+ /* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */
+ /* irq_idx: 640-643 */
+ { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0,
+ DPU_INTR_VIDEO_INTO_STATIC, 10},
+ { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0,
+ DPU_INTR_VIDEO_OUTOF_STATIC, 10},
+ { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0,
+ DPU_INTR_DSICMD_0_INTO_STATIC, 10},
+ { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0,
+ DPU_INTR_DSICMD_0_OUTOF_STATIC, 10},
+ /* irq_idx: 644-647 */
+ { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0,
+ DPU_INTR_DSICMD_1_INTO_STATIC, 10},
+ { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0,
+ DPU_INTR_DSICMD_1_OUTOF_STATIC, 10},
+ { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0,
+ DPU_INTR_DSICMD_2_INTO_STATIC, 10},
+ { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0,
+ DPU_INTR_DSICMD_2_OUTOF_STATIC, 10},
+ /* irq_idx: 648-651 */
+ { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ /* irq_idx: 652-655 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ /* irq_idx: 656-659 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ /* irq_idx: 660-663 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ /* irq_idx: 664-667 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ /* irq_idx: 668-671 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ /* irq_idx: 672-703 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 10},
+ /* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */
+ /* irq_idx: 704-707 */
+ { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1,
+ DPU_INTR_VIDEO_INTO_STATIC, 11},
+ { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1,
+ DPU_INTR_VIDEO_OUTOF_STATIC, 11},
+ { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1,
+ DPU_INTR_DSICMD_0_INTO_STATIC, 11},
+ { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1,
+ DPU_INTR_DSICMD_0_OUTOF_STATIC, 11},
+ /* irq_idx: 708-711 */
+ { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1,
+ DPU_INTR_DSICMD_1_INTO_STATIC, 11},
+ { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1,
+ DPU_INTR_DSICMD_1_OUTOF_STATIC, 11},
+ { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1,
+ DPU_INTR_DSICMD_2_INTO_STATIC, 11},
+ { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1,
+ DPU_INTR_DSICMD_2_OUTOF_STATIC, 11},
+ /* irq_idx: 712-715 */
+ { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ /* irq_idx: 716-719 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ /* irq_idx: 720-723 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ /* irq_idx: 724-727 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ /* irq_idx: 728-731 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ /* irq_idx: 732-735 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ /* irq_idx: 736-767 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 11},
+ /* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */
+ /* irq_idx: 768-771 */
+ { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5,
+ DPU_INTR_VIDEO_INTO_STATIC, 12},
+ { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5,
+ DPU_INTR_VIDEO_OUTOF_STATIC, 12},
+ { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5,
+ DPU_INTR_DSICMD_0_INTO_STATIC, 12},
+ { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5,
+ DPU_INTR_DSICMD_0_OUTOF_STATIC, 12},
+ /* irq_idx: 772-775 */
+ { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5,
+ DPU_INTR_DSICMD_1_INTO_STATIC, 12},
+ { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5,
+ DPU_INTR_DSICMD_1_OUTOF_STATIC, 12},
+ { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5,
+ DPU_INTR_DSICMD_2_INTO_STATIC, 12},
+ { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5,
+ DPU_INTR_DSICMD_2_OUTOF_STATIC, 12},
+ /* irq_idx: 776-779 */
+ { DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ /* irq_idx: 780-783 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ /* irq_idx: 784-787 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ /* irq_idx: 788-791 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ /* irq_idx: 792-795 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ /* irq_idx: 796-799 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ /* irq_idx: 800-831 */
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
+ { DPU_IRQ_TYPE_RESERVED, 0, 0, 12},
};
-static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type intr_type,
- u32 instance_idx)
+static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr,
+ enum dpu_intr_type intr_type, u32 instance_idx)
{
int i;
for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) {
if (intr_type == dpu_irq_map[i].intr_type &&
- instance_idx == dpu_irq_map[i].instance_idx)
+ instance_idx == dpu_irq_map[i].instance_idx &&
+ !(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type)))
return i;
}
@@ -795,11 +1386,11 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
irq_status = intr->save_irq_status[reg_idx];
/*
- * Each Interrupt register has a range of 32 indexes, and
+ * Each Interrupt register has a range of 64 indexes, and
* that is static for dpu_irq_map.
*/
- start_idx = reg_idx * 32;
- end_idx = start_idx + 32;
+ start_idx = reg_idx * 64;
+ end_idx = start_idx + 64;
if (!test_bit(reg_idx, &intr->irq_mask) ||
start_idx >= ARRAY_SIZE(dpu_irq_map))
@@ -814,7 +1405,9 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
(irq_idx < end_idx) && irq_status;
irq_idx++)
if ((irq_status & dpu_irq_map[irq_idx].irq_mask) &&
- (dpu_irq_map[irq_idx].reg_idx == reg_idx)) {
+ (dpu_irq_map[irq_idx].reg_idx == reg_idx) &&
+ !(intr->obsolete_irq &
+ BIT(dpu_irq_map[irq_idx].intr_type))) {
/*
* Once a match on irq mask, perform a callback
* to the given cbfunc. cbfunc will take care
@@ -1126,6 +1719,8 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
}
intr->irq_mask = m->mdss_irqs;
+ intr->obsolete_irq = m->obsolete_irq;
+
spin_lock_init(&intr->irq_lock);
return intr;
generated by cgit (git 2.34.1) at 2024-06-20 10:30:44 +0000