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path: root/drivers/gpu/drm/nouveau/nv10_fb.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_fb.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv10_fb.c103
1 files changed, 0 insertions, 103 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_fb.c b/drivers/gpu/drm/nouveau/nv10_fb.c
deleted file mode 100644
index 510e90f34482..000000000000
--- a/drivers/gpu/drm/nouveau/nv10_fb.c
+++ /dev/null
@@ -1,103 +0,0 @@
-#include <drm/drmP.h>
-#include "nouveau_drv.h"
-#include <drm/nouveau_drm.h>
-
-void
-nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
- uint32_t size, uint32_t pitch, uint32_t flags)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
-
- tile->addr = 0x80000000 | addr;
- tile->limit = max(1u, addr + size) - 1;
- tile->pitch = pitch;
-}
-
-void
-nv10_fb_free_tile_region(struct drm_device *dev, int i)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
-
- tile->addr = tile->limit = tile->pitch = tile->zcomp = 0;
-}
-
-void
-nv10_fb_set_tile_region(struct drm_device *dev, int i)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
-
- nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
- nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
- nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
-}
-
-int
-nv1a_fb_vram_init(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct pci_dev *bridge;
- uint32_t mem, mib;
-
- bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
- if (!bridge) {
- NV_ERROR(dev, "no bridge device\n");
- return 0;
- }
-
- if (dev_priv->chipset == 0x1a) {
- pci_read_config_dword(bridge, 0x7c, &mem);
- mib = ((mem >> 6) & 31) + 1;
- } else {
- pci_read_config_dword(bridge, 0x84, &mem);
- mib = ((mem >> 4) & 127) + 1;
- }
-
- dev_priv->vram_size = mib * 1024 * 1024;
- return 0;
-}
-
-int
-nv10_fb_vram_init(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- u32 fifo_data = nv_rd32(dev, NV04_PFB_FIFO_DATA);
- u32 cfg0 = nv_rd32(dev, 0x100200);
-
- dev_priv->vram_size = fifo_data & NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
-
- if (cfg0 & 0x00000001)
- dev_priv->vram_type = NV_MEM_TYPE_DDR1;
- else
- dev_priv->vram_type = NV_MEM_TYPE_SDRAM;
-
- return 0;
-}
-
-int
-nv10_fb_init(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
- int i;
-
- /* Turn all the tiling regions off. */
- pfb->num_tiles = NV10_PFB_TILE__SIZE;
- for (i = 0; i < pfb->num_tiles; i++)
- pfb->set_tile_region(dev, i);
-
- return 0;
-}
-
-void
-nv10_fb_takedown(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
- int i;
-
- for (i = 0; i < pfb->num_tiles; i++)
- pfb->free_tile_region(dev, i);
-}