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path: root/drivers/gpu/drm/tegra/fb.c
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Diffstat (limited to 'drivers/gpu/drm/tegra/fb.c')
-rw-r--r--drivers/gpu/drm/tegra/fb.c35
1 files changed, 29 insertions, 6 deletions
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
index 80540c1c66dc..406e895d82cc 100644
--- a/drivers/gpu/drm/tegra/fb.c
+++ b/drivers/gpu/drm/tegra/fb.c
@@ -54,17 +54,40 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
struct tegra_fb *fb = to_tegra_fb(framebuffer);
uint64_t modifier = fb->base.modifier;
- switch (fourcc_mod_tegra_mod(modifier)) {
- case NV_FORMAT_MOD_TEGRA_TILED:
+ switch (modifier) {
+ case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
tiling->mode = TEGRA_BO_TILING_MODE_TILED;
tiling->value = 0;
break;
- case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
+ case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
- tiling->value = fourcc_mod_tegra_param(modifier);
- if (tiling->value > 5)
- return -EINVAL;
+ tiling->value = 0;
+ break;
+
+ case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
+ tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+ tiling->value = 1;
+ break;
+
+ case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
+ tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+ tiling->value = 2;
+ break;
+
+ case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
+ tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+ tiling->value = 3;
+ break;
+
+ case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
+ tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+ tiling->value = 4;
+ break;
+
+ case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
+ tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+ tiling->value = 5;
break;
default: