diff options
Diffstat (limited to 'drivers/gpu')
228 files changed, 11139 insertions, 1507 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index d0aa6cff2e02..4bffa08f610a 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -389,6 +389,8 @@ source "drivers/gpu/drm/aspeed/Kconfig" source "drivers/gpu/drm/mcde/Kconfig" +source "drivers/gpu/drm/tidss/Kconfig" + # Keep legacy drivers last menuconfig DRM_LEGACY diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 6493088a0fdd..ca0ca775d37f 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -122,3 +122,4 @@ obj-$(CONFIG_DRM_LIMA) += lima/ obj-$(CONFIG_DRM_PANFROST) += panfrost/ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/ obj-$(CONFIG_DRM_MCDE) += mcde/ +obj-$(CONFIG_DRM_TIDSS) += tidss/ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 39cd545976b7..53fdafd85cb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1136,7 +1136,7 @@ static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) * locking inversion with the driver load path. And the access here is * completely racy anyway. So don't bother with locking for now. */ - return dev->open_count == 0; + return atomic_read(&dev->open_count) == 0; } static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a9c4edca70c9..94e2fd758e01 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -1004,7 +1004,7 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, /* Renoir */ - {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, /* Navi12 */ {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c index 07914e34bc25..1311d6aec5d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c @@ -52,7 +52,7 @@ static int amdgpu_perf_event_init(struct perf_event *event) return -ENOENT; /* update the hw_perf_event struct with config data */ - hwc->conf = event->attr.config; + hwc->config = event->attr.config; return 0; } @@ -74,9 +74,9 @@ static void amdgpu_perf_start(struct perf_event *event, int flags) switch (pe->pmu_perf_type) { case PERF_TYPE_AMDGPU_DF: if (!(flags & PERF_EF_RELOAD)) - pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1); + pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 1); - pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 0); + pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 0); break; default: break; @@ -101,7 +101,7 @@ static void amdgpu_perf_read(struct perf_event *event) switch (pe->pmu_perf_type) { case PERF_TYPE_AMDGPU_DF: - pe->adev->df.funcs->pmc_get_count(pe->adev, hwc->conf, + pe->adev->df.funcs->pmc_get_count(pe->adev, hwc->config, &count); break; default: @@ -126,7 +126,7 @@ static void amdgpu_perf_stop(struct perf_event *event, int flags) switch (pe->pmu_perf_type) { case PERF_TYPE_AMDGPU_DF: - pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 0); + pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, 0); break; default: break; @@ -156,7 +156,8 @@ static int amdgpu_perf_add(struct perf_event *event, int flags) switch (pe->pmu_perf_type) { case PERF_TYPE_AMDGPU_DF: - retval = pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1); + retval = pe->adev->df.funcs->pmc_start(pe->adev, + hwc->config, 1); break; default: return 0; @@ -184,7 +185,7 @@ static void amdgpu_perf_del(struct perf_event *event, int flags) switch (pe->pmu_perf_type) { case PERF_TYPE_AMDGPU_DF: - pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 1); + pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, 1); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index dee446278417..3ab46d4647e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -69,11 +69,6 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo, static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev); -static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) -{ - return 0; -} - /** * amdgpu_init_mem_type - Initialize a memory manager for a specific type of * memory request. @@ -1638,7 +1633,6 @@ static struct ttm_bo_driver amdgpu_bo_driver = { .ttm_tt_create = &amdgpu_ttm_tt_create, .ttm_tt_populate = &amdgpu_ttm_tt_populate, .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, - .invalidate_caches = &amdgpu_invalidate_caches, .init_mem_type = &amdgpu_init_mem_type, .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, .evict_flags = &amdgpu_evict_flags, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index d6deb0eb1e15..6fe057329de2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -179,6 +179,7 @@ struct amdgpu_vcn_inst { struct amdgpu_irq_src irq; struct amdgpu_vcn_reg external; struct amdgpu_bo *dpg_sram_bo; + struct dpg_pause_state pause_state; void *dpg_sram_cpu_addr; uint64_t dpg_sram_gpu_addr; uint32_t *dpg_sram_curr_addr; @@ -190,8 +191,6 @@ struct amdgpu_vcn { const struct firmware *fw; /* VCN firmware */ unsigned num_enc_rings; enum amd_powergating_state cur_state; - struct dpg_pause_state pause_state; - bool indirect_sram; uint8_t num_vcn_inst; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 90f64b8bc358..b33a4eb39193 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4374,9 +4374,17 @@ static int gfx_v9_0_ecc_late_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; - r = gfx_v9_0_do_edc_gds_workarounds(adev); - if (r) - return r; + /* + * Temp workaround to fix the issue that CP firmware fails to + * update read pointer when CPDMA is writing clearing operation + * to GDS in suspend/resume sequence on several cards. So just + * limit this operation in cold boot sequence. + */ + if (!adev->in_suspend) { + r = gfx_v9_0_do_edc_gds_workarounds(adev); + if (r) + return r; + } /* requires IBs so do in late init after IB pool is initialized */ r = gfx_v9_0_do_edc_gpr_workarounds(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 1a24fadd30e2..71f61afdc655 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1207,9 +1207,10 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, struct amdgpu_ring *ring; /* pause/unpause if state is changed */ - if (adev->vcn.pause_state.fw_based != new_state->fw_based) { + if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", - adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, + adev->vcn.inst[inst_idx].pause_state.fw_based, + adev->vcn.inst[inst_idx].pause_state.jpeg, new_state->fw_based, new_state->jpeg); reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & @@ -1258,13 +1259,14 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); } - adev->vcn.pause_state.fw_based = new_state->fw_based; + adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; } /* pause/unpause if state is changed */ - if (adev->vcn.pause_state.jpeg != new_state->jpeg) { + if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", - adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, + adev->vcn.inst[inst_idx].pause_state.fw_based, + adev->vcn.inst[inst_idx].pause_state.jpeg, new_state->fw_based, new_state->jpeg); reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & @@ -1318,7 +1320,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); } - adev->vcn.pause_state.jpeg = new_state->jpeg; + adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 4f7216788f11..c387c81f8695 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -1137,9 +1137,9 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, int ret_code; /* pause/unpause if state is changed */ - if (adev->vcn.pause_state.fw_based != new_state->fw_based) { + if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { DRM_DEBUG("dpg pause state changed %d -> %d", - adev->vcn.pause_state.fw_based, new_state->fw_based); + adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); @@ -1185,7 +1185,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); } - adev->vcn.pause_state.fw_based = new_state->fw_based; + adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 70fae7977f8f..2d64ba1adf99 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1367,9 +1367,9 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, int ret_code; /* pause/unpause if state is changed */ - if (adev->vcn.pause_state.fw_based != new_state->fw_based) { + if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { DRM_DEBUG("dpg pause state changed %d -> %d", - adev->vcn.pause_state.fw_based, new_state->fw_based); + adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) & (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); @@ -1407,14 +1407,14 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, RREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF); SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS, - 0x0, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); } } else { /* unpause dpg, no need to wait */ reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data); } - adev->vcn.pause_state.fw_based = new_state->fw_based; + adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; } return 0; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 279541517a99..63e8a12a74bc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8408,7 +8408,6 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) /* Calculate number of static frames before generating interrupt to * enter PSR. */ - unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; // Init fail safe of 2 frames static unsigned int num_frames_static = 2; @@ -8423,8 +8422,10 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) * Calculate number of frames such that at least 30 ms of time has * passed. */ - if (vsync_rate_hz != 0) + if (vsync_rate_hz != 0) { + unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; num_frames_static = (30000 / frame_time_microsec) + 1; + } params.triggers.cursor_update = true; params.triggers.overlay_update = true; diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c index 629a07a2719b..c4ba6e84db65 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c @@ -711,10 +711,6 @@ static void enable_disp_power_gating_dmcub( power_gating.header.sub_type = DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING; power_gating.power_gating.pwr = *pwr; - /* ATOM_ENABLE is old API in DMUB */ - if (power_gating.power_gating.pwr.enable == ATOM_ENABLE) - power_gating.power_gating.pwr.enable = ATOM_INIT; - dc_dmub_srv_cmd_queue(dmcub, &power_gating.header); dc_dmub_srv_cmd_execute(dmcub); dc_dmub_srv_wait_idle(dmcub); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile index 3cd283195091..c0f6a8c7de7d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile @@ -87,6 +87,12 @@ AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20) ############################################################################### CLK_MGR_DCN21 = rn_clk_mgr.o rn_clk_mgr_vbios_smu.o +# prevent build errors regarding soft-float vs hard-float FP ABI tags +# this code is currently unused on ppc64, as it applies to Renoir APUs only +ifdef CONFIG_PPC64 +CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute) +endif + AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21)) AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index 495f01e9f2ca..49ce46b543ea 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -117,7 +117,7 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; - if (safe_to_lower || prev_dppclk_khz < dppclk_khz) { + if ((prev_dppclk_khz > dppclk_khz && safe_to_lower) || prev_dppclk_khz < dppclk_khz) { clk_mgr->dccg->funcs->update_dpp_dto( clk_mgr->dccg, dpp_inst, dppclk_khz); } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 7ae4c06232dd..9ef3f7b91a1d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -151,6 +151,12 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); } + // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. + if (!IS_DIAG_DC(dc->ctx->dce_environment)) { + if (new_clocks->dppclk_khz < 100000) + new_clocks->dppclk_khz = 100000; + } + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) dpp_clock_lowered = true; @@ -412,19 +418,19 @@ void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_ra ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; - /* We will not select WM based on dcfclk, so leave it as unconstrained */ - ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; - ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; - /* fclk wil be used to select WM*/ + /* We will not select WM based on fclk, so leave it as unconstrained */ + ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; + ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; + /* dcfclk wil be used to select WM*/ if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) { if (i == 0) - ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0; + ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0; else { /* add 1 to make it non-overlapping with next lvl */ - ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1; + ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; } - ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz; + ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; } else { /* unconstrained for memory retraining */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index f1a5d2c6aa37..68c4049cbc2a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -400,7 +400,7 @@ static bool acquire( { enum gpio_result result; - if (!is_engine_available(engine)) + if ((engine == NULL) || !is_engine_available(engine)) return false; result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index cfbbaffa8654..a444fed94184 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -572,7 +572,6 @@ void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) dpp->funcs->dpp_dppclk_control(dpp, false, false); hubp->power_gated = true; - dc->optimized_required = false; /* We're powering off, no need to optimize */ hws->funcs.plane_atomic_power_down(dc, pipe_ctx->plane_res.dpp, diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index 0d506d30d6b6..33d0a176841a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -60,6 +60,7 @@ #include "dcn20/dcn20_dccg.h" #include "dcn21_hubbub.h" #include "dcn10/dcn10_resource.h" +#include "dce110/dce110_resource.h" #include "dcn20/dcn20_dwb.h" #include "dcn20/dcn20_mmhubbub.h" @@ -856,6 +857,7 @@ static const struct dc_debug_options debug_defaults_diags = { enum dcn20_clk_src_array_id { DCN20_CLK_SRC_PLL0, DCN20_CLK_SRC_PLL1, + DCN20_CLK_SRC_PLL2, DCN20_CLK_SRC_TOTAL_DCN21 }; @@ -1718,6 +1720,10 @@ static bool dcn21_resource_construct( dcn21_clock_source_create(ctx, ctx->dc_bios, CLOCK_SOURCE_COMBO_PHY_PLL1, &clk_src_regs[1], false); + pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = + dcn21_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL2, + &clk_src_regs[2], false); pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h index b2f96a101124..7a63cf8e85ed 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h @@ -39,21 +39,39 @@ #define SMU_11_0_PP_OVERDRIVE_VERSION 0x0800 #define SMU_11_0_PP_POWERSAVINGCLOCK_VERSION 0x0100 +enum SMU_11_0_ODFEATURE_CAP { + SMU_11_0_ODCAP_GFXCLK_LIMITS = 0, + SMU_11_0_ODCAP_GFXCLK_CURVE, + SMU_11_0_ODCAP_UCLK_MAX, + SMU_11_0_ODCAP_POWER_LIMIT, + SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT, + SMU_11_0_ODCAP_FAN_SPEED_MIN, + SMU_11_0_ODCAP_TEMPERATURE_FAN, + SMU_11_0_ODCAP_TEMPERATURE_SYSTEM, + SMU_11_0_ODCAP_MEMORY_TIMING_TUNE, + SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL, + SMU_11_0_ODCAP_AUTO_UV_ENGINE, + SMU_11_0_ODCAP_AUTO_OC_ENGINE, + SMU_11_0_ODCAP_AUTO_OC_MEMORY, + SMU_11_0_ODCAP_FAN_CURVE, + SMU_11_0_ODCAP_COUNT, +}; + enum SMU_11_0_ODFEATURE_ID { - SMU_11_0_ODFEATURE_GFXCLK_LIMITS = 1 << 0, //GFXCLK Limit feature - SMU_11_0_ODFEATURE_GFXCLK_CURVE = 1 << 1, //GFXCLK Curve feature - SMU_11_0_ODFEATURE_UCLK_MAX = 1 << 2, //UCLK Limit feature - SMU_11_0_ODFEATURE_POWER_LIMIT = 1 << 3, //Power Limit feature - SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << 4, //Fan Acoustic RPM feature - SMU_11_0_ODFEATURE_FAN_SPEED_MIN = 1 << 5, //Minimum Fan Speed feature - SMU_11_0_ODFEATURE_TEMPERATURE_FAN = 1 << 6, //Fan Target Temperature Limit feature - SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM = 1 << 7, //Operating Temperature Limit feature - SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE = 1 << 8, //AC Timing Tuning feature - SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << 9, //Zero RPM feature - SMU_11_0_ODFEATURE_AUTO_UV_ENGINE = 1 << 10, //Auto Under Volt GFXCLK feature - SMU_11_0_ODFEATURE_AUTO_OC_ENGINE = 1 << 11, //Auto Over Clock GFXCLK feature - SMU_11_0_ODFEATURE_AUTO_OC_MEMORY = 1 << 12, //Auto Over Clock MCLK feature - SMU_11_0_ODFEATURE_FAN_CURVE = 1 << 13, //VICTOR TODO + SMU_11_0_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_11_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature + SMU_11_0_ODFEATURE_GFXCLK_CURVE = 1 << SMU_11_0_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature + SMU_11_0_ODFEATURE_UCLK_MAX = 1 << SMU_11_0_ODCAP_UCLK_MAX, //UCLK Limit feature + SMU_11_0_ODFEATURE_POWER_LIMIT = 1 << SMU_11_0_ODCAP_POWER_LIMIT, //Power Limit feature + SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature + SMU_11_0_ODFEATURE_FAN_SPEED_MIN = 1 << SMU_11_0_ODCAP_FAN_SPEED_MIN, //Minimum Fan Speed feature + SMU_11_0_ODFEATURE_TEMPERATURE_FAN = 1 << SMU_11_0_ODCAP_TEMPERATURE_FAN, //Fan Target Temperature Limit feature + SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM = 1 << SMU_11_0_ODCAP_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature + SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE = 1 << SMU_11_0_ODCAP_MEMORY_TIMING_TUNE, //AC Timing Tuning feature + SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL, //Zero RPM feature + SMU_11_0_ODFEATURE_AUTO_UV_ENGINE = 1 << SMU_11_0_ODCAP_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature + SMU_11_0_ODFEATURE_AUTO_OC_ENGINE = 1 << SMU_11_0_ODCAP_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature + SMU_11_0_ODFEATURE_AUTO_OC_MEMORY = 1 << SMU_11_0_ODCAP_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature + SMU_11_0_ODFEATURE_FAN_CURVE = 1 << SMU_11_0_ODCAP_FAN_CURVE, //Fan Curve feature SMU_11_0_ODFEATURE_COUNT = 14, }; #define SMU_11_0_MAX_ODFEATURE 32 //Maximum Number of OD Features diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 19a9846b730e..0d73a49166af 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -736,9 +736,9 @@ static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu return dpm_desc->SnapToDiscrete == 0 ? true : false; } -static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature) +static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) { - return od_table->cap[feature]; + return od_table->cap[cap]; } static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table, @@ -846,7 +846,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, case SMU_OD_SCLK: if (!smu->od_enabled || !od_table || !od_settings) break; - if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) + if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) break; size += sprintf(buf + size, "OD_SCLK:\n"); size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax); @@ -854,7 +854,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, case SMU_OD_MCLK: if (!smu->od_enabled || !od_table || !od_settings) break; - if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) + if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) break; size += sprintf(buf + size, "OD_MCLK:\n"); size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax); @@ -862,7 +862,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, case SMU_OD_VDDC_CURVE: if (!smu->od_enabled || !od_table || !od_settings) break; - if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) + if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) break; size += sprintf(buf + size, "OD_VDDC_CURVE:\n"); for (i = 0; i < 3; i++) { @@ -887,7 +887,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, break; size = sprintf(buf, "%s:\n", "OD_RANGE"); - if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) { + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, &min_value, NULL); navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, @@ -896,14 +896,14 @@ static int navi10_print_clk_levels(struct smu_context *smu, min_value, max_value); } - if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) { + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, &min_value, &max_value); size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", min_value, max_value); } - if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) { + if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, &min_value, &max_value); size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", @@ -2056,7 +2056,7 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL switch (type) { case PP_OD_EDIT_SCLK_VDDC_TABLE: - if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) { + if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { pr_warn("GFXCLK_LIMITS not supported!\n"); return -ENOTSUPP; } @@ -2102,7 +2102,7 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL } break; case PP_OD_EDIT_MCLK_VDDC_TABLE: - if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) { + if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { pr_warn("UCLK_MAX not supported!\n"); return -ENOTSUPP; } @@ -2143,7 +2143,7 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL } break; case PP_OD_EDIT_VDDC_CURVE: - if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) { + if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { pr_warn("GFXCLK_CURVE not supported!\n"); return -ENOTSUPP; } diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c b/drivers/gpu/drm/arc/arcpgu_crtc.c index 8ae1e1f97a73..be7c29cec318 100644 --- a/drivers/gpu/drm/arc/arcpgu_crtc.c +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c @@ -9,7 +9,6 @@ #include <drm/drm_device.h> #include <drm/drm_fb_cma_helper.h> #include <drm/drm_gem_cma_helper.h> -#include <drm/drm_vblank.h> #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> #include <linux/clk.h> @@ -138,24 +137,9 @@ static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc, ~ARCPGU_CTRL_ENABLE_MASK); } -static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc, - struct drm_crtc_state *state) -{ - struct drm_pending_vblank_event *event = crtc->state->event; - - if (event) { - crtc->state->event = NULL; - - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, event); - spin_unlock_irq(&crtc->dev->event_lock); - } -} - static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = { .mode_valid = arc_pgu_crtc_mode_valid, .mode_set_nofb = arc_pgu_crtc_mode_set_nofb, - .atomic_begin = arc_pgu_crtc_atomic_begin, .atomic_enable = arc_pgu_crtc_atomic_enable, .atomic_disable = arc_pgu_crtc_atomic_disable, }; diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index b79f484e9bd2..18a0a4ce00f6 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -388,31 +388,9 @@ static int ast_get_dram_info(struct drm_device *dev) return 0; } -enum drm_mode_status ast_mode_config_mode_valid(struct drm_device *dev, - const struct drm_display_mode *mode) -{ - static const unsigned long max_bpp = 4; /* DRM_FORMAT_XRGBA8888 */ - - struct ast_private *ast = dev->dev_private; - unsigned long fbsize, fbpages, max_fbpages; - - /* To support double buffering, a framebuffer may not - * consume more than half of the available VRAM. - */ - max_fbpages = (ast->vram_size / 2) >> PAGE_SHIFT; - - fbsize = mode->hdisplay * mode->vdisplay * max_bpp; - fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); - - if (fbpages > max_fbpages) - return MODE_MEM; - - return MODE_OK; -} - static const struct drm_mode_config_funcs ast_mode_funcs = { .fb_create = drm_gem_fb_create, - .mode_valid = ast_mode_config_mode_valid, + .mode_valid = drm_vram_helper_mode_valid, .atomic_check = drm_atomic_helper_check, .atomic_commit = drm_atomic_helper_commit, }; diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index 34608f0499eb..7810a84e7e9e 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -833,8 +833,6 @@ static void ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode_info; struct drm_display_mode *adjusted_mode; - crtc->state->no_vblank = true; - ast_state = to_ast_crtc_state(crtc->state); format = ast_state->format; diff --git a/drivers/gpu/drm/bochs/bochs_kms.c b/drivers/gpu/drm/bochs/bochs_kms.c index 3f0006c2470d..7410b0ea4623 100644 --- a/drivers/gpu/drm/bochs/bochs_kms.c +++ b/drivers/gpu/drm/bochs/bochs_kms.c @@ -7,7 +7,6 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_probe_helper.h> -#include <drm/drm_vblank.h> #include "bochs.h" @@ -57,16 +56,8 @@ static void bochs_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *old_state) { struct bochs_device *bochs = pipe->crtc.dev->dev_private; - struct drm_crtc *crtc = &pipe->crtc; bochs_plane_update(bochs, pipe->plane.state); - - if (crtc->state->event) { - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, crtc->state->event); - crtc->state->event = NULL; - spin_unlock_irq(&crtc->dev->event_lock); - } } static const struct drm_simple_display_pipe_funcs bochs_pipe_funcs = { @@ -92,32 +83,11 @@ static int bochs_connector_get_modes(struct drm_connector *connector) return count; } -static enum drm_mode_status bochs_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct bochs_device *bochs = - container_of(connector, struct bochs_device, connector); - unsigned long size = mode->hdisplay * mode->vdisplay * 4; - - /* - * Make sure we can fit two framebuffers into video memory. - * This allows up to 1600x1200 with 16 MB (default size). - * If you want more try this: - * 'qemu -vga std -global VGA.vgamem_mb=32 $otherargs' - */ - if (size * 2 > bochs->fb_size) - return MODE_BAD; - - return MODE_OK; -} - static const struct drm_connector_helper_funcs bochs_connector_connector_helper_funcs = { .get_modes = bochs_connector_get_modes, - .mode_valid = bochs_connector_mode_valid, }; static const struct drm_connector_funcs bochs_connector_connector_funcs = { - .dpms = drm_helper_connector_dpms, .fill_modes = drm_helper_probe_single_connector_modes, .destroy = drm_connector_cleanup, .reset = drm_atomic_helper_connector_reset, @@ -157,6 +127,7 @@ bochs_gem_fb_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_config_funcs bochs_mode_funcs = { .fb_create = bochs_gem_fb_create, + .mode_valid = drm_vram_helper_mode_valid, .atomic_check = drm_atomic_helper_check, .atomic_commit = drm_atomic_helper_commit, }; diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 0b9ca5862455..8397bf72d2f3 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -72,6 +72,17 @@ config DRM_PARADE_PS8622 ---help--- Parade eDP-LVDS bridge chip driver. +config DRM_PARADE_PS8640 + tristate "Parade PS8640 MIPI DSI to eDP Converter" + depends on OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + help + Choose this option if you have PS8640 for display + The PS8640 is a high-performance and low-power + MIPI DSI to eDP converter + config DRM_SIL_SII8620 tristate "Silicon Image SII8620 HDMI/MHL bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index cd16ce830270..1eb5376c5d68 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o +obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o obj-$(CONFIG_DRM_SII902X) += sii902x.o obj-$(CONFIG_DRM_SII9234) += sii9234.o diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 6effe532f820..dfb59a5fefea 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1289,19 +1289,21 @@ struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp, return conn_state->crtc; } -static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) +static void +analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) { + struct drm_atomic_state *old_state = old_bridge_state->base.state; struct analogix_dp_device *dp = bridge->driver_private; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; int ret; - crtc = analogix_dp_get_new_crtc(dp, state); + crtc = analogix_dp_get_new_crtc(dp, old_state); if (!crtc) return; - old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); + old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc); /* Don't touch the panel if we're coming back from PSR */ if (old_crtc_state && old_crtc_state->self_refresh_active) return; @@ -1366,20 +1368,22 @@ out_dp_clk_pre: return ret; } -static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) +static void +analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) { + struct drm_atomic_state *old_state = old_bridge_state->base.state; struct analogix_dp_device *dp = bridge->driver_private; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; int timeout_loop = 0; int ret; - crtc = analogix_dp_get_new_crtc(dp, state); + crtc = analogix_dp_get_new_crtc(dp, old_state); if (!crtc) return; - old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); + old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc); /* Not a full enable, just disable PSR and continue */ if (old_crtc_state && old_crtc_state->self_refresh_active) { ret = analogix_dp_disable_psr(dp); @@ -1440,18 +1444,20 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge) dp->dpms_mode = DRM_MODE_DPMS_OFF; } -static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) +static void +analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) { + struct drm_atomic_state *old_state = old_bridge_state->base.state; struct analogix_dp_device *dp = bridge->driver_private; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state = NULL; - crtc = analogix_dp_get_new_crtc(dp, state); + crtc = analogix_dp_get_new_crtc(dp, old_state); if (!crtc) goto out; - new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); + new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc); if (!new_crtc_state) goto out; @@ -1463,20 +1469,21 @@ out: analogix_dp_bridge_disable(bridge); } -static -void analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) +static void +analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) { + struct drm_atomic_state *old_state = old_bridge_state->base.state; struct analogix_dp_device *dp = bridge->driver_private; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; int ret; - crtc = analogix_dp_get_new_crtc(dp, state); + crtc = analogix_dp_get_new_crtc(dp, old_state); if (!crtc) return; - new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); + new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc); if (!new_crtc_state || !new_crtc_state->self_refresh_active) return; @@ -1563,6 +1570,9 @@ static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge, } static const struct drm_bridge_funcs analogix_dp_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable, .atomic_enable = analogix_dp_bridge_atomic_enable, .atomic_disable = analogix_dp_bridge_atomic_disable, diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c new file mode 100644 index 000000000000..c6c06688aff2 --- /dev/null +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -0,0 +1,348 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016 MediaTek Inc. + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/gpio/consumer.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_graph.h> +#include <linux/regulator/consumer.h> + +#include <drm/drm_bridge.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_of.h> +#include <drm/drm_panel.h> +#include <drm/drm_print.h> + +#define PAGE2_GPIO_H 0xa7 +#define PS_GPIO9 BIT(1) +#define PAGE2_I2C_BYPASS 0xea +#define I2C_BYPASS_EN 0xd0 +#define PAGE2_MCS_EN 0xf3 +#define MCS_EN BIT(0) +#define PAGE3_SET_ADD 0xfe +#define VDO_CTL_ADD 0x13 +#define VDO_DIS 0x18 +#define VDO_EN 0x1c +#define DP_NUM_LANES 4 + +/* + * PS8640 uses multiple addresses: + * page[0]: for DP control + * page[1]: for VIDEO Bridge + * page[2]: for control top + * page[3]: for DSI Link Control1 + * page[4]: for MIPI Phy + * page[5]: for VPLL + * page[6]: for DSI Link Control2 + * page[7]: for SPI ROM mapping + */ +enum page_addr_offset { + PAGE0_DP_CNTL = 0, + PAGE1_VDO_BDG, + PAGE2_TOP_CNTL, + PAGE3_DSI_CNTL1, + PAGE4_MIPI_PHY, + PAGE5_VPLL, + PAGE6_DSI_CNTL2, + PAGE7_SPI_CNTL, + MAX_DEVS +}; + +enum ps8640_vdo_control { + DISABLE = VDO_DIS, + ENABLE = VDO_EN, +}; + +struct ps8640 { + struct drm_bridge bridge; + struct drm_bridge *panel_bridge; + struct mipi_dsi_device *dsi; + struct i2c_client *page[MAX_DEVS]; + struct regulator_bulk_data supplies[2]; + struct gpio_desc *gpio_reset; + struct gpio_desc *gpio_powerdown; +}; + +static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) +{ + return container_of(e, struct ps8640, bridge); +} + +static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, + const enum ps8640_vdo_control ctrl) +{ + struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1]; + u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; + int ret; + + ret = i2c_smbus_write_i2c_block_data(client, PAGE3_SET_ADD, + sizeof(vdo_ctrl_buf), + vdo_ctrl_buf); + if (ret < 0) + return ret; + + return 0; +} + +static void ps8640_pre_enable(struct drm_bridge *bridge) +{ + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL]; + unsigned long timeout; + int ret, status; + + ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), + ps_bridge->supplies); + if (ret < 0) { + DRM_ERROR("cannot enable regulators %d\n", ret); + return; + } + + gpiod_set_value(ps_bridge->gpio_powerdown, 0); + gpiod_set_value(ps_bridge->gpio_reset, 1); + usleep_range(2000, 2500); + gpiod_set_value(ps_bridge->gpio_reset, 0); + + /* + * Wait for the ps8640 embedded MCU to be ready + * First wait 200ms and then check the MCU ready flag every 20ms + */ + msleep(200); + + timeout = jiffies + msecs_to_jiffies(200) + 1; + + while (time_is_after_jiffies(timeout)) { + status = i2c_smbus_read_byte_data(client, PAGE2_GPIO_H); + if (status < 0) { + DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", status); + goto err_regulators_disable; + } + if ((status & PS_GPIO9) == PS_GPIO9) + break; + + msleep(20); + } + + msleep(50); + + /* + * The Manufacturer Command Set (MCS) is a device dependent interface + * intended for factory programming of the display module default + * parameters. Once the display module is configured, the MCS shall be + * disabled by the manufacturer. Once disabled, all MCS commands are + * ignored by the display interface. + */ + status = i2c_smbus_read_byte_data(client, PAGE2_MCS_EN); + if (status < 0) { + DRM_ERROR("failed read PAGE2_MCS_EN: %d\n", status); + goto err_regulators_disable; + } + + ret = i2c_smbus_write_byte_data(client, PAGE2_MCS_EN, + status & ~MCS_EN); + if (ret < 0) { + DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret); + goto err_regulators_disable; + } + + ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE); + if (ret) { + DRM_ERROR("failed to enable VDO: %d\n", ret); + goto err_regulators_disable; + } + + /* Switch access edp panel's edid through i2c */ + ret = i2c_smbus_write_byte_data(client, PAGE2_I2C_BYPASS, + I2C_BYPASS_EN); + if (ret < 0) { + DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret); + goto err_regulators_disable; + } + + return; + +err_regulators_disable: + regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), + ps_bridge->supplies); +} + +static void ps8640_post_disable(struct drm_bridge *bridge) +{ + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + int ret; + + ret = ps8640_bridge_vdo_control(ps_bridge, DISABLE); + if (ret < 0) + DRM_ERROR("failed to disable VDO: %d\n", ret); + + gpiod_set_value(ps_bridge->gpio_reset, 1); + gpiod_set_value(ps_bridge->gpio_powerdown, 1); + ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), + ps_bridge->supplies); + if (ret < 0) + DRM_ERROR("cannot disable regulators %d\n", ret); +} + +static int ps8640_bridge_attach(struct drm_bridge *bridge) +{ + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + struct device *dev = &ps_bridge->page[0]->dev; + struct device_node *in_ep, *dsi_node; + struct mipi_dsi_device *dsi; + struct mipi_dsi_host *host; + int ret; + const struct mipi_dsi_device_info info = { .type = "ps8640", + .channel = 0, + .node = NULL, + }; + /* port@0 is ps8640 dsi input port */ + in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); + if (!in_ep) + return -ENODEV; + + dsi_node = of_graph_get_remote_port_parent(in_ep); + of_node_put(in_ep); + if (!dsi_node) + return -ENODEV; + + host = of_find_mipi_dsi_host_by_node(dsi_node); + of_node_put(dsi_node); + if (!host) + return -ENODEV; + + dsi = mipi_dsi_device_register_full(host, &info); + if (IS_ERR(dsi)) { + dev_err(dev, "failed to create dsi device\n"); + ret = PTR_ERR(dsi); + return ret; + } + + ps_bridge->dsi = dsi; + + dsi->host = host; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->lanes = DP_NUM_LANES; + ret = mipi_dsi_attach(dsi); + if (ret) + goto err_dsi_attach; + + /* Attach the panel-bridge to the dsi bridge */ + return drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, + &ps_bridge->bridge); + +err_dsi_attach: + mipi_dsi_device_unregister(dsi); + return ret; +} + +static const struct drm_bridge_funcs ps8640_bridge_funcs = { + .attach = ps8640_bridge_attach, + .post_disable = ps8640_post_disable, + .pre_enable = ps8640_pre_enable, +}; + +static int ps8640_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct device_node *np = dev->of_node; + struct ps8640 *ps_bridge; + struct drm_panel *panel; + int ret; + u32 i; + + ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL); + if (!ps_bridge) + return -ENOMEM; + + /* port@1 is ps8640 output port */ + ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); + if (ret < 0) + return ret; + if (!panel) + return -ENODEV; + + panel->connector_type = DRM_MODE_CONNECTOR_eDP; + + ps_bridge->panel_bridge = devm_drm_panel_bridge_add(dev, panel); + if (IS_ERR(ps_bridge->panel_bridge)) + return PTR_ERR(ps_bridge->panel_bridge); + + ps_bridge->supplies[0].supply = "vdd33"; + ps_bridge->supplies[1].supply = "vdd12"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies), + ps_bridge->supplies); + if (ret) + return ret; + + ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown", + GPIOD_OUT_HIGH); + if (IS_ERR(ps_bridge->gpio_powerdown)) + return PTR_ERR(ps_bridge->gpio_powerdown); + + /* + * Assert the reset to avoid the bridge being initialized prematurely + */ + ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(ps_bridge->gpio_reset)) + return PTR_ERR(ps_bridge->gpio_reset); + + ps_bridge->bridge.funcs = &ps8640_bridge_funcs; + ps_bridge->bridge.of_node = dev->of_node; + + ps_bridge->page[PAGE0_DP_CNTL] = client; + + for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) { + ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev, + client->adapter, + client->addr + i); + if (IS_ERR(ps_bridge->page[i])) { + dev_err(dev, "failed i2c dummy device, address %02x\n", + client->addr + i); + return PTR_ERR(ps_bridge->page[i]); + } + } + + i2c_set_clientdata(client, ps_bridge); + + drm_bridge_add(&ps_bridge->bridge); + + return 0; +} + +static int ps8640_remove(struct i2c_client *client) +{ + struct ps8640 *ps_bridge = i2c_get_clientdata(client); + + drm_bridge_remove(&ps_bridge->bridge); + + return 0; +} + +static const struct of_device_id ps8640_match[] = { + { .compatible = "parade,ps8640" }, + { } +}; +MODULE_DEVICE_TABLE(of, ps8640_match); + +static struct i2c_driver ps8640_driver = { + .probe_new = ps8640_probe, + .remove = ps8640_remove, + .driver = { + .name = "ps8640", + .of_match_table = ps8640_match, + }, +}; +module_i2c_driver(ps8640_driver); + +MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>"); +MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>"); +MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>"); +MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/cirrus/cirrus.c b/drivers/gpu/drm/cirrus/cirrus.c index 248c9f765c45..a91fb0d7282c 100644 --- a/drivers/gpu/drm/cirrus/cirrus.c +++ b/drivers/gpu/drm/cirrus/cirrus.c @@ -38,7 +38,6 @@ #include <drm/drm_modeset_helper_vtables.h> #include <drm/drm_probe_helper.h> #include <drm/drm_simple_kms_helper.h> -#include <drm/drm_vblank.h> #define DRIVER_NAME "cirrus" #define DRIVER_DESC "qemu cirrus vga" @@ -434,13 +433,6 @@ static void cirrus_pipe_update(struct drm_simple_display_pipe *pipe, if (drm_atomic_helper_damage_merged(old_state, state, &rect)) cirrus_fb_blit_rect(pipe->plane.state->fb, &rect); - - if (crtc->state->event) { - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, crtc->state->event); - crtc->state->event = NULL; - spin_unlock_irq(&crtc->dev->event_lock); - } } static const struct drm_simple_display_pipe_funcs cirrus_pipe_funcs = { diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index d33691512a8e..65c46ed049c5 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -30,6 +30,7 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_uapi.h> +#include <drm/drm_bridge.h> #include <drm/drm_debugfs.h> #include <drm/drm_device.h> #include <drm/drm_drv.h> @@ -1018,6 +1019,121 @@ static void drm_atomic_connector_print_state(struct drm_printer *p, } /** + * drm_atomic_get_bridge_state - get bridge state + * @state: global atomic state object + * @bridge: bridge to get state object for + * + * This function returns the bridge state for the given bridge, allocating it + * if needed. It will also grab the relevant bridge lock to make sure that the + * state is consistent. + * + * Returns: + * + * Either the allocated state or the error code encoded into the pointer. When + * the error is EDEADLK then the w/w mutex code has detected a deadlock and the + * entire atomic sequence must be restarted. + */ +struct drm_bridge_state * +drm_atomic_get_bridge_state(struct drm_atomic_state *state, + struct drm_bridge *bridge) +{ + struct drm_private_state *obj_state; + + obj_state = drm_atomic_get_private_obj_state(state, &bridge->base); + if (IS_ERR(obj_state)) + return ERR_CAST(obj_state); + + return drm_priv_to_bridge_state(obj_state); +} +EXPORT_SYMBOL(drm_atomic_get_bridge_state); + +/** + * drm_atomic_get_old_bridge_state - get old bridge state, if it exists + * @state: global atomic state object + * @bridge: bridge to grab + * + * This function returns the old bridge state for the given bridge, or NULL if + * the bridge is not part of the global atomic state. + */ +struct drm_bridge_state * +drm_atomic_get_old_bridge_state(struct drm_atomic_state *state, + struct drm_bridge *bridge) +{ + struct drm_private_state *obj_state; + + obj_state = drm_atomic_get_old_private_obj_state(state, &bridge->base); + if (!obj_state) + return NULL; + + return drm_priv_to_bridge_state(obj_state); +} +EXPORT_SYMBOL(drm_atomic_get_old_bridge_state); + +/** + * drm_atomic_get_new_bridge_state - get new bridge state, if it exists + * @state: global atomic state object + * @bridge: bridge to grab + * + * This function returns the new bridge state for the given bridge, or NULL if + * the bridge is not part of the global atomic state. + */ +struct drm_bridge_state * +drm_atomic_get_new_bridge_state(struct drm_atomic_state *state, + struct drm_bridge *bridge) +{ + struct drm_private_state *obj_state; + + obj_state = drm_atomic_get_new_private_obj_state(state, &bridge->base); + if (!obj_state) + return NULL; + + return drm_priv_to_bridge_state(obj_state); +} +EXPORT_SYMBOL(drm_atomic_get_new_bridge_state); + +/** + * drm_atomic_add_encoder_bridges - add bridges attached to an encoder + * @state: atomic state + * @encoder: DRM encoder + * + * This function adds all bridges attached to @encoder. This is needed to add + * bridge states to @state and make them available when + * &bridge_funcs.atomic_{check,pre_enable,enable,disable_post_disable}() are + * called + * + * Returns: + * 0 on success or can fail with -EDEADLK or -ENOMEM. When the error is EDEADLK + * then the w/w mutex code has detected a deadlock and the entire atomic + * sequence must be restarted. All other errors are fatal. + */ +int +drm_atomic_add_encoder_bridges(struct drm_atomic_state *state, + struct drm_encoder *encoder) +{ + struct drm_bridge_state *bridge_state; + struct drm_bridge *bridge; + + if (!encoder) + return 0; + + DRM_DEBUG_ATOMIC("Adding all bridges for [encoder:%d:%s] to %p\n", + encoder->base.id, encoder->name, state); + + drm_for_each_bridge_in_chain(encoder, bridge) { + /* Skip bridges that don't implement the atomic state hooks. */ + if (!bridge->funcs->atomic_duplicate_state) + continue; + + bridge_state = drm_atomic_get_bridge_state(state, bridge); + if (IS_ERR(bridge_state)) + return PTR_ERR(bridge_state); + } + + return 0; +} +EXPORT_SYMBOL(drm_atomic_add_encoder_bridges); + +/** * drm_atomic_add_affected_connectors - add connectors for CRTC * @state: atomic state * @crtc: DRM CRTC diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 4511c2e07bb9..85d163f16801 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -437,12 +437,12 @@ mode_fixup(struct drm_atomic_state *state) funcs = encoder->helper_private; bridge = drm_bridge_chain_get_first_bridge(encoder); - ret = drm_bridge_chain_mode_fixup(bridge, - &new_crtc_state->mode, - &new_crtc_state->adjusted_mode); - if (!ret) { - DRM_DEBUG_ATOMIC("Bridge fixup failed\n"); - return -EINVAL; + ret = drm_atomic_bridge_chain_check(bridge, + new_crtc_state, + new_conn_state); + if (ret) { + DRM_DEBUG_ATOMIC("Bridge atomic check failed\n"); + return ret; } if (funcs && funcs->atomic_check) { @@ -583,6 +583,7 @@ mode_valid(struct drm_atomic_state *state) * &drm_crtc_state.connectors_changed is set when a connector is added or * removed from the CRTC. &drm_crtc_state.active_changed is set when * &drm_crtc_state.active changes, which is used for DPMS. + * &drm_crtc_state.no_vblank is set from the result of drm_dev_has_vblank(). * See also: drm_atomic_crtc_needs_modeset() * * IMPORTANT: @@ -649,6 +650,11 @@ drm_atomic_helper_check_modeset(struct drm_device *dev, return -EINVAL; } + + if (drm_dev_has_vblank(dev)) + new_crtc_state->no_vblank = false; + else + new_crtc_state->no_vblank = true; } ret = handle_conflicting_encoders(state, false); @@ -730,6 +736,26 @@ drm_atomic_helper_check_modeset(struct drm_device *dev, return ret; } + /* + * Iterate over all connectors again, and add all affected bridges to + * the state. + */ + for_each_oldnew_connector_in_state(state, connector, + old_connector_state, + new_connector_state, i) { + struct drm_encoder *encoder; + + encoder = old_connector_state->best_encoder; + ret = drm_atomic_add_encoder_bridges(state, encoder); + if (ret) + return ret; + + encoder = new_connector_state->best_encoder; + ret = drm_atomic_add_encoder_bridges(state, encoder); + if (ret) + return ret; + } + ret = mode_valid(state); if (ret) return ret; @@ -2215,7 +2241,9 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_dependencies); * when a job is queued, and any change to the pipeline that does not touch the * connector is leading to timeouts when calling * drm_atomic_helper_wait_for_vblanks() or - * drm_atomic_helper_wait_for_flip_done(). + * drm_atomic_helper_wait_for_flip_done(). In addition to writeback + * connectors, this function can also fake VBLANK events for CRTCs without + * VBLANK interrupt. * * This is part of the atomic helper support for nonblocking commits, see * drm_atomic_helper_setup_commit() for an overview. @@ -3508,3 +3536,44 @@ fail: return ret; } EXPORT_SYMBOL(drm_atomic_helper_legacy_gamma_set); + +/** + * drm_atomic_helper_bridge_propagate_bus_fmt() - Propagate output format to + * the input end of a bridge + * @bridge: bridge control structure + * @bridge_state: new bridge state + * @crtc_state: new CRTC state + * @conn_state: new connector state + * @output_fmt: tested output bus format + * @num_input_fmts: will contain the size of the returned array + * + * This helper is a pluggable implementation of the + * &drm_bridge_funcs.atomic_get_input_bus_fmts operation for bridges that don't + * modify the bus configuration between their input and their output. It + * returns an array of input formats with a single element set to @output_fmt. + * + * RETURNS: + * a valid format array of size @num_input_fmts, or NULL if the allocation + * failed + */ +u32 * +drm_atomic_helper_bridge_propagate_bus_fmt(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + input_fmts = kzalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) { + *num_input_fmts = 0; + return NULL; + } + + *num_input_fmts = 1; + input_fmts[0] = output_fmt; + return input_fmts; +} +EXPORT_SYMBOL(drm_atomic_helper_bridge_propagate_bus_fmt); diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 7cf3cf936547..33141d2cdad4 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -26,6 +26,7 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_state_helper.h> +#include <drm/drm_bridge.h> #include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include <drm/drm_device.h> @@ -551,3 +552,105 @@ void __drm_atomic_helper_private_obj_duplicate_state(struct drm_private_obj *obj memcpy(state, obj->state, sizeof(*state)); } EXPORT_SYMBOL(__drm_atomic_helper_private_obj_duplicate_state); + +/** + * __drm_atomic_helper_bridge_duplicate_state() - Copy atomic bridge state + * @bridge: bridge object + * @state: atomic bridge state + * + * Copies atomic state from a bridge's current state and resets inferred values. + * This is useful for drivers that subclass the bridge state. + */ +void __drm_atomic_helper_bridge_duplicate_state(struct drm_bridge *bridge, + struct drm_bridge_state *state) +{ + __drm_atomic_helper_private_obj_duplicate_state(&bridge->base, + &state->base); + state->bridge = bridge; +} +EXPORT_SYMBOL(__drm_atomic_helper_bridge_duplicate_state); + +/** + * drm_atomic_helper_bridge_duplicate_state() - Duplicate a bridge state object + * @bridge: bridge object + * + * Allocates a new bridge state and initializes it with the current bridge + * state values. This helper is meant to be used as a bridge + * &drm_bridge_funcs.atomic_duplicate_state hook for bridges that don't + * subclass the bridge state. + */ +struct drm_bridge_state * +drm_atomic_helper_bridge_duplicate_state(struct drm_bridge *bridge) +{ + struct drm_bridge_state *new; + + if (WARN_ON(!bridge->base.state)) + return NULL; + + new = kzalloc(sizeof(*new), GFP_KERNEL); + if (new) + __drm_atomic_helper_bridge_duplicate_state(bridge, new); + + return new; +} +EXPORT_SYMBOL(drm_atomic_helper_bridge_duplicate_state); + +/** + * drm_atomic_helper_bridge_destroy_state() - Destroy a bridge state object + * @bridge: the bridge this state refers to + * @state: bridge state to destroy + * + * Destroys a bridge state previously created by + * &drm_atomic_helper_bridge_reset() or + * &drm_atomic_helper_bridge_duplicate_state(). This helper is meant to be + * used as a bridge &drm_bridge_funcs.atomic_destroy_state hook for bridges + * that don't subclass the bridge state. + */ +void drm_atomic_helper_bridge_destroy_state(struct drm_bridge *bridge, + struct drm_bridge_state *state) +{ + kfree(state); +} +EXPORT_SYMBOL(drm_atomic_helper_bridge_destroy_state); + +/** + * __drm_atomic_helper_bridge_reset() - Initialize a bridge state to its + * default + * @bridge: the bridge this state refers to + * @state: bridge state to initialize + * + * Initializes the bridge state to default values. This is meant to be called + * by the bridge &drm_bridge_funcs.atomic_reset hook for bridges that subclass + * the bridge state. + */ +void __drm_atomic_helper_bridge_reset(struct drm_bridge *bridge, + struct drm_bridge_state *state) +{ + memset(state, 0, sizeof(*state)); + state->bridge = bridge; +} +EXPORT_SYMBOL(__drm_atomic_helper_bridge_reset); + +/** + * drm_atomic_helper_bridge_reset() - Allocate and initialize a bridge state + * to its default + * @bridge: the bridge this state refers to + * @state: bridge state to initialize + * + * Allocates the bridge state and initializes it to default values. This helper + * is meant to be used as a bridge &drm_bridge_funcs.atomic_reset hook for + * bridges that don't subclass the bridge state. + */ +struct drm_bridge_state * +drm_atomic_helper_bridge_reset(struct drm_bridge *bridge) +{ + struct drm_bridge_state *bridge_state; + + bridge_state = kzalloc(sizeof(*bridge_state), GFP_KERNEL); + if (!bridge_state) + return ERR_PTR(-ENOMEM); + + __drm_atomic_helper_bridge_reset(bridge, bridge_state); + return bridge_state; +} +EXPORT_SYMBOL(drm_atomic_helper_bridge_reset); diff --git a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c index cc9acd986c68..531b876d0ed8 100644 --- a/drivers/gpu/drm/drm_auth.c +++ b/drivers/gpu/drm/drm_auth.c @@ -153,11 +153,6 @@ static int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv) return -ENOMEM; } - if (dev->driver->master_create) { - ret = dev->driver->master_create(dev, fpriv->master); - if (ret) - goto out_err; - } fpriv->is_master = 1; fpriv->authenticated = 1; @@ -332,9 +327,6 @@ static void drm_master_destroy(struct kref *kref) if (drm_core_check_feature(dev, DRIVER_MODESET)) drm_lease_destroy(master); - if (dev->driver->master_destroy) - dev->driver->master_destroy(dev, master); - drm_legacy_master_rmmaps(dev, master); idr_destroy(&master->magic_map); diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index c2cf0c90fa26..68ab933ee430 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -25,6 +25,7 @@ #include <linux/module.h> #include <linux/mutex.h> +#include <drm/drm_atomic_state_helper.h> #include <drm/drm_bridge.h> #include <drm/drm_encoder.h> @@ -89,6 +90,31 @@ void drm_bridge_remove(struct drm_bridge *bridge) } EXPORT_SYMBOL(drm_bridge_remove); +static struct drm_private_state * +drm_bridge_atomic_duplicate_priv_state(struct drm_private_obj *obj) +{ + struct drm_bridge *bridge = drm_priv_to_bridge(obj); + struct drm_bridge_state *state; + + state = bridge->funcs->atomic_duplicate_state(bridge); + return state ? &state->base : NULL; +} + +static void +drm_bridge_atomic_destroy_priv_state(struct drm_private_obj *obj, + struct drm_private_state *s) +{ + struct drm_bridge_state *state = drm_priv_to_bridge_state(s); + struct drm_bridge *bridge = drm_priv_to_bridge(obj); + + bridge->funcs->atomic_destroy_state(bridge, state); +} + +static const struct drm_private_state_funcs drm_bridge_priv_state_funcs = { + .atomic_duplicate_state = drm_bridge_atomic_duplicate_priv_state, + .atomic_destroy_state = drm_bridge_atomic_destroy_priv_state, +}; + /** * drm_bridge_attach - attach the bridge to an encoder's chain * @@ -135,15 +161,35 @@ int drm_bridge_attach(struct drm_encoder *encoder, struct drm_bridge *bridge, if (bridge->funcs->attach) { ret = bridge->funcs->attach(bridge); - if (ret < 0) { - list_del(&bridge->chain_node); - bridge->dev = NULL; - bridge->encoder = NULL; - return ret; + if (ret < 0) + goto err_reset_bridge; + } + + if (bridge->funcs->atomic_reset) { + struct drm_bridge_state *state; + + state = bridge->funcs->atomic_reset(bridge); + if (IS_ERR(state)) { + ret = PTR_ERR(state); + goto err_detach_bridge; } + + drm_atomic_private_obj_init(bridge->dev, &bridge->base, + &state->base, + &drm_bridge_priv_state_funcs); } return 0; + +err_detach_bridge: + if (bridge->funcs->detach) + bridge->funcs->detach(bridge); + +err_reset_bridge: + bridge->dev = NULL; + bridge->encoder = NULL; + list_del(&bridge->chain_node); + return ret; } EXPORT_SYMBOL(drm_bridge_attach); @@ -155,6 +201,9 @@ void drm_bridge_detach(struct drm_bridge *bridge) if (WARN_ON(!bridge->dev)) return; + if (bridge->funcs->atomic_reset) + drm_atomic_private_obj_fini(&bridge->base); + if (bridge->funcs->detach) bridge->funcs->detach(bridge); @@ -409,10 +458,19 @@ void drm_atomic_bridge_chain_disable(struct drm_bridge *bridge, encoder = bridge->encoder; list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { - if (iter->funcs->atomic_disable) - iter->funcs->atomic_disable(iter, old_state); - else if (iter->funcs->disable) + if (iter->funcs->atomic_disable) { + struct drm_bridge_state *old_bridge_state; + + old_bridge_state = + drm_atomic_get_old_bridge_state(old_state, + iter); + if (WARN_ON(!old_bridge_state)) + return; + + iter->funcs->atomic_disable(iter, old_bridge_state); + } else if (iter->funcs->disable) { iter->funcs->disable(iter); + } if (iter == bridge) break; @@ -443,10 +501,20 @@ void drm_atomic_bridge_chain_post_disable(struct drm_bridge *bridge, encoder = bridge->encoder; list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) { - if (bridge->funcs->atomic_post_disable) - bridge->funcs->atomic_post_disable(bridge, old_state); - else if (bridge->funcs->post_disable) + if (bridge->funcs->atomic_post_disable) { + struct drm_bridge_state *old_bridge_state; + + old_bridge_state = + drm_atomic_get_old_bridge_state(old_state, + bridge); + if (WARN_ON(!old_bridge_state)) + return; + + bridge->funcs->atomic_post_disable(bridge, + old_bridge_state); + } else if (bridge->funcs->post_disable) { bridge->funcs->post_disable(bridge); + } } } EXPORT_SYMBOL(drm_atomic_bridge_chain_post_disable); @@ -475,10 +543,19 @@ void drm_atomic_bridge_chain_pre_enable(struct drm_bridge *bridge, encoder = bridge->encoder; list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { - if (iter->funcs->atomic_pre_enable) - iter->funcs->atomic_pre_enable(iter, old_state); - else if (iter->funcs->pre_enable) + if (iter->funcs->atomic_pre_enable) { + struct drm_bridge_state *old_bridge_state; + + old_bridge_state = + drm_atomic_get_old_bridge_state(old_state, + iter); + if (WARN_ON(!old_bridge_state)) + return; + + iter->funcs->atomic_pre_enable(iter, old_bridge_state); + } else if (iter->funcs->pre_enable) { iter->funcs->pre_enable(iter); + } if (iter == bridge) break; @@ -508,14 +585,340 @@ void drm_atomic_bridge_chain_enable(struct drm_bridge *bridge, encoder = bridge->encoder; list_for_each_entry_from(bridge, &encoder->bridge_chain, chain_node) { - if (bridge->funcs->atomic_enable) - bridge->funcs->atomic_enable(bridge, old_state); - else if (bridge->funcs->enable) + if (bridge->funcs->atomic_enable) { + struct drm_bridge_state *old_bridge_state; + + old_bridge_state = + drm_atomic_get_old_bridge_state(old_state, + bridge); + if (WARN_ON(!old_bridge_state)) + return; + + bridge->funcs->atomic_enable(bridge, old_bridge_state); + } else if (bridge->funcs->enable) { bridge->funcs->enable(bridge); + } } } EXPORT_SYMBOL(drm_atomic_bridge_chain_enable); +static int drm_atomic_bridge_check(struct drm_bridge *bridge, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + if (bridge->funcs->atomic_check) { + struct drm_bridge_state *bridge_state; + int ret; + + bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state, + bridge); + if (WARN_ON(!bridge_state)) + return -EINVAL; + + ret = bridge->funcs->atomic_check(bridge, bridge_state, + crtc_state, conn_state); + if (ret) + return ret; + } else if (bridge->funcs->mode_fixup) { + if (!bridge->funcs->mode_fixup(bridge, &crtc_state->mode, + &crtc_state->adjusted_mode)) + return -EINVAL; + } + + return 0; +} + +static int select_bus_fmt_recursive(struct drm_bridge *first_bridge, + struct drm_bridge *cur_bridge, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 out_bus_fmt) +{ + struct drm_bridge_state *cur_state; + unsigned int num_in_bus_fmts, i; + struct drm_bridge *prev_bridge; + u32 *in_bus_fmts; + int ret; + + prev_bridge = drm_bridge_get_prev_bridge(cur_bridge); + cur_state = drm_atomic_get_new_bridge_state(crtc_state->state, + cur_bridge); + + /* + * If bus format negotiation is not supported by this bridge, let's + * pass MEDIA_BUS_FMT_FIXED to the previous bridge in the chain and + * hope that it can handle this situation gracefully (by providing + * appropriate default values). + */ + if (!cur_bridge->funcs->atomic_get_input_bus_fmts) { + if (cur_bridge != first_bridge) { + ret = select_bus_fmt_recursive(first_bridge, + prev_bridge, crtc_state, + conn_state, + MEDIA_BUS_FMT_FIXED); + if (ret) + return ret; + } + + /* + * Driver does not implement the atomic state hooks, but that's + * fine, as long as it does not access the bridge state. + */ + if (cur_state) { + cur_state->input_bus_cfg.format = MEDIA_BUS_FMT_FIXED; + cur_state->output_bus_cfg.format = out_bus_fmt; + } + + return 0; + } + + /* + * If the driver implements ->atomic_get_input_bus_fmts() it + * should also implement the atomic state hooks. + */ + if (WARN_ON(!cur_state)) + return -EINVAL; + + in_bus_fmts = cur_bridge->funcs->atomic_get_input_bus_fmts(cur_bridge, + cur_state, + crtc_state, + conn_state, + out_bus_fmt, + &num_in_bus_fmts); + if (!num_in_bus_fmts) + return -ENOTSUPP; + else if (!in_bus_fmts) + return -ENOMEM; + + if (first_bridge == cur_bridge) { + cur_state->input_bus_cfg.format = in_bus_fmts[0]; + cur_state->output_bus_cfg.format = out_bus_fmt; + kfree(in_bus_fmts); + return 0; + } + + for (i = 0; i < num_in_bus_fmts; i++) { + ret = select_bus_fmt_recursive(first_bridge, prev_bridge, + crtc_state, conn_state, + in_bus_fmts[i]); + if (ret != -ENOTSUPP) + break; + } + + if (!ret) { + cur_state->input_bus_cfg.format = in_bus_fmts[i]; + cur_state->output_bus_cfg.format = out_bus_fmt; + } + + kfree(in_bus_fmts); + return ret; +} + +/* + * This function is called by &drm_atomic_bridge_chain_check() just before + * calling &drm_bridge_funcs.atomic_check() on all elements of the chain. + * It performs bus format negotiation between bridge elements. The negotiation + * happens in reverse order, starting from the last element in the chain up to + * @bridge. + * + * Negotiation starts by retrieving supported output bus formats on the last + * bridge element and testing them one by one. The test is recursive, meaning + * that for each tested output format, the whole chain will be walked backward, + * and each element will have to choose an input bus format that can be + * transcoded to the requested output format. When a bridge element does not + * support transcoding into a specific output format -ENOTSUPP is returned and + * the next bridge element will have to try a different format. If none of the + * combinations worked, -ENOTSUPP is returned and the atomic modeset will fail. + * + * This implementation is relying on + * &drm_bridge_funcs.atomic_get_output_bus_fmts() and + * &drm_bridge_funcs.atomic_get_input_bus_fmts() to gather supported + * input/output formats. + * + * When &drm_bridge_funcs.atomic_get_output_bus_fmts() is not implemented by + * the last element of the chain, &drm_atomic_bridge_chain_select_bus_fmts() + * tries a single format: &drm_connector.display_info.bus_formats[0] if + * available, MEDIA_BUS_FMT_FIXED otherwise. + * + * When &drm_bridge_funcs.atomic_get_input_bus_fmts() is not implemented, + * &drm_atomic_bridge_chain_select_bus_fmts() skips the negotiation on the + * bridge element that lacks this hook and asks the previous element in the + * chain to try MEDIA_BUS_FMT_FIXED. It's up to bridge drivers to decide what + * to do in that case (fail if they want to enforce bus format negotiation, or + * provide a reasonable default if they need to support pipelines where not + * all elements support bus format negotiation). + */ +static int +drm_atomic_bridge_chain_select_bus_fmts(struct drm_bridge *bridge, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_connector *conn = conn_state->connector; + struct drm_encoder *encoder = bridge->encoder; + struct drm_bridge_state *last_bridge_state; + unsigned int i, num_out_bus_fmts; + struct drm_bridge *last_bridge; + u32 *out_bus_fmts; + int ret = 0; + + last_bridge = list_last_entry(&encoder->bridge_chain, + struct drm_bridge, chain_node); + last_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state, + last_bridge); + + if (last_bridge->funcs->atomic_get_output_bus_fmts) { + const struct drm_bridge_funcs *funcs = last_bridge->funcs; + + /* + * If the driver implements ->atomic_get_output_bus_fmts() it + * should also implement the atomic state hooks. + */ + if (WARN_ON(!last_bridge_state)) + return -EINVAL; + + out_bus_fmts = funcs->atomic_get_output_bus_fmts(last_bridge, + last_bridge_state, + crtc_state, + conn_state, + &num_out_bus_fmts); + if (!num_out_bus_fmts) + return -ENOTSUPP; + else if (!out_bus_fmts) + return -ENOMEM; + } else { + num_out_bus_fmts = 1; + out_bus_fmts = kmalloc(sizeof(*out_bus_fmts), GFP_KERNEL); + if (!out_bus_fmts) + return -ENOMEM; + + if (conn->display_info.num_bus_formats && + conn->display_info.bus_formats) + out_bus_fmts[0] = conn->display_info.bus_formats[0]; + else + out_bus_fmts[0] = MEDIA_BUS_FMT_FIXED; + } + + for (i = 0; i < num_out_bus_fmts; i++) { + ret = select_bus_fmt_recursive(bridge, last_bridge, crtc_state, + conn_state, out_bus_fmts[i]); + if (ret != -ENOTSUPP) + break; + } + + kfree(out_bus_fmts); + + return ret; +} + +static void +drm_atomic_bridge_propagate_bus_flags(struct drm_bridge *bridge, + struct drm_connector *conn, + struct drm_atomic_state *state) +{ + struct drm_bridge_state *bridge_state, *next_bridge_state; + struct drm_bridge *next_bridge; + u32 output_flags = 0; + + bridge_state = drm_atomic_get_new_bridge_state(state, bridge); + + /* No bridge state attached to this bridge => nothing to propagate. */ + if (!bridge_state) + return; + + next_bridge = drm_bridge_get_next_bridge(bridge); + + /* + * Let's try to apply the most common case here, that is, propagate + * display_info flags for the last bridge, and propagate the input + * flags of the next bridge element to the output end of the current + * bridge when the bridge is not the last one. + * There are exceptions to this rule, like when signal inversion is + * happening at the board level, but that's something drivers can deal + * with from their &drm_bridge_funcs.atomic_check() implementation by + * simply overriding the flags value we've set here. + */ + if (!next_bridge) { + output_flags = conn->display_info.bus_flags; + } else { + next_bridge_state = drm_atomic_get_new_bridge_state(state, + next_bridge); + /* + * No bridge state attached to the next bridge, just leave the + * flags to 0. + */ + if (next_bridge_state) + output_flags = next_bridge_state->input_bus_cfg.flags; + } + + bridge_state->output_bus_cfg.flags = output_flags; + + /* + * Propage the output flags to the input end of the bridge. Again, it's + * not necessarily what all bridges want, but that's what most of them + * do, and by doing that by default we avoid forcing drivers to + * duplicate the "dummy propagation" logic. + */ + bridge_state->input_bus_cfg.flags = output_flags; +} + +/** + * drm_atomic_bridge_chain_check() - Do an atomic check on the bridge chain + * @bridge: bridge control structure + * @crtc_state: new CRTC state + * @conn_state: new connector state + * + * First trigger a bus format negotiation before calling + * &drm_bridge_funcs.atomic_check() (falls back on + * &drm_bridge_funcs.mode_fixup()) op for all the bridges in the encoder chain, + * starting from the last bridge to the first. These are called before calling + * &drm_encoder_helper_funcs.atomic_check() + * + * RETURNS: + * 0 on success, a negative error code on failure + */ +int drm_atomic_bridge_chain_check(struct drm_bridge *bridge, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_connector *conn = conn_state->connector; + struct drm_encoder *encoder; + struct drm_bridge *iter; + int ret; + + if (!bridge) + return 0; + + ret = drm_atomic_bridge_chain_select_bus_fmts(bridge, crtc_state, + conn_state); + if (ret) + return ret; + + encoder = bridge->encoder; + list_for_each_entry_reverse(iter, &encoder->bridge_chain, chain_node) { + int ret; + + /* + * Bus flags are propagated by default. If a bridge needs to + * tweak the input bus flags for any reason, it should happen + * in its &drm_bridge_funcs.atomic_check() implementation such + * that preceding bridges in the chain can propagate the new + * bus flags. + */ + drm_atomic_bridge_propagate_bus_flags(iter, conn, + crtc_state->state); + + ret = drm_atomic_bridge_check(iter, crtc_state, conn_state); + if (ret) + return ret; + + if (iter == bridge) + break; + } + + return 0; +} +EXPORT_SYMBOL(drm_atomic_bridge_chain_check); + #ifdef CONFIG_OF /** * of_drm_find_bridge - find the bridge corresponding to the device node in diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c index 8ce9d73fab4f..19297e58b232 100644 --- a/drivers/gpu/drm/drm_bufs.c +++ b/drivers/gpu/drm/drm_bufs.c @@ -149,7 +149,6 @@ static int drm_addmap_core(struct drm_device *dev, resource_size_t offset, { struct drm_local_map *map; struct drm_map_list *list; - drm_dma_handle_t *dmah; unsigned long user_token; int ret; @@ -324,14 +323,14 @@ static int drm_addmap_core(struct drm_device *dev, resource_size_t offset, * As we're limiting the address to 2^32-1 (or less), * casting it down to 32 bits is no problem, but we * need to point to a 64bit variable first. */ - dmah = drm_pci_alloc(dev, map->size, map->size); - if (!dmah) { + map->handle = dma_alloc_coherent(&dev->pdev->dev, + map->size, + &map->offset, + GFP_KERNEL); + if (!map->handle) { kfree(map); return -ENOMEM; } - map->handle = dmah->vaddr; - map->offset = (unsigned long)dmah->busaddr; - kfree(dmah); break; default: kfree(map); @@ -513,7 +512,6 @@ int drm_legacy_getmap_ioctl(struct drm_device *dev, void *data, int drm_legacy_rmmap_locked(struct drm_device *dev, struct drm_local_map *map) { struct drm_map_list *r_list = NULL, *list_t; - drm_dma_handle_t dmah; int found = 0; struct drm_master *master; @@ -554,10 +552,10 @@ int drm_legacy_rmmap_locked(struct drm_device *dev, struct drm_local_map *map) case _DRM_SCATTER_GATHER: break; case _DRM_CONSISTENT: - dmah.vaddr = map->handle; - dmah.busaddr = map->offset; - dmah.size = map->size; - __drm_legacy_pci_free(dev, &dmah); + dma_free_coherent(&dev->pdev->dev, + map->size, + map->handle, + map->offset); break; } kfree(map); diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 2166000ed057..f632ca05960e 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -140,6 +140,13 @@ static void drm_connector_get_cmdline_mode(struct drm_connector *connector) connector->force = mode->force; } + if (mode->panel_orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) { + DRM_INFO("cmdline forces connector %s panel_orientation to %d\n", + connector->name, mode->panel_orientation); + drm_connector_set_panel_orientation(connector, + mode->panel_orientation); + } + DRM_DEBUG_KMS("cmdline mode for connector %s %s %dx%d@%dHz%s%s%s\n", connector->name, mode->name, mode->xres, mode->yres, @@ -1139,7 +1146,8 @@ static const struct drm_prop_enum_list dp_colorspaces[] = { * coordinates, so if userspace rotates the picture to adjust for * the orientation it must also apply the same transformation to the * touchscreen input coordinates. This property is initialized by calling - * drm_connector_init_panel_orientation_property(). + * drm_connector_set_panel_orientation() or + * drm_connector_set_panel_orientation_with_quirk() * * scaling mode: * This property defines how a non-native mode is upscaled to the native @@ -2046,38 +2054,41 @@ void drm_connector_set_vrr_capable_property( EXPORT_SYMBOL(drm_connector_set_vrr_capable_property); /** - * drm_connector_init_panel_orientation_property - - * initialize the connecters panel_orientation property - * @connector: connector for which to init the panel-orientation property. - * @width: width in pixels of the panel, used for panel quirk detection - * @height: height in pixels of the panel, used for panel quirk detection + * drm_connector_set_panel_orientation - sets the connecter's panel_orientation + * @connector: connector for which to set the panel-orientation property. + * @panel_orientation: drm_panel_orientation value to set + * + * This function sets the connector's panel_orientation and attaches + * a "panel orientation" property to the connector. * - * This function should only be called for built-in panels, after setting - * connector->display_info.panel_orientation first (if known). + * Calling this function on a connector where the panel_orientation has + * already been set is a no-op (e.g. the orientation has been overridden with + * a kernel commandline option). * - * This function will check for platform specific (e.g. DMI based) quirks - * overriding display_info.panel_orientation first, then if panel_orientation - * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the - * "panel orientation" property to the connector. + * It is allowed to call this function with a panel_orientation of + * DRM_MODE_PANEL_ORIENTATION_UNKNOWN, in which case it is a no-op. * * Returns: * Zero on success, negative errno on failure. */ -int drm_connector_init_panel_orientation_property( - struct drm_connector *connector, int width, int height) +int drm_connector_set_panel_orientation( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation) { struct drm_device *dev = connector->dev; struct drm_display_info *info = &connector->display_info; struct drm_property *prop; - int orientation_quirk; - orientation_quirk = drm_get_panel_orientation_quirk(width, height); - if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) - info->panel_orientation = orientation_quirk; + /* Already set? */ + if (info->panel_orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) + return 0; - if (info->panel_orientation == DRM_MODE_PANEL_ORIENTATION_UNKNOWN) + /* Don't attach the property if the orientation is unknown */ + if (panel_orientation == DRM_MODE_PANEL_ORIENTATION_UNKNOWN) return 0; + info->panel_orientation = panel_orientation; + prop = dev->mode_config.panel_orientation_property; if (!prop) { prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE, @@ -2094,7 +2105,37 @@ int drm_connector_init_panel_orientation_property( info->panel_orientation); return 0; } -EXPORT_SYMBOL(drm_connector_init_panel_orientation_property); +EXPORT_SYMBOL(drm_connector_set_panel_orientation); + +/** + * drm_connector_set_panel_orientation_with_quirk - + * set the connecter's panel_orientation after checking for quirks + * @connector: connector for which to init the panel-orientation property. + * @panel_orientation: drm_panel_orientation value to set + * @width: width in pixels of the panel, used for panel quirk detection + * @height: height in pixels of the panel, used for panel quirk detection + * + * Like drm_connector_set_panel_orientation(), but with a check for platform + * specific (e.g. DMI based) quirks overriding the passed in panel_orientation. + * + * Returns: + * Zero on success, negative errno on failure. + */ +int drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height) +{ + int orientation_quirk; + + orientation_quirk = drm_get_panel_orientation_quirk(width, height); + if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) + panel_orientation = orientation_quirk; + + return drm_connector_set_panel_orientation(connector, + panel_orientation); +} +EXPORT_SYMBOL(drm_connector_set_panel_orientation_with_quirk); int drm_connector_set_obj_prop(struct drm_mode_object *obj, struct drm_property *property, diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index c7d5e4c21423..16f2413403aa 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -216,6 +216,8 @@ int drm_mode_rmfb_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int drm_mode_getfb(struct drm_device *dev, void *data, struct drm_file *file_priv); +int drm_mode_getfb2_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv); int drm_mode_dirtyfb_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c index eab0f2687cd6..4e673d318503 100644 --- a/drivers/gpu/drm/drm_debugfs.c +++ b/drivers/gpu/drm/drm_debugfs.c @@ -182,8 +182,7 @@ int drm_debugfs_create_files(const struct drm_info_list *files, int count, for (i = 0; i < count; i++) { u32 features = files[i].driver_features; - if (features != 0 && - (dev->driver->driver_features & features) != features) + if (features && !drm_core_check_all_features(dev, features)) continue; tmp = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); diff --git a/drivers/gpu/drm/drm_debugfs_crc.c b/drivers/gpu/drm/drm_debugfs_crc.c index e22b812c4b80..5d67a41f7c3a 100644 --- a/drivers/gpu/drm/drm_debugfs_crc.c +++ b/drivers/gpu/drm/drm_debugfs_crc.c @@ -372,7 +372,7 @@ void drm_debugfs_crtc_crc_add(struct drm_crtc *crtc) crc_ent = debugfs_create_dir("crc", crtc->debugfs_entry); - debugfs_create_file("control", S_IRUGO, crc_ent, crtc, + debugfs_create_file("control", S_IRUGO | S_IWUSR, crc_ent, crtc, &drm_crtc_crc_control_fops); debugfs_create_file("data", S_IRUGO, crc_ent, crtc, &drm_crtc_crc_data_fops); diff --git a/drivers/gpu/drm/drm_dma.c b/drivers/gpu/drm/drm_dma.c index e45b07890c5a..a7add55a85b4 100644 --- a/drivers/gpu/drm/drm_dma.c +++ b/drivers/gpu/drm/drm_dma.c @@ -42,10 +42,10 @@ #include "drm_legacy.h" /** - * Initialize the DMA data. + * drm_legacy_dma_setup() - Initialize the DMA data. * - * \param dev DRM device. - * \return zero on success or a negative value on failure. + * @dev: DRM device. + * Return: zero on success or a negative value on failure. * * Allocate and initialize a drm_device_dma structure. */ @@ -71,9 +71,9 @@ int drm_legacy_dma_setup(struct drm_device *dev) } /** - * Cleanup the DMA resources. + * drm_legacy_dma_takedown() - Cleanup the DMA resources. * - * \param dev DRM device. + * @dev: DRM device. * * Free all pages associated with DMA buffers, the buffers and pages lists, and * finally the drm_device::dma structure itself. @@ -120,10 +120,10 @@ void drm_legacy_dma_takedown(struct drm_device *dev) } /** - * Free a buffer. + * drm_legacy_free_buffer() - Free a buffer. * - * \param dev DRM device. - * \param buf buffer to free. + * @dev: DRM device. + * @buf: buffer to free. * * Resets the fields of \p buf. */ @@ -139,9 +139,10 @@ void drm_legacy_free_buffer(struct drm_device *dev, struct drm_buf * buf) } /** - * Reclaim the buffers. + * drm_legacy_reclaim_buffers() - Reclaim the buffers. * - * \param file_priv DRM file private. + * @dev: DRM device. + * @file_priv: DRM file private. * * Frees each buffer associated with \p file_priv not already on the hardware. */ diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index a5364b5192b8..5a103e9b3c86 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -470,8 +470,7 @@ void drm_dp_downstream_debug(struct seq_file *m, int len; uint8_t rev[2]; int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; - bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] & - DP_DWN_STRM_PORT_PRESENT; + bool branch_device = drm_dp_is_branch(dpcd); seq_printf(m, "\tDP branch device present: %s\n", branch_device ? "yes" : "no"); diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 38bf111e5f9b..a811247cecfe 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1935,73 +1935,90 @@ static u8 drm_dp_calculate_rad(struct drm_dp_mst_port *port, return parent_lct + 1; } -static int drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt) +static bool drm_dp_mst_is_dp_mst_end_device(u8 pdt, bool mcs) +{ + switch (pdt) { + case DP_PEER_DEVICE_DP_LEGACY_CONV: + case DP_PEER_DEVICE_SST_SINK: + return true; + case DP_PEER_DEVICE_MST_BRANCHING: + /* For sst branch device */ + if (!mcs) + return true; + + return false; + } + return true; +} + +static int +drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, + bool new_mcs) { struct drm_dp_mst_topology_mgr *mgr = port->mgr; struct drm_dp_mst_branch *mstb; u8 rad[8], lct; int ret = 0; - if (port->pdt == new_pdt) + if (port->pdt == new_pdt && port->mcs == new_mcs) return 0; /* Teardown the old pdt, if there is one */ - switch (port->pdt) { - case DP_PEER_DEVICE_DP_LEGACY_CONV: - case DP_PEER_DEVICE_SST_SINK: - /* - * If the new PDT would also have an i2c bus, don't bother - * with reregistering it - */ - if (new_pdt == DP_PEER_DEVICE_DP_LEGACY_CONV || - new_pdt == DP_PEER_DEVICE_SST_SINK) { - port->pdt = new_pdt; - return 0; - } + if (port->pdt != DP_PEER_DEVICE_NONE) { + if (drm_dp_mst_is_dp_mst_end_device(port->pdt, port->mcs)) { + /* + * If the new PDT would also have an i2c bus, + * don't bother with reregistering it + */ + if (new_pdt != DP_PEER_DEVICE_NONE && + drm_dp_mst_is_dp_mst_end_device(new_pdt, new_mcs)) { + port->pdt = new_pdt; + port->mcs = new_mcs; + return 0; + } - /* remove i2c over sideband */ - drm_dp_mst_unregister_i2c_bus(&port->aux); - break; - case DP_PEER_DEVICE_MST_BRANCHING: - mutex_lock(&mgr->lock); - drm_dp_mst_topology_put_mstb(port->mstb); - port->mstb = NULL; - mutex_unlock(&mgr->lock); - break; + /* remove i2c over sideband */ + drm_dp_mst_unregister_i2c_bus(&port->aux); + } else { + mutex_lock(&mgr->lock); + drm_dp_mst_topology_put_mstb(port->mstb); + port->mstb = NULL; + mutex_unlock(&mgr->lock); + } } port->pdt = new_pdt; - switch (port->pdt) { - case DP_PEER_DEVICE_DP_LEGACY_CONV: - case DP_PEER_DEVICE_SST_SINK: - /* add i2c over sideband */ - ret = drm_dp_mst_register_i2c_bus(&port->aux); - break; + port->mcs = new_mcs; - case DP_PEER_DEVICE_MST_BRANCHING: - lct = drm_dp_calculate_rad(port, rad); - mstb = drm_dp_add_mst_branch_device(lct, rad); - if (!mstb) { - ret = -ENOMEM; - DRM_ERROR("Failed to create MSTB for port %p", port); - goto out; - } + if (port->pdt != DP_PEER_DEVICE_NONE) { + if (drm_dp_mst_is_dp_mst_end_device(port->pdt, port->mcs)) { + /* add i2c over sideband */ + ret = drm_dp_mst_register_i2c_bus(&port->aux); + } else { + lct = drm_dp_calculate_rad(port, rad); + mstb = drm_dp_add_mst_branch_device(lct, rad); + if (!mstb) { + ret = -ENOMEM; + DRM_ERROR("Failed to create MSTB for port %p", + port); + goto out; + } - mutex_lock(&mgr->lock); - port->mstb = mstb; - mstb->mgr = port->mgr; - mstb->port_parent = port; + mutex_lock(&mgr->lock); + port->mstb = mstb; + mstb->mgr = port->mgr; + mstb->port_parent = port; - /* - * Make sure this port's memory allocation stays - * around until its child MSTB releases it - */ - drm_dp_mst_get_port_malloc(port); - mutex_unlock(&mgr->lock); + /* + * Make sure this port's memory allocation stays + * around until its child MSTB releases it + */ + drm_dp_mst_get_port_malloc(port); + mutex_unlock(&mgr->lock); - /* And make sure we send a link address for this */ - ret = 1; - break; + /* And make sure we send a link address for this */ + ret = 1; + } } out: @@ -2154,9 +2171,8 @@ drm_dp_mst_port_add_connector(struct drm_dp_mst_branch *mstb, goto error; } - if ((port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV || - port->pdt == DP_PEER_DEVICE_SST_SINK) && - port->port_num >= DP_MST_LOGICAL_PORT_0) { + if (port->pdt != DP_PEER_DEVICE_NONE && + drm_dp_mst_is_dp_mst_end_device(port->pdt, port->mcs)) { port->cached_edid = drm_get_edid(port->connector, &port->aux.ddc); drm_connector_set_tile_property(port->connector); @@ -2224,6 +2240,7 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb, struct drm_dp_mst_port *port; int old_ddps = 0, ret; u8 new_pdt = DP_PEER_DEVICE_NONE; + bool new_mcs = 0; bool created = false, send_link_addr = false, changed = false; port = drm_dp_get_port(mstb, port_msg->port_number); @@ -2268,7 +2285,7 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb, port->input = port_msg->input_port; if (!port->input) new_pdt = port_msg->peer_device_type; - port->mcs = port_msg->mcs; + new_mcs = port_msg->mcs; port->ddps = port_msg->ddps; port->ldps = port_msg->legacy_device_plug_status; port->dpcd_rev = port_msg->dpcd_revision; @@ -2296,7 +2313,7 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb, } } - ret = drm_dp_port_set_pdt(port, new_pdt); + ret = drm_dp_port_set_pdt(port, new_pdt, new_mcs); if (ret == 1) { send_link_addr = true; } else if (ret < 0) { @@ -2310,7 +2327,8 @@ drm_dp_mst_handle_link_address_port(struct drm_dp_mst_branch *mstb, * we're coming out of suspend. In this case, always resend the link * address if there's an MSTB on this port */ - if (!created && port->pdt == DP_PEER_DEVICE_MST_BRANCHING) + if (!created && port->pdt == DP_PEER_DEVICE_MST_BRANCHING && + port->mcs) send_link_addr = true; if (port->connector) @@ -2347,6 +2365,7 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch *mstb, struct drm_dp_mst_port *port; int old_ddps, old_input, ret, i; u8 new_pdt; + bool new_mcs; bool dowork = false, create_connector = false; port = drm_dp_get_port(mstb, conn_stat->port_number); @@ -2378,7 +2397,6 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch *mstb, old_ddps = port->ddps; old_input = port->input; port->input = conn_stat->input_port; - port->mcs = conn_stat->message_capability_status; port->ldps = conn_stat->legacy_device_plug_status; port->ddps = conn_stat->displayport_device_plug_status; @@ -2391,8 +2409,8 @@ drm_dp_mst_handle_conn_stat(struct drm_dp_mst_branch *mstb, } new_pdt = port->input ? DP_PEER_DEVICE_NONE : conn_stat->peer_device_type; - - ret = drm_dp_port_set_pdt(port, new_pdt); + new_mcs = conn_stat->message_capability_status; + ret = drm_dp_port_set_pdt(port, new_pdt, new_mcs); if (ret == 1) { dowork = true; } else if (ret < 0) { @@ -3481,9 +3499,9 @@ static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8 dp_link_count) int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state) { int ret = 0; - int i = 0; struct drm_dp_mst_branch *mstb = NULL; + mutex_lock(&mgr->payload_lock); mutex_lock(&mgr->lock); if (mst_state == mgr->mst_state) goto out_unlock; @@ -3491,6 +3509,8 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms mgr->mst_state = mst_state; /* set the device into MST mode */ if (mst_state) { + struct drm_dp_payload reset_pay; + WARN_ON(mgr->mst_primary); /* get dpcd info */ @@ -3520,17 +3540,15 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms drm_dp_mst_topology_get_mstb(mgr->mst_primary); ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, - DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); - if (ret < 0) { + DP_MST_EN | + DP_UP_REQ_EN | + DP_UPSTREAM_IS_SRC); + if (ret < 0) goto out_unlock; - } - { - struct drm_dp_payload reset_pay; - reset_pay.start_slot = 0; - reset_pay.num_slots = 0x3f; - drm_dp_dpcd_write_payload(mgr, 0, &reset_pay); - } + reset_pay.start_slot = 0; + reset_pay.num_slots = 0x3f; + drm_dp_dpcd_write_payload(mgr, 0, &reset_pay); queue_work(system_long_wq, &mgr->work); @@ -3542,27 +3560,19 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms /* this can fail if the device is gone */ drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 0); ret = 0; - mutex_lock(&mgr->payload_lock); - memset(mgr->payloads, 0, mgr->max_payloads * sizeof(struct drm_dp_payload)); + memset(mgr->payloads, 0, + mgr->max_payloads * sizeof(mgr->payloads[0])); + memset(mgr->proposed_vcpis, 0, + mgr->max_payloads * sizeof(mgr->proposed_vcpis[0])); mgr->payload_mask = 0; set_bit(0, &mgr->payload_mask); - for (i = 0; i < mgr->max_payloads; i++) { - struct drm_dp_vcpi *vcpi = mgr->proposed_vcpis[i]; - - if (vcpi) { - vcpi->vcpi = 0; - vcpi->num_slots = 0; - } - mgr->proposed_vcpis[i] = NULL; - } mgr->vcpi_mask = 0; - mutex_unlock(&mgr->payload_lock); - mgr->payload_id_table_cleared = false; } out_unlock: mutex_unlock(&mgr->lock); + mutex_unlock(&mgr->payload_lock); if (mstb) drm_dp_mst_topology_put_mstb(mstb); return ret; @@ -3690,7 +3700,7 @@ static bool drm_dp_get_one_sb_msg(struct drm_dp_mst_topology_mgr *mgr, bool up) { int len; u8 replyblock[32]; - int replylen, origlen, curreply; + int replylen, curreply; int ret; struct drm_dp_sideband_msg_rx *msg; int basereg = up ? DP_SIDEBAND_MSG_UP_REQ_BASE : DP_SIDEBAND_MSG_DOWN_REP_BASE; @@ -3710,7 +3720,6 @@ static bool drm_dp_get_one_sb_msg(struct drm_dp_mst_topology_mgr *mgr, bool up) } replylen = msg->curchunk_len + msg->curchunk_hdrlen; - origlen = replylen; replylen -= len; curreply = len; while (replylen > 0) { @@ -3820,7 +3829,8 @@ drm_dp_mst_process_up_req(struct drm_dp_mst_topology_mgr *mgr, else if (msg->req_type == DP_RESOURCE_STATUS_NOTIFY) guid = msg->u.resource_stat.guid; - mstb = drm_dp_get_mst_branch_device_by_guid(mgr, guid); + if (guid) + mstb = drm_dp_get_mst_branch_device_by_guid(mgr, guid); } else { mstb = drm_dp_get_mst_branch_device(mgr, hdr->lct, hdr->rad); } @@ -4007,6 +4017,8 @@ drm_dp_mst_detect_port(struct drm_connector *connector, switch (port->pdt) { case DP_PEER_DEVICE_NONE: case DP_PEER_DEVICE_MST_BRANCHING: + if (!port->mcs) + ret = connector_status_connected; break; case DP_PEER_DEVICE_SST_SINK: @@ -4641,7 +4653,7 @@ drm_dp_delayed_destroy_port(struct drm_dp_mst_port *port) if (port->connector) port->mgr->cbs->destroy_connector(port->mgr, port->connector); - drm_dp_port_set_pdt(port, DP_PEER_DEVICE_NONE); + drm_dp_port_set_pdt(port, DP_PEER_DEVICE_NONE, port->mcs); drm_dp_mst_put_port_malloc(port); } diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 99769d6c9f84..805fb004c8eb 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3211,7 +3211,7 @@ static u8 *drm_find_cea_extension(const struct edid *edid) return cea; } -static const struct drm_display_mode *cea_mode_for_vic(u8 vic) +static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) { BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); diff --git a/drivers/gpu/drm/drm_file.c b/drivers/gpu/drm/drm_file.c index 92d16724f949..1075b3a8b5b1 100644 --- a/drivers/gpu/drm/drm_file.c +++ b/drivers/gpu/drm/drm_file.c @@ -220,7 +220,7 @@ void drm_file_free(struct drm_file *file) DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n", task_pid_nr(current), (long)old_encode_dev(file->minor->kdev->devt), - dev->open_count); + atomic_read(&dev->open_count)); if (drm_core_check_feature(dev, DRIVER_LEGACY) && dev->driver->preclose) @@ -379,7 +379,7 @@ int drm_open(struct inode *inode, struct file *filp) return PTR_ERR(minor); dev = minor->dev; - if (!dev->open_count++) + if (!atomic_fetch_inc(&dev->open_count)) need_setup = 1; /* share address_space across all char-devs of a single device */ @@ -398,7 +398,7 @@ int drm_open(struct inode *inode, struct file *filp) return 0; err_undo: - dev->open_count--; + atomic_dec(&dev->open_count); drm_minor_release(minor); return retcode; } @@ -440,11 +440,11 @@ int drm_release(struct inode *inode, struct file *filp) mutex_lock(&drm_global_mutex); - DRM_DEBUG("open_count = %d\n", dev->open_count); + DRM_DEBUG("open_count = %d\n", atomic_read(&dev->open_count)); drm_close_helper(filp); - if (!--dev->open_count) + if (atomic_dec_and_test(&dev->open_count)) drm_lastclose(dev); mutex_unlock(&drm_global_mutex); @@ -456,6 +456,40 @@ int drm_release(struct inode *inode, struct file *filp) EXPORT_SYMBOL(drm_release); /** + * drm_release_noglobal - release method for DRM file + * @inode: device inode + * @filp: file pointer. + * + * This function may be used by drivers as their &file_operations.release + * method. It frees any resources associated with the open file prior to taking + * the drm_global_mutex, which then calls the &drm_driver.postclose driver + * callback. If this is the last open file for the DRM device also proceeds to + * call the &drm_driver.lastclose driver callback. + * + * RETURNS: + * + * Always succeeds and returns 0. + */ +int drm_release_noglobal(struct inode *inode, struct file *filp) +{ + struct drm_file *file_priv = filp->private_data; + struct drm_minor *minor = file_priv->minor; + struct drm_device *dev = minor->dev; + + drm_close_helper(filp); + + if (atomic_dec_and_mutex_lock(&dev->open_count, &drm_global_mutex)) { + drm_lastclose(dev); + mutex_unlock(&drm_global_mutex); + } + + drm_minor_release(minor); + + return 0; +} +EXPORT_SYMBOL(drm_release_noglobal); + +/** * drm_read - read method for DRM file * @filp: file pointer * @buffer: userspace destination pointer for the read diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index 57564318ceea..57ac94ce9b9e 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -31,6 +31,7 @@ #include <drm/drm_file.h> #include <drm/drm_fourcc.h> #include <drm/drm_framebuffer.h> +#include <drm/drm_gem.h> #include <drm/drm_print.h> #include <drm/drm_util.h> @@ -548,7 +549,128 @@ int drm_mode_getfb(struct drm_device *dev, out: drm_framebuffer_put(fb); + return ret; +} + +/** + * drm_mode_getfb2 - get extended FB info + * @dev: drm device for the ioctl + * @data: data pointer for the ioctl + * @file_priv: drm file for the ioctl call + * + * Lookup the FB given its ID and return info about it. + * + * Called by the user via ioctl. + * + * Returns: + * Zero on success, negative errno on failure. + */ +int drm_mode_getfb2_ioctl(struct drm_device *dev, + void *data, struct drm_file *file_priv) +{ + struct drm_mode_fb_cmd2 *r = data; + struct drm_framebuffer *fb; + unsigned int i; + int ret; + + if (!drm_core_check_feature(dev, DRIVER_MODESET)) + return -EINVAL; + + fb = drm_framebuffer_lookup(dev, file_priv, r->fb_id); + if (!fb) + return -ENOENT; + + /* For multi-plane framebuffers, we require the driver to place the + * GEM objects directly in the drm_framebuffer. For single-plane + * framebuffers, we can fall back to create_handle. + */ + if (!fb->obj[0] && + (fb->format->num_planes > 1 || !fb->funcs->create_handle)) { + ret = -ENODEV; + goto out; + } + + r->height = fb->height; + r->width = fb->width; + r->pixel_format = fb->format->format; + + r->flags = 0; + if (dev->mode_config.allow_fb_modifiers) + r->flags |= DRM_MODE_FB_MODIFIERS; + + for (i = 0; i < ARRAY_SIZE(r->handles); i++) { + r->handles[i] = 0; + r->pitches[i] = 0; + r->offsets[i] = 0; + r->modifier[i] = 0; + } + + for (i = 0; i < fb->format->num_planes; i++) { + r->pitches[i] = fb->pitches[i]; + r->offsets[i] = fb->offsets[i]; + if (dev->mode_config.allow_fb_modifiers) + r->modifier[i] = fb->modifier; + } + + /* GET_FB2() is an unprivileged ioctl so we must not return a + * buffer-handle to non master/root processes! To match GET_FB() + * just return invalid handles (0) for non masters/root + * rather than making GET_FB2() privileged. + */ + if (!drm_is_current_master(file_priv) && !capable(CAP_SYS_ADMIN)) { + ret = 0; + goto out; + } + for (i = 0; i < fb->format->num_planes; i++) { + int j; + + /* If we reuse the same object for multiple planes, also + * return the same handle. + */ + for (j = 0; j < i; j++) { + if (fb->obj[i] == fb->obj[j]) { + r->handles[i] = r->handles[j]; + break; + } + } + + if (r->handles[i]) + continue; + + if (fb->obj[i]) { + ret = drm_gem_handle_create(file_priv, fb->obj[i], + &r->handles[i]); + } else { + WARN_ON(i > 0); + ret = fb->funcs->create_handle(fb, file_priv, + &r->handles[i]); + } + + if (ret != 0) + goto out; + } + +out: + if (ret != 0) { + /* Delete any previously-created handles on failure. */ + for (i = 0; i < ARRAY_SIZE(r->handles); i++) { + int j; + + if (r->handles[i]) + drm_gem_handle_delete(file_priv, r->handles[i]); + + /* Zero out any handles identical to the one we just + * deleted. + */ + for (j = i + 1; j < ARRAY_SIZE(r->handles); j++) { + if (r->handles[j] == r->handles[i]) + r->handles[j] = 0; + } + } + } + + drm_framebuffer_put(fb); return ret; } diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c index a4863326061a..92a11bb42365 100644 --- a/drivers/gpu/drm/drm_gem_vram_helper.c +++ b/drivers/gpu/drm/drm_gem_vram_helper.c @@ -1141,3 +1141,64 @@ void drm_vram_helper_release_mm(struct drm_device *dev) dev->vram_mm = NULL; } EXPORT_SYMBOL(drm_vram_helper_release_mm); + +/* + * Mode-config helpers + */ + +static enum drm_mode_status +drm_vram_helper_mode_valid_internal(struct drm_device *dev, + const struct drm_display_mode *mode, + unsigned long max_bpp) +{ + struct drm_vram_mm *vmm = dev->vram_mm; + unsigned long fbsize, fbpages, max_fbpages; + + if (WARN_ON(!dev->vram_mm)) + return MODE_BAD; + + max_fbpages = (vmm->vram_size / 2) >> PAGE_SHIFT; + + fbsize = mode->hdisplay * mode->vdisplay * max_bpp; + fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE); + + if (fbpages > max_fbpages) + return MODE_MEM; + + return MODE_OK; +} + +/** + * drm_vram_helper_mode_valid - Tests if a display mode's + * framebuffer fits into the available video memory. + * @dev: the DRM device + * @mode: the mode to test + * + * This function tests if enough video memory is available for using the + * specified display mode. Atomic modesetting requires importing the + * designated framebuffer into video memory before evicting the active + * one. Hence, any framebuffer may consume at most half of the available + * VRAM. Display modes that require a larger framebuffer can not be used, + * even if the CRTC does support them. Each framebuffer is assumed to + * have 32-bit color depth. + * + * Note: + * The function can only test if the display mode is supported in + * general. If there are too many framebuffers pinned to video memory, + * a display mode may still not be usable in practice. The color depth of + * 32-bit fits all current use case. A more flexible test can be added + * when necessary. + * + * Returns: + * MODE_OK if the display mode is supported, or an error code of type + * enum drm_mode_status otherwise. + */ +enum drm_mode_status +drm_vram_helper_mode_valid(struct drm_device *dev, + const struct drm_display_mode *mode) +{ + static const unsigned long max_bpp = 4; /* DRM_FORMAT_XRGB8888 */ + + return drm_vram_helper_mode_valid_internal(dev, mode, max_bpp); +} +EXPORT_SYMBOL(drm_vram_helper_mode_valid); diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 5afb39688b55..9e41972c4bbc 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -671,6 +671,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_connector_property_set_ioctl, DRM_MASTER), DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, 0), DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, 0), + DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB2, drm_mode_getfb2_ioctl, 0), DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb_ioctl, 0), DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB2, drm_mode_addfb2_ioctl, 0), DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb_ioctl, 0), diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c index 16bff1be4b8a..558baf989f5a 100644 --- a/drivers/gpu/drm/drm_mipi_dbi.c +++ b/drivers/gpu/drm/drm_mipi_dbi.c @@ -24,7 +24,6 @@ #include <drm/drm_modes.h> #include <drm/drm_probe_helper.h> #include <drm/drm_rect.h> -#include <drm/drm_vblank.h> #include <video/mipi_display.h> #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */ @@ -238,6 +237,23 @@ int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb, } EXPORT_SYMBOL(mipi_dbi_buf_copy); +static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev, + unsigned int xs, unsigned int xe, + unsigned int ys, unsigned int ye) +{ + struct mipi_dbi *dbi = &dbidev->dbi; + + xs += dbidev->left_offset; + xe += dbidev->left_offset; + ys += dbidev->top_offset; + ye += dbidev->top_offset; + + mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff, + xs & 0xff, (xe >> 8) & 0xff, xe & 0xff); + mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff, + ys & 0xff, (ye >> 8) & 0xff, ye & 0xff); +} + static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) { struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0); @@ -271,12 +287,8 @@ static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) tr = cma_obj->vaddr; } - mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, - (rect->x1 >> 8) & 0xff, rect->x1 & 0xff, - ((rect->x2 - 1) >> 8) & 0xff, (rect->x2 - 1) & 0xff); - mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, - (rect->y1 >> 8) & 0xff, rect->y1 & 0xff, - ((rect->y2 - 1) >> 8) & 0xff, (rect->y2 - 1) & 0xff); + mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1, + rect->y2 - 1); ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr, width * height * 2); @@ -299,18 +311,10 @@ void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *old_state) { struct drm_plane_state *state = pipe->plane.state; - struct drm_crtc *crtc = &pipe->crtc; struct drm_rect rect; if (drm_atomic_helper_damage_merged(old_state, state, &rect)) mipi_dbi_fb_dirty(state->fb, &rect); - - if (crtc->state->event) { - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, crtc->state->event); - spin_unlock_irq(&crtc->dev->event_lock); - crtc->state->event = NULL; - } } EXPORT_SYMBOL(mipi_dbi_pipe_update); @@ -366,10 +370,7 @@ static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev) memset(dbidev->tx_buf, 0, len); - mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0, - ((width - 1) >> 8) & 0xFF, (width - 1) & 0xFF); - mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0, - ((height - 1) >> 8) & 0xFF, (height - 1) & 0xFF); + mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1); mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, (u8 *)dbidev->tx_buf, len); diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c index f2e43d341980..c6bb98729a26 100644 --- a/drivers/gpu/drm/drm_pci.c +++ b/drivers/gpu/drm/drm_pci.c @@ -51,8 +51,6 @@ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align) { drm_dma_handle_t *dmah; - unsigned long addr; - size_t sz; /* pci_alloc_consistent only guarantees alignment to the smallest * PAGE_SIZE order which is greater than or equal to the requested size. @@ -68,47 +66,18 @@ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t ali dmah->size = size; dmah->vaddr = dma_alloc_coherent(&dev->pdev->dev, size, &dmah->busaddr, - GFP_KERNEL | __GFP_COMP); + GFP_KERNEL); if (dmah->vaddr == NULL) { kfree(dmah); return NULL; } - /* XXX - Is virt_to_page() legal for consistent mem? */ - /* Reserve */ - for (addr = (unsigned long)dmah->vaddr, sz = size; - sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { - SetPageReserved(virt_to_page((void *)addr)); - } - return dmah; } EXPORT_SYMBOL(drm_pci_alloc); -/* - * Free a PCI consistent memory block without freeing its descriptor. - * - * This function is for internal use in the Linux-specific DRM core code. - */ -void __drm_legacy_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah) -{ - unsigned long addr; - size_t sz; - - if (dmah->vaddr) { - /* XXX - Is virt_to_page() legal for consistent mem? */ - /* Unreserve */ - for (addr = (unsigned long)dmah->vaddr, sz = dmah->size; - sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { - ClearPageReserved(virt_to_page((void *)addr)); - } - dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr, - dmah->busaddr); - } -} - /** * drm_pci_free - Free a PCI consistent memory block * @dev: DRM device @@ -119,7 +88,8 @@ void __drm_legacy_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah) */ void drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah) { - __drm_legacy_pci_free(dev, dmah); + dma_free_coherent(&dev->pdev->dev, dmah->size, dmah->vaddr, + dmah->busaddr); kfree(dmah); } diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c index 669c93fe2500..42d46414f767 100644 --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@ -43,27 +43,66 @@ * - Signal a syncobj (set a trivially signaled fence) * - Wait for a syncobj's fence to appear and be signaled * + * The syncobj userspace API also provides operations to manipulate a syncobj + * in terms of a timeline of struct &dma_fence_chain rather than a single + * struct &dma_fence, through the following operations: + * + * - Signal a given point on the timeline + * - Wait for a given point to appear and/or be signaled + * - Import and export from/to a given point of a timeline + * * At it's core, a syncobj is simply a wrapper around a pointer to a struct * &dma_fence which may be NULL. * When a syncobj is first created, its pointer is either NULL or a pointer * to an already signaled fence depending on whether the * &DRM_SYNCOBJ_CREATE_SIGNALED flag is passed to * &DRM_IOCTL_SYNCOBJ_CREATE. - * When GPU work which signals a syncobj is enqueued in a DRM driver, - * the syncobj fence is replaced with a fence which will be signaled by the - * completion of that work. - * When GPU work which waits on a syncobj is enqueued in a DRM driver, the - * driver retrieves syncobj's current fence at the time the work is enqueued - * waits on that fence before submitting the work to hardware. - * If the syncobj's fence is NULL, the enqueue operation is expected to fail. - * All manipulation of the syncobjs's fence happens in terms of the current - * fence at the time the ioctl is called by userspace regardless of whether - * that operation is an immediate host-side operation (signal or reset) or - * or an operation which is enqueued in some driver queue. - * &DRM_IOCTL_SYNCOBJ_RESET and &DRM_IOCTL_SYNCOBJ_SIGNAL can be used to - * manipulate a syncobj from the host by resetting its pointer to NULL or + * + * If the syncobj is considered as a binary (its state is either signaled or + * unsignaled) primitive, when GPU work is enqueued in a DRM driver to signal + * the syncobj, the syncobj's fence is replaced with a fence which will be + * signaled by the completion of that work. + * If the syncobj is considered as a timeline primitive, when GPU work is + * enqueued in a DRM driver to signal the a given point of the syncobj, a new + * struct &dma_fence_chain pointing to the DRM driver's fence and also + * pointing to the previous fence that was in the syncobj. The new struct + * &dma_fence_chain fence replace the syncobj's fence and will be signaled by + * completion of the DRM driver's work and also any work associated with the + * fence previously in the syncobj. + * + * When GPU work which waits on a syncobj is enqueued in a DRM driver, at the + * time the work is enqueued, it waits on the syncobj's fence before + * submitting the work to hardware. That fence is either : + * + * - The syncobj's current fence if the syncobj is considered as a binary + * primitive. + * - The struct &dma_fence associated with a given point if the syncobj is + * considered as a timeline primitive. + * + * If the syncobj's fence is NULL or not present in the syncobj's timeline, + * the enqueue operation is expected to fail. + * + * With binary syncobj, all manipulation of the syncobjs's fence happens in + * terms of the current fence at the time the ioctl is called by userspace + * regardless of whether that operation is an immediate host-side operation + * (signal or reset) or or an operation which is enqueued in some driver + * queue. &DRM_IOCTL_SYNCOBJ_RESET and &DRM_IOCTL_SYNCOBJ_SIGNAL can be used + * to manipulate a syncobj from the host by resetting its pointer to NULL or * setting its pointer to a fence which is already signaled. * + * With a timeline syncobj, all manipulation of the synobj's fence happens in + * terms of a u64 value referring to point in the timeline. See + * dma_fence_chain_find_seqno() to see how a given point is found in the + * timeline. + * + * Note that applications should be careful to always use timeline set of + * ioctl() when dealing with syncobj considered as timeline. Using a binary + * set of ioctl() with a syncobj considered as timeline could result incorrect + * synchronization. The use of binary syncobj is supported through the + * timeline set of ioctl() by using a point value of 0, this will reproduce + * the behavior of the binary set of ioctl() (for example replace the + * syncobj's fence when signaling). + * * * Host-side wait on syncobjs * -------------------------- @@ -87,6 +126,16 @@ * synchronize between the two. * This requirement is inherited from the Vulkan fence API. * + * Similarly, &DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT takes an array of syncobj + * handles as well as an array of u64 points and does a host-side wait on all + * of syncobj fences at the given points simultaneously. + * + * &DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT also adds the ability to wait for a given + * fence to materialize on the timeline without waiting for the fence to be + * signaled by using the &DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE flag. This + * requirement is inherited from the wait-before-signal behavior required by + * the Vulkan timeline semaphore API. + * * * Import/export of syncobjs * ------------------------- @@ -120,6 +169,18 @@ * Because sync files are immutable, resetting or signaling the syncobj * will not affect any sync files whose fences have been imported into the * syncobj. + * + * + * Import/export of timeline points in timeline syncobjs + * ----------------------------------------------------- + * + * &DRM_IOCTL_SYNCOBJ_TRANSFER provides a mechanism to transfer a struct + * &dma_fence_chain of a syncobj at a given u64 point to another u64 point + * into another syncobj. + * + * Note that if you want to transfer a struct &dma_fence_chain from a given + * point on a timeline syncobj from/into a binary syncobj, you can use the + * point 0 to mean take/replace the fence in the syncobj. */ #include <linux/anon_inodes.h> diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c index 1659b13b178c..27a99c486f02 100644 --- a/drivers/gpu/drm/drm_vblank.c +++ b/drivers/gpu/drm/drm_vblank.c @@ -69,6 +69,12 @@ * &drm_driver.max_vblank_count. In that case the vblank core only disables the * vblanks after a timer has expired, which can be configured through the * ``vblankoffdelay`` module parameter. + * + * Drivers for hardware without support for vertical-blanking interrupts + * must not call drm_vblank_init(). For such drivers, atomic helpers will + * automatically generate fake vblank events as part of the display update. + * This functionality also can be controlled by the driver by enabling and + * disabling struct drm_crtc_state.no_vblank. */ /* Retry timestamp calculation up to 3 times to satisfy @@ -502,6 +508,28 @@ err: EXPORT_SYMBOL(drm_vblank_init); /** + * drm_dev_has_vblank - test if vblanking has been initialized for + * a device + * @dev: the device + * + * Drivers may call this function to test if vblank support is + * initialized for a device. For most hardware this means that vblanking + * can also be enabled. + * + * Atomic helpers use this function to initialize + * &drm_crtc_state.no_vblank. See also drm_atomic_helper_check_modeset(). + * + * Returns: + * True if vblanking has been initialized for the given device, false + * otherwise. + */ +bool drm_dev_has_vblank(const struct drm_device *dev) +{ + return dev->num_crtcs != 0; +} +EXPORT_SYMBOL(drm_dev_has_vblank); + +/** * drm_crtc_vblank_waitqueue - get vblank waitqueue for the CRTC * @crtc: which CRTC's vblank waitqueue to retrieve * diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index 52e87e4869a5..64619fe90046 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -269,8 +269,6 @@ static void drm_vm_shm_close(struct vm_area_struct *vma) } if (!found_maps) { - drm_dma_handle_t dmah; - switch (map->type) { case _DRM_REGISTERS: case _DRM_FRAME_BUFFER: @@ -284,10 +282,10 @@ static void drm_vm_shm_close(struct vm_area_struct *vma) case _DRM_SCATTER_GATHER: break; case _DRM_CONSISTENT: - dmah.vaddr = map->handle; - dmah.busaddr = map->offset; - dmah.size = map->size; - __drm_legacy_pci_free(dev, &dmah); + dma_free_coherent(&dev->pdev->dev, + map->size, + map->handle, + map->offset); break; } kfree(map); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index 76ecdf8bd31c..6b43c1c94e8f 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -283,11 +283,6 @@ static int etnaviv_ioctl_gem_new(struct drm_device *dev, void *data, args->flags, &args->handle); } -#define TS(t) ((struct timespec){ \ - .tv_sec = (t).tv_sec, \ - .tv_nsec = (t).tv_nsec \ -}) - static int etnaviv_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, struct drm_file *file) { @@ -302,7 +297,7 @@ static int etnaviv_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, if (!obj) return -ENOENT; - ret = etnaviv_gem_cpu_prep(obj, args->op, &TS(args->timeout)); + ret = etnaviv_gem_cpu_prep(obj, args->op, &args->timeout); drm_gem_object_put_unlocked(obj); @@ -355,7 +350,7 @@ static int etnaviv_ioctl_wait_fence(struct drm_device *dev, void *data, { struct drm_etnaviv_wait_fence *args = data; struct etnaviv_drm_private *priv = dev->dev_private; - struct timespec *timeout = &TS(args->timeout); + struct drm_etnaviv_timespec *timeout = &args->timeout; struct etnaviv_gpu *gpu; if (args->flags & ~(ETNA_WAIT_NONBLOCK)) @@ -404,7 +399,7 @@ static int etnaviv_ioctl_gem_wait(struct drm_device *dev, void *data, { struct etnaviv_drm_private *priv = dev->dev_private; struct drm_etnaviv_gem_wait *args = data; - struct timespec *timeout = &TS(args->timeout); + struct drm_etnaviv_timespec *timeout = &args->timeout; struct drm_gem_object *obj; struct etnaviv_gpu *gpu; int ret; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h b/drivers/gpu/drm/etnaviv/etnaviv_drv.h index 32cfa5a48d42..efc656efeb0f 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h @@ -61,7 +61,7 @@ int etnaviv_gem_prime_pin(struct drm_gem_object *obj); void etnaviv_gem_prime_unpin(struct drm_gem_object *obj); void *etnaviv_gem_vmap(struct drm_gem_object *obj); int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op, - struct timespec *timeout); + struct drm_etnaviv_timespec *timeout); int etnaviv_gem_cpu_fini(struct drm_gem_object *obj); void etnaviv_gem_free_object(struct drm_gem_object *obj); int etnaviv_gem_new_handle(struct drm_device *dev, struct drm_file *file, @@ -107,11 +107,12 @@ static inline size_t size_vstruct(size_t nelem, size_t elem_size, size_t base) * between the specified timeout and the current CLOCK_MONOTONIC time. */ static inline unsigned long etnaviv_timeout_to_jiffies( - const struct timespec *timeout) + const struct drm_etnaviv_timespec *timeout) { - struct timespec64 ts, to; - - to = timespec_to_timespec64(*timeout); + struct timespec64 ts, to = { + .tv_sec = timeout->tv_sec, + .tv_nsec = timeout->tv_nsec, + }; ktime_get_ts64(&ts); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnaviv/etnaviv_gem.c index cb1faaac380a..6adea180d629 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c @@ -373,7 +373,7 @@ static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op) } int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op, - struct timespec *timeout) + struct drm_etnaviv_timespec *timeout) { struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj); struct drm_device *dev = obj->dev; @@ -431,7 +431,7 @@ int etnaviv_gem_cpu_fini(struct drm_gem_object *obj) } int etnaviv_gem_wait_bo(struct etnaviv_gpu *gpu, struct drm_gem_object *obj, - struct timespec *timeout) + struct drm_etnaviv_timespec *timeout) { struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.h b/drivers/gpu/drm/etnaviv/etnaviv_gem.h index d6270acce619..6b68fe16041b 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.h @@ -112,7 +112,7 @@ struct etnaviv_gem_submit { void etnaviv_submit_put(struct etnaviv_gem_submit * submit); int etnaviv_gem_wait_bo(struct etnaviv_gpu *gpu, struct drm_gem_object *obj, - struct timespec *timeout); + struct drm_etnaviv_timespec *timeout); int etnaviv_gem_new_private(struct drm_device *dev, size_t size, u32 flags, const struct etnaviv_gem_ops *ops, struct etnaviv_gem_object **res); void etnaviv_gem_obj_add(struct drm_device *dev, struct drm_gem_object *obj); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index d47d1a8e0219..799ec20b267d 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1132,7 +1132,7 @@ static void event_free(struct etnaviv_gpu *gpu, unsigned int event) * Cmdstream submission/retirement: */ int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, - u32 id, struct timespec *timeout) + u32 id, struct drm_etnaviv_timespec *timeout) { struct dma_fence *fence; int ret; @@ -1179,7 +1179,8 @@ int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, * that lock in this function while waiting. */ int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, - struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout) + struct etnaviv_gem_object *etnaviv_obj, + struct drm_etnaviv_timespec *timeout) { unsigned long remaining; long ret; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h index 8f9bd4edc96a..97bb48042b4d 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h @@ -169,9 +169,10 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m); void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu); void etnaviv_gpu_retire(struct etnaviv_gpu *gpu); int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, - u32 fence, struct timespec *timeout); + u32 fence, struct drm_etnaviv_timespec *timeout); int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, - struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout); + struct etnaviv_gem_object *etnaviv_obj, + struct drm_etnaviv_timespec *timeout); struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit); int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu); void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu); diff --git a/drivers/gpu/drm/gma500/gtt.c b/drivers/gpu/drm/gma500/gtt.c index afaf4bea21cf..9278bcfad1bf 100644 --- a/drivers/gpu/drm/gma500/gtt.c +++ b/drivers/gpu/drm/gma500/gtt.c @@ -503,7 +503,7 @@ int psb_gtt_init(struct drm_device *dev, int resume) * Map the GTT and the stolen memory area */ if (!resume) - dev_priv->gtt_map = ioremap_nocache(pg->gtt_phys_start, + dev_priv->gtt_map = ioremap(pg->gtt_phys_start, gtt_pages << PAGE_SHIFT); if (!dev_priv->gtt_map) { dev_err(dev->dev, "Failure to map gtt.\n"); diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c index 52591416f8fe..6956c8e7501c 100644 --- a/drivers/gpu/drm/gma500/psb_drv.c +++ b/drivers/gpu/drm/gma500/psb_drv.c @@ -256,7 +256,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags) PSB_AUX_RESOURCE); resource_len = pci_resource_len(dev_priv->aux_pdev, PSB_AUX_RESOURCE); - dev_priv->aux_reg = ioremap_nocache(resource_start, + dev_priv->aux_reg = ioremap(resource_start, resource_len); if (!dev_priv->aux_reg) goto out_err; diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c index 11d1b0761c9a..4a8a4cfb4b75 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -213,7 +213,7 @@ static int hibmc_hw_map(struct hibmc_drm_private *priv) ioaddr = pci_resource_start(pdev, 1); iosize = pci_resource_len(pdev, 1); - priv->mmio = devm_ioremap_nocache(dev->dev, ioaddr, iosize); + priv->mmio = devm_ioremap(dev->dev, ioaddr, iosize); if (!priv->mmio) { DRM_ERROR("Cannot map mmio region\n"); return -ENOMEM; diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c index 50b988fdd5cc..99397ac3b363 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c @@ -54,6 +54,7 @@ int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev, } const struct drm_mode_config_funcs hibmc_mode_funcs = { + .mode_valid = drm_vram_helper_mode_valid, .atomic_check = drm_atomic_helper_check, .atomic_commit = drm_atomic_helper_commit, .fb_create = drm_gem_fb_create, diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index b314d44ded5e..9db81b9ac0f3 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -82,6 +82,7 @@ gt-y += \ gt/gen8_ppgtt.o \ gt/intel_breadcrumbs.o \ gt/intel_context.o \ + gt/intel_context_param.o \ gt/intel_context_sseu.o \ gt/intel_engine_cs.o \ gt/intel_engine_heartbeat.o \ @@ -301,7 +302,7 @@ extra-$(CONFIG_DRM_I915_WERROR) += \ $(shell cd $(srctree)/$(src) && find * -name '*.h'))) quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@) - cmd_hdrtest = $(CC) $(c_flags) -S -o /dev/null -x c /dev/null -include $<; touch $@ + cmd_hdrtest = $(CC) $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; touch $@ $(obj)/%.hdrtest: $(src)/%.h FORCE $(call if_changed_dep,hdrtest) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index d0f7419fb02b..d842e280699d 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1718,9 +1718,8 @@ static void icl_dsi_add_properties(struct intel_connector *connector) connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; - connector->base.display_info.panel_orientation = - intel_dsi_get_panel_orientation(connector); - drm_connector_init_panel_orientation_property(&connector->base, + drm_connector_set_panel_orientation_with_quirk(&connector->base, + intel_dsi_get_panel_orientation(connector), connector->panel.fixed_mode->hdisplay, connector->panel.fixed_mode->vdisplay); } diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 30fb7c887ff0..19bf206037c2 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -844,7 +844,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, struct intel_crtc *crtc; int ret; - crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); + crtc = intel_get_first_crtc(dev_priv); if (!crtc) return; diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 146c2b9bb7fb..0741d643455b 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -525,7 +525,8 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) * FIXME is this guaranteed to clear * immediately or should we poll for it? */ - WARN_ON(intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); } static void vlv_set_cdclk(struct drm_i915_private *dev_priv, @@ -727,12 +728,13 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, u32 val; int ret; - if (WARN((intel_de_read(dev_priv, LCPLL_CTL) & - (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | - LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | - LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | - LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, - "trying to change cdclk frequency with cdclk not enabled\n")) + if (drm_WARN(&dev_priv->drm, + (intel_de_read(dev_priv, LCPLL_CTL) & + (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | + LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | + LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | + LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, + "trying to change cdclk frequency with cdclk not enabled\n")) return; ret = sandybridge_pcode_write(dev_priv, @@ -842,15 +844,16 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, if ((val & LCPLL_PLL_ENABLE) == 0) return; - if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) + if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) return; val = intel_de_read(dev_priv, DPLL_CTRL1); - if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | - DPLL_CTRL1_SSC(SKL_DPLL0) | - DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != - DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) + if (drm_WARN_ON(&dev_priv->drm, + (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | + DPLL_CTRL1_SSC(SKL_DPLL0) | + DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != + DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) return; switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { @@ -952,7 +955,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) { u32 val; - WARN_ON(vco != 8100000 && vco != 8640000); + drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); /* * We always enable DPLL0 with the lowest link rate possible, but still @@ -1017,7 +1020,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, * use the corresponding VCO freq as that always leads to using the * minimum 308MHz CDCLK. */ - WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000); + drm_WARN_ON_ONCE(&dev_priv->drm, + IS_SKYLAKE(dev_priv) && vco == 8640000); ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, SKL_CDCLK_PREPARE_FOR_CHANGE, @@ -1032,8 +1036,9 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, /* Choose frequency for this cdclk */ switch (cdclk) { default: - WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); - WARN_ON(vco != 0); + drm_WARN_ON(&dev_priv->drm, + cdclk != dev_priv->cdclk.hw.bypass); + drm_WARN_ON(&dev_priv->drm, vco != 0); /* fall through */ case 308571: case 337500: @@ -1235,8 +1240,9 @@ static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) table[i].cdclk >= min_cdclk) return table[i].cdclk; - WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n", - min_cdclk, dev_priv->cdclk.hw.ref); + drm_WARN(&dev_priv->drm, 1, + "Cannot satisfy minimum cdclk %d with refclk %u\n", + min_cdclk, dev_priv->cdclk.hw.ref); return 0; } @@ -1253,8 +1259,8 @@ static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) table[i].cdclk == cdclk) return dev_priv->cdclk.hw.ref * table[i].ratio; - WARN(1, "cdclk %d not valid for refclk %u\n", - cdclk, dev_priv->cdclk.hw.ref); + drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", + cdclk, dev_priv->cdclk.hw.ref); return 0; } @@ -1399,15 +1405,17 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, div = 2; break; case BXT_CDCLK_CD2X_DIV_SEL_1_5: - WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, - "Unsupported divider\n"); + drm_WARN(&dev_priv->drm, + IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, + "Unsupported divider\n"); div = 3; break; case BXT_CDCLK_CD2X_DIV_SEL_2: div = 4; break; case BXT_CDCLK_CD2X_DIV_SEL_4: - WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n"); + drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, + "Unsupported divider\n"); div = 8; break; default: @@ -1547,22 +1555,25 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, /* cdclk = vco / 2 / div{1,1.5,2,4} */ switch (DIV_ROUND_CLOSEST(vco, cdclk)) { default: - WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); - WARN_ON(vco != 0); + drm_WARN_ON(&dev_priv->drm, + cdclk != dev_priv->cdclk.hw.bypass); + drm_WARN_ON(&dev_priv->drm, vco != 0); /* fall through */ case 2: divider = BXT_CDCLK_CD2X_DIV_SEL_1; break; case 3: - WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, - "Unsupported divider\n"); + drm_WARN(&dev_priv->drm, + IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, + "Unsupported divider\n"); divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; break; case 4: divider = BXT_CDCLK_CD2X_DIV_SEL_2; break; case 8: - WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n"); + drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, + "Unsupported divider\n"); divider = BXT_CDCLK_CD2X_DIV_SEL_4; break; } @@ -1860,15 +1871,16 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) return; - if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk)) return; intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to"); dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe); - if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), - "cdclk state doesn't match!\n")) { + if (drm_WARN(&dev_priv->drm, + intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), + "cdclk state doesn't match!\n")) { intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]"); intel_dump_cdclk_config(cdclk_config, "[sw state]"); } @@ -1897,7 +1909,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) if (pipe == INVALID_PIPE || old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { - WARN_ON(!new_cdclk_state->base.changed); + drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); } @@ -1926,7 +1938,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) if (pipe != INVALID_PIPE && old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { - WARN_ON(!new_cdclk_state->base.changed); + drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); } @@ -2550,7 +2562,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) int max_cdclk, vco; vco = dev_priv->skl_preferred_vco_freq; - WARN_ON(vco != 8100000 && vco != 8640000); + drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); /* * Use the lower (vco 8640) cdclk values as a @@ -2809,8 +2821,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) else if (IS_I845G(dev_priv)) dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; else { /* 830 */ - WARN(!IS_I830(dev_priv), - "Unknown platform. Assuming 133 MHz CDCLK\n"); + drm_WARN(&dev_priv->drm, !IS_I830(dev_priv), + "Unknown platform. Assuming 133 MHz CDCLK\n"); dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; } } diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index d44bd8287801..36dd52d2a9ee 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -392,6 +392,13 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state intel_de_write(dev_priv, CGM_PIPE_MODE(pipe), crtc_state->cgm_mode); } +static u32 i9xx_lut_8(const struct drm_color_lut *color) +{ + return drm_color_lut_extract(color->red, 8) << 16 | + drm_color_lut_extract(color->green, 8) << 8 | + drm_color_lut_extract(color->blue, 8); +} + /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */ static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color) { @@ -435,10 +442,7 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state, const struct drm_color_lut *lut = blob->data; for (i = 0; i < 256; i++) { - u32 word = - (drm_color_lut_extract(lut[i].red, 8) << 16) | - (drm_color_lut_extract(lut[i].green, 8) << 8) | - drm_color_lut_extract(lut[i].blue, 8); + u32 word = i9xx_lut_8(&lut[i]); if (HAS_GMCH(dev_priv)) intel_de_write(dev_priv, PALETTE(pipe, i), diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 45ecc7d9c829..f49c98f6cb7e 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -1046,6 +1046,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv) !dmi_check_system(intel_spurious_crt_detect)) { crt->base.hpd_pin = HPD_CRT; crt->base.hotplug = intel_encoder_hotplug; + intel_connector->polled = DRM_CONNECTOR_POLL_HPD; } else { intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; } diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ff292dfe2dd3..9f7d1d7189ae 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1006,18 +1006,18 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder) intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); default_entry = 6; } else { - WARN(1, "ddi translation table missing\n"); + drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); return 0; } - if (WARN_ON_ONCE(n_entries == 0)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) return 0; level = intel_bios_hdmi_level_shift(encoder); if (level < 0) level = default_entry; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; return level; @@ -1075,9 +1075,9 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); - if (WARN_ON_ONCE(!ddi_translations)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; /* If we're boosting the current, set bit 31 of trans1 */ @@ -1208,7 +1208,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, /* Configure Port Clock Select */ ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); - WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); + drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); /* Start the training iterating through available voltages and emphasis, * testing each value twice. */ @@ -1317,8 +1317,9 @@ intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) } if (num_encoders != 1) - WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, - pipe_name(crtc->pipe)); + drm_WARN(dev, 1, "%d encoders on crtc for pipe %c\n", + num_encoders, + pipe_name(crtc->pipe)); BUG_ON(ret == NULL); return ret; @@ -1476,7 +1477,7 @@ int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; - if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) + if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0)) return 0; return dco_freq / (p0 * p1 * p2 * 5); @@ -1664,7 +1665,7 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder, link_clock = 405000; break; default: - WARN(1, "Unsupported link rate\n"); + drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n"); break; } link_clock *= 2; @@ -1756,12 +1757,12 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder, else if (pll == SPLL_FREQ_2700MHz) link_clock = 270000; else { - WARN(1, "bad spll freq\n"); + drm_WARN(&dev_priv->drm, 1, "bad spll freq\n"); return; } break; default: - WARN(1, "bad port clock sel\n"); + drm_WARN(&dev_priv->drm, 1, "bad port clock sel\n"); return; } @@ -1822,7 +1823,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, if (!intel_crtc_has_dp_encoder(crtc_state)) return; - WARN_ON(transcoder_is_dsi(cpu_transcoder)); + drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); temp = DP_MSA_MISC_SYNC_CLOCK; @@ -1845,8 +1846,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, } /* nonsense combination */ - WARN_ON(crtc_state->limited_color_range && - crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); + drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); if (crtc_state->limited_color_range) temp |= DP_MSA_MISC_COLOR_CEA_RGB; @@ -1962,7 +1963,8 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state) enum transcoder master; master = crtc_state->mst_master_transcoder; - WARN_ON(master == INVALID_TRANSCODER); + drm_WARN_ON(&dev_priv->drm, + master == INVALID_TRANSCODER); temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); } } else { @@ -2043,10 +2045,11 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, wakeref = intel_display_power_get_if_enabled(dev_priv, intel_encoder->power_domain); - if (WARN_ON(!wakeref)) + if (drm_WARN_ON(dev, !wakeref)) return -ENXIO; - if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) { + if (drm_WARN_ON(dev, + !intel_encoder->get_hw_state(intel_encoder, &pipe))) { ret = -EIO; goto out; } @@ -2283,7 +2286,8 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, * happen since fake-MST encoders don't set their get_power_domains() * hook. */ - if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) + if (drm_WARN_ON(&dev_priv->drm, + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) return; dig_port = enc_to_dig_port(encoder); @@ -2381,9 +2385,9 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, else ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); - if (WARN_ON_ONCE(!ddi_translations)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; iboost = ddi_translations[level].i_boost; @@ -2416,9 +2420,9 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, else ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); - if (WARN_ON_ONCE(!ddi_translations)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; bxt_ddi_phy_set_signal_level(dev_priv, port, @@ -2468,9 +2472,10 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); } - if (WARN_ON(n_entries < 1)) + if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) n_entries = 1; - if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) + if (drm_WARN_ON(&dev_priv->drm, + n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) n_entries = ARRAY_SIZE(index_to_dp_signal_levels); return index_to_dp_signal_levels[n_entries - 1] & @@ -2513,9 +2518,9 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, else ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); - if (WARN_ON_ONCE(!ddi_translations)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ @@ -3047,7 +3052,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, mutex_lock(&dev_priv->dpll_lock); val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); - WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); + drm_WARN_ON(&dev_priv->drm, + (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { /* @@ -3106,7 +3112,7 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, * Punt on the case now where clock is gated, but it would * be needed by the port. Something else is really broken then. */ - if (WARN_ON(ddi_clk_needed)) + if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) continue; DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", @@ -3138,7 +3144,7 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) * In the unlikely case that BIOS enables DP in MST mode, just * warn since our MST HW readout is incomplete. */ - if (WARN_ON(is_mst)) + if (drm_WARN_ON(&dev_priv->drm, is_mst)) return; } @@ -3157,7 +3163,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) if (other_encoder == encoder) continue; - if (WARN_ON(port_mask & BIT(other_encoder->port))) + if (drm_WARN_ON(&dev_priv->drm, + port_mask & BIT(other_encoder->port))) return; } /* @@ -3179,7 +3186,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, u32 val; const struct intel_shared_dpll *pll = crtc_state->shared_dpll; - if (WARN_ON(!pll)) + if (drm_WARN_ON(&dev_priv->drm, !pll)) return; mutex_lock(&dev_priv->dpll_lock); @@ -3285,7 +3292,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, switch (pin_assignment) { case 0x0: - WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY); + drm_WARN_ON(&dev_priv->drm, + intel_dig_port->tc_mode != TC_PORT_LEGACY); if (width == 1) { ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; } else { @@ -3542,9 +3550,10 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, int level = intel_ddi_dp_level(intel_dp); if (INTEL_GEN(dev_priv) < 11) - WARN_ON(is_mst && (port == PORT_A || port == PORT_E)); + drm_WARN_ON(&dev_priv->drm, + is_mst && (port == PORT_A || port == PORT_E)); else - WARN_ON(is_mst && port == PORT_A); + drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count, is_mst); @@ -3683,7 +3692,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder, * the DP link parameteres */ - WARN_ON(crtc_state->has_pch_encoder); + drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); if (INTEL_GEN(dev_priv) >= 11) icl_map_plls_to_ports(encoder, crtc_state); @@ -3958,9 +3967,9 @@ gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, [PORT_E] = TRANSCODER_A, }; - WARN_ON(INTEL_GEN(dev_priv) < 9); + drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); - if (WARN_ON(port < PORT_A || port > PORT_E)) + if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) port = PORT_A; return CHICKEN_TRANS(trans[port]); @@ -4258,7 +4267,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, u32 temp, flags = 0; /* XXX: DSI transcoder paranoia */ - if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) + if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) return; intel_dsc_get_config(encoder, pipe_config); @@ -4661,7 +4670,8 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, crtc_state = to_intel_crtc_state(crtc->base.state); - WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); + drm_WARN_ON(&dev_priv->drm, + !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); if (!crtc_state->hw.active) return 0; @@ -4913,7 +4923,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->update_complete = intel_ddi_update_complete; } - WARN_ON(port > PORT_I); + drm_WARN_ON(&dev_priv->drm, port > PORT_I); intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + port - PORT_A; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 86ca35d160b8..6c373594d9e5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -203,9 +203,9 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv, val = vlv_cck_read(dev_priv, reg); divider = val & CCK_FREQUENCY_VALUES; - WARN((val & CCK_FREQUENCY_STATUS) != - (divider << CCK_FREQUENCY_STATUS_SHIFT), - "%s change in progress\n", name); + drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != + (divider << CCK_FREQUENCY_STATUS_SHIFT), + "%s change in progress\n", name); return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); } @@ -249,6 +249,15 @@ intel_fdi_link_freq(struct drm_i915_private *dev_priv, return dev_priv->fdi_pll_freq; } +static bool +has_transcoder(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) +{ + if (cpu_transcoder == TRANSCODER_EDP) + return HAS_TRANSCODER_EDP(dev_priv); + else + return INTEL_INFO(dev_priv)->pipe_mask & BIT(cpu_transcoder); +} + static const struct intel_limit intel_limits_i8xx_dac = { .dot = { .min = 25000, .max = 350000 }, .vco = { .min = 908000, .max = 1512000 }, @@ -882,7 +891,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, return calculated_clock->p > best_clock->p; } - if (WARN_ON_ONCE(!target_freq)) + if (drm_WARN_ON_ONCE(dev, !target_freq)) return false; *error_ppm = div_u64(1000000ULL * @@ -1090,7 +1099,8 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) /* Wait for the Pipe State to go off */ if (intel_de_wait_for_clear(dev_priv, reg, I965_PIPECONF_ACTIVE, 100)) - WARN(1, "pipe_off wait timed out\n"); + drm_WARN(&dev_priv->drm, 1, + "pipe_off wait timed out\n"); } else { intel_wait_for_pipe_scanline_stopped(crtc); } @@ -1205,7 +1215,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) enum pipe panel_pipe = INVALID_PIPE; bool locked = true; - if (WARN_ON(HAS_DDI(dev_priv))) + if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv))) return; if (HAS_PCH_SPLIT(dev_priv)) { @@ -1241,7 +1251,8 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) pp_reg = PP_CONTROL(0); port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; - WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS); + drm_WARN_ON(&dev_priv->drm, + port_sel != PANEL_PORT_SELECT_LVDS); intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe); } @@ -1482,7 +1493,9 @@ static void chv_enable_pll(struct intel_crtc *crtc, * DPLLB VGA mode also seems to cause problems. * We should always have it disabled. */ - WARN_ON((intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); + drm_WARN_ON(&dev_priv->drm, + (intel_de_read(dev_priv, DPLL(PIPE_B)) & + DPLL_VGA_MODE_DIS) == 0); } else { intel_de_write(dev_priv, DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); @@ -1630,10 +1643,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, if (intel_de_wait_for_register(dev_priv, dpll_reg, port_mask, expected_mask, 1000)) - WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", - dport->base.base.base.id, dport->base.base.name, - intel_de_read(dev_priv, dpll_reg) & port_mask, - expected_mask); + drm_WARN(&dev_priv->drm, 1, + "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", + dport->base.base.base.id, dport->base.base.name, + intel_de_read(dev_priv, dpll_reg) & port_mask, + expected_mask); } static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) @@ -1872,7 +1886,7 @@ void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) val = intel_de_read(dev_priv, reg); if (val & PIPECONF_ENABLE) { /* we keep both pipes enabled on 830 */ - WARN_ON(!IS_I830(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); return; } @@ -2218,11 +2232,11 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int pinctl; u32 alignment; - if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) + if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) return ERR_PTR(-EINVAL); alignment = intel_surf_alignment(fb, 0); - if (WARN_ON(alignment && !is_power_of_2(alignment))) + if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) return ERR_PTR(-EINVAL); /* Note that the w/a also requires 64 PTE of padding following the @@ -2393,7 +2407,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y, struct drm_i915_private *dev_priv = to_i915(fb->dev); unsigned int cpp = fb->format->cpp[color_plane]; - WARN_ON(new_offset > old_offset); + drm_WARN_ON(&dev_priv->drm, new_offset > old_offset); if (!is_surface_linear(fb, color_plane)) { unsigned int tile_size, tile_width, tile_height; @@ -2715,9 +2729,10 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, /* * We assume the primary plane for pipe A has - * the highest stride limits of them all. + * the highest stride limits of them all, + * if in case pipe A is disabled, use the first pipe from pipe_mask. */ - crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); + crtc = intel_get_first_crtc(dev_priv); if (!crtc) return 0; @@ -3155,7 +3170,7 @@ intel_plane_remap_gtt(struct intel_plane_state *plane_state) src_w = drm_rect_width(&plane_state->uapi.src) >> 16; src_h = drm_rect_height(&plane_state->uapi.src) >> 16; - WARN_ON(is_ccs_modifier(fb->modifier)); + drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier)); /* Make src coordinates relative to the viewport */ drm_rect_translate(&plane_state->uapi.src, @@ -3196,7 +3211,7 @@ intel_plane_remap_gtt(struct intel_plane_state *plane_state) DRM_MODE_ROTATE_0, tile_size); offset /= tile_size; - WARN_ON(i >= ARRAY_SIZE(info->plane)); + drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane)); info->plane[i].offset = offset; info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); @@ -3847,7 +3862,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) intel_add_fb_offsets(&x, &y, plane_state, 0); offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0); alignment = intel_surf_alignment(fb, 0); - if (WARN_ON(alignment && !is_power_of_2(alignment))) + if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) return -EINVAL; /* @@ -4494,10 +4509,15 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) { struct drm_device *dev = intel_crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - intel_de_write(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0); - intel_de_write(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); - intel_de_write(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); + intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0); + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); + + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } /* @@ -4841,7 +4861,7 @@ __intel_display_resume(struct drm_device *dev, ret = drm_atomic_helper_commit_duplicated_state(state, ctx); - WARN_ON(ret == -EDEADLK); + drm_WARN_ON(dev, ret == -EDEADLK); return ret; } @@ -5621,10 +5641,10 @@ static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) } /* This should not happen with any sane values */ - WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & - ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); - WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & - ~SBI_SSCDIVINTPHASE_INCVAL_MASK); + drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) & + ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); + drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) & + ~SBI_SSCDIVINTPHASE_INCVAL_MASK); drm_dbg_kms(&dev_priv->drm, "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", @@ -5730,8 +5750,12 @@ static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool e if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) return; - WARN_ON(intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); - WARN_ON(intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & + FDI_RX_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & + FDI_RX_ENABLE); temp &= ~FDI_BC_BIFURCATION_SELECT; if (enable) @@ -5880,7 +5904,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state, temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; port = intel_get_crtc_new_encoder(state, crtc_state)->port; - WARN_ON(port < PORT_B || port > PORT_D); + drm_WARN_ON(dev, port < PORT_B || port > PORT_D); temp |= TRANS_DP_PORT_SEL(port); intel_de_write(dev_priv, reg, temp); @@ -6234,9 +6258,11 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) if (crtc_state->pch_pfit.enabled) { u16 uv_rgb_hphase, uv_rgb_vphase; int pfit_w, pfit_h, hscale, vscale; + unsigned long irqflags; int id; - if (WARN_ON(crtc_state->scaler_state.scaler_id < 0)) + if (drm_WARN_ON(&dev_priv->drm, + crtc_state->scaler_state.scaler_id < 0)) return; pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF; @@ -6249,16 +6275,21 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); id = scaler_state->scaler_id; - intel_de_write(dev_priv, SKL_PS_CTRL(pipe, id), - PS_SCALER_EN | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN | + PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); - intel_de_write(dev_priv, SKL_PS_WIN_POS(pipe, id), - crtc_state->pch_pfit.pos); - intel_de_write(dev_priv, SKL_PS_WIN_SZ(pipe, id), - crtc_state->pch_pfit.size); + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), + crtc_state->pch_pfit.pos); + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), + crtc_state->pch_pfit.size); + + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } } @@ -6300,11 +6331,11 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) * This function is called from post_plane_update, which is run after * a vblank wait. */ - WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); + drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); if (IS_BROADWELL(dev_priv)) { - WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, - IPS_ENABLE | IPS_PCODE_CONTROL)); + drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, + IPS_ENABLE | IPS_PCODE_CONTROL)); /* Quoting Art Runyan: "its not safe to expect any particular * value in IPS_CTL bit 31 after enabling IPS through the * mailbox." Moreover, the mailbox may return a bogus state, @@ -6333,7 +6364,8 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) return; if (IS_BROADWELL(dev_priv)) { - WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); + drm_WARN_ON(dev, + sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); /* * Wait for PCODE to finish disabling IPS. The BSpec specified * 42ms timeout value leads to occasional timeouts so use 100ms @@ -6846,7 +6878,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (WARN_ON(crtc->active)) + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; /* @@ -7002,7 +7034,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; bool psl_clkgate_wa; - if (WARN_ON(crtc->active)) + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; intel_encoders_pre_pll_enable(state, crtc); @@ -7185,7 +7217,8 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) * The panel fitter should only be adjusted whilst the pipe is disabled, * according to register description and PRM. */ - WARN_ON(intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); intel_de_write(dev_priv, PFIT_PGM_RATIOS, @@ -7381,7 +7414,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (WARN_ON(crtc->active)) + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; if (intel_crtc_has_dp_encoder(new_crtc_state)) @@ -7447,7 +7480,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (WARN_ON(crtc->active)) + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; i9xx_set_pll_dividers(new_crtc_state); @@ -7593,7 +7626,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); ret = drm_atomic_add_affected_connectors(state, &crtc->base); - WARN_ON(IS_ERR(temp_crtc_state) || ret); + drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc); @@ -7606,7 +7639,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, crtc->active = false; crtc->base.enabled = false; - WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); + drm_WARN_ON(&dev_priv->drm, + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); crtc_state->uapi.active = false; crtc_state->uapi.connector_mask = 0; crtc_state->uapi.encoder_mask = 0; @@ -9216,7 +9250,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, if (!plane->get_hw_state(plane, &pipe)) return; - WARN_ON(pipe != crtc->pipe); + drm_WARN_ON(dev, pipe != crtc->pipe); intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); if (!intel_fb) { @@ -9328,7 +9362,8 @@ bdw_get_pipemisc_output_format(struct intel_crtc *crtc) if (tmp & PIPEMISC_YUV420_ENABLE) { /* We support 4:2:0 in full blend mode only */ - WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); + drm_WARN_ON(&dev_priv->drm, + (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); return INTEL_OUTPUT_FORMAT_YCBCR420; } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { @@ -9755,10 +9790,11 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, { u32 reg, tmp; - if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) + if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread, + "FDI requires downspread\n")) with_spread = true; - if (WARN(HAS_PCH_LPT_LP(dev_priv) && - with_fdi, "LP PCH doesn't have FDI\n")) + if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && + with_fdi, "LP PCH doesn't have FDI\n")) with_fdi = false; mutex_lock(&dev_priv->sb_lock); @@ -9852,10 +9888,10 @@ static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) u32 tmp; int idx = BEND_IDX(steps); - if (WARN_ON(steps % 5 != 0)) + if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0)) return; - if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) + if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase))) return; mutex_lock(&dev_priv->sb_lock); @@ -10023,8 +10059,8 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) * This would end up with an odd purple hue over * the entire display. Make sure we don't do it. */ - WARN_ON(crtc_state->limited_color_range && - crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); + drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); if (crtc_state->limited_color_range) val |= PIPECONF_COLOR_RANGE_SELECT; @@ -10435,7 +10471,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, if (!plane->get_hw_state(plane, &pipe)) return; - WARN_ON(pipe != crtc->pipe); + drm_WARN_ON(dev, pipe != crtc->pipe); intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); if (!intel_fb) { @@ -10570,8 +10606,8 @@ static void ilk_get_pfit_config(struct intel_crtc *crtc, * ivb/hsw (since we don't use the higher upscaling modes which * differentiates them) so just WARN about this case for now. */ if (IS_GEN(dev_priv, 7)) { - WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != - PF_PIPE_SEL_IVB(crtc->pipe)); + drm_WARN_ON(dev, (tmp & PF_PIPE_SEL_MASK_IVB) != + PF_PIPE_SEL_IVB(crtc->pipe)); } } } @@ -10669,8 +10705,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, intel_get_shared_dpll_by_id(dev_priv, pll_id); pll = pipe_config->shared_dpll; - WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll, - &pipe_config->dpll_hw_state)); + drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll, + &pipe_config->dpll_hw_state)); tmp = pipe_config->dpll_hw_state.dpll; pipe_config->pixel_multiplier = @@ -10727,7 +10763,7 @@ static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); - if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) + if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2)) return; pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); @@ -10754,12 +10790,13 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, port)); port_dpll_id = ICL_PORT_DPLL_MG_PHY; } else { - WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162); + drm_WARN_ON(&dev_priv->drm, + clk_sel < DDI_CLK_SEL_TBT_162); id = DPLL_ID_ICL_TBTPLL; port_dpll_id = ICL_PORT_DPLL_DEFAULT; } } else { - WARN(1, "Invalid port %x\n", port); + drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port); return; } @@ -10802,7 +10839,7 @@ static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); id = temp >> (port * 3 + 1); - if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) + if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3)) return; pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); @@ -10896,8 +10933,9 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { default: - WARN(1, "unknown pipe linked to transcoder %s\n", - transcoder_name(panel_transcoder)); + drm_WARN(dev, 1, + "unknown pipe linked to transcoder %s\n", + transcoder_name(panel_transcoder)); /* fall through */ case TRANS_DDI_EDP_INPUT_A_ONOFF: force_thru = true; @@ -10925,11 +10963,11 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, /* * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1 */ - WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) && - enabled_panel_transcoders != BIT(TRANSCODER_EDP)); + drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) && + enabled_panel_transcoders != BIT(TRANSCODER_EDP)); power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); - WARN_ON(*power_domain_mask & BIT_ULL(power_domain)); + drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain)); wf = intel_display_power_get_if_enabled(dev_priv, power_domain); if (!wf) @@ -10963,7 +11001,7 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, cpu_transcoder = TRANSCODER_DSI_C; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - WARN_ON(*power_domain_mask & BIT_ULL(power_domain)); + drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain)); wf = intel_display_power_get_if_enabled(dev_priv, power_domain); if (!wf) @@ -11032,7 +11070,8 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc, pll = pipe_config->shared_dpll; if (pll) { - WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll, + drm_WARN_ON(&dev_priv->drm, + !pll->info->funcs->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state)); } @@ -11103,8 +11142,9 @@ static void icl_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) intel_display_power_put(dev_priv, power_domain, trans_wakeref); } - WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER && - crtc_state->sync_mode_slaves_mask); + drm_WARN_ON(&dev_priv->drm, + crtc_state->master_transcoder != INVALID_TRANSCODER && + crtc_state->sync_mode_slaves_mask); } static bool hsw_get_pipe_config(struct intel_crtc *crtc, @@ -11135,7 +11175,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, if (IS_GEN9_LP(dev_priv) && bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask, wakerefs)) { - WARN_ON(active); + drm_WARN_ON(&dev_priv->drm, active); active = true; } @@ -11202,7 +11242,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); - WARN_ON(power_domain_mask & BIT_ULL(power_domain)); + drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain)); wf = intel_display_power_get_if_enabled(dev_priv, power_domain); if (wf) { @@ -11449,8 +11489,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, return -EINVAL; } - WARN_ON(plane_state->uapi.visible && - plane_state->color_plane[0].stride != fb->pitches[0]); + drm_WARN_ON(&i915->drm, plane_state->uapi.visible && + plane_state->color_plane[0].stride != fb->pitches[0]); switch (fb->pitches[0]) { case 256: @@ -11666,8 +11706,8 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, return -EINVAL; } - WARN_ON(plane_state->uapi.visible && - plane_state->color_plane[0].stride != fb->pitches[0]); + drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && + plane_state->color_plane[0].stride != fb->pitches[0]); if (fb->pitches[0] != drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { @@ -11886,7 +11926,7 @@ int intel_get_load_detect_pipe(struct drm_connector *connector, old->restore_state = NULL; - WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); + drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); /* * Algorithm gets a little messy: @@ -12330,7 +12370,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat was_visible = old_plane_state->uapi.visible; visible = plane_state->uapi.visible; - if (!was_crtc_enabled && WARN_ON(was_visible)) + if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible)) was_visible = false; /* @@ -12676,7 +12716,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (mode_changed && crtc_state->hw.enable && dev_priv->display.crtc_compute_clock && - !WARN_ON(crtc_state->shared_dpll)) { + !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state); if (ret) return ret; @@ -12706,7 +12746,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, } if (dev_priv->display.compute_intermediate_wm) { - if (WARN_ON(!dev_priv->display.compute_pipe_wm)) + if (drm_WARN_ON(&dev_priv->drm, + !dev_priv->display.compute_pipe_wm)) return 0; /* @@ -13141,24 +13182,21 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state) encoder = to_intel_encoder(connector_state->best_encoder); - WARN_ON(!connector_state->crtc); + drm_WARN_ON(dev, !connector_state->crtc); switch (encoder->type) { - unsigned int port_mask; case INTEL_OUTPUT_DDI: - if (WARN_ON(!HAS_DDI(to_i915(dev)))) + if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) break; /* else, fall through */ case INTEL_OUTPUT_DP: case INTEL_OUTPUT_HDMI: case INTEL_OUTPUT_EDP: - port_mask = 1 << encoder->port; - /* the same port mustn't appear more than once */ - if (used_ports & port_mask) + if (used_ports & BIT(encoder->port)) ret = false; - used_ports |= port_mask; + used_ports |= BIT(encoder->port); break; case INTEL_OUTPUT_DP_MST: used_mst_ports |= @@ -13365,7 +13403,8 @@ encoder_retry: } if (ret == RETRY) { - if (WARN(!retry, "loop in pipe configuration computation\n")) + if (drm_WARN(&i915->drm, !retry, + "loop in pipe configuration computation\n")) return -EINVAL; drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); @@ -13925,9 +13964,10 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, * FDI already provided one idea for the dotclock. * Yell if the encoder disagrees. */ - WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), - "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", - fdi_dotclock, dotclock); + drm_WARN(&dev_priv->drm, + !intel_fuzzy_clock_check(fdi_dotclock, dotclock), + "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", + fdi_dotclock, dotclock); } } @@ -14269,11 +14309,11 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, if (new_crtc_state->hw.active) I915_STATE_WARN(!(pll->active_mask & crtc_mask), "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", - pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask); + pipe_name(crtc->pipe), pll->active_mask); else I915_STATE_WARN(pll->active_mask & crtc_mask, "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", - pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask); + pipe_name(crtc->pipe), pll->active_mask); I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", @@ -14302,10 +14342,10 @@ verify_shared_dpll_state(struct intel_crtc *crtc, I915_STATE_WARN(pll->active_mask & crtc_mask, "pll active mismatch (didn't expect pipe %c in active mask)\n", - pipe_name(drm_crtc_index(&crtc->base))); + pipe_name(crtc->pipe)); I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, "pll enabled crtcs mismatch (found %x in enabled mask)\n", - pipe_name(drm_crtc_index(&crtc->base))); + pipe_name(crtc->pipe)); } } @@ -15054,7 +15094,8 @@ static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *ne struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); enum transcoder slave_transcoder; - WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask)); + drm_WARN_ON(&dev_priv->drm, + !is_power_of_2(new_crtc_state->sync_mode_slaves_mask)); slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1; return intel_get_crtc_for_pipe(dev_priv, @@ -15222,8 +15263,8 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc, struct intel_crtc_state *old_slave_crtc_state = intel_atomic_get_old_crtc_state(state, slave_crtc); - WARN_ON(!slave_crtc || !new_slave_crtc_state || - !old_slave_crtc_state); + drm_WARN_ON(&i915->drm, !slave_crtc || !new_slave_crtc_state || + !old_slave_crtc_state); drm_dbg_kms(&i915->drm, "Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n", @@ -15287,7 +15328,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) struct intel_crtc *crtc; struct intel_crtc_state *old_crtc_state, *new_crtc_state; struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; - const u8 num_pipes = INTEL_NUM_PIPES(dev_priv); u8 update_pipes = 0, modeset_pipes = 0; int i; @@ -15324,7 +15364,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) continue; if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, num_pipes, pipe)) + entries, I915_MAX_PIPES, pipe)) continue; entries[pipe] = new_crtc_state->wm.skl.ddb; @@ -15361,8 +15401,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) is_trans_port_sync_slave(new_crtc_state)) continue; - WARN_ON(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, num_pipes, pipe)); + drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, + entries, I915_MAX_PIPES, pipe)); entries[pipe] = new_crtc_state->wm.skl.ddb; modeset_pipes &= ~BIT(pipe); @@ -15396,8 +15436,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((modeset_pipes & BIT(pipe)) == 0) continue; - WARN_ON(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, num_pipes, pipe)); + drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, + entries, I915_MAX_PIPES, pipe)); entries[pipe] = new_crtc_state->wm.skl.ddb; modeset_pipes &= ~BIT(pipe); @@ -15405,7 +15445,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) intel_update_crtc(crtc, state, old_crtc_state, new_crtc_state); } - WARN_ON(modeset_pipes); + drm_WARN_ON(&dev_priv->drm, modeset_pipes); } @@ -16659,7 +16699,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) intel_color_init(crtc); - WARN_ON(drm_crtc_index(&crtc->base) != crtc->pipe); + drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); return 0; @@ -17526,7 +17566,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv) return; state = drm_atomic_state_alloc(&dev_priv->drm); - if (WARN_ON(!state)) + if (drm_WARN_ON(&dev_priv->drm, !state)) return; intel_state = to_intel_atomic_state(state); @@ -17578,7 +17618,8 @@ fail: * If this actually happens, we'll have to just leave the * BIOS-programmed watermarks untouched and hope for the best. */ - WARN(ret, "Could not determine valid watermarks for inherited state\n"); + drm_WARN(&dev_priv->drm, ret, + "Could not determine valid watermarks for inherited state\n"); drm_atomic_state_put(state); @@ -17746,11 +17787,9 @@ static void plane_config_fini(struct intel_initial_plane_config *plane_config) i915_vma_put(plane_config->vma); } -int intel_modeset_init(struct drm_i915_private *i915) +/* part #1: call before irq install */ +int intel_modeset_init_noirq(struct drm_i915_private *i915) { - struct drm_device *dev = &i915->drm; - enum pipe pipe; - struct intel_crtc *crtc; int ret; i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); @@ -17775,6 +17814,17 @@ int intel_modeset_init(struct drm_i915_private *i915) intel_fbc_init(i915); + return 0; +} + +/* part #2: call after irq install */ +int intel_modeset_init(struct drm_i915_private *i915) +{ + struct drm_device *dev = &i915->drm; + enum pipe pipe; + struct intel_crtc *crtc; + int ret; + intel_init_pm(i915); intel_panel_sanitize_ssc(i915); @@ -17873,7 +17923,8 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) u32 dpll, fp; int i; - WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154); + drm_WARN_ON(&dev_priv->drm, + i9xx_calc_dpll_params(48000, &clock) != 25154); drm_dbg_kms(&dev_priv->drm, "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", @@ -17938,11 +17989,19 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", pipe_name(pipe)); - WARN_ON(intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); - WARN_ON(intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); - WARN_ON(intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); - WARN_ON(intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE); - WARN_ON(intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & + DISPLAY_PLANE_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & + DISPLAY_PLANE_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & + DISPLAY_PLANE_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE); intel_de_write(dev_priv, PIPECONF(pipe), 0); intel_de_posting_read(dev_priv, PIPECONF(pipe)); @@ -18446,7 +18505,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) if (crtc_state->hw.active) { min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); - if (WARN_ON(min_cdclk < 0)) + if (drm_WARN_ON(dev, min_cdclk < 0)) min_cdclk = 0; } @@ -18660,7 +18719,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, u64 put_domains; put_domains = modeset_get_crtc_power_domains(crtc_state); - if (WARN_ON(put_domains)) + if (drm_WARN_ON(dev, put_domains)) modeset_put_power_domains(dev_priv, put_domains); } @@ -18727,7 +18786,7 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915) flush_workqueue(i915->modeset_wq); flush_work(&i915->atomic_helper.free_work); - WARN_ON(!llist_empty(&i915->atomic_helper.free_list)); + drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); } /* part #2: call after irq uninstall */ @@ -18880,7 +18939,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) { enum transcoder cpu_transcoder = transcoders[i]; - if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder]) + if (!has_transcoder(dev_priv, cpu_transcoder)) continue; error->transcoder[i].available = true; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index f92efbbec838..a790b8ce7dfe 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -313,10 +313,11 @@ enum phy_fia { }; #define for_each_pipe(__dev_priv, __p) \ - for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) + for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ + for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p)) #define for_each_pipe_masked(__dev_priv, __p, __mask) \ - for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \ + for_each_pipe(__dev_priv, __p) \ for_each_if((__mask) & BIT(__p)) #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ @@ -614,6 +615,7 @@ intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, /* modesetting */ void intel_modeset_init_hw(struct drm_i915_private *i915); +int intel_modeset_init_noirq(struct drm_i915_private *i915); int intel_modeset_init(struct drm_i915_private *i915); void intel_modeset_driver_remove(struct drm_i915_private *i915); void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 722399fc2ace..6e25a1317161 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -183,8 +183,9 @@ static void intel_power_well_get(struct drm_i915_private *dev_priv, static void intel_power_well_put(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - WARN(!power_well->count, "Use count on power well %s is already zero", - power_well->desc->name); + drm_WARN(&dev_priv->drm, !power_well->count, + "Use count on power well %s is already zero", + power_well->desc->name); if (!--power_well->count) intel_power_well_disable(dev_priv, power_well); @@ -294,7 +295,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, power_well->desc->name); /* An AUX timeout is expected if the TBT DP tunnel is down. */ - WARN_ON(!power_well->desc->hsw.is_tc_tbt); + drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt); } } @@ -347,8 +348,9 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, enum skl_power_gate pg) { /* Timeout 5us for PG#0, for other PGs 1us */ - WARN_ON(intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS, - SKL_FUSE_PG_DIST_STATUS(pg), 1)); + drm_WARN_ON(&dev_priv->drm, + intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS, + SKL_FUSE_PG_DIST_STATUS(pg), 1)); } static void hsw_power_well_enable(struct drm_i915_private *dev_priv, @@ -423,7 +425,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); u32 val; - WARN_ON(!IS_ICELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); val = intel_de_read(dev_priv, regs->driver); intel_de_write(dev_priv, regs->driver, @@ -455,7 +457,7 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); u32 val; - WARN_ON(!IS_ICELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)); intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy), @@ -493,7 +495,7 @@ static int power_well_async_ref_count(struct drm_i915_private *dev_priv, int refs = hweight64(power_well->desc->domains & async_put_domains_mask(&dev_priv->power_domains)); - WARN_ON(refs > power_well->count); + drm_WARN_ON(&dev_priv->drm, refs > power_well->count); return refs; } @@ -523,7 +525,7 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, continue; dig_port = enc_to_dig_port(encoder); - if (WARN_ON(!dig_port)) + if (drm_WARN_ON(&dev_priv->drm, !dig_port)) continue; if (dig_port->aux_ch != aux_ch) { @@ -534,10 +536,10 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, break; } - if (WARN_ON(!dig_port)) + if (drm_WARN_ON(&dev_priv->drm, !dig_port)) return; - WARN_ON(!intel_tc_port_ref_held(dig_port)); + drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port)); } #else @@ -623,15 +625,19 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) { - WARN_ONCE((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9), - "DC9 already programmed to be enabled.\n"); - WARN_ONCE(intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, - "DC5 still not disabled to enable DC9.\n"); - WARN_ONCE(intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) & - HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), - "Power well 2 on.\n"); - WARN_ONCE(intel_irqs_enabled(dev_priv), - "Interrupts not disabled yet.\n"); + drm_WARN_ONCE(&dev_priv->drm, + (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9), + "DC9 already programmed to be enabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, + intel_de_read(dev_priv, DC_STATE_EN) & + DC_STATE_EN_UPTO_DC5, + "DC5 still not disabled to enable DC9.\n"); + drm_WARN_ONCE(&dev_priv->drm, + intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) & + HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), + "Power well 2 on.\n"); + drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), + "Interrupts not disabled yet.\n"); /* * TODO: check for the following to verify the conditions to enter DC9 @@ -644,10 +650,12 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) { - WARN_ONCE(intel_irqs_enabled(dev_priv), - "Interrupts not disabled yet.\n"); - WARN_ONCE(intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, - "DC5 still not disabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), + "Interrupts not disabled yet.\n"); + drm_WARN_ONCE(&dev_priv->drm, + intel_de_read(dev_priv, DC_STATE_EN) & + DC_STATE_EN_UPTO_DC5, + "DC5 still not disabled.\n"); /* * TODO: check for the following to verify DC9 state was indeed @@ -756,7 +764,8 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) u32 val; u32 mask; - if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, + state & ~dev_priv->csr.allowed_dc_mask)) state &= dev_priv->csr.allowed_dc_mask; val = intel_de_read(dev_priv, DC_STATE_EN); @@ -851,11 +860,13 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv) static void assert_csr_loaded(struct drm_i915_private *dev_priv) { - WARN_ONCE(!intel_de_read(dev_priv, CSR_PROGRAM(0)), - "CSR program storage start is NULL\n"); - WARN_ONCE(!intel_de_read(dev_priv, CSR_SSP_BASE), - "CSR SSP Base Not fine\n"); - WARN_ONCE(!intel_de_read(dev_priv, CSR_HTP_SKL), "CSR HTP Not fine\n"); + drm_WARN_ONCE(&dev_priv->drm, + !intel_de_read(dev_priv, CSR_PROGRAM(0)), + "CSR program storage start is NULL\n"); + drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_SSP_BASE), + "CSR SSP Base Not fine\n"); + drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_HTP_SKL), + "CSR HTP Not fine\n"); } static struct i915_power_well * @@ -875,7 +886,9 @@ lookup_power_well(struct drm_i915_private *dev_priv, * the first power well and hope the WARN gets reported so we can fix * our driver. */ - WARN(1, "Power well %d not defined for this platform\n", power_well_id); + drm_WARN(&dev_priv->drm, 1, + "Power well %d not defined for this platform\n", + power_well_id); return &dev_priv->power_domains.power_wells[0]; } @@ -898,7 +911,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, mutex_lock(&power_domains->lock); power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF); - if (WARN_ON(!power_well)) + if (drm_WARN_ON(&dev_priv->drm, !power_well)) goto unlock; state = sanitize_target_dc_state(dev_priv, state); @@ -929,10 +942,13 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, SKL_DISP_PW_2); - WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); + drm_WARN_ONCE(&dev_priv->drm, pg2_enabled, + "PG2 not disabled to enable DC5.\n"); - WARN_ONCE((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), - "DC5 already programmed to be enabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, + (intel_de_read(dev_priv, DC_STATE_EN) & + DC_STATE_EN_UPTO_DC5), + "DC5 already programmed to be enabled.\n"); assert_rpm_wakelock_held(&dev_priv->runtime_pm); assert_csr_loaded(dev_priv); @@ -954,10 +970,13 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv) static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) { - WARN_ONCE(intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE, - "Backlight is not disabled.\n"); - WARN_ONCE((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), - "DC6 already programmed to be enabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, + intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE, + "Backlight is not disabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, + (intel_de_read(dev_priv, DC_STATE_EN) & + DC_STATE_EN_UPTO_DC6), + "DC6 already programmed to be enabled.\n"); assert_csr_loaded(dev_priv); } @@ -1045,10 +1064,11 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv); u8 enabled_dbuf_slices = dev_priv->enabled_dbuf_slices_mask; - WARN(hw_enabled_dbuf_slices != enabled_dbuf_slices, - "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", - hw_enabled_dbuf_slices, - enabled_dbuf_slices); + drm_WARN(&dev_priv->drm, + hw_enabled_dbuf_slices != enabled_dbuf_slices, + "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", + hw_enabled_dbuf_slices, + enabled_dbuf_slices); } static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) @@ -1064,7 +1084,9 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) dev_priv->display.get_cdclk(dev_priv, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ - WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_config)); + drm_WARN_ON(&dev_priv->drm, + intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, + &cdclk_config)); gen9_assert_dbuf_enabled(dev_priv); @@ -1221,8 +1243,8 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, * We only ever set the power-on and power-gate states, anything * else is unexpected. */ - WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) && - state != PUNIT_PWRGT_PWR_GATE(pw_idx)); + drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && + state != PUNIT_PWRGT_PWR_GATE(pw_idx)); if (state == ctrl) enabled = true; @@ -1231,7 +1253,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, * is poking at the power controls too. */ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; - WARN_ON(ctrl != state); + drm_WARN_ON(&dev_priv->drm, ctrl != state); vlv_punit_put(dev_priv); @@ -1260,7 +1282,7 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); intel_de_write(dev_priv, CBR1_VLV, 0); - WARN_ON(RUNTIME_INFO(dev_priv)->rawclk_freq == 0); + drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0); intel_de_write(dev_priv, RAWCLK_FREQ_VLV, DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 1000)); @@ -1502,8 +1524,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, enum pipe pipe; u32 tmp; - WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && - power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); + drm_WARN_ON_ONCE(&dev_priv->drm, + power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && + power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) { pipe = PIPE_A; @@ -1564,8 +1587,9 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, { enum dpio_phy phy; - WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && - power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); + drm_WARN_ON_ONCE(&dev_priv->drm, + power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && + power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) { phy = DPIO_PHY0; @@ -1647,11 +1671,13 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; - WARN(actual != expected, - "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", - !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), - !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), - reg, val); + drm_WARN(&dev_priv->drm, actual != expected, + "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", + !!(actual & DPIO_ALLDL_POWERDOWN), + !!(actual & DPIO_ANYDL_POWERDOWN), + !!(expected & DPIO_ALLDL_POWERDOWN), + !!(expected & DPIO_ANYDL_POWERDOWN), + reg, val); } bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, @@ -1733,7 +1759,8 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, * We only ever set the power-on and power-gate states, anything * else is unexpected. */ - WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); + drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) && + state != DP_SSS_PWR_GATE(pipe)); enabled = state == DP_SSS_PWR_ON(pipe); /* @@ -1741,7 +1768,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, * is poking at the power controls too. */ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); - WARN_ON(ctrl << 16 != state); + drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state); vlv_punit_put(dev_priv); @@ -2019,12 +2046,13 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv, power_domains = &dev_priv->power_domains; - WARN(!power_domains->domain_use_count[domain], - "Use count on domain %s is already zero\n", - name); - WARN(async_put_domains_mask(power_domains) & BIT_ULL(domain), - "Async disabling of domain %s is pending\n", - name); + drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain], + "Use count on domain %s is already zero\n", + name); + drm_WARN(&dev_priv->drm, + async_put_domains_mask(power_domains) & BIT_ULL(domain), + "Async disabling of domain %s is pending\n", + name); power_domains->domain_use_count[domain]--; @@ -2169,7 +2197,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915, goto out_verify; } - WARN_ON(power_domains->domain_use_count[domain] != 1); + drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1); /* Let a pending work requeue itself or queue a new one. */ if (power_domains->async_put_wakeref) { @@ -2244,7 +2272,7 @@ intel_display_power_flush_work_sync(struct drm_i915_private *i915) verify_async_put_domains_state(power_domains); - WARN_ON(power_domains->async_put_wakeref); + drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); } #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) @@ -4443,8 +4471,8 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; struct i915_power_domains *power_domains = &dev_priv->power_domains; - WARN(hweight8(req_slices) > max_slices, - "Invalid number of dbuf slices requested\n"); + drm_WARN(&dev_priv->drm, hweight8(req_slices) > max_slices, + "Invalid number of dbuf slices requested\n"); DRM_DEBUG_KMS("Updating dbuf slices to 0x%x\n", req_slices); @@ -4486,14 +4514,22 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv) static void icl_mbus_init(struct drm_i915_private *dev_priv) { - u32 val; + u32 mask, val; + mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | + MBUS_ABOX_BT_CREDIT_POOL2_MASK | + MBUS_ABOX_B_CREDIT_MASK | + MBUS_ABOX_BW_CREDIT_MASK; val = MBUS_ABOX_BT_CREDIT_POOL1(16) | - MBUS_ABOX_BT_CREDIT_POOL2(16) | - MBUS_ABOX_B_CREDIT(1) | - MBUS_ABOX_BW_CREDIT(1); + MBUS_ABOX_BT_CREDIT_POOL2(16) | + MBUS_ABOX_B_CREDIT(1) | + MBUS_ABOX_BW_CREDIT(1); - intel_de_write(dev_priv, MBUS_ABOX_CTL, val); + intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val); + if (INTEL_GEN(dev_priv) >= 12) { + intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val); + intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val); + } } static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) @@ -4995,6 +5031,14 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) table[i].page_mask); intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, table[i].page_mask); + + /* Wa_22010178259:tgl */ + intel_de_rmw(dev_priv, BW_BUDDY1_CTL, + BW_BUDDY_TLB_REQ_TIMER_MASK, + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); + intel_de_rmw(dev_priv, BW_BUDDY2_CTL, + BW_BUDDY_TLB_REQ_TIMER_MASK, + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); } } @@ -5195,8 +5239,9 @@ static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0 static void assert_ved_power_gated(struct drm_i915_private *dev_priv) { - WARN(!vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0), - "VED not power gated\n"); + drm_WARN(&dev_priv->drm, + !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0), + "VED not power gated\n"); } static void assert_isp_power_gated(struct drm_i915_private *dev_priv) @@ -5207,9 +5252,9 @@ static void assert_isp_power_gated(struct drm_i915_private *dev_priv) {} }; - WARN(!pci_dev_present(isp_ids) && - !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0), - "ISP not power gated\n"); + drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) && + !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0), + "ISP not power gated\n"); } static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); @@ -5339,7 +5384,7 @@ void intel_power_domains_disable(struct drm_i915_private *i915) { struct i915_power_domains *power_domains = &i915->power_domains; - WARN_ON(power_domains->wakeref); + drm_WARN_ON(&i915->drm, power_domains->wakeref); power_domains->wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); @@ -5421,7 +5466,7 @@ void intel_power_domains_resume(struct drm_i915_private *i915) intel_power_domains_init_hw(i915, true); power_domains->display_core_suspended = false; } else { - WARN_ON(power_domains->wakeref); + drm_WARN_ON(&i915->drm, power_domains->wakeref); power_domains->wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e6147364c413..61f4628f5602 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1168,8 +1168,6 @@ struct intel_hdmi { }; struct intel_dp_mst_encoder; -#define DP_MAX_DOWNSTREAM_PORTS 0x10 - /* * enum link_m_n_set: * When platform provides two set of M_N registers for dp, we can @@ -1409,8 +1407,17 @@ vlv_pipe_to_channel(enum pipe pipe) } static inline struct intel_crtc * +intel_get_first_crtc(struct drm_i915_private *dev_priv) +{ + return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0)); +} + +static inline struct intel_crtc * intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { + /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */ + drm_WARN_ON(&dev_priv->drm, + !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe))); return dev_priv->pipe_to_crtc_mapping[pipe]; } @@ -1600,11 +1607,15 @@ intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) (1 << INTEL_OUTPUT_DP_MST) | (1 << INTEL_OUTPUT_EDP)); } + static inline void intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) { - drm_wait_one_vblank(&dev_priv->drm, pipe); + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + + drm_crtc_wait_one_vblank(&crtc->base); } + static inline void intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7d69b4f43fe2..0a5a9197f8f5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -325,7 +325,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) int size, max_rate = 0, vbt_max_rate; /* This should only be done once */ - WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); + drm_WARN_ON(&dev_priv->drm, + intel_dp->source_rates || intel_dp->num_source_rates); if (INTEL_GEN(dev_priv) >= 10) { source_rates = cnl_rates; @@ -757,10 +758,11 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) enum dpio_channel ch = vlv_pipe_to_channel(pipe); u32 DP; - if (WARN(intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, - "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name)) + if (drm_WARN(&dev_priv->drm, + intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, + "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", + pipe_name(pipe), intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name)) return; drm_dbg_kms(&dev_priv->drm, @@ -836,13 +838,16 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (encoder->type == INTEL_OUTPUT_EDP) { - WARN_ON(intel_dp->active_pipe != INVALID_PIPE && - intel_dp->active_pipe != intel_dp->pps_pipe); + drm_WARN_ON(&dev_priv->drm, + intel_dp->active_pipe != INVALID_PIPE && + intel_dp->active_pipe != + intel_dp->pps_pipe); if (intel_dp->pps_pipe != INVALID_PIPE) pipes &= ~(1 << intel_dp->pps_pipe); } else { - WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); + drm_WARN_ON(&dev_priv->drm, + intel_dp->pps_pipe != INVALID_PIPE); if (intel_dp->active_pipe != INVALID_PIPE) pipes &= ~(1 << intel_dp->active_pipe); @@ -865,10 +870,10 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); /* We should never land here with regular DP ports */ - WARN_ON(!intel_dp_is_edp(intel_dp)); + drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); - WARN_ON(intel_dp->active_pipe != INVALID_PIPE && - intel_dp->active_pipe != intel_dp->pps_pipe); + drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE && + intel_dp->active_pipe != intel_dp->pps_pipe); if (intel_dp->pps_pipe != INVALID_PIPE) return intel_dp->pps_pipe; @@ -879,7 +884,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) * Didn't find one. This should not happen since there * are two power sequencers and up to two eDP ports. */ - if (WARN_ON(pipe == INVALID_PIPE)) + if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE)) pipe = PIPE_A; vlv_steal_power_sequencer(dev_priv, pipe); @@ -913,7 +918,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); /* We should never land here with regular DP ports */ - WARN_ON(!intel_dp_is_edp(intel_dp)); + drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); if (!intel_dp->pps_reset) return backlight_controller; @@ -1018,8 +1023,10 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; - if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - !IS_GEN9_LP(dev_priv))) + if (drm_WARN_ON(&dev_priv->drm, + !(IS_VALLEYVIEW(dev_priv) || + IS_CHERRYVIEW(dev_priv) || + IS_GEN9_LP(dev_priv)))) return; /* @@ -1035,7 +1042,8 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) for_each_intel_dp(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - WARN_ON(intel_dp->active_pipe != INVALID_PIPE); + drm_WARN_ON(&dev_priv->drm, + intel_dp->active_pipe != INVALID_PIPE); if (encoder->type != INTEL_OUTPUT_EDP) continue; @@ -1170,7 +1178,8 @@ intel_dp_check_edp(struct intel_dp *intel_dp) return; if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { - WARN(1, "eDP powered off while attempting aux channel communication.\n"); + drm_WARN(&dev_priv->drm, 1, + "eDP powered off while attempting aux channel communication.\n"); drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n", intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp))); @@ -1384,8 +1393,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, const u32 status = intel_uncore_read(uncore, ch_ctl); if (status != intel_dp->aux_busy_last_status) { - WARN(1, "%s: not started (status 0x%08x)\n", - intel_dp->aux.name, status); + drm_WARN(&i915->drm, 1, + "%s: not started (status 0x%08x)\n", + intel_dp->aux.name, status); intel_dp->aux_busy_last_status = status; } @@ -1394,7 +1404,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, } /* Only 5 data registers! */ - if (WARN_ON(send_bytes > 20 || recv_size > 20)) { + if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { ret = -E2BIG; goto out; } @@ -2679,8 +2689,8 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)); - if (WARN_ON(!HAS_DDI(dev_priv) && - (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { + if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) && + (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { control &= ~PANEL_UNLOCK_MASK; control |= PANEL_UNLOCK_REGS; } @@ -2779,7 +2789,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); - WARN_ON(intel_dp->want_panel_vdd); + drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd); if (!edp_have_panel_vdd(intel_dp)) return; @@ -2876,10 +2886,10 @@ static void edp_panel_on(struct intel_dp *intel_dp) dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)->base.base.name); - if (WARN(edp_have_panel_power(intel_dp), - "[ENCODER:%d:%s] panel power already on\n", - dp_to_dig_port(intel_dp)->base.base.base.id, - dp_to_dig_port(intel_dp)->base.base.name)) + if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp), + "[ENCODER:%d:%s] panel power already on\n", + dp_to_dig_port(intel_dp)->base.base.base.id, + dp_to_dig_port(intel_dp)->base.base.name)) return; wait_panel_power_cycle(intel_dp); @@ -2937,8 +2947,9 @@ static void edp_panel_off(struct intel_dp *intel_dp) drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n", dig_port->base.base.base.id, dig_port->base.base.name); - WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n", - dig_port->base.base.base.id, dig_port->base.base.name); + drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd, + "Need [ENCODER:%d:%s] VDD to turn off panel\n", + dig_port->base.base.base.id, dig_port->base.base.name); pp = ilk_get_pp_control(intel_dp); /* We need to switch off panel power _and_ force vdd, for otherwise some @@ -3170,7 +3181,7 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) * FIXME should really check all downstream ports... */ return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && - intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && + drm_dp_is_branch(intel_dp->dpcd) && intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; } @@ -3581,7 +3592,7 @@ static void intel_enable_dp(struct intel_encoder *encoder, enum pipe pipe = crtc->pipe; intel_wakeref_t wakeref; - if (WARN_ON(dp_reg & DP_PORT_EN)) + if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN)) return; with_pps_lock(intel_dp, wakeref) { @@ -3652,9 +3663,9 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) enum pipe pipe = intel_dp->pps_pipe; i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); - WARN_ON(intel_dp->active_pipe != INVALID_PIPE); + drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); - if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) + if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) return; edp_panel_vdd_off_sync(intel_dp); @@ -3688,10 +3699,10 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, for_each_intel_dp(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - WARN(intel_dp->active_pipe == pipe, - "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n", - pipe_name(pipe), encoder->base.base.id, - encoder->base.name); + drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe, + "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n", + pipe_name(pipe), encoder->base.base.id, + encoder->base.name); if (intel_dp->pps_pipe != pipe) continue; @@ -3715,7 +3726,7 @@ static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, lockdep_assert_held(&dev_priv->pps_mutex); - WARN_ON(intel_dp->active_pipe != INVALID_PIPE); + drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); if (intel_dp->pps_pipe != INVALID_PIPE && intel_dp->pps_pipe != crtc->pipe) { @@ -4243,7 +4254,9 @@ intel_dp_link_down(struct intel_encoder *encoder, enum port port = encoder->port; u32 DP = intel_dp->DP; - if (WARN_ON((intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN) == 0)) + if (drm_WARN_ON(&dev_priv->drm, + (intel_de_read(dev_priv, intel_dp->output_reg) & + DP_PORT_EN) == 0)) return; drm_dbg_kms(&dev_priv->drm, "\n"); @@ -4405,7 +4418,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) to_i915(dp_to_dig_port(intel_dp)->base.base.dev); /* this function is meant to be called only once */ - WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); + drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); if (!intel_dp_read_dpcd(intel_dp)) return false; @@ -5161,7 +5174,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, crtc_state = to_intel_crtc_state(crtc->base.state); - WARN_ON(!intel_crtc_has_dp_encoder(crtc_state)); + drm_WARN_ON(&dev_priv->drm, !intel_crtc_has_dp_encoder(crtc_state)); if (!crtc_state->hw.active) return 0; @@ -5696,7 +5709,8 @@ intel_dp_detect(struct drm_connector *connector, drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); - WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); + drm_WARN_ON(&dev_priv->drm, + !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); /* Can't disconnect eDP */ if (intel_dp_is_edp(intel_dp)) @@ -6622,7 +6636,7 @@ static int intel_modeset_tile_group(struct intel_atomic_state *state, if (ret) break; } - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); + drm_connector_list_iter_end(&conn_iter); return ret; } @@ -6662,7 +6676,7 @@ static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, transcoders &= ~BIT(crtc_state->cpu_transcoder); } - WARN_ON(transcoders != 0); + drm_WARN_ON(&dev_priv->drm, transcoders != 0); return 0; } @@ -7043,7 +7057,8 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, if (force_disable_vdd) { u32 pp = ilk_get_pp_control(intel_dp); - WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); + drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON, + "Panel power already on\n"); if (pp & EDP_FORCE_VDD) drm_dbg_kms(&dev_priv->drm, @@ -7519,7 +7534,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, * with an already powered-on LVDS power sequencer. */ if (intel_get_lvds_encoder(dev_priv)) { - WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); + drm_WARN_ON(dev, + !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); drm_info(&dev_priv->drm, "LVDS was detected, not registering eDP\n"); @@ -7592,9 +7608,12 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, intel_connector->panel.backlight.power = intel_edp_backlight_power; intel_panel_setup_backlight(connector, pipe); - if (fixed_mode) - drm_connector_init_panel_orientation_property( - connector, fixed_mode->hdisplay, fixed_mode->vdisplay); + if (fixed_mode) { + /* We do not know the orientation, but their might be a quirk */ + drm_connector_set_panel_orientation_with_quirk(connector, + DRM_MODE_PANEL_ORIENTATION_UNKNOWN, + fixed_mode->hdisplay, fixed_mode->vdisplay); + } return true; @@ -7650,10 +7669,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, INIT_WORK(&intel_connector->modeset_retry_work, intel_dp_modeset_retry_work_fn); - if (WARN(intel_dig_port->max_lanes < 1, - "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", - intel_dig_port->max_lanes, intel_encoder->base.base.id, - intel_encoder->base.name)) + if (drm_WARN(dev, intel_dig_port->max_lanes < 1, + "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", + intel_dig_port->max_lanes, intel_encoder->base.base.id, + intel_encoder->base.name)) return false; intel_dp_set_source_rates(intel_dp); @@ -7671,7 +7690,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, * Currently we don't support eDP on TypeC ports, although in * theory it could work on TypeC legacy ports. */ - WARN_ON(intel_phy_is_tc(dev_priv, phy)); + drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy)); type = DRM_MODE_CONNECTOR_eDP; } else { type = DRM_MODE_CONNECTOR_DisplayPort; @@ -7689,9 +7708,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_encoder->type = INTEL_OUTPUT_EDP; /* eDP only on port B and/or C on vlv/chv */ - if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && - intel_dp_is_edp(intel_dp) && - port != PORT_B && port != PORT_C)) + if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || + IS_CHERRYVIEW(dev_priv)) && + intel_dp_is_edp(intel_dp) && + port != PORT_B && port != PORT_C)) return false; drm_dbg_kms(&dev_priv->drm, @@ -7710,6 +7730,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, connector->ycbcr_420_allowed = true; intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); + intel_connector->polled = DRM_CONNECTOR_POLL_HPD; intel_dp_aux_init(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 30e0a3aa9d57..229b4e329864 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -872,7 +872,8 @@ static int intel_hdcp_check_link(struct intel_connector *connector) goto out; } - if (WARN_ON(!intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) { + if (drm_WARN_ON(&dev_priv->drm, + !intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) { drm_err(&dev_priv->drm, "%s:%d HDCP link stopped encryption,%x\n", connector->base.name, connector->base.base.id, @@ -1561,8 +1562,9 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; - WARN_ON(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & - LINK_ENCRYPTION_STATUS); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & + LINK_ENCRYPTION_STATUS); if (hdcp->shim->toggle_signalling) { ret = hdcp->shim->toggle_signalling(intel_dig_port, true); if (ret) { @@ -1599,8 +1601,8 @@ static int hdcp2_disable_encryption(struct intel_connector *connector) enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; - WARN_ON(!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & - LINK_ENCRYPTION_STATUS)); + drm_WARN_ON(&dev_priv->drm, !(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & + LINK_ENCRYPTION_STATUS)); intel_de_write(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port), intel_de_read(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port)) & ~CTL_LINK_ENCRYPTION_REQ); @@ -1720,7 +1722,8 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) goto out; } - if (WARN_ON(!intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) { + if (drm_WARN_ON(&dev_priv->drm, + !intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) { drm_err(&dev_priv->drm, "HDCP2.2 link stopped the encryption, %x\n", intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port))); @@ -1916,7 +1919,7 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv) return; mutex_lock(&dev_priv->hdcp_comp_mutex); - WARN_ON(dev_priv->hdcp_comp_added); + drm_WARN_ON(&dev_priv->drm, dev_priv->hdcp_comp_added); dev_priv->hdcp_comp_added = true; mutex_unlock(&dev_priv->hdcp_comp_mutex); @@ -1990,7 +1993,8 @@ int intel_hdcp_enable(struct intel_connector *connector, return -ENOENT; mutex_lock(&hdcp->mutex); - WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); + drm_WARN_ON(&dev_priv->drm, + hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); hdcp->content_type = content_type; if (INTEL_GEN(dev_priv) >= 12) { diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 476ce1d9c557..bdbb5ce3fa81 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3176,6 +3176,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, connector->ycbcr_420_allowed = true; intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); + intel_connector->polled = DRM_CONNECTOR_POLL_HPD; if (HAS_DDI(dev_priv)) intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 127a2f28c1ac..8af0ae61e1bb 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -242,36 +242,37 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work) container_of(work, typeof(*dev_priv), hotplug.reenable_work.work); struct drm_device *dev = &dev_priv->drm; + struct drm_connector_list_iter conn_iter; + struct intel_connector *connector; intel_wakeref_t wakeref; enum hpd_pin pin; wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); spin_lock_irq(&dev_priv->irq_lock); - for_each_hpd_pin(pin) { - struct drm_connector_list_iter conn_iter; - struct intel_connector *connector; - if (dev_priv->hotplug.stats[pin].state != HPD_DISABLED) + drm_connector_list_iter_begin(dev, &conn_iter); + for_each_intel_connector_iter(connector, &conn_iter) { + pin = intel_connector_hpd_pin(connector); + if (pin == HPD_NONE || + dev_priv->hotplug.stats[pin].state != HPD_DISABLED) continue; - dev_priv->hotplug.stats[pin].state = HPD_ENABLED; - - drm_connector_list_iter_begin(dev, &conn_iter); - for_each_intel_connector_iter(connector, &conn_iter) { - if (intel_connector_hpd_pin(connector) == pin) { - if (connector->base.polled != connector->polled) - DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", - connector->base.name); - connector->base.polled = connector->polled; - if (!connector->base.polled) - connector->base.polled = DRM_CONNECTOR_POLL_HPD; - } - } - drm_connector_list_iter_end(&conn_iter); + if (connector->base.polled != connector->polled) + DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", + connector->base.name); + connector->base.polled = connector->polled; } + drm_connector_list_iter_end(&conn_iter); + + for_each_hpd_pin(pin) { + if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) + dev_priv->hotplug.stats[pin].state = HPD_ENABLED; + } + if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) dev_priv->display.hpd_irq_setup(dev_priv); + spin_unlock_irq(&dev_priv->irq_lock); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); @@ -617,16 +618,17 @@ static void i915_hpd_poll_init_work(struct work_struct *work) drm_connector_list_iter_begin(dev, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { - enum hpd_pin pin = intel_connector_hpd_pin(connector); + enum hpd_pin pin; + + pin = intel_connector_hpd_pin(connector); + if (pin == HPD_NONE) + continue; connector->base.polled = connector->polled; - if (pin != HPD_NONE && I915_HAS_HOTPLUG(dev_priv) && - !connector->base.polled) - connector->base.polled = enabled ? - DRM_CONNECTOR_POLL_CONNECT | - DRM_CONNECTOR_POLL_DISCONNECT : - DRM_CONNECTOR_POLL_HPD; + if (enabled && connector->base.polled == DRM_CONNECTOR_POLL_HPD) + connector->base.polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; } drm_connector_list_iter_end(&conn_iter); diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 585688b6ebac..5aead622019c 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -434,8 +434,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, /* 965+ wants fuzzy fitting */ /* FIXME: handle multiple panels by failing gracefully */ if (INTEL_GEN(dev_priv) >= 4) - pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | - PFIT_FILTER_FUZZY); + pfit_control |= PFIT_PIPE(intel_crtc->pipe) | PFIT_FILTER_FUZZY; out: if ((pfit_control & PFIT_ENABLE) == 0) { diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b4942b6445ae..7e754201f54d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -936,10 +936,12 @@ void intel_psr_enable(struct intel_dp *intel_dp, { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (!crtc_state->has_psr) + if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp) return; - if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv))) + dev_priv->psr.force_mode_changed = false; + + if (!crtc_state->has_psr) return; drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); @@ -1099,6 +1101,8 @@ void intel_psr_update(struct intel_dp *intel_dp, if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) return; + dev_priv->psr.force_mode_changed = false; + mutex_lock(&dev_priv->psr.lock); enable = crtc_state->has_psr && psr_global_enabled(dev_priv); @@ -1629,7 +1633,7 @@ void intel_psr_atomic_check(struct drm_connector *connector, struct drm_crtc_state *crtc_state; if (!CAN_PSR(dev_priv) || !new_state->crtc || - dev_priv->psr.initially_probed) + !dev_priv->psr.force_mode_changed) return; intel_connector = to_intel_connector(connector); @@ -1640,5 +1644,18 @@ void intel_psr_atomic_check(struct drm_connector *connector, crtc_state = drm_atomic_get_new_crtc_state(new_state->state, new_state->crtc); crtc_state->mode_changed = true; - dev_priv->psr.initially_probed = true; +} + +void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv; + + if (!intel_dp) + return; + + dev_priv = dp_to_i915(intel_dp); + if (!CAN_PSR(dev_priv) || intel_dp != dev_priv->psr.dp) + return; + + dev_priv->psr.force_mode_changed = true; } diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index c58a1d438808..274fc6bb6221 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -40,5 +40,6 @@ bool intel_psr_enabled(struct intel_dp *intel_dp); void intel_psr_atomic_check(struct drm_connector *connector, struct drm_connector_state *old_state, struct drm_connector_state *new_state); +void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp); #endif /* __INTEL_PSR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index a4921b549f8b..b0588150752c 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -2721,6 +2721,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) * Some SDVO devices have one-shot hotplug interrupts. * Ensure that they get re-enabled when an interrupt happens. */ + intel_connector->polled = DRM_CONNECTOR_POLL_HPD; intel_encoder->hotplug = intel_sdvo_hotplug; intel_sdvo_enable_hotplug(intel_encoder); } else { diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index b9f2e3ce5185..d07cfad8ce6f 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -1660,10 +1660,9 @@ static void vlv_dsi_add_properties(struct intel_connector *connector) connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; - connector->base.display_info.panel_orientation = - vlv_dsi_get_panel_orientation(connector); - drm_connector_init_panel_orientation_property( + drm_connector_set_panel_orientation_with_quirk( &connector->base, + vlv_dsi_get_panel_orientation(connector), connector->panel.fixed_mode->hdisplay, connector->panel.fixed_mode->vdisplay); } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 3e82739bdbc0..b24ee8e104cf 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -71,6 +71,7 @@ #include "gt/gen6_ppgtt.h" #include "gt/intel_context.h" +#include "gt/intel_context_param.h" #include "gt/intel_engine_heartbeat.h" #include "gt/intel_engine_user.h" #include "gt/intel_ring.h" @@ -668,23 +669,30 @@ err_free: return ERR_PTR(err); } -static void +static int context_apply_all(struct i915_gem_context *ctx, - void (*fn)(struct intel_context *ce, void *data), + int (*fn)(struct intel_context *ce, void *data), void *data) { struct i915_gem_engines_iter it; struct intel_context *ce; + int err = 0; - for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) - fn(ce, data); + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) { + err = fn(ce, data); + if (err) + break; + } i915_gem_context_unlock_engines(ctx); + + return err; } -static void __apply_ppgtt(struct intel_context *ce, void *vm) +static int __apply_ppgtt(struct intel_context *ce, void *vm) { i915_vm_put(ce->vm); ce->vm = i915_vm_get(vm); + return 0; } static struct i915_address_space * @@ -722,9 +730,10 @@ static void __set_timeline(struct intel_timeline **dst, intel_timeline_put(old); } -static void __apply_timeline(struct intel_context *ce, void *timeline) +static int __apply_timeline(struct intel_context *ce, void *timeline) { __set_timeline(&ce->timeline, timeline); + return 0; } static void __assign_timeline(struct i915_gem_context *ctx, @@ -1215,6 +1224,63 @@ out: return err; } +static int __apply_ringsize(struct intel_context *ce, void *sz) +{ + return intel_context_set_ring_size(ce, (unsigned long)sz); +} + +static int set_ringsize(struct i915_gem_context *ctx, + struct drm_i915_gem_context_param *args) +{ + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915)) + return -ENODEV; + + if (args->size) + return -EINVAL; + + if (!IS_ALIGNED(args->value, I915_GTT_PAGE_SIZE)) + return -EINVAL; + + if (args->value < I915_GTT_PAGE_SIZE) + return -EINVAL; + + if (args->value > 128 * I915_GTT_PAGE_SIZE) + return -EINVAL; + + return context_apply_all(ctx, + __apply_ringsize, + __intel_context_ring_size(args->value)); +} + +static int __get_ringsize(struct intel_context *ce, void *arg) +{ + long sz; + + sz = intel_context_get_ring_size(ce); + GEM_BUG_ON(sz > INT_MAX); + + return sz; /* stop on first engine */ +} + +static int get_ringsize(struct i915_gem_context *ctx, + struct drm_i915_gem_context_param *args) +{ + int sz; + + if (!HAS_LOGICAL_RING_CONTEXTS(ctx->i915)) + return -ENODEV; + + if (args->size) + return -EINVAL; + + sz = context_apply_all(ctx, __get_ringsize, NULL); + if (sz < 0) + return sz; + + args->value = sz; + return 0; +} + static int user_to_context_sseu(struct drm_i915_private *i915, const struct drm_i915_gem_context_param_sseu *user, @@ -1390,7 +1456,7 @@ set_engines__load_balance(struct i915_user_extension __user *base, void *data) if (!HAS_EXECLISTS(i915)) return -ENODEV; - if (USES_GUC_SUBMISSION(i915)) + if (intel_uc_uses_guc_submission(&i915->gt.uc)) return -ENODEV; /* not implement yet */ if (get_user(idx, &ext->engine_index)) @@ -1852,17 +1918,19 @@ set_persistence(struct i915_gem_context *ctx, return __context_set_persistence(ctx, args->value); } -static void __apply_priority(struct intel_context *ce, void *arg) +static int __apply_priority(struct intel_context *ce, void *arg) { struct i915_gem_context *ctx = arg; if (!intel_engine_has_semaphores(ce->engine)) - return; + return 0; if (ctx->sched.priority >= I915_PRIORITY_NORMAL) intel_context_set_use_semaphores(ce); else intel_context_clear_use_semaphores(ce); + + return 0; } static int set_priority(struct i915_gem_context *ctx, @@ -1955,6 +2023,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv, ret = set_persistence(ctx, args); break; + case I915_CONTEXT_PARAM_RINGSIZE: + ret = set_ringsize(ctx, args); + break; + case I915_CONTEXT_PARAM_BAN_PERIOD: default: ret = -EINVAL; @@ -1983,6 +2055,18 @@ static int create_setparam(struct i915_user_extension __user *ext, void *data) return ctx_setparam(arg->fpriv, arg->ctx, &local.param); } +static int copy_ring_size(struct intel_context *dst, + struct intel_context *src) +{ + long sz; + + sz = intel_context_get_ring_size(src); + if (sz < 0) + return sz; + + return intel_context_set_ring_size(dst, sz); +} + static int clone_engines(struct i915_gem_context *dst, struct i915_gem_context *src) { @@ -2026,6 +2110,12 @@ static int clone_engines(struct i915_gem_context *dst, } intel_context_set_gem(clone->engines[n], dst); + + /* Copy across the preferred ringsize */ + if (copy_ring_size(clone->engines[n], e->engines[n])) { + __free_engines(clone, n + 1); + goto err_unlock; + } } clone->num_engines = n; @@ -2388,6 +2478,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, args->value = i915_gem_context_is_persistent(ctx); break; + case I915_CONTEXT_PARAM_RINGSIZE: + ret = get_ringsize(ctx, args); + break; + case I915_CONTEXT_PARAM_BAN_PERIOD: default: ret = -EINVAL; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 87fa5f42c39a..fe1e50937fe2 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2327,15 +2327,22 @@ static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce) intel_context_timeline_unlock(tl); if (rq) { - if (i915_request_wait(rq, - I915_WAIT_INTERRUPTIBLE, - MAX_SCHEDULE_TIMEOUT) < 0) { - i915_request_put(rq); - err = -EINTR; - goto err_exit; - } + bool nonblock = eb->file->filp->f_flags & O_NONBLOCK; + long timeout; + timeout = MAX_SCHEDULE_TIMEOUT; + if (nonblock) + timeout = 0; + + timeout = i915_request_wait(rq, + I915_WAIT_INTERRUPTIBLE, + timeout); i915_request_put(rq); + + if (timeout < 0) { + err = nonblock ? -EWOULDBLOCK : timeout; + goto err_exit; + } } eb->engine = ce->engine; @@ -2713,7 +2720,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, vma = i915_gem_object_ggtt_pin(eb.batch->obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { err = PTR_ERR(vma); - goto err_vma; + goto err_parse; } eb.batch = vma; @@ -2792,6 +2799,7 @@ err_request: err_batch_unpin: if (eb.batch_flags & I915_DISPATCH_SECURE) i915_vma_unpin(eb.batch); +err_parse: if (eb.batch->private) intel_engine_pool_put(eb.batch->private); err_vma: diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index 35985218bd85..5da9f9e534b9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -225,6 +225,7 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, /* But keep the pointer alive for RCU-protected lookups */ call_rcu(&obj->rcu, __i915_gem_free_object_rcu); + cond_resched(); } intel_runtime_pm_put(&i915->runtime_pm, wakeref); } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c index 7eaa2ab01de3..830d3f96e1f6 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c @@ -256,8 +256,7 @@ unsigned long i915_gem_shrink_all(struct drm_i915_private *i915) with_intel_runtime_pm(&i915->runtime_pm, wakeref) { freed = i915_gem_shrink(i915, -1UL, NULL, I915_SHRINK_BOUND | - I915_SHRINK_UNBOUND | - I915_SHRINK_ACTIVE); + I915_SHRINK_UNBOUND); } return freed; @@ -336,7 +335,6 @@ i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) freed_pages = 0; with_intel_runtime_pm(&i915->runtime_pm, wakeref) freed_pages += i915_gem_shrink(i915, -1UL, NULL, - I915_SHRINK_ACTIVE | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_WRITEBACK); diff --git a/drivers/gpu/drm/i915/gt/intel_context_param.c b/drivers/gpu/drm/i915/gt/intel_context_param.c new file mode 100644 index 000000000000..65dcd090245d --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_context_param.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2019 Intel Corporation + */ + +#include "i915_active.h" +#include "intel_context.h" +#include "intel_context_param.h" +#include "intel_ring.h" + +int intel_context_set_ring_size(struct intel_context *ce, long sz) +{ + int err; + + if (intel_context_lock_pinned(ce)) + return -EINTR; + + err = i915_active_wait(&ce->active); + if (err < 0) + goto unlock; + + if (intel_context_is_pinned(ce)) { + err = -EBUSY; /* In active use, come back later! */ + goto unlock; + } + + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { + struct intel_ring *ring; + + /* Replace the existing ringbuffer */ + ring = intel_engine_create_ring(ce->engine, sz); + if (IS_ERR(ring)) { + err = PTR_ERR(ring); + goto unlock; + } + + intel_ring_put(ce->ring); + ce->ring = ring; + + /* Context image will be updated on next pin */ + } else { + ce->ring = __intel_context_ring_size(sz); + } + +unlock: + intel_context_unlock_pinned(ce); + return err; +} + +long intel_context_get_ring_size(struct intel_context *ce) +{ + long sz = (unsigned long)READ_ONCE(ce->ring); + + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { + if (intel_context_lock_pinned(ce)) + return -EINTR; + + sz = ce->ring->size; + intel_context_unlock_pinned(ce); + } + + return sz; +} diff --git a/drivers/gpu/drm/i915/gt/intel_context_param.h b/drivers/gpu/drm/i915/gt/intel_context_param.h new file mode 100644 index 000000000000..f053d8633fe2 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_context_param.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2019 Intel Corporation + */ + +#ifndef INTEL_CONTEXT_PARAM_H +#define INTEL_CONTEXT_PARAM_H + +struct intel_context; + +int intel_context_set_ring_size(struct intel_context *ce, long sz); +long intel_context_get_ring_size(struct intel_context *ce); + +#endif /* INTEL_CONTEXT_PARAM_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e46e55354e95..119c9cb24fd4 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -639,7 +639,7 @@ static int measure_breadcrumb_dw(struct intel_context *ce) { struct intel_engine_cs *engine = ce->engine; struct measure_breadcrumb *frame; - int dw = -ENOMEM; + int dw; GEM_BUG_ON(!engine->gt->scratch); diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 7dae91e0d002..41a00281f364 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -427,7 +427,7 @@ static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt) u64 size; int ret; - if (!USES_GUC(ggtt->vm.i915)) + if (!intel_uc_uses_guc(&ggtt->vm.gt->uc)) return 0; GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP); @@ -754,7 +754,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) * readback check when writing GTT PTE entries. */ if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10) - ggtt->gsm = ioremap_nocache(phys_addr, size); + ggtt->gsm = ioremap(phys_addr, size); else ggtt->gsm = ioremap_wc(phys_addr, size); if (!ggtt->gsm) { diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index f1f1b306e0af..3dea8881e915 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -592,7 +592,9 @@ int intel_gt_init(struct intel_gt *gt) if (err) goto err_engines; - intel_uc_init(>->uc); + err = intel_uc_init(>->uc); + if (err) + goto err_engines; err = intel_gt_resume(gt); if (err) @@ -642,6 +644,13 @@ void intel_gt_driver_remove(struct intel_gt *gt) void intel_gt_driver_unregister(struct intel_gt *gt) { intel_rps_driver_unregister(>->rps); + + /* + * Upon unregistering the device to prevent any new users, cancel + * all in-flight requests so that we can quickly unbind the active + * resources. + */ + intel_gt_set_wedged(gt); } void intel_gt_driver_release(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index ba31cbe8c68e..39b0125b7143 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1668,9 +1668,9 @@ last_active(const struct intel_engine_execlists *execlists) wait_link) #define for_each_signaler(p__, rq__) \ - list_for_each_entry_lockless(p__, \ - &(rq__)->sched.signalers_list, \ - signal_link) + list_for_each_entry_rcu(p__, \ + &(rq__)->sched.signalers_list, \ + signal_link) static void defer_request(struct i915_request *rq, struct list_head * const pl) { @@ -2533,11 +2533,13 @@ unlock: static bool hold_request(const struct i915_request *rq) { struct i915_dependency *p; + bool result = false; /* * If one of our ancestors is on hold, we must also be on hold, * otherwise we will bypass it and execute before it. */ + rcu_read_lock(); for_each_signaler(p, rq) { const struct i915_request *s = container_of(p->signaler, typeof(*s), sched); @@ -2545,11 +2547,13 @@ static bool hold_request(const struct i915_request *rq) if (s->engine != rq->engine) continue; - if (i915_request_on_hold(s)) - return true; + result = i915_request_on_hold(s); + if (result) + break; } + rcu_read_unlock(); - return false; + return result; } static void __execlists_unhold(struct i915_request *rq) @@ -2962,6 +2966,7 @@ __execlists_update_reg_state(const struct intel_context *ce, regs[CTX_RING_START] = i915_ggtt_offset(ring->vma); regs[CTX_RING_HEAD] = head; regs[CTX_RING_TAIL] = ring->tail; + regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID; /* RPCS */ if (engine->class == RENDER_CLASS) { diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 3e5e6c86e843..c3514ec7b8db 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1640,7 +1640,7 @@ static int igt_reset_engines_atomic(void *arg) if (!intel_has_reset_engine(gt)) return 0; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(>->uc)) return 0; igt_global_reset_lock(gt); diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 49b93cda04ca..febd608c23a7 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -2109,7 +2109,7 @@ static int live_suppress_self_preempt(void *arg) if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915)) return 0; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(>->uc)) return 0; /* presume black blox */ if (intel_vgpu_active(gt->i915)) @@ -3224,7 +3224,7 @@ static int live_virtual_engine(void *arg) unsigned int class, inst; int err; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(>->uc)) return 0; for_each_engine(engine, gt, id) { @@ -3357,7 +3357,7 @@ static int live_virtual_mask(void *arg) unsigned int class, inst; int err; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(>->uc)) return 0; for (class = 0; class <= MAX_ENGINE_CLASS; class++) { @@ -3499,7 +3499,7 @@ static int live_virtual_preserved(void *arg) * are preserved. */ - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(>->uc)) return 0; /* As we use CS_GPR we cannot run before they existed on all engines. */ @@ -3729,7 +3729,7 @@ static int live_virtual_bond(void *arg) unsigned int class, inst; int err; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(>->uc)) return 0; for (class = 0; class <= MAX_ENGINE_CLASS; class++) { @@ -3890,7 +3890,7 @@ static int live_virtual_reset(void *arg) * forgotten. */ - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(>->uc)) return 0; if (!intel_has_reset_engine(gt)) diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c index 6ad6aca315f6..35406ecdf0b2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_reset.c +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c @@ -115,7 +115,7 @@ static int igt_atomic_engine_reset(void *arg) if (!intel_has_reset_engine(gt)) return 0; - if (USES_GUC_SUBMISSION(gt->i915)) + if (intel_uc_uses_guc_submission(>->uc)) return 0; intel_gt_pm_get(gt); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index c4c1523da7a6..819f09ef51fc 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -207,7 +207,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc) { u32 flags = 0; - if (!intel_guc_is_submission_supported(guc)) + if (!intel_guc_submission_is_used(guc)) flags |= GUC_CTL_DISABLE_SCHEDULER; return flags; @@ -217,7 +217,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc) { u32 flags = 0; - if (intel_guc_is_submission_supported(guc)) { + if (intel_guc_submission_is_used(guc)) { u32 ctxnum, base; base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool); @@ -333,7 +333,7 @@ int intel_guc_init(struct intel_guc *guc) ret = intel_uc_fw_init(&guc->fw); if (ret) - goto err_fetch; + goto out; ret = intel_guc_log_create(&guc->log); if (ret) @@ -348,7 +348,7 @@ int intel_guc_init(struct intel_guc *guc) if (ret) goto err_ads; - if (intel_guc_is_submission_supported(guc)) { + if (intel_guc_submission_is_used(guc)) { /* * This is stuff we need to have available at fw load time * if we are planning to enable submission later @@ -364,6 +364,8 @@ int intel_guc_init(struct intel_guc *guc) /* We need to notify the guc whenever we change the GGTT */ i915_ggtt_enable_guc(gt->ggtt); + intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOADABLE); + return 0; err_ct: @@ -374,9 +376,8 @@ err_log: intel_guc_log_destroy(&guc->log); err_fw: intel_uc_fw_fini(&guc->fw); -err_fetch: - intel_uc_fw_cleanup_fetch(&guc->fw); - DRM_DEV_DEBUG_DRIVER(gt->i915->drm.dev, "failed with %d\n", ret); +out: + i915_probe_error(gt->i915, "failed with %d\n", ret); return ret; } @@ -384,12 +385,12 @@ void intel_guc_fini(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); - if (!intel_uc_fw_is_available(&guc->fw)) + if (!intel_uc_fw_is_loadable(&guc->fw)) return; i915_ggtt_disable_guc(gt->ggtt); - if (intel_guc_is_submission_supported(guc)) + if (intel_guc_submission_is_used(guc)) intel_guc_submission_fini(guc); intel_guc_ct_fini(&guc->ct); @@ -397,9 +398,6 @@ void intel_guc_fini(struct intel_guc *guc) intel_guc_ads_destroy(guc); intel_guc_log_destroy(&guc->log); intel_uc_fw_fini(&guc->fw); - intel_uc_fw_cleanup_fetch(&guc->fw); - - intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_DISABLED); } /* @@ -544,7 +542,7 @@ int intel_guc_suspend(struct intel_guc *guc) * If GuC communication is enabled but submission is not supported, * we do not need to suspend the GuC. */ - if (!intel_guc_submission_is_enabled(guc)) + if (!intel_guc_submission_is_used(guc) || !intel_guc_is_ready(guc)) return 0; /* @@ -609,7 +607,7 @@ int intel_guc_resume(struct intel_guc *guc) * we do not need to resume the GuC but we do need to enable the * GuC communication on resume (above). */ - if (!intel_guc_submission_is_enabled(guc)) + if (!intel_guc_submission_is_used(guc) || !intel_guc_is_ready(guc)) return 0; return intel_guc_send(guc, action, ARRAY_SIZE(action)); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index 668b067b71e2..4594ccbeaa34 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -39,7 +39,7 @@ struct intel_guc { void (*disable)(struct intel_guc *guc); } interrupts; - bool submission_supported; + bool submission_selected; struct i915_vma *ads_vma; struct __guc_ads_blob *ads_blob; @@ -143,11 +143,17 @@ static inline bool intel_guc_is_supported(struct intel_guc *guc) return intel_uc_fw_is_supported(&guc->fw); } -static inline bool intel_guc_is_enabled(struct intel_guc *guc) +static inline bool intel_guc_is_wanted(struct intel_guc *guc) { return intel_uc_fw_is_enabled(&guc->fw); } +static inline bool intel_guc_is_used(struct intel_guc *guc) +{ + GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED); + return intel_uc_fw_is_available(&guc->fw); +} + static inline bool intel_guc_is_fw_running(struct intel_guc *guc) { return intel_uc_fw_is_running(&guc->fw); @@ -167,11 +173,6 @@ static inline int intel_guc_sanitize(struct intel_guc *guc) return 0; } -static inline bool intel_guc_is_submission_supported(struct intel_guc *guc) -{ - return guc->submission_supported; -} - static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask) { spin_lock_irq(&guc->irq_lock); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 9e42324fdecd..1beaa77f9bb6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -660,12 +660,9 @@ void intel_guc_submission_disable(struct intel_guc *guc) guc_proc_desc_fini(guc); } -static bool __guc_submission_support(struct intel_guc *guc) +static bool __guc_submission_selected(struct intel_guc *guc) { - /* XXX: GuC submission is unavailable for now */ - return false; - - if (!intel_guc_is_supported(guc)) + if (!intel_guc_submission_is_supported(guc)) return false; return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION; @@ -673,7 +670,7 @@ static bool __guc_submission_support(struct intel_guc *guc) void intel_guc_submission_init_early(struct intel_guc *guc) { - guc->submission_supported = __guc_submission_support(guc); + guc->submission_selected = __guc_submission_selected(guc); } bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h index e402a2932592..4cf9d3e50263 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h @@ -8,7 +8,8 @@ #include <linux/types.h> -struct intel_guc; +#include "intel_guc.h" + struct intel_engine_cs; void intel_guc_submission_init_early(struct intel_guc *guc); @@ -20,4 +21,20 @@ int intel_guc_preempt_work_create(struct intel_guc *guc); void intel_guc_preempt_work_destroy(struct intel_guc *guc); bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine); +static inline bool intel_guc_submission_is_supported(struct intel_guc *guc) +{ + /* XXX: GuC submission is unavailable for now */ + return false; +} + +static inline bool intel_guc_submission_is_wanted(struct intel_guc *guc) +{ + return guc->submission_selected; +} + +static inline bool intel_guc_submission_is_used(struct intel_guc *guc) +{ + return intel_guc_is_used(guc) && intel_guc_submission_is_wanted(guc); +} + #endif diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c index 32a069841c14..a74b65694512 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@ -121,19 +121,20 @@ int intel_huc_init(struct intel_huc *huc) if (err) goto out_fini; + intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOADABLE); + return 0; out_fini: intel_uc_fw_fini(&huc->fw); out: - intel_uc_fw_cleanup_fetch(&huc->fw); - DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "failed with %d\n", err); + i915_probe_error(i915, "failed with %d\n", err); return err; } void intel_huc_fini(struct intel_huc *huc) { - if (!intel_uc_fw_is_available(&huc->fw)) + if (!intel_uc_fw_is_loadable(&huc->fw)) return; intel_huc_rsa_data_destroy(huc); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h index 644c059fe01d..a40b9cfc6c22 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h @@ -41,11 +41,17 @@ static inline bool intel_huc_is_supported(struct intel_huc *huc) return intel_uc_fw_is_supported(&huc->fw); } -static inline bool intel_huc_is_enabled(struct intel_huc *huc) +static inline bool intel_huc_is_wanted(struct intel_huc *huc) { return intel_uc_fw_is_enabled(&huc->fw); } +static inline bool intel_huc_is_used(struct intel_huc *huc) +{ + GEM_BUG_ON(__intel_uc_fw_status(&huc->fw) == INTEL_UC_FIRMWARE_SELECTED); + return intel_uc_fw_is_available(&huc->fw); +} + static inline bool intel_huc_is_authenticated(struct intel_huc *huc) { return intel_uc_fw_is_running(&huc->fw); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c index eee193bf2cc4..9cdf4cbe691c 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c @@ -20,7 +20,7 @@ void intel_huc_fw_init_early(struct intel_huc *huc) struct drm_i915_private *i915 = gt->i915; intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC, - intel_uc_uses_guc(uc), + intel_uc_wants_guc(uc), INTEL_INFO(i915)->platform, INTEL_REVID(i915)); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index affc4d6f9ead..a4cbe06e06bd 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -48,17 +48,17 @@ static void __confirm_options(struct intel_uc *uc) DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "enable_guc=%d (guc:%s submission:%s huc:%s)\n", i915_modparams.enable_guc, - yesno(intel_uc_uses_guc(uc)), - yesno(intel_uc_uses_guc_submission(uc)), - yesno(intel_uc_uses_huc(uc))); + yesno(intel_uc_wants_guc(uc)), + yesno(intel_uc_wants_guc_submission(uc)), + yesno(intel_uc_wants_huc(uc))); if (i915_modparams.enable_guc == -1) return; if (i915_modparams.enable_guc == 0) { - GEM_BUG_ON(intel_uc_uses_guc(uc)); - GEM_BUG_ON(intel_uc_uses_guc_submission(uc)); - GEM_BUG_ON(intel_uc_uses_huc(uc)); + GEM_BUG_ON(intel_uc_wants_guc(uc)); + GEM_BUG_ON(intel_uc_wants_guc_submission(uc)); + GEM_BUG_ON(intel_uc_wants_huc(uc)); return; } @@ -93,7 +93,7 @@ void intel_uc_init_early(struct intel_uc *uc) __confirm_options(uc); - if (intel_uc_uses_guc(uc)) + if (intel_uc_wants_guc(uc)) uc->ops = &uc_ops_on; else uc->ops = &uc_ops_off; @@ -257,13 +257,13 @@ static void __uc_fetch_firmwares(struct intel_uc *uc) { int err; - GEM_BUG_ON(!intel_uc_uses_guc(uc)); + GEM_BUG_ON(!intel_uc_wants_guc(uc)); err = intel_uc_fw_fetch(&uc->guc.fw); if (err) return; - if (intel_uc_uses_huc(uc)) + if (intel_uc_wants_huc(uc)) intel_uc_fw_fetch(&uc->huc.fw); } @@ -273,25 +273,38 @@ static void __uc_cleanup_firmwares(struct intel_uc *uc) intel_uc_fw_cleanup_fetch(&uc->guc.fw); } -static void __uc_init(struct intel_uc *uc) +static int __uc_init(struct intel_uc *uc) { struct intel_guc *guc = &uc->guc; struct intel_huc *huc = &uc->huc; int ret; - GEM_BUG_ON(!intel_uc_uses_guc(uc)); + GEM_BUG_ON(!intel_uc_wants_guc(uc)); + + if (!intel_uc_uses_guc(uc)) + return 0; + + if (i915_inject_probe_failure(uc_to_gt(uc)->i915)) + return -ENOMEM; /* XXX: GuC submission is unavailable for now */ - GEM_BUG_ON(intel_uc_supports_guc_submission(uc)); + GEM_BUG_ON(intel_uc_uses_guc_submission(uc)); ret = intel_guc_init(guc); - if (ret) { - intel_uc_fw_cleanup_fetch(&huc->fw); - return; + if (ret) + return ret; + + if (intel_uc_uses_huc(uc)) { + ret = intel_huc_init(huc); + if (ret) + goto out_guc; } - if (intel_uc_uses_huc(uc)) - intel_huc_init(huc); + return 0; + +out_guc: + intel_guc_fini(guc); + return ret; } static void __uc_fini(struct intel_uc *uc) @@ -402,12 +415,12 @@ static int __uc_init_hw(struct intel_uc *uc) int ret, attempts; GEM_BUG_ON(!intel_uc_supports_guc(uc)); - GEM_BUG_ON(!intel_uc_uses_guc(uc)); + GEM_BUG_ON(!intel_uc_wants_guc(uc)); - if (!intel_uc_fw_is_available(&guc->fw)) { + if (!intel_uc_fw_is_loadable(&guc->fw)) { ret = __uc_check_hw(uc) || intel_uc_fw_is_overridden(&guc->fw) || - intel_uc_supports_guc_submission(uc) ? + intel_uc_wants_guc_submission(uc) ? intel_uc_fw_status_to_error(guc->fw.status) : 0; goto err_out; } @@ -459,14 +472,14 @@ static int __uc_init_hw(struct intel_uc *uc) if (ret) goto err_communication; - if (intel_uc_supports_guc_submission(uc)) + if (intel_uc_uses_guc_submission(uc)) intel_guc_submission_enable(guc); dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n", intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path, guc->fw.major_ver_found, guc->fw.minor_ver_found, "submission", - enableddisabled(intel_uc_supports_guc_submission(uc))); + enableddisabled(intel_uc_uses_guc_submission(uc))); if (intel_uc_uses_huc(uc)) { dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n", @@ -508,7 +521,7 @@ static void __uc_fini_hw(struct intel_uc *uc) if (!intel_guc_is_fw_running(guc)) return; - if (intel_uc_supports_guc_submission(uc)) + if (intel_uc_uses_guc_submission(uc)) intel_guc_submission_disable(guc); if (guc_communication_enabled(guc)) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h index 49c913524686..5ae7b50b7dc1 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h @@ -7,6 +7,7 @@ #define _INTEL_UC_H_ #include "intel_guc.h" +#include "intel_guc_submission.h" #include "intel_huc.h" #include "i915_params.h" @@ -16,7 +17,7 @@ struct intel_uc_ops { int (*sanitize)(struct intel_uc *uc); void (*init_fw)(struct intel_uc *uc); void (*fini_fw)(struct intel_uc *uc); - void (*init)(struct intel_uc *uc); + int (*init)(struct intel_uc *uc); void (*fini)(struct intel_uc *uc); int (*init_hw)(struct intel_uc *uc); void (*fini_hw)(struct intel_uc *uc); @@ -40,35 +41,44 @@ void intel_uc_runtime_suspend(struct intel_uc *uc); int intel_uc_resume(struct intel_uc *uc); int intel_uc_runtime_resume(struct intel_uc *uc); -static inline bool intel_uc_supports_guc(struct intel_uc *uc) -{ - return intel_guc_is_supported(&uc->guc); -} - -static inline bool intel_uc_uses_guc(struct intel_uc *uc) -{ - return intel_guc_is_enabled(&uc->guc); -} +/* + * We need to know as early as possible if we're going to use GuC or not to + * take the correct setup paths. Additionally, once we've started loading the + * GuC, it is unsafe to keep executing without it because some parts of the HW, + * a subset of which is not cleaned on GT reset, will start expecting the GuC FW + * to be running. + * To solve both these requirements, we commit to using the microcontrollers if + * the relevant modparam is set and the blobs are found on the system. At this + * stage, the only thing that can stop us from attempting to load the blobs on + * the HW and use them is a fundamental issue (e.g. no memory for our + * structures); if we hit such a problem during driver load we're broken even + * without GuC, so there is no point in trying to fall back. + * + * Given the above, we can be in one of 4 states, with the last one implying + * we're committed to using the microcontroller: + * - Not supported: not available in HW and/or firmware not defined. + * - Supported: available in HW and firmware defined. + * - Wanted: supported + enabled in modparam. + * - In use: wanted + firmware found on the system and successfully fetched. + */ -static inline bool intel_uc_supports_guc_submission(struct intel_uc *uc) -{ - return intel_guc_is_submission_supported(&uc->guc); +#define __uc_state_checker(x, func, state, required) \ +static inline bool intel_uc_##state##_##func(struct intel_uc *uc) \ +{ \ + return intel_##func##_is_##required(&uc->x); \ } -static inline bool intel_uc_uses_guc_submission(struct intel_uc *uc) -{ - return intel_guc_is_submission_supported(&uc->guc); -} +#define uc_state_checkers(x, func) \ +__uc_state_checker(x, func, supports, supported) \ +__uc_state_checker(x, func, wants, wanted) \ +__uc_state_checker(x, func, uses, used) -static inline bool intel_uc_supports_huc(struct intel_uc *uc) -{ - return intel_uc_supports_guc(uc); -} +uc_state_checkers(guc, guc); +uc_state_checkers(huc, huc); +uc_state_checkers(guc, guc_submission); -static inline bool intel_uc_uses_huc(struct intel_uc *uc) -{ - return intel_huc_is_enabled(&uc->huc); -} +#undef uc_state_checkers +#undef __uc_state_checker #define intel_uc_ops_function(_NAME, _OPS, _TYPE, _RET) \ static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \ @@ -80,7 +90,7 @@ static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \ intel_uc_ops_function(sanitize, sanitize, int, 0); intel_uc_ops_function(fetch_firmwares, init_fw, void, ); intel_uc_ops_function(cleanup_firmwares, fini_fw, void, ); -intel_uc_ops_function(init, init, void, ); +intel_uc_ops_function(init, init, int, 0); intel_uc_ops_function(fini, fini, void, ); intel_uc_ops_function(init_hw, init_hw, int, 0); intel_uc_ops_function(fini_hw, fini_hw, void, ); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 8ee0a0c7f447..5434c07aefa1 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -279,7 +279,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw) err = i915_inject_probe_error(i915, -ENXIO); if (err) - return err; + goto fail; __force_fw_fetch_failures(uc_fw, -EINVAL); __force_fw_fetch_failures(uc_fw, -ESTALE); @@ -501,7 +501,7 @@ int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags) if (err) return err; - if (!intel_uc_fw_is_available(uc_fw)) + if (!intel_uc_fw_is_loadable(uc_fw)) return -ENOEXEC; /* Call custom loader */ @@ -544,7 +544,10 @@ int intel_uc_fw_init(struct intel_uc_fw *uc_fw) void intel_uc_fw_fini(struct intel_uc_fw *uc_fw) { - intel_uc_fw_cleanup_fetch(uc_fw); + if (i915_gem_object_has_pinned_pages(uc_fw->obj)) + i915_gem_object_unpin_pages(uc_fw->obj); + + intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_AVAILABLE); } /** diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h index 1f30543d0d2d..888ff0de0244 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h @@ -29,8 +29,11 @@ struct intel_gt; * | | SELECTED | * +------------+- / | \ -+ * | | MISSING <--/ | \--> ERROR | - * | fetch | | | - * | | /------> AVAILABLE <---<-----------\ | + * | fetch | V | + * | | AVAILABLE | + * +------------+- | -+ + * | init | V | + * | | /------> LOADABLE <----<-----------\ | * +------------+- \ / \ \ \ -+ * | | FAIL <--< \--> TRANSFERRED \ | * | upload | \ / \ / | @@ -46,6 +49,7 @@ enum intel_uc_fw_status { INTEL_UC_FIRMWARE_MISSING, /* blob not found on the system */ INTEL_UC_FIRMWARE_ERROR, /* invalid format or version */ INTEL_UC_FIRMWARE_AVAILABLE, /* blob found and copied in mem */ + INTEL_UC_FIRMWARE_LOADABLE, /* all fw-required objects are ready */ INTEL_UC_FIRMWARE_FAIL, /* failed to xfer or init/auth the fw */ INTEL_UC_FIRMWARE_TRANSFERRED, /* dma xfer done */ INTEL_UC_FIRMWARE_RUNNING /* init/auth done */ @@ -115,6 +119,8 @@ const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status) return "ERROR"; case INTEL_UC_FIRMWARE_AVAILABLE: return "AVAILABLE"; + case INTEL_UC_FIRMWARE_LOADABLE: + return "LOADABLE"; case INTEL_UC_FIRMWARE_FAIL: return "FAIL"; case INTEL_UC_FIRMWARE_TRANSFERRED: @@ -143,6 +149,7 @@ static inline int intel_uc_fw_status_to_error(enum intel_uc_fw_status status) case INTEL_UC_FIRMWARE_SELECTED: return -ESTALE; case INTEL_UC_FIRMWARE_AVAILABLE: + case INTEL_UC_FIRMWARE_LOADABLE: case INTEL_UC_FIRMWARE_TRANSFERRED: case INTEL_UC_FIRMWARE_RUNNING: return 0; @@ -184,6 +191,11 @@ static inline bool intel_uc_fw_is_available(struct intel_uc_fw *uc_fw) return __intel_uc_fw_status(uc_fw) >= INTEL_UC_FIRMWARE_AVAILABLE; } +static inline bool intel_uc_fw_is_loadable(struct intel_uc_fw *uc_fw) +{ + return __intel_uc_fw_status(uc_fw) >= INTEL_UC_FIRMWARE_LOADABLE; +} + static inline bool intel_uc_fw_is_loaded(struct intel_uc_fw *uc_fw) { return __intel_uc_fw_status(uc_fw) >= INTEL_UC_FIRMWARE_TRANSFERRED; @@ -202,7 +214,7 @@ static inline bool intel_uc_fw_is_overridden(const struct intel_uc_fw *uc_fw) static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw) { if (intel_uc_fw_is_loaded(uc_fw)) - intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_AVAILABLE); + intel_uc_fw_change_status(uc_fw, INTEL_UC_FIRMWARE_LOADABLE); } static inline u32 __intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw) diff --git a/drivers/gpu/drm/i915/gvt/firmware.c b/drivers/gpu/drm/i915/gvt/firmware.c index 049775e8e350..b0c1fda32977 100644 --- a/drivers/gpu/drm/i915/gvt/firmware.c +++ b/drivers/gpu/drm/i915/gvt/firmware.c @@ -146,7 +146,7 @@ void intel_gvt_free_firmware(struct intel_gvt *gvt) clean_firmware_sysfs(gvt); kfree(gvt->firmware.cfg_space); - kfree(gvt->firmware.mmio); + vfree(gvt->firmware.mmio); } static int verify_firmware(struct intel_gvt *gvt, @@ -229,7 +229,7 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt) firmware->cfg_space = mem; - mem = kmalloc(info->mmio_size, GFP_KERNEL); + mem = vmalloc(info->mmio_size); if (!mem) { kfree(path); kfree(firmware->cfg_space); diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 7090fd5c4f7c..25bd5c052909 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -1963,7 +1963,11 @@ void _intel_vgpu_mm_release(struct kref *mm_ref) if (mm->type == INTEL_GVT_MM_PPGTT) { list_del(&mm->ppgtt_mm.list); + + mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock); list_del(&mm->ppgtt_mm.lru_list); + mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock); + invalidate_ppgtt_mm(mm); } else { vfree(mm->ggtt_mm.virtual_ggtt); diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index cc89afd7b5f1..68932b33c057 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -1246,7 +1246,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) ce->vm = i915_vm_get(&ppgtt->vm); intel_context_set_single_submission(ce); - if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */ + /* Max ring buffer size */ + if (!intel_uc_wants_guc_submission(&engine->gt->uc)) { const unsigned int ring_size = 512 * SZ_4K; ce->ring = __intel_context_ring_size(ring_size); diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c index 9ccb931a733e..0b12d5023800 100644 --- a/drivers/gpu/drm/i915/i915_active.c +++ b/drivers/gpu/drm/i915/i915_active.c @@ -7,6 +7,7 @@ #include <linux/debugobjects.h> #include "gt/intel_context.h" +#include "gt/intel_engine_heartbeat.h" #include "gt/intel_engine_pm.h" #include "gt/intel_ring.h" @@ -460,26 +461,49 @@ static void enable_signaling(struct i915_active_fence *active) dma_fence_put(fence); } -int i915_active_wait(struct i915_active *ref) +static int flush_barrier(struct active_node *it) { - struct active_node *it, *n; - int err = 0; + struct intel_engine_cs *engine; - might_sleep(); + if (likely(!is_barrier(&it->base))) + return 0; - if (!i915_active_acquire_if_busy(ref)) + engine = __barrier_to_engine(it); + smp_rmb(); /* serialise with add_active_barriers */ + if (!is_barrier(&it->base)) return 0; - /* Flush lazy signals */ + return intel_engine_flush_barriers(engine); +} + +static int flush_lazy_signals(struct i915_active *ref) +{ + struct active_node *it, *n; + int err = 0; + enable_signaling(&ref->excl); rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) { - if (is_barrier(&it->base)) /* unconnected idle barrier */ - continue; + err = flush_barrier(it); /* unconnected idle barrier? */ + if (err) + break; enable_signaling(&it->base); } - /* Any fence added after the wait begins will not be auto-signaled */ + return err; +} + +int i915_active_wait(struct i915_active *ref) +{ + int err; + + might_sleep(); + + if (!i915_active_acquire_if_busy(ref)) + return 0; + + /* Any fence added after the wait begins will not be auto-signaled */ + err = flush_lazy_signals(ref); i915_active_release(ref); if (err) return err; @@ -823,7 +847,6 @@ __i915_active_fence_set(struct i915_active_fence *active, __list_del_entry(&active->cb.node); spin_unlock(prev->lock); /* serialise with prev->cb_list */ } - GEM_BUG_ON(rcu_access_pointer(active->fence) != fence); list_add_tail(&active->cb.node, &fence->cb_list); spin_unlock_irqrestore(fence->lock, flags); diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e5eea915bd0d..8f2525e4ce0f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1533,10 +1533,8 @@ stringify_guc_log_type(enum guc_log_buffer_type type) return ""; } -static void i915_guc_log_info(struct seq_file *m, - struct drm_i915_private *dev_priv) +static void i915_guc_log_info(struct seq_file *m, struct intel_guc_log *log) { - struct intel_guc_log *log = &dev_priv->gt.uc.guc.log; enum guc_log_buffer_type type; if (!intel_guc_log_relay_created(log)) { @@ -1560,11 +1558,12 @@ static void i915_guc_log_info(struct seq_file *m, static int i915_guc_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_uc *uc = &dev_priv->gt.uc; - if (!USES_GUC(dev_priv)) + if (!intel_uc_uses_guc(uc)) return -ENODEV; - i915_guc_log_info(m, dev_priv); + i915_guc_log_info(m, &uc->guc.log); /* Add more as required ... */ @@ -1574,11 +1573,11 @@ static int i915_guc_info(struct seq_file *m, void *data) static int i915_guc_stage_pool(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - const struct intel_guc *guc = &dev_priv->gt.uc.guc; - struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; + struct intel_uc *uc = &dev_priv->gt.uc; + struct guc_stage_desc *desc = uc->guc.stage_desc_pool_vaddr; int index; - if (!USES_GUC_SUBMISSION(dev_priv)) + if (!intel_uc_uses_guc_submission(uc)) return -ENODEV; for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) { @@ -1665,11 +1664,12 @@ static int i915_guc_log_dump(struct seq_file *m, void *data) static int i915_guc_log_level_get(void *data, u64 *val) { struct drm_i915_private *dev_priv = data; + struct intel_uc *uc = &dev_priv->gt.uc; - if (!USES_GUC(dev_priv)) + if (!intel_uc_uses_guc(uc)) return -ENODEV; - *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log); + *val = intel_guc_log_get_level(&uc->guc.log); return 0; } @@ -1677,11 +1677,12 @@ static int i915_guc_log_level_get(void *data, u64 *val) static int i915_guc_log_level_set(void *data, u64 val) { struct drm_i915_private *dev_priv = data; + struct intel_uc *uc = &dev_priv->gt.uc; - if (!USES_GUC(dev_priv)) + if (!intel_uc_uses_guc(uc)) return -ENODEV; - return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val); + return intel_guc_log_set_level(&uc->guc.log, val); } DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops, diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4dd8294b68e1..a87b28ee2d90 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -58,6 +58,7 @@ #include "display/intel_hotplug.h" #include "display/intel_overlay.h" #include "display/intel_pipe_crc.h" +#include "display/intel_psr.h" #include "display/intel_sprite.h" #include "display/intel_vga.h" @@ -212,7 +213,8 @@ intel_teardown_mchbar(struct drm_i915_private *dev_priv) release_resource(&dev_priv->mch_res); } -static int i915_driver_modeset_probe(struct drm_i915_private *i915) +/* part #1: call before irq install */ +static int i915_driver_modeset_probe_noirq(struct drm_i915_private *i915) { int ret; @@ -236,15 +238,28 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915) intel_csr_ucode_init(i915); - ret = intel_irq_install(i915); + ret = intel_modeset_init_noirq(i915); if (ret) - goto cleanup_csr; + goto cleanup_vga_client; + + return 0; + +cleanup_vga_client: + intel_vga_unregister(i915); +out: + return ret; +} + +/* part #2: call after irq install */ +static int i915_driver_modeset_probe(struct drm_i915_private *i915) +{ + int ret; /* Important: The output setup functions called by modeset_init need * working irqs for e.g. gmbus and dp aux transfers. */ ret = intel_modeset_init(i915); if (ret) - goto cleanup_irq; + goto out; ret = i915_gem_init(i915); if (ret) @@ -264,6 +279,8 @@ static int i915_driver_modeset_probe(struct drm_i915_private *i915) intel_init_ipc(i915); + intel_psr_set_force_mode_changed(i915->psr.dp); + return 0; cleanup_gem: @@ -271,16 +288,10 @@ cleanup_gem: i915_gem_driver_remove(i915); i915_gem_driver_release(i915); cleanup_modeset: + /* FIXME */ intel_modeset_driver_remove(i915); intel_irq_uninstall(i915); intel_modeset_driver_remove_noirq(i915); - goto cleanup_csr; -cleanup_irq: - intel_irq_uninstall(i915); -cleanup_csr: - intel_csr_ucode_fini(i915); - intel_power_domains_driver_remove(i915); - intel_vga_unregister(i915); out: return ret; } @@ -1370,8 +1381,6 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) return ERR_PTR(err); } - i915->drm.dev_private = i915; - i915->drm.pdev = pdev; pci_set_drvdata(pdev, i915); @@ -1459,10 +1468,18 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (ret < 0) goto out_cleanup_mmio; - ret = i915_driver_modeset_probe(i915); + ret = i915_driver_modeset_probe_noirq(i915); if (ret < 0) goto out_cleanup_hw; + ret = intel_irq_install(i915); + if (ret) + goto out_cleanup_modeset; + + ret = i915_driver_modeset_probe(i915); + if (ret < 0) + goto out_cleanup_irq; + i915_driver_register(i915); enable_rpm_wakeref_asserts(&i915->runtime_pm); @@ -1471,6 +1488,10 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) return 0; +out_cleanup_irq: + intel_irq_uninstall(i915); +out_cleanup_modeset: + /* FIXME */ out_cleanup_hw: i915_driver_hw_remove(i915); intel_memory_regions_driver_release(i915); @@ -1494,13 +1515,6 @@ void i915_driver_remove(struct drm_i915_private *i915) i915_driver_unregister(i915); - /* - * After unregistering the device to prevent any new users, cancel - * all in-flight requests so that we can quickly unbind the active - * resources. - */ - intel_gt_set_wedged(&i915->gt); - /* Flush any external code that still may be under the RCU lock */ synchronize_rcu(); @@ -2230,7 +2244,7 @@ const struct dev_pm_ops i915_pm_ops = { static const struct file_operations i915_driver_fops = { .owner = THIS_MODULE, .open = drm_open, - .release = drm_release, + .release = drm_release_noglobal, .unlocked_ioctl = drm_ioctl, .mmap = i915_gem_mmap, .poll = drm_poll, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9928d00ea0b1..ea13fc0b409b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -112,8 +112,8 @@ #define DRIVER_NAME "i915" #define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20200114" -#define DRIVER_TIMESTAMP 1579001978 +#define DRIVER_DATE "20200225" +#define DRIVER_TIMESTAMP 1582656081 struct drm_i915_gem_object; @@ -505,7 +505,7 @@ struct i915_psr { bool dc3co_enabled; u32 dc3co_exit_delay; struct delayed_work dc3co_work; - bool initially_probed; + bool force_mode_changed; }; #define QUIRK_LVDS_SSC_DISABLE (1<<1) @@ -1692,10 +1692,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) -/* Having GuC is not the same as using GuC */ -#define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc) -#define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc) - #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) @@ -2004,10 +2000,4 @@ i915_coherent_map_type(struct drm_i915_private *i915) return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; } -static inline bool intel_guc_submission_is_enabled(struct intel_guc *guc) -{ - return intel_guc_is_submission_supported(guc) && - intel_guc_is_ready(guc); -} - #endif diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 3d0cd0960bd2..45f3f73c3f76 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -169,6 +169,14 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), }; +static void +intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) +{ + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + + drm_crtc_handle_vblank(&crtc->base); +} + void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, i915_reg_t iir, i915_reg_t ier) { @@ -1364,7 +1372,7 @@ static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, for_each_pipe(dev_priv, pipe) { if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) - drm_handle_vblank(&dev_priv->drm, pipe); + intel_handle_vblank(dev_priv, pipe); if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) i9xx_pipe_crc_irq_handler(dev_priv, pipe); @@ -1382,7 +1390,7 @@ static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, for_each_pipe(dev_priv, pipe) { if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) - drm_handle_vblank(&dev_priv->drm, pipe); + intel_handle_vblank(dev_priv, pipe); if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) blc_event = true; @@ -1406,7 +1414,7 @@ static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, for_each_pipe(dev_priv, pipe) { if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) - drm_handle_vblank(&dev_priv->drm, pipe); + intel_handle_vblank(dev_priv, pipe); if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) blc_event = true; @@ -1432,7 +1440,7 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, for_each_pipe(dev_priv, pipe) { if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) - drm_handle_vblank(&dev_priv->drm, pipe); + intel_handle_vblank(dev_priv, pipe); if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) i9xx_pipe_crc_irq_handler(dev_priv, pipe); @@ -1739,11 +1747,12 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) if (pch_iir & SDE_POISON) drm_err(&dev_priv->drm, "PCH poison interrupt\n"); - if (pch_iir & SDE_FDI_MASK) + if (pch_iir & SDE_FDI_MASK) { for_each_pipe(dev_priv, pipe) drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", pipe_name(pipe), I915_READ(FDI_RX_IIR(pipe))); + } if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n"); @@ -1823,11 +1832,12 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) if (pch_iir & SDE_AUDIO_CP_CHG_CPT) drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n"); - if (pch_iir & SDE_FDI_MASK_CPT) + if (pch_iir & SDE_FDI_MASK_CPT) { for_each_pipe(dev_priv, pipe) drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", pipe_name(pipe), I915_READ(FDI_RX_IIR(pipe))); + } if (pch_iir & SDE_ERROR_CPT) cpt_serr_int_handler(dev_priv); @@ -1968,7 +1978,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, for_each_pipe(dev_priv, pipe) { if (de_iir & DE_PIPE_VBLANK(pipe)) - drm_handle_vblank(&dev_priv->drm, pipe); + intel_handle_vblank(dev_priv, pipe); if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); @@ -2021,7 +2031,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, for_each_pipe(dev_priv, pipe) { if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) - drm_handle_vblank(&dev_priv->drm, pipe); + intel_handle_vblank(dev_priv, pipe); } /* check event from PCH */ @@ -2334,7 +2344,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); if (iir & GEN8_PIPE_VBLANK) - drm_handle_vblank(&dev_priv->drm, pipe); + intel_handle_vblank(dev_priv, pipe); if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe); diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 24b1f0ce8743..1d678aa7d420 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -437,7 +437,7 @@ static const struct intel_device_info snb_m_gt2_info = { .has_rc6 = 1, \ .has_rc6p = 1, \ .has_rps = true, \ - .ppgtt_type = INTEL_PPGTT_FULL, \ + .ppgtt_type = INTEL_PPGTT_ALIASING, \ .ppgtt_size = 31, \ IVB_PIPE_OFFSETS, \ IVB_CURSOR_OFFSETS, \ @@ -494,7 +494,7 @@ static const struct intel_device_info vlv_info = { .has_rps = true, .display.has_gmch = 1, .display.has_hotplug = 1, - .ppgtt_type = INTEL_PPGTT_FULL, + .ppgtt_type = INTEL_PPGTT_ALIASING, .ppgtt_size = 31, .has_snoop = true, .has_coherent_ggtt = false, diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index b5249ee5bda6..e34c79df6ebc 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -555,8 +555,9 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) aging_tail = hw_tail; stream->oa_buffer.aging_timestamp = now; } else { - DRM_ERROR("Ignoring spurious out of range OA buffer tail pointer = %x\n", - hw_tail); + drm_err(&stream->perf->i915->drm, + "Ignoring spurious out of range OA buffer tail pointer = %x\n", + hw_tail); } } @@ -745,7 +746,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream, */ if (drm_WARN_ON(&uncore->i915->drm, (OA_BUFFER_SIZE - head) < report_size)) { - DRM_ERROR("Spurious OA head ptr: non-integral report offset\n"); + drm_err(&uncore->i915->drm, + "Spurious OA head ptr: non-integral report offset\n"); break; } @@ -1041,7 +1043,8 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream, */ if (drm_WARN_ON(&uncore->i915->drm, (OA_BUFFER_SIZE - head) < report_size)) { - DRM_ERROR("Spurious OA head ptr: non-integral report offset\n"); + drm_err(&uncore->i915->drm, + "Spurious OA head ptr: non-integral report offset\n"); break; } @@ -1339,9 +1342,10 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) ce->tag = stream->specific_ctx_id; - DRM_DEBUG_DRIVER("filtering on ctx_id=0x%x ctx_id_mask=0x%x\n", - stream->specific_ctx_id, - stream->specific_ctx_id_mask); + drm_dbg(&stream->perf->i915->drm, + "filtering on ctx_id=0x%x ctx_id_mask=0x%x\n", + stream->specific_ctx_id, + stream->specific_ctx_id_mask); return 0; } @@ -2657,7 +2661,8 @@ static void gen7_oa_disable(struct i915_perf_stream *stream) if (intel_wait_for_register(uncore, GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0, 50)) - DRM_ERROR("wait for OA to be disabled timed out\n"); + drm_err(&stream->perf->i915->drm, + "wait for OA to be disabled timed out\n"); } static void gen8_oa_disable(struct i915_perf_stream *stream) @@ -2668,7 +2673,8 @@ static void gen8_oa_disable(struct i915_perf_stream *stream) if (intel_wait_for_register(uncore, GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0, 50)) - DRM_ERROR("wait for OA to be disabled timed out\n"); + drm_err(&stream->perf->i915->drm, + "wait for OA to be disabled timed out\n"); } static void gen12_oa_disable(struct i915_perf_stream *stream) @@ -2680,7 +2686,8 @@ static void gen12_oa_disable(struct i915_perf_stream *stream) GEN12_OAG_OACONTROL, GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0, 50)) - DRM_ERROR("wait for OA to be disabled timed out\n"); + drm_err(&stream->perf->i915->drm, + "wait for OA to be disabled timed out\n"); } /** diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index a3b61fb96226..2c062534eac1 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -822,11 +822,6 @@ static ssize_t i915_pmu_event_show(struct device *dev, return sprintf(buf, "config=0x%lx\n", eattr->val); } -static struct attribute_group i915_pmu_events_attr_group = { - .name = "events", - /* Patch in attrs at runtime. */ -}; - static ssize_t i915_pmu_get_attr_cpumask(struct device *dev, struct device_attribute *attr, @@ -846,13 +841,6 @@ static const struct attribute_group i915_pmu_cpumask_attr_group = { .attrs = i915_cpumask_attrs, }; -static const struct attribute_group *i915_pmu_attr_groups[] = { - &i915_pmu_format_attr_group, - &i915_pmu_events_attr_group, - &i915_pmu_cpumask_attr_group, - NULL -}; - #define __event(__config, __name, __unit) \ { \ .config = (__config), \ @@ -1026,23 +1014,23 @@ err_alloc: static void free_event_attributes(struct i915_pmu *pmu) { - struct attribute **attr_iter = i915_pmu_events_attr_group.attrs; + struct attribute **attr_iter = pmu->events_attr_group.attrs; for (; *attr_iter; attr_iter++) kfree((*attr_iter)->name); - kfree(i915_pmu_events_attr_group.attrs); + kfree(pmu->events_attr_group.attrs); kfree(pmu->i915_attr); kfree(pmu->pmu_attr); - i915_pmu_events_attr_group.attrs = NULL; + pmu->events_attr_group.attrs = NULL; pmu->i915_attr = NULL; pmu->pmu_attr = NULL; } static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node) { - struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); + struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node); GEM_BUG_ON(!pmu->base.event_init); @@ -1055,7 +1043,7 @@ static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node) static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node) { - struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node); + struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node); unsigned int target; GEM_BUG_ON(!pmu->base.event_init); @@ -1072,8 +1060,6 @@ static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node) return 0; } -static enum cpuhp_state cpuhp_slot = CPUHP_INVALID; - static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu) { enum cpuhp_state slot; @@ -1087,21 +1073,22 @@ static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu) return ret; slot = ret; - ret = cpuhp_state_add_instance(slot, &pmu->node); + ret = cpuhp_state_add_instance(slot, &pmu->cpuhp.node); if (ret) { cpuhp_remove_multi_state(slot); return ret; } - cpuhp_slot = slot; + pmu->cpuhp.slot = slot; return 0; } static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu) { - WARN_ON(cpuhp_slot == CPUHP_INVALID); - WARN_ON(cpuhp_state_remove_instance(cpuhp_slot, &pmu->node)); - cpuhp_remove_multi_state(cpuhp_slot); + WARN_ON(pmu->cpuhp.slot == CPUHP_INVALID); + WARN_ON(cpuhp_state_remove_instance(pmu->cpuhp.slot, &pmu->cpuhp.node)); + cpuhp_remove_multi_state(pmu->cpuhp.slot); + pmu->cpuhp.slot = CPUHP_INVALID; } static bool is_igp(struct drm_i915_private *i915) @@ -1118,6 +1105,13 @@ static bool is_igp(struct drm_i915_private *i915) void i915_pmu_register(struct drm_i915_private *i915) { struct i915_pmu *pmu = &i915->pmu; + const struct attribute_group *attr_groups[] = { + &i915_pmu_format_attr_group, + &pmu->events_attr_group, + &i915_pmu_cpumask_attr_group, + NULL + }; + int ret = -ENOMEM; if (INTEL_GEN(i915) <= 2) { @@ -1128,6 +1122,7 @@ void i915_pmu_register(struct drm_i915_private *i915) spin_lock_init(&pmu->lock); hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); pmu->timer.function = i915_sample; + pmu->cpuhp.slot = CPUHP_INVALID; if (!is_igp(i915)) { pmu->name = kasprintf(GFP_KERNEL, @@ -1143,11 +1138,16 @@ void i915_pmu_register(struct drm_i915_private *i915) if (!pmu->name) goto err; - i915_pmu_events_attr_group.attrs = create_event_attributes(pmu); - if (!i915_pmu_events_attr_group.attrs) + pmu->events_attr_group.name = "events"; + pmu->events_attr_group.attrs = create_event_attributes(pmu); + if (!pmu->events_attr_group.attrs) goto err_name; - pmu->base.attr_groups = i915_pmu_attr_groups; + pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups), + GFP_KERNEL); + if (!pmu->base.attr_groups) + goto err_attr; + pmu->base.task_ctx_nr = perf_invalid_context; pmu->base.event_init = i915_pmu_event_init; pmu->base.add = i915_pmu_event_add; @@ -1159,7 +1159,7 @@ void i915_pmu_register(struct drm_i915_private *i915) ret = perf_pmu_register(&pmu->base, pmu->name, -1); if (ret) - goto err_attr; + goto err_groups; ret = i915_pmu_register_cpuhp_state(pmu); if (ret) @@ -1169,6 +1169,8 @@ void i915_pmu_register(struct drm_i915_private *i915) err_unreg: perf_pmu_unregister(&pmu->base); +err_groups: + kfree(pmu->base.attr_groups); err_attr: pmu->base.event_init = NULL; free_event_attributes(pmu); @@ -1194,6 +1196,7 @@ void i915_pmu_unregister(struct drm_i915_private *i915) perf_pmu_unregister(&pmu->base); pmu->base.event_init = NULL; + kfree(pmu->base.attr_groups); if (!is_igp(i915)) kfree(pmu->name); free_event_attributes(pmu); diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index 6c1647c5daf2..f1d6cad0d7d5 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -39,9 +39,12 @@ struct i915_pmu_sample { struct i915_pmu { /** - * @node: List node for CPU hotplug handling. + * @cpuhp: Struct used for CPU hotplug handling. */ - struct hlist_node node; + struct { + struct hlist_node node; + enum cpuhp_state slot; + } cpuhp; /** * @base: PMU base. */ @@ -105,6 +108,10 @@ struct i915_pmu { */ ktime_t sleep_last; /** + * @events_attr_group: Device events attribute group. + */ + struct attribute_group events_attr_group; + /** * @i915_attr: Memory block holding device attributes. */ void *i915_attr; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b09c1d6dc0aa..f45b5e86ec63 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2865,6 +2865,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ #define MBUS_ABOX_CTL _MMIO(0x45038) +#define MBUS_ABOX1_CTL _MMIO(0x45048) +#define MBUS_ABOX2_CTL _MMIO(0x4504C) #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) @@ -4928,6 +4930,7 @@ enum { #define PFIT_ENABLE (1 << 31) #define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_SHIFT 29 +#define PFIT_PIPE(pipe) ((pipe) << 29) #define VERT_INTERP_DISABLE (0 << 10) #define VERT_INTERP_BILINEAR (1 << 10) #define VERT_INTERP_MASK (3 << 10) @@ -7764,6 +7767,7 @@ enum { #define BW_BUDDY1_CTL _MMIO(0x45140) #define BW_BUDDY2_CTL _MMIO(0x45150) #define BW_BUDDY_DISABLE REG_BIT(31) +#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) #define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) #define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 6daf18dbb3d4..d53af93b919b 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -51,7 +51,6 @@ struct execute_cb { static struct i915_global_request { struct i915_global base; struct kmem_cache *slab_requests; - struct kmem_cache *slab_dependencies; struct kmem_cache *slab_execute_cbs; } global; @@ -1614,14 +1613,12 @@ out: static void i915_global_request_shrink(void) { - kmem_cache_shrink(global.slab_dependencies); kmem_cache_shrink(global.slab_execute_cbs); kmem_cache_shrink(global.slab_requests); } static void i915_global_request_exit(void) { - kmem_cache_destroy(global.slab_dependencies); kmem_cache_destroy(global.slab_execute_cbs); kmem_cache_destroy(global.slab_requests); } @@ -1651,17 +1648,9 @@ int __init i915_global_request_init(void) if (!global.slab_execute_cbs) goto err_requests; - global.slab_dependencies = KMEM_CACHE(i915_dependency, - SLAB_HWCACHE_ALIGN | - SLAB_RECLAIM_ACCOUNT); - if (!global.slab_dependencies) - goto err_execute_cbs; - i915_global_register(&global.base); return 0; -err_execute_cbs: - kmem_cache_destroy(global.slab_execute_cbs); err_requests: kmem_cache_destroy(global.slab_requests); return -ENOMEM; diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index e19a37a83397..be770f2419b1 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -363,6 +363,9 @@ static void __bump_priority(struct i915_sched_node *node, unsigned int bump) { struct i915_sched_attr attr = node->attr; + if (attr.priority & bump) + return; + attr.priority |= bump; __i915_schedule(node, &attr); } @@ -486,7 +489,7 @@ void i915_sched_node_fini(struct i915_sched_node *node) list_for_each_entry_safe(dep, tmp, &node->signalers_list, signal_link) { GEM_BUG_ON(!list_empty(&dep->dfs_link)); - list_del(&dep->wait_link); + list_del_rcu(&dep->wait_link); if (dep->flags & I915_DEPENDENCY_ALLOC) i915_dependency_free(dep); } @@ -497,7 +500,7 @@ void i915_sched_node_fini(struct i915_sched_node *node) GEM_BUG_ON(dep->signaler != node); GEM_BUG_ON(!list_empty(&dep->dfs_link)); - list_del(&dep->signal_link); + list_del_rcu(&dep->signal_link); if (dep->flags & I915_DEPENDENCY_ALLOC) i915_dependency_free(dep); } @@ -526,7 +529,8 @@ static struct i915_global_scheduler global = { { int __init i915_global_scheduler_init(void) { global.slab_dependencies = KMEM_CACHE(i915_dependency, - SLAB_HWCACHE_ALIGN); + SLAB_HWCACHE_ALIGN | + SLAB_TYPESAFE_BY_RCU); if (!global.slab_dependencies) return -ENOMEM; diff --git a/drivers/gpu/drm/i915/i915_switcheroo.c b/drivers/gpu/drm/i915/i915_switcheroo.c index 39c79e1c5b52..ed69b5d4a375 100644 --- a/drivers/gpu/drm/i915/i915_switcheroo.c +++ b/drivers/gpu/drm/i915/i915_switcheroo.c @@ -43,7 +43,7 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev) * locking inversion with the driver load path. And the access here is * completely racy anyway. So don't bother with locking for now. */ - return i915 && i915->drm.open_count == 0; + return i915 && atomic_read(&i915->drm.open_count) == 0; } static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 74dc3ba59ce5..298ca4316e65 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -919,6 +919,11 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (err) goto err_fence; + if (unlikely(i915_vma_is_closed(vma))) { + err = -ENOENT; + goto err_unlock; + } + bound = atomic_read(&vma->flags); if (unlikely(bound & I915_VMA_ERROR)) { err = -ENOMEM; diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index 38ebd5562c7c..e73fd752adef 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -105,7 +105,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) return 0; } - if (USES_GUC_SUBMISSION(dev_priv)) { + if (intel_uc_wants_guc_submission(&dev_priv->gt.uc)) { drm_err(&dev_priv->drm, "i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n"); return -EIO; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ffac0b862ca5..22aa205793e5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -469,9 +469,9 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; enum pipe pipe = crtc->pipe; int sprite0_start, sprite1_start; + u32 dsparb, dsparb2, dsparb3; switch (pipe) { - u32 dsparb, dsparb2, dsparb3; case PIPE_A: dsparb = I915_READ(DSPARB); dsparb2 = I915_READ(DSPARB2); @@ -1969,6 +1969,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, const struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; int sprite0_start, sprite1_start, fifo_size; + u32 dsparb, dsparb2, dsparb3; if (!crtc_state->fifo_changed) return; @@ -1994,7 +1995,6 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, spin_lock(&uncore->lock); switch (crtc->pipe) { - u32 dsparb, dsparb2, dsparb3; case PIPE_A: dsparb = intel_uncore_read_fw(uncore, DSPARB); dsparb2 = intel_uncore_read_fw(uncore, DSPARB2); @@ -4178,7 +4178,7 @@ struct dbuf_slice_conf_entry { * as is from BSpec itself - that way it is at least easier * to compare, change and check. */ -static struct dbuf_slice_conf_entry icl_allowed_dbufs[] = +static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] = /* Autogenerated with igt/tools/intel_dbuf_map tool: */ { { @@ -4240,7 +4240,7 @@ static struct dbuf_slice_conf_entry icl_allowed_dbufs[] = * as is from BSpec itself - that way it is at least easier * to compare, change and check. */ -static struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = +static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = /* Autogenerated with igt/tools/intel_dbuf_map tool: */ { { diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c b/drivers/gpu/drm/i915/selftests/i915_active.c index ef572a0c2566..067e30b8927f 100644 --- a/drivers/gpu/drm/i915/selftests/i915_active.c +++ b/drivers/gpu/drm/i915/selftests/i915_active.c @@ -201,11 +201,57 @@ static int live_active_retire(void *arg) return err; } +static int live_active_barrier(void *arg) +{ + struct drm_i915_private *i915 = arg; + struct intel_engine_cs *engine; + struct live_active *active; + int err = 0; + + /* Check that we get a callback when requests retire upon waiting */ + + active = __live_alloc(i915); + if (!active) + return -ENOMEM; + + err = i915_active_acquire(&active->base); + if (err) + goto out; + + for_each_uabi_engine(engine, i915) { + err = i915_active_acquire_preallocate_barrier(&active->base, + engine); + if (err) + break; + + i915_active_acquire_barrier(&active->base); + } + + i915_active_release(&active->base); + + if (err == 0) + err = i915_active_wait(&active->base); + + if (err == 0 && !READ_ONCE(active->retired)) { + pr_err("i915_active not retired after flushing barriers!\n"); + err = -EINVAL; + } + +out: + __live_put(active); + + if (igt_flush_test(i915)) + err = -EIO; + + return err; +} + int i915_active_live_selftests(struct drm_i915_private *i915) { static const struct i915_subtest tests[] = { SUBTEST(live_active_wait), SUBTEST(live_active_retire), + SUBTEST(live_active_barrier), }; if (intel_gt_is_wedged(&i915->gt)) diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 3b8986983afc..754d0eb6beaa 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -144,7 +144,6 @@ struct drm_i915_private *mock_gem_device(void) goto put_device; } i915->drm.pdev = pdev; - i915->drm.dev_private = i915; intel_runtime_pm_init_early(&i915->runtime_pm); diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c index 28826c0aa24a..6776ebb3246d 100644 --- a/drivers/gpu/drm/imx/ipuv3-plane.c +++ b/drivers/gpu/drm/imx/ipuv3-plane.c @@ -359,7 +359,7 @@ static int ipu_plane_atomic_check(struct drm_plane *plane, if (!fb) return 0; - if (!state->crtc) + if (WARN_ON(!state->crtc)) return -EINVAL; crtc_state = diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c index 3dca424059f7..142acff5ab37 100644 --- a/drivers/gpu/drm/imx/parallel-display.c +++ b/drivers/gpu/drm/imx/parallel-display.c @@ -24,6 +24,7 @@ struct imx_parallel_display { struct drm_connector connector; struct drm_encoder encoder; + struct drm_bridge bridge; struct device *dev; void *edid; int edid_len; @@ -31,7 +32,7 @@ struct imx_parallel_display { u32 bus_flags; struct drm_display_mode mode; struct drm_panel *panel; - struct drm_bridge *bridge; + struct drm_bridge *next_bridge; }; static inline struct imx_parallel_display *con_to_imxpd(struct drm_connector *c) @@ -44,6 +45,11 @@ static inline struct imx_parallel_display *enc_to_imxpd(struct drm_encoder *e) return container_of(e, struct imx_parallel_display, encoder); } +static inline struct imx_parallel_display *bridge_to_imxpd(struct drm_bridge *b) +{ + return container_of(b, struct imx_parallel_display, bridge); +} + static int imx_pd_connector_get_modes(struct drm_connector *connector) { struct imx_parallel_display *imxpd = con_to_imxpd(connector); @@ -89,37 +95,148 @@ static struct drm_encoder *imx_pd_connector_best_encoder( return &imxpd->encoder; } -static void imx_pd_encoder_enable(struct drm_encoder *encoder) +static void imx_pd_bridge_enable(struct drm_bridge *bridge) { - struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); + struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge); drm_panel_prepare(imxpd->panel); drm_panel_enable(imxpd->panel); } -static void imx_pd_encoder_disable(struct drm_encoder *encoder) +static void imx_pd_bridge_disable(struct drm_bridge *bridge) { - struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); + struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge); drm_panel_disable(imxpd->panel); drm_panel_unprepare(imxpd->panel); } -static int imx_pd_encoder_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +static const u32 imx_pd_bus_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_BGR888_1X24, + MEDIA_BUS_FMT_GBR888_1X24, + MEDIA_BUS_FMT_RGB666_1X18, + MEDIA_BUS_FMT_RGB666_1X24_CPADHI, + MEDIA_BUS_FMT_RGB565_1X16, +}; + +static u32 * +imx_pd_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) { - struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); struct drm_display_info *di = &conn_state->connector->display_info; - struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); + struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge); + u32 *output_fmts; - if (!imxpd->bus_format && di->num_bus_formats) { - imx_crtc_state->bus_flags = di->bus_flags; - imx_crtc_state->bus_format = di->bus_formats[0]; - } else { - imx_crtc_state->bus_flags = imxpd->bus_flags; - imx_crtc_state->bus_format = imxpd->bus_format; + if (!imxpd->bus_format && !di->num_bus_formats) { + *num_output_fmts = ARRAY_SIZE(imx_pd_bus_fmts); + return kmemdup(imx_pd_bus_fmts, sizeof(imx_pd_bus_fmts), + GFP_KERNEL); + } + + *num_output_fmts = 1; + output_fmts = kmalloc(sizeof(*output_fmts), GFP_KERNEL); + if (!output_fmts) + return NULL; + + if (!imxpd->bus_format && di->num_bus_formats) + output_fmts[0] = di->bus_formats[0]; + else + output_fmts[0] = imxpd->bus_format; + + return output_fmts; +} + +static bool imx_pd_format_supported(u32 output_fmt) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(imx_pd_bus_fmts); i++) { + if (imx_pd_bus_fmts[i] == output_fmt) + return true; + } + + return false; +} + +static u32 * +imx_pd_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge); + u32 *input_fmts; + + /* + * If the next bridge does not support bus format negotiation, let's + * use the static bus format definition (imxpd->bus_format) if it's + * specified, RGB888 when it's not. + */ + if (output_fmt == MEDIA_BUS_FMT_FIXED) + output_fmt = imxpd->bus_format ? : MEDIA_BUS_FMT_RGB888_1X24; + + /* Now make sure the requested output format is supported. */ + if ((imxpd->bus_format && imxpd->bus_format != output_fmt) || + !imx_pd_format_supported(output_fmt)) { + *num_input_fmts = 0; + return NULL; + } + + *num_input_fmts = 1; + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + input_fmts[0] = output_fmt; + return input_fmts; +} + +static int imx_pd_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); + struct drm_display_info *di = &conn_state->connector->display_info; + struct imx_parallel_display *imxpd = bridge_to_imxpd(bridge); + struct drm_bridge_state *next_bridge_state = NULL; + struct drm_bridge *next_bridge; + u32 bus_flags, bus_fmt; + + next_bridge = drm_bridge_get_next_bridge(bridge); + if (next_bridge) + next_bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state, + next_bridge); + + if (next_bridge_state) + bus_flags = next_bridge_state->input_bus_cfg.flags; + else if (!imxpd->bus_format && di->num_bus_formats) + bus_flags = di->bus_flags; + else + bus_flags = imxpd->bus_flags; + + bus_fmt = bridge_state->input_bus_cfg.format; + if (!imx_pd_format_supported(bus_fmt)) + return -EINVAL; + + if (bus_flags & + ~(DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | + DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)) { + dev_warn(imxpd->dev, "invalid bus_flags (%x)\n", bus_flags); + return -EINVAL; } + + bridge_state->output_bus_cfg.flags = bus_flags; + bridge_state->input_bus_cfg.flags = bus_flags; + imx_crtc_state->bus_flags = bus_flags; + imx_crtc_state->bus_format = bridge_state->input_bus_cfg.format; imx_crtc_state->di_hsync_pin = 2; imx_crtc_state->di_vsync_pin = 3; @@ -143,10 +260,15 @@ static const struct drm_encoder_funcs imx_pd_encoder_funcs = { .destroy = imx_drm_encoder_destroy, }; -static const struct drm_encoder_helper_funcs imx_pd_encoder_helper_funcs = { - .enable = imx_pd_encoder_enable, - .disable = imx_pd_encoder_disable, - .atomic_check = imx_pd_encoder_atomic_check, +static const struct drm_bridge_funcs imx_pd_bridge_funcs = { + .enable = imx_pd_bridge_enable, + .disable = imx_pd_bridge_disable, + .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_check = imx_pd_bridge_atomic_check, + .atomic_get_input_bus_fmts = imx_pd_bridge_atomic_get_input_bus_fmts, + .atomic_get_output_bus_fmts = imx_pd_bridge_atomic_get_output_bus_fmts, }; static int imx_pd_register(struct drm_device *drm, @@ -166,11 +288,13 @@ static int imx_pd_register(struct drm_device *drm, */ imxpd->connector.dpms = DRM_MODE_DPMS_OFF; - drm_encoder_helper_add(encoder, &imx_pd_encoder_helper_funcs); drm_encoder_init(drm, encoder, &imx_pd_encoder_funcs, DRM_MODE_ENCODER_NONE, NULL); - if (!imxpd->bridge) { + imxpd->bridge.funcs = &imx_pd_bridge_funcs; + drm_bridge_attach(encoder, &imxpd->bridge, NULL); + + if (!imxpd->next_bridge) { drm_connector_helper_add(&imxpd->connector, &imx_pd_connector_helper_funcs); drm_connector_init(drm, &imxpd->connector, @@ -181,8 +305,9 @@ static int imx_pd_register(struct drm_device *drm, if (imxpd->panel) drm_panel_attach(imxpd->panel, &imxpd->connector); - if (imxpd->bridge) { - ret = drm_bridge_attach(encoder, imxpd->bridge, NULL); + if (imxpd->next_bridge) { + ret = drm_bridge_attach(encoder, imxpd->next_bridge, + &imxpd->bridge); if (ret < 0) { dev_err(imxpd->dev, "failed to attach bridge: %d\n", ret); @@ -227,7 +352,8 @@ static int imx_pd_bind(struct device *dev, struct device *master, void *data) imxpd->bus_format = bus_format; /* port@1 is the output port */ - ret = drm_of_find_panel_or_bridge(np, 1, 0, &imxpd->panel, &imxpd->bridge); + ret = drm_of_find_panel_or_bridge(np, 1, 0, &imxpd->panel, + &imxpd->next_bridge); if (ret && ret != -ENODEV) return ret; diff --git a/drivers/gpu/drm/lima/lima_drv.c b/drivers/gpu/drm/lima/lima_drv.c index 124efe4fa97b..2daac64d8955 100644 --- a/drivers/gpu/drm/lima/lima_drv.c +++ b/drivers/gpu/drm/lima/lima_drv.c @@ -15,10 +15,14 @@ #include "lima_vm.h" int lima_sched_timeout_ms; +uint lima_heap_init_nr_pages = 8; MODULE_PARM_DESC(sched_timeout_ms, "task run timeout in ms"); module_param_named(sched_timeout_ms, lima_sched_timeout_ms, int, 0444); +MODULE_PARM_DESC(heap_init_nr_pages, "heap buffer init number of pages"); +module_param_named(heap_init_nr_pages, lima_heap_init_nr_pages, uint, 0444); + static int lima_ioctl_get_param(struct drm_device *dev, void *data, struct drm_file *file) { struct drm_lima_get_param *args = data; @@ -68,7 +72,7 @@ static int lima_ioctl_gem_create(struct drm_device *dev, void *data, struct drm_ if (args->pad) return -EINVAL; - if (args->flags) + if (args->flags & ~(LIMA_BO_FLAG_HEAP)) return -EINVAL; if (args->size == 0) @@ -241,6 +245,12 @@ static const struct drm_ioctl_desc lima_drm_driver_ioctls[] = { DEFINE_DRM_GEM_FOPS(lima_drm_driver_fops); +/** + * Changelog: + * + * - 1.1.0 - add heap buffer support + */ + static struct drm_driver lima_drm_driver = { .driver_features = DRIVER_RENDER | DRIVER_GEM | DRIVER_SYNCOBJ, .open = lima_drm_driver_open, @@ -250,9 +260,9 @@ static struct drm_driver lima_drm_driver = { .fops = &lima_drm_driver_fops, .name = "lima", .desc = "lima DRM", - .date = "20190217", + .date = "20191231", .major = 1, - .minor = 0, + .minor = 1, .patchlevel = 0, .gem_create_object = lima_gem_create_object, diff --git a/drivers/gpu/drm/lima/lima_drv.h b/drivers/gpu/drm/lima/lima_drv.h index 69c7344715c9..f492ecc6a5d9 100644 --- a/drivers/gpu/drm/lima/lima_drv.h +++ b/drivers/gpu/drm/lima/lima_drv.h @@ -9,6 +9,7 @@ #include "lima_ctx.h" extern int lima_sched_timeout_ms; +extern uint lima_heap_init_nr_pages; struct lima_vm; struct lima_bo; diff --git a/drivers/gpu/drm/lima/lima_gem.c b/drivers/gpu/drm/lima/lima_gem.c index d0059d8c97d8..5404e0d668db 100644 --- a/drivers/gpu/drm/lima/lima_gem.c +++ b/drivers/gpu/drm/lima/lima_gem.c @@ -4,6 +4,8 @@ #include <linux/mm.h> #include <linux/sync_file.h> #include <linux/pagemap.h> +#include <linux/shmem_fs.h> +#include <linux/dma-mapping.h> #include <drm/drm_file.h> #include <drm/drm_syncobj.h> @@ -15,6 +17,83 @@ #include "lima_gem.h" #include "lima_vm.h" +int lima_heap_alloc(struct lima_bo *bo, struct lima_vm *vm) +{ + struct page **pages; + struct address_space *mapping = bo->base.base.filp->f_mapping; + struct device *dev = bo->base.base.dev->dev; + size_t old_size = bo->heap_size; + size_t new_size = bo->heap_size ? bo->heap_size * 2 : + (lima_heap_init_nr_pages << PAGE_SHIFT); + struct sg_table sgt; + int i, ret; + + if (bo->heap_size >= bo->base.base.size) + return -ENOSPC; + + new_size = min(new_size, bo->base.base.size); + + mutex_lock(&bo->base.pages_lock); + + if (bo->base.pages) { + pages = bo->base.pages; + } else { + pages = kvmalloc_array(bo->base.base.size >> PAGE_SHIFT, + sizeof(*pages), GFP_KERNEL | __GFP_ZERO); + if (!pages) { + mutex_unlock(&bo->base.pages_lock); + return -ENOMEM; + } + + bo->base.pages = pages; + bo->base.pages_use_count = 1; + + mapping_set_unevictable(mapping); + } + + for (i = old_size >> PAGE_SHIFT; i < new_size >> PAGE_SHIFT; i++) { + struct page *page = shmem_read_mapping_page(mapping, i); + + if (IS_ERR(page)) { + mutex_unlock(&bo->base.pages_lock); + return PTR_ERR(page); + } + pages[i] = page; + } + + mutex_unlock(&bo->base.pages_lock); + + ret = sg_alloc_table_from_pages(&sgt, pages, i, 0, + new_size, GFP_KERNEL); + if (ret) + return ret; + + if (bo->base.sgt) { + dma_unmap_sg(dev, bo->base.sgt->sgl, + bo->base.sgt->nents, DMA_BIDIRECTIONAL); + sg_free_table(bo->base.sgt); + } else { + bo->base.sgt = kmalloc(sizeof(*bo->base.sgt), GFP_KERNEL); + if (!bo->base.sgt) { + sg_free_table(&sgt); + return -ENOMEM; + } + } + + dma_map_sg(dev, sgt.sgl, sgt.nents, DMA_BIDIRECTIONAL); + + *bo->base.sgt = sgt; + + if (vm) { + ret = lima_vm_map_bo(vm, bo, old_size >> PAGE_SHIFT); + if (ret) + return ret; + } + + bo->heap_size = new_size; + return 0; +} + int lima_gem_create_handle(struct drm_device *dev, struct drm_file *file, u32 size, u32 flags, u32 *handle) { @@ -22,7 +101,8 @@ int lima_gem_create_handle(struct drm_device *dev, struct drm_file *file, gfp_t mask; struct drm_gem_shmem_object *shmem; struct drm_gem_object *obj; - struct sg_table *sgt; + struct lima_bo *bo; + bool is_heap = flags & LIMA_BO_FLAG_HEAP; shmem = drm_gem_shmem_create(dev, size); if (IS_ERR(shmem)) @@ -36,10 +116,18 @@ int lima_gem_create_handle(struct drm_device *dev, struct drm_file *file, mask |= __GFP_DMA32; mapping_set_gfp_mask(obj->filp->f_mapping, mask); - sgt = drm_gem_shmem_get_pages_sgt(obj); - if (IS_ERR(sgt)) { - err = PTR_ERR(sgt); - goto out; + if (is_heap) { + bo = to_lima_bo(obj); + err = lima_heap_alloc(bo, NULL); + if (err) + goto out; + } else { + struct sg_table *sgt = drm_gem_shmem_get_pages_sgt(obj); + + if (IS_ERR(sgt)) { + err = PTR_ERR(sgt); + goto out; + } } err = drm_gem_handle_create(file, obj, handle); @@ -79,17 +167,47 @@ static void lima_gem_object_close(struct drm_gem_object *obj, struct drm_file *f lima_vm_bo_del(vm, bo); } +static int lima_gem_pin(struct drm_gem_object *obj) +{ + struct lima_bo *bo = to_lima_bo(obj); + + if (bo->heap_size) + return -EINVAL; + + return drm_gem_shmem_pin(obj); +} + +static void *lima_gem_vmap(struct drm_gem_object *obj) +{ + struct lima_bo *bo = to_lima_bo(obj); + + if (bo->heap_size) + return ERR_PTR(-EINVAL); + + return drm_gem_shmem_vmap(obj); +} + +static int lima_gem_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) +{ + struct lima_bo *bo = to_lima_bo(obj); + + if (bo->heap_size) + return -EINVAL; + + return drm_gem_shmem_mmap(obj, vma); +} + static const struct drm_gem_object_funcs lima_gem_funcs = { .free = lima_gem_free_object, .open = lima_gem_object_open, .close = lima_gem_object_close, .print_info = drm_gem_shmem_print_info, - .pin = drm_gem_shmem_pin, + .pin = lima_gem_pin, .unpin = drm_gem_shmem_unpin, .get_sg_table = drm_gem_shmem_get_sg_table, - .vmap = drm_gem_shmem_vmap, + .vmap = lima_gem_vmap, .vunmap = drm_gem_shmem_vunmap, - .mmap = drm_gem_shmem_mmap, + .mmap = lima_gem_mmap, }; struct drm_gem_object *lima_gem_create_object(struct drm_device *dev, size_t size) diff --git a/drivers/gpu/drm/lima/lima_gem.h b/drivers/gpu/drm/lima/lima_gem.h index 1800feb3e47f..ccea06142f4b 100644 --- a/drivers/gpu/drm/lima/lima_gem.h +++ b/drivers/gpu/drm/lima/lima_gem.h @@ -7,12 +7,15 @@ #include <drm/drm_gem_shmem_helper.h> struct lima_submit; +struct lima_vm; struct lima_bo { struct drm_gem_shmem_object base; struct mutex lock; struct list_head va; + + size_t heap_size; }; static inline struct lima_bo * @@ -31,6 +34,7 @@ static inline struct dma_resv *lima_bo_resv(struct lima_bo *bo) return bo->base.base.resv; } +int lima_heap_alloc(struct lima_bo *bo, struct lima_vm *vm); struct drm_gem_object *lima_gem_create_object(struct drm_device *dev, size_t size); int lima_gem_create_handle(struct drm_device *dev, struct drm_file *file, u32 size, u32 flags, u32 *handle); diff --git a/drivers/gpu/drm/lima/lima_gp.c b/drivers/gpu/drm/lima/lima_gp.c index ccf49faedebf..52b210f9a605 100644 --- a/drivers/gpu/drm/lima/lima_gp.c +++ b/drivers/gpu/drm/lima/lima_gp.c @@ -11,6 +11,8 @@ #include "lima_device.h" #include "lima_gp.h" #include "lima_regs.h" +#include "lima_gem.h" +#include "lima_vm.h" #define gp_write(reg, data) writel(data, ip->iomem + reg) #define gp_read(reg) readl(ip->iomem + reg) @@ -20,6 +22,7 @@ static irqreturn_t lima_gp_irq_handler(int irq, void *data) struct lima_ip *ip = data; struct lima_device *dev = ip->dev; struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_gp; + struct lima_sched_task *task = pipe->current_task; u32 state = gp_read(LIMA_GP_INT_STAT); u32 status = gp_read(LIMA_GP_STATUS); bool done = false; @@ -29,8 +32,16 @@ static irqreturn_t lima_gp_irq_handler(int irq, void *data) return IRQ_NONE; if (state & LIMA_GP_IRQ_MASK_ERROR) { - dev_err(dev->dev, "gp error irq state=%x status=%x\n", - state, status); + if ((state & LIMA_GP_IRQ_MASK_ERROR) == + LIMA_GP_IRQ_PLBU_OUT_OF_MEM) { + dev_dbg(dev->dev, "gp out of heap irq status=%x\n", + status); + } else { + dev_err(dev->dev, "gp error irq state=%x status=%x\n", + state, status); + if (task) + task->recoverable = false; + } /* mask all interrupts before hard reset */ gp_write(LIMA_GP_INT_MASK, 0); @@ -43,6 +54,7 @@ static irqreturn_t lima_gp_irq_handler(int irq, void *data) bool active = status & (LIMA_GP_STATUS_VS_ACTIVE | LIMA_GP_STATUS_PLBU_ACTIVE); done = valid && !active; + pipe->error = false; } gp_write(LIMA_GP_INT_CLEAR, state); @@ -121,6 +133,22 @@ static void lima_gp_task_run(struct lima_sched_pipe *pipe, u32 cmd = 0; int i; + /* update real heap buffer size for GP */ + for (i = 0; i < task->num_bos; i++) { + struct lima_bo *bo = task->bos[i]; + + if (bo->heap_size && + lima_vm_get_va(task->vm, bo) == + f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2]) { + f[LIMA_GP_PLBU_ALLOC_END_ADDR >> 2] = + f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2] + + bo->heap_size; + task->recoverable = true; + task->heap = bo; + break; + } + } + if (f[LIMA_GP_VSCL_START_ADDR >> 2] != f[LIMA_GP_VSCL_END_ADDR >> 2]) cmd |= LIMA_GP_CMD_START_VS; @@ -184,6 +212,31 @@ static void lima_gp_task_mmu_error(struct lima_sched_pipe *pipe) lima_sched_pipe_task_done(pipe); } +static int lima_gp_task_recover(struct lima_sched_pipe *pipe) +{ + struct lima_ip *ip = pipe->processor[0]; + struct lima_sched_task *task = pipe->current_task; + struct drm_lima_gp_frame *frame = task->frame; + u32 *f = frame->frame; + size_t fail_size = + f[LIMA_GP_PLBU_ALLOC_END_ADDR >> 2] - + f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2]; + + if (fail_size == task->heap->heap_size) { + int ret; + + ret = lima_heap_alloc(task->heap, task->vm); + if (ret < 0) + return ret; + } + + gp_write(LIMA_GP_INT_MASK, LIMA_GP_IRQ_MASK_USED); + gp_write(LIMA_GP_PLBU_ALLOC_END_ADDR, + f[LIMA_GP_PLBU_ALLOC_START_ADDR >> 2] + task->heap->heap_size); + gp_write(LIMA_GP_CMD, LIMA_GP_CMD_UPDATE_PLBU_ALLOC); + return 0; +} + static void lima_gp_print_version(struct lima_ip *ip) { u32 version, major, minor; @@ -270,6 +323,7 @@ int lima_gp_pipe_init(struct lima_device *dev) pipe->task_fini = lima_gp_task_fini; pipe->task_error = lima_gp_task_error; pipe->task_mmu_error = lima_gp_task_mmu_error; + pipe->task_recover = lima_gp_task_recover; return 0; } diff --git a/drivers/gpu/drm/lima/lima_mmu.c b/drivers/gpu/drm/lima/lima_mmu.c index 97ec09dee572..f79d2af427e7 100644 --- a/drivers/gpu/drm/lima/lima_mmu.c +++ b/drivers/gpu/drm/lima/lima_mmu.c @@ -99,6 +99,11 @@ void lima_mmu_fini(struct lima_ip *ip) } +void lima_mmu_flush_tlb(struct lima_ip *ip) +{ + mmu_write(LIMA_MMU_COMMAND, LIMA_MMU_COMMAND_ZAP_CACHE); +} + void lima_mmu_switch_vm(struct lima_ip *ip, struct lima_vm *vm) { struct lima_device *dev = ip->dev; diff --git a/drivers/gpu/drm/lima/lima_mmu.h b/drivers/gpu/drm/lima/lima_mmu.h index 8c78319bcc8e..4f8ccbebcba1 100644 --- a/drivers/gpu/drm/lima/lima_mmu.h +++ b/drivers/gpu/drm/lima/lima_mmu.h @@ -10,6 +10,7 @@ struct lima_vm; int lima_mmu_init(struct lima_ip *ip); void lima_mmu_fini(struct lima_ip *ip); +void lima_mmu_flush_tlb(struct lima_ip *ip); void lima_mmu_switch_vm(struct lima_ip *ip, struct lima_vm *vm); void lima_mmu_page_fault_resume(struct lima_ip *ip); diff --git a/drivers/gpu/drm/lima/lima_regs.h b/drivers/gpu/drm/lima/lima_regs.h index ace8ecefbe90..0124c90e0153 100644 --- a/drivers/gpu/drm/lima/lima_regs.h +++ b/drivers/gpu/drm/lima/lima_regs.h @@ -239,6 +239,7 @@ #define LIMA_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) #define LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) #define LIMA_MMU_STATUS_BUS_ID(x) ((x >> 6) & 0x1F) +#define LIMA_MMU_STATUS_STALL_NOT_ACTIVE BIT(31) #define LIMA_MMU_COMMAND 0x0008 #define LIMA_MMU_COMMAND_ENABLE_PAGING 0x00 #define LIMA_MMU_COMMAND_DISABLE_PAGING 0x01 diff --git a/drivers/gpu/drm/lima/lima_sched.c b/drivers/gpu/drm/lima/lima_sched.c index b561dd05bd62..3886999b4533 100644 --- a/drivers/gpu/drm/lima/lima_sched.c +++ b/drivers/gpu/drm/lima/lima_sched.c @@ -313,6 +313,26 @@ static const struct drm_sched_backend_ops lima_sched_ops = { .free_job = lima_sched_free_job, }; +static void lima_sched_recover_work(struct work_struct *work) +{ + struct lima_sched_pipe *pipe = + container_of(work, struct lima_sched_pipe, recover_work); + int i; + + for (i = 0; i < pipe->num_l2_cache; i++) + lima_l2_cache_flush(pipe->l2_cache[i]); + + if (pipe->bcast_mmu) { + lima_mmu_flush_tlb(pipe->bcast_mmu); + } else { + for (i = 0; i < pipe->num_mmu; i++) + lima_mmu_flush_tlb(pipe->mmu[i]); + } + + if (pipe->task_recover(pipe)) + drm_sched_fault(&pipe->base); +} + int lima_sched_pipe_init(struct lima_sched_pipe *pipe, const char *name) { unsigned int timeout = lima_sched_timeout_ms > 0 ? @@ -321,6 +341,8 @@ int lima_sched_pipe_init(struct lima_sched_pipe *pipe, const char *name) pipe->fence_context = dma_fence_context_alloc(1); spin_lock_init(&pipe->fence_lock); + INIT_WORK(&pipe->recover_work, lima_sched_recover_work); + return drm_sched_init(&pipe->base, &lima_sched_ops, 1, 0, msecs_to_jiffies(timeout), name); } @@ -332,11 +354,14 @@ void lima_sched_pipe_fini(struct lima_sched_pipe *pipe) void lima_sched_pipe_task_done(struct lima_sched_pipe *pipe) { - if (pipe->error) - drm_sched_fault(&pipe->base); - else { - struct lima_sched_task *task = pipe->current_task; - + struct lima_sched_task *task = pipe->current_task; + + if (pipe->error) { + if (task && task->recoverable) + schedule_work(&pipe->recover_work); + else + drm_sched_fault(&pipe->base); + } else { pipe->task_fini(pipe); dma_fence_signal(task->fence); } diff --git a/drivers/gpu/drm/lima/lima_sched.h b/drivers/gpu/drm/lima/lima_sched.h index 1d814fecbcc0..d64393fb50a9 100644 --- a/drivers/gpu/drm/lima/lima_sched.h +++ b/drivers/gpu/drm/lima/lima_sched.h @@ -20,6 +20,9 @@ struct lima_sched_task { struct lima_bo **bos; int num_bos; + bool recoverable; + struct lima_bo *heap; + /* pipe fence */ struct dma_fence *fence; }; @@ -68,6 +71,9 @@ struct lima_sched_pipe { void (*task_fini)(struct lima_sched_pipe *pipe); void (*task_error)(struct lima_sched_pipe *pipe); void (*task_mmu_error)(struct lima_sched_pipe *pipe); + int (*task_recover)(struct lima_sched_pipe *pipe); + + struct work_struct recover_work; }; int lima_sched_task_init(struct lima_sched_task *task, diff --git a/drivers/gpu/drm/lima/lima_vm.c b/drivers/gpu/drm/lima/lima_vm.c index 840e2350d872..5b92fb82674a 100644 --- a/drivers/gpu/drm/lima/lima_vm.c +++ b/drivers/gpu/drm/lima/lima_vm.c @@ -155,6 +155,7 @@ err_out0: void lima_vm_bo_del(struct lima_vm *vm, struct lima_bo *bo) { struct lima_bo_va *bo_va; + u32 size; mutex_lock(&bo->lock); @@ -166,8 +167,9 @@ void lima_vm_bo_del(struct lima_vm *vm, struct lima_bo *bo) mutex_lock(&vm->lock); + size = bo->heap_size ? bo->heap_size : bo_va->node.size; lima_vm_unmap_range(vm, bo_va->node.start, - bo_va->node.start + bo_va->node.size - 1); + bo_va->node.start + size - 1); drm_mm_remove_node(&bo_va->node); @@ -277,3 +279,45 @@ void lima_vm_print(struct lima_vm *vm) } } } + +int lima_vm_map_bo(struct lima_vm *vm, struct lima_bo *bo, int pageoff) +{ + struct lima_bo_va *bo_va; + struct sg_dma_page_iter sg_iter; + int offset = 0, err; + u32 base; + + mutex_lock(&bo->lock); + + bo_va = lima_vm_bo_find(vm, bo); + if (!bo_va) { + err = -ENOENT; + goto err_out0; + } + + mutex_lock(&vm->lock); + + base = bo_va->node.start + (pageoff << PAGE_SHIFT); + for_each_sg_dma_page(bo->base.sgt->sgl, &sg_iter, + bo->base.sgt->nents, pageoff) { + err = lima_vm_map_page(vm, sg_page_iter_dma_address(&sg_iter), + base + offset); + if (err) + goto err_out1; + + offset += PAGE_SIZE; + } + + mutex_unlock(&vm->lock); + + mutex_unlock(&bo->lock); + return 0; + +err_out1: + if (offset) + lima_vm_unmap_range(vm, base, base + offset - 1); + mutex_unlock(&vm->lock); +err_out0: + mutex_unlock(&bo->lock); + return err; +} diff --git a/drivers/gpu/drm/lima/lima_vm.h b/drivers/gpu/drm/lima/lima_vm.h index e0bdedcf14dd..22aeec77d84d 100644 --- a/drivers/gpu/drm/lima/lima_vm.h +++ b/drivers/gpu/drm/lima/lima_vm.h @@ -58,5 +58,6 @@ static inline void lima_vm_put(struct lima_vm *vm) } void lima_vm_print(struct lima_vm *vm); +int lima_vm_map_bo(struct lima_vm *vm, struct lima_bo *bo, int pageoff); #endif diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 8f6100db90ed..1c894548dd72 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -751,9 +751,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id); hw = clk_hw_register_mux(dev, clk_name, - (const char *[]){ + ((const char *[]){ parent, parent2, parent3, parent4 - }, 4, 0, pll_10nm->phy_cmn_mmio + + }), 4, 0, pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1, 0, 2, 0, NULL); if (IS_ERR(hw)) { diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c index 8c99e01ae332..6dffd7f4a99b 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c @@ -554,9 +554,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id); snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id); clks[num++] = clk_register_mux(dev, clk_name, - (const char *[]){ + ((const char *[]){ parent1, parent2 - }, 2, CLK_SET_RATE_PARENT, pll_28nm->mmio + + }), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL); snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index f50fefb87040..e4b750b0c2d3 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -138,7 +138,7 @@ void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, size = resource_size(res); - ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); + ptr = devm_ioremap(&pdev->dev, res->start, size); if (!ptr) { DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name); return ERR_PTR(-ENOMEM); @@ -441,6 +441,14 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) if (ret) goto err_msm_uninit; + if (!dev->dma_parms) { + dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), + GFP_KERNEL); + if (!dev->dma_parms) + return -ENOMEM; + } + dma_set_max_seg_size(dev, DMA_BIT_MASK(32)); + msm_gem_shrinker_init(ddev); switch (get_mdp_ver(pdev)) { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 71547e756e29..740bf7c70d8f 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -454,8 +454,7 @@ static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) remaining_jiffies = 0; } else { ktime_t rem = ktime_sub(*timeout, now); - struct timespec ts = ktime_to_timespec(rem); - remaining_jiffies = timespec_to_jiffies(&ts); + remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); } return remaining_jiffies; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 1b62ccc57aef..2b4b21b02e40 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -647,13 +647,6 @@ nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) } static int -nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) -{ - /* We'll do this from user space. */ - return 0; -} - -static int nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, struct ttm_mem_type_manager *man) { @@ -1697,7 +1690,6 @@ struct ttm_bo_driver nouveau_bo_driver = { .ttm_tt_create = &nouveau_ttm_tt_create, .ttm_tt_populate = &nouveau_ttm_tt_populate, .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, - .invalidate_caches = nouveau_bo_invalidate_caches, .init_mem_type = nouveau_bo_init_mem_type, .eviction_valuable = ttm_bo_eviction_valuable, .evict_flags = nouveau_bo_evict_flags, diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c index d865d8aeac3c..c85dd8afa3c3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vga.c +++ b/drivers/gpu/drm/nouveau/nouveau_vga.c @@ -72,7 +72,7 @@ nouveau_switcheroo_can_switch(struct pci_dev *pdev) * locking inversion with the driver load path. And the access here is * completely racy anyway. So don't bother with locking for now. */ - return dev->open_count == 0; + return atomic_read(&dev->open_count) == 0; } static const struct vga_switcheroo_client_ops diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index ae44ac2ec106..da3b84602cdd 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -29,6 +29,15 @@ config DRM_PANEL_BOE_HIMAX8279D 24 bit RGB per pixel. It provides a MIPI DSI interface to the host and has a built-in LED backlight. +config DRM_PANEL_BOE_TV101WUM_NL6 + tristate "BOE TV101WUM and AUO KD101N80 45NA 1200x1920 panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to support for BOE TV101WUM and AUO KD101N80 + 45NA WUXGA PANEL DSI Video Mode panel + config DRM_PANEL_LVDS tristate "Generic LVDS panel driver" depends on OF @@ -50,6 +59,15 @@ config DRM_PANEL_SIMPLE that it can be automatically turned off when the panel goes into a low power state. +config DRM_PANEL_FEIXIN_K101_IM2BA02 + tristate "Feixin K101 IM2BA02 panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for the Feixin K101 IM2BA02 + 4-lane 800x1280 MIPI DSI panel. + config DRM_PANEL_FEIYANG_FY07024DI26A30D tristate "Feiyang FY07024DI26A30-D MIPI-DSI LCD panel" depends on OF @@ -275,6 +293,12 @@ config DRM_PANEL_SAMSUNG_S6E63M0 Say Y here if you want to enable support for Samsung S6E63M0 AMOLED LCD panel. +config DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 + tristate "Samsung AMS452EF01 panel with S6E88A0 DSI video mode controller" + depends on OF + select DRM_MIPI_DSI + select VIDEOMODE_HELPERS + config DRM_PANEL_SAMSUNG_S6E8AA0 tristate "Samsung S6E8AA0 DSI video mode panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 7c4d3c581fd4..af1e2a3cc5fc 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -1,8 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o +obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o +obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o @@ -28,6 +30,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D16D0) += panel-samsung-s6d16d0.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0) += panel-samsung-s6e63m0.o +obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01) += panel-samsung-s6e88a0-ams452ef01.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) += panel-samsung-s6e8aa0.o obj-$(CONFIG_DRM_PANEL_SEIKO_43WVF1G) += panel-seiko-43wvf1g.o obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c new file mode 100644 index 000000000000..48a164257d18 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Jitao Shi <jitao.shi@mediatek.com> + */ + +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/regulator/consumer.h> + +#include <drm/drm_crtc.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_panel.h> + +#include <video/mipi_display.h> + +struct panel_desc { + const struct drm_display_mode *modes; + unsigned int bpc; + + /** + * @width_mm: width of the panel's active display area + * @height_mm: height of the panel's active display area + */ + struct { + unsigned int width_mm; + unsigned int height_mm; + } size; + + unsigned long mode_flags; + enum mipi_dsi_pixel_format format; + const struct panel_init_cmd *init_cmds; + unsigned int lanes; + bool discharge_on_disable; +}; + +struct boe_panel { + struct drm_panel base; + struct mipi_dsi_device *dsi; + + const struct panel_desc *desc; + + struct regulator *pp1800; + struct regulator *avee; + struct regulator *avdd; + struct gpio_desc *enable_gpio; + + bool prepared; +}; + +enum dsi_cmd_type { + INIT_DCS_CMD, + DELAY_CMD, +}; + +struct panel_init_cmd { + enum dsi_cmd_type type; + size_t len; + const char *data; +}; + +#define _INIT_DCS_CMD(...) { \ + .type = INIT_DCS_CMD, \ + .len = sizeof((char[]){__VA_ARGS__}), \ + .data = (char[]){__VA_ARGS__} } + +#define _INIT_DELAY_CMD(...) { \ + .type = DELAY_CMD,\ + .len = sizeof((char[]){__VA_ARGS__}), \ + .data = (char[]){__VA_ARGS__} } + +static const struct panel_init_cmd boe_init_cmd[] = { + _INIT_DELAY_CMD(24), + _INIT_DCS_CMD(0xB0, 0x05), + _INIT_DCS_CMD(0xB1, 0xE5), + _INIT_DCS_CMD(0xB3, 0x52), + _INIT_DCS_CMD(0xB0, 0x00), + _INIT_DCS_CMD(0xB3, 0x88), + _INIT_DCS_CMD(0xB0, 0x04), + _INIT_DCS_CMD(0xB8, 0x00), + _INIT_DCS_CMD(0xB0, 0x00), + _INIT_DCS_CMD(0xB6, 0x03), + _INIT_DCS_CMD(0xBA, 0x8B), + _INIT_DCS_CMD(0xBF, 0x1A), + _INIT_DCS_CMD(0xC0, 0x0F), + _INIT_DCS_CMD(0xC2, 0x0C), + _INIT_DCS_CMD(0xC3, 0x02), + _INIT_DCS_CMD(0xC4, 0x0C), + _INIT_DCS_CMD(0xC5, 0x02), + _INIT_DCS_CMD(0xB0, 0x01), + _INIT_DCS_CMD(0xE0, 0x26), + _INIT_DCS_CMD(0xE1, 0x26), + _INIT_DCS_CMD(0xDC, 0x00), + _INIT_DCS_CMD(0xDD, 0x00), + _INIT_DCS_CMD(0xCC, 0x26), + _INIT_DCS_CMD(0xCD, 0x26), + _INIT_DCS_CMD(0xC8, 0x00), + _INIT_DCS_CMD(0xC9, 0x00), + _INIT_DCS_CMD(0xD2, 0x03), + _INIT_DCS_CMD(0xD3, 0x03), + _INIT_DCS_CMD(0xE6, 0x04), + _INIT_DCS_CMD(0xE7, 0x04), + _INIT_DCS_CMD(0xC4, 0x09), + _INIT_DCS_CMD(0xC5, 0x09), + _INIT_DCS_CMD(0xD8, 0x0A), + _INIT_DCS_CMD(0xD9, 0x0A), + _INIT_DCS_CMD(0xC2, 0x0B), + _INIT_DCS_CMD(0xC3, 0x0B), + _INIT_DCS_CMD(0xD6, 0x0C), + _INIT_DCS_CMD(0xD7, 0x0C), + _INIT_DCS_CMD(0xC0, 0x05), + _INIT_DCS_CMD(0xC1, 0x05), + _INIT_DCS_CMD(0xD4, 0x06), + _INIT_DCS_CMD(0xD5, 0x06), + _INIT_DCS_CMD(0xCA, 0x07), + _INIT_DCS_CMD(0xCB, 0x07), + _INIT_DCS_CMD(0xDE, 0x08), + _INIT_DCS_CMD(0xDF, 0x08), + _INIT_DCS_CMD(0xB0, 0x02), + _INIT_DCS_CMD(0xC0, 0x00), + _INIT_DCS_CMD(0xC1, 0x0D), + _INIT_DCS_CMD(0xC2, 0x17), + _INIT_DCS_CMD(0xC3, 0x26), + _INIT_DCS_CMD(0xC4, 0x31), + _INIT_DCS_CMD(0xC5, 0x1C), + _INIT_DCS_CMD(0xC6, 0x2C), + _INIT_DCS_CMD(0xC7, 0x33), + _INIT_DCS_CMD(0xC8, 0x31), + _INIT_DCS_CMD(0xC9, 0x37), + _INIT_DCS_CMD(0xCA, 0x37), + _INIT_DCS_CMD(0xCB, 0x37), + _INIT_DCS_CMD(0xCC, 0x39), + _INIT_DCS_CMD(0xCD, 0x2E), + _INIT_DCS_CMD(0xCE, 0x2F), + _INIT_DCS_CMD(0xCF, 0x2F), + _INIT_DCS_CMD(0xD0, 0x07), + _INIT_DCS_CMD(0xD2, 0x00), + _INIT_DCS_CMD(0xD3, 0x0D), + _INIT_DCS_CMD(0xD4, 0x17), + _INIT_DCS_CMD(0xD5, 0x26), + _INIT_DCS_CMD(0xD6, 0x31), + _INIT_DCS_CMD(0xD7, 0x3F), + _INIT_DCS_CMD(0xD8, 0x3F), + _INIT_DCS_CMD(0xD9, 0x3F), + _INIT_DCS_CMD(0xDA, 0x3F), + _INIT_DCS_CMD(0xDB, 0x37), + _INIT_DCS_CMD(0xDC, 0x37), + _INIT_DCS_CMD(0xDD, 0x37), + _INIT_DCS_CMD(0xDE, 0x39), + _INIT_DCS_CMD(0xDF, 0x2E), + _INIT_DCS_CMD(0xE0, 0x2F), + _INIT_DCS_CMD(0xE1, 0x2F), + _INIT_DCS_CMD(0xE2, 0x07), + _INIT_DCS_CMD(0xB0, 0x03), + _INIT_DCS_CMD(0xC8, 0x0B), + _INIT_DCS_CMD(0xC9, 0x07), + _INIT_DCS_CMD(0xC3, 0x00), + _INIT_DCS_CMD(0xE7, 0x00), + _INIT_DCS_CMD(0xC5, 0x2A), + _INIT_DCS_CMD(0xDE, 0x2A), + _INIT_DCS_CMD(0xCA, 0x43), + _INIT_DCS_CMD(0xC9, 0x07), + _INIT_DCS_CMD(0xE4, 0xC0), + _INIT_DCS_CMD(0xE5, 0x0D), + _INIT_DCS_CMD(0xCB, 0x00), + _INIT_DCS_CMD(0xB0, 0x06), + _INIT_DCS_CMD(0xB8, 0xA5), + _INIT_DCS_CMD(0xC0, 0xA5), + _INIT_DCS_CMD(0xC7, 0x0F), + _INIT_DCS_CMD(0xD5, 0x32), + _INIT_DCS_CMD(0xB8, 0x00), + _INIT_DCS_CMD(0xC0, 0x00), + _INIT_DCS_CMD(0xBC, 0x00), + _INIT_DCS_CMD(0xB0, 0x07), + _INIT_DCS_CMD(0xB1, 0x00), + _INIT_DCS_CMD(0xB2, 0x02), + _INIT_DCS_CMD(0xB3, 0x0F), + _INIT_DCS_CMD(0xB4, 0x25), + _INIT_DCS_CMD(0xB5, 0x39), + _INIT_DCS_CMD(0xB6, 0x4E), + _INIT_DCS_CMD(0xB7, 0x72), + _INIT_DCS_CMD(0xB8, 0x97), + _INIT_DCS_CMD(0xB9, 0xDC), + _INIT_DCS_CMD(0xBA, 0x22), + _INIT_DCS_CMD(0xBB, 0xA4), + _INIT_DCS_CMD(0xBC, 0x2B), + _INIT_DCS_CMD(0xBD, 0x2F), + _INIT_DCS_CMD(0xBE, 0xA9), + _INIT_DCS_CMD(0xBF, 0x25), + _INIT_DCS_CMD(0xC0, 0x61), + _INIT_DCS_CMD(0xC1, 0x97), + _INIT_DCS_CMD(0xC2, 0xB2), + _INIT_DCS_CMD(0xC3, 0xCD), + _INIT_DCS_CMD(0xC4, 0xD9), + _INIT_DCS_CMD(0xC5, 0xE7), + _INIT_DCS_CMD(0xC6, 0xF4), + _INIT_DCS_CMD(0xC7, 0xFA), + _INIT_DCS_CMD(0xC8, 0xFC), + _INIT_DCS_CMD(0xC9, 0x00), + _INIT_DCS_CMD(0xCA, 0x00), + _INIT_DCS_CMD(0xCB, 0x16), + _INIT_DCS_CMD(0xCC, 0xAF), + _INIT_DCS_CMD(0xCD, 0xFF), + _INIT_DCS_CMD(0xCE, 0xFF), + _INIT_DCS_CMD(0xB0, 0x08), + _INIT_DCS_CMD(0xB1, 0x04), + _INIT_DCS_CMD(0xB2, 0x05), + _INIT_DCS_CMD(0xB3, 0x11), + _INIT_DCS_CMD(0xB4, 0x24), + _INIT_DCS_CMD(0xB5, 0x39), + _INIT_DCS_CMD(0xB6, 0x4F), + _INIT_DCS_CMD(0xB7, 0x72), + _INIT_DCS_CMD(0xB8, 0x98), + _INIT_DCS_CMD(0xB9, 0xDC), + _INIT_DCS_CMD(0xBA, 0x23), + _INIT_DCS_CMD(0xBB, 0xA6), + _INIT_DCS_CMD(0xBC, 0x2C), + _INIT_DCS_CMD(0xBD, 0x30), + _INIT_DCS_CMD(0xBE, 0xAA), + _INIT_DCS_CMD(0xBF, 0x26), + _INIT_DCS_CMD(0xC0, 0x62), + _INIT_DCS_CMD(0xC1, 0x9B), + _INIT_DCS_CMD(0xC2, 0xB5), + _INIT_DCS_CMD(0xC3, 0xCF), + _INIT_DCS_CMD(0xC4, 0xDB), + _INIT_DCS_CMD(0xC5, 0xE8), + _INIT_DCS_CMD(0xC6, 0xF5), + _INIT_DCS_CMD(0xC7, 0xFA), + _INIT_DCS_CMD(0xC8, 0xFC), + _INIT_DCS_CMD(0xC9, 0x00), + _INIT_DCS_CMD(0xCA, 0x00), + _INIT_DCS_CMD(0xCB, 0x16), + _INIT_DCS_CMD(0xCC, 0xAF), + _INIT_DCS_CMD(0xCD, 0xFF), + _INIT_DCS_CMD(0xCE, 0xFF), + _INIT_DCS_CMD(0xB0, 0x09), + _INIT_DCS_CMD(0xB1, 0x04), + _INIT_DCS_CMD(0xB2, 0x02), + _INIT_DCS_CMD(0xB3, 0x16), + _INIT_DCS_CMD(0xB4, 0x24), + _INIT_DCS_CMD(0xB5, 0x3B), + _INIT_DCS_CMD(0xB6, 0x4F), + _INIT_DCS_CMD(0xB7, 0x73), + _INIT_DCS_CMD(0xB8, 0x99), + _INIT_DCS_CMD(0xB9, 0xE0), + _INIT_DCS_CMD(0xBA, 0x26), + _INIT_DCS_CMD(0xBB, 0xAD), + _INIT_DCS_CMD(0xBC, 0x36), + _INIT_DCS_CMD(0xBD, 0x3A), + _INIT_DCS_CMD(0xBE, 0xAE), + _INIT_DCS_CMD(0xBF, 0x2A), + _INIT_DCS_CMD(0xC0, 0x66), + _INIT_DCS_CMD(0xC1, 0x9E), + _INIT_DCS_CMD(0xC2, 0xB8), + _INIT_DCS_CMD(0xC3, 0xD1), + _INIT_DCS_CMD(0xC4, 0xDD), + _INIT_DCS_CMD(0xC5, 0xE9), + _INIT_DCS_CMD(0xC6, 0xF6), + _INIT_DCS_CMD(0xC7, 0xFA), + _INIT_DCS_CMD(0xC8, 0xFC), + _INIT_DCS_CMD(0xC9, 0x00), + _INIT_DCS_CMD(0xCA, 0x00), + _INIT_DCS_CMD(0xCB, 0x16), + _INIT_DCS_CMD(0xCC, 0xAF), + _INIT_DCS_CMD(0xCD, 0xFF), + _INIT_DCS_CMD(0xCE, 0xFF), + _INIT_DCS_CMD(0xB0, 0x0A), + _INIT_DCS_CMD(0xB1, 0x00), + _INIT_DCS_CMD(0xB2, 0x02), + _INIT_DCS_CMD(0xB3, 0x0F), + _INIT_DCS_CMD(0xB4, 0x25), + _INIT_DCS_CMD(0xB5, 0x39), + _INIT_DCS_CMD(0xB6, 0x4E), + _INIT_DCS_CMD(0xB7, 0x72), + _INIT_DCS_CMD(0xB8, 0x97), + _INIT_DCS_CMD(0xB9, 0xDC), + _INIT_DCS_CMD(0xBA, 0x22), + _INIT_DCS_CMD(0xBB, 0xA4), + _INIT_DCS_CMD(0xBC, 0x2B), + _INIT_DCS_CMD(0xBD, 0x2F), + _INIT_DCS_CMD(0xBE, 0xA9), + _INIT_DCS_CMD(0xBF, 0x25), + _INIT_DCS_CMD(0xC0, 0x61), + _INIT_DCS_CMD(0xC1, 0x97), + _INIT_DCS_CMD(0xC2, 0xB2), + _INIT_DCS_CMD(0xC3, 0xCD), + _INIT_DCS_CMD(0xC4, 0xD9), + _INIT_DCS_CMD(0xC5, 0xE7), + _INIT_DCS_CMD(0xC6, 0xF4), + _INIT_DCS_CMD(0xC7, 0xFA), + _INIT_DCS_CMD(0xC8, 0xFC), + _INIT_DCS_CMD(0xC9, 0x00), + _INIT_DCS_CMD(0xCA, 0x00), + _INIT_DCS_CMD(0xCB, 0x16), + _INIT_DCS_CMD(0xCC, 0xAF), + _INIT_DCS_CMD(0xCD, 0xFF), + _INIT_DCS_CMD(0xCE, 0xFF), + _INIT_DCS_CMD(0xB0, 0x0B), + _INIT_DCS_CMD(0xB1, 0x04), + _INIT_DCS_CMD(0xB2, 0x05), + _INIT_DCS_CMD(0xB3, 0x11), + _INIT_DCS_CMD(0xB4, 0x24), + _INIT_DCS_CMD(0xB5, 0x39), + _INIT_DCS_CMD(0xB6, 0x4F), + _INIT_DCS_CMD(0xB7, 0x72), + _INIT_DCS_CMD(0xB8, 0x98), + _INIT_DCS_CMD(0xB9, 0xDC), + _INIT_DCS_CMD(0xBA, 0x23), + _INIT_DCS_CMD(0xBB, 0xA6), + _INIT_DCS_CMD(0xBC, 0x2C), + _INIT_DCS_CMD(0xBD, 0x30), + _INIT_DCS_CMD(0xBE, 0xAA), + _INIT_DCS_CMD(0xBF, 0x26), + _INIT_DCS_CMD(0xC0, 0x62), + _INIT_DCS_CMD(0xC1, 0x9B), + _INIT_DCS_CMD(0xC2, 0xB5), + _INIT_DCS_CMD(0xC3, 0xCF), + _INIT_DCS_CMD(0xC4, 0xDB), + _INIT_DCS_CMD(0xC5, 0xE8), + _INIT_DCS_CMD(0xC6, 0xF5), + _INIT_DCS_CMD(0xC7, 0xFA), + _INIT_DCS_CMD(0xC8, 0xFC), + _INIT_DCS_CMD(0xC9, 0x00), + _INIT_DCS_CMD(0xCA, 0x00), + _INIT_DCS_CMD(0xCB, 0x16), + _INIT_DCS_CMD(0xCC, 0xAF), + _INIT_DCS_CMD(0xCD, 0xFF), + _INIT_DCS_CMD(0xCE, 0xFF), + _INIT_DCS_CMD(0xB0, 0x0C), + _INIT_DCS_CMD(0xB1, 0x04), + _INIT_DCS_CMD(0xB2, 0x02), + _INIT_DCS_CMD(0xB3, 0x16), + _INIT_DCS_CMD(0xB4, 0x24), + _INIT_DCS_CMD(0xB5, 0x3B), + _INIT_DCS_CMD(0xB6, 0x4F), + _INIT_DCS_CMD(0xB7, 0x73), + _INIT_DCS_CMD(0xB8, 0x99), + _INIT_DCS_CMD(0xB9, 0xE0), + _INIT_DCS_CMD(0xBA, 0x26), + _INIT_DCS_CMD(0xBB, 0xAD), + _INIT_DCS_CMD(0xBC, 0x36), + _INIT_DCS_CMD(0xBD, 0x3A), + _INIT_DCS_CMD(0xBE, 0xAE), + _INIT_DCS_CMD(0xBF, 0x2A), + _INIT_DCS_CMD(0xC0, 0x66), + _INIT_DCS_CMD(0xC1, 0x9E), + _INIT_DCS_CMD(0xC2, 0xB8), + _INIT_DCS_CMD(0xC3, 0xD1), + _INIT_DCS_CMD(0xC4, 0xDD), + _INIT_DCS_CMD(0xC5, 0xE9), + _INIT_DCS_CMD(0xC6, 0xF6), + _INIT_DCS_CMD(0xC7, 0xFA), + _INIT_DCS_CMD(0xC8, 0xFC), + _INIT_DCS_CMD(0xC9, 0x00), + _INIT_DCS_CMD(0xCA, 0x00), + _INIT_DCS_CMD(0xCB, 0x16), + _INIT_DCS_CMD(0xCC, 0xAF), + _INIT_DCS_CMD(0xCD, 0xFF), + _INIT_DCS_CMD(0xCE, 0xFF), + _INIT_DCS_CMD(0xB0, 0x00), + _INIT_DCS_CMD(0xB3, 0x08), + _INIT_DCS_CMD(0xB0, 0x04), + _INIT_DCS_CMD(0xB8, 0x68), + _INIT_DELAY_CMD(150), + {}, +}; + +static const struct panel_init_cmd auo_kd101n80_45na_init_cmd[] = { + _INIT_DELAY_CMD(24), + _INIT_DCS_CMD(0x11), + _INIT_DELAY_CMD(120), + _INIT_DCS_CMD(0x29), + _INIT_DELAY_CMD(120), + {}, +}; + +static const struct panel_init_cmd auo_b101uan08_3_init_cmd[] = { + _INIT_DELAY_CMD(24), + _INIT_DCS_CMD(0xB0, 0x01), + _INIT_DCS_CMD(0xC0, 0x48), + _INIT_DCS_CMD(0xC1, 0x48), + _INIT_DCS_CMD(0xC2, 0x47), + _INIT_DCS_CMD(0xC3, 0x47), + _INIT_DCS_CMD(0xC4, 0x46), + _INIT_DCS_CMD(0xC5, 0x46), + _INIT_DCS_CMD(0xC6, 0x45), + _INIT_DCS_CMD(0xC7, 0x45), + _INIT_DCS_CMD(0xC8, 0x64), + _INIT_DCS_CMD(0xC9, 0x64), + _INIT_DCS_CMD(0xCA, 0x4F), + _INIT_DCS_CMD(0xCB, 0x4F), + _INIT_DCS_CMD(0xCC, 0x40), + _INIT_DCS_CMD(0xCD, 0x40), + _INIT_DCS_CMD(0xCE, 0x66), + _INIT_DCS_CMD(0xCF, 0x66), + _INIT_DCS_CMD(0xD0, 0x4F), + _INIT_DCS_CMD(0xD1, 0x4F), + _INIT_DCS_CMD(0xD2, 0x41), + _INIT_DCS_CMD(0xD3, 0x41), + _INIT_DCS_CMD(0xD4, 0x48), + _INIT_DCS_CMD(0xD5, 0x48), + _INIT_DCS_CMD(0xD6, 0x47), + _INIT_DCS_CMD(0xD7, 0x47), + _INIT_DCS_CMD(0xD8, 0x46), + _INIT_DCS_CMD(0xD9, 0x46), + _INIT_DCS_CMD(0xDA, 0x45), + _INIT_DCS_CMD(0xDB, 0x45), + _INIT_DCS_CMD(0xDC, 0x64), + _INIT_DCS_CMD(0xDD, 0x64), + _INIT_DCS_CMD(0xDE, 0x4F), + _INIT_DCS_CMD(0xDF, 0x4F), + _INIT_DCS_CMD(0xE0, 0x40), + _INIT_DCS_CMD(0xE1, 0x40), + _INIT_DCS_CMD(0xE2, 0x66), + _INIT_DCS_CMD(0xE3, 0x66), + _INIT_DCS_CMD(0xE4, 0x4F), + _INIT_DCS_CMD(0xE5, 0x4F), + _INIT_DCS_CMD(0xE6, 0x41), + _INIT_DCS_CMD(0xE7, 0x41), + _INIT_DELAY_CMD(150), + {}, +}; + +static inline struct boe_panel *to_boe_panel(struct drm_panel *panel) +{ + return container_of(panel, struct boe_panel, base); +} + +static int boe_panel_init_dcs_cmd(struct boe_panel *boe) +{ + struct mipi_dsi_device *dsi = boe->dsi; + struct drm_panel *panel = &boe->base; + int i, err = 0; + + if (boe->desc->init_cmds) { + const struct panel_init_cmd *init_cmds = boe->desc->init_cmds; + + for (i = 0; init_cmds[i].len != 0; i++) { + const struct panel_init_cmd *cmd = &init_cmds[i]; + + switch (cmd->type) { + case DELAY_CMD: + msleep(cmd->data[0]); + err = 0; + break; + + case INIT_DCS_CMD: + err = mipi_dsi_dcs_write(dsi, cmd->data[0], + cmd->len <= 1 ? NULL : + &cmd->data[1], + cmd->len - 1); + break; + + default: + err = -EINVAL; + } + + if (err < 0) { + dev_err(panel->dev, + "failed to write command %u\n", i); + return err; + } + } + } + return 0; +} + +static int boe_panel_enter_sleep_mode(struct boe_panel *boe) +{ + struct mipi_dsi_device *dsi = boe->dsi; + int ret; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) + return ret; + + ret = mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) + return ret; + + return 0; +} + +static int boe_panel_unprepare(struct drm_panel *panel) +{ + struct boe_panel *boe = to_boe_panel(panel); + int ret; + + if (!boe->prepared) + return 0; + + ret = boe_panel_enter_sleep_mode(boe); + if (ret < 0) { + dev_err(panel->dev, "failed to set panel off: %d\n", ret); + return ret; + } + + msleep(150); + + if (boe->desc->discharge_on_disable) { + regulator_disable(boe->avee); + regulator_disable(boe->avdd); + usleep_range(5000, 7000); + gpiod_set_value(boe->enable_gpio, 0); + usleep_range(5000, 7000); + regulator_disable(boe->pp1800); + } else { + gpiod_set_value(boe->enable_gpio, 0); + usleep_range(500, 1000); + regulator_disable(boe->avee); + regulator_disable(boe->avdd); + usleep_range(5000, 7000); + regulator_disable(boe->pp1800); + } + + boe->prepared = false; + + return 0; +} + +static int boe_panel_prepare(struct drm_panel *panel) +{ + struct boe_panel *boe = to_boe_panel(panel); + int ret; + + if (boe->prepared) + return 0; + + gpiod_set_value(boe->enable_gpio, 0); + usleep_range(1000, 1500); + + ret = regulator_enable(boe->pp1800); + if (ret < 0) + return ret; + + usleep_range(3000, 5000); + + ret = regulator_enable(boe->avdd); + if (ret < 0) + goto poweroff1v8; + ret = regulator_enable(boe->avee); + if (ret < 0) + goto poweroffavdd; + + usleep_range(5000, 10000); + + gpiod_set_value(boe->enable_gpio, 1); + usleep_range(1000, 2000); + gpiod_set_value(boe->enable_gpio, 0); + usleep_range(1000, 2000); + gpiod_set_value(boe->enable_gpio, 1); + usleep_range(6000, 10000); + + ret = boe_panel_init_dcs_cmd(boe); + if (ret < 0) { + dev_err(panel->dev, "failed to init panel: %d\n", ret); + goto poweroff; + } + + boe->prepared = true; + + return 0; + +poweroff: + regulator_disable(boe->avee); +poweroffavdd: + regulator_disable(boe->avdd); +poweroff1v8: + usleep_range(5000, 7000); + regulator_disable(boe->pp1800); + gpiod_set_value(boe->enable_gpio, 0); + + return ret; +} + +static int boe_panel_enable(struct drm_panel *panel) +{ + msleep(130); + return 0; +} + +static const struct drm_display_mode boe_tv101wum_nl6_default_mode = { + .clock = 159425, + .hdisplay = 1200, + .hsync_start = 1200 + 100, + .hsync_end = 1200 + 100 + 40, + .htotal = 1200 + 100 + 40 + 24, + .vdisplay = 1920, + .vsync_start = 1920 + 10, + .vsync_end = 1920 + 10 + 14, + .vtotal = 1920 + 10 + 14 + 4, + .vrefresh = 60, +}; + +static const struct panel_desc boe_tv101wum_nl6_desc = { + .modes = &boe_tv101wum_nl6_default_mode, + .bpc = 8, + .size = { + .width_mm = 135, + .height_mm = 216, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds = boe_init_cmd, + .discharge_on_disable = false, +}; + +static const struct drm_display_mode auo_kd101n80_45na_default_mode = { + .clock = 157000, + .hdisplay = 1200, + .hsync_start = 1200 + 80, + .hsync_end = 1200 + 80 + 24, + .htotal = 1200 + 80 + 24 + 36, + .vdisplay = 1920, + .vsync_start = 1920 + 16, + .vsync_end = 1920 + 16 + 4, + .vtotal = 1920 + 16 + 4 + 16, + .vrefresh = 60, +}; + +static const struct panel_desc auo_kd101n80_45na_desc = { + .modes = &auo_kd101n80_45na_default_mode, + .bpc = 8, + .size = { + .width_mm = 135, + .height_mm = 216, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds = auo_kd101n80_45na_init_cmd, + .discharge_on_disable = true, +}; + +static const struct drm_display_mode boe_tv101wum_n53_default_mode = { + .clock = 159916, + .hdisplay = 1200, + .hsync_start = 1200 + 80, + .hsync_end = 1200 + 80 + 24, + .htotal = 1200 + 80 + 24 + 60, + .vdisplay = 1920, + .vsync_start = 1920 + 20, + .vsync_end = 1920 + 20 + 4, + .vtotal = 1920 + 20 + 4 + 10, + .vrefresh = 60, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc boe_tv101wum_n53_desc = { + .modes = &boe_tv101wum_n53_default_mode, + .bpc = 8, + .size = { + .width_mm = 135, + .height_mm = 216, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds = boe_init_cmd, +}; + +static const struct drm_display_mode auo_b101uan08_3_default_mode = { + .clock = 159667, + .hdisplay = 1200, + .hsync_start = 1200 + 60, + .hsync_end = 1200 + 60 + 4, + .htotal = 1200 + 60 + 4 + 80, + .vdisplay = 1920, + .vsync_start = 1920 + 34, + .vsync_end = 1920 + 34 + 2, + .vtotal = 1920 + 34 + 2 + 24, + .vrefresh = 60, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc auo_b101uan08_3_desc = { + .modes = &auo_b101uan08_3_default_mode, + .bpc = 8, + .size = { + .width_mm = 135, + .height_mm = 216, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds = auo_b101uan08_3_init_cmd, +}; + +static int boe_panel_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct boe_panel *boe = to_boe_panel(panel); + const struct drm_display_mode *m = boe->desc->modes; + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, m); + if (!mode) { + dev_err(panel->dev, "failed to add mode %ux%u@%u\n", + m->hdisplay, m->vdisplay, m->vrefresh); + return -ENOMEM; + } + + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + drm_mode_set_name(mode); + drm_mode_probed_add(connector, mode); + + connector->display_info.width_mm = boe->desc->size.width_mm; + connector->display_info.height_mm = boe->desc->size.height_mm; + connector->display_info.bpc = boe->desc->bpc; + + return 1; +} + +static const struct drm_panel_funcs boe_panel_funcs = { + .unprepare = boe_panel_unprepare, + .prepare = boe_panel_prepare, + .enable = boe_panel_enable, + .get_modes = boe_panel_get_modes, +}; + +static int boe_panel_add(struct boe_panel *boe) +{ + struct device *dev = &boe->dsi->dev; + int err; + + boe->avdd = devm_regulator_get(dev, "avdd"); + if (IS_ERR(boe->avdd)) + return PTR_ERR(boe->avdd); + + boe->avee = devm_regulator_get(dev, "avee"); + if (IS_ERR(boe->avee)) + return PTR_ERR(boe->avee); + + boe->pp1800 = devm_regulator_get(dev, "pp1800"); + if (IS_ERR(boe->pp1800)) + return PTR_ERR(boe->pp1800); + + boe->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); + if (IS_ERR(boe->enable_gpio)) { + dev_err(dev, "cannot get reset-gpios %ld\n", + PTR_ERR(boe->enable_gpio)); + return PTR_ERR(boe->enable_gpio); + } + + gpiod_set_value(boe->enable_gpio, 0); + + drm_panel_init(&boe->base, dev, &boe_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + + err = drm_panel_of_backlight(&boe->base); + if (err) + return err; + + boe->base.funcs = &boe_panel_funcs; + boe->base.dev = &boe->dsi->dev; + + return drm_panel_add(&boe->base); +} + +static int boe_panel_probe(struct mipi_dsi_device *dsi) +{ + struct boe_panel *boe; + int ret; + const struct panel_desc *desc; + + boe = devm_kzalloc(&dsi->dev, sizeof(*boe), GFP_KERNEL); + if (!boe) + return -ENOMEM; + + desc = of_device_get_match_data(&dsi->dev); + dsi->lanes = desc->lanes; + dsi->format = desc->format; + dsi->mode_flags = desc->mode_flags; + boe->desc = desc; + boe->dsi = dsi; + ret = boe_panel_add(boe); + if (ret < 0) + return ret; + + mipi_dsi_set_drvdata(dsi, boe); + + ret = mipi_dsi_attach(dsi); + if (ret) + drm_panel_remove(&boe->base); + + return ret; +} + +static void boe_panel_shutdown(struct mipi_dsi_device *dsi) +{ + struct boe_panel *boe = mipi_dsi_get_drvdata(dsi); + + drm_panel_disable(&boe->base); + drm_panel_unprepare(&boe->base); +} + +static int boe_panel_remove(struct mipi_dsi_device *dsi) +{ + struct boe_panel *boe = mipi_dsi_get_drvdata(dsi); + int ret; + + boe_panel_shutdown(dsi); + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret); + + if (boe->base.dev) + drm_panel_remove(&boe->base); + + return 0; +} + +static const struct of_device_id boe_of_match[] = { + { .compatible = "boe,tv101wum-nl6", + .data = &boe_tv101wum_nl6_desc + }, + { .compatible = "auo,kd101n80-45na", + .data = &auo_kd101n80_45na_desc + }, + { .compatible = "boe,tv101wum-n53", + .data = &boe_tv101wum_n53_desc + }, + { .compatible = "auo,b101uan08.3", + .data = &auo_b101uan08_3_desc + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, boe_of_match); + +static struct mipi_dsi_driver boe_panel_driver = { + .driver = { + .name = "panel-boe-tv101wum-nl6", + .of_match_table = boe_of_match, + }, + .probe = boe_panel_probe, + .remove = boe_panel_remove, + .shutdown = boe_panel_shutdown, +}; +module_mipi_dsi_driver(boe_panel_driver); + +MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>"); +MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/panel/panel-feixin-k101-im2ba02.c b/drivers/gpu/drm/panel/panel-feixin-k101-im2ba02.c new file mode 100644 index 000000000000..fddbfddf6566 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-feixin-k101-im2ba02.c @@ -0,0 +1,526 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2020 Icenowy Zheng <icenowy@aosc.io> + */ + +#include <linux/gpio/consumer.h> +#include <linux/delay.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/regulator/consumer.h> + +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_print.h> + +#define K101_IM2BA02_INIT_CMD_LEN 2 + +static const char * const regulator_names[] = { + "dvdd", + "avdd", + "cvdd" +}; + +struct k101_im2ba02 { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + + struct regulator_bulk_data supplies[ARRAY_SIZE(regulator_names)]; + struct gpio_desc *reset; +}; + +static inline struct k101_im2ba02 *panel_to_k101_im2ba02(struct drm_panel *panel) +{ + return container_of(panel, struct k101_im2ba02, panel); +} + +struct k101_im2ba02_init_cmd { + u8 data[K101_IM2BA02_INIT_CMD_LEN]; +}; + +static const struct k101_im2ba02_init_cmd k101_im2ba02_init_cmds[] = { + /* Switch to page 0 */ + { .data = { 0xE0, 0x00 } }, + + /* Seems to be some password */ + { .data = { 0xE1, 0x93} }, + { .data = { 0xE2, 0x65 } }, + { .data = { 0xE3, 0xF8 } }, + + /* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */ + { .data = { 0x80, 0x03 } }, + + /* Sequence control */ + { .data = { 0x70, 0x02 } }, + { .data = { 0x71, 0x23 } }, + { .data = { 0x72, 0x06 } }, + + /* Switch to page 1 */ + { .data = { 0xE0, 0x01 } }, + + /* Set VCOM */ + { .data = { 0x00, 0x00 } }, + { .data = { 0x01, 0x66 } }, + /* Set VCOM_Reverse */ + { .data = { 0x03, 0x00 } }, + { .data = { 0x04, 0x25 } }, + + /* Set Gamma Power, VG[MS][PN] */ + { .data = { 0x17, 0x00 } }, + { .data = { 0x18, 0x6D } }, + { .data = { 0x19, 0x00 } }, + { .data = { 0x1A, 0x00 } }, + { .data = { 0x1B, 0xBF } }, /* VGMN = -4.5V */ + { .data = { 0x1C, 0x00 } }, + + /* Set Gate Power */ + { .data = { 0x1F, 0x3E } }, /* VGH_R = 15V */ + { .data = { 0x20, 0x28 } }, /* VGL_R = -11V */ + { .data = { 0x21, 0x28 } }, /* VGL_R2 = -11V */ + { .data = { 0x22, 0x0E } }, /* PA[6:4] = 0, PA[0] = 0 */ + + /* Set Panel */ + { .data = { 0x37, 0x09 } }, /* SS = 1, BGR = 1 */ + + /* Set RGBCYC */ + { .data = { 0x38, 0x04 } }, /* JDT = 100 column inversion */ + { .data = { 0x39, 0x08 } }, /* RGB_N_EQ1 */ + { .data = { 0x3A, 0x12 } }, /* RGB_N_EQ2 */ + { .data = { 0x3C, 0x78 } }, /* set EQ3 for TE_H */ + { .data = { 0x3D, 0xFF } }, /* set CHGEN_ON */ + { .data = { 0x3E, 0xFF } }, /* set CHGEN_OFF */ + { .data = { 0x3F, 0x7F } }, /* set CHGEN_OFF2 */ + + /* Set TCON parameter */ + { .data = { 0x40, 0x06 } }, /* RSO = 800 points */ + { .data = { 0x41, 0xA0 } }, /* LN = 1280 lines */ + + /* Set power voltage */ + { .data = { 0x55, 0x0F } }, /* DCDCM */ + { .data = { 0x56, 0x01 } }, + { .data = { 0x57, 0x69 } }, + { .data = { 0x58, 0x0A } }, + { .data = { 0x59, 0x0A } }, + { .data = { 0x5A, 0x45 } }, + { .data = { 0x5B, 0x15 } }, + + /* Set gamma */ + { .data = { 0x5D, 0x7C } }, + { .data = { 0x5E, 0x65 } }, + { .data = { 0x5F, 0x55 } }, + { .data = { 0x60, 0x49 } }, + { .data = { 0x61, 0x44 } }, + { .data = { 0x62, 0x35 } }, + { .data = { 0x63, 0x3A } }, + { .data = { 0x64, 0x23 } }, + { .data = { 0x65, 0x3D } }, + { .data = { 0x66, 0x3C } }, + { .data = { 0x67, 0x3D } }, + { .data = { 0x68, 0x5D } }, + { .data = { 0x69, 0x4D } }, + { .data = { 0x6A, 0x56 } }, + { .data = { 0x6B, 0x48 } }, + { .data = { 0x6C, 0x45 } }, + { .data = { 0x6D, 0x38 } }, + { .data = { 0x6E, 0x25 } }, + { .data = { 0x6F, 0x00 } }, + { .data = { 0x70, 0x7C } }, + { .data = { 0x71, 0x65 } }, + { .data = { 0x72, 0x55 } }, + { .data = { 0x73, 0x49 } }, + { .data = { 0x74, 0x44 } }, + { .data = { 0x75, 0x35 } }, + { .data = { 0x76, 0x3A } }, + { .data = { 0x77, 0x23 } }, + { .data = { 0x78, 0x3D } }, + { .data = { 0x79, 0x3C } }, + { .data = { 0x7A, 0x3D } }, + { .data = { 0x7B, 0x5D } }, + { .data = { 0x7C, 0x4D } }, + { .data = { 0x7D, 0x56 } }, + { .data = { 0x7E, 0x48 } }, + { .data = { 0x7F, 0x45 } }, + { .data = { 0x80, 0x38 } }, + { .data = { 0x81, 0x25 } }, + { .data = { 0x82, 0x00 } }, + + /* Switch to page 2, for GIP */ + { .data = { 0xE0, 0x02 } }, + + { .data = { 0x00, 0x1E } }, + { .data = { 0x01, 0x1E } }, + { .data = { 0x02, 0x41 } }, + { .data = { 0x03, 0x41 } }, + { .data = { 0x04, 0x43 } }, + { .data = { 0x05, 0x43 } }, + { .data = { 0x06, 0x1F } }, + { .data = { 0x07, 0x1F } }, + { .data = { 0x08, 0x1F } }, + { .data = { 0x09, 0x1F } }, + { .data = { 0x0A, 0x1E } }, + { .data = { 0x0B, 0x1E } }, + { .data = { 0x0C, 0x1F } }, + { .data = { 0x0D, 0x47 } }, + { .data = { 0x0E, 0x47 } }, + { .data = { 0x0F, 0x45 } }, + { .data = { 0x10, 0x45 } }, + { .data = { 0x11, 0x4B } }, + { .data = { 0x12, 0x4B } }, + { .data = { 0x13, 0x49 } }, + { .data = { 0x14, 0x49 } }, + { .data = { 0x15, 0x1F } }, + + { .data = { 0x16, 0x1E } }, + { .data = { 0x17, 0x1E } }, + { .data = { 0x18, 0x40 } }, + { .data = { 0x19, 0x40 } }, + { .data = { 0x1A, 0x42 } }, + { .data = { 0x1B, 0x42 } }, + { .data = { 0x1C, 0x1F } }, + { .data = { 0x1D, 0x1F } }, + { .data = { 0x1E, 0x1F } }, + { .data = { 0x1F, 0x1f } }, + { .data = { 0x20, 0x1E } }, + { .data = { 0x21, 0x1E } }, + { .data = { 0x22, 0x1f } }, + { .data = { 0x23, 0x46 } }, + { .data = { 0x24, 0x46 } }, + { .data = { 0x25, 0x44 } }, + { .data = { 0x26, 0x44 } }, + { .data = { 0x27, 0x4A } }, + { .data = { 0x28, 0x4A } }, + { .data = { 0x29, 0x48 } }, + { .data = { 0x2A, 0x48 } }, + { .data = { 0x2B, 0x1f } }, + + { .data = { 0x2C, 0x1F } }, + { .data = { 0x2D, 0x1F } }, + { .data = { 0x2E, 0x42 } }, + { .data = { 0x2F, 0x42 } }, + { .data = { 0x30, 0x40 } }, + { .data = { 0x31, 0x40 } }, + { .data = { 0x32, 0x1E } }, + { .data = { 0x33, 0x1E } }, + { .data = { 0x34, 0x1F } }, + { .data = { 0x35, 0x1F } }, + { .data = { 0x36, 0x1E } }, + { .data = { 0x37, 0x1E } }, + { .data = { 0x38, 0x1F } }, + { .data = { 0x39, 0x48 } }, + { .data = { 0x3A, 0x48 } }, + { .data = { 0x3B, 0x4A } }, + { .data = { 0x3C, 0x4A } }, + { .data = { 0x3D, 0x44 } }, + { .data = { 0x3E, 0x44 } }, + { .data = { 0x3F, 0x46 } }, + { .data = { 0x40, 0x46 } }, + { .data = { 0x41, 0x1F } }, + + { .data = { 0x42, 0x1F } }, + { .data = { 0x43, 0x1F } }, + { .data = { 0x44, 0x43 } }, + { .data = { 0x45, 0x43 } }, + { .data = { 0x46, 0x41 } }, + { .data = { 0x47, 0x41 } }, + { .data = { 0x48, 0x1E } }, + { .data = { 0x49, 0x1E } }, + { .data = { 0x4A, 0x1E } }, + { .data = { 0x4B, 0x1F } }, + { .data = { 0x4C, 0x1E } }, + { .data = { 0x4D, 0x1E } }, + { .data = { 0x4E, 0x1F } }, + { .data = { 0x4F, 0x49 } }, + { .data = { 0x50, 0x49 } }, + { .data = { 0x51, 0x4B } }, + { .data = { 0x52, 0x4B } }, + { .data = { 0x53, 0x45 } }, + { .data = { 0x54, 0x45 } }, + { .data = { 0x55, 0x47 } }, + { .data = { 0x56, 0x47 } }, + { .data = { 0x57, 0x1F } }, + + { .data = { 0x58, 0x10 } }, + { .data = { 0x59, 0x00 } }, + { .data = { 0x5A, 0x00 } }, + { .data = { 0x5B, 0x30 } }, + { .data = { 0x5C, 0x02 } }, + { .data = { 0x5D, 0x40 } }, + { .data = { 0x5E, 0x01 } }, + { .data = { 0x5F, 0x02 } }, + { .data = { 0x60, 0x30 } }, + { .data = { 0x61, 0x01 } }, + { .data = { 0x62, 0x02 } }, + { .data = { 0x63, 0x6A } }, + { .data = { 0x64, 0x6A } }, + { .data = { 0x65, 0x05 } }, + { .data = { 0x66, 0x12 } }, + { .data = { 0x67, 0x74 } }, + { .data = { 0x68, 0x04 } }, + { .data = { 0x69, 0x6A } }, + { .data = { 0x6A, 0x6A } }, + { .data = { 0x6B, 0x08 } }, + + { .data = { 0x6C, 0x00 } }, + { .data = { 0x6D, 0x04 } }, + { .data = { 0x6E, 0x04 } }, + { .data = { 0x6F, 0x88 } }, + { .data = { 0x70, 0x00 } }, + { .data = { 0x71, 0x00 } }, + { .data = { 0x72, 0x06 } }, + { .data = { 0x73, 0x7B } }, + { .data = { 0x74, 0x00 } }, + { .data = { 0x75, 0x07 } }, + { .data = { 0x76, 0x00 } }, + { .data = { 0x77, 0x5D } }, + { .data = { 0x78, 0x17 } }, + { .data = { 0x79, 0x1F } }, + { .data = { 0x7A, 0x00 } }, + { .data = { 0x7B, 0x00 } }, + { .data = { 0x7C, 0x00 } }, + { .data = { 0x7D, 0x03 } }, + { .data = { 0x7E, 0x7B } }, + + { .data = { 0xE0, 0x04 } }, + { .data = { 0x2B, 0x2B } }, + { .data = { 0x2E, 0x44 } }, + + { .data = { 0xE0, 0x01 } }, + { .data = { 0x0E, 0x01 } }, + + { .data = { 0xE0, 0x03 } }, + { .data = { 0x98, 0x2F } }, + + { .data = { 0xE0, 0x00 } }, + { .data = { 0xE6, 0x02 } }, + { .data = { 0xE7, 0x02 } }, + + { .data = { 0x11, 0x00 } }, +}; + +static const struct k101_im2ba02_init_cmd timed_cmds[] = { + { .data = { 0x29, 0x00 } }, + { .data = { 0x35, 0x00 } }, +}; + +static int k101_im2ba02_prepare(struct drm_panel *panel) +{ + struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); + struct mipi_dsi_device *dsi = ctx->dsi; + unsigned int i; + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret) + return ret; + + msleep(30); + + gpiod_set_value(ctx->reset, 1); + msleep(50); + + gpiod_set_value(ctx->reset, 0); + msleep(50); + + gpiod_set_value(ctx->reset, 1); + msleep(200); + + for (i = 0; i < ARRAY_SIZE(k101_im2ba02_init_cmds); i++) { + const struct k101_im2ba02_init_cmd *cmd = &k101_im2ba02_init_cmds[i]; + + ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN); + if (ret < 0) + goto powerdown; + } + + return 0; + +powerdown: + gpiod_set_value(ctx->reset, 0); + msleep(50); + + return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); +} + +static int k101_im2ba02_enable(struct drm_panel *panel) +{ + struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); + const struct k101_im2ba02_init_cmd *cmd = &timed_cmds[1]; + int ret; + + msleep(150); + + ret = mipi_dsi_dcs_set_display_on(ctx->dsi); + if (ret < 0) + return ret; + + msleep(50); + + return mipi_dsi_dcs_write_buffer(ctx->dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN); +} + +static int k101_im2ba02_disable(struct drm_panel *panel) +{ + struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); + + return mipi_dsi_dcs_set_display_off(ctx->dsi); +} + +static int k101_im2ba02_unprepare(struct drm_panel *panel) +{ + struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); + int ret; + + ret = mipi_dsi_dcs_set_display_off(ctx->dsi); + if (ret < 0) + DRM_DEV_ERROR(panel->dev, "failed to set display off: %d\n", + ret); + + ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi); + if (ret < 0) + DRM_DEV_ERROR(panel->dev, "failed to enter sleep mode: %d\n", + ret); + + msleep(200); + + gpiod_set_value(ctx->reset, 0); + msleep(20); + + return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); +} + +static const struct drm_display_mode k101_im2ba02_default_mode = { + .clock = 70000, + .vrefresh = 60, + + .hdisplay = 800, + .hsync_start = 800 + 20, + .hsync_end = 800 + 20 + 20, + .htotal = 800 + 20 + 20 + 20, + + .vdisplay = 1280, + .vsync_start = 1280 + 16, + .vsync_end = 1280 + 16 + 4, + .vtotal = 1280 + 16 + 4 + 4, + + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + .width_mm = 136, + .height_mm = 217, +}; + +static int k101_im2ba02_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel); + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, &k101_im2ba02_default_mode); + if (!mode) { + DRM_DEV_ERROR(&ctx->dsi->dev, "failed to add mode %ux%ux@%u\n", + k101_im2ba02_default_mode.hdisplay, + k101_im2ba02_default_mode.vdisplay, + k101_im2ba02_default_mode.vrefresh); + return -ENOMEM; + } + + drm_mode_set_name(mode); + + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + drm_mode_probed_add(connector, mode); + + return 1; +} + +static const struct drm_panel_funcs k101_im2ba02_funcs = { + .disable = k101_im2ba02_disable, + .unprepare = k101_im2ba02_unprepare, + .prepare = k101_im2ba02_prepare, + .enable = k101_im2ba02_enable, + .get_modes = k101_im2ba02_get_modes, +}; + +static int k101_im2ba02_dsi_probe(struct mipi_dsi_device *dsi) +{ + struct k101_im2ba02 *ctx; + unsigned int i; + int ret; + + ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + mipi_dsi_set_drvdata(dsi, ctx); + ctx->dsi = dsi; + + for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++) + ctx->supplies[i].supply = regulator_names[i]; + + ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(ctx->supplies), + ctx->supplies); + if (ret < 0) { + DRM_DEV_ERROR(&dsi->dev, "Couldn't get regulators\n"); + return ret; + } + + ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset)) { + DRM_DEV_ERROR(&dsi->dev, "Couldn't get our reset GPIO\n"); + return PTR_ERR(ctx->reset); + } + + drm_panel_init(&ctx->panel, &dsi->dev, &k101_im2ba02_funcs, + DRM_MODE_CONNECTOR_DSI); + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return ret; + + ret = drm_panel_add(&ctx->panel); + if (ret < 0) + return ret; + + dsi->mode_flags = MIPI_DSI_MODE_VIDEO; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->lanes = 4; + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static int k101_im2ba02_dsi_remove(struct mipi_dsi_device *dsi) +{ + struct k101_im2ba02 *ctx = mipi_dsi_get_drvdata(dsi); + + mipi_dsi_detach(dsi); + drm_panel_remove(&ctx->panel); + + return 0; +} + +static const struct of_device_id k101_im2ba02_of_match[] = { + { .compatible = "feixin,k101-im2ba02", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, k101_im2ba02_of_match); + +static struct mipi_dsi_driver k101_im2ba02_driver = { + .probe = k101_im2ba02_dsi_probe, + .remove = k101_im2ba02_dsi_remove, + .driver = { + .name = "feixin-k101-im2ba02", + .of_match_table = k101_im2ba02_of_match, + }, +}; +module_mipi_dsi_driver(k101_im2ba02_driver); + +MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>"); +MODULE_DESCRIPTION("Feixin K101 IM2BA02 MIPI-DSI LCD panel"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c b/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c new file mode 100644 index 000000000000..9d843fcc3a22 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-samsung-s6e88a0-ams452ef01.c @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2019, Michael Srba + +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regulator/consumer.h> + +#include <video/mipi_display.h> + +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> + +struct s6e88a0_ams452ef01 { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct regulator_bulk_data supplies[2]; + struct gpio_desc *reset_gpio; + + bool prepared; +}; + +static inline struct +s6e88a0_ams452ef01 *to_s6e88a0_ams452ef01(struct drm_panel *panel) +{ + return container_of(panel, struct s6e88a0_ams452ef01, panel); +} + +#define dsi_dcs_write_seq(dsi, seq...) do { \ + static const u8 d[] = { seq }; \ + int ret; \ + ret = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \ + if (ret < 0) \ + return ret; \ + } while (0) + +static void s6e88a0_ams452ef01_reset(struct s6e88a0_ams452ef01 *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(5000, 6000); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(1000, 2000); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(10000, 11000); +} + +static int s6e88a0_ams452ef01_on(struct s6e88a0_ams452ef01 *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct device *dev = &dsi->dev; + int ret; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands + dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to exit sleep mode: %d\n", ret); + return ret; + } + msleep(120); + + // set default brightness/gama + dsi_dcs_write_seq(dsi, 0xca, + 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, // V255 RR,GG,BB + 0x80, 0x80, 0x80, // V203 R,G,B + 0x80, 0x80, 0x80, // V151 R,G,B + 0x80, 0x80, 0x80, // V87 R,G,B + 0x80, 0x80, 0x80, // V51 R,G,B + 0x80, 0x80, 0x80, // V35 R,G,B + 0x80, 0x80, 0x80, // V23 R,G,B + 0x80, 0x80, 0x80, // V11 R,G,B + 0x6b, 0x68, 0x71, // V3 R,G,B + 0x00, 0x00, 0x00); // V1 R,G,B + // set default Amoled Off Ratio + dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); + dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage + dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update + dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display on: %d\n", ret); + return ret; + } + + return 0; +} + +static int s6e88a0_ams452ef01_off(struct s6e88a0_ams452ef01 *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct device *dev = &dsi->dev; + int ret; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) { + dev_err(dev, "Failed to set display off: %d\n", ret); + return ret; + } + msleep(35); + + ret = mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) { + dev_err(dev, "Failed to enter sleep mode: %d\n", ret); + return ret; + } + msleep(120); + + return 0; +} + +static int s6e88a0_ams452ef01_prepare(struct drm_panel *panel) +{ + struct s6e88a0_ams452ef01 *ctx = to_s6e88a0_ams452ef01(panel); + struct device *dev = &ctx->dsi->dev; + int ret; + + if (ctx->prepared) + return 0; + + ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + if (ret < 0) { + dev_err(dev, "Failed to enable regulators: %d\n", ret); + return ret; + } + + s6e88a0_ams452ef01_reset(ctx); + + ret = s6e88a0_ams452ef01_on(ctx); + if (ret < 0) { + dev_err(dev, "Failed to initialize panel: %d\n", ret); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), + ctx->supplies); + return ret; + } + + ctx->prepared = true; + return 0; +} + +static int s6e88a0_ams452ef01_unprepare(struct drm_panel *panel) +{ + struct s6e88a0_ams452ef01 *ctx = to_s6e88a0_ams452ef01(panel); + struct device *dev = &ctx->dsi->dev; + int ret; + + if (!ctx->prepared) + return 0; + + ret = s6e88a0_ams452ef01_off(ctx); + if (ret < 0) + dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + + ctx->prepared = false; + return 0; +} + +static const struct drm_display_mode s6e88a0_ams452ef01_mode = { + .clock = (540 + 88 + 4 + 20) * (960 + 14 + 2 + 8) * 60 / 1000, + .hdisplay = 540, + .hsync_start = 540 + 88, + .hsync_end = 540 + 88 + 4, + .htotal = 540 + 88 + 4 + 20, + .vdisplay = 960, + .vsync_start = 960 + 14, + .vsync_end = 960 + 14 + 2, + .vtotal = 960 + 14 + 2 + 8, + .vrefresh = 60, + .width_mm = 56, + .height_mm = 100, +}; + +static int s6e88a0_ams452ef01_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, &s6e88a0_ams452ef01_mode); + if (!mode) + return -ENOMEM; + + drm_mode_set_name(mode); + + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + drm_mode_probed_add(connector, mode); + + return 1; +} + +static const struct drm_panel_funcs s6e88a0_ams452ef01_panel_funcs = { + .unprepare = s6e88a0_ams452ef01_unprepare, + .prepare = s6e88a0_ams452ef01_prepare, + .get_modes = s6e88a0_ams452ef01_get_modes, +}; + +static int s6e88a0_ams452ef01_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct s6e88a0_ams452ef01 *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->supplies[0].supply = "vdd3"; + ctx->supplies[1].supply = "vci"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies), + ctx->supplies); + if (ret < 0) { + dev_err(dev, "Failed to get regulators: %d\n", ret); + return ret; + } + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset_gpio)) { + ret = PTR_ERR(ctx->reset_gpio); + dev_err(dev, "Failed to get reset-gpios: %d\n", ret); + return ret; + } + + ctx->dsi = dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes = 2; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST; + + drm_panel_init(&ctx->panel, dev, &s6e88a0_ams452ef01_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + + ret = drm_panel_add(&ctx->panel); + if (ret < 0) { + dev_err(dev, "Failed to add panel: %d\n", ret); + return ret; + } + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err(dev, "Failed to attach to DSI host: %d\n", ret); + return ret; + } + + return 0; +} + +static int s6e88a0_ams452ef01_remove(struct mipi_dsi_device *dsi) +{ + struct s6e88a0_ams452ef01 *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); + + drm_panel_remove(&ctx->panel); + + return 0; +} + +static const struct of_device_id s6e88a0_ams452ef01_of_match[] = { + { .compatible = "samsung,s6e88a0-ams452ef01" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, s6e88a0_ams452ef01_of_match); + +static struct mipi_dsi_driver s6e88a0_ams452ef01_driver = { + .probe = s6e88a0_ams452ef01_probe, + .remove = s6e88a0_ams452ef01_remove, + .driver = { + .name = "panel-s6e88a0-ams452ef01", + .of_match_table = s6e88a0_ams452ef01_of_match, + }, +}; +module_mipi_dsi_driver(s6e88a0_ams452ef01_driver); + +MODULE_AUTHOR("Michael Srba <Michael.Srba@seznam.cz>"); +MODULE_DESCRIPTION("MIPI-DSI based Panel Driver for AMS452EF01 AMOLED LCD with a S6E88A0 controller"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index e14c14ac62b5..d901ccb5cf9b 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1301,6 +1301,37 @@ static const struct panel_desc edt_et035012dm6 = { .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, }; +static const struct drm_display_mode edt_etm043080dh6gp_mode = { + .clock = 10870, + .hdisplay = 480, + .hsync_start = 480 + 8, + .hsync_end = 480 + 8 + 4, + .htotal = 480 + 8 + 4 + 41, + + /* + * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while + * fb_align + */ + + .vdisplay = 288, + .vsync_start = 288 + 2, + .vsync_end = 288 + 2 + 4, + .vtotal = 288 + 2 + 4 + 10, + .vrefresh = 60, +}; + +static const struct panel_desc edt_etm043080dh6gp = { + .modes = &edt_etm043080dh6gp_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 100, + .height = 65, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .connector_type = DRM_MODE_CONNECTOR_DPI, +}; + static const struct drm_display_mode edt_etm0430g0dh6_mode = { .clock = 9000, .hdisplay = 480, @@ -1440,6 +1471,33 @@ static const struct panel_desc foxlink_fl500wvr00_a0t = { .bus_format = MEDIA_BUS_FMT_RGB888_1X24, }; +static const struct drm_display_mode frida_frd350h54004_mode = { + .clock = 6000, + .hdisplay = 320, + .hsync_start = 320 + 44, + .hsync_end = 320 + 44 + 16, + .htotal = 320 + 44 + 16 + 20, + .vdisplay = 240, + .vsync_start = 240 + 2, + .vsync_end = 240 + 2 + 6, + .vtotal = 240 + 2 + 6 + 2, + .vrefresh = 60, + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, +}; + +static const struct panel_desc frida_frd350h54004 = { + .modes = &frida_frd350h54004_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 77, + .height = 64, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, + .connector_type = DRM_MODE_CONNECTOR_DPI, +}; + static const struct drm_display_mode friendlyarm_hd702e_mode = { .clock = 67185, .hdisplay = 800, @@ -2080,6 +2138,64 @@ static const struct panel_desc lg_lp129qe = { }, }; +static const struct display_timing logictechno_lt161010_2nh_timing = { + .pixelclock = { 26400000, 33300000, 46800000 }, + .hactive = { 800, 800, 800 }, + .hfront_porch = { 16, 210, 354 }, + .hback_porch = { 46, 46, 46 }, + .hsync_len = { 1, 20, 40 }, + .vactive = { 480, 480, 480 }, + .vfront_porch = { 7, 22, 147 }, + .vback_porch = { 23, 23, 23 }, + .vsync_len = { 1, 10, 20 }, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | + DISPLAY_FLAGS_SYNC_POSEDGE, +}; + +static const struct panel_desc logictechno_lt161010_2nh = { + .timings = &logictechno_lt161010_2nh_timing, + .num_timings = 1, + .size = { + .width = 154, + .height = 86, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | + DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, + .connector_type = DRM_MODE_CONNECTOR_DPI, +}; + +static const struct display_timing logictechno_lt170410_2whc_timing = { + .pixelclock = { 68900000, 71100000, 73400000 }, + .hactive = { 1280, 1280, 1280 }, + .hfront_porch = { 23, 60, 71 }, + .hback_porch = { 23, 60, 71 }, + .hsync_len = { 15, 40, 47 }, + .vactive = { 800, 800, 800 }, + .vfront_porch = { 5, 7, 10 }, + .vback_porch = { 5, 7, 10 }, + .vsync_len = { 6, 9, 12 }, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | + DISPLAY_FLAGS_SYNC_POSEDGE, +}; + +static const struct panel_desc logictechno_lt170410_2whc = { + .timings = &logictechno_lt170410_2whc_timing, + .num_timings = 1, + .size = { + .width = 217, + .height = 136, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | + DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, + .connector_type = DRM_MODE_CONNECTOR_LVDS, +}; + static const struct drm_display_mode mitsubishi_aa070mc01_mode = { .clock = 30400, .hdisplay = 800, @@ -3023,7 +3139,7 @@ static const struct panel_desc toshiba_lt089ac29000 = { .width = 194, .height = 116, }, - .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, .connector_type = DRM_MODE_CONNECTOR_LVDS, }; @@ -3286,6 +3402,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "edt,et035012dm6", .data = &edt_et035012dm6, }, { + .compatible = "edt,etm043080dh6gp", + .data = &edt_etm043080dh6gp, + }, { .compatible = "edt,etm0430g0dh6", .data = &edt_etm0430g0dh6, }, { @@ -3310,6 +3429,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "foxlink,fl500wvr00-a0t", .data = &foxlink_fl500wvr00_a0t, }, { + .compatible = "frida,frd350h54004", + .data = &frida_frd350h54004, + }, { .compatible = "friendlyarm,hd702e", .data = &friendlyarm_hd702e, }, { @@ -3388,6 +3510,15 @@ static const struct of_device_id platform_of_match[] = { .compatible = "logicpd,type28", .data = &logicpd_type_28, }, { + .compatible = "logictechno,lt161010-2nhc", + .data = &logictechno_lt161010_2nh, + }, { + .compatible = "logictechno,lt161010-2nhr", + .data = &logictechno_lt161010_2nh, + }, { + .compatible = "logictechno,lt170410-2whc", + .data = &logictechno_lt170410_2whc, + }, { .compatible = "mitsubishi,aa070mc01-ca1", .data = &mitsubishi_aa070mc01, }, { diff --git a/drivers/gpu/drm/panel/panel-tpo-td028ttec1.c b/drivers/gpu/drm/panel/panel-tpo-td028ttec1.c index cf29405a2dbe..aeca15dfeb3c 100644 --- a/drivers/gpu/drm/panel/panel-tpo-td028ttec1.c +++ b/drivers/gpu/drm/panel/panel-tpo-td028ttec1.c @@ -86,7 +86,12 @@ struct td028ttec1_panel { #define to_td028ttec1_device(p) container_of(p, struct td028ttec1_panel, panel) -static int jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err) +/* + * noinline_for_stack so we don't get multiple copies of tx_buf + * on the stack in case of gcc-plugin-structleak + */ +static int noinline_for_stack +jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err) { struct spi_device *spi = lcd->spi; u16 tx_buf = JBT_COMMAND | reg; @@ -105,8 +110,9 @@ static int jbt_ret_write_0(struct td028ttec1_panel *lcd, u8 reg, int *err) return ret; } -static int jbt_reg_write_1(struct td028ttec1_panel *lcd, - u8 reg, u8 data, int *err) +static int noinline_for_stack +jbt_reg_write_1(struct td028ttec1_panel *lcd, + u8 reg, u8 data, int *err) { struct spi_device *spi = lcd->spi; u16 tx_buf[2]; @@ -128,8 +134,9 @@ static int jbt_reg_write_1(struct td028ttec1_panel *lcd, return ret; } -static int jbt_reg_write_2(struct td028ttec1_panel *lcd, - u8 reg, u16 data, int *err) +static int noinline_for_stack +jbt_reg_write_2(struct td028ttec1_panel *lcd, + u8 reg, u16 data, int *err) { struct spi_device *spi = lcd->spi; u16 tx_buf[3]; diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c index 48e3c4165247..b7a618db3ee2 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -78,8 +78,10 @@ static int panfrost_ioctl_get_param(struct drm_device *ddev, void *data, struct static int panfrost_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file) { + struct panfrost_file_priv *priv = file->driver_priv; struct panfrost_gem_object *bo; struct drm_panfrost_create_bo *args = data; + struct panfrost_gem_mapping *mapping; if (!args->size || args->pad || (args->flags & ~(PANFROST_BO_NOEXEC | PANFROST_BO_HEAP))) @@ -95,7 +97,14 @@ static int panfrost_ioctl_create_bo(struct drm_device *dev, void *data, if (IS_ERR(bo)) return PTR_ERR(bo); - args->offset = bo->node.start << PAGE_SHIFT; + mapping = panfrost_gem_mapping_get(bo, priv); + if (!mapping) { + drm_gem_object_put_unlocked(&bo->base.base); + return -EINVAL; + } + + args->offset = mapping->mmnode.start << PAGE_SHIFT; + panfrost_gem_mapping_put(mapping); return 0; } @@ -119,6 +128,11 @@ panfrost_lookup_bos(struct drm_device *dev, struct drm_panfrost_submit *args, struct panfrost_job *job) { + struct panfrost_file_priv *priv = file_priv->driver_priv; + struct panfrost_gem_object *bo; + unsigned int i; + int ret; + job->bo_count = args->bo_handle_count; if (!job->bo_count) @@ -130,9 +144,33 @@ panfrost_lookup_bos(struct drm_device *dev, if (!job->implicit_fences) return -ENOMEM; - return drm_gem_objects_lookup(file_priv, - (void __user *)(uintptr_t)args->bo_handles, - job->bo_count, &job->bos); + ret = drm_gem_objects_lookup(file_priv, + (void __user *)(uintptr_t)args->bo_handles, + job->bo_count, &job->bos); + if (ret) + return ret; + + job->mappings = kvmalloc_array(job->bo_count, + sizeof(struct panfrost_gem_mapping *), + GFP_KERNEL | __GFP_ZERO); + if (!job->mappings) + return -ENOMEM; + + for (i = 0; i < job->bo_count; i++) { + struct panfrost_gem_mapping *mapping; + + bo = to_panfrost_bo(job->bos[i]); + mapping = panfrost_gem_mapping_get(bo, priv); + if (!mapping) { + ret = -EINVAL; + break; + } + + atomic_inc(&bo->gpu_usecount); + job->mappings[i] = mapping; + } + + return ret; } /** @@ -320,7 +358,9 @@ out: static int panfrost_ioctl_get_bo_offset(struct drm_device *dev, void *data, struct drm_file *file_priv) { + struct panfrost_file_priv *priv = file_priv->driver_priv; struct drm_panfrost_get_bo_offset *args = data; + struct panfrost_gem_mapping *mapping; struct drm_gem_object *gem_obj; struct panfrost_gem_object *bo; @@ -331,18 +371,26 @@ static int panfrost_ioctl_get_bo_offset(struct drm_device *dev, void *data, } bo = to_panfrost_bo(gem_obj); - args->offset = bo->node.start << PAGE_SHIFT; - + mapping = panfrost_gem_mapping_get(bo, priv); drm_gem_object_put_unlocked(gem_obj); + + if (!mapping) + return -EINVAL; + + args->offset = mapping->mmnode.start << PAGE_SHIFT; + panfrost_gem_mapping_put(mapping); return 0; } static int panfrost_ioctl_madvise(struct drm_device *dev, void *data, struct drm_file *file_priv) { + struct panfrost_file_priv *priv = file_priv->driver_priv; struct drm_panfrost_madvise *args = data; struct panfrost_device *pfdev = dev->dev_private; struct drm_gem_object *gem_obj; + struct panfrost_gem_object *bo; + int ret = 0; gem_obj = drm_gem_object_lookup(file_priv, args->handle); if (!gem_obj) { @@ -350,22 +398,48 @@ static int panfrost_ioctl_madvise(struct drm_device *dev, void *data, return -ENOENT; } + bo = to_panfrost_bo(gem_obj); + mutex_lock(&pfdev->shrinker_lock); + mutex_lock(&bo->mappings.lock); + if (args->madv == PANFROST_MADV_DONTNEED) { + struct panfrost_gem_mapping *first; + + first = list_first_entry(&bo->mappings.list, + struct panfrost_gem_mapping, + node); + + /* + * If we want to mark the BO purgeable, there must be only one + * user: the caller FD. + * We could do something smarter and mark the BO purgeable only + * when all its users have marked it purgeable, but globally + * visible/shared BOs are likely to never be marked purgeable + * anyway, so let's not bother. + */ + if (!list_is_singular(&bo->mappings.list) || + WARN_ON_ONCE(first->mmu != &priv->mmu)) { + ret = -EINVAL; + goto out_unlock_mappings; + } + } + args->retained = drm_gem_shmem_madvise(gem_obj, args->madv); if (args->retained) { - struct panfrost_gem_object *bo = to_panfrost_bo(gem_obj); - if (args->madv == PANFROST_MADV_DONTNEED) list_add_tail(&bo->base.madv_list, &pfdev->shrinker_list); else if (args->madv == PANFROST_MADV_WILLNEED) list_del_init(&bo->base.madv_list); } + +out_unlock_mappings: + mutex_unlock(&bo->mappings.lock); mutex_unlock(&pfdev->shrinker_lock); drm_gem_object_put_unlocked(gem_obj); - return 0; + return ret; } int panfrost_unstable_ioctl_check(void) diff --git a/drivers/gpu/drm/panfrost/panfrost_gem.c b/drivers/gpu/drm/panfrost/panfrost_gem.c index fd766b1395fb..17b654e1eb94 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gem.c +++ b/drivers/gpu/drm/panfrost/panfrost_gem.c @@ -29,6 +29,12 @@ static void panfrost_gem_free_object(struct drm_gem_object *obj) list_del_init(&bo->base.madv_list); mutex_unlock(&pfdev->shrinker_lock); + /* + * If we still have mappings attached to the BO, there's a problem in + * our refcounting. + */ + WARN_ON_ONCE(!list_empty(&bo->mappings.list)); + if (bo->sgts) { int i; int n_sgt = bo->base.base.size / SZ_2M; @@ -46,6 +52,69 @@ static void panfrost_gem_free_object(struct drm_gem_object *obj) drm_gem_shmem_free_object(obj); } +struct panfrost_gem_mapping * +panfrost_gem_mapping_get(struct panfrost_gem_object *bo, + struct panfrost_file_priv *priv) +{ + struct panfrost_gem_mapping *iter, *mapping = NULL; + + mutex_lock(&bo->mappings.lock); + list_for_each_entry(iter, &bo->mappings.list, node) { + if (iter->mmu == &priv->mmu) { + kref_get(&iter->refcount); + mapping = iter; + break; + } + } + mutex_unlock(&bo->mappings.lock); + + return mapping; +} + +static void +panfrost_gem_teardown_mapping(struct panfrost_gem_mapping *mapping) +{ + struct panfrost_file_priv *priv; + + if (mapping->active) + panfrost_mmu_unmap(mapping); + + priv = container_of(mapping->mmu, struct panfrost_file_priv, mmu); + spin_lock(&priv->mm_lock); + if (drm_mm_node_allocated(&mapping->mmnode)) + drm_mm_remove_node(&mapping->mmnode); + spin_unlock(&priv->mm_lock); +} + +static void panfrost_gem_mapping_release(struct kref *kref) +{ + struct panfrost_gem_mapping *mapping; + + mapping = container_of(kref, struct panfrost_gem_mapping, refcount); + + panfrost_gem_teardown_mapping(mapping); + drm_gem_object_put_unlocked(&mapping->obj->base.base); + kfree(mapping); +} + +void panfrost_gem_mapping_put(struct panfrost_gem_mapping *mapping) +{ + if (!mapping) + return; + + kref_put(&mapping->refcount, panfrost_gem_mapping_release); +} + +void panfrost_gem_teardown_mappings(struct panfrost_gem_object *bo) +{ + struct panfrost_gem_mapping *mapping; + + mutex_lock(&bo->mappings.lock); + list_for_each_entry(mapping, &bo->mappings.list, node) + panfrost_gem_teardown_mapping(mapping); + mutex_unlock(&bo->mappings.lock); +} + int panfrost_gem_open(struct drm_gem_object *obj, struct drm_file *file_priv) { int ret; @@ -54,6 +123,16 @@ int panfrost_gem_open(struct drm_gem_object *obj, struct drm_file *file_priv) struct panfrost_gem_object *bo = to_panfrost_bo(obj); unsigned long color = bo->noexec ? PANFROST_BO_NOEXEC : 0; struct panfrost_file_priv *priv = file_priv->driver_priv; + struct panfrost_gem_mapping *mapping; + + mapping = kzalloc(sizeof(*mapping), GFP_KERNEL); + if (!mapping) + return -ENOMEM; + + INIT_LIST_HEAD(&mapping->node); + kref_init(&mapping->refcount); + drm_gem_object_get(obj); + mapping->obj = bo; /* * Executable buffers cannot cross a 16MB boundary as the program @@ -66,37 +145,48 @@ int panfrost_gem_open(struct drm_gem_object *obj, struct drm_file *file_priv) else align = size >= SZ_2M ? SZ_2M >> PAGE_SHIFT : 0; - bo->mmu = &priv->mmu; + mapping->mmu = &priv->mmu; spin_lock(&priv->mm_lock); - ret = drm_mm_insert_node_generic(&priv->mm, &bo->node, + ret = drm_mm_insert_node_generic(&priv->mm, &mapping->mmnode, size >> PAGE_SHIFT, align, color, 0); spin_unlock(&priv->mm_lock); if (ret) - return ret; + goto err; if (!bo->is_heap) { - ret = panfrost_mmu_map(bo); - if (ret) { - spin_lock(&priv->mm_lock); - drm_mm_remove_node(&bo->node); - spin_unlock(&priv->mm_lock); - } + ret = panfrost_mmu_map(mapping); + if (ret) + goto err; } + + mutex_lock(&bo->mappings.lock); + WARN_ON(bo->base.madv != PANFROST_MADV_WILLNEED); + list_add_tail(&mapping->node, &bo->mappings.list); + mutex_unlock(&bo->mappings.lock); + +err: + if (ret) + panfrost_gem_mapping_put(mapping); return ret; } void panfrost_gem_close(struct drm_gem_object *obj, struct drm_file *file_priv) { - struct panfrost_gem_object *bo = to_panfrost_bo(obj); struct panfrost_file_priv *priv = file_priv->driver_priv; + struct panfrost_gem_object *bo = to_panfrost_bo(obj); + struct panfrost_gem_mapping *mapping = NULL, *iter; - if (bo->is_mapped) - panfrost_mmu_unmap(bo); + mutex_lock(&bo->mappings.lock); + list_for_each_entry(iter, &bo->mappings.list, node) { + if (iter->mmu == &priv->mmu) { + mapping = iter; + list_del(&iter->node); + break; + } + } + mutex_unlock(&bo->mappings.lock); - spin_lock(&priv->mm_lock); - if (drm_mm_node_allocated(&bo->node)) - drm_mm_remove_node(&bo->node); - spin_unlock(&priv->mm_lock); + panfrost_gem_mapping_put(mapping); } static int panfrost_gem_pin(struct drm_gem_object *obj) @@ -136,6 +226,8 @@ struct drm_gem_object *panfrost_gem_create_object(struct drm_device *dev, size_t if (!obj) return NULL; + INIT_LIST_HEAD(&obj->mappings.list); + mutex_init(&obj->mappings.lock); obj->base.base.funcs = &panfrost_gem_funcs; return &obj->base.base; diff --git a/drivers/gpu/drm/panfrost/panfrost_gem.h b/drivers/gpu/drm/panfrost/panfrost_gem.h index 4b17e7308764..b3517ff9630c 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gem.h +++ b/drivers/gpu/drm/panfrost/panfrost_gem.h @@ -13,23 +13,52 @@ struct panfrost_gem_object { struct drm_gem_shmem_object base; struct sg_table *sgts; - struct panfrost_mmu *mmu; - struct drm_mm_node node; - bool is_mapped :1; + /* + * Use a list for now. If searching a mapping ever becomes the + * bottleneck, we should consider using an RB-tree, or even better, + * let the core store drm_gem_object_mapping entries (where we + * could place driver specific data) instead of drm_gem_object ones + * in its drm_file->object_idr table. + * + * struct drm_gem_object_mapping { + * struct drm_gem_object *obj; + * void *driver_priv; + * }; + */ + struct { + struct list_head list; + struct mutex lock; + } mappings; + + /* + * Count the number of jobs referencing this BO so we don't let the + * shrinker reclaim this object prematurely. + */ + atomic_t gpu_usecount; + bool noexec :1; bool is_heap :1; }; +struct panfrost_gem_mapping { + struct list_head node; + struct kref refcount; + struct panfrost_gem_object *obj; + struct drm_mm_node mmnode; + struct panfrost_mmu *mmu; + bool active :1; +}; + static inline struct panfrost_gem_object *to_panfrost_bo(struct drm_gem_object *obj) { return container_of(to_drm_gem_shmem_obj(obj), struct panfrost_gem_object, base); } -static inline -struct panfrost_gem_object *drm_mm_node_to_panfrost_bo(struct drm_mm_node *node) +static inline struct panfrost_gem_mapping * +drm_mm_node_to_panfrost_mapping(struct drm_mm_node *node) { - return container_of(node, struct panfrost_gem_object, node); + return container_of(node, struct panfrost_gem_mapping, mmnode); } struct drm_gem_object *panfrost_gem_create_object(struct drm_device *dev, size_t size); @@ -49,6 +78,12 @@ int panfrost_gem_open(struct drm_gem_object *obj, struct drm_file *file_priv); void panfrost_gem_close(struct drm_gem_object *obj, struct drm_file *file_priv); +struct panfrost_gem_mapping * +panfrost_gem_mapping_get(struct panfrost_gem_object *bo, + struct panfrost_file_priv *priv); +void panfrost_gem_mapping_put(struct panfrost_gem_mapping *mapping); +void panfrost_gem_teardown_mappings(struct panfrost_gem_object *bo); + void panfrost_gem_shrinker_init(struct drm_device *dev); void panfrost_gem_shrinker_cleanup(struct drm_device *dev); diff --git a/drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c b/drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c index 458f0fa68111..288e46c40673 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c +++ b/drivers/gpu/drm/panfrost/panfrost_gem_shrinker.c @@ -39,11 +39,15 @@ panfrost_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc static bool panfrost_gem_purge(struct drm_gem_object *obj) { struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); + struct panfrost_gem_object *bo = to_panfrost_bo(obj); + + if (atomic_read(&bo->gpu_usecount)) + return false; if (!mutex_trylock(&shmem->pages_lock)) return false; - panfrost_mmu_unmap(to_panfrost_bo(obj)); + panfrost_gem_teardown_mappings(bo); drm_gem_shmem_purge_locked(obj); mutex_unlock(&shmem->pages_lock); diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c index 8822ec13a0d6..1b9b79cd5804 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -309,10 +309,6 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev) ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO, val, val == pfdev->features.l2_present, 100, 1000); - gpu_write(pfdev, STACK_PWRON_LO, pfdev->features.stack_present); - ret |= readl_relaxed_poll_timeout(pfdev->iomem + STACK_READY_LO, - val, val == pfdev->features.stack_present, 100, 1000); - gpu_write(pfdev, SHADER_PWRON_LO, pfdev->features.shader_present); ret |= readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO, val, val == pfdev->features.shader_present, 100, 1000); @@ -329,7 +325,6 @@ void panfrost_gpu_power_off(struct panfrost_device *pfdev) { gpu_write(pfdev, TILER_PWROFF_LO, 0); gpu_write(pfdev, SHADER_PWROFF_LO, 0); - gpu_write(pfdev, STACK_PWROFF_LO, 0); gpu_write(pfdev, L2_PWROFF_LO, 0); } @@ -351,7 +346,7 @@ int panfrost_gpu_init(struct panfrost_device *pfdev) return -ENODEV; err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler, - IRQF_SHARED, "gpu", pfdev); + IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev); if (err) { dev_err(pfdev->dev, "failed to request gpu irq"); return err; diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c index a9ed088ebf08..8fd8726313ae 100644 --- a/drivers/gpu/drm/panfrost/panfrost_job.c +++ b/drivers/gpu/drm/panfrost/panfrost_job.c @@ -268,9 +268,25 @@ static void panfrost_job_cleanup(struct kref *ref) dma_fence_put(job->done_fence); dma_fence_put(job->render_done_fence); + if (job->mappings) { + for (i = 0; i < job->bo_count; i++) { + if (!job->mappings[i]) + break; + + atomic_dec(&job->mappings[i]->obj->gpu_usecount); + panfrost_gem_mapping_put(job->mappings[i]); + } + kvfree(job->mappings); + } + if (job->bos) { - for (i = 0; i < job->bo_count; i++) + struct panfrost_gem_object *bo; + + for (i = 0; i < job->bo_count; i++) { + bo = to_panfrost_bo(job->bos[i]); drm_gem_object_put_unlocked(job->bos[i]); + } + kvfree(job->bos); } @@ -496,7 +512,7 @@ int panfrost_job_init(struct panfrost_device *pfdev) return -ENODEV; ret = devm_request_irq(pfdev->dev, irq, panfrost_job_irq_handler, - IRQF_SHARED, "job", pfdev); + IRQF_SHARED, KBUILD_MODNAME "-job", pfdev); if (ret) { dev_err(pfdev->dev, "failed to request job irq"); return ret; diff --git a/drivers/gpu/drm/panfrost/panfrost_job.h b/drivers/gpu/drm/panfrost/panfrost_job.h index 62454128a792..bbd3ba97ff67 100644 --- a/drivers/gpu/drm/panfrost/panfrost_job.h +++ b/drivers/gpu/drm/panfrost/panfrost_job.h @@ -32,6 +32,7 @@ struct panfrost_job { /* Exclusive fences we have taken from the BOs to wait for */ struct dma_fence **implicit_fences; + struct panfrost_gem_mapping **mappings; struct drm_gem_object **bos; u32 bo_count; diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c index a3ed64a1f15e..23314f41717b 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.c +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c @@ -269,14 +269,15 @@ static int mmu_map_sg(struct panfrost_device *pfdev, struct panfrost_mmu *mmu, return 0; } -int panfrost_mmu_map(struct panfrost_gem_object *bo) +int panfrost_mmu_map(struct panfrost_gem_mapping *mapping) { + struct panfrost_gem_object *bo = mapping->obj; struct drm_gem_object *obj = &bo->base.base; struct panfrost_device *pfdev = to_panfrost_device(obj->dev); struct sg_table *sgt; int prot = IOMMU_READ | IOMMU_WRITE; - if (WARN_ON(bo->is_mapped)) + if (WARN_ON(mapping->active)) return 0; if (bo->noexec) @@ -286,25 +287,28 @@ int panfrost_mmu_map(struct panfrost_gem_object *bo) if (WARN_ON(IS_ERR(sgt))) return PTR_ERR(sgt); - mmu_map_sg(pfdev, bo->mmu, bo->node.start << PAGE_SHIFT, prot, sgt); - bo->is_mapped = true; + mmu_map_sg(pfdev, mapping->mmu, mapping->mmnode.start << PAGE_SHIFT, + prot, sgt); + mapping->active = true; return 0; } -void panfrost_mmu_unmap(struct panfrost_gem_object *bo) +void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping) { + struct panfrost_gem_object *bo = mapping->obj; struct drm_gem_object *obj = &bo->base.base; struct panfrost_device *pfdev = to_panfrost_device(obj->dev); - struct io_pgtable_ops *ops = bo->mmu->pgtbl_ops; - u64 iova = bo->node.start << PAGE_SHIFT; - size_t len = bo->node.size << PAGE_SHIFT; + struct io_pgtable_ops *ops = mapping->mmu->pgtbl_ops; + u64 iova = mapping->mmnode.start << PAGE_SHIFT; + size_t len = mapping->mmnode.size << PAGE_SHIFT; size_t unmapped_len = 0; - if (WARN_ON(!bo->is_mapped)) + if (WARN_ON(!mapping->active)) return; - dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx", bo->mmu->as, iova, len); + dev_dbg(pfdev->dev, "unmap: as=%d, iova=%llx, len=%zx", + mapping->mmu->as, iova, len); while (unmapped_len < len) { size_t unmapped_page; @@ -318,8 +322,9 @@ void panfrost_mmu_unmap(struct panfrost_gem_object *bo) unmapped_len += pgsize; } - panfrost_mmu_flush_range(pfdev, bo->mmu, bo->node.start << PAGE_SHIFT, len); - bo->is_mapped = false; + panfrost_mmu_flush_range(pfdev, mapping->mmu, + mapping->mmnode.start << PAGE_SHIFT, len); + mapping->active = false; } static void mmu_tlb_inv_context_s1(void *cookie) @@ -394,10 +399,10 @@ void panfrost_mmu_pgtable_free(struct panfrost_file_priv *priv) free_io_pgtable_ops(mmu->pgtbl_ops); } -static struct panfrost_gem_object * -addr_to_drm_mm_node(struct panfrost_device *pfdev, int as, u64 addr) +static struct panfrost_gem_mapping * +addr_to_mapping(struct panfrost_device *pfdev, int as, u64 addr) { - struct panfrost_gem_object *bo = NULL; + struct panfrost_gem_mapping *mapping = NULL; struct panfrost_file_priv *priv; struct drm_mm_node *node; u64 offset = addr >> PAGE_SHIFT; @@ -418,8 +423,9 @@ found_mmu: drm_mm_for_each_node(node, &priv->mm) { if (offset >= node->start && offset < (node->start + node->size)) { - bo = drm_mm_node_to_panfrost_bo(node); - drm_gem_object_get(&bo->base.base); + mapping = drm_mm_node_to_panfrost_mapping(node); + + kref_get(&mapping->refcount); break; } } @@ -427,7 +433,7 @@ found_mmu: spin_unlock(&priv->mm_lock); out: spin_unlock(&pfdev->as_lock); - return bo; + return mapping; } #define NUM_FAULT_PAGES (SZ_2M / PAGE_SIZE) @@ -436,28 +442,30 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, u64 addr) { int ret, i; + struct panfrost_gem_mapping *bomapping; struct panfrost_gem_object *bo; struct address_space *mapping; pgoff_t page_offset; struct sg_table *sgt; struct page **pages; - bo = addr_to_drm_mm_node(pfdev, as, addr); - if (!bo) + bomapping = addr_to_mapping(pfdev, as, addr); + if (!bomapping) return -ENOENT; + bo = bomapping->obj; if (!bo->is_heap) { dev_WARN(pfdev->dev, "matching BO is not heap type (GPU VA = %llx)", - bo->node.start << PAGE_SHIFT); + bomapping->mmnode.start << PAGE_SHIFT); ret = -EINVAL; goto err_bo; } - WARN_ON(bo->mmu->as != as); + WARN_ON(bomapping->mmu->as != as); /* Assume 2MB alignment and size multiple */ addr &= ~((u64)SZ_2M - 1); page_offset = addr >> PAGE_SHIFT; - page_offset -= bo->node.start; + page_offset -= bomapping->mmnode.start; mutex_lock(&bo->base.pages_lock); @@ -509,13 +517,14 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, goto err_map; } - mmu_map_sg(pfdev, bo->mmu, addr, IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt); + mmu_map_sg(pfdev, bomapping->mmu, addr, + IOMMU_WRITE | IOMMU_READ | IOMMU_NOEXEC, sgt); - bo->is_mapped = true; + bomapping->active = true; dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr); - drm_gem_object_put_unlocked(&bo->base.base); + panfrost_gem_mapping_put(bomapping); return 0; @@ -632,9 +641,11 @@ int panfrost_mmu_init(struct panfrost_device *pfdev) if (irq <= 0) return -ENODEV; - err = devm_request_threaded_irq(pfdev->dev, irq, panfrost_mmu_irq_handler, + err = devm_request_threaded_irq(pfdev->dev, irq, + panfrost_mmu_irq_handler, panfrost_mmu_irq_handler_thread, - IRQF_SHARED, "mmu", pfdev); + IRQF_SHARED, KBUILD_MODNAME "-mmu", + pfdev); if (err) { dev_err(pfdev->dev, "failed to request mmu irq"); diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.h b/drivers/gpu/drm/panfrost/panfrost_mmu.h index 7c5b6775ae23..44fc2edf63ce 100644 --- a/drivers/gpu/drm/panfrost/panfrost_mmu.h +++ b/drivers/gpu/drm/panfrost/panfrost_mmu.h @@ -4,12 +4,12 @@ #ifndef __PANFROST_MMU_H__ #define __PANFROST_MMU_H__ -struct panfrost_gem_object; +struct panfrost_gem_mapping; struct panfrost_file_priv; struct panfrost_mmu; -int panfrost_mmu_map(struct panfrost_gem_object *bo); -void panfrost_mmu_unmap(struct panfrost_gem_object *bo); +int panfrost_mmu_map(struct panfrost_gem_mapping *mapping); +void panfrost_mmu_unmap(struct panfrost_gem_mapping *mapping); int panfrost_mmu_init(struct panfrost_device *pfdev); void panfrost_mmu_fini(struct panfrost_device *pfdev); diff --git a/drivers/gpu/drm/panfrost/panfrost_perfcnt.c b/drivers/gpu/drm/panfrost/panfrost_perfcnt.c index 2c04e858c50a..684820448be3 100644 --- a/drivers/gpu/drm/panfrost/panfrost_perfcnt.c +++ b/drivers/gpu/drm/panfrost/panfrost_perfcnt.c @@ -25,7 +25,7 @@ #define V4_SHADERS_PER_COREGROUP 4 struct panfrost_perfcnt { - struct panfrost_gem_object *bo; + struct panfrost_gem_mapping *mapping; size_t bosize; void *buf; struct panfrost_file_priv *user; @@ -49,7 +49,7 @@ static int panfrost_perfcnt_dump_locked(struct panfrost_device *pfdev) int ret; reinit_completion(&pfdev->perfcnt->dump_comp); - gpuva = pfdev->perfcnt->bo->node.start << PAGE_SHIFT; + gpuva = pfdev->perfcnt->mapping->mmnode.start << PAGE_SHIFT; gpu_write(pfdev, GPU_PERFCNT_BASE_LO, gpuva); gpu_write(pfdev, GPU_PERFCNT_BASE_HI, gpuva >> 32); gpu_write(pfdev, GPU_INT_CLEAR, @@ -89,17 +89,22 @@ static int panfrost_perfcnt_enable_locked(struct panfrost_device *pfdev, if (IS_ERR(bo)) return PTR_ERR(bo); - perfcnt->bo = to_panfrost_bo(&bo->base); - /* Map the perfcnt buf in the address space attached to file_priv. */ - ret = panfrost_gem_open(&perfcnt->bo->base.base, file_priv); + ret = panfrost_gem_open(&bo->base, file_priv); if (ret) goto err_put_bo; + perfcnt->mapping = panfrost_gem_mapping_get(to_panfrost_bo(&bo->base), + user); + if (!perfcnt->mapping) { + ret = -EINVAL; + goto err_close_bo; + } + perfcnt->buf = drm_gem_shmem_vmap(&bo->base); if (IS_ERR(perfcnt->buf)) { ret = PTR_ERR(perfcnt->buf); - goto err_close_bo; + goto err_put_mapping; } /* @@ -154,12 +159,17 @@ static int panfrost_perfcnt_enable_locked(struct panfrost_device *pfdev, if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8186)) gpu_write(pfdev, GPU_PRFCNT_TILER_EN, 0xffffffff); + /* The BO ref is retained by the mapping. */ + drm_gem_object_put_unlocked(&bo->base); + return 0; err_vunmap: - drm_gem_shmem_vunmap(&perfcnt->bo->base.base, perfcnt->buf); + drm_gem_shmem_vunmap(&bo->base, perfcnt->buf); +err_put_mapping: + panfrost_gem_mapping_put(perfcnt->mapping); err_close_bo: - panfrost_gem_close(&perfcnt->bo->base.base, file_priv); + panfrost_gem_close(&bo->base, file_priv); err_put_bo: drm_gem_object_put_unlocked(&bo->base); return ret; @@ -182,11 +192,11 @@ static int panfrost_perfcnt_disable_locked(struct panfrost_device *pfdev, GPU_PERFCNT_CFG_MODE(GPU_PERFCNT_CFG_MODE_OFF)); perfcnt->user = NULL; - drm_gem_shmem_vunmap(&perfcnt->bo->base.base, perfcnt->buf); + drm_gem_shmem_vunmap(&perfcnt->mapping->obj->base.base, perfcnt->buf); perfcnt->buf = NULL; - panfrost_gem_close(&perfcnt->bo->base.base, file_priv); - drm_gem_object_put_unlocked(&perfcnt->bo->base.base); - perfcnt->bo = NULL; + panfrost_gem_close(&perfcnt->mapping->obj->base.base, file_priv); + panfrost_gem_mapping_put(perfcnt->mapping); + perfcnt->mapping = NULL; pm_runtime_mark_last_busy(pfdev->dev); pm_runtime_put_autosuspend(pfdev->dev); diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 16d73b22f3f5..ab4f8dd00400 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -31,7 +31,6 @@ #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> -#include <drm/drm_vblank.h> #include "qxl_drv.h" #include "qxl_object.h" @@ -372,19 +371,6 @@ static void qxl_crtc_update_monitors_config(struct drm_crtc *crtc, static void qxl_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { - struct drm_device *dev = crtc->dev; - struct drm_pending_vblank_event *event; - unsigned long flags; - - if (crtc->state && crtc->state->event) { - event = crtc->state->event; - crtc->state->event = NULL; - - spin_lock_irqsave(&dev->event_lock, flags); - drm_crtc_send_vblank_event(crtc, event); - spin_unlock_irqrestore(&dev->event_lock, flags); - } - qxl_crtc_update_monitors_config(crtc, "flush"); } diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index 16a5e903533d..62a5e424971b 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -48,11 +48,6 @@ static struct qxl_device *qxl_get_qdev(struct ttm_bo_device *bdev) return qdev; } -static int qxl_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) -{ - return 0; -} - static int qxl_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, struct ttm_mem_type_manager *man) { @@ -256,7 +251,6 @@ static void qxl_bo_move_notify(struct ttm_buffer_object *bo, static struct ttm_bo_driver qxl_bo_driver = { .ttm_tt_create = &qxl_ttm_tt_create, - .invalidate_caches = &qxl_invalidate_caches, .init_mem_type = &qxl_init_mem_type, .eviction_valuable = ttm_bo_eviction_valuable, .evict_flags = &qxl_evict_flags, diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 92ccd7aed0d4..c693b2ca0329 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -5,7 +5,7 @@ ccflags-y := -Idrivers/gpu/drm/amd/include -hostprogs-y := mkregtable +hostprogs := mkregtable clean-files := rn50_reg_safe.h r100_reg_safe.h r200_reg_safe.h rv515_reg_safe.h r300_reg_safe.h r420_reg_safe.h rs600_reg_safe.h r600_reg_safe.h evergreen_reg_safe.h cayman_reg_safe.h quiet_cmd_mkregtable = MKREGTABLE $@ diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index a522e092038b..266e3cbbd09b 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -1263,7 +1263,7 @@ static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) * locking inversion with the driver load path. And the access here is * completely racy anyway. So don't bother with locking for now. */ - return dev->open_count == 0; + return atomic_read(&dev->open_count) == 0; } static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index f4af67035673..badf1b6d1549 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -66,11 +66,6 @@ static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) return rdev; } -static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) -{ - return 0; -} - static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, struct ttm_mem_type_manager *man) { @@ -443,7 +438,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_ mem->bus.size); else mem->bus.addr = - ioremap_nocache(mem->bus.base + mem->bus.offset, + ioremap(mem->bus.base + mem->bus.offset, mem->bus.size); if (!mem->bus.addr) return -ENOMEM; @@ -774,7 +769,6 @@ static struct ttm_bo_driver radeon_bo_driver = { .ttm_tt_create = &radeon_ttm_tt_create, .ttm_tt_populate = &radeon_ttm_tt_populate, .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, - .invalidate_caches = &radeon_invalidate_caches, .init_mem_type = &radeon_init_mem_type, .eviction_valuable = ttm_bo_eviction_valuable, .evict_flags = &radeon_evict_flags, diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 8ffa4fbbdeb3..06432c881e07 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -590,8 +590,9 @@ static void __rcar_lvds_atomic_enable(struct drm_bridge *bridge, } static void rcar_lvds_atomic_enable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_bridge_state *old_bridge_state) { + struct drm_atomic_state *state = old_bridge_state->base.state; struct drm_connector *connector; struct drm_crtc *crtc; @@ -603,7 +604,7 @@ static void rcar_lvds_atomic_enable(struct drm_bridge *bridge, } static void rcar_lvds_atomic_disable(struct drm_bridge *bridge, - struct drm_atomic_state *state) + struct drm_bridge_state *old_bridge_state) { struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); @@ -618,7 +619,8 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge, /* Disable the companion LVDS encoder in dual-link mode. */ if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion) - lvds->companion->funcs->atomic_disable(lvds->companion, state); + lvds->companion->funcs->atomic_disable(lvds->companion, + old_bridge_state); clk_disable_unprepare(lvds->clocks.mod); } @@ -682,6 +684,9 @@ static void rcar_lvds_detach(struct drm_bridge *bridge) static const struct drm_bridge_funcs rcar_lvds_bridge_ops = { .attach = rcar_lvds_attach, .detach = rcar_lvds_detach, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, .atomic_enable = rcar_lvds_atomic_enable, .atomic_disable = rcar_lvds_atomic_disable, .mode_fixup = rcar_lvds_mode_fixup, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index 7582d0e6a60a..0d1884684dcb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -6,6 +6,7 @@ #include <linux/dma-buf.h> #include <linux/iommu.h> +#include <linux/vmalloc.h> #include <drm/drm.h> #include <drm/drm_gem.h> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index d04b3492bdac..cecb2cc781f5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -724,7 +724,7 @@ static int vop_plane_atomic_check(struct drm_plane *plane, int max_scale = win->phy->scl ? FRAC_16_16(8, 1) : DRM_PLANE_HELPER_NO_SCALING; - if (!crtc || !fb) + if (!crtc || WARN_ON(!fb)) return 0; crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 0b3d18c457b2..cc672620d6e0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -328,7 +328,7 @@ static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, { int act_height; - act_height = (src_h + vskiplines - 1) / vskiplines; + act_height = DIV_ROUND_UP(src_h, vskiplines); if (act_height == dst_h) return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines; diff --git a/drivers/gpu/drm/sti/sti_dvo.c b/drivers/gpu/drm/sti/sti_dvo.c index df2ee86cd4c1..b2778ec1cdd7 100644 --- a/drivers/gpu/drm/sti/sti_dvo.c +++ b/drivers/gpu/drm/sti/sti_dvo.c @@ -534,7 +534,7 @@ static int sti_dvo_probe(struct platform_device *pdev) DRM_ERROR("Invalid dvo resource\n"); return -ENOMEM; } - dvo->regs = devm_ioremap_nocache(dev, res->start, + dvo->regs = devm_ioremap(dev, res->start, resource_size(res)); if (!dvo->regs) return -ENOMEM; diff --git a/drivers/gpu/drm/sti/sti_hda.c b/drivers/gpu/drm/sti/sti_hda.c index 8f7bf33815fd..2bb32009d117 100644 --- a/drivers/gpu/drm/sti/sti_hda.c +++ b/drivers/gpu/drm/sti/sti_hda.c @@ -759,14 +759,14 @@ static int sti_hda_probe(struct platform_device *pdev) DRM_ERROR("Invalid hda resource\n"); return -ENOMEM; } - hda->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); + hda->regs = devm_ioremap(dev, res->start, resource_size(res)); if (!hda->regs) return -ENOMEM; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "video-dacs-ctrl"); if (res) { - hda->video_dacs_ctrl = devm_ioremap_nocache(dev, res->start, + hda->video_dacs_ctrl = devm_ioremap(dev, res->start, resource_size(res)); if (!hda->video_dacs_ctrl) return -ENOMEM; diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c index 814560ead4e1..64ed102033c8 100644 --- a/drivers/gpu/drm/sti/sti_hdmi.c +++ b/drivers/gpu/drm/sti/sti_hdmi.c @@ -1393,7 +1393,7 @@ static int sti_hdmi_probe(struct platform_device *pdev) ret = -ENOMEM; goto release_adapter; } - hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); + hdmi->regs = devm_ioremap(dev, res->start, resource_size(res)); if (!hdmi->regs) { ret = -ENOMEM; goto release_adapter; diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c index 5767e93dd1cd..c36a8da373cb 100644 --- a/drivers/gpu/drm/sti/sti_tvout.c +++ b/drivers/gpu/drm/sti/sti_tvout.c @@ -860,7 +860,7 @@ static int sti_tvout_probe(struct platform_device *pdev) DRM_ERROR("Invalid glue resource\n"); return -ENOMEM; } - tvout->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); + tvout->regs = devm_ioremap(dev, res->start, resource_size(res)); if (!tvout->regs) return -ENOMEM; diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c index 0b17ac8a3faa..5e5f82b6a5d9 100644 --- a/drivers/gpu/drm/sti/sti_vtg.c +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -393,7 +393,7 @@ static int vtg_probe(struct platform_device *pdev) DRM_ERROR("Get memory resource failed\n"); return -ENOMEM; } - vtg->regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); + vtg->regs = devm_ioremap(dev, res->start, resource_size(res)); if (!vtg->regs) { DRM_ERROR("failed to remap I/O memory\n"); return -ENOMEM; diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c index 4b165635b2d4..2e1f2664495d 100644 --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c @@ -377,7 +377,9 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) dsi->pllref_clk = devm_clk_get(dev, "ref"); if (IS_ERR(dsi->pllref_clk)) { ret = PTR_ERR(dsi->pllref_clk); - DRM_ERROR("Unable to get pll reference clock: %d\n", ret); + if (ret != -EPROBE_DEFER) + DRM_ERROR("Unable to get pll reference clock: %d\n", + ret); goto err_clk_get; } diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index c2815e8ae1da..8750ee831bea 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -648,9 +648,14 @@ static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) { struct ltdc_device *ldev = crtc_to_ltdc(crtc); + struct drm_crtc_state *state = crtc->state; DRM_DEBUG_DRIVER("\n"); - reg_set(ldev->regs, LTDC_IER, IER_LIE); + + if (state->enable) + reg_set(ldev->regs, LTDC_IER, IER_LIE); + else + return -EPERM; return 0; } @@ -1146,12 +1151,14 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.pad_max_freq_hz = 90000000; if (ldev->caps.hw_version == HWVER_10200) ldev->caps.pad_max_freq_hz = 65000000; + ldev->caps.nb_irq = 2; break; case HWVER_20101: ldev->caps.reg_ofs = REG_OFS_4; ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; ldev->caps.non_alpha_only_l1 = false; ldev->caps.pad_max_freq_hz = 150000000; + ldev->caps.nb_irq = 4; break; default: return -ENODEV; @@ -1251,13 +1258,21 @@ int ltdc_load(struct drm_device *ddev) reg_clear(ldev->regs, LTDC_IER, IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); - for (i = 0; i < MAX_IRQ; i++) { + ret = ltdc_get_caps(ddev); + if (ret) { + DRM_ERROR("hardware identifier (0x%08x) not supported!\n", + ldev->caps.hw_version); + goto err; + } + + DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); + + for (i = 0; i < ldev->caps.nb_irq; i++) { irq = platform_get_irq(pdev, i); - if (irq == -EPROBE_DEFER) + if (irq < 0) { + ret = irq; goto err; - - if (irq < 0) - continue; + } ret = devm_request_threaded_irq(dev, irq, ltdc_irq, ltdc_irq_thread, IRQF_ONESHOT, @@ -1268,16 +1283,6 @@ int ltdc_load(struct drm_device *ddev) } } - - ret = ltdc_get_caps(ddev); - if (ret) { - DRM_ERROR("hardware identifier (0x%08x) not supported!\n", - ldev->caps.hw_version); - goto err; - } - - DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); - /* Add endpoints panels or bridges if any */ for (i = 0; i < MAX_ENDPOINTS; i++) { if (panel[i]) { diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index a1ad0ae3b006..310e87f0667c 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -19,6 +19,7 @@ struct ltdc_caps { const u32 *pix_fmt_hw; /* supported pixel formats */ bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */ int pad_max_freq_hz; /* max frequency supported by pad */ + int nb_irq; /* number of hardware interrupts */ }; #define LTDC_MAX_LAYER 4 diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index 5ae67d526b1d..328272ff77d8 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c @@ -85,7 +85,6 @@ static int sun4i_drv_bind(struct device *dev) } drm_mode_config_init(drm); - drm->mode_config.allow_fb_modifiers = true; ret = component_bind_all(drm->dev, drm); if (ret) { diff --git a/drivers/gpu/drm/tidss/Kconfig b/drivers/gpu/drm/tidss/Kconfig new file mode 100644 index 000000000000..f790a5215302 --- /dev/null +++ b/drivers/gpu/drm/tidss/Kconfig @@ -0,0 +1,14 @@ +config DRM_TIDSS + tristate "DRM Support for TI Keystone" + depends on DRM && OF + depends on ARM || ARM64 || COMPILE_TEST + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_GEM_CMA_HELPER + help + The TI Keystone family SoCs introduced a new generation of + Display SubSystem. There is currently three Keystone family + SoCs released with DSS. Each with somewhat different version + of it. The SoCs are 66AK2Gx, AM65x, and J721E. Set this to Y + or M to add display support for TI Keystone family + platforms. diff --git a/drivers/gpu/drm/tidss/Makefile b/drivers/gpu/drm/tidss/Makefile new file mode 100644 index 000000000000..312645271014 --- /dev/null +++ b/drivers/gpu/drm/tidss/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 + +tidss-y := tidss_crtc.o \ + tidss_drv.o \ + tidss_encoder.o \ + tidss_kms.o \ + tidss_irq.o \ + tidss_plane.o \ + tidss_scale_coefs.o \ + tidss_dispc.o + +obj-$(CONFIG_DRM_TIDSS) += tidss.o diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c new file mode 100644 index 000000000000..032c31ee2820 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_crtc.c @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_plane_helper.h> +#include <drm/drm_vblank.h> + +#include "tidss_crtc.h" +#include "tidss_dispc.h" +#include "tidss_drv.h" +#include "tidss_irq.h" + +/* Page flip and frame done IRQs */ + +static void tidss_crtc_finish_page_flip(struct tidss_crtc *tcrtc) +{ + struct drm_device *ddev = tcrtc->crtc.dev; + struct tidss_device *tidss = ddev->dev_private; + struct drm_pending_vblank_event *event; + unsigned long flags; + bool busy; + + spin_lock_irqsave(&ddev->event_lock, flags); + + /* + * New settings are taken into use at VFP, and GO bit is cleared at + * the same time. This happens before the vertical blank interrupt. + * So there is a small change that the driver sets GO bit after VFP, but + * before vblank, and we have to check for that case here. + */ + busy = dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport); + if (busy) { + spin_unlock_irqrestore(&ddev->event_lock, flags); + return; + } + + event = tcrtc->event; + tcrtc->event = NULL; + + if (!event) { + spin_unlock_irqrestore(&ddev->event_lock, flags); + return; + } + + drm_crtc_send_vblank_event(&tcrtc->crtc, event); + + spin_unlock_irqrestore(&ddev->event_lock, flags); + + drm_crtc_vblank_put(&tcrtc->crtc); +} + +void tidss_crtc_vblank_irq(struct drm_crtc *crtc) +{ + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + + drm_crtc_handle_vblank(crtc); + + tidss_crtc_finish_page_flip(tcrtc); +} + +void tidss_crtc_framedone_irq(struct drm_crtc *crtc) +{ + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + + complete(&tcrtc->framedone_completion); +} + +void tidss_crtc_error_irq(struct drm_crtc *crtc, u64 irqstatus) +{ + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + + dev_err_ratelimited(crtc->dev->dev, "CRTC%u SYNC LOST: (irq %llx)\n", + tcrtc->hw_videoport, irqstatus); +} + +/* drm_crtc_helper_funcs */ + +static int tidss_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct drm_device *ddev = crtc->dev; + struct tidss_device *tidss = ddev->dev_private; + struct dispc_device *dispc = tidss->dispc; + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + u32 hw_videoport = tcrtc->hw_videoport; + const struct drm_display_mode *mode; + enum drm_mode_status ok; + + dev_dbg(ddev->dev, "%s\n", __func__); + + if (!state->enable) + return 0; + + mode = &state->adjusted_mode; + + ok = dispc_vp_mode_valid(dispc, hw_videoport, mode); + if (ok != MODE_OK) { + dev_dbg(ddev->dev, "%s: bad mode: %ux%u pclk %u kHz\n", + __func__, mode->hdisplay, mode->vdisplay, mode->clock); + return -EINVAL; + } + + return dispc_vp_bus_check(dispc, hw_videoport, state); +} + +static void tidss_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state) +{ + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + struct drm_device *ddev = crtc->dev; + struct tidss_device *tidss = ddev->dev_private; + unsigned long flags; + + dev_dbg(ddev->dev, + "%s: %s enabled %d, needs modeset %d, event %p\n", __func__, + crtc->name, drm_atomic_crtc_needs_modeset(crtc->state), + crtc->state->enable, crtc->state->event); + + /* There is nothing to do if CRTC is not going to be enabled. */ + if (!crtc->state->enable) + return; + + /* + * Flush CRTC changes with go bit only if new modeset is not + * coming, so CRTC is enabled trough out the commit. + */ + if (drm_atomic_crtc_needs_modeset(crtc->state)) + return; + + /* If the GO bit is stuck we better quit here. */ + if (WARN_ON(dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport))) + return; + + /* We should have event if CRTC is enabled through out this commit. */ + if (WARN_ON(!crtc->state->event)) + return; + + /* Write vp properties to HW if needed. */ + dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, false); + + WARN_ON(drm_crtc_vblank_get(crtc) != 0); + + spin_lock_irqsave(&ddev->event_lock, flags); + dispc_vp_go(tidss->dispc, tcrtc->hw_videoport); + + WARN_ON(tcrtc->event); + + tcrtc->event = crtc->state->event; + crtc->state->event = NULL; + + spin_unlock_irqrestore(&ddev->event_lock, flags); +} + +static void tidss_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) +{ + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + struct drm_device *ddev = crtc->dev; + struct tidss_device *tidss = ddev->dev_private; + const struct drm_display_mode *mode = &crtc->state->adjusted_mode; + unsigned long flags; + int r; + + dev_dbg(ddev->dev, "%s, event %p\n", __func__, crtc->state->event); + + tidss_runtime_get(tidss); + + r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport, + mode->clock * 1000); + if (r != 0) + return; + + r = dispc_vp_enable_clk(tidss->dispc, tcrtc->hw_videoport); + if (r != 0) + return; + + dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, true); + + /* Turn vertical blanking interrupt reporting on. */ + drm_crtc_vblank_on(crtc); + + dispc_vp_prepare(tidss->dispc, tcrtc->hw_videoport, crtc->state); + + dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport, crtc->state); + + spin_lock_irqsave(&ddev->event_lock, flags); + + if (crtc->state->event) { + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event = NULL; + } + + spin_unlock_irqrestore(&ddev->event_lock, flags); +} + +static void tidss_crtc_atomic_disable(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) +{ + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + struct drm_device *ddev = crtc->dev; + struct tidss_device *tidss = ddev->dev_private; + unsigned long flags; + + dev_dbg(ddev->dev, "%s, event %p\n", __func__, crtc->state->event); + + reinit_completion(&tcrtc->framedone_completion); + + dispc_vp_disable(tidss->dispc, tcrtc->hw_videoport); + + if (!wait_for_completion_timeout(&tcrtc->framedone_completion, + msecs_to_jiffies(500))) + dev_err(tidss->dev, "Timeout waiting for framedone on crtc %d", + tcrtc->hw_videoport); + + dispc_vp_unprepare(tidss->dispc, tcrtc->hw_videoport); + + spin_lock_irqsave(&ddev->event_lock, flags); + if (crtc->state->event) { + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event = NULL; + } + spin_unlock_irqrestore(&ddev->event_lock, flags); + + drm_crtc_vblank_off(crtc); + + dispc_vp_disable_clk(tidss->dispc, tcrtc->hw_videoport); + + tidss_runtime_put(tidss); +} + +static +enum drm_mode_status tidss_crtc_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) +{ + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + struct drm_device *ddev = crtc->dev; + struct tidss_device *tidss = ddev->dev_private; + + return dispc_vp_mode_valid(tidss->dispc, tcrtc->hw_videoport, mode); +} + +static const struct drm_crtc_helper_funcs tidss_crtc_helper_funcs = { + .atomic_check = tidss_crtc_atomic_check, + .atomic_flush = tidss_crtc_atomic_flush, + .atomic_enable = tidss_crtc_atomic_enable, + .atomic_disable = tidss_crtc_atomic_disable, + + .mode_valid = tidss_crtc_mode_valid, +}; + +/* drm_crtc_funcs */ + +static int tidss_crtc_enable_vblank(struct drm_crtc *crtc) +{ + struct drm_device *ddev = crtc->dev; + struct tidss_device *tidss = ddev->dev_private; + + dev_dbg(ddev->dev, "%s\n", __func__); + + tidss_runtime_get(tidss); + + tidss_irq_enable_vblank(crtc); + + return 0; +} + +static void tidss_crtc_disable_vblank(struct drm_crtc *crtc) +{ + struct drm_device *ddev = crtc->dev; + struct tidss_device *tidss = ddev->dev_private; + + dev_dbg(ddev->dev, "%s\n", __func__); + + tidss_irq_disable_vblank(crtc); + + tidss_runtime_put(tidss); +} + +static void tidss_crtc_reset(struct drm_crtc *crtc) +{ + struct tidss_crtc_state *tcrtc; + + if (crtc->state) + __drm_atomic_helper_crtc_destroy_state(crtc->state); + + kfree(crtc->state); + + tcrtc = kzalloc(sizeof(*tcrtc), GFP_KERNEL); + if (!tcrtc) { + crtc->state = NULL; + return; + } + + crtc->state = &tcrtc->base; + crtc->state->crtc = crtc; +} + +static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc) +{ + struct tidss_crtc_state *state, *current_state; + + if (WARN_ON(!crtc->state)) + return NULL; + + current_state = to_tidss_crtc_state(crtc->state); + + state = kmalloc(sizeof(*state), GFP_KERNEL); + if (!state) + return NULL; + + __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); + + state->bus_format = current_state->bus_format; + state->bus_flags = current_state->bus_flags; + + return &state->base; +} + +static const struct drm_crtc_funcs tidss_crtc_funcs = { + .reset = tidss_crtc_reset, + .destroy = drm_crtc_cleanup, + .set_config = drm_atomic_helper_set_config, + .page_flip = drm_atomic_helper_page_flip, + .atomic_duplicate_state = tidss_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, + .enable_vblank = tidss_crtc_enable_vblank, + .disable_vblank = tidss_crtc_disable_vblank, +}; + +struct tidss_crtc *tidss_crtc_create(struct tidss_device *tidss, + u32 hw_videoport, + struct drm_plane *primary) +{ + struct tidss_crtc *tcrtc; + struct drm_crtc *crtc; + unsigned int gamma_lut_size = 0; + bool has_ctm = tidss->feat->vp_feat.color.has_ctm; + int ret; + + tcrtc = devm_kzalloc(tidss->dev, sizeof(*tcrtc), GFP_KERNEL); + if (!tcrtc) + return ERR_PTR(-ENOMEM); + + tcrtc->hw_videoport = hw_videoport; + init_completion(&tcrtc->framedone_completion); + + crtc = &tcrtc->crtc; + + ret = drm_crtc_init_with_planes(&tidss->ddev, crtc, primary, + NULL, &tidss_crtc_funcs, NULL); + if (ret < 0) + return ERR_PTR(ret); + + drm_crtc_helper_add(crtc, &tidss_crtc_helper_funcs); + + /* + * The dispc gamma functions adapt to what ever size we ask + * from it no matter what HW supports. X-server assumes 256 + * element gamma tables so lets use that. + */ + if (tidss->feat->vp_feat.color.gamma_size) + gamma_lut_size = 256; + + drm_crtc_enable_color_mgmt(crtc, 0, has_ctm, gamma_lut_size); + if (gamma_lut_size) + drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size); + + return tcrtc; +} diff --git a/drivers/gpu/drm/tidss/tidss_crtc.h b/drivers/gpu/drm/tidss/tidss_crtc.h new file mode 100644 index 000000000000..df9d90b1ad2d --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_crtc.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#ifndef __TIDSS_CRTC_H__ +#define __TIDSS_CRTC_H__ + +#include <linux/completion.h> +#include <linux/wait.h> + +#include <drm/drm_crtc.h> + +#define to_tidss_crtc(c) container_of((c), struct tidss_crtc, crtc) + +struct tidss_device; + +struct tidss_crtc { + struct drm_crtc crtc; + + u32 hw_videoport; + + struct drm_pending_vblank_event *event; + + struct completion framedone_completion; +}; + +#define to_tidss_crtc_state(x) container_of(x, struct tidss_crtc_state, base) + +struct tidss_crtc_state { + /* Must be first. */ + struct drm_crtc_state base; + + u32 bus_format; + u32 bus_flags; +}; + +void tidss_crtc_vblank_irq(struct drm_crtc *crtc); +void tidss_crtc_framedone_irq(struct drm_crtc *crtc); +void tidss_crtc_error_irq(struct drm_crtc *crtc, u64 irqstatus); + +struct tidss_crtc *tidss_crtc_create(struct tidss_device *tidss, + u32 hw_videoport, + struct drm_plane *primary); +#endif diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c new file mode 100644 index 000000000000..eeb160dc047b --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -0,0 +1,2768 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Jyri Sarha <jsarha@ti.com> + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <drm/drm_fourcc.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_panel.h> + +#include "tidss_crtc.h" +#include "tidss_dispc.h" +#include "tidss_drv.h" +#include "tidss_irq.h" +#include "tidss_plane.h" + +#include "tidss_dispc_regs.h" +#include "tidss_scale_coefs.h" + +static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { + [DSS_REVISION_OFF] = 0x00, + [DSS_SYSCONFIG_OFF] = 0x04, + [DSS_SYSSTATUS_OFF] = 0x08, + [DISPC_IRQ_EOI_OFF] = 0x20, + [DISPC_IRQSTATUS_RAW_OFF] = 0x24, + [DISPC_IRQSTATUS_OFF] = 0x28, + [DISPC_IRQENABLE_SET_OFF] = 0x2c, + [DISPC_IRQENABLE_CLR_OFF] = 0x30, + + [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x40, + [DISPC_GLOBAL_BUFFER_OFF] = 0x44, + + [DISPC_DBG_CONTROL_OFF] = 0x4c, + [DISPC_DBG_STATUS_OFF] = 0x50, + + [DISPC_CLKGATING_DISABLE_OFF] = 0x54, +}; + +const struct dispc_features dispc_k2g_feats = { + .min_pclk_khz = 4375, + + .max_pclk_khz = { + [DISPC_VP_DPI] = 150000, + }, + + /* + * XXX According TRM the RGB input buffer width up to 2560 should + * work on 3 taps, but in practice it only works up to 1280. + */ + .scaling = { + .in_width_max_5tap_rgb = 1280, + .in_width_max_3tap_rgb = 1280, + .in_width_max_5tap_yuv = 2560, + .in_width_max_3tap_yuv = 2560, + .upscale_limit = 16, + .downscale_limit_5tap = 4, + .downscale_limit_3tap = 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max = 32, + }, + + .subrev = DISPC_K2G, + + .common = "common", + + .common_regs = tidss_k2g_common_regs, + + .num_vps = 1, + .vp_name = { "vp1" }, + .ovr_name = { "ovr1" }, + .vpclk_name = { "vp1" }, + .vp_bus_type = { DISPC_VP_DPI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 256, + .gamma_type = TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes = 1, + .vid_name = { "vid1" }, + .vid_lite = { false }, + .vid_order = { 0 }, +}; + +static const u16 tidss_am65x_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { + [DSS_REVISION_OFF] = 0x4, + [DSS_SYSCONFIG_OFF] = 0x8, + [DSS_SYSSTATUS_OFF] = 0x20, + [DISPC_IRQ_EOI_OFF] = 0x24, + [DISPC_IRQSTATUS_RAW_OFF] = 0x28, + [DISPC_IRQSTATUS_OFF] = 0x2c, + [DISPC_IRQENABLE_SET_OFF] = 0x30, + [DISPC_IRQENABLE_CLR_OFF] = 0x40, + [DISPC_VID_IRQENABLE_OFF] = 0x44, + [DISPC_VID_IRQSTATUS_OFF] = 0x58, + [DISPC_VP_IRQENABLE_OFF] = 0x70, + [DISPC_VP_IRQSTATUS_OFF] = 0x7c, + + [WB_IRQENABLE_OFF] = 0x88, + [WB_IRQSTATUS_OFF] = 0x8c, + + [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x90, + [DISPC_GLOBAL_OUTPUT_ENABLE_OFF] = 0x94, + [DISPC_GLOBAL_BUFFER_OFF] = 0x98, + [DSS_CBA_CFG_OFF] = 0x9c, + [DISPC_DBG_CONTROL_OFF] = 0xa0, + [DISPC_DBG_STATUS_OFF] = 0xa4, + [DISPC_CLKGATING_DISABLE_OFF] = 0xa8, + [DISPC_SECURE_DISABLE_OFF] = 0xac, +}; + +const struct dispc_features dispc_am65x_feats = { + .max_pclk_khz = { + [DISPC_VP_DPI] = 165000, + [DISPC_VP_OLDI] = 165000, + }, + + .scaling = { + .in_width_max_5tap_rgb = 1280, + .in_width_max_3tap_rgb = 2560, + .in_width_max_5tap_yuv = 2560, + .in_width_max_3tap_yuv = 4096, + .upscale_limit = 16, + .downscale_limit_5tap = 4, + .downscale_limit_3tap = 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max = 32, + }, + + .subrev = DISPC_AM65X, + + .common = "common", + .common_regs = tidss_am65x_common_regs, + + .num_vps = 2, + .vp_name = { "vp1", "vp2" }, + .ovr_name = { "ovr1", "ovr2" }, + .vpclk_name = { "vp1", "vp2" }, + .vp_bus_type = { DISPC_VP_OLDI, DISPC_VP_DPI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 256, + .gamma_type = TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes = 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name = { "vid", "vidl1" }, + .vid_lite = { false, true, }, + .vid_order = { 1, 0 }, + + .errata = { + .i2000 = true, + }, +}; + +static const u16 tidss_j721e_common_regs[DISPC_COMMON_REG_TABLE_LEN] = { + [DSS_REVISION_OFF] = 0x4, + [DSS_SYSCONFIG_OFF] = 0x8, + [DSS_SYSSTATUS_OFF] = 0x20, + [DISPC_IRQ_EOI_OFF] = 0x80, + [DISPC_IRQSTATUS_RAW_OFF] = 0x28, + [DISPC_IRQSTATUS_OFF] = 0x2c, + [DISPC_IRQENABLE_SET_OFF] = 0x30, + [DISPC_IRQENABLE_CLR_OFF] = 0x34, + [DISPC_VID_IRQENABLE_OFF] = 0x38, + [DISPC_VID_IRQSTATUS_OFF] = 0x48, + [DISPC_VP_IRQENABLE_OFF] = 0x58, + [DISPC_VP_IRQSTATUS_OFF] = 0x68, + + [WB_IRQENABLE_OFF] = 0x78, + [WB_IRQSTATUS_OFF] = 0x7c, + + [DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x98, + [DISPC_GLOBAL_OUTPUT_ENABLE_OFF] = 0x9c, + [DISPC_GLOBAL_BUFFER_OFF] = 0xa0, + [DSS_CBA_CFG_OFF] = 0xa4, + [DISPC_DBG_CONTROL_OFF] = 0xa8, + [DISPC_DBG_STATUS_OFF] = 0xac, + [DISPC_CLKGATING_DISABLE_OFF] = 0xb0, + [DISPC_SECURE_DISABLE_OFF] = 0x90, + + [FBDC_REVISION_1_OFF] = 0xb8, + [FBDC_REVISION_2_OFF] = 0xbc, + [FBDC_REVISION_3_OFF] = 0xc0, + [FBDC_REVISION_4_OFF] = 0xc4, + [FBDC_REVISION_5_OFF] = 0xc8, + [FBDC_REVISION_6_OFF] = 0xcc, + [FBDC_COMMON_CONTROL_OFF] = 0xd0, + [FBDC_CONSTANT_COLOR_0_OFF] = 0xd4, + [FBDC_CONSTANT_COLOR_1_OFF] = 0xd8, + [DISPC_CONNECTIONS_OFF] = 0xe4, + [DISPC_MSS_VP1_OFF] = 0xe8, + [DISPC_MSS_VP3_OFF] = 0xec, +}; + +const struct dispc_features dispc_j721e_feats = { + .max_pclk_khz = { + [DISPC_VP_DPI] = 170000, + [DISPC_VP_INTERNAL] = 600000, + }, + + .scaling = { + .in_width_max_5tap_rgb = 2048, + .in_width_max_3tap_rgb = 4096, + .in_width_max_5tap_yuv = 4096, + .in_width_max_3tap_yuv = 4096, + .upscale_limit = 16, + .downscale_limit_5tap = 4, + .downscale_limit_3tap = 2, + /* + * The max supported pixel inc value is 255. The value + * of pixel inc is calculated like this: 1+(xinc-1)*bpp. + * The maximum bpp of all formats supported by the HW + * is 8. So the maximum supported xinc value is 32, + * because 1+(32-1)*8 < 255 < 1+(33-1)*4. + */ + .xinc_max = 32, + }, + + .subrev = DISPC_J721E, + + .common = "common_m", + .common_regs = tidss_j721e_common_regs, + + .num_vps = 4, + .vp_name = { "vp1", "vp2", "vp3", "vp4" }, + .ovr_name = { "ovr1", "ovr2", "ovr3", "ovr4" }, + .vpclk_name = { "vp1", "vp2", "vp3", "vp4" }, + /* Currently hard coded VP routing (see dispc_initial_config()) */ + .vp_bus_type = { DISPC_VP_INTERNAL, DISPC_VP_DPI, + DISPC_VP_INTERNAL, DISPC_VP_DPI, }, + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 1024, + .gamma_type = TIDSS_GAMMA_10BIT, + }, + }, + .num_planes = 4, + .vid_name = { "vid1", "vidl1", "vid2", "vidl2" }, + .vid_lite = { 0, 1, 0, 1, }, + .vid_order = { 1, 3, 0, 2 }, +}; + +static const u16 *dispc_common_regmap; + +struct dss_vp_data { + u32 *gamma_table; +}; + +struct dss_plane_data { + u32 zorder; + u32 hw_videoport; +}; + +struct dispc_device { + struct tidss_device *tidss; + struct device *dev; + + void __iomem *base_common; + void __iomem *base_vid[TIDSS_MAX_PLANES]; + void __iomem *base_ovr[TIDSS_MAX_PORTS]; + void __iomem *base_vp[TIDSS_MAX_PORTS]; + + struct regmap *oldi_io_ctrl; + + struct clk *vp_clk[TIDSS_MAX_PORTS]; + + const struct dispc_features *feat; + + struct clk *fclk; + + bool is_enabled; + + struct dss_vp_data vp_data[TIDSS_MAX_PORTS]; + + struct dss_plane_data plane_data[TIDSS_MAX_PLANES]; + + u32 *fourccs; + u32 num_fourccs; + + u32 memory_bandwidth_limit; +}; + +static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) +{ + iowrite32(val, dispc->base_common + reg); +} + +static u32 dispc_read(struct dispc_device *dispc, u16 reg) +{ + return ioread32(dispc->base_common + reg); +} + +static +void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) +{ + void __iomem *base = dispc->base_vid[hw_plane]; + + iowrite32(val, base + reg); +} + +static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) +{ + void __iomem *base = dispc->base_vid[hw_plane]; + + return ioread32(base + reg); +} + +static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, + u16 reg, u32 val) +{ + void __iomem *base = dispc->base_ovr[hw_videoport]; + + iowrite32(val, base + reg); +} + +static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) +{ + void __iomem *base = dispc->base_ovr[hw_videoport]; + + return ioread32(base + reg); +} + +static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport, + u16 reg, u32 val) +{ + void __iomem *base = dispc->base_vp[hw_videoport]; + + iowrite32(val, base + reg); +} + +static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) +{ + void __iomem *base = dispc->base_vp[hw_videoport]; + + return ioread32(base + reg); +} + +/* + * TRM gives bitfields as start:end, where start is the higher bit + * number. For example 7:0 + */ + +static u32 FLD_MASK(u32 start, u32 end) +{ + return ((1 << (start - end + 1)) - 1) << end; +} + +static u32 FLD_VAL(u32 val, u32 start, u32 end) +{ + return (val << end) & FLD_MASK(start, end); +} + +static u32 FLD_GET(u32 val, u32 start, u32 end) +{ + return (val & FLD_MASK(start, end)) >> end; +} + +static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) +{ + return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end); +} + +static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) +{ + return FLD_GET(dispc_read(dispc, idx), start, end); +} + +static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, + u32 start, u32 end) +{ + dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, + start, end)); +} + +static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, + u32 start, u32 end) +{ + return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); +} + +static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx, + u32 val, u32 start, u32 end) +{ + dispc_vid_write(dispc, hw_plane, idx, + FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), + val, start, end)); +} + +static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, + u32 start, u32 end) +{ + return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end); +} + +static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val, + u32 start, u32 end) +{ + dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), + val, start, end)); +} + +__maybe_unused +static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx, + u32 start, u32 end) +{ + return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end); +} + +static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, + u32 val, u32 start, u32 end) +{ + dispc_ovr_write(dispc, ovr, idx, + FLD_MOD(dispc_ovr_read(dispc, ovr, idx), + val, start, end)); +} + +static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) +{ + dispc_irq_t vp_stat = 0; + + if (stat & BIT(0)) + vp_stat |= DSS_IRQ_VP_FRAME_DONE(hw_videoport); + if (stat & BIT(1)) + vp_stat |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport); + if (stat & BIT(2)) + vp_stat |= DSS_IRQ_VP_VSYNC_ODD(hw_videoport); + if (stat & BIT(4)) + vp_stat |= DSS_IRQ_VP_SYNC_LOST(hw_videoport); + + return vp_stat; +} + +static u32 dispc_vp_irq_to_raw(dispc_irq_t vpstat, u32 hw_videoport) +{ + u32 stat = 0; + + if (vpstat & DSS_IRQ_VP_FRAME_DONE(hw_videoport)) + stat |= BIT(0); + if (vpstat & DSS_IRQ_VP_VSYNC_EVEN(hw_videoport)) + stat |= BIT(1); + if (vpstat & DSS_IRQ_VP_VSYNC_ODD(hw_videoport)) + stat |= BIT(2); + if (vpstat & DSS_IRQ_VP_SYNC_LOST(hw_videoport)) + stat |= BIT(4); + + return stat; +} + +static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane) +{ + dispc_irq_t vid_stat = 0; + + if (stat & BIT(0)) + vid_stat |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane); + + return vid_stat; +} + +static u32 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane) +{ + u32 stat = 0; + + if (vidstat & DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane)) + stat |= BIT(0); + + return stat; +} + +static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS); + + return dispc_vp_irq_from_raw(stat, hw_videoport); +} + +static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc, + u32 hw_videoport, dispc_irq_t vpstat) +{ + u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport); + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat); +} + +static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc, + u32 hw_plane) +{ + u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS); + + return dispc_vid_irq_from_raw(stat, hw_plane); +} + +static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc, + u32 hw_plane, dispc_irq_t vidstat) +{ + u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); + + dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat); +} + +static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE); + + return dispc_vp_irq_from_raw(stat, hw_videoport); +} + +static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc, + u32 hw_videoport, dispc_irq_t vpstat) +{ + u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport); + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat); +} + +static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc, + u32 hw_plane) +{ + u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE); + + return dispc_vid_irq_from_raw(stat, hw_plane); +} + +static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc, + u32 hw_plane, dispc_irq_t vidstat) +{ + u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); + + dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat); +} + +static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc, + dispc_irq_t mask) +{ + dispc_k2g_vp_write_irqstatus(dispc, 0, mask); + dispc_k2g_vid_write_irqstatus(dispc, 0, mask); +} + +static +dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc) +{ + dispc_irq_t stat = 0; + + /* always clear the top level irqstatus */ + dispc_write(dispc, DISPC_IRQSTATUS, + dispc_read(dispc, DISPC_IRQSTATUS)); + + stat |= dispc_k2g_vp_read_irqstatus(dispc, 0); + stat |= dispc_k2g_vid_read_irqstatus(dispc, 0); + + dispc_k2g_clear_irqstatus(dispc, stat); + + return stat; +} + +static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc) +{ + dispc_irq_t stat = 0; + + stat |= dispc_k2g_vp_read_irqenable(dispc, 0); + stat |= dispc_k2g_vid_read_irqenable(dispc, 0); + + return stat; +} + +static +void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) +{ + dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc); + + /* clear the irqstatus for newly enabled irqs */ + dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask); + + dispc_k2g_vp_set_irqenable(dispc, 0, mask); + dispc_k2g_vid_set_irqenable(dispc, 0, mask); + + dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7)); + + /* flush posted write */ + dispc_k2g_read_irqenable(dispc); +} + +static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport)); + + return dispc_vp_irq_from_raw(stat, hw_videoport); +} + +static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc, + u32 hw_videoport, dispc_irq_t vpstat) +{ + u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport); + + dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat); +} + +static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc, + u32 hw_plane) +{ + u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane)); + + return dispc_vid_irq_from_raw(stat, hw_plane); +} + +static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc, + u32 hw_plane, dispc_irq_t vidstat) +{ + u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); + + dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat); +} + +static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport)); + + return dispc_vp_irq_from_raw(stat, hw_videoport); +} + +static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc, + u32 hw_videoport, dispc_irq_t vpstat) +{ + u32 stat = dispc_vp_irq_to_raw(vpstat, hw_videoport); + + dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat); +} + +static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc, + u32 hw_plane) +{ + u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane)); + + return dispc_vid_irq_from_raw(stat, hw_plane); +} + +static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc, + u32 hw_plane, dispc_irq_t vidstat) +{ + u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); + + dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat); +} + +static +void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) +{ + unsigned int i; + u32 top_clear = 0; + + for (i = 0; i < dispc->feat->num_vps; ++i) { + if (clearmask & DSS_IRQ_VP_MASK(i)) { + dispc_k3_vp_write_irqstatus(dispc, i, clearmask); + top_clear |= BIT(i); + } + } + for (i = 0; i < dispc->feat->num_planes; ++i) { + if (clearmask & DSS_IRQ_PLANE_MASK(i)) { + dispc_k3_vid_write_irqstatus(dispc, i, clearmask); + top_clear |= BIT(4 + i); + } + } + if (dispc->feat->subrev == DISPC_K2G) + return; + + dispc_write(dispc, DISPC_IRQSTATUS, top_clear); + + /* Flush posted writes */ + dispc_read(dispc, DISPC_IRQSTATUS); +} + +static +dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc) +{ + dispc_irq_t status = 0; + unsigned int i; + + for (i = 0; i < dispc->feat->num_vps; ++i) + status |= dispc_k3_vp_read_irqstatus(dispc, i); + + for (i = 0; i < dispc->feat->num_planes; ++i) + status |= dispc_k3_vid_read_irqstatus(dispc, i); + + dispc_k3_clear_irqstatus(dispc, status); + + return status; +} + +static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc) +{ + dispc_irq_t enable = 0; + unsigned int i; + + for (i = 0; i < dispc->feat->num_vps; ++i) + enable |= dispc_k3_vp_read_irqenable(dispc, i); + + for (i = 0; i < dispc->feat->num_planes; ++i) + enable |= dispc_k3_vid_read_irqenable(dispc, i); + + return enable; +} + +static void dispc_k3_set_irqenable(struct dispc_device *dispc, + dispc_irq_t mask) +{ + unsigned int i; + u32 main_enable = 0, main_disable = 0; + dispc_irq_t old_mask; + + old_mask = dispc_k3_read_irqenable(dispc); + + /* clear the irqstatus for newly enabled irqs */ + dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask); + + for (i = 0; i < dispc->feat->num_vps; ++i) { + dispc_k3_vp_set_irqenable(dispc, i, mask); + if (mask & DSS_IRQ_VP_MASK(i)) + main_enable |= BIT(i); /* VP IRQ */ + else + main_disable |= BIT(i); /* VP IRQ */ + } + + for (i = 0; i < dispc->feat->num_planes; ++i) { + dispc_k3_vid_set_irqenable(dispc, i, mask); + if (mask & DSS_IRQ_PLANE_MASK(i)) + main_enable |= BIT(i + 4); /* VID IRQ */ + else + main_disable |= BIT(i + 4); /* VID IRQ */ + } + + if (main_enable) + dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable); + + if (main_disable) + dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable); + + /* Flush posted writes */ + dispc_read(dispc, DISPC_IRQENABLE_SET); +} + +dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) +{ + switch (dispc->feat->subrev) { + case DISPC_K2G: + return dispc_k2g_read_and_clear_irqstatus(dispc); + case DISPC_AM65X: + case DISPC_J721E: + return dispc_k3_read_and_clear_irqstatus(dispc); + default: + WARN_ON(1); + return 0; + } +} + +void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) +{ + switch (dispc->feat->subrev) { + case DISPC_K2G: + dispc_k2g_set_irqenable(dispc, mask); + break; + case DISPC_AM65X: + case DISPC_J721E: + dispc_k3_set_irqenable(dispc, mask); + break; + default: + WARN_ON(1); + break; + } +} + +enum dispc_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 }; + +struct dispc_bus_format { + u32 bus_fmt; + u32 data_width; + bool is_oldi_fmt; + enum dispc_oldi_mode_reg_val oldi_mode_reg_val; +}; + +static const struct dispc_bus_format dispc_bus_formats[] = { + { MEDIA_BUS_FMT_RGB444_1X12, 12, false, 0 }, + { MEDIA_BUS_FMT_RGB565_1X16, 16, false, 0 }, + { MEDIA_BUS_FMT_RGB666_1X18, 18, false, 0 }, + { MEDIA_BUS_FMT_RGB888_1X24, 24, false, 0 }, + { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, 0 }, + { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, 0 }, + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, SPWG_18 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, SPWG_24 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, JEIDA_24 }, +}; + +static const +struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc, + u32 hw_videoport, + u32 bus_fmt, u32 bus_flags) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dispc_bus_formats); ++i) { + if (dispc_bus_formats[i].bus_fmt == bus_fmt) + return &dispc_bus_formats[i]; + } + + return NULL; +} + +int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state) +{ + const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); + const struct dispc_bus_format *fmt; + + fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, + tstate->bus_flags); + if (!fmt) { + dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", + __func__, tstate->bus_format); + return -EINVAL; + } + + if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && + fmt->is_oldi_fmt) { + dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", + __func__, dispc->feat->vp_name[hw_videoport]); + return -EINVAL; + } + + return 0; +} + +static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) +{ + u32 val = power ? 0 : OLDI_PWRDN_TX; + + if (WARN_ON(!dispc->oldi_io_ctrl)) + return; + + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, + OLDI_PWRDN_TX, val); + regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, + OLDI_PWRDN_TX, val); +} + +static void dispc_set_num_datalines(struct dispc_device *dispc, + u32 hw_videoport, int num_lines) +{ + int v; + + switch (num_lines) { + case 12: + v = 0; break; + case 16: + v = 1; break; + case 18: + v = 2; break; + case 24: + v = 3; break; + case 30: + v = 4; break; + case 36: + v = 5; break; + default: + WARN_ON(1); + v = 3; + } + + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); +} + +static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, + const struct dispc_bus_format *fmt) +{ + u32 oldi_cfg = 0; + u32 oldi_reset_bit = BIT(5 + hw_videoport); + int count = 0; + + /* + * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC + * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0. + */ + + if (fmt->data_width == 24) + oldi_cfg |= BIT(8); /* MSB */ + else if (fmt->data_width != 18) + dev_warn(dispc->dev, "%s: %d port width not supported\n", + __func__, fmt->data_width); + + oldi_cfg |= BIT(7); /* DEPOL */ + + oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1); + + oldi_cfg |= BIT(12); /* SOFTRST */ + + oldi_cfg |= BIT(0); /* ENABLE */ + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); + + while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) && + count < 10000) + count++; + + if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS))) + dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", + __func__); +} + +void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state) +{ + const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); + const struct dispc_bus_format *fmt; + + fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, + tstate->bus_flags); + + if (WARN_ON(!fmt)) + return; + + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { + dispc_oldi_tx_power(dispc, true); + + dispc_enable_oldi(dispc, hw_videoport, fmt); + } +} + +void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state) +{ + const struct drm_display_mode *mode = &state->adjusted_mode; + const struct tidss_crtc_state *tstate = to_tidss_crtc_state(state); + bool align, onoff, rf, ieo, ipc, ihs, ivs; + const struct dispc_bus_format *fmt; + u32 hsw, hfp, hbp, vsw, vfp, vbp; + + fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, + tstate->bus_flags); + + if (WARN_ON(!fmt)) + return; + + dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); + + hfp = mode->hsync_start - mode->hdisplay; + hsw = mode->hsync_end - mode->hsync_start; + hbp = mode->htotal - mode->hsync_end; + + vfp = mode->vsync_start - mode->vdisplay; + vsw = mode->vsync_end - mode->vsync_start; + vbp = mode->vtotal - mode->vsync_end; + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, + FLD_VAL(hsw - 1, 7, 0) | + FLD_VAL(hfp - 1, 19, 8) | + FLD_VAL(hbp - 1, 31, 20)); + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, + FLD_VAL(vsw - 1, 7, 0) | + FLD_VAL(vfp, 19, 8) | + FLD_VAL(vbp, 31, 20)); + + ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); + + ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); + + ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); + + ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE); + + /* always use the 'rf' setting */ + onoff = true; + + rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_POSEDGE); + + /* always use aligned syncs */ + align = true; + + /* always use DE_HIGH for OLDI */ + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) + ieo = false; + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, + FLD_VAL(align, 18, 18) | + FLD_VAL(onoff, 17, 17) | + FLD_VAL(rf, 16, 16) | + FLD_VAL(ieo, 15, 15) | + FLD_VAL(ipc, 14, 14) | + FLD_VAL(ihs, 13, 13) | + FLD_VAL(ivs, 12, 12)); + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, + FLD_VAL(mode->hdisplay - 1, 11, 0) | + FLD_VAL(mode->vdisplay - 1, 27, 16)); + + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); +} + +void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) +{ + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); +} + +void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) +{ + if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0); + + dispc_oldi_tx_power(dispc, false); + } +} + +bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) +{ + return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5); +} + +void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) +{ + WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5)); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); +} + +enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; + +static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) +{ + u16 c12; + + c12 = c8 << 4; + + switch (mode) { + case C8_TO_C12_REPLICATE: + /* Copy c8 4 MSB to 4 LSB for full scale c12 */ + c12 |= c8 >> 4; + break; + case C8_TO_C12_MAX: + c12 |= 0xF; + break; + default: + case C8_TO_C12_MIN: + break; + } + + return c12; +} + +static u64 argb8888_to_argb12121212(u32 argb8888, enum c8_to_c12_mode m) +{ + u8 a, r, g, b; + u64 v; + + a = (argb8888 >> 24) & 0xff; + r = (argb8888 >> 16) & 0xff; + g = (argb8888 >> 8) & 0xff; + b = (argb8888 >> 0) & 0xff; + + v = ((u64)c8_to_c12(a, m) << 36) | ((u64)c8_to_c12(r, m) << 24) | + ((u64)c8_to_c12(g, m) << 12) | (u64)c8_to_c12(b, m); + + return v; +} + +static void dispc_vp_set_default_color(struct dispc_device *dispc, + u32 hw_videoport, u32 default_color) +{ + u64 v; + + v = argb8888_to_argb12121212(default_color, C8_TO_C12_REPLICATE); + + dispc_ovr_write(dispc, hw_videoport, + DISPC_OVR_DEFAULT_COLOR, v & 0xffffffff); + dispc_ovr_write(dispc, hw_videoport, + DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff); +} + +enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, + u32 hw_videoport, + const struct drm_display_mode *mode) +{ + u32 hsw, hfp, hbp, vsw, vfp, vbp; + enum dispc_vp_bus_type bus_type; + int max_pclk; + + bus_type = dispc->feat->vp_bus_type[hw_videoport]; + + max_pclk = dispc->feat->max_pclk_khz[bus_type]; + + if (WARN_ON(max_pclk == 0)) + return MODE_BAD; + + if (mode->clock < dispc->feat->min_pclk_khz) + return MODE_CLOCK_LOW; + + if (mode->clock > max_pclk) + return MODE_CLOCK_HIGH; + + if (mode->hdisplay > 4096) + return MODE_BAD; + + if (mode->vdisplay > 4096) + return MODE_BAD; + + /* TODO: add interlace support */ + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + return MODE_NO_INTERLACE; + + /* + * Enforce the output width is divisible by 2. Actually this + * is only needed in following cases: + * - YUV output selected (BT656, BT1120) + * - Dithering enabled + * - TDM with TDMCycleFormat == 3 + * But for simplicity we enforce that always. + */ + if ((mode->hdisplay % 2) != 0) + return MODE_BAD_HVALUE; + + hfp = mode->hsync_start - mode->hdisplay; + hsw = mode->hsync_end - mode->hsync_start; + hbp = mode->htotal - mode->hsync_end; + + vfp = mode->vsync_start - mode->vdisplay; + vsw = mode->vsync_end - mode->vsync_start; + vbp = mode->vtotal - mode->vsync_end; + + if (hsw < 1 || hsw > 256 || + hfp < 1 || hfp > 4096 || + hbp < 1 || hbp > 4096) + return MODE_BAD_HVALUE; + + if (vsw < 1 || vsw > 256 || + vfp > 4095 || vbp > 4095) + return MODE_BAD_VVALUE; + + if (dispc->memory_bandwidth_limit) { + const unsigned int bpp = 4; + u64 bandwidth; + + bandwidth = 1000 * mode->clock; + bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; + bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); + + if (dispc->memory_bandwidth_limit < bandwidth) + return MODE_BAD; + } + + return MODE_OK; +} + +int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport) +{ + int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); + + if (ret) + dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, + ret); + + return ret; +} + +void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport) +{ + clk_disable_unprepare(dispc->vp_clk[hw_videoport]); +} + +/* + * Calculate the percentage difference between the requested pixel clock rate + * and the effective rate resulting from calculating the clock divider value. + */ +static +unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate) +{ + int r = rate / 100, rr = real_rate / 100; + + return (unsigned int)(abs(((rr - r) * 100) / r)); +} + +int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, + unsigned long rate) +{ + int r; + unsigned long new_rate; + + r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); + if (r) { + dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", + hw_videoport, rate); + return r; + } + + new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); + + if (dispc_pclk_diff(rate, new_rate) > 5) + dev_warn(dispc->dev, + "vp%d: Clock rate %lu differs over 5%% from requsted %lu\n", + hw_videoport, new_rate, rate); + + dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", + hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); + + return 0; +} + +/* OVR */ +static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc, + u32 hw_plane, u32 hw_videoport, + u32 x, u32 y, u32 zpos) +{ + /* On k2g there is only one plane and no need for ovr */ + dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION, + x | (y << 16)); +} + +static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc, + u32 hw_plane, u32 hw_videoport, + u32 x, u32 y, u32 zpos) +{ + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + hw_plane, 4, 1); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + x, 17, 6); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + y, 30, 19); +} + +static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, + u32 hw_plane, u32 hw_videoport, + u32 x, u32 y, u32 zpos) +{ + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + hw_plane, 4, 1); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(zpos), + x, 13, 0); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(zpos), + y, 29, 16); +} + +static void dispc_ovr_set_plane(struct dispc_device *dispc, + u32 hw_plane, u32 hw_videoport, + u32 x, u32 y, u32 zpos) +{ + switch (dispc->feat->subrev) { + case DISPC_K2G: + dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, + x, y, zpos); + break; + case DISPC_AM65X: + dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, + x, y, zpos); + break; + case DISPC_J721E: + dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport, + x, y, zpos); + break; + default: + WARN_ON(1); + break; + } +} + +static void dispc_ovr_enable_plane(struct dispc_device *dispc, + u32 hw_videoport, u32 zpos, bool enable) +{ + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(zpos), + !!enable, 0, 0); +} + +/* CSC */ +enum csc_ctm { + CSC_RR, CSC_RG, CSC_RB, + CSC_GR, CSC_GG, CSC_GB, + CSC_BR, CSC_BG, CSC_BB, +}; + +enum csc_yuv2rgb { + CSC_RY, CSC_RCB, CSC_RCR, + CSC_GY, CSC_GCB, CSC_GCR, + CSC_BY, CSC_BCB, CSC_BCR, +}; + +enum csc_rgb2yuv { + CSC_YR, CSC_YG, CSC_YB, + CSC_CBR, CSC_CBG, CSC_CBB, + CSC_CRR, CSC_CRG, CSC_CRB, +}; + +struct dispc_csc_coef { + void (*to_regval)(const struct dispc_csc_coef *csc, u32 *regval); + int m[9]; + int preoffset[3]; + int postoffset[3]; + enum { CLIP_LIMITED_RANGE = 0, CLIP_FULL_RANGE = 1, } cliping; + const char *name; +}; + +#define DISPC_CSC_REGVAL_LEN 8 + +static +void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) +{ +#define OVAL(x, y) (FLD_VAL(x, 15, 3) | FLD_VAL(y, 31, 19)) + regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); + regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); + regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); +#undef OVAL +} + +#define CVAL(x, y) (FLD_VAL(x, 10, 0) | FLD_VAL(y, 26, 16)) +static +void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval) +{ + regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); + regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); + regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); + regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]); + regval[4] = CVAL(csc->m[CSC_BCB], 0); + + dispc_csc_offset_regval(csc, regval); +} + +__maybe_unused static +void dispc_csc_rgb2yuv_regval(const struct dispc_csc_coef *csc, u32 *regval) +{ + regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]); + regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]); + regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]); + regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]); + regval[4] = CVAL(csc->m[CSC_CBB], 0); + + dispc_csc_offset_regval(csc, regval); +} + +static void dispc_csc_cpr_regval(const struct dispc_csc_coef *csc, + u32 *regval) +{ + regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]); + regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]); + regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]); + regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]); + regval[4] = CVAL(csc->m[CSC_BB], 0); + + dispc_csc_offset_regval(csc, regval); +} + +#undef CVAL + +static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, + const struct dispc_csc_coef *csc) +{ + static const u16 dispc_vid_csc_coef_reg[] = { + DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1), + DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3), + DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5), + DISPC_VID_CSC_COEF(6), /* K2G has no post offset support */ + }; + u32 regval[DISPC_CSC_REGVAL_LEN]; + unsigned int i; + + csc->to_regval(csc, regval); + + if (regval[7] != 0) + dev_warn(dispc->dev, "%s: No post offset support for %s\n", + __func__, csc->name); + + for (i = 0; i < ARRAY_SIZE(dispc_vid_csc_coef_reg); i++) + dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], + regval[i]); +} + +static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, + const struct dispc_csc_coef *csc) +{ + static const u16 dispc_vid_csc_coef_reg[DISPC_CSC_REGVAL_LEN] = { + DISPC_VID_CSC_COEF(0), DISPC_VID_CSC_COEF(1), + DISPC_VID_CSC_COEF(2), DISPC_VID_CSC_COEF(3), + DISPC_VID_CSC_COEF(4), DISPC_VID_CSC_COEF(5), + DISPC_VID_CSC_COEF(6), DISPC_VID_CSC_COEF7, + }; + u32 regval[DISPC_CSC_REGVAL_LEN]; + unsigned int i; + + csc->to_regval(csc, regval); + + for (i = 0; i < ARRAY_SIZE(dispc_vid_csc_coef_reg); i++) + dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], + regval[i]); +} + +/* YUV -> RGB, ITU-R BT.601, full range */ +static const struct dispc_csc_coef csc_yuv2rgb_bt601_full = { + dispc_csc_yuv2rgb_regval, + { 256, 0, 358, /* ry, rcb, rcr |1.000 0.000 1.402|*/ + 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/ + 256, 452, 0, }, /* by, bcb, bcr |1.000 1.772 0.000|*/ + { 0, -2048, -2048, }, /* full range */ + { 0, 0, 0, }, + CLIP_FULL_RANGE, + "BT.601 Full", +}; + +/* YUV -> RGB, ITU-R BT.601, limited range */ +static const struct dispc_csc_coef csc_yuv2rgb_bt601_lim = { + dispc_csc_yuv2rgb_regval, + { 298, 0, 409, /* ry, rcb, rcr |1.164 0.000 1.596|*/ + 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/ + 298, 516, 0, }, /* by, bcb, bcr |1.164 2.017 0.000|*/ + { -256, -2048, -2048, }, /* limited range */ + { 0, 0, 0, }, + CLIP_FULL_RANGE, + "BT.601 Limited", +}; + +/* YUV -> RGB, ITU-R BT.709, full range */ +static const struct dispc_csc_coef csc_yuv2rgb_bt709_full = { + dispc_csc_yuv2rgb_regval, + { 256, 0, 402, /* ry, rcb, rcr |1.000 0.000 1.570|*/ + 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/ + 256, 475, 0, }, /* by, bcb, bcr |1.000 1.856 0.000|*/ + { 0, -2048, -2048, }, /* full range */ + { 0, 0, 0, }, + CLIP_FULL_RANGE, + "BT.709 Full", +}; + +/* YUV -> RGB, ITU-R BT.709, limited range */ +static const struct dispc_csc_coef csc_yuv2rgb_bt709_lim = { + dispc_csc_yuv2rgb_regval, + { 298, 0, 459, /* ry, rcb, rcr |1.164 0.000 1.793|*/ + 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/ + 298, 541, 0, }, /* by, bcb, bcr |1.164 2.112 0.000|*/ + { -256, -2048, -2048, }, /* limited range */ + { 0, 0, 0, }, + CLIP_FULL_RANGE, + "BT.709 Limited", +}; + +static const struct { + enum drm_color_encoding encoding; + enum drm_color_range range; + const struct dispc_csc_coef *csc; +} dispc_csc_table[] = { + { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_FULL_RANGE, + &csc_yuv2rgb_bt601_full, }, + { DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_LIMITED_RANGE, + &csc_yuv2rgb_bt601_lim, }, + { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_FULL_RANGE, + &csc_yuv2rgb_bt709_full, }, + { DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE, + &csc_yuv2rgb_bt709_lim, }, +}; + +static const +struct dispc_csc_coef *dispc_find_csc(enum drm_color_encoding encoding, + enum drm_color_range range) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dispc_csc_table); i++) { + if (dispc_csc_table[i].encoding == encoding && + dispc_csc_table[i].range == range) { + return dispc_csc_table[i].csc; + } + } + return NULL; +} + +static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, + const struct drm_plane_state *state) +{ + static const struct dispc_csc_coef *coef; + + coef = dispc_find_csc(state->color_encoding, state->color_range); + if (!coef) { + dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", + __func__, state->color_encoding, state->color_range); + return; + } + + if (dispc->feat->subrev == DISPC_K2G) + dispc_k2g_vid_write_csc(dispc, hw_plane, coef); + else + dispc_k3_vid_write_csc(dispc, hw_plane, coef); +} + +static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, + bool enable) +{ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); +} + +/* SCALER */ + +static u32 dispc_calc_fir_inc(u32 in, u32 out) +{ + return (u32)div_u64(0x200000ull * in, out); +} + +enum dispc_vid_fir_coef_set { + DISPC_VID_FIR_COEF_HORIZ, + DISPC_VID_FIR_COEF_HORIZ_UV, + DISPC_VID_FIR_COEF_VERT, + DISPC_VID_FIR_COEF_VERT_UV, +}; + +static void dispc_vid_write_fir_coefs(struct dispc_device *dispc, + u32 hw_plane, + enum dispc_vid_fir_coef_set coef_set, + const struct tidss_scale_coefs *coefs) +{ + static const u16 c0_regs[] = { + [DISPC_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H0, + [DISPC_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H0_C, + [DISPC_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V0, + [DISPC_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V0_C, + }; + + static const u16 c12_regs[] = { + [DISPC_VID_FIR_COEF_HORIZ] = DISPC_VID_FIR_COEFS_H12, + [DISPC_VID_FIR_COEF_HORIZ_UV] = DISPC_VID_FIR_COEFS_H12_C, + [DISPC_VID_FIR_COEF_VERT] = DISPC_VID_FIR_COEFS_V12, + [DISPC_VID_FIR_COEF_VERT_UV] = DISPC_VID_FIR_COEFS_V12_C, + }; + + const u16 c0_base = c0_regs[coef_set]; + const u16 c12_base = c12_regs[coef_set]; + int phase; + + if (!coefs) { + dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); + return; + } + + for (phase = 0; phase <= 8; ++phase) { + u16 reg = c0_base + phase * 4; + u16 c0 = coefs->c0[phase]; + + dispc_vid_write(dispc, hw_plane, reg, c0); + } + + for (phase = 0; phase <= 15; ++phase) { + u16 reg = c12_base + phase * 4; + s16 c1, c2; + u32 c12; + + c1 = coefs->c1[phase]; + c2 = coefs->c2[phase]; + c12 = FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20); + + dispc_vid_write(dispc, hw_plane, reg, c12); + } +} + +static bool dispc_fourcc_is_yuv(u32 fourcc) +{ + switch (fourcc) { + case DRM_FORMAT_YUYV: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_NV12: + return true; + default: + return false; + } +} + +struct dispc_scaling_params { + int xinc, yinc; + u32 in_w, in_h, in_w_uv, in_h_uv; + u32 fir_xinc, fir_yinc, fir_xinc_uv, fir_yinc_uv; + bool scale_x, scale_y; + const struct tidss_scale_coefs *xcoef, *ycoef, *xcoef_uv, *ycoef_uv; + bool five_taps; +}; + +static int dispc_vid_calc_scaling(struct dispc_device *dispc, + const struct drm_plane_state *state, + struct dispc_scaling_params *sp, + bool lite_plane) +{ + const struct dispc_features_scaling *f = &dispc->feat->scaling; + u32 fourcc = state->fb->format->format; + u32 in_width_max_5tap = f->in_width_max_5tap_rgb; + u32 in_width_max_3tap = f->in_width_max_3tap_rgb; + u32 downscale_limit; + u32 in_width_max; + + memset(sp, 0, sizeof(*sp)); + sp->xinc = 1; + sp->yinc = 1; + sp->in_w = state->src_w >> 16; + sp->in_w_uv = sp->in_w; + sp->in_h = state->src_h >> 16; + sp->in_h_uv = sp->in_h; + + sp->scale_x = sp->in_w != state->crtc_w; + sp->scale_y = sp->in_h != state->crtc_h; + + if (dispc_fourcc_is_yuv(fourcc)) { + in_width_max_5tap = f->in_width_max_5tap_yuv; + in_width_max_3tap = f->in_width_max_3tap_yuv; + + sp->in_w_uv >>= 1; + sp->scale_x = true; + + if (fourcc == DRM_FORMAT_NV12) { + sp->in_h_uv >>= 1; + sp->scale_y = true; + } + } + + /* Skip the rest if no scaling is used */ + if ((!sp->scale_x && !sp->scale_y) || lite_plane) + return 0; + + if (sp->in_w > in_width_max_5tap) { + sp->five_taps = false; + in_width_max = in_width_max_3tap; + downscale_limit = f->downscale_limit_3tap; + } else { + sp->five_taps = true; + in_width_max = in_width_max_5tap; + downscale_limit = f->downscale_limit_5tap; + } + + if (sp->scale_x) { + sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); + + if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) { + dev_dbg(dispc->dev, + "%s: X-scaling factor %u/%u > %u\n", + __func__, state->crtc_w, state->src_w >> 16, + f->upscale_limit); + return -EINVAL; + } + + if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) { + sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w, + state->crtc_w), + downscale_limit); + + if (sp->xinc > f->xinc_max) { + dev_dbg(dispc->dev, + "%s: X-scaling factor %u/%u < 1/%u\n", + __func__, state->crtc_w, + state->src_w >> 16, + downscale_limit * f->xinc_max); + return -EINVAL; + } + + sp->in_w = (state->src_w >> 16) / sp->xinc; + } + + while (sp->in_w > in_width_max) { + sp->xinc++; + sp->in_w = (state->src_w >> 16) / sp->xinc; + } + + if (sp->xinc > f->xinc_max) { + dev_dbg(dispc->dev, + "%s: Too wide input bufer %u > %u\n", __func__, + state->src_w >> 16, in_width_max * f->xinc_max); + return -EINVAL; + } + + /* + * We need even line length for YUV formats. Decimation + * can lead to odd length, so we need to make it even + * again. + */ + if (dispc_fourcc_is_yuv(fourcc)) + sp->in_w &= ~1; + + sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); + } + + if (sp->scale_y) { + sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, state->crtc_h); + + if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) { + dev_dbg(dispc->dev, + "%s: Y-scaling factor %u/%u > %u\n", + __func__, state->crtc_h, state->src_h >> 16, + f->upscale_limit); + return -EINVAL; + } + + if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) { + sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h, + state->crtc_h), + downscale_limit); + + sp->in_h /= sp->yinc; + sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, + state->crtc_h); + } + } + + dev_dbg(dispc->dev, + "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n", + __func__, state->src_w >> 16, state->src_h >> 16, + sp->xinc, sp->yinc, sp->in_w, sp->in_h, + sp->fir_xinc / 0x200000u, + ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, + sp->fir_yinc / 0x200000u, + ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, + sp->five_taps ? 5 : 3, + state->crtc_w, state->crtc_h); + + if (dispc_fourcc_is_yuv(fourcc)) { + if (sp->scale_x) { + sp->in_w_uv /= sp->xinc; + sp->fir_xinc_uv = dispc_calc_fir_inc(sp->in_w_uv, + state->crtc_w); + sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, + sp->fir_xinc_uv, + true); + } + if (sp->scale_y) { + sp->in_h_uv /= sp->yinc; + sp->fir_yinc_uv = dispc_calc_fir_inc(sp->in_h_uv, + state->crtc_h); + sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, + sp->fir_yinc_uv, + sp->five_taps); + } + } + + if (sp->scale_x) + sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, + true); + + if (sp->scale_y) + sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, + sp->five_taps); + + return 0; +} + +static void dispc_vid_set_scaling(struct dispc_device *dispc, + u32 hw_plane, + struct dispc_scaling_params *sp, + u32 fourcc) +{ + /* HORIZONTAL RESIZE ENABLE */ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, + sp->scale_x, 7, 7); + + /* VERTICAL RESIZE ENABLE */ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, + sp->scale_y, 8, 8); + + /* Skip the rest if no scaling is used */ + if (!sp->scale_x && !sp->scale_y) + return; + + /* VERTICAL 5-TAPS */ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, + sp->five_taps, 21, 21); + + if (dispc_fourcc_is_yuv(fourcc)) { + if (sp->scale_x) { + dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, + sp->fir_xinc_uv); + dispc_vid_write_fir_coefs(dispc, hw_plane, + DISPC_VID_FIR_COEF_HORIZ_UV, + sp->xcoef_uv); + } + if (sp->scale_y) { + dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2, + sp->fir_yinc_uv); + dispc_vid_write_fir_coefs(dispc, hw_plane, + DISPC_VID_FIR_COEF_VERT_UV, + sp->ycoef_uv); + } + } + + if (sp->scale_x) { + dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); + dispc_vid_write_fir_coefs(dispc, hw_plane, + DISPC_VID_FIR_COEF_HORIZ, + sp->xcoef); + } + + if (sp->scale_y) { + dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); + dispc_vid_write_fir_coefs(dispc, hw_plane, + DISPC_VID_FIR_COEF_VERT, sp->ycoef); + } +} + +/* OTHER */ + +static const struct { + u32 fourcc; + u8 dss_code; +} dispc_color_formats[] = { + { DRM_FORMAT_ARGB4444, 0x0, }, + { DRM_FORMAT_ABGR4444, 0x1, }, + { DRM_FORMAT_RGBA4444, 0x2, }, + + { DRM_FORMAT_RGB565, 0x3, }, + { DRM_FORMAT_BGR565, 0x4, }, + + { DRM_FORMAT_ARGB1555, 0x5, }, + { DRM_FORMAT_ABGR1555, 0x6, }, + + { DRM_FORMAT_ARGB8888, 0x7, }, + { DRM_FORMAT_ABGR8888, 0x8, }, + { DRM_FORMAT_RGBA8888, 0x9, }, + { DRM_FORMAT_BGRA8888, 0xa, }, + + { DRM_FORMAT_RGB888, 0xb, }, + { DRM_FORMAT_BGR888, 0xc, }, + + { DRM_FORMAT_ARGB2101010, 0xe, }, + { DRM_FORMAT_ABGR2101010, 0xf, }, + + { DRM_FORMAT_XRGB4444, 0x20, }, + { DRM_FORMAT_XBGR4444, 0x21, }, + { DRM_FORMAT_RGBX4444, 0x22, }, + + { DRM_FORMAT_ARGB1555, 0x25, }, + { DRM_FORMAT_ABGR1555, 0x26, }, + + { DRM_FORMAT_XRGB8888, 0x27, }, + { DRM_FORMAT_XBGR8888, 0x28, }, + { DRM_FORMAT_RGBX8888, 0x29, }, + { DRM_FORMAT_BGRX8888, 0x2a, }, + + { DRM_FORMAT_XRGB2101010, 0x2e, }, + { DRM_FORMAT_XBGR2101010, 0x2f, }, + + { DRM_FORMAT_YUYV, 0x3e, }, + { DRM_FORMAT_UYVY, 0x3f, }, + + { DRM_FORMAT_NV12, 0x3d, }, +}; + +static void dispc_plane_set_pixel_format(struct dispc_device *dispc, + u32 hw_plane, u32 fourcc) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { + if (dispc_color_formats[i].fourcc == fourcc) { + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, + dispc_color_formats[i].dss_code, + 6, 1); + return; + } + } + + WARN_ON(1); +} + +const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len) +{ + WARN_ON(!dispc->fourccs); + + *len = dispc->num_fourccs; + + return dispc->fourccs; +} + +static s32 pixinc(int pixels, u8 ps) +{ + if (pixels == 1) + return 1; + else if (pixels > 1) + return 1 + (pixels - 1) * ps; + else if (pixels < 0) + return 1 - (-pixels + 1) * ps; + + WARN_ON(1); + return 0; +} + +int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, + const struct drm_plane_state *state, + u32 hw_videoport) +{ + bool lite = dispc->feat->vid_lite[hw_plane]; + u32 fourcc = state->fb->format->format; + bool need_scaling = state->src_w >> 16 != state->crtc_w || + state->src_h >> 16 != state->crtc_h; + struct dispc_scaling_params scaling; + int ret; + + if (dispc_fourcc_is_yuv(fourcc)) { + if (!dispc_find_csc(state->color_encoding, + state->color_range)) { + dev_dbg(dispc->dev, + "%s: Unsupported CSC (%u,%u) for HW plane %u\n", + __func__, state->color_encoding, + state->color_range, hw_plane); + return -EINVAL; + } + } + + if (need_scaling) { + if (lite) { + dev_dbg(dispc->dev, + "%s: Lite plane %u can't scale %ux%u!=%ux%u\n", + __func__, hw_plane, + state->src_w >> 16, state->src_h >> 16, + state->crtc_w, state->crtc_h); + return -EINVAL; + } + ret = dispc_vid_calc_scaling(dispc, state, &scaling, false); + if (ret) + return ret; + } + + return 0; +} + +static +dma_addr_t dispc_plane_state_paddr(const struct drm_plane_state *state) +{ + struct drm_framebuffer *fb = state->fb; + struct drm_gem_cma_object *gem; + u32 x = state->src_x >> 16; + u32 y = state->src_y >> 16; + + gem = drm_fb_cma_get_gem_obj(state->fb, 0); + + return gem->paddr + fb->offsets[0] + x * fb->format->cpp[0] + + y * fb->pitches[0]; +} + +static +dma_addr_t dispc_plane_state_p_uv_addr(const struct drm_plane_state *state) +{ + struct drm_framebuffer *fb = state->fb; + struct drm_gem_cma_object *gem; + u32 x = state->src_x >> 16; + u32 y = state->src_y >> 16; + + if (WARN_ON(state->fb->format->num_planes != 2)) + return 0; + + gem = drm_fb_cma_get_gem_obj(fb, 1); + + return gem->paddr + fb->offsets[1] + + (x * fb->format->cpp[1] / fb->format->hsub) + + (y * fb->pitches[1] / fb->format->vsub); +} + +int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, + const struct drm_plane_state *state, + u32 hw_videoport) +{ + bool lite = dispc->feat->vid_lite[hw_plane]; + u32 fourcc = state->fb->format->format; + u16 cpp = state->fb->format->cpp[0]; + u32 fb_width = state->fb->pitches[0] / cpp; + dma_addr_t paddr = dispc_plane_state_paddr(state); + struct dispc_scaling_params scale; + + dispc_vid_calc_scaling(dispc, state, &scale, lite); + + dispc_plane_set_pixel_format(dispc, hw_plane, fourcc); + + dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, paddr & 0xffffffff); + dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)paddr >> 32); + dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, paddr & 0xffffffff); + dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)paddr >> 32); + + dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, + (scale.in_w - 1) | ((scale.in_h - 1) << 16)); + + /* For YUV422 format we use the macropixel size for pixel inc */ + if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) + dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, + pixinc(scale.xinc, cpp * 2)); + else + dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, + pixinc(scale.xinc, cpp)); + + dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC, + pixinc(1 + (scale.yinc * fb_width - + scale.xinc * scale.in_w), + cpp)); + + if (state->fb->format->num_planes == 2) { + u16 cpp_uv = state->fb->format->cpp[1]; + u32 fb_width_uv = state->fb->pitches[1] / cpp_uv; + dma_addr_t p_uv_addr = dispc_plane_state_p_uv_addr(state); + + dispc_vid_write(dispc, hw_plane, + DISPC_VID_BA_UV_0, p_uv_addr & 0xffffffff); + dispc_vid_write(dispc, hw_plane, + DISPC_VID_BA_UV_EXT_0, (u64)p_uv_addr >> 32); + dispc_vid_write(dispc, hw_plane, + DISPC_VID_BA_UV_1, p_uv_addr & 0xffffffff); + dispc_vid_write(dispc, hw_plane, + DISPC_VID_BA_UV_EXT_1, (u64)p_uv_addr >> 32); + + dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV, + pixinc(1 + (scale.yinc * fb_width_uv - + scale.xinc * scale.in_w_uv), + cpp_uv)); + } + + if (!lite) { + dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE, + (state->crtc_w - 1) | + ((state->crtc_h - 1) << 16)); + + dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc); + } + + /* enable YUV->RGB color conversion */ + if (dispc_fourcc_is_yuv(fourcc)) { + dispc_vid_csc_setup(dispc, hw_plane, state); + dispc_vid_csc_enable(dispc, hw_plane, true); + } else { + dispc_vid_csc_enable(dispc, hw_plane, false); + } + + dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, + 0xFF & (state->alpha >> 8)); + + if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, + 28, 28); + else + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, + 28, 28); + + dispc_ovr_set_plane(dispc, hw_plane, hw_videoport, + state->crtc_x, state->crtc_y, + state->normalized_zpos); + + dispc->plane_data[hw_plane].zorder = state->normalized_zpos; + dispc->plane_data[hw_plane].hw_videoport = hw_videoport; + + return 0; +} + +int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) +{ + dispc_ovr_enable_plane(dispc, dispc->plane_data[hw_plane].hw_videoport, + dispc->plane_data[hw_plane].zorder, enable); + + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); + + return 0; +} + +static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) +{ + return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0); +} + +static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, + u32 hw_plane, u32 low, u32 high) +{ + dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); +} + +static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, + u32 hw_plane, u32 low, u32 high) +{ + dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); +} + +static void dispc_k2g_plane_init(struct dispc_device *dispc) +{ + unsigned int hw_plane; + + dev_dbg(dispc->dev, "%s()\n", __func__); + + /* MFLAG_CTRL = ENABLED */ + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + /* MFLAG_START = MFLAGNORMALSTARTMODE */ + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + + for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { + u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); + u32 thr_low, thr_high; + u32 mflag_low, mflag_high; + u32 preload; + + thr_high = size - 1; + thr_low = size / 2; + + mflag_high = size * 2 / 3; + mflag_low = size / 3; + + preload = thr_low; + + dev_dbg(dispc->dev, + "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n", + dispc->feat->vid_name[hw_plane], + size, + thr_high, thr_low, + mflag_high, mflag_low, + preload); + + dispc_vid_set_buf_threshold(dispc, hw_plane, + thr_low, thr_high); + dispc_vid_set_mflag_threshold(dispc, hw_plane, + mflag_low, mflag_high); + + dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); + + /* + * Prefetch up to fifo high-threshold value to minimize the + * possibility of underflows. Note that this means the PRELOAD + * register is ignored. + */ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, + 19, 19); + } +} + +static void dispc_k3_plane_init(struct dispc_device *dispc) +{ + unsigned int hw_plane; + u32 cba_lo_pri = 1; + u32 cba_hi_pri = 0; + + dev_dbg(dispc->dev, "%s()\n", __func__); + + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); + + /* MFLAG_CTRL = ENABLED */ + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + /* MFLAG_START = MFLAGNORMALSTARTMODE */ + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + + for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { + u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); + u32 thr_low, thr_high; + u32 mflag_low, mflag_high; + u32 preload; + + thr_high = size - 1; + thr_low = size / 2; + + mflag_high = size * 2 / 3; + mflag_low = size / 3; + + preload = thr_low; + + dev_dbg(dispc->dev, + "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n", + dispc->feat->vid_name[hw_plane], + size, + thr_high, thr_low, + mflag_high, mflag_low, + preload); + + dispc_vid_set_buf_threshold(dispc, hw_plane, + thr_low, thr_high); + dispc_vid_set_mflag_threshold(dispc, hw_plane, + mflag_low, mflag_high); + + dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); + + /* Prefech up to PRELOAD value */ + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, + 19, 19); + } +} + +static void dispc_plane_init(struct dispc_device *dispc) +{ + switch (dispc->feat->subrev) { + case DISPC_K2G: + dispc_k2g_plane_init(dispc); + break; + case DISPC_AM65X: + case DISPC_J721E: + dispc_k3_plane_init(dispc); + break; + default: + WARN_ON(1); + } +} + +static void dispc_vp_init(struct dispc_device *dispc) +{ + unsigned int i; + + dev_dbg(dispc->dev, "%s()\n", __func__); + + /* Enable the gamma Shadow bit-field for all VPs*/ + for (i = 0; i < dispc->feat->num_vps; i++) + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); +} + +static void dispc_initial_config(struct dispc_device *dispc) +{ + dispc_plane_init(dispc); + dispc_vp_init(dispc); + + /* Note: Hardcoded DPI routing on J721E for now */ + if (dispc->feat->subrev == DISPC_J721E) { + dispc_write(dispc, DISPC_CONNECTIONS, + FLD_VAL(2, 3, 0) | /* VP1 to DPI0 */ + FLD_VAL(8, 7, 4) /* VP3 to DPI1 */ + ); + } +} + +static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 *table = dispc->vp_data[hw_videoport].gamma_table; + u32 hwlen = dispc->feat->vp_feat.color.gamma_size; + unsigned int i; + + dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); + + if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) + return; + + for (i = 0; i < hwlen; ++i) { + u32 v = table[i]; + + v |= i << 24; + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE, + v); + } +} + +static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 *table = dispc->vp_data[hw_videoport].gamma_table; + u32 hwlen = dispc->feat->vp_feat.color.gamma_size; + unsigned int i; + + dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); + + if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) + return; + + for (i = 0; i < hwlen; ++i) { + u32 v = table[i]; + + v |= i << 24; + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); + } +} + +static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc, + u32 hw_videoport) +{ + u32 *table = dispc->vp_data[hw_videoport].gamma_table; + u32 hwlen = dispc->feat->vp_feat.color.gamma_size; + unsigned int i; + + dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); + + if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) + return; + + for (i = 0; i < hwlen; ++i) { + u32 v = table[i]; + + if (i == 0) + v |= 1 << 31; + + dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); + } +} + +static void dispc_vp_write_gamma_table(struct dispc_device *dispc, + u32 hw_videoport) +{ + switch (dispc->feat->subrev) { + case DISPC_K2G: + dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); + break; + case DISPC_AM65X: + dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); + break; + case DISPC_J721E: + dispc_j721e_vp_write_gamma_table(dispc, hw_videoport); + break; + default: + WARN_ON(1); + break; + } +} + +static const struct drm_color_lut dispc_vp_gamma_default_lut[] = { + { .red = 0, .green = 0, .blue = 0, }, + { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, +}; + +static void dispc_vp_set_gamma(struct dispc_device *dispc, + u32 hw_videoport, + const struct drm_color_lut *lut, + unsigned int length) +{ + u32 *table = dispc->vp_data[hw_videoport].gamma_table; + u32 hwlen = dispc->feat->vp_feat.color.gamma_size; + u32 hwbits; + unsigned int i; + + dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", + __func__, hw_videoport, length, hwlen); + + if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) + hwbits = 10; + else + hwbits = 8; + + if (!lut || length < 2) { + lut = dispc_vp_gamma_default_lut; + length = ARRAY_SIZE(dispc_vp_gamma_default_lut); + } + + for (i = 0; i < length - 1; ++i) { + unsigned int first = i * (hwlen - 1) / (length - 1); + unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); + unsigned int w = last - first; + u16 r, g, b; + unsigned int j; + + if (w == 0) + continue; + + for (j = 0; j <= w; j++) { + r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; + g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; + b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; + + r >>= 16 - hwbits; + g >>= 16 - hwbits; + b >>= 16 - hwbits; + + table[first + j] = (r << (hwbits * 2)) | + (g << hwbits) | b; + } + } + + dispc_vp_write_gamma_table(dispc, hw_videoport); +} + +static s16 dispc_S31_32_to_s2_8(s64 coef) +{ + u64 sign_bit = 1ULL << 63; + u64 cbits = (u64)coef; + s16 ret; + + if (cbits & sign_bit) + ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x200); + else + ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x1FF); + + return ret; +} + +static void dispc_k2g_cpr_from_ctm(const struct drm_color_ctm *ctm, + struct dispc_csc_coef *cpr) +{ + memset(cpr, 0, sizeof(*cpr)); + + cpr->to_regval = dispc_csc_cpr_regval; + cpr->m[CSC_RR] = dispc_S31_32_to_s2_8(ctm->matrix[0]); + cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]); + cpr->m[CSC_RB] = dispc_S31_32_to_s2_8(ctm->matrix[2]); + cpr->m[CSC_GR] = dispc_S31_32_to_s2_8(ctm->matrix[3]); + cpr->m[CSC_GG] = dispc_S31_32_to_s2_8(ctm->matrix[4]); + cpr->m[CSC_GB] = dispc_S31_32_to_s2_8(ctm->matrix[5]); + cpr->m[CSC_BR] = dispc_S31_32_to_s2_8(ctm->matrix[6]); + cpr->m[CSC_BG] = dispc_S31_32_to_s2_8(ctm->matrix[7]); + cpr->m[CSC_BB] = dispc_S31_32_to_s2_8(ctm->matrix[8]); +} + +#define CVAL(xR, xG, xB) (FLD_VAL(xR, 9, 0) | FLD_VAL(xG, 20, 11) | \ + FLD_VAL(xB, 31, 22)) + +static void dispc_k2g_vp_csc_cpr_regval(const struct dispc_csc_coef *csc, + u32 *regval) +{ + regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); + regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]); + regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]); +} + +#undef CVAL + +static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, + const struct dispc_csc_coef *csc) +{ + static const u16 dispc_vp_cpr_coef_reg[] = { + DISPC_VP_CSC_COEF0, DISPC_VP_CSC_COEF1, DISPC_VP_CSC_COEF2, + /* K2G CPR is packed to three registers. */ + }; + u32 regval[DISPC_CSC_REGVAL_LEN]; + unsigned int i; + + dispc_k2g_vp_csc_cpr_regval(csc, regval); + + for (i = 0; i < ARRAY_SIZE(dispc_vp_cpr_coef_reg); i++) + dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i], + regval[i]); +} + +static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, + struct drm_color_ctm *ctm) +{ + u32 cprenable = 0; + + if (ctm) { + struct dispc_csc_coef cpr; + + dispc_k2g_cpr_from_ctm(ctm, &cpr); + dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); + cprenable = 1; + } + + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, + cprenable, 15, 15); +} + +static s16 dispc_S31_32_to_s3_8(s64 coef) +{ + u64 sign_bit = 1ULL << 63; + u64 cbits = (u64)coef; + s16 ret; + + if (cbits & sign_bit) + ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x400); + else + ret = clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x3FF); + + return ret; +} + +static void dispc_csc_from_ctm(const struct drm_color_ctm *ctm, + struct dispc_csc_coef *cpr) +{ + memset(cpr, 0, sizeof(*cpr)); + + cpr->to_regval = dispc_csc_cpr_regval; + cpr->m[CSC_RR] = dispc_S31_32_to_s3_8(ctm->matrix[0]); + cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]); + cpr->m[CSC_RB] = dispc_S31_32_to_s3_8(ctm->matrix[2]); + cpr->m[CSC_GR] = dispc_S31_32_to_s3_8(ctm->matrix[3]); + cpr->m[CSC_GG] = dispc_S31_32_to_s3_8(ctm->matrix[4]); + cpr->m[CSC_GB] = dispc_S31_32_to_s3_8(ctm->matrix[5]); + cpr->m[CSC_BR] = dispc_S31_32_to_s3_8(ctm->matrix[6]); + cpr->m[CSC_BG] = dispc_S31_32_to_s3_8(ctm->matrix[7]); + cpr->m[CSC_BB] = dispc_S31_32_to_s3_8(ctm->matrix[8]); +} + +static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, + const struct dispc_csc_coef *csc) +{ + static const u16 dispc_vp_csc_coef_reg[DISPC_CSC_REGVAL_LEN] = { + DISPC_VP_CSC_COEF0, DISPC_VP_CSC_COEF1, DISPC_VP_CSC_COEF2, + DISPC_VP_CSC_COEF3, DISPC_VP_CSC_COEF4, DISPC_VP_CSC_COEF5, + DISPC_VP_CSC_COEF6, DISPC_VP_CSC_COEF7, + }; + u32 regval[DISPC_CSC_REGVAL_LEN]; + unsigned int i; + + csc->to_regval(csc, regval); + + for (i = 0; i < ARRAY_SIZE(regval); i++) + dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i], + regval[i]); +} + +static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, + struct drm_color_ctm *ctm) +{ + u32 colorconvenable = 0; + + if (ctm) { + struct dispc_csc_coef csc; + + dispc_csc_from_ctm(ctm, &csc); + dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); + colorconvenable = 1; + } + + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, + colorconvenable, 24, 24); +} + +static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, + u32 hw_videoport, + const struct drm_crtc_state *state, + bool newmodeset) +{ + struct drm_color_lut *lut = NULL; + struct drm_color_ctm *ctm = NULL; + unsigned int length = 0; + + if (!(state->color_mgmt_changed || newmodeset)) + return; + + if (state->gamma_lut) { + lut = (struct drm_color_lut *)state->gamma_lut->data; + length = state->gamma_lut->length / sizeof(*lut); + } + + dispc_vp_set_gamma(dispc, hw_videoport, lut, length); + + if (state->ctm) + ctm = (struct drm_color_ctm *)state->ctm->data; + + if (dispc->feat->subrev == DISPC_K2G) + dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm); + else + dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm); +} + +void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state, bool newmodeset) +{ + dispc_vp_set_default_color(dispc, hw_videoport, 0); + dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset); +} + +int dispc_runtime_suspend(struct dispc_device *dispc) +{ + dev_dbg(dispc->dev, "suspend\n"); + + dispc->is_enabled = false; + + clk_disable_unprepare(dispc->fclk); + + return 0; +} + +int dispc_runtime_resume(struct dispc_device *dispc) +{ + dev_dbg(dispc->dev, "resume\n"); + + clk_prepare_enable(dispc->fclk); + + if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0) + dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); + + dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", + dispc_read(dispc, DSS_REVISION)); + + dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", + REG_GET(dispc, DSS_SYSSTATUS, 1, 1), + REG_GET(dispc, DSS_SYSSTATUS, 2, 2), + REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); + + if (dispc->feat->subrev == DISPC_AM65X) + dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", + REG_GET(dispc, DSS_SYSSTATUS, 5, 5), + REG_GET(dispc, DSS_SYSSTATUS, 6, 6), + REG_GET(dispc, DSS_SYSSTATUS, 7, 7)); + + dev_dbg(dispc->dev, "DISPC IDLE %d\n", + REG_GET(dispc, DSS_SYSSTATUS, 9, 9)); + + dispc_initial_config(dispc); + + dispc->is_enabled = true; + + tidss_irq_resume(dispc->tidss); + + return 0; +} + +void dispc_remove(struct tidss_device *tidss) +{ + dev_dbg(tidss->dev, "%s\n", __func__); + + tidss->dispc = NULL; +} + +static int dispc_iomap_resource(struct platform_device *pdev, const char *name, + void __iomem **base) +{ + struct resource *res; + void __iomem *b; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); + if (!res) { + dev_err(&pdev->dev, "cannot get mem resource '%s'\n", name); + return -EINVAL; + } + + b = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(b)) { + dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name); + return PTR_ERR(b); + } + + *base = b; + + return 0; +} + +static int dispc_init_am65x_oldi_io_ctrl(struct device *dev, + struct dispc_device *dispc) +{ + dispc->oldi_io_ctrl = + syscon_regmap_lookup_by_phandle(dev->of_node, + "ti,am65x-oldi-io-ctrl"); + if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { + dispc->oldi_io_ctrl = NULL; + } else if (IS_ERR(dispc->oldi_io_ctrl)) { + dev_err(dev, "%s: syscon_regmap_lookup_by_phandle failed %ld\n", + __func__, PTR_ERR(dispc->oldi_io_ctrl)); + return PTR_ERR(dispc->oldi_io_ctrl); + } + return 0; +} + +int dispc_init(struct tidss_device *tidss) +{ + struct device *dev = tidss->dev; + struct platform_device *pdev = to_platform_device(dev); + struct dispc_device *dispc; + const struct dispc_features *feat; + unsigned int i, num_fourccs; + int r = 0; + + dev_dbg(dev, "%s\n", __func__); + + feat = tidss->feat; + + if (feat->subrev != DISPC_K2G) { + r = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); + if (r) + dev_warn(dev, "cannot set DMA masks to 48-bit\n"); + } + + dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL); + if (!dispc) + return -ENOMEM; + + dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), + sizeof(*dispc->fourccs), GFP_KERNEL); + if (!dispc->fourccs) + return -ENOMEM; + + num_fourccs = 0; + for (i = 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { + if (feat->errata.i2000 && + dispc_fourcc_is_yuv(dispc_color_formats[i].fourcc)) + continue; + dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; + } + dispc->num_fourccs = num_fourccs; + dispc->tidss = tidss; + dispc->dev = dev; + dispc->feat = feat; + + dispc_common_regmap = dispc->feat->common_regs; + + r = dispc_iomap_resource(pdev, dispc->feat->common, + &dispc->base_common); + if (r) + return r; + + for (i = 0; i < dispc->feat->num_planes; i++) { + r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], + &dispc->base_vid[i]); + if (r) + return r; + } + + for (i = 0; i < dispc->feat->num_vps; i++) { + u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; + u32 *gamma_table; + struct clk *clk; + + r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], + &dispc->base_ovr[i]); + if (r) + return r; + + r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], + &dispc->base_vp[i]); + if (r) + return r; + + clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); + if (IS_ERR(clk)) { + dev_err(dev, "%s: Failed to get clk %s:%ld\n", __func__, + dispc->feat->vpclk_name[i], PTR_ERR(clk)); + return PTR_ERR(clk); + } + dispc->vp_clk[i] = clk; + + gamma_table = devm_kmalloc_array(dev, gamma_size, + sizeof(*gamma_table), + GFP_KERNEL); + if (!gamma_table) + return -ENOMEM; + dispc->vp_data[i].gamma_table = gamma_table; + } + + if (feat->subrev == DISPC_AM65X) { + r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); + if (r) + return r; + } + + dispc->fclk = devm_clk_get(dev, "fck"); + if (IS_ERR(dispc->fclk)) { + dev_err(dev, "%s: Failed to get fclk: %ld\n", + __func__, PTR_ERR(dispc->fclk)); + return PTR_ERR(dispc->fclk); + } + dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); + + of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", + &dispc->memory_bandwidth_limit); + + tidss->dispc = dispc; + + return 0; +} diff --git a/drivers/gpu/drm/tidss/tidss_dispc.h b/drivers/gpu/drm/tidss/tidss_dispc.h new file mode 100644 index 000000000000..e65e6a2bb821 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_dispc.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#ifndef __TIDSS_DISPC_H__ +#define __TIDSS_DISPC_H__ + +#include "tidss_drv.h" + +struct dispc_device; + +struct drm_crtc_state; + +enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT }; + +struct tidss_vp_feat { + struct tidss_vp_color_feat { + u32 gamma_size; + enum tidss_gamma_type gamma_type; + bool has_ctm; + } color; +}; + +struct tidss_plane_feat { + struct tidss_plane_color_feat { + u32 encodings; + u32 ranges; + enum drm_color_encoding default_encoding; + enum drm_color_range default_range; + } color; + struct tidss_plane_blend_feat { + bool global_alpha; + } blend; +}; + +struct dispc_features_scaling { + u32 in_width_max_5tap_rgb; + u32 in_width_max_3tap_rgb; + u32 in_width_max_5tap_yuv; + u32 in_width_max_3tap_yuv; + u32 upscale_limit; + u32 downscale_limit_5tap; + u32 downscale_limit_3tap; + u32 xinc_max; +}; + +struct dispc_errata { + bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */ +}; + +enum dispc_vp_bus_type { + DISPC_VP_DPI, /* DPI output */ + DISPC_VP_OLDI, /* OLDI (LVDS) output */ + DISPC_VP_INTERNAL, /* SoC internal routing */ + DISPC_VP_MAX_BUS_TYPE, +}; + +enum dispc_dss_subrevision { + DISPC_K2G, + DISPC_AM65X, + DISPC_J721E, +}; + +struct dispc_features { + int min_pclk_khz; + int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE]; + + struct dispc_features_scaling scaling; + + enum dispc_dss_subrevision subrev; + + const char *common; + const u16 *common_regs; + u32 num_vps; + const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ + const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ + const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ + const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; + struct tidss_vp_feat vp_feat; + u32 num_planes; + const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ + bool vid_lite[TIDSS_MAX_PLANES]; + u32 vid_order[TIDSS_MAX_PLANES]; + + struct dispc_errata errata; +}; + +extern const struct dispc_features dispc_k2g_feats; +extern const struct dispc_features dispc_am65x_feats; +extern const struct dispc_features dispc_j721e_feats; + +void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask); +dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc); + +void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state); +void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state); +void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport); +void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport); +bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport); +void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport); +int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state); +enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, + u32 hw_videoport, + const struct drm_display_mode *mode); +int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport); +void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport); +int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, + unsigned long rate); +void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, + const struct drm_crtc_state *state, bool newmodeset); + +int dispc_runtime_suspend(struct dispc_device *dispc); +int dispc_runtime_resume(struct dispc_device *dispc); + +int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, + const struct drm_plane_state *state, + u32 hw_videoport); +int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, + const struct drm_plane_state *state, + u32 hw_videoport); +int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable); +const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len); + +int dispc_init(struct tidss_device *tidss); +void dispc_remove(struct tidss_device *tidss); + +#endif diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tidss/tidss_dispc_regs.h new file mode 100644 index 000000000000..88a83a41b6e3 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Jyri Sarha <jsarha@ti.com> + */ + +#ifndef __TIDSS_DISPC_REGS_H +#define __TIDSS_DISPC_REGS_H + +enum dispc_common_regs { + NOT_APPLICABLE_OFF = 0, + DSS_REVISION_OFF, + DSS_SYSCONFIG_OFF, + DSS_SYSSTATUS_OFF, + DISPC_IRQ_EOI_OFF, + DISPC_IRQSTATUS_RAW_OFF, + DISPC_IRQSTATUS_OFF, + DISPC_IRQENABLE_SET_OFF, + DISPC_IRQENABLE_CLR_OFF, + DISPC_VID_IRQENABLE_OFF, + DISPC_VID_IRQSTATUS_OFF, + DISPC_VP_IRQENABLE_OFF, + DISPC_VP_IRQSTATUS_OFF, + WB_IRQENABLE_OFF, + WB_IRQSTATUS_OFF, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF, + DISPC_GLOBAL_OUTPUT_ENABLE_OFF, + DISPC_GLOBAL_BUFFER_OFF, + DSS_CBA_CFG_OFF, + DISPC_DBG_CONTROL_OFF, + DISPC_DBG_STATUS_OFF, + DISPC_CLKGATING_DISABLE_OFF, + DISPC_SECURE_DISABLE_OFF, + FBDC_REVISION_1_OFF, + FBDC_REVISION_2_OFF, + FBDC_REVISION_3_OFF, + FBDC_REVISION_4_OFF, + FBDC_REVISION_5_OFF, + FBDC_REVISION_6_OFF, + FBDC_COMMON_CONTROL_OFF, + FBDC_CONSTANT_COLOR_0_OFF, + FBDC_CONSTANT_COLOR_1_OFF, + DISPC_CONNECTIONS_OFF, + DISPC_MSS_VP1_OFF, + DISPC_MSS_VP3_OFF, + DISPC_COMMON_REG_TABLE_LEN, +}; + +/* + * dispc_common_regmap should be defined as const u16 * and pointing + * to a valid dss common register map for the platform, before the + * macros bellow can be used. + */ + +#define REG(r) (dispc_common_regmap[r ## _OFF]) + +#define DSS_REVISION REG(DSS_REVISION) +#define DSS_SYSCONFIG REG(DSS_SYSCONFIG) +#define DSS_SYSSTATUS REG(DSS_SYSSTATUS) +#define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI) +#define DISPC_IRQSTATUS_RAW REG(DISPC_IRQSTATUS_RAW) +#define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS) +#define DISPC_IRQENABLE_SET REG(DISPC_IRQENABLE_SET) +#define DISPC_IRQENABLE_CLR REG(DISPC_IRQENABLE_CLR) +#define DISPC_VID_IRQENABLE(n) (REG(DISPC_VID_IRQENABLE) + (n) * 4) +#define DISPC_VID_IRQSTATUS(n) (REG(DISPC_VID_IRQSTATUS) + (n) * 4) +#define DISPC_VP_IRQENABLE(n) (REG(DISPC_VP_IRQENABLE) + (n) * 4) +#define DISPC_VP_IRQSTATUS(n) (REG(DISPC_VP_IRQSTATUS) + (n) * 4) +#define WB_IRQENABLE REG(WB_IRQENABLE) +#define WB_IRQSTATUS REG(WB_IRQSTATUS) + +#define DISPC_GLOBAL_MFLAG_ATTRIBUTE REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE) +#define DISPC_GLOBAL_OUTPUT_ENABLE REG(DISPC_GLOBAL_OUTPUT_ENABLE) +#define DISPC_GLOBAL_BUFFER REG(DISPC_GLOBAL_BUFFER) +#define DSS_CBA_CFG REG(DSS_CBA_CFG) +#define DISPC_DBG_CONTROL REG(DISPC_DBG_CONTROL) +#define DISPC_DBG_STATUS REG(DISPC_DBG_STATUS) +#define DISPC_CLKGATING_DISABLE REG(DISPC_CLKGATING_DISABLE) +#define DISPC_SECURE_DISABLE REG(DISPC_SECURE_DISABLE) + +#define FBDC_REVISION_1 REG(FBDC_REVISION_1) +#define FBDC_REVISION_2 REG(FBDC_REVISION_2) +#define FBDC_REVISION_3 REG(FBDC_REVISION_3) +#define FBDC_REVISION_4 REG(FBDC_REVISION_4) +#define FBDC_REVISION_5 REG(FBDC_REVISION_5) +#define FBDC_REVISION_6 REG(FBDC_REVISION_6) +#define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL) +#define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0) +#define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1) +#define DISPC_CONNECTIONS REG(DISPC_CONNECTIONS) +#define DISPC_MSS_VP1 REG(DISPC_MSS_VP1) +#define DISPC_MSS_VP3 REG(DISPC_MSS_VP3) + +/* VID */ + +#define DISPC_VID_ACCUH_0 0x0 +#define DISPC_VID_ACCUH_1 0x4 +#define DISPC_VID_ACCUH2_0 0x8 +#define DISPC_VID_ACCUH2_1 0xc +#define DISPC_VID_ACCUV_0 0x10 +#define DISPC_VID_ACCUV_1 0x14 +#define DISPC_VID_ACCUV2_0 0x18 +#define DISPC_VID_ACCUV2_1 0x1c +#define DISPC_VID_ATTRIBUTES 0x20 +#define DISPC_VID_ATTRIBUTES2 0x24 +#define DISPC_VID_BA_0 0x28 +#define DISPC_VID_BA_1 0x2c +#define DISPC_VID_BA_UV_0 0x30 +#define DISPC_VID_BA_UV_1 0x34 +#define DISPC_VID_BUF_SIZE_STATUS 0x38 +#define DISPC_VID_BUF_THRESHOLD 0x3c +#define DISPC_VID_CSC_COEF(n) (0x40 + (n) * 4) + +#define DISPC_VID_FIRH 0x5c +#define DISPC_VID_FIRH2 0x60 +#define DISPC_VID_FIRV 0x64 +#define DISPC_VID_FIRV2 0x68 + +#define DISPC_VID_FIR_COEFS_H0 0x6c +#define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) +#define DISPC_VID_FIR_COEFS_H0_C 0x90 +#define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) + +#define DISPC_VID_FIR_COEFS_H12 0xb4 +#define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) +#define DISPC_VID_FIR_COEFS_H12_C 0xf4 +#define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) + +#define DISPC_VID_FIR_COEFS_V0 0x134 +#define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) +#define DISPC_VID_FIR_COEFS_V0_C 0x158 +#define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) + +#define DISPC_VID_FIR_COEFS_V12 0x17c +#define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) +#define DISPC_VID_FIR_COEFS_V12_C 0x1bc +#define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) + +#define DISPC_VID_GLOBAL_ALPHA 0x1fc +#define DISPC_VID_K2G_IRQENABLE 0x200 /* K2G */ +#define DISPC_VID_K2G_IRQSTATUS 0x204 /* K2G */ +#define DISPC_VID_MFLAG_THRESHOLD 0x208 +#define DISPC_VID_PICTURE_SIZE 0x20c +#define DISPC_VID_PIXEL_INC 0x210 +#define DISPC_VID_K2G_POSITION 0x214 /* K2G */ +#define DISPC_VID_PRELOAD 0x218 +#define DISPC_VID_ROW_INC 0x21c +#define DISPC_VID_SIZE 0x220 +#define DISPC_VID_BA_EXT_0 0x22c +#define DISPC_VID_BA_EXT_1 0x230 +#define DISPC_VID_BA_UV_EXT_0 0x234 +#define DISPC_VID_BA_UV_EXT_1 0x238 +#define DISPC_VID_CSC_COEF7 0x23c +#define DISPC_VID_ROW_INC_UV 0x248 +#define DISPC_VID_CLUT 0x260 +#define DISPC_VID_SAFETY_ATTRIBUTES 0x2a0 +#define DISPC_VID_SAFETY_CAPT_SIGNATURE 0x2a4 +#define DISPC_VID_SAFETY_POSITION 0x2a8 +#define DISPC_VID_SAFETY_REF_SIGNATURE 0x2ac +#define DISPC_VID_SAFETY_SIZE 0x2b0 +#define DISPC_VID_SAFETY_LFSR_SEED 0x2b4 +#define DISPC_VID_LUMAKEY 0x2b8 +#define DISPC_VID_DMA_BUFSIZE 0x2bc /* J721E */ + +/* OVR */ + +#define DISPC_OVR_CONFIG 0x0 +#define DISPC_OVR_VIRTVP 0x4 /* J721E */ +#define DISPC_OVR_DEFAULT_COLOR 0x8 +#define DISPC_OVR_DEFAULT_COLOR2 0xc +#define DISPC_OVR_TRANS_COLOR_MAX 0x10 +#define DISPC_OVR_TRANS_COLOR_MAX2 0x14 +#define DISPC_OVR_TRANS_COLOR_MIN 0x18 +#define DISPC_OVR_TRANS_COLOR_MIN2 0x1c +#define DISPC_OVR_ATTRIBUTES(n) (0x20 + (n) * 4) +#define DISPC_OVR_ATTRIBUTES2(n) (0x34 + (n) * 4) /* J721E */ +/* VP */ + +#define DISPC_VP_CONFIG 0x0 +#define DISPC_VP_CONTROL 0x4 +#define DISPC_VP_CSC_COEF0 0x8 +#define DISPC_VP_CSC_COEF1 0xc +#define DISPC_VP_CSC_COEF2 0x10 +#define DISPC_VP_DATA_CYCLE_0 0x14 +#define DISPC_VP_DATA_CYCLE_1 0x18 +#define DISPC_VP_K2G_GAMMA_TABLE 0x20 /* K2G */ +#define DISPC_VP_K2G_IRQENABLE 0x3c /* K2G */ +#define DISPC_VP_K2G_IRQSTATUS 0x40 /* K2G */ +#define DISPC_VP_DATA_CYCLE_2 0x1c +#define DISPC_VP_LINE_NUMBER 0x44 +#define DISPC_VP_POL_FREQ 0x4c +#define DISPC_VP_SIZE_SCREEN 0x50 +#define DISPC_VP_TIMING_H 0x54 +#define DISPC_VP_TIMING_V 0x58 +#define DISPC_VP_CSC_COEF3 0x5c +#define DISPC_VP_CSC_COEF4 0x60 +#define DISPC_VP_CSC_COEF5 0x64 +#define DISPC_VP_CSC_COEF6 0x68 +#define DISPC_VP_CSC_COEF7 0x6c +#define DISPC_VP_SAFETY_ATTRIBUTES_0 0x70 +#define DISPC_VP_SAFETY_ATTRIBUTES_1 0x74 +#define DISPC_VP_SAFETY_ATTRIBUTES_2 0x78 +#define DISPC_VP_SAFETY_ATTRIBUTES_3 0x7c +#define DISPC_VP_SAFETY_CAPT_SIGNATURE_0 0x90 +#define DISPC_VP_SAFETY_CAPT_SIGNATURE_1 0x94 +#define DISPC_VP_SAFETY_CAPT_SIGNATURE_2 0x98 +#define DISPC_VP_SAFETY_CAPT_SIGNATURE_3 0x9c +#define DISPC_VP_SAFETY_POSITION_0 0xb0 +#define DISPC_VP_SAFETY_POSITION_1 0xb4 +#define DISPC_VP_SAFETY_POSITION_2 0xb8 +#define DISPC_VP_SAFETY_POSITION_3 0xbc +#define DISPC_VP_SAFETY_REF_SIGNATURE_0 0xd0 +#define DISPC_VP_SAFETY_REF_SIGNATURE_1 0xd4 +#define DISPC_VP_SAFETY_REF_SIGNATURE_2 0xd8 +#define DISPC_VP_SAFETY_REF_SIGNATURE_3 0xdc +#define DISPC_VP_SAFETY_SIZE_0 0xf0 +#define DISPC_VP_SAFETY_SIZE_1 0xf4 +#define DISPC_VP_SAFETY_SIZE_2 0xf8 +#define DISPC_VP_SAFETY_SIZE_3 0xfc +#define DISPC_VP_SAFETY_LFSR_SEED 0x110 +#define DISPC_VP_GAMMA_TABLE 0x120 +#define DISPC_VP_DSS_OLDI_CFG 0x160 +#define DISPC_VP_DSS_OLDI_STATUS 0x164 +#define DISPC_VP_DSS_OLDI_LB 0x168 +#define DISPC_VP_DSS_MERGE_SPLIT 0x16c /* J721E */ +#define DISPC_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */ +#define DISPC_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */ + +/* + * OLDI IO_CTRL register offsets. On AM654 the registers are found + * from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from + * CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL + * register range. + */ +#define OLDI_DAT0_IO_CTRL 0x00 +#define OLDI_DAT1_IO_CTRL 0x04 +#define OLDI_DAT2_IO_CTRL 0x08 +#define OLDI_DAT3_IO_CTRL 0x0C +#define OLDI_CLK_IO_CTRL 0x10 + +#define OLDI_PWRDN_TX BIT(8) + +#endif /* __TIDSS_DISPC_REGS_H */ diff --git a/drivers/gpu/drm/tidss/tidss_drv.c b/drivers/gpu/drm/tidss/tidss_drv.c new file mode 100644 index 000000000000..d95e4be2c7b9 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_drv.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#include <linux/console.h> +#include <linux/of_device.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> + +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_drv.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_irq.h> +#include <drm/drm_probe_helper.h> + +#include "tidss_dispc.h" +#include "tidss_drv.h" +#include "tidss_kms.h" +#include "tidss_irq.h" + +/* Power management */ + +int tidss_runtime_get(struct tidss_device *tidss) +{ + int r; + + dev_dbg(tidss->dev, "%s\n", __func__); + + r = pm_runtime_get_sync(tidss->dev); + WARN_ON(r < 0); + return r < 0 ? r : 0; +} + +void tidss_runtime_put(struct tidss_device *tidss) +{ + int r; + + dev_dbg(tidss->dev, "%s\n", __func__); + + r = pm_runtime_put_sync(tidss->dev); + WARN_ON(r < 0); +} + +static int __maybe_unused tidss_pm_runtime_suspend(struct device *dev) +{ + struct tidss_device *tidss = dev_get_drvdata(dev); + + dev_dbg(dev, "%s\n", __func__); + + return dispc_runtime_suspend(tidss->dispc); +} + +static int __maybe_unused tidss_pm_runtime_resume(struct device *dev) +{ + struct tidss_device *tidss = dev_get_drvdata(dev); + int r; + + dev_dbg(dev, "%s\n", __func__); + + r = dispc_runtime_resume(tidss->dispc); + if (r) + return r; + + return 0; +} + +static int __maybe_unused tidss_suspend(struct device *dev) +{ + struct tidss_device *tidss = dev_get_drvdata(dev); + + dev_dbg(dev, "%s\n", __func__); + + return drm_mode_config_helper_suspend(&tidss->ddev); +} + +static int __maybe_unused tidss_resume(struct device *dev) +{ + struct tidss_device *tidss = dev_get_drvdata(dev); + + dev_dbg(dev, "%s\n", __func__); + + return drm_mode_config_helper_resume(&tidss->ddev); +} + +#ifdef CONFIG_PM + +static const struct dev_pm_ops tidss_pm_ops = { + .runtime_suspend = tidss_pm_runtime_suspend, + .runtime_resume = tidss_pm_runtime_resume, + SET_SYSTEM_SLEEP_PM_OPS(tidss_suspend, tidss_resume) +}; + +#endif /* CONFIG_PM */ + +/* DRM device Information */ + +static void tidss_release(struct drm_device *ddev) +{ + struct tidss_device *tidss = ddev->dev_private; + + drm_kms_helper_poll_fini(ddev); + + tidss_modeset_cleanup(tidss); + + drm_dev_fini(ddev); + + kfree(tidss); +} + +DEFINE_DRM_GEM_CMA_FOPS(tidss_fops); + +static struct drm_driver tidss_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + .fops = &tidss_fops, + .release = tidss_release, + DRM_GEM_CMA_VMAP_DRIVER_OPS, + .name = "tidss", + .desc = "TI Keystone DSS", + .date = "20180215", + .major = 1, + .minor = 0, + + .irq_preinstall = tidss_irq_preinstall, + .irq_postinstall = tidss_irq_postinstall, + .irq_handler = tidss_irq_handler, + .irq_uninstall = tidss_irq_uninstall, +}; + +static int tidss_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct tidss_device *tidss; + struct drm_device *ddev; + int ret; + int irq; + + dev_dbg(dev, "%s\n", __func__); + + /* Can't use devm_* since drm_device's lifetime may exceed dev's */ + tidss = kzalloc(sizeof(*tidss), GFP_KERNEL); + if (!tidss) + return -ENOMEM; + + ddev = &tidss->ddev; + + ret = devm_drm_dev_init(&pdev->dev, ddev, &tidss_driver); + if (ret) { + kfree(ddev); + return ret; + } + + tidss->dev = dev; + tidss->feat = of_device_get_match_data(dev); + + platform_set_drvdata(pdev, tidss); + + ddev->dev_private = tidss; + + ret = dispc_init(tidss); + if (ret) { + dev_err(dev, "failed to initialize dispc: %d\n", ret); + return ret; + } + + pm_runtime_enable(dev); + +#ifndef CONFIG_PM + /* If we don't have PM, we need to call resume manually */ + dispc_runtime_resume(tidss->dispc); +#endif + + ret = tidss_modeset_init(tidss); + if (ret < 0) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to init DRM/KMS (%d)\n", ret); + goto err_runtime_suspend; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + ret = irq; + goto err_runtime_suspend; + } + + ret = drm_irq_install(ddev, irq); + if (ret) { + dev_err(dev, "drm_irq_install failed: %d\n", ret); + goto err_runtime_suspend; + } + + drm_kms_helper_poll_init(ddev); + + drm_mode_config_reset(ddev); + + ret = drm_dev_register(ddev, 0); + if (ret) { + dev_err(dev, "failed to register DRM device\n"); + goto err_irq_uninstall; + } + + drm_fbdev_generic_setup(ddev, 32); + + dev_dbg(dev, "%s done\n", __func__); + + return 0; + +err_irq_uninstall: + drm_irq_uninstall(ddev); + +err_runtime_suspend: +#ifndef CONFIG_PM + dispc_runtime_suspend(tidss->dispc); +#endif + pm_runtime_disable(dev); + + return ret; +} + +static int tidss_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct tidss_device *tidss = platform_get_drvdata(pdev); + struct drm_device *ddev = &tidss->ddev; + + dev_dbg(dev, "%s\n", __func__); + + drm_dev_unregister(ddev); + + drm_atomic_helper_shutdown(ddev); + + drm_irq_uninstall(ddev); + +#ifndef CONFIG_PM + /* If we don't have PM, we need to call suspend manually */ + dispc_runtime_suspend(tidss->dispc); +#endif + pm_runtime_disable(dev); + + /* devm allocated dispc goes away with the dev so mark it NULL */ + dispc_remove(tidss); + + dev_dbg(dev, "%s done\n", __func__); + + return 0; +} + +static void tidss_shutdown(struct platform_device *pdev) +{ + drm_atomic_helper_shutdown(platform_get_drvdata(pdev)); +} + +static const struct of_device_id tidss_of_table[] = { + { .compatible = "ti,k2g-dss", .data = &dispc_k2g_feats, }, + { .compatible = "ti,am65x-dss", .data = &dispc_am65x_feats, }, + { .compatible = "ti,j721e-dss", .data = &dispc_j721e_feats, }, + { } +}; + +MODULE_DEVICE_TABLE(of, tidss_of_table); + +static struct platform_driver tidss_platform_driver = { + .probe = tidss_probe, + .remove = tidss_remove, + .shutdown = tidss_shutdown, + .driver = { + .name = "tidss", +#ifdef CONFIG_PM + .pm = &tidss_pm_ops, +#endif + .of_match_table = tidss_of_table, + .suppress_bind_attrs = true, + }, +}; + +module_platform_driver(tidss_platform_driver); + +MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ti.com>"); +MODULE_DESCRIPTION("TI Keystone DSS Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tidss_drv.h new file mode 100644 index 000000000000..e2aa6436ad18 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_drv.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#ifndef __TIDSS_DRV_H__ +#define __TIDSS_DRV_H__ + +#include <linux/spinlock.h> + +#define TIDSS_MAX_PORTS 4 +#define TIDSS_MAX_PLANES 4 + +typedef u32 dispc_irq_t; + +struct tidss_device { + struct drm_device ddev; /* DRM device for DSS */ + struct device *dev; /* Underlying DSS device */ + + const struct dispc_features *feat; + struct dispc_device *dispc; + + unsigned int num_crtcs; + struct drm_crtc *crtcs[TIDSS_MAX_PORTS]; + + unsigned int num_planes; + struct drm_plane *planes[TIDSS_MAX_PLANES]; + + spinlock_t wait_lock; /* protects the irq masks */ + dispc_irq_t irq_mask; /* enabled irqs in addition to wait_list */ + + struct drm_atomic_state *saved_state; +}; + +int tidss_runtime_get(struct tidss_device *tidss); +void tidss_runtime_put(struct tidss_device *tidss); + +#endif diff --git a/drivers/gpu/drm/tidss/tidss_encoder.c b/drivers/gpu/drm/tidss/tidss_encoder.c new file mode 100644 index 000000000000..f7fe3a43ead0 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_encoder.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#include <linux/export.h> + +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_panel.h> +#include <drm/drm_of.h> + +#include "tidss_crtc.h" +#include "tidss_drv.h" +#include "tidss_encoder.h" + +static int tidss_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_device *ddev = encoder->dev; + struct tidss_crtc_state *tcrtc_state = to_tidss_crtc_state(crtc_state); + struct drm_display_info *di = &conn_state->connector->display_info; + struct drm_bridge *bridge; + bool bus_flags_set = false; + + dev_dbg(ddev->dev, "%s\n", __func__); + + /* + * Take the bus_flags from the first bridge that defines + * bridge timings, or from the connector's display_info if no + * bridge defines the timings. + */ + list_for_each_entry(bridge, &encoder->bridge_chain, chain_node) { + if (!bridge->timings) + continue; + + tcrtc_state->bus_flags = bridge->timings->input_bus_flags; + bus_flags_set = true; + break; + } + + if (!di->bus_formats || di->num_bus_formats == 0) { + dev_err(ddev->dev, "%s: No bus_formats in connected display\n", + __func__); + return -EINVAL; + } + + // XXX any cleaner way to set bus format and flags? + tcrtc_state->bus_format = di->bus_formats[0]; + if (!bus_flags_set) + tcrtc_state->bus_flags = di->bus_flags; + + return 0; +} + +static const struct drm_encoder_helper_funcs encoder_helper_funcs = { + .atomic_check = tidss_encoder_atomic_check, +}; + +static const struct drm_encoder_funcs encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss, + u32 encoder_type, u32 possible_crtcs) +{ + struct drm_encoder *enc; + int ret; + + enc = devm_kzalloc(tidss->dev, sizeof(*enc), GFP_KERNEL); + if (!enc) + return ERR_PTR(-ENOMEM); + + enc->possible_crtcs = possible_crtcs; + + ret = drm_encoder_init(&tidss->ddev, enc, &encoder_funcs, + encoder_type, NULL); + if (ret < 0) + return ERR_PTR(ret); + + drm_encoder_helper_add(enc, &encoder_helper_funcs); + + dev_dbg(tidss->dev, "Encoder create done\n"); + + return enc; +} diff --git a/drivers/gpu/drm/tidss/tidss_encoder.h b/drivers/gpu/drm/tidss/tidss_encoder.h new file mode 100644 index 000000000000..06854d66e7e6 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_encoder.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#ifndef __TIDSS_ENCODER_H__ +#define __TIDSS_ENCODER_H__ + +#include <drm/drm_encoder.h> + +struct tidss_device; + +struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss, + u32 encoder_type, u32 possible_crtcs); + +#endif diff --git a/drivers/gpu/drm/tidss/tidss_irq.c b/drivers/gpu/drm/tidss/tidss_irq.c new file mode 100644 index 000000000000..612c046738e5 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_irq.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#include <drm/drm_print.h> + +#include "tidss_crtc.h" +#include "tidss_dispc.h" +#include "tidss_drv.h" +#include "tidss_irq.h" +#include "tidss_plane.h" + +/* call with wait_lock and dispc runtime held */ +static void tidss_irq_update(struct tidss_device *tidss) +{ + assert_spin_locked(&tidss->wait_lock); + + dispc_set_irqenable(tidss->dispc, tidss->irq_mask); +} + +void tidss_irq_enable_vblank(struct drm_crtc *crtc) +{ + struct drm_device *ddev = crtc->dev; + struct tidss_device *tidss = ddev->dev_private; + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + u32 hw_videoport = tcrtc->hw_videoport; + unsigned long flags; + + spin_lock_irqsave(&tidss->wait_lock, flags); + tidss->irq_mask |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) | + DSS_IRQ_VP_VSYNC_ODD(hw_videoport); + tidss_irq_update(tidss); + spin_unlock_irqrestore(&tidss->wait_lock, flags); +} + +void tidss_irq_disable_vblank(struct drm_crtc *crtc) +{ + struct drm_device *ddev = crtc->dev; + struct tidss_device *tidss = ddev->dev_private; + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + u32 hw_videoport = tcrtc->hw_videoport; + unsigned long flags; + + spin_lock_irqsave(&tidss->wait_lock, flags); + tidss->irq_mask &= ~(DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) | + DSS_IRQ_VP_VSYNC_ODD(hw_videoport)); + tidss_irq_update(tidss); + spin_unlock_irqrestore(&tidss->wait_lock, flags); +} + +irqreturn_t tidss_irq_handler(int irq, void *arg) +{ + struct drm_device *ddev = (struct drm_device *)arg; + struct tidss_device *tidss = ddev->dev_private; + unsigned int id; + dispc_irq_t irqstatus; + + if (WARN_ON(!ddev->irq_enabled)) + return IRQ_NONE; + + irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); + + for (id = 0; id < tidss->num_crtcs; id++) { + struct drm_crtc *crtc = tidss->crtcs[id]; + struct tidss_crtc *tcrtc = to_tidss_crtc(crtc); + u32 hw_videoport = tcrtc->hw_videoport; + + if (irqstatus & (DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) | + DSS_IRQ_VP_VSYNC_ODD(hw_videoport))) + tidss_crtc_vblank_irq(crtc); + + if (irqstatus & (DSS_IRQ_VP_FRAME_DONE(hw_videoport))) + tidss_crtc_framedone_irq(crtc); + + if (irqstatus & DSS_IRQ_VP_SYNC_LOST(hw_videoport)) + tidss_crtc_error_irq(crtc, irqstatus); + } + + if (irqstatus & DSS_IRQ_DEVICE_OCP_ERR) + dev_err_ratelimited(tidss->dev, "OCP error\n"); + + return IRQ_HANDLED; +} + +void tidss_irq_resume(struct tidss_device *tidss) +{ + unsigned long flags; + + spin_lock_irqsave(&tidss->wait_lock, flags); + tidss_irq_update(tidss); + spin_unlock_irqrestore(&tidss->wait_lock, flags); +} + +void tidss_irq_preinstall(struct drm_device *ddev) +{ + struct tidss_device *tidss = ddev->dev_private; + + spin_lock_init(&tidss->wait_lock); + + tidss_runtime_get(tidss); + + dispc_set_irqenable(tidss->dispc, 0); + dispc_read_and_clear_irqstatus(tidss->dispc); + + tidss_runtime_put(tidss); +} + +int tidss_irq_postinstall(struct drm_device *ddev) +{ + struct tidss_device *tidss = ddev->dev_private; + unsigned long flags; + unsigned int i; + + tidss_runtime_get(tidss); + + spin_lock_irqsave(&tidss->wait_lock, flags); + + tidss->irq_mask = DSS_IRQ_DEVICE_OCP_ERR; + + for (i = 0; i < tidss->num_crtcs; ++i) { + struct tidss_crtc *tcrtc = to_tidss_crtc(tidss->crtcs[i]); + + tidss->irq_mask |= DSS_IRQ_VP_SYNC_LOST(tcrtc->hw_videoport); + + tidss->irq_mask |= DSS_IRQ_VP_FRAME_DONE(tcrtc->hw_videoport); + } + + tidss_irq_update(tidss); + + spin_unlock_irqrestore(&tidss->wait_lock, flags); + + tidss_runtime_put(tidss); + + return 0; +} + +void tidss_irq_uninstall(struct drm_device *ddev) +{ + struct tidss_device *tidss = ddev->dev_private; + + tidss_runtime_get(tidss); + dispc_set_irqenable(tidss->dispc, 0); + tidss_runtime_put(tidss); +} diff --git a/drivers/gpu/drm/tidss/tidss_irq.h b/drivers/gpu/drm/tidss/tidss_irq.h new file mode 100644 index 000000000000..aa92db403cca --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_irq.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#ifndef __TIDSS_IRQ_H__ +#define __TIDSS_IRQ_H__ + +#include <linux/types.h> + +#include "tidss_drv.h" + +/* + * The IRQ status from various DISPC IRQ registers are packed into a single + * value, where the bits are defined as follows: + * + * bit group |dev|wb |mrg0|mrg1|mrg2|mrg3|plane0-3| <unused> | + * bit use |D |fou|FEOL|FEOL|FEOL|FEOL| UUUU | | + * bit number|0 |1-3|4-7 |8-11| 12-19 | 20-23 | 24-31 | + * + * device bits: D = OCP error + * WB bits: f = frame done wb, o = wb buffer overflow, + * u = wb buffer uncomplete + * vp bits: F = frame done, E = vsync even, O = vsync odd, L = sync lost + * plane bits: U = fifo underflow + */ + +#define DSS_IRQ_DEVICE_OCP_ERR BIT(0) + +#define DSS_IRQ_DEVICE_FRAMEDONEWB BIT(1) +#define DSS_IRQ_DEVICE_WBBUFFEROVERFLOW BIT(2) +#define DSS_IRQ_DEVICE_WBUNCOMPLETEERROR BIT(3) +#define DSS_IRQ_DEVICE_WB_MASK GENMASK(3, 1) + +#define DSS_IRQ_VP_BIT_N(ch, bit) (4 + 4 * (ch) + (bit)) +#define DSS_IRQ_PLANE_BIT_N(plane, bit) \ + (DSS_IRQ_VP_BIT_N(TIDSS_MAX_PORTS, 0) + 1 * (plane) + (bit)) + +#define DSS_IRQ_VP_BIT(ch, bit) BIT(DSS_IRQ_VP_BIT_N((ch), (bit))) +#define DSS_IRQ_PLANE_BIT(plane, bit) \ + BIT(DSS_IRQ_PLANE_BIT_N((plane), (bit))) + +static inline dispc_irq_t DSS_IRQ_VP_MASK(u32 ch) +{ + return GENMASK(DSS_IRQ_VP_BIT_N((ch), 3), DSS_IRQ_VP_BIT_N((ch), 0)); +} + +static inline dispc_irq_t DSS_IRQ_PLANE_MASK(u32 plane) +{ + return GENMASK(DSS_IRQ_PLANE_BIT_N((plane), 0), + DSS_IRQ_PLANE_BIT_N((plane), 0)); +} + +#define DSS_IRQ_VP_FRAME_DONE(ch) DSS_IRQ_VP_BIT((ch), 0) +#define DSS_IRQ_VP_VSYNC_EVEN(ch) DSS_IRQ_VP_BIT((ch), 1) +#define DSS_IRQ_VP_VSYNC_ODD(ch) DSS_IRQ_VP_BIT((ch), 2) +#define DSS_IRQ_VP_SYNC_LOST(ch) DSS_IRQ_VP_BIT((ch), 3) + +#define DSS_IRQ_PLANE_FIFO_UNDERFLOW(plane) DSS_IRQ_PLANE_BIT((plane), 0) + +struct drm_crtc; +struct drm_device; + +struct tidss_device; + +void tidss_irq_enable_vblank(struct drm_crtc *crtc); +void tidss_irq_disable_vblank(struct drm_crtc *crtc); + +void tidss_irq_preinstall(struct drm_device *ddev); +int tidss_irq_postinstall(struct drm_device *ddev); +void tidss_irq_uninstall(struct drm_device *ddev); +irqreturn_t tidss_irq_handler(int irq, void *arg); + +void tidss_irq_resume(struct tidss_device *tidss); + +#endif diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c new file mode 100644 index 000000000000..5311e0f1c551 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_kms.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_bridge.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> +#include <drm/drm_of.h> +#include <drm/drm_panel.h> +#include <drm/drm_vblank.h> + +#include "tidss_crtc.h" +#include "tidss_dispc.h" +#include "tidss_drv.h" +#include "tidss_encoder.h" +#include "tidss_kms.h" +#include "tidss_plane.h" + +static void tidss_atomic_commit_tail(struct drm_atomic_state *old_state) +{ + struct drm_device *ddev = old_state->dev; + struct tidss_device *tidss = ddev->dev_private; + + dev_dbg(ddev->dev, "%s\n", __func__); + + tidss_runtime_get(tidss); + + drm_atomic_helper_commit_modeset_disables(ddev, old_state); + drm_atomic_helper_commit_planes(ddev, old_state, 0); + drm_atomic_helper_commit_modeset_enables(ddev, old_state); + + drm_atomic_helper_commit_hw_done(old_state); + drm_atomic_helper_wait_for_flip_done(ddev, old_state); + + drm_atomic_helper_cleanup_planes(ddev, old_state); + + tidss_runtime_put(tidss); +} + +static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { + .atomic_commit_tail = tidss_atomic_commit_tail, +}; + +static const struct drm_mode_config_funcs mode_config_funcs = { + .fb_create = drm_gem_fb_create, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, +}; + +static int tidss_dispc_modeset_init(struct tidss_device *tidss) +{ + struct device *dev = tidss->dev; + unsigned int fourccs_len; + const u32 *fourccs = dispc_plane_formats(tidss->dispc, &fourccs_len); + unsigned int i; + + struct pipe { + u32 hw_videoport; + struct drm_bridge *bridge; + u32 enc_type; + }; + + const struct dispc_features *feat = tidss->feat; + u32 max_vps = feat->num_vps; + u32 max_planes = feat->num_planes; + + struct pipe pipes[TIDSS_MAX_PORTS]; + u32 num_pipes = 0; + u32 crtc_mask; + + /* first find all the connected panels & bridges */ + + for (i = 0; i < max_vps; i++) { + struct drm_panel *panel; + struct drm_bridge *bridge; + u32 enc_type = DRM_MODE_ENCODER_NONE; + int ret; + + ret = drm_of_find_panel_or_bridge(dev->of_node, i, 0, + &panel, &bridge); + if (ret == -ENODEV) { + dev_dbg(dev, "no panel/bridge for port %d\n", i); + continue; + } else if (ret) { + dev_dbg(dev, "port %d probe returned %d\n", i, ret); + return ret; + } + + if (panel) { + u32 conn_type; + + dev_dbg(dev, "Setting up panel for port %d\n", i); + + switch (feat->vp_bus_type[i]) { + case DISPC_VP_OLDI: + enc_type = DRM_MODE_ENCODER_LVDS; + conn_type = DRM_MODE_CONNECTOR_LVDS; + break; + case DISPC_VP_DPI: + enc_type = DRM_MODE_ENCODER_DPI; + conn_type = DRM_MODE_CONNECTOR_LVDS; + break; + default: + WARN_ON(1); + return -EINVAL; + } + + if (panel->connector_type != conn_type) { + dev_err(dev, + "%s: Panel %s has incompatible connector type for vp%d (%d != %d)\n", + __func__, dev_name(panel->dev), i, + panel->connector_type, conn_type); + return -EINVAL; + } + + bridge = devm_drm_panel_bridge_add(dev, panel); + if (IS_ERR(bridge)) { + dev_err(dev, + "failed to set up panel bridge for port %d\n", + i); + return PTR_ERR(bridge); + } + } + + pipes[num_pipes].hw_videoport = i; + pipes[num_pipes].bridge = bridge; + pipes[num_pipes].enc_type = enc_type; + num_pipes++; + } + + /* all planes can be on any crtc */ + crtc_mask = (1 << num_pipes) - 1; + + /* then create a plane, a crtc and an encoder for each panel/bridge */ + + for (i = 0; i < num_pipes; ++i) { + struct tidss_plane *tplane; + struct tidss_crtc *tcrtc; + struct drm_encoder *enc; + u32 hw_plane_id = feat->vid_order[tidss->num_planes]; + int ret; + + tplane = tidss_plane_create(tidss, hw_plane_id, + DRM_PLANE_TYPE_PRIMARY, crtc_mask, + fourccs, fourccs_len); + if (IS_ERR(tplane)) { + dev_err(tidss->dev, "plane create failed\n"); + return PTR_ERR(tplane); + } + + tidss->planes[tidss->num_planes++] = &tplane->plane; + + tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, + &tplane->plane); + if (IS_ERR(tcrtc)) { + dev_err(tidss->dev, "crtc create failed\n"); + return PTR_ERR(tcrtc); + } + + tidss->crtcs[tidss->num_crtcs++] = &tcrtc->crtc; + + enc = tidss_encoder_create(tidss, pipes[i].enc_type, + 1 << tcrtc->crtc.index); + if (IS_ERR(enc)) { + dev_err(tidss->dev, "encoder create failed\n"); + return PTR_ERR(enc); + } + + ret = drm_bridge_attach(enc, pipes[i].bridge, NULL); + if (ret) { + dev_err(tidss->dev, "bridge attach failed: %d\n", ret); + return ret; + } + } + + /* create overlay planes of the leftover planes */ + + while (tidss->num_planes < max_planes) { + struct tidss_plane *tplane; + u32 hw_plane_id = feat->vid_order[tidss->num_planes]; + + tplane = tidss_plane_create(tidss, hw_plane_id, + DRM_PLANE_TYPE_OVERLAY, crtc_mask, + fourccs, fourccs_len); + + if (IS_ERR(tplane)) { + dev_err(tidss->dev, "plane create failed\n"); + return PTR_ERR(tplane); + } + + tidss->planes[tidss->num_planes++] = &tplane->plane; + } + + return 0; +} + +int tidss_modeset_init(struct tidss_device *tidss) +{ + struct drm_device *ddev = &tidss->ddev; + unsigned int i; + int ret; + + dev_dbg(tidss->dev, "%s\n", __func__); + + drm_mode_config_init(ddev); + + ddev->mode_config.min_width = 8; + ddev->mode_config.min_height = 8; + ddev->mode_config.max_width = 8096; + ddev->mode_config.max_height = 8096; + ddev->mode_config.normalize_zpos = true; + ddev->mode_config.funcs = &mode_config_funcs; + ddev->mode_config.helper_private = &mode_config_helper_funcs; + + ret = tidss_dispc_modeset_init(tidss); + if (ret) + goto err_mode_config_cleanup; + + ret = drm_vblank_init(ddev, tidss->num_crtcs); + if (ret) + goto err_mode_config_cleanup; + + /* Start with vertical blanking interrupt reporting disabled. */ + for (i = 0; i < tidss->num_crtcs; ++i) + drm_crtc_vblank_reset(tidss->crtcs[i]); + + drm_mode_config_reset(ddev); + + dev_dbg(tidss->dev, "%s done\n", __func__); + + return 0; + +err_mode_config_cleanup: + drm_mode_config_cleanup(ddev); + return ret; +} + +void tidss_modeset_cleanup(struct tidss_device *tidss) +{ + struct drm_device *ddev = &tidss->ddev; + + drm_mode_config_cleanup(ddev); +} diff --git a/drivers/gpu/drm/tidss/tidss_kms.h b/drivers/gpu/drm/tidss/tidss_kms.h new file mode 100644 index 000000000000..dda5625d0128 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_kms.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#ifndef __TIDSS_KMS_H__ +#define __TIDSS_KMS_H__ + +struct tidss_device; + +int tidss_modeset_init(struct tidss_device *tidss); +void tidss_modeset_cleanup(struct tidss_device *tidss); + +#endif diff --git a/drivers/gpu/drm/tidss/tidss_plane.c b/drivers/gpu/drm/tidss/tidss_plane.c new file mode 100644 index 000000000000..ff99b2dd4a17 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_plane.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_fb_cma_helper.h> + +#include "tidss_crtc.h" +#include "tidss_dispc.h" +#include "tidss_drv.h" +#include "tidss_plane.h" + +/* drm_plane_helper_funcs */ + +static int tidss_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct drm_device *ddev = plane->dev; + struct tidss_device *tidss = ddev->dev_private; + struct tidss_plane *tplane = to_tidss_plane(plane); + const struct drm_format_info *finfo; + struct drm_crtc_state *crtc_state; + u32 hw_plane = tplane->hw_plane_id; + u32 hw_videoport; + int ret; + + dev_dbg(ddev->dev, "%s\n", __func__); + + if (!state->crtc) { + /* + * The visible field is not reset by the DRM core but only + * updated by drm_plane_helper_check_state(), set it manually. + */ + state->visible = false; + return 0; + } + + crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + ret = drm_atomic_helper_check_plane_state(state, crtc_state, 0, + INT_MAX, true, true); + if (ret < 0) + return ret; + + /* + * The HW is only able to start drawing at subpixel boundary + * (the two first checks bellow). At the end of a row the HW + * can only jump integer number of subpixels forward to the + * beginning of the next row. So we can only show picture with + * integer subpixel width (the third check). However, after + * reaching the end of the drawn picture the drawing starts + * again at the absolute memory address where top left corner + * position of the drawn picture is (so there is no need to + * check for odd height). + */ + + finfo = drm_format_info(state->fb->format->format); + + if ((state->src_x >> 16) % finfo->hsub != 0) { + dev_dbg(ddev->dev, + "%s: x-position %u not divisible subpixel size %u\n", + __func__, (state->src_x >> 16), finfo->hsub); + return -EINVAL; + } + + if ((state->src_y >> 16) % finfo->vsub != 0) { + dev_dbg(ddev->dev, + "%s: y-position %u not divisible subpixel size %u\n", + __func__, (state->src_y >> 16), finfo->vsub); + return -EINVAL; + } + + if ((state->src_w >> 16) % finfo->hsub != 0) { + dev_dbg(ddev->dev, + "%s: src width %u not divisible by subpixel size %u\n", + __func__, (state->src_w >> 16), finfo->hsub); + return -EINVAL; + } + + if (!state->visible) + return 0; + + hw_videoport = to_tidss_crtc(state->crtc)->hw_videoport; + + ret = dispc_plane_check(tidss->dispc, hw_plane, state, hw_videoport); + if (ret) + return ret; + + return 0; +} + +static void tidss_plane_atomic_update(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct drm_device *ddev = plane->dev; + struct tidss_device *tidss = ddev->dev_private; + struct tidss_plane *tplane = to_tidss_plane(plane); + struct drm_plane_state *state = plane->state; + u32 hw_videoport; + int ret; + + dev_dbg(ddev->dev, "%s\n", __func__); + + if (!state->visible) { + dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); + return; + } + + hw_videoport = to_tidss_crtc(state->crtc)->hw_videoport; + + ret = dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, + state, hw_videoport); + + if (ret) { + dev_err(plane->dev->dev, "%s: Failed to setup plane %d\n", + __func__, tplane->hw_plane_id); + dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); + return; + } + + dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true); +} + +static void tidss_plane_atomic_disable(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct drm_device *ddev = plane->dev; + struct tidss_device *tidss = ddev->dev_private; + struct tidss_plane *tplane = to_tidss_plane(plane); + + dev_dbg(ddev->dev, "%s\n", __func__); + + dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); +} + +static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = { + .atomic_check = tidss_plane_atomic_check, + .atomic_update = tidss_plane_atomic_update, + .atomic_disable = tidss_plane_atomic_disable, +}; + +static const struct drm_plane_funcs tidss_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .reset = drm_atomic_helper_plane_reset, + .destroy = drm_plane_cleanup, + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, +}; + +struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, + u32 hw_plane_id, u32 plane_type, + u32 crtc_mask, const u32 *formats, + u32 num_formats) +{ + struct tidss_plane *tplane; + enum drm_plane_type type; + u32 possible_crtcs; + u32 num_planes = tidss->feat->num_planes; + u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) | + BIT(DRM_COLOR_YCBCR_BT709)); + u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) | + BIT(DRM_COLOR_YCBCR_LIMITED_RANGE)); + u32 default_encoding = DRM_COLOR_YCBCR_BT601; + u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE; + u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE)); + int ret; + + tplane = devm_kzalloc(tidss->dev, sizeof(*tplane), GFP_KERNEL); + if (!tplane) + return ERR_PTR(-ENOMEM); + + tplane->hw_plane_id = hw_plane_id; + + possible_crtcs = crtc_mask; + type = plane_type; + + ret = drm_universal_plane_init(&tidss->ddev, &tplane->plane, + possible_crtcs, + &tidss_plane_funcs, + formats, num_formats, + NULL, type, NULL); + if (ret < 0) + return ERR_PTR(ret); + + drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs); + + drm_plane_create_zpos_property(&tplane->plane, hw_plane_id, 0, + num_planes - 1); + + ret = drm_plane_create_color_properties(&tplane->plane, + color_encodings, + color_ranges, + default_encoding, + default_range); + if (ret) + return ERR_PTR(ret); + + ret = drm_plane_create_alpha_property(&tplane->plane); + if (ret) + return ERR_PTR(ret); + + ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes); + if (ret) + return ERR_PTR(ret); + + return tplane; +} diff --git a/drivers/gpu/drm/tidss/tidss_plane.h b/drivers/gpu/drm/tidss/tidss_plane.h new file mode 100644 index 000000000000..80ff1c5a2535 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_plane.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#ifndef __TIDSS_PLANE_H__ +#define __TIDSS_PLANE_H__ + +#define to_tidss_plane(p) container_of((p), struct tidss_plane, plane) + +struct tidss_device; + +struct tidss_plane { + struct drm_plane plane; + + u32 hw_plane_id; +}; + +struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, + u32 hw_plane_id, u32 plane_type, + u32 crtc_mask, const u32 *formats, + u32 num_formats); + +#endif diff --git a/drivers/gpu/drm/tidss/tidss_scale_coefs.c b/drivers/gpu/drm/tidss/tidss_scale_coefs.c new file mode 100644 index 000000000000..5ec68389cc68 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_scale_coefs.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Jyri Sarha <jsarha@ti.com> + */ + +#include <linux/device.h> +#include <linux/kernel.h> + +#include "tidss_scale_coefs.h" + +/* + * These are interpolated with a custom python script from DSS5 + * (drivers/gpu/drm/omapdrm/dss/dispc_coef.c) coefficients. + */ +static const struct tidss_scale_coefs coef5_m32 = { + .c2 = { 28, 34, 40, 46, 52, 58, 64, 70, 0, 2, 4, 8, 12, 16, 20, 24, }, + .c1 = { 132, 138, 144, 150, 156, 162, 168, 174, 76, 84, 92, 98, 104, 110, 116, 124, }, + .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, }, +}; + +static const struct tidss_scale_coefs coef5_m26 = { + .c2 = { 24, 28, 32, 38, 44, 50, 56, 64, 0, 2, 4, 6, 8, 12, 16, 20, }, + .c1 = { 132, 138, 144, 152, 160, 166, 172, 178, 72, 80, 88, 94, 100, 108, 116, 124, }, + .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, }, +}; + +static const struct tidss_scale_coefs coef5_m22 = { + .c2 = { 16, 20, 24, 30, 36, 42, 48, 56, 0, 0, 0, 2, 4, 8, 12, 14, }, + .c1 = { 132, 140, 148, 156, 164, 172, 180, 186, 64, 72, 80, 88, 96, 104, 112, 122, }, + .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, }, +}; + +static const struct tidss_scale_coefs coef5_m19 = { + .c2 = { 12, 14, 16, 22, 28, 34, 40, 48, 0, 0, 0, 2, 4, 4, 4, 8, }, + .c1 = { 128, 140, 152, 160, 168, 176, 184, 192, 56, 64, 72, 82, 92, 100, 108, 118, }, + .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, }, +}; + +static const struct tidss_scale_coefs coef5_m16 = { + .c2 = { 0, 2, 4, 8, 12, 18, 24, 32, 0, 0, 0, -2, -4, -4, -4, -2, }, + .c1 = { 124, 138, 152, 164, 176, 186, 196, 206, 40, 48, 56, 68, 80, 90, 100, 112, }, + .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, }, +}; + +static const struct tidss_scale_coefs coef5_m14 = { + .c2 = { -8, -6, -4, -2, 0, 6, 12, 18, 0, -2, -4, -6, -8, -8, -8, -8, }, + .c1 = { 120, 134, 148, 164, 180, 194, 208, 220, 24, 32, 40, 52, 64, 78, 92, 106, }, + .c0 = { 288, 286, 284, 280, 276, 266, 256, 244, 232, }, +}; + +static const struct tidss_scale_coefs coef5_m13 = { + .c2 = { -12, -12, -12, -10, -8, -4, 0, 6, 0, -2, -4, -6, -8, -10, -12, -12, }, + .c1 = { 112, 130, 148, 164, 180, 196, 212, 228, 12, 22, 32, 44, 56, 70, 84, 98, }, + .c0 = { 312, 308, 304, 298, 292, 282, 272, 258, 244, }, +}; + +static const struct tidss_scale_coefs coef5_m12 = { + .c2 = { -16, -18, -20, -18, -16, -14, -12, -6, 0, -2, -4, -6, -8, -10, -12, -14, }, + .c1 = { 104, 124, 144, 164, 184, 202, 220, 238, 0, 10, 20, 30, 40, 56, 72, 88, }, + .c0 = { 336, 332, 328, 320, 312, 300, 288, 272, 256, }, +}; + +static const struct tidss_scale_coefs coef5_m11 = { + .c2 = { -20, -22, -24, -24, -24, -24, -24, -20, 0, -2, -4, -6, -8, -10, -12, -16, }, + .c1 = { 92, 114, 136, 158, 180, 204, 228, 250, -16, -8, 0, 12, 24, 38, 52, 72, }, + .c0 = { 368, 364, 360, 350, 340, 326, 312, 292, 272, }, +}; + +static const struct tidss_scale_coefs coef5_m10 = { + .c2 = { -16, -20, -24, -28, -32, -34, -36, -34, 0, 0, 0, -2, -4, -8, -12, -14, }, + .c1 = { 72, 96, 120, 148, 176, 204, 232, 260, -32, -26, -20, -10, 0, 16, 32, 52, }, + .c0 = { 400, 398, 396, 384, 372, 354, 336, 312, 288, }, +}; + +static const struct tidss_scale_coefs coef5_m9 = { + .c2 = { -12, -18, -24, -28, -32, -38, -44, -46, 0, 2, 4, 2, 0, -2, -4, -8, }, + .c1 = { 40, 68, 96, 128, 160, 196, 232, 268, -48, -46, -44, -36, -28, -14, 0, 20, }, + .c0 = { 456, 450, 444, 428, 412, 388, 364, 334, 304, }, +}; + +static const struct tidss_scale_coefs coef5_m8 = { + .c2 = { 0, -4, -8, -16, -24, -32, -40, -48, 0, 2, 4, 6, 8, 6, 4, 2, }, + .c1 = { 0, 28, 56, 94, 132, 176, 220, 266, -56, -60, -64, -62, -60, -50, -40, -20, }, + .c0 = { 512, 506, 500, 478, 456, 424, 392, 352, 312, }, +}; + +static const struct tidss_scale_coefs coef3_m32 = { + .c1 = { 108, 92, 76, 62, 48, 36, 24, 140, 256, 236, 216, 198, 180, 162, 144, 126, }, + .c0 = { 296, 294, 292, 288, 284, 278, 272, 136, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m26 = { + .c1 = { 104, 90, 76, 60, 44, 32, 20, 138, 256, 236, 216, 198, 180, 160, 140, 122, }, + .c0 = { 304, 300, 296, 292, 288, 282, 276, 138, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m22 = { + .c1 = { 100, 84, 68, 54, 40, 30, 20, 138, 256, 236, 216, 196, 176, 156, 136, 118, }, + .c0 = { 312, 310, 308, 302, 296, 286, 276, 138, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m19 = { + .c1 = { 96, 80, 64, 50, 36, 26, 16, 136, 256, 236, 216, 194, 172, 152, 132, 114, }, + .c0 = { 320, 318, 316, 310, 304, 292, 280, 140, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m16 = { + .c1 = { 88, 72, 56, 44, 32, 22, 12, 134, 256, 234, 212, 190, 168, 148, 128, 108, }, + .c0 = { 336, 332, 328, 320, 312, 300, 288, 144, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m14 = { + .c1 = { 80, 64, 48, 36, 24, 16, 8, 132, 256, 232, 208, 186, 164, 142, 120, 100, }, + .c0 = { 352, 348, 344, 334, 324, 310, 296, 148, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m13 = { + .c1 = { 72, 56, 40, 30, 20, 12, 4, 130, 256, 232, 208, 184, 160, 136, 112, 92, }, + .c0 = { 368, 364, 360, 346, 332, 316, 300, 150, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m12 = { + .c1 = { 64, 50, 36, 26, 16, 10, 4, 130, 256, 230, 204, 178, 152, 128, 104, 84, }, + .c0 = { 384, 378, 372, 358, 344, 324, 304, 152, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m11 = { + .c1 = { 56, 40, 24, 16, 8, 4, 0, 128, 256, 228, 200, 172, 144, 120, 96, 76, }, + .c0 = { 400, 396, 392, 376, 360, 336, 312, 156, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m10 = { + .c1 = { 40, 26, 12, 6, 0, -2, -4, 126, 256, 226, 196, 166, 136, 110, 84, 62, }, + .c0 = { 432, 424, 416, 396, 376, 348, 320, 160, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m9 = { + .c1 = { 24, 12, 0, -4, -8, -8, -8, 124, 256, 222, 188, 154, 120, 92, 64, 44, }, + .c0 = { 464, 456, 448, 424, 400, 366, 332, 166, 256, }, +}; + +static const struct tidss_scale_coefs coef3_m8 = { + .c1 = { 0, -8, -16, -16, -16, -12, -8, 124, 256, 214, 172, 134, 96, 66, 36, 18, }, + .c0 = { 512, 502, 492, 462, 432, 390, 348, 174, 256, }, +}; + +const struct tidss_scale_coefs *tidss_get_scale_coefs(struct device *dev, + u32 firinc, + bool five_taps) +{ + int i; + int inc; + static const struct { + int mmin; + int mmax; + const struct tidss_scale_coefs *coef3; + const struct tidss_scale_coefs *coef5; + const char *name; + } coefs[] = { + { 27, 32, &coef3_m32, &coef5_m32, "M32" }, + { 23, 26, &coef3_m26, &coef5_m26, "M26" }, + { 20, 22, &coef3_m22, &coef5_m22, "M22" }, + { 17, 19, &coef3_m19, &coef5_m19, "M19" }, + { 15, 16, &coef3_m16, &coef5_m16, "M16" }, + { 14, 14, &coef3_m14, &coef5_m14, "M14" }, + { 13, 13, &coef3_m13, &coef5_m13, "M13" }, + { 12, 12, &coef3_m12, &coef5_m12, "M12" }, + { 11, 11, &coef3_m11, &coef5_m11, "M11" }, + { 10, 10, &coef3_m10, &coef5_m10, "M10" }, + { 9, 9, &coef3_m9, &coef5_m9, "M9" }, + { 4, 8, &coef3_m8, &coef5_m8, "M8" }, + /* + * When upscaling more than two times, blockiness and outlines + * around the image are observed when M8 tables are used. M11, + * M16 and M19 tables are used to prevent this. + */ + { 3, 3, &coef3_m11, &coef5_m11, "M11" }, + { 2, 2, &coef3_m16, &coef5_m16, "M16" }, + { 0, 1, &coef3_m19, &coef5_m19, "M19" }, + }; + + /* + * inc is result of 0x200000 * in_size / out_size. This dividing + * by 0x40000 scales it down to 8 * in_size / out_size. After + * division the actual scaling factor is 8/inc. + */ + inc = firinc / 0x40000; + for (i = 0; i < ARRAY_SIZE(coefs); ++i) { + if (inc >= coefs[i].mmin && inc <= coefs[i].mmax) { + if (five_taps) + return coefs[i].coef5; + else + return coefs[i].coef3; + } + } + + dev_err(dev, "%s: Coefficients not found for firinc 0x%08x, inc %d\n", + __func__, firinc, inc); + + return NULL; +} diff --git a/drivers/gpu/drm/tidss/tidss_scale_coefs.h b/drivers/gpu/drm/tidss/tidss_scale_coefs.h new file mode 100644 index 000000000000..64b5af5b5361 --- /dev/null +++ b/drivers/gpu/drm/tidss/tidss_scale_coefs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Author: Jyri Sarha <jsarha@ti.com> + */ + +#ifndef __TIDSS_DISPC_COEF_H__ +#define __TIDSS_DISPC_COEF_H__ + +#include <linux/types.h> + +struct tidss_scale_coefs { + s16 c2[16]; + s16 c1[16]; + u16 c0[9]; +}; + +const struct tidss_scale_coefs *tidss_get_scale_coefs(struct device *dev, + u32 firinc, + bool five_taps); + +#endif diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index c18a28df6e2c..0791a0200cc3 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -249,7 +249,7 @@ static int tilcdc_init(struct drm_driver *ddrv, struct device *dev) goto init_failed; } - priv->mmio = ioremap_nocache(res->start, resource_size(res)); + priv->mmio = ioremap(res->start, resource_size(res)); if (!priv->mmio) { dev_err(dev, "failed to ioremap\n"); ret = -ENOMEM; diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig index a46ac284dd5e..4160e74e4751 100644 --- a/drivers/gpu/drm/tiny/Kconfig +++ b/drivers/gpu/drm/tiny/Kconfig @@ -47,6 +47,20 @@ config TINYDRM_ILI9341 If M is selected the module will be called ili9341. +config TINYDRM_ILI9486 + tristate "DRM support for ILI9486 display panels" + depends on DRM && SPI + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_MIPI_DBI + select BACKLIGHT_CLASS_DEVICE + help + DRM driver for the following Ilitek ILI9486 panels: + * PISCREEN 3.5" 320x480 TFT (Ozzmaker 3.5") + * RPILCD 3.5" 320x480 TFT (Waveshare 3.5") + + If M is selected the module will be called ili9486. + config TINYDRM_MI0283QT tristate "DRM support for MI0283QT" depends on DRM && SPI @@ -85,14 +99,16 @@ config TINYDRM_ST7586 If M is selected the module will be called st7586. config TINYDRM_ST7735R - tristate "DRM support for Sitronix ST7735R display panels" + tristate "DRM support for Sitronix ST7715R/ST7735R display panels" depends on DRM && SPI select DRM_KMS_HELPER select DRM_KMS_CMA_HELPER select DRM_MIPI_DBI select BACKLIGHT_CLASS_DEVICE help - DRM driver Sitronix ST7735R with one of the following LCDs: - * JD-T18003-T01 1.8" 128x160 TFT + DRM driver for Sitronix ST7715R/ST7735R with one of the following + LCDs: + * Jianda JD-T18003-T01 1.8" 128x160 TFT + * Okaya RH128128T 1.44" 128x128 TFT If M is selected the module will be called st7735r. diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile index 896cf31132d3..c96ceee71453 100644 --- a/drivers/gpu/drm/tiny/Makefile +++ b/drivers/gpu/drm/tiny/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_DRM_GM12U320) += gm12u320.o obj-$(CONFIG_TINYDRM_HX8357D) += hx8357d.o obj-$(CONFIG_TINYDRM_ILI9225) += ili9225.o obj-$(CONFIG_TINYDRM_ILI9341) += ili9341.o +obj-$(CONFIG_TINYDRM_ILI9486) += ili9486.o obj-$(CONFIG_TINYDRM_MI0283QT) += mi0283qt.o obj-$(CONFIG_TINYDRM_REPAPER) += repaper.o obj-$(CONFIG_TINYDRM_ST7586) += st7586.o diff --git a/drivers/gpu/drm/tiny/gm12u320.c b/drivers/gpu/drm/tiny/gm12u320.c index 94fb1f593564..a48173441ae0 100644 --- a/drivers/gpu/drm/tiny/gm12u320.c +++ b/drivers/gpu/drm/tiny/gm12u320.c @@ -22,7 +22,6 @@ #include <drm/drm_modeset_helper_vtables.h> #include <drm/drm_probe_helper.h> #include <drm/drm_simple_kms_helper.h> -#include <drm/drm_vblank.h> static bool eco_mode; module_param(eco_mode, bool, 0644); @@ -610,18 +609,10 @@ static void gm12u320_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *old_state) { struct drm_plane_state *state = pipe->plane.state; - struct drm_crtc *crtc = &pipe->crtc; struct drm_rect rect; if (drm_atomic_helper_damage_merged(old_state, state, &rect)) gm12u320_fb_mark_dirty(pipe->plane.state->fb, &rect); - - if (crtc->state->event) { - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, crtc->state->event); - crtc->state->event = NULL; - spin_unlock_irq(&crtc->dev->event_lock); - } } static const struct drm_simple_display_pipe_funcs gm12u320_pipe_funcs = { diff --git a/drivers/gpu/drm/tiny/ili9225.c b/drivers/gpu/drm/tiny/ili9225.c index c66acc566c2b..802fb8dde1b6 100644 --- a/drivers/gpu/drm/tiny/ili9225.c +++ b/drivers/gpu/drm/tiny/ili9225.c @@ -26,7 +26,6 @@ #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_mipi_dbi.h> #include <drm/drm_rect.h> -#include <drm/drm_vblank.h> #define ILI9225_DRIVER_READ_CODE 0x00 #define ILI9225_DRIVER_OUTPUT_CONTROL 0x01 @@ -165,18 +164,10 @@ static void ili9225_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *old_state) { struct drm_plane_state *state = pipe->plane.state; - struct drm_crtc *crtc = &pipe->crtc; struct drm_rect rect; if (drm_atomic_helper_damage_merged(old_state, state, &rect)) ili9225_fb_dirty(state->fb, &rect); - - if (crtc->state->event) { - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, crtc->state->event); - spin_unlock_irq(&crtc->dev->event_lock); - crtc->state->event = NULL; - } } static void ili9225_pipe_enable(struct drm_simple_display_pipe *pipe, diff --git a/drivers/gpu/drm/tiny/ili9486.c b/drivers/gpu/drm/tiny/ili9486.c new file mode 100644 index 000000000000..5084b38c1a71 --- /dev/null +++ b/drivers/gpu/drm/tiny/ili9486.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DRM driver for Ilitek ILI9486 panels + * + * Copyright 2020 Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com> + */ + +#include <linux/backlight.h> +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/property.h> +#include <linux/spi/spi.h> + +#include <video/mipi_display.h> + +#include <drm/drm_atomic_helper.h> +#include <drm/drm_drv.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> +#include <drm/drm_mipi_dbi.h> +#include <drm/drm_modeset_helper.h> + +#define ILI9486_ITFCTR1 0xb0 +#define ILI9486_PWCTRL1 0xc2 +#define ILI9486_VMCTRL1 0xc5 +#define ILI9486_PGAMCTRL 0xe0 +#define ILI9486_NGAMCTRL 0xe1 +#define ILI9486_DGAMCTRL 0xe2 +#define ILI9486_MADCTL_BGR BIT(3) +#define ILI9486_MADCTL_MV BIT(5) +#define ILI9486_MADCTL_MX BIT(6) +#define ILI9486_MADCTL_MY BIT(7) + +/* + * The PiScreen/waveshare rpi-lcd-35 has a SPI to 16-bit parallel bus converter + * in front of the display controller. This means that 8-bit values have to be + * transferred as 16-bit. + */ +static int waveshare_command(struct mipi_dbi *mipi, u8 *cmd, u8 *par, + size_t num) +{ + struct spi_device *spi = mipi->spi; + void *data = par; + u32 speed_hz; + int i, ret; + u16 *buf; + + buf = kmalloc(32 * sizeof(u16), GFP_KERNEL); + if (!buf) + return -ENOMEM; + + /* + * The displays are Raspberry Pi HATs and connected to the 8-bit only + * SPI controller, so 16-bit command and parameters need byte swapping + * before being transferred as 8-bit on the big endian SPI bus. + * Pixel data bytes have already been swapped before this function is + * called. + */ + buf[0] = cpu_to_be16(*cmd); + gpiod_set_value_cansleep(mipi->dc, 0); + speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 2); + ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, buf, 2); + if (ret || !num) + goto free; + + /* 8-bit configuration data, not 16-bit pixel data */ + if (num <= 32) { + for (i = 0; i < num; i++) + buf[i] = cpu_to_be16(par[i]); + num *= 2; + speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num); + data = buf; + } + + gpiod_set_value_cansleep(mipi->dc, 1); + ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, data, num); + free: + kfree(buf); + + return ret; +} + +static void waveshare_enable(struct drm_simple_display_pipe *pipe, + struct drm_crtc_state *crtc_state, + struct drm_plane_state *plane_state) +{ + struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); + struct mipi_dbi *dbi = &dbidev->dbi; + u8 addr_mode; + int ret, idx; + + if (!drm_dev_enter(pipe->crtc.dev, &idx)) + return; + + DRM_DEBUG_KMS("\n"); + + ret = mipi_dbi_poweron_conditional_reset(dbidev); + if (ret < 0) + goto out_exit; + if (ret == 1) + goto out_enable; + + mipi_dbi_command(dbi, ILI9486_ITFCTR1); + mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE); + msleep(250); + + mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 0x55); + + mipi_dbi_command(dbi, ILI9486_PWCTRL1, 0x44); + + mipi_dbi_command(dbi, ILI9486_VMCTRL1, 0x00, 0x00, 0x00, 0x00); + + mipi_dbi_command(dbi, ILI9486_PGAMCTRL, + 0x0F, 0x1F, 0x1C, 0x0C, 0x0F, 0x08, 0x48, 0x98, + 0x37, 0x0A, 0x13, 0x04, 0x11, 0x0D, 0x0); + mipi_dbi_command(dbi, ILI9486_NGAMCTRL, + 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75, + 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00); + mipi_dbi_command(dbi, ILI9486_DGAMCTRL, + 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75, + 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00); + + mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON); + msleep(100); + + out_enable: + switch (dbidev->rotation) { + case 90: + addr_mode = ILI9486_MADCTL_MY; + break; + case 180: + addr_mode = ILI9486_MADCTL_MV; + break; + case 270: + addr_mode = ILI9486_MADCTL_MX; + break; + default: + addr_mode = ILI9486_MADCTL_MV | ILI9486_MADCTL_MY | + ILI9486_MADCTL_MX; + break; + } + addr_mode |= ILI9486_MADCTL_BGR; + mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode); + mipi_dbi_enable_flush(dbidev, crtc_state, plane_state); + out_exit: + drm_dev_exit(idx); +} + +static const struct drm_simple_display_pipe_funcs waveshare_pipe_funcs = { + .enable = waveshare_enable, + .disable = mipi_dbi_pipe_disable, + .update = mipi_dbi_pipe_update, + .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, +}; + +static const struct drm_display_mode waveshare_mode = { + DRM_SIMPLE_MODE(480, 320, 73, 49), +}; + +DEFINE_DRM_GEM_CMA_FOPS(ili9486_fops); + +static struct drm_driver ili9486_driver = { + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, + .fops = &ili9486_fops, + .release = mipi_dbi_release, + DRM_GEM_CMA_VMAP_DRIVER_OPS, + .debugfs_init = mipi_dbi_debugfs_init, + .name = "ili9486", + .desc = "Ilitek ILI9486", + .date = "20200118", + .major = 1, + .minor = 0, +}; + +static const struct of_device_id ili9486_of_match[] = { + { .compatible = "waveshare,rpi-lcd-35" }, + { .compatible = "ozzmaker,piscreen" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ili9486_of_match); + +static const struct spi_device_id ili9486_id[] = { + { "ili9486", 0 }, + { } +}; +MODULE_DEVICE_TABLE(spi, ili9486_id); + +static int ili9486_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct mipi_dbi_dev *dbidev; + struct drm_device *drm; + struct mipi_dbi *dbi; + struct gpio_desc *dc; + u32 rotation = 0; + int ret; + + dbidev = kzalloc(sizeof(*dbidev), GFP_KERNEL); + if (!dbidev) + return -ENOMEM; + + dbi = &dbidev->dbi; + drm = &dbidev->drm; + ret = devm_drm_dev_init(dev, drm, &ili9486_driver); + if (ret) { + kfree(dbidev); + return ret; + } + + drm_mode_config_init(drm); + + dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(dbi->reset)) { + DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n"); + return PTR_ERR(dbi->reset); + } + + dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW); + if (IS_ERR(dc)) { + DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n"); + return PTR_ERR(dc); + } + + dbidev->backlight = devm_of_find_backlight(dev); + if (IS_ERR(dbidev->backlight)) + return PTR_ERR(dbidev->backlight); + + device_property_read_u32(dev, "rotation", &rotation); + + ret = mipi_dbi_spi_init(spi, dbi, dc); + if (ret) + return ret; + + dbi->command = waveshare_command; + dbi->read_commands = NULL; + + ret = mipi_dbi_dev_init(dbidev, &waveshare_pipe_funcs, + &waveshare_mode, rotation); + if (ret) + return ret; + + drm_mode_config_reset(drm); + + ret = drm_dev_register(drm, 0); + if (ret) + return ret; + + spi_set_drvdata(spi, drm); + + drm_fbdev_generic_setup(drm, 0); + + return 0; +} + +static int ili9486_remove(struct spi_device *spi) +{ + struct drm_device *drm = spi_get_drvdata(spi); + + drm_dev_unplug(drm); + drm_atomic_helper_shutdown(drm); + + return 0; +} + +static void ili9486_shutdown(struct spi_device *spi) +{ + drm_atomic_helper_shutdown(spi_get_drvdata(spi)); +} + +static struct spi_driver ili9486_spi_driver = { + .driver = { + .name = "ili9486", + .of_match_table = ili9486_of_match, + }, + .id_table = ili9486_id, + .probe = ili9486_probe, + .remove = ili9486_remove, + .shutdown = ili9486_shutdown, +}; +module_spi_driver(ili9486_spi_driver); + +MODULE_DESCRIPTION("Ilitek ILI9486 DRM driver"); +MODULE_AUTHOR("Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/tiny/repaper.c b/drivers/gpu/drm/tiny/repaper.c index 76d179200775..f5ebcaf7ee3a 100644 --- a/drivers/gpu/drm/tiny/repaper.c +++ b/drivers/gpu/drm/tiny/repaper.c @@ -17,7 +17,7 @@ #include <linux/dma-buf.h> #include <linux/gpio/consumer.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/property.h> #include <linux/sched/clock.h> #include <linux/spi/spi.h> #include <linux/thermal.h> @@ -33,13 +33,13 @@ #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_modes.h> #include <drm/drm_rect.h> -#include <drm/drm_vblank.h> #include <drm/drm_probe_helper.h> #include <drm/drm_simple_kms_helper.h> #define REPAPER_RID_G2_COG_ID 0x12 enum repaper_model { + /* 0 is reserved to avoid clashing with NULL */ E1144CS021 = 1, E1190CS021, E2200CS021, @@ -856,18 +856,10 @@ static void repaper_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *old_state) { struct drm_plane_state *state = pipe->plane.state; - struct drm_crtc *crtc = &pipe->crtc; struct drm_rect rect; if (drm_atomic_helper_damage_merged(old_state, state, &rect)) repaper_fb_dirty(state->fb); - - if (crtc->state->event) { - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, crtc->state->event); - spin_unlock_irq(&crtc->dev->event_lock); - crtc->state->event = NULL; - } } static const struct drm_simple_display_pipe_funcs repaper_pipe_funcs = { @@ -995,21 +987,21 @@ static int repaper_probe(struct spi_device *spi) { const struct drm_display_mode *mode; const struct spi_device_id *spi_id; - const struct of_device_id *match; struct device *dev = &spi->dev; enum repaper_model model; const char *thermal_zone; struct repaper_epd *epd; size_t line_buffer_size; struct drm_device *drm; + const void *match; int ret; - match = of_match_device(repaper_of_match, dev); + match = device_get_match_data(dev); if (match) { - model = (enum repaper_model)match->data; + model = (enum repaper_model)match; } else { spi_id = spi_get_device_id(spi); - model = spi_id->driver_data; + model = (enum repaper_model)spi_id->driver_data; } /* The SPI device is used to allocate dma memory */ @@ -1197,7 +1189,6 @@ static void repaper_shutdown(struct spi_device *spi) static struct spi_driver repaper_spi_driver = { .driver = { .name = "repaper", - .owner = THIS_MODULE, .of_match_table = repaper_of_match, }, .id_table = repaper_id, diff --git a/drivers/gpu/drm/tiny/st7586.c b/drivers/gpu/drm/tiny/st7586.c index 060cc756194f..9ef559dd3191 100644 --- a/drivers/gpu/drm/tiny/st7586.c +++ b/drivers/gpu/drm/tiny/st7586.c @@ -23,7 +23,6 @@ #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_mipi_dbi.h> #include <drm/drm_rect.h> -#include <drm/drm_vblank.h> /* controller-specific commands */ #define ST7586_DISP_MODE_GRAY 0x38 @@ -159,18 +158,10 @@ static void st7586_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *old_state) { struct drm_plane_state *state = pipe->plane.state; - struct drm_crtc *crtc = &pipe->crtc; struct drm_rect rect; if (drm_atomic_helper_damage_merged(old_state, state, &rect)) st7586_fb_dirty(state->fb, &rect); - - if (crtc->state->event) { - spin_lock_irq(&crtc->dev->event_lock); - drm_crtc_send_vblank_event(crtc, crtc->state->event); - spin_unlock_irq(&crtc->dev->event_lock); - crtc->state->event = NULL; - } } static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe, diff --git a/drivers/gpu/drm/tiny/st7735r.c b/drivers/gpu/drm/tiny/st7735r.c index 3f4487c71684..3cd9b8d9888d 100644 --- a/drivers/gpu/drm/tiny/st7735r.c +++ b/drivers/gpu/drm/tiny/st7735r.c @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * DRM driver for Sitronix ST7735R panels + * DRM driver for display panels connected to a Sitronix ST7715R or ST7735R + * display controller in SPI mode. * * Copyright 2017 David Lechner <david@lechnology.com> + * Copyright (C) 2019 Glider bvba */ #include <linux/backlight.h> @@ -37,12 +39,28 @@ #define ST7735R_MY BIT(7) #define ST7735R_MX BIT(6) #define ST7735R_MV BIT(5) +#define ST7735R_RGB BIT(3) + +struct st7735r_cfg { + const struct drm_display_mode mode; + unsigned int left_offset; + unsigned int top_offset; + unsigned int write_only:1; + unsigned int rgb:1; /* RGB (vs. BGR) */ +}; + +struct st7735r_priv { + struct mipi_dbi_dev dbidev; /* Must be first for .release() */ + const struct st7735r_cfg *cfg; +}; -static void jd_t18003_t01_pipe_enable(struct drm_simple_display_pipe *pipe, - struct drm_crtc_state *crtc_state, - struct drm_plane_state *plane_state) +static void st7735r_pipe_enable(struct drm_simple_display_pipe *pipe, + struct drm_crtc_state *crtc_state, + struct drm_plane_state *plane_state) { struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); + struct st7735r_priv *priv = container_of(dbidev, struct st7735r_priv, + dbidev); struct mipi_dbi *dbi = &dbidev->dbi; int ret, idx; u8 addr_mode; @@ -87,6 +105,10 @@ static void jd_t18003_t01_pipe_enable(struct drm_simple_display_pipe *pipe, addr_mode = ST7735R_MY | ST7735R_MV; break; } + + if (priv->cfg->rgb) + addr_mode |= ST7735R_RGB; + mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode); mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); @@ -109,15 +131,24 @@ out_exit: drm_dev_exit(idx); } -static const struct drm_simple_display_pipe_funcs jd_t18003_t01_pipe_funcs = { - .enable = jd_t18003_t01_pipe_enable, +static const struct drm_simple_display_pipe_funcs st7735r_pipe_funcs = { + .enable = st7735r_pipe_enable, .disable = mipi_dbi_pipe_disable, .update = mipi_dbi_pipe_update, .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, }; -static const struct drm_display_mode jd_t18003_t01_mode = { - DRM_SIMPLE_MODE(128, 160, 28, 35), +static const struct st7735r_cfg jd_t18003_t01_cfg = { + .mode = { DRM_SIMPLE_MODE(128, 160, 28, 35) }, + /* Cannot read from Adafruit 1.8" display via SPI */ + .write_only = true, +}; + +static const struct st7735r_cfg rh128128t_cfg = { + .mode = { DRM_SIMPLE_MODE(128, 128, 25, 26) }, + .left_offset = 2, + .top_offset = 3, + .rgb = true, }; DEFINE_DRM_GEM_CMA_FOPS(st7735r_fops); @@ -136,13 +167,14 @@ static struct drm_driver st7735r_driver = { }; static const struct of_device_id st7735r_of_match[] = { - { .compatible = "jianda,jd-t18003-t01" }, + { .compatible = "jianda,jd-t18003-t01", .data = &jd_t18003_t01_cfg }, + { .compatible = "okaya,rh128128t", .data = &rh128128t_cfg }, { }, }; MODULE_DEVICE_TABLE(of, st7735r_of_match); static const struct spi_device_id st7735r_id[] = { - { "jd-t18003-t01", 0 }, + { "jd-t18003-t01", (uintptr_t)&jd_t18003_t01_cfg }, { }, }; MODULE_DEVICE_TABLE(spi, st7735r_id); @@ -150,17 +182,26 @@ MODULE_DEVICE_TABLE(spi, st7735r_id); static int st7735r_probe(struct spi_device *spi) { struct device *dev = &spi->dev; + const struct st7735r_cfg *cfg; struct mipi_dbi_dev *dbidev; + struct st7735r_priv *priv; struct drm_device *drm; struct mipi_dbi *dbi; struct gpio_desc *dc; u32 rotation = 0; int ret; - dbidev = kzalloc(sizeof(*dbidev), GFP_KERNEL); - if (!dbidev) + cfg = device_get_match_data(&spi->dev); + if (!cfg) + cfg = (void *)spi_get_device_id(spi)->driver_data; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) return -ENOMEM; + dbidev = &priv->dbidev; + priv->cfg = cfg; + dbi = &dbidev->dbi; drm = &dbidev->drm; ret = devm_drm_dev_init(dev, drm, &st7735r_driver); @@ -193,10 +234,14 @@ static int st7735r_probe(struct spi_device *spi) if (ret) return ret; - /* Cannot read from Adafruit 1.8" display via SPI */ - dbi->read_commands = NULL; + if (cfg->write_only) + dbi->read_commands = NULL; + + dbidev->left_offset = cfg->left_offset; + dbidev->top_offset = cfg->top_offset; - ret = mipi_dbi_dev_init(dbidev, &jd_t18003_t01_pipe_funcs, &jd_t18003_t01_mode, rotation); + ret = mipi_dbi_dev_init(dbidev, &st7735r_pipe_funcs, &cfg->mode, + rotation); if (ret) return ret; @@ -231,7 +276,6 @@ static void st7735r_shutdown(struct spi_device *spi) static struct spi_driver st7735r_spi_driver = { .driver = { .name = "st7735r", - .owner = THIS_MODULE, .of_match_table = st7735r_of_match, }, .id_table = st7735r_id, diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 5df596fb0280..1fbc36f05d89 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -372,14 +372,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, } moved: - if (bo->evicted) { - if (bdev->driver->invalidate_caches) { - ret = bdev->driver->invalidate_caches(bdev, bo->mem.placement); - if (ret) - pr_err("Can not flush read caches\n"); - } - bo->evicted = false; - } + bo->evicted = false; if (bo->mem.mm_node) bo->offset = (bo->mem.start << PAGE_SHIFT) + @@ -498,8 +491,10 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) dma_resv_unlock(bo->base.resv); } - if (bo->base.resv != &bo->base._resv) + if (bo->base.resv != &bo->base._resv) { + ttm_bo_flush_all_fences(bo); dma_resv_unlock(&bo->base._resv); + } error: kref_get(&bo->list_kref); diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 2b0e5a088da0..49ed55779128 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -218,7 +218,7 @@ static int ttm_mem_reg_ioremap(struct ttm_bo_device *bdev, struct ttm_mem_reg *m if (mem->placement & TTM_PL_FLAG_WC) addr = ioremap_wc(mem->bus.base + mem->bus.offset, mem->bus.size); else - addr = ioremap_nocache(mem->bus.base + mem->bus.offset, mem->bus.size); + addr = ioremap(mem->bus.base + mem->bus.offset, mem->bus.size); if (!addr) { (void) ttm_mem_io_lock(man, false); ttm_mem_io_free(bdev, mem); @@ -564,7 +564,7 @@ static int ttm_bo_ioremap(struct ttm_buffer_object *bo, map->virtual = ioremap_wc(bo->mem.bus.base + bo->mem.bus.offset + offset, size); else - map->virtual = ioremap_nocache(bo->mem.bus.base + bo->mem.bus.offset + offset, + map->virtual = ioremap(bo->mem.bus.base + bo->mem.bus.offset + offset, size); } return (!map->virtual) ? -ENOMEM : 0; diff --git a/drivers/gpu/drm/udl/udl_connector.c b/drivers/gpu/drm/udl/udl_connector.c index e9671d38b4a0..0afdfb0d1fe1 100644 --- a/drivers/gpu/drm/udl/udl_connector.c +++ b/drivers/gpu/drm/udl/udl_connector.c @@ -109,7 +109,6 @@ static const struct drm_connector_helper_funcs udl_connector_helper_funcs = { }; static const struct drm_connector_funcs udl_connector_funcs = { - .dpms = drm_helper_connector_dpms, .reset = drm_atomic_helper_connector_reset, .detect = udl_detect, .fill_modes = drm_helper_probe_single_connector_modes, diff --git a/drivers/gpu/drm/udl/udl_modeset.c b/drivers/gpu/drm/udl/udl_modeset.c index 22af17959053..d59ebac70b15 100644 --- a/drivers/gpu/drm/udl/udl_modeset.c +++ b/drivers/gpu/drm/udl/udl_modeset.c @@ -375,8 +375,6 @@ udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe, char *wrptr; int color_depth = UDL_COLOR_DEPTH_16BPP; - crtc_state->no_vblank = true; - buf = (char *)udl->mode_buf; /* This first section has to do with setting the base address on the @@ -428,14 +426,6 @@ udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe) udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer); } -static int -udl_simple_display_pipe_check(struct drm_simple_display_pipe *pipe, - struct drm_plane_state *plane_state, - struct drm_crtc_state *crtc_state) -{ - return 0; -} - static void udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *old_plane_state) @@ -457,7 +447,6 @@ struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = { .mode_valid = udl_simple_display_pipe_mode_valid, .enable = udl_simple_display_pipe_enable, .disable = udl_simple_display_pipe_disable, - .check = udl_simple_display_pipe_check, .update = udl_simple_display_pipe_update, .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, }; diff --git a/drivers/gpu/drm/vboxvideo/vbox_mode.c b/drivers/gpu/drm/vboxvideo/vbox_mode.c index 19612132c8a3..0883a435e62b 100644 --- a/drivers/gpu/drm/vboxvideo/vbox_mode.c +++ b/drivers/gpu/drm/vboxvideo/vbox_mode.c @@ -18,7 +18,6 @@ #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> -#include <drm/drm_vblank.h> #include "hgsmi_channels.h" #include "vbox_drv.h" @@ -226,17 +225,6 @@ static void vbox_crtc_atomic_disable(struct drm_crtc *crtc, static void vbox_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { - struct drm_pending_vblank_event *event; - unsigned long flags; - - if (crtc->state && crtc->state->event) { - event = crtc->state->event; - crtc->state->event = NULL; - - spin_lock_irqsave(&crtc->dev->event_lock, flags); - drm_crtc_send_vblank_event(crtc, event); - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - } } static const struct drm_crtc_helper_funcs vbox_crtc_helper_funcs = { @@ -838,6 +826,7 @@ static int vbox_connector_init(struct drm_device *dev, static const struct drm_mode_config_funcs vbox_mode_funcs = { .fb_create = drm_gem_fb_create_with_dirty, + .mode_valid = drm_vram_helper_mode_valid, .atomic_check = drm_atomic_helper_check, .atomic_commit = drm_atomic_helper_commit, }; diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c index 4934127f0d76..91e408f7a56e 100644 --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -139,7 +139,7 @@ static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst) static bool plane_enabled(struct drm_plane_state *state) { - return state->fb && state->crtc; + return state->fb && !WARN_ON(!state->crtc); } static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane) diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c index 5bd60ded3d81..909eba43664a 100644 --- a/drivers/gpu/drm/vgem/vgem_drv.c +++ b/drivers/gpu/drm/vgem/vgem_drv.c @@ -196,9 +196,10 @@ static struct drm_gem_object *vgem_gem_create(struct drm_device *dev, return ERR_CAST(obj); ret = drm_gem_handle_create(file, &obj->base, handle); - drm_gem_object_put_unlocked(&obj->base); - if (ret) + if (ret) { + drm_gem_object_put_unlocked(&obj->base); return ERR_PTR(ret); + } return &obj->base; } @@ -221,7 +222,9 @@ static int vgem_gem_dumb_create(struct drm_file *file, struct drm_device *dev, args->size = gem_object->size; args->pitch = pitch; - DRM_DEBUG("Created object of size %lld\n", size); + drm_gem_object_put_unlocked(gem_object); + + DRM_DEBUG("Created object of size %llu\n", args->size); return 0; } diff --git a/drivers/gpu/drm/via/via_dmablit.c b/drivers/gpu/drm/via/via_dmablit.c index d13a3897506e..551fa31629af 100644 --- a/drivers/gpu/drm/via/via_dmablit.c +++ b/drivers/gpu/drm/via/via_dmablit.c @@ -188,8 +188,8 @@ via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg) kfree(vsg->desc_pages); /* fall through */ case dr_via_pages_locked: - put_user_pages_dirty_lock(vsg->pages, vsg->num_pages, - (vsg->direction == DMA_FROM_DEVICE)); + unpin_user_pages_dirty_lock(vsg->pages, vsg->num_pages, + (vsg->direction == DMA_FROM_DEVICE)); /* fall through */ case dr_via_pages_alloc: vfree(vsg->pages); @@ -239,7 +239,7 @@ via_lock_all_dma_pages(drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer) vsg->pages = vzalloc(array_size(sizeof(struct page *), vsg->num_pages)); if (NULL == vsg->pages) return -ENOMEM; - ret = get_user_pages_fast((unsigned long)xfer->mem_addr, + ret = pin_user_pages_fast((unsigned long)xfer->mem_addr, vsg->num_pages, vsg->direction == DMA_FROM_DEVICE ? FOLL_WRITE : 0, vsg->pages); diff --git a/drivers/gpu/drm/virtio/virtgpu_debugfs.c b/drivers/gpu/drm/virtio/virtgpu_debugfs.c index 5156e6b279db..e27120d512b0 100644 --- a/drivers/gpu/drm/virtio/virtgpu_debugfs.c +++ b/drivers/gpu/drm/virtio/virtgpu_debugfs.c @@ -47,6 +47,7 @@ static int virtio_gpu_features(struct seq_file *m, void *data) virtio_add_bool(m, "virgl", vgdev->has_virgl_3d); virtio_add_bool(m, "edid", vgdev->has_edid); + virtio_add_bool(m, "indirect", vgdev->has_indirect); virtio_add_int(m, "cap sets", vgdev->num_capsets); virtio_add_int(m, "scanouts", vgdev->num_scanouts); return 0; diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c index 0966208ec30d..7b0f0643bb2d 100644 --- a/drivers/gpu/drm/virtio/virtgpu_display.c +++ b/drivers/gpu/drm/virtio/virtgpu_display.c @@ -30,7 +30,6 @@ #include <drm/drm_fourcc.h> #include <drm/drm_gem_framebuffer_helper.h> #include <drm/drm_probe_helper.h> -#include <drm/drm_vblank.h> #include "virtgpu_drv.h" @@ -121,13 +120,6 @@ static int virtio_gpu_crtc_atomic_check(struct drm_crtc *crtc, static void virtio_gpu_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { - unsigned long flags; - - spin_lock_irqsave(&crtc->dev->event_lock, flags); - if (crtc->state->event) - drm_crtc_send_vblank_event(crtc, crtc->state->event); - crtc->state->event = NULL; - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); } static const struct drm_crtc_helper_funcs virtio_gpu_crtc_helper_funcs = { @@ -332,6 +324,7 @@ static void vgdev_atomic_commit_tail(struct drm_atomic_state *state) drm_atomic_helper_commit_modeset_enables(dev, state); drm_atomic_helper_commit_planes(dev, state, 0); + drm_atomic_helper_fake_vblank(state); drm_atomic_helper_commit_hw_done(state); drm_atomic_helper_wait_for_vblanks(dev, state); diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h b/drivers/gpu/drm/virtio/virtgpu_drv.h index 7e69c06e168e..d278c8c50f39 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.h +++ b/drivers/gpu/drm/virtio/virtgpu_drv.h @@ -193,6 +193,7 @@ struct virtio_gpu_device { bool has_virgl_3d; bool has_edid; + bool has_indirect; struct work_struct config_changed_work; diff --git a/drivers/gpu/drm/virtio/virtgpu_kms.c b/drivers/gpu/drm/virtio/virtgpu_kms.c index 2f5773e43557..c1086df49816 100644 --- a/drivers/gpu/drm/virtio/virtgpu_kms.c +++ b/drivers/gpu/drm/virtio/virtgpu_kms.c @@ -159,6 +159,9 @@ int virtio_gpu_init(struct drm_device *dev) if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_EDID)) { vgdev->has_edid = true; } + if (virtio_has_feature(vgdev->vdev, VIRTIO_RING_F_INDIRECT_DESC)) { + vgdev->has_indirect = true; + } DRM_INFO("features: %cvirgl %cedid\n", vgdev->has_virgl_3d ? '+' : '-', diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c index 5914e79d3429..cc02fc4bab2a 100644 --- a/drivers/gpu/drm/virtio/virtgpu_vq.c +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c @@ -95,7 +95,8 @@ virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev, if (!vbuf) return ERR_PTR(-ENOMEM); - BUG_ON(size > MAX_INLINE_CMD_SIZE); + BUG_ON(size > MAX_INLINE_CMD_SIZE || + size < sizeof(struct virtio_gpu_ctrl_hdr)); vbuf->buf = (void *)vbuf + sizeof(*vbuf); vbuf->size = size; @@ -109,6 +110,16 @@ virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev, return vbuf; } +static struct virtio_gpu_ctrl_hdr * +virtio_gpu_vbuf_ctrl_hdr(struct virtio_gpu_vbuffer *vbuf) +{ + /* this assumes a vbuf contains a command that starts with a + * virtio_gpu_ctrl_hdr, which is true for both ctrl and cursor + * virtqueues. + */ + return (struct virtio_gpu_ctrl_hdr *)vbuf->buf; +} + static void *virtio_gpu_alloc_cmd(struct virtio_gpu_device *vgdev, struct virtio_gpu_vbuffer **vbuffer_p, int size) @@ -211,10 +222,10 @@ void virtio_gpu_dequeue_ctrl_func(struct work_struct *work) if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA)) { if (resp->type >= cpu_to_le32(VIRTIO_GPU_RESP_ERR_UNSPEC)) { struct virtio_gpu_ctrl_hdr *cmd; - cmd = (struct virtio_gpu_ctrl_hdr *)entry->buf; - DRM_ERROR("response 0x%x (command 0x%x)\n", - le32_to_cpu(resp->type), - le32_to_cpu(cmd->type)); + cmd = virtio_gpu_vbuf_ctrl_hdr(entry); + DRM_ERROR_RATELIMITED("response 0x%x (command 0x%x)\n", + le32_to_cpu(resp->type), + le32_to_cpu(cmd->type)); } else DRM_DEBUG("response 0x%x\n", le32_to_cpu(resp->type)); } @@ -307,109 +318,113 @@ static struct sg_table *vmalloc_to_sgt(char *data, uint32_t size, int *sg_ents) return sgt; } -static bool virtio_gpu_queue_ctrl_buffer_locked(struct virtio_gpu_device *vgdev, - struct virtio_gpu_vbuffer *vbuf, - struct scatterlist *vout) - __releases(&vgdev->ctrlq.qlock) - __acquires(&vgdev->ctrlq.qlock) +static void virtio_gpu_queue_ctrl_sgs(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf, + struct virtio_gpu_fence *fence, + int elemcnt, + struct scatterlist **sgs, + int outcnt, + int incnt) { struct virtqueue *vq = vgdev->ctrlq.vq; - struct scatterlist *sgs[3], vcmd, vresp; - int outcnt = 0, incnt = 0; bool notify = false; int ret; - if (!vgdev->vqs_ready) - return notify; + if (vgdev->has_indirect) + elemcnt = 1; - sg_init_one(&vcmd, vbuf->buf, vbuf->size); - sgs[outcnt + incnt] = &vcmd; - outcnt++; +again: + spin_lock(&vgdev->ctrlq.qlock); - if (vout) { - sgs[outcnt + incnt] = vout; - outcnt++; + if (!vgdev->vqs_ready) { + spin_unlock(&vgdev->ctrlq.qlock); + + if (fence && vbuf->objs) + virtio_gpu_array_unlock_resv(vbuf->objs); + return; } - if (vbuf->resp_size) { - sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size); - sgs[outcnt + incnt] = &vresp; - incnt++; + if (vq->num_free < elemcnt) { + spin_unlock(&vgdev->ctrlq.qlock); + wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= elemcnt); + goto again; + } + + /* now that the position of the vbuf in the virtqueue is known, we can + * finally set the fence id + */ + if (fence) { + virtio_gpu_fence_emit(vgdev, virtio_gpu_vbuf_ctrl_hdr(vbuf), + fence); + if (vbuf->objs) { + virtio_gpu_array_add_fence(vbuf->objs, &fence->f); + virtio_gpu_array_unlock_resv(vbuf->objs); + } } -retry: ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC); - if (ret == -ENOSPC) { - spin_unlock(&vgdev->ctrlq.qlock); - wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= outcnt + incnt); - spin_lock(&vgdev->ctrlq.qlock); - goto retry; - } else { - trace_virtio_gpu_cmd_queue(vq, - (struct virtio_gpu_ctrl_hdr *)vbuf->buf); + WARN_ON(ret); - notify = virtqueue_kick_prepare(vq); + trace_virtio_gpu_cmd_queue(vq, virtio_gpu_vbuf_ctrl_hdr(vbuf)); + + notify = virtqueue_kick_prepare(vq); + + spin_unlock(&vgdev->ctrlq.qlock); + + if (notify) { + if (vgdev->disable_notify) + vgdev->pending_notify = true; + else + virtqueue_notify(vq); } - return notify; } static void virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev, struct virtio_gpu_vbuffer *vbuf, - struct virtio_gpu_ctrl_hdr *hdr, struct virtio_gpu_fence *fence) { - struct virtqueue *vq = vgdev->ctrlq.vq; - struct scatterlist *vout = NULL, sg; + struct scatterlist *sgs[3], vcmd, vout, vresp; struct sg_table *sgt = NULL; - bool notify; - int outcnt = 0; + int elemcnt = 0, outcnt = 0, incnt = 0; + /* set up vcmd */ + sg_init_one(&vcmd, vbuf->buf, vbuf->size); + elemcnt++; + sgs[outcnt] = &vcmd; + outcnt++; + + /* set up vout */ if (vbuf->data_size) { if (is_vmalloc_addr(vbuf->data_buf)) { + int sg_ents; sgt = vmalloc_to_sgt(vbuf->data_buf, vbuf->data_size, - &outcnt); - if (!sgt) + &sg_ents); + if (!sgt) { + if (fence && vbuf->objs) + virtio_gpu_array_unlock_resv(vbuf->objs); return; - vout = sgt->sgl; + } + + elemcnt += sg_ents; + sgs[outcnt] = sgt->sgl; } else { - sg_init_one(&sg, vbuf->data_buf, vbuf->data_size); - vout = &sg; - outcnt = 1; + sg_init_one(&vout, vbuf->data_buf, vbuf->data_size); + elemcnt++; + sgs[outcnt] = &vout; } + outcnt++; } -again: - spin_lock(&vgdev->ctrlq.qlock); - - /* - * Make sure we have enouth space in the virtqueue. If not - * wait here until we have. - * - * Without that virtio_gpu_queue_ctrl_buffer_nolock might have - * to wait for free space, which can result in fence ids being - * submitted out-of-order. - */ - if (vq->num_free < 2 + outcnt) { - spin_unlock(&vgdev->ctrlq.qlock); - wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= 3); - goto again; + /* set up vresp */ + if (vbuf->resp_size) { + sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size); + elemcnt++; + sgs[outcnt + incnt] = &vresp; + incnt++; } - if (hdr && fence) { - virtio_gpu_fence_emit(vgdev, hdr, fence); - if (vbuf->objs) { - virtio_gpu_array_add_fence(vbuf->objs, &fence->f); - virtio_gpu_array_unlock_resv(vbuf->objs); - } - } - notify = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf, vout); - spin_unlock(&vgdev->ctrlq.qlock); - if (notify) { - if (vgdev->disable_notify) - vgdev->pending_notify = true; - else - virtqueue_notify(vgdev->ctrlq.vq); - } + virtio_gpu_queue_ctrl_sgs(vgdev, vbuf, fence, elemcnt, sgs, outcnt, + incnt); if (sgt) { sg_free_table(sgt); @@ -435,7 +450,7 @@ void virtio_gpu_enable_notify(struct virtio_gpu_device *vgdev) static void virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev, struct virtio_gpu_vbuffer *vbuf) { - virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, NULL, NULL); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, NULL); } static void virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev, @@ -464,7 +479,7 @@ retry: goto retry; } else { trace_virtio_gpu_cmd_queue(vq, - (struct virtio_gpu_ctrl_hdr *)vbuf->buf); + virtio_gpu_vbuf_ctrl_hdr(vbuf)); notify = virtqueue_kick_prepare(vq); } @@ -499,7 +514,7 @@ void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev, cmd_p->width = cpu_to_le32(params->width); cmd_p->height = cpu_to_le32(params->height); - virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); bo->created = true; } @@ -531,7 +546,7 @@ static void virtio_gpu_cmd_resource_inval_backing(struct virtio_gpu_device *vgde cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING); cmd_p->resource_id = cpu_to_le32(resource_id); - virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); } void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev, @@ -606,7 +621,7 @@ void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev, cmd_p->r.x = cpu_to_le32(x); cmd_p->r.y = cpu_to_le32(y); - virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); } static void @@ -629,7 +644,7 @@ virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev, vbuf->data_buf = ents; vbuf->data_size = sizeof(*ents) * nents; - virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); } static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev, @@ -988,7 +1003,7 @@ virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev, cmd_p->nr_samples = cpu_to_le32(params->nr_samples); cmd_p->flags = cpu_to_le32(params->flags); - virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); bo->created = true; } @@ -1021,7 +1036,7 @@ void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev, cmd_p->offset = cpu_to_le64(offset); cmd_p->level = cpu_to_le32(level); - virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); } void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev, @@ -1047,7 +1062,7 @@ void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev, cmd_p->offset = cpu_to_le64(offset); cmd_p->level = cpu_to_le32(level); - virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); } void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev, @@ -1070,7 +1085,7 @@ void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev, cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id); cmd_p->size = cpu_to_le32(data_size); - virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence); } int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev, diff --git a/drivers/gpu/drm/vkms/vkms_plane.c b/drivers/gpu/drm/vkms/vkms_plane.c index 5fc8f85aaf3d..6d31265a2ab7 100644 --- a/drivers/gpu/drm/vkms/vkms_plane.c +++ b/drivers/gpu/drm/vkms/vkms_plane.c @@ -117,7 +117,7 @@ static int vkms_plane_atomic_check(struct drm_plane *plane, bool can_position = false; int ret; - if (!state->fb | !state->crtc) + if (!state->fb || WARN_ON(!state->crtc)) return 0; crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c index d8ea3dd10af0..3f3b2c7a208a 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c @@ -736,11 +736,6 @@ out_no_init: return NULL; } -static int vmw_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) -{ - return 0; -} - static int vmw_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, struct ttm_mem_type_manager *man) { @@ -866,7 +861,6 @@ struct ttm_bo_driver vmw_bo_driver = { .ttm_tt_create = &vmw_ttm_tt_create, .ttm_tt_populate = &vmw_ttm_populate, .ttm_tt_unpopulate = &vmw_ttm_unpopulate, - .invalidate_caches = vmw_invalidate_caches, .init_mem_type = vmw_init_mem_type, .eviction_valuable = ttm_bo_eviction_valuable, .evict_flags = vmw_evict_flags, diff --git a/drivers/gpu/drm/xen/xen_drm_front_kms.c b/drivers/gpu/drm/xen/xen_drm_front_kms.c index 4f34c5208180..78096bbcd226 100644 --- a/drivers/gpu/drm/xen/xen_drm_front_kms.c +++ b/drivers/gpu/drm/xen/xen_drm_front_kms.c @@ -220,6 +220,24 @@ static bool display_send_page_flip(struct drm_simple_display_pipe *pipe, return false; } +static int display_check(struct drm_simple_display_pipe *pipe, + struct drm_plane_state *plane_state, + struct drm_crtc_state *crtc_state) +{ + /* + * Xen doesn't initialize vblanking via drm_vblank_init(), so + * DRM helpers assume that it doesn't handle vblanking and start + * sending out fake VBLANK events automatically. + * + * As xen contains it's own logic for sending out VBLANK events + * in send_pending_event(), disable no_vblank (i.e., the xen + * driver has vblanking support). + */ + crtc_state->no_vblank = false; + + return 0; +} + static void display_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *old_plane_state) { @@ -284,6 +302,7 @@ static const struct drm_simple_display_pipe_funcs display_funcs = { .enable = display_enable, .disable = display_disable, .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, + .check = display_check, .update = display_update, }; diff --git a/drivers/gpu/drm/zte/zx_plane.c b/drivers/gpu/drm/zte/zx_plane.c index 086c50fac689..c8f7b21fa09e 100644 --- a/drivers/gpu/drm/zte/zx_plane.c +++ b/drivers/gpu/drm/zte/zx_plane.c @@ -54,7 +54,7 @@ static int zx_vl_plane_atomic_check(struct drm_plane *plane, int min_scale = FRAC_16_16(1, 8); int max_scale = FRAC_16_16(8, 1); - if (!crtc || !fb) + if (!crtc || WARN_ON(!fb)) return 0; crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state, @@ -281,7 +281,7 @@ static int zx_gl_plane_atomic_check(struct drm_plane *plane, struct drm_crtc *crtc = plane_state->crtc; struct drm_crtc_state *crtc_state; - if (!crtc || !fb) + if (!crtc || WARN_ON(!fb)) return 0; crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state, |