diff options
Diffstat (limited to 'drivers/net/ethernet/cadence')
| -rw-r--r-- | drivers/net/ethernet/cadence/macb.c | 55 | ||||
| -rw-r--r-- | drivers/net/ethernet/cadence/macb.h | 525 |
2 files changed, 469 insertions, 111 deletions
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index 3767271c7667..dd8c202c0708 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -1827,12 +1827,23 @@ static int macb_close(struct net_device *dev) static void gem_update_stats(struct macb *bp) { - u32 __iomem *reg = bp->regs + GEM_OTX; + int i; u32 *p = &bp->hw_stats.gem.tx_octets_31_0; - u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1; - for (; p < end; p++, reg++) - *p += __raw_readl(reg); + for (i = 0; i < GEM_STATS_LEN; ++i, ++p) { + u32 offset = gem_statistics[i].offset; + u64 val = __raw_readl(bp->regs+offset); + + bp->ethtool_stats[i] += val; + *p += val; + + if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) { + /* Add GEM_OCTTXH, GEM_OCTRXH */ + val = __raw_readl(bp->regs+offset+4); + bp->ethtool_stats[i] += ((u64)val)<<32; + *(++p) += val; + } + } } static struct net_device_stats *gem_get_stats(struct macb *bp) @@ -1873,6 +1884,39 @@ static struct net_device_stats *gem_get_stats(struct macb *bp) return nstat; } +static void gem_get_ethtool_stats(struct net_device *dev, + struct ethtool_stats *stats, u64 *data) +{ + struct macb *bp; + + bp = netdev_priv(dev); + gem_update_stats(bp); + memcpy(data, &bp->ethtool_stats, sizeof(u64)*GEM_STATS_LEN); +} + +static int gem_get_sset_count(struct net_device *dev, int sset) +{ + switch (sset) { + case ETH_SS_STATS: + return GEM_STATS_LEN; + default: + return -EOPNOTSUPP; + } +} + +static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p) +{ + int i; + + switch (sset) { + case ETH_SS_STATS: + for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN) + memcpy(p, gem_statistics[i].stat_string, + ETH_GSTRING_LEN); + break; + } +} + struct net_device_stats *macb_get_stats(struct net_device *dev) { struct macb *bp = netdev_priv(dev); @@ -1988,6 +2032,9 @@ const struct ethtool_ops macb_ethtool_ops = { .get_regs = macb_get_regs, .get_link = ethtool_op_get_link, .get_ts_info = ethtool_op_get_ts_info, + .get_ethtool_stats = gem_get_ethtool_stats, + .get_strings = gem_get_ethtool_strings, + .get_sset_count = gem_get_sset_count, }; EXPORT_SYMBOL_GPL(macb_ethtool_ops); diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 084191b6fad2..378b2183ab8d 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -15,20 +15,20 @@ #define MACB_MAX_QUEUES 8 /* MACB register offsets */ -#define MACB_NCR 0x0000 -#define MACB_NCFGR 0x0004 -#define MACB_NSR 0x0008 +#define MACB_NCR 0x0000 /* Network Control */ +#define MACB_NCFGR 0x0004 /* Network Config */ +#define MACB_NSR 0x0008 /* Network Status */ #define MACB_TAR 0x000c /* AT91RM9200 only */ #define MACB_TCR 0x0010 /* AT91RM9200 only */ -#define MACB_TSR 0x0014 -#define MACB_RBQP 0x0018 -#define MACB_TBQP 0x001c -#define MACB_RSR 0x0020 -#define MACB_ISR 0x0024 -#define MACB_IER 0x0028 -#define MACB_IDR 0x002c -#define MACB_IMR 0x0030 -#define MACB_MAN 0x0034 +#define MACB_TSR 0x0014 /* Transmit Status */ +#define MACB_RBQP 0x0018 /* RX Q Base Address */ +#define MACB_TBQP 0x001c /* TX Q Base Address */ +#define MACB_RSR 0x0020 /* Receive Status */ +#define MACB_ISR 0x0024 /* Interrupt Status */ +#define MACB_IER 0x0028 /* Interrupt Enable */ +#define MACB_IDR 0x002c /* Interrupt Disable */ +#define MACB_IMR 0x0030 /* Interrupt Mask */ +#define MACB_MAN 0x0034 /* PHY Maintenance */ #define MACB_PTR 0x0038 #define MACB_PFR 0x003c #define MACB_FTO 0x0040 @@ -68,27 +68,180 @@ #define MACB_MID 0x00fc /* GEM register offsets. */ -#define GEM_NCFGR 0x0004 -#define GEM_USRIO 0x000c -#define GEM_DMACFG 0x0010 -#define GEM_HRB 0x0080 -#define GEM_HRT 0x0084 -#define GEM_SA1B 0x0088 -#define GEM_SA1T 0x008C -#define GEM_SA2B 0x0090 -#define GEM_SA2T 0x0094 -#define GEM_SA3B 0x0098 -#define GEM_SA3T 0x009C -#define GEM_SA4B 0x00A0 -#define GEM_SA4T 0x00A4 -#define GEM_OTX 0x0100 -#define GEM_DCFG1 0x0280 -#define GEM_DCFG2 0x0284 -#define GEM_DCFG3 0x0288 -#define GEM_DCFG4 0x028c -#define GEM_DCFG5 0x0290 -#define GEM_DCFG6 0x0294 -#define GEM_DCFG7 0x0298 +#define GEM_NCFGR 0x0004 /* Network Config */ +#define GEM_USRIO 0x000c /* User IO */ +#define GEM_DMACFG 0x0010 /* DMA Configuration */ +#define GEM_HRB 0x0080 /* Hash Bottom */ +#define GEM_HRT 0x0084 /* Hash Top */ +#define GEM_SA1B 0x0088 /* Specific1 Bottom */ +#define GEM_SA1T 0x008C /* Specific1 Top */ +#define GEM_SA2B 0x0090 /* Specific2 Bottom */ +#define GEM_SA2T 0x0094 /* Specific2 Top */ +#define GEM_SA3B 0x0098 /* Specific3 Bottom */ +#define GEM_SA3T 0x009C /* Specific3 Top */ +#define GEM_SA4B 0x00A0 /* Specific4 Bottom */ +#define GEM_SA4T 0x00A4 /* Specific4 Top */ +#define GEM_OTX 0x0100 /* Octets transmitted */ +#define GEM_OCTTXL 0x0100 /* Octets transmitted + * [31:0] + */ +#define GEM_OCTTXH 0x0104 /* Octets transmitted + * [47:32] + */ +#define GEM_TXCNT 0x0108 /* Error-free Frames + * Transmitted counter + */ +#define GEM_TXBCCNT 0x010c /* Error-free Broadcast + * Frames counter + */ +#define GEM_TXMCCNT 0x0110 /* Error-free Multicast + * Frames counter + */ +#define GEM_TXPAUSECNT 0x0114 /* Pause Frames + * Transmitted Counter + */ +#define GEM_TX64CNT 0x0118 /* Error-free 64 byte + * Frames Transmitted + * counter + */ +#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte + * Frames Transmitted + * counter + */ +#define GEM_TX128CNT 0x0120 /* Error-free 128-255 + * byte Frames + * Transmitted counter + */ +#define GEM_TX256CNT 0x0124 /* Error-free 256-511 + * byte Frames + * transmitted counter + */ +#define GEM_TX512CNT 0x0128 /* Error-free 512-1023 + * byte Frames + * transmitted counter + */ +#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518 + * byte Frames + * transmitted counter + */ +#define GEM_TX1519CNT 0x0130 /* Error-free larger than + * 1519 byte Frames + * tranmitted counter + */ +#define GEM_TXURUNCNT 0x0134 /* TX under run error + * counter + */ +#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame + * Counter + */ +#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision + * Frame Counter + */ +#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision + * Frame Counter + */ +#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame + * Counter + */ +#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission + * Frame Counter + */ +#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error + * Counter + */ +#define GEM_ORX 0x0150 /* Octets received */ +#define GEM_OCTRXL 0x0150 /* Octets received + * [31:0] + */ +#define GEM_OCTRXH 0x0154 /* Octets received + * [47:32] + */ +#define GEM_RXCNT 0x0158 /* Error-free Frames + * Received Counter + */ +#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast + * Frames Received + * Counter + */ +#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast + * Frames Received + * Counter + */ +#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause + * Frames Received + * Counter + */ +#define GEM_RX64CNT 0x0168 /* Error-free 64 byte + * Frames Received + * Counter + */ +#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte + * Frames Received + * Counter + */ +#define GEM_RX128CNT 0x0170 /* Error-free 128-255 + * byte Frames Received + * Counter + */ +#define GEM_RX256CNT 0x0174 /* Error-free 256-511 + * byte Frames Received + * Counter + */ +#define GEM_RX512CNT 0x0178 /* Error-free 512-1023 + * byte Frames Received + * Counter + */ +#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518 + * byte Frames Received + * Counter + */ +#define GEM_RX1519CNT 0x0180 /* Error-free larger than + * 1519 Frames Received + * Counter + */ +#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames + * Received Counter + */ +#define GEM_RXOVRCNT 0x0188 /* Oversize Frames + * Received Counter + */ +#define GEM_RXJABCNT 0x018c /* Jabbers Received + * Counter + */ +#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence + * Error Counter + */ +#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error + * Counter + */ +#define GEM_RXSYMBCNT 0x0198 /* Symbol Error + * Counter + */ +#define GEM_RXALIGNCNT 0x019c /* Alignment Error + * Counter + */ +#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error + * Counter + */ +#define GEM_RXORCNT 0x01a4 /* Receive Overrun + * Counter + */ +#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum + * Error Counter + */ +#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error + * Counter + */ +#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error + * Counter + */ +#define GEM_DCFG1 0x0280 /* Design Config 1 */ +#define GEM_DCFG2 0x0284 /* Design Config 2 */ +#define GEM_DCFG3 0x0288 /* Design Config 3 */ +#define GEM_DCFG4 0x028c /* Design Config 4 */ +#define GEM_DCFG5 0x0290 /* Design Config 5 */ +#define GEM_DCFG6 0x0294 /* Design Config 6 */ +#define GEM_DCFG7 0x0298 /* Design Config 7 */ #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) @@ -98,67 +251,73 @@ #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) /* Bitfields in NCR */ -#define MACB_LB_OFFSET 0 +#define MACB_LB_OFFSET 0 /* reserved */ #define MACB_LB_SIZE 1 -#define MACB_LLB_OFFSET 1 +#define MACB_LLB_OFFSET 1 /* Loop back local */ #define MACB_LLB_SIZE 1 -#define MACB_RE_OFFSET 2 +#define MACB_RE_OFFSET 2 /* Receive enable */ #define MACB_RE_SIZE 1 -#define MACB_TE_OFFSET 3 +#define MACB_TE_OFFSET 3 /* Transmit enable */ #define MACB_TE_SIZE 1 -#define MACB_MPE_OFFSET 4 +#define MACB_MPE_OFFSET 4 /* Management port enable */ #define MACB_MPE_SIZE 1 -#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */ #define MACB_CLRSTAT_SIZE 1 -#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */ #define MACB_INCSTAT_SIZE 1 -#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */ #define MACB_WESTAT_SIZE 1 -#define MACB_BP_OFFSET 8 +#define MACB_BP_OFFSET 8 /* Back pressure */ #define MACB_BP_SIZE 1 -#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_OFFSET 9 /* Start transmission */ #define MACB_TSTART_SIZE 1 -#define MACB_THALT_OFFSET 10 +#define MACB_THALT_OFFSET 10 /* Transmit halt */ #define MACB_THALT_SIZE 1 -#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ #define MACB_NCR_TPF_SIZE 1 -#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum + * pause frame + */ #define MACB_TZQ_SIZE 1 /* Bitfields in NCFGR */ -#define MACB_SPD_OFFSET 0 +#define MACB_SPD_OFFSET 0 /* Speed */ #define MACB_SPD_SIZE 1 -#define MACB_FD_OFFSET 1 +#define MACB_FD_OFFSET 1 /* Full duplex */ #define MACB_FD_SIZE 1 -#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */ #define MACB_BIT_RATE_SIZE 1 -#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_OFFSET 3 /* reserved */ #define MACB_JFRAME_SIZE 1 -#define MACB_CAF_OFFSET 4 +#define MACB_CAF_OFFSET 4 /* Copy all frames */ #define MACB_CAF_SIZE 1 -#define MACB_NBC_OFFSET 5 +#define MACB_NBC_OFFSET 5 /* No broadcast */ #define MACB_NBC_SIZE 1 -#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */ #define MACB_NCFGR_MTI_SIZE 1 -#define MACB_UNI_OFFSET 7 +#define MACB_UNI_OFFSET 7 /* Unicast hash enable */ #define MACB_UNI_SIZE 1 -#define MACB_BIG_OFFSET 8 +#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ #define MACB_BIG_SIZE 1 -#define MACB_EAE_OFFSET 9 +#define MACB_EAE_OFFSET 9 /* External address match + * enable + */ #define MACB_EAE_SIZE 1 #define MACB_CLK_OFFSET 10 #define MACB_CLK_SIZE 2 -#define MACB_RTY_OFFSET 12 +#define MACB_RTY_OFFSET 12 /* Retry test */ #define MACB_RTY_SIZE 1 -#define MACB_PAE_OFFSET 13 +#define MACB_PAE_OFFSET 13 /* Pause enable */ #define MACB_PAE_SIZE 1 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ -#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ #define MACB_RBOF_SIZE 2 -#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_OFFSET 16 /* Length field error frame + * discard + */ #define MACB_RLCE_SIZE 1 -#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_OFFSET 17 /* FCS remove */ #define MACB_DRFCS_SIZE 1 #define MACB_EFRHD_OFFSET 18 #define MACB_EFRHD_SIZE 1 @@ -166,111 +325,160 @@ #define MACB_IRXFCS_SIZE 1 /* GEM specific NCFGR bitfields. */ -#define GEM_GBE_OFFSET 10 +#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ #define GEM_GBE_SIZE 1 -#define GEM_CLK_OFFSET 18 +#define GEM_CLK_OFFSET 18 /* MDC clock division */ #define GEM_CLK_SIZE 3 -#define GEM_DBW_OFFSET 21 +#define GEM_DBW_OFFSET 21 /* Data bus width */ #define GEM_DBW_SIZE 2 #define GEM_RXCOEN_OFFSET 24 #define GEM_RXCOEN_SIZE 1 /* Constants for data bus width. */ -#define GEM_DBW32 0 -#define GEM_DBW64 1 -#define GEM_DBW128 2 +#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus + * width + */ +#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus + * width + */ +#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus + * width + */ /* Bitfields in DMACFG. */ -#define GEM_FBLDO_OFFSET 0 +#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for + * DMA data operations + */ #define GEM_FBLDO_SIZE 5 -#define GEM_ENDIA_OFFSET 7 +#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable + * for packet data accesses + */ #define GEM_ENDIA_SIZE 1 -#define GEM_RXBMS_OFFSET 8 +#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer + * memory size select + */ #define GEM_RXBMS_SIZE 2 -#define GEM_TXPBMS_OFFSET 10 +#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer + * memory size select + */ #define GEM_TXPBMS_SIZE 1 -#define GEM_TXCOEN_OFFSET 11 +#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and + * UDP checksum generation + * offload enable + */ #define GEM_TXCOEN_SIZE 1 -#define GEM_RXBS_OFFSET 16 +#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in + * AHB system memory + */ #define GEM_RXBS_SIZE 8 -#define GEM_DDRP_OFFSET 24 +#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ #define GEM_DDRP_SIZE 1 /* Bitfields in NSR */ -#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ #define MACB_NSR_LINK_SIZE 1 -#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_OFFSET 1 /* status of the mdio_in + * pin + */ #define MACB_MDIO_SIZE 1 -#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_OFFSET 2 /* The PHY management logic is + * idle (i.e. has completed) + */ #define MACB_IDLE_SIZE 1 /* Bitfields in TSR */ -#define MACB_UBR_OFFSET 0 +#define MACB_UBR_OFFSET 0 /* Used bit read */ #define MACB_UBR_SIZE 1 -#define MACB_COL_OFFSET 1 +#define MACB_COL_OFFSET 1 /* Collision occurred */ #define MACB_COL_SIZE 1 -#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */ #define MACB_TSR_RLE_SIZE 1 -#define MACB_TGO_OFFSET 3 +#define MACB_TGO_OFFSET 3 /* Transmit go */ #define MACB_TGO_SIZE 1 -#define MACB_BEX_OFFSET 4 +#define MACB_BEX_OFFSET 4 /* Transmit frame corruption + * due to AHB error + */ #define MACB_BEX_SIZE 1 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ -#define MACB_COMP_OFFSET 5 +#define MACB_COMP_OFFSET 5 /* Trnasmit complete */ #define MACB_COMP_SIZE 1 -#define MACB_UND_OFFSET 6 +#define MACB_UND_OFFSET 6 /* Trnasmit under run */ #define MACB_UND_SIZE 1 /* Bitfields in RSR */ -#define MACB_BNA_OFFSET 0 +#define MACB_BNA_OFFSET 0 /* Buffer not available */ #define MACB_BNA_SIZE 1 -#define MACB_REC_OFFSET 1 +#define MACB_REC_OFFSET 1 /* Frame received */ #define MACB_REC_SIZE 1 -#define MACB_OVR_OFFSET 2 +#define MACB_OVR_OFFSET 2 /* Receive overrun */ #define MACB_OVR_SIZE 1 /* Bitfields in ISR/IER/IDR/IMR */ -#define MACB_MFD_OFFSET 0 +#define MACB_MFD_OFFSET 0 /* Management frame sent */ #define MACB_MFD_SIZE 1 -#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_OFFSET 1 /* Receive complete */ #define MACB_RCOMP_SIZE 1 -#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_OFFSET 2 /* RX used bit read */ #define MACB_RXUBR_SIZE 1 -#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_OFFSET 3 /* TX used bit read */ #define MACB_TXUBR_SIZE 1 -#define MACB_ISR_TUND_OFFSET 4 +#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer + * under run interrupt + */ #define MACB_ISR_TUND_SIZE 1 -#define MACB_ISR_RLE_OFFSET 5 +#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded + * or late collision interrupt + */ #define MACB_ISR_RLE_SIZE 1 -#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_OFFSET 6 /* Enable transmit frame + * corruption due to AHB error + * interrupt + */ #define MACB_TXERR_SIZE 1 -#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete + * interrupt + */ #define MACB_TCOMP_SIZE 1 -#define MACB_ISR_LINK_OFFSET 9 +#define MACB_ISR_LINK_OFFSET 9 /* Enable link change + * interrupt + */ #define MACB_ISR_LINK_SIZE 1 -#define MACB_ISR_ROVR_OFFSET 10 +#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun + * interrupt + */ #define MACB_ISR_ROVR_SIZE 1 -#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK + * interrupt + */ #define MACB_HRESP_SIZE 1 -#define MACB_PFR_OFFSET 12 +#define MACB_PFR_OFFSET 12 /* Enable pause frame with + * non-zero pause quantum + * interrupt + */ #define MACB_PFR_SIZE 1 -#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_OFFSET 13 /* Enable pause time zero + * interrupt + */ #define MACB_PTZ_SIZE 1 /* Bitfields in MAN */ -#define MACB_DATA_OFFSET 0 +#define MACB_DATA_OFFSET 0 /* data */ #define MACB_DATA_SIZE 16 -#define MACB_CODE_OFFSET 16 +#define MACB_CODE_OFFSET 16 /* Must be written to 10 */ #define MACB_CODE_SIZE 2 -#define MACB_REGA_OFFSET 18 +#define MACB_REGA_OFFSET 18 /* Register address */ #define MACB_REGA_SIZE 5 -#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_OFFSET 23 /* PHY address */ #define MACB_PHYA_SIZE 5 -#define MACB_RW_OFFSET 28 +#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 + * is write. + */ #define MACB_RW_SIZE 2 -#define MACB_SOF_OFFSET 30 +#define MACB_SOF_OFFSET 30 /* Must be written to 1 for + * Clause 22 operation + */ #define MACB_SOF_SIZE 2 /* Bitfields in USRIO (AVR32) */ @@ -286,7 +494,7 @@ /* Bitfields in USRIO (AT91) */ #define MACB_RMII_OFFSET 0 #define MACB_RMII_SIZE 1 -#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ +#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ #define GEM_RGMII_SIZE 1 #define MACB_CLKEN_OFFSET 1 #define MACB_CLKEN_SIZE 1 @@ -595,6 +803,107 @@ struct gem_stats { u32 rx_udp_checksum_errors; }; +/* Describes the name and offset of an individual statistic register, as + * returned by `ethtool -S`. Also describes which net_device_stats statistics + * this register should contribute to. + */ +struct gem_statistic { + char stat_string[ETH_GSTRING_LEN]; + int offset; + u32 stat_bits; +}; + +/* Bitfield defs for net_device_stat statistics */ +#define GEM_NDS_RXERR_OFFSET 0 +#define GEM_NDS_RXLENERR_OFFSET 1 +#define GEM_NDS_RXOVERERR_OFFSET 2 +#define GEM_NDS_RXCRCERR_OFFSET 3 +#define GEM_NDS_RXFRAMEERR_OFFSET 4 +#define GEM_NDS_RXFIFOERR_OFFSET 5 +#define GEM_NDS_TXERR_OFFSET 6 +#define GEM_NDS_TXABORTEDERR_OFFSET 7 +#define GEM_NDS_TXCARRIERERR_OFFSET 8 +#define GEM_NDS_TXFIFOERR_OFFSET 9 +#define GEM_NDS_COLLISIONS_OFFSET 10 + +#define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0) +#define GEM_STAT_TITLE_BITS(name, title, bits) { \ + .stat_string = title, \ + .offset = GEM_##name, \ + .stat_bits = bits \ +} + +/* list of gem statistic registers. The names MUST match the + * corresponding GEM_* definitions. + */ +static const struct gem_statistic gem_statistics[] = { + GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */ + GEM_STAT_TITLE(TXCNT, "tx_frames"), + GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"), + GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"), + GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"), + GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"), + GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"), + GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"), + GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"), + GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"), + GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"), + GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"), + GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun", + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)), + GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames", + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), + GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames", + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), + GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions", + GEM_BIT(NDS_TXERR)| + GEM_BIT(NDS_TXABORTEDERR)| + GEM_BIT(NDS_COLLISIONS)), + GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions", + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), + GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"), + GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors", + GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), + GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */ + GEM_STAT_TITLE(RXCNT, "rx_frames"), + GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"), + GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"), + GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"), + GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"), + GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"), + GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"), + GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"), + GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"), + GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"), + GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"), + GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames", + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), + GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames", + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), + GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers", + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), + GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors", + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)), + GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors", + GEM_BIT(NDS_RXERR)), + GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors", + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)), + GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors", + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), + GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors", + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), + GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns", + GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)), + GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors", + GEM_BIT(NDS_RXERR)), + GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors", + GEM_BIT(NDS_RXERR)), + GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors", + GEM_BIT(NDS_RXERR)), +}; + +#define GEM_STATS_LEN ARRAY_SIZE(gem_statistics) + struct macb; struct macb_or_gem_ops { @@ -673,6 +982,8 @@ struct macb { dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ int skb_length; /* saved skb length for pci_unmap_single */ unsigned int max_tx_length; + + u64 ethtool_stats[GEM_STATS_LEN]; }; extern const struct ethtool_ops macb_ethtool_ops; |