diff options
Diffstat (limited to 'drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c')
| -rw-r--r-- | drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c | 1910 |
1 files changed, 201 insertions, 1709 deletions
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c b/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c index 5d681d2697cd..5dbfc0d0c369 100644 --- a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c +++ b/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c @@ -1,6 +1,10 @@ // SPDX-License-Identifier: BSD-3-Clause -/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. - * Microchip VCAP API Test VCAP Model Data +/* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries. + * Microchip VCAP test model interface for kunit testing + */ + +/* This file is autogenerated by cml-utils 2023-02-10 11:16:00 +0100. + * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada */ #include <linux/types.h> @@ -10,177 +14,6 @@ #include "vcap_model_kunit.h" /* keyfields */ -static const struct vcap_field is0_mll_keyfield[] = { - [VCAP_KF_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 0, - .width = 2, - }, - [VCAP_KF_LOOKUP_FIRST_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 2, - .width = 1, - }, - [VCAP_KF_IF_IGR_PORT] = { - .type = VCAP_FIELD_U32, - .offset = 3, - .width = 7, - }, - [VCAP_KF_8021Q_VLAN_TAGS] = { - .type = VCAP_FIELD_U32, - .offset = 10, - .width = 3, - }, - [VCAP_KF_8021Q_TPID0] = { - .type = VCAP_FIELD_U32, - .offset = 13, - .width = 3, - }, - [VCAP_KF_8021Q_VID0] = { - .type = VCAP_FIELD_U32, - .offset = 16, - .width = 12, - }, - [VCAP_KF_8021Q_TPID1] = { - .type = VCAP_FIELD_U32, - .offset = 28, - .width = 3, - }, - [VCAP_KF_8021Q_VID1] = { - .type = VCAP_FIELD_U32, - .offset = 31, - .width = 12, - }, - [VCAP_KF_L2_DMAC] = { - .type = VCAP_FIELD_U48, - .offset = 43, - .width = 48, - }, - [VCAP_KF_L2_SMAC] = { - .type = VCAP_FIELD_U48, - .offset = 91, - .width = 48, - }, - [VCAP_KF_ETYPE_MPLS] = { - .type = VCAP_FIELD_U32, - .offset = 139, - .width = 2, - }, - [VCAP_KF_L4_RNG] = { - .type = VCAP_FIELD_U32, - .offset = 141, - .width = 8, - }, -}; - -static const struct vcap_field is0_tri_vid_keyfield[] = { - [VCAP_KF_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 0, - .width = 2, - }, - [VCAP_KF_LOOKUP_FIRST_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 2, - .width = 1, - }, - [VCAP_KF_IF_IGR_PORT] = { - .type = VCAP_FIELD_U32, - .offset = 3, - .width = 7, - }, - [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 10, - .width = 2, - }, - [VCAP_KF_LOOKUP_GEN_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 12, - .width = 12, - }, - [VCAP_KF_8021Q_VLAN_TAGS] = { - .type = VCAP_FIELD_U32, - .offset = 24, - .width = 3, - }, - [VCAP_KF_8021Q_TPID0] = { - .type = VCAP_FIELD_U32, - .offset = 27, - .width = 3, - }, - [VCAP_KF_8021Q_PCP0] = { - .type = VCAP_FIELD_U32, - .offset = 30, - .width = 3, - }, - [VCAP_KF_8021Q_DEI0] = { - .type = VCAP_FIELD_BIT, - .offset = 33, - .width = 1, - }, - [VCAP_KF_8021Q_VID0] = { - .type = VCAP_FIELD_U32, - .offset = 34, - .width = 12, - }, - [VCAP_KF_8021Q_TPID1] = { - .type = VCAP_FIELD_U32, - .offset = 46, - .width = 3, - }, - [VCAP_KF_8021Q_PCP1] = { - .type = VCAP_FIELD_U32, - .offset = 49, - .width = 3, - }, - [VCAP_KF_8021Q_DEI1] = { - .type = VCAP_FIELD_BIT, - .offset = 52, - .width = 1, - }, - [VCAP_KF_8021Q_VID1] = { - .type = VCAP_FIELD_U32, - .offset = 53, - .width = 12, - }, - [VCAP_KF_8021Q_TPID2] = { - .type = VCAP_FIELD_U32, - .offset = 65, - .width = 3, - }, - [VCAP_KF_8021Q_PCP2] = { - .type = VCAP_FIELD_U32, - .offset = 68, - .width = 3, - }, - [VCAP_KF_8021Q_DEI2] = { - .type = VCAP_FIELD_BIT, - .offset = 71, - .width = 1, - }, - [VCAP_KF_8021Q_VID2] = { - .type = VCAP_FIELD_U32, - .offset = 72, - .width = 12, - }, - [VCAP_KF_L4_RNG] = { - .type = VCAP_FIELD_U32, - .offset = 84, - .width = 8, - }, - [VCAP_KF_OAM_Y1731_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 92, - .width = 1, - }, - [VCAP_KF_OAM_MEL_FLAGS] = { - .type = VCAP_FIELD_U32, - .offset = 93, - .width = 7, - }, -}; - static const struct vcap_field is0_ll_full_keyfield[] = { [VCAP_KF_TYPE] = { .type = VCAP_FIELD_U32, @@ -344,194 +177,6 @@ static const struct vcap_field is0_ll_full_keyfield[] = { }, }; -static const struct vcap_field is0_normal_keyfield[] = { - [VCAP_KF_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 0, - .width = 2, - }, - [VCAP_KF_LOOKUP_FIRST_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 2, - .width = 1, - }, - [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 3, - .width = 2, - }, - [VCAP_KF_LOOKUP_GEN_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 5, - .width = 12, - }, - [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 17, - .width = 2, - }, - [VCAP_KF_IF_IGR_PORT_MASK] = { - .type = VCAP_FIELD_U72, - .offset = 19, - .width = 65, - }, - [VCAP_KF_L2_MC_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 84, - .width = 1, - }, - [VCAP_KF_L2_BC_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 85, - .width = 1, - }, - [VCAP_KF_8021Q_VLAN_TAGS] = { - .type = VCAP_FIELD_U32, - .offset = 86, - .width = 3, - }, - [VCAP_KF_8021Q_TPID0] = { - .type = VCAP_FIELD_U32, - .offset = 89, - .width = 3, - }, - [VCAP_KF_8021Q_PCP0] = { - .type = VCAP_FIELD_U32, - .offset = 92, - .width = 3, - }, - [VCAP_KF_8021Q_DEI0] = { - .type = VCAP_FIELD_BIT, - .offset = 95, - .width = 1, - }, - [VCAP_KF_8021Q_VID0] = { - .type = VCAP_FIELD_U32, - .offset = 96, - .width = 12, - }, - [VCAP_KF_8021Q_TPID1] = { - .type = VCAP_FIELD_U32, - .offset = 108, - .width = 3, - }, - [VCAP_KF_8021Q_PCP1] = { - .type = VCAP_FIELD_U32, - .offset = 111, - .width = 3, - }, - [VCAP_KF_8021Q_DEI1] = { - .type = VCAP_FIELD_BIT, - .offset = 114, - .width = 1, - }, - [VCAP_KF_8021Q_VID1] = { - .type = VCAP_FIELD_U32, - .offset = 115, - .width = 12, - }, - [VCAP_KF_8021Q_TPID2] = { - .type = VCAP_FIELD_U32, - .offset = 127, - .width = 3, - }, - [VCAP_KF_8021Q_PCP2] = { - .type = VCAP_FIELD_U32, - .offset = 130, - .width = 3, - }, - [VCAP_KF_8021Q_DEI2] = { - .type = VCAP_FIELD_BIT, - .offset = 133, - .width = 1, - }, - [VCAP_KF_8021Q_VID2] = { - .type = VCAP_FIELD_U32, - .offset = 134, - .width = 12, - }, - [VCAP_KF_DST_ENTRY] = { - .type = VCAP_FIELD_BIT, - .offset = 146, - .width = 1, - }, - [VCAP_KF_L2_SMAC] = { - .type = VCAP_FIELD_U48, - .offset = 147, - .width = 48, - }, - [VCAP_KF_IP_MC_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 195, - .width = 1, - }, - [VCAP_KF_ETYPE_LEN_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 196, - .width = 1, - }, - [VCAP_KF_ETYPE] = { - .type = VCAP_FIELD_U32, - .offset = 197, - .width = 16, - }, - [VCAP_KF_IP_SNAP_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 213, - .width = 1, - }, - [VCAP_KF_IP4_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 214, - .width = 1, - }, - [VCAP_KF_L3_FRAGMENT_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 215, - .width = 2, - }, - [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { - .type = VCAP_FIELD_BIT, - .offset = 217, - .width = 1, - }, - [VCAP_KF_L3_OPTIONS_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 218, - .width = 1, - }, - [VCAP_KF_L3_DSCP] = { - .type = VCAP_FIELD_U32, - .offset = 219, - .width = 6, - }, - [VCAP_KF_L3_IP4_SIP] = { - .type = VCAP_FIELD_U32, - .offset = 225, - .width = 32, - }, - [VCAP_KF_TCP_UDP_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 257, - .width = 1, - }, - [VCAP_KF_TCP_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 258, - .width = 1, - }, - [VCAP_KF_L4_SPORT] = { - .type = VCAP_FIELD_U32, - .offset = 259, - .width = 16, - }, - [VCAP_KF_L4_RNG] = { - .type = VCAP_FIELD_U32, - .offset = 275, - .width = 8, - }, -}; - static const struct vcap_field is0_normal_7tuple_keyfield[] = { [VCAP_KF_TYPE] = { .type = VCAP_FIELD_BIT, @@ -1095,16 +740,6 @@ static const struct vcap_field is2_mac_etype_keyfield[] = { .offset = 85, .width = 1, }, - [VCAP_KF_L3_SMAC_SIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 86, - .width = 1, - }, - [VCAP_KF_L3_DMAC_DIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 87, - .width = 1, - }, [VCAP_KF_L3_RT_IS] = { .type = VCAP_FIELD_BIT, .offset = 88, @@ -1381,16 +1016,6 @@ static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = { .offset = 85, .width = 1, }, - [VCAP_KF_L3_SMAC_SIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 86, - .width = 1, - }, - [VCAP_KF_L3_DMAC_DIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 87, - .width = 1, - }, [VCAP_KF_L3_RT_IS] = { .type = VCAP_FIELD_BIT, .offset = 88, @@ -1594,16 +1219,6 @@ static const struct vcap_field is2_ip4_other_keyfield[] = { .offset = 85, .width = 1, }, - [VCAP_KF_L3_SMAC_SIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 86, - .width = 1, - }, - [VCAP_KF_L3_DMAC_DIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 87, - .width = 1, - }, [VCAP_KF_L3_RT_IS] = { .type = VCAP_FIELD_BIT, .offset = 88, @@ -1757,26 +1372,11 @@ static const struct vcap_field is2_ip6_std_keyfield[] = { .offset = 85, .width = 1, }, - [VCAP_KF_L3_SMAC_SIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 86, - .width = 1, - }, - [VCAP_KF_L3_DMAC_DIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 87, - .width = 1, - }, [VCAP_KF_L3_RT_IS] = { .type = VCAP_FIELD_BIT, .offset = 88, .width = 1, }, - [VCAP_KF_L3_DST_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 89, - .width = 1, - }, [VCAP_KF_L3_TTL_GT0] = { .type = VCAP_FIELD_BIT, .offset = 90, @@ -1890,16 +1490,6 @@ static const struct vcap_field is2_ip_7tuple_keyfield[] = { .offset = 116, .width = 1, }, - [VCAP_KF_L3_SMAC_SIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 117, - .width = 1, - }, - [VCAP_KF_L3_DMAC_DIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 118, - .width = 1, - }, [VCAP_KF_L3_RT_IS] = { .type = VCAP_FIELD_BIT, .offset = 119, @@ -2022,69 +1612,6 @@ static const struct vcap_field is2_ip_7tuple_keyfield[] = { }, }; -static const struct vcap_field is2_ip6_vid_keyfield[] = { - [VCAP_KF_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 0, - .width = 4, - }, - [VCAP_KF_LOOKUP_FIRST_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 4, - .width = 1, - }, - [VCAP_KF_LOOKUP_PAG] = { - .type = VCAP_FIELD_U32, - .offset = 5, - .width = 8, - }, - [VCAP_KF_ISDX_GT0_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 13, - .width = 1, - }, - [VCAP_KF_ISDX_CLS] = { - .type = VCAP_FIELD_U32, - .offset = 14, - .width = 12, - }, - [VCAP_KF_8021Q_VID_CLS] = { - .type = VCAP_FIELD_U32, - .offset = 26, - .width = 13, - }, - [VCAP_KF_L3_SMAC_SIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 39, - .width = 1, - }, - [VCAP_KF_L3_DMAC_DIP_MATCH] = { - .type = VCAP_FIELD_BIT, - .offset = 40, - .width = 1, - }, - [VCAP_KF_L3_RT_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 41, - .width = 1, - }, - [VCAP_KF_L3_DST_IS] = { - .type = VCAP_FIELD_BIT, - .offset = 42, - .width = 1, - }, - [VCAP_KF_L3_IP6_DIP] = { - .type = VCAP_FIELD_U128, - .offset = 43, - .width = 128, - }, - [VCAP_KF_L3_IP6_SIP] = { - .type = VCAP_FIELD_U128, - .offset = 171, - .width = 128, - }, -}; - static const struct vcap_field es2_mac_etype_keyfield[] = { [VCAP_KF_TYPE] = { .type = VCAP_FIELD_U32, @@ -2096,16 +1623,6 @@ static const struct vcap_field es2_mac_etype_keyfield[] = { .offset = 3, .width = 1, }, - [VCAP_KF_ACL_GRP_ID] = { - .type = VCAP_FIELD_U32, - .offset = 4, - .width = 8, - }, - [VCAP_KF_PROT_ACTIVE] = { - .type = VCAP_FIELD_BIT, - .offset = 12, - .width = 1, - }, [VCAP_KF_L2_MC_IS] = { .type = VCAP_FIELD_BIT, .offset = 13, @@ -2181,16 +1698,6 @@ static const struct vcap_field es2_mac_etype_keyfield[] = { .offset = 95, .width = 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 96, - .width = 1, - }, - [VCAP_KF_MIRROR_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 97, - .width = 2, - }, [VCAP_KF_L2_DMAC] = { .type = VCAP_FIELD_U48, .offset = 99, @@ -2239,16 +1746,6 @@ static const struct vcap_field es2_arp_keyfield[] = { .offset = 3, .width = 1, }, - [VCAP_KF_ACL_GRP_ID] = { - .type = VCAP_FIELD_U32, - .offset = 4, - .width = 8, - }, - [VCAP_KF_PROT_ACTIVE] = { - .type = VCAP_FIELD_BIT, - .offset = 12, - .width = 1, - }, [VCAP_KF_L2_MC_IS] = { .type = VCAP_FIELD_BIT, .offset = 13, @@ -2319,16 +1816,6 @@ static const struct vcap_field es2_arp_keyfield[] = { .offset = 94, .width = 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 95, - .width = 1, - }, - [VCAP_KF_MIRROR_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 96, - .width = 2, - }, [VCAP_KF_L2_SMAC] = { .type = VCAP_FIELD_U48, .offset = 98, @@ -2397,16 +1884,6 @@ static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { .offset = 3, .width = 1, }, - [VCAP_KF_ACL_GRP_ID] = { - .type = VCAP_FIELD_U32, - .offset = 4, - .width = 8, - }, - [VCAP_KF_PROT_ACTIVE] = { - .type = VCAP_FIELD_BIT, - .offset = 12, - .width = 1, - }, [VCAP_KF_L2_MC_IS] = { .type = VCAP_FIELD_BIT, .offset = 13, @@ -2482,16 +1959,6 @@ static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { .offset = 95, .width = 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 96, - .width = 1, - }, - [VCAP_KF_MIRROR_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 97, - .width = 2, - }, [VCAP_KF_IP4_IS] = { .type = VCAP_FIELD_BIT, .offset = 99, @@ -2610,16 +2077,6 @@ static const struct vcap_field es2_ip4_other_keyfield[] = { .offset = 3, .width = 1, }, - [VCAP_KF_ACL_GRP_ID] = { - .type = VCAP_FIELD_U32, - .offset = 4, - .width = 8, - }, - [VCAP_KF_PROT_ACTIVE] = { - .type = VCAP_FIELD_BIT, - .offset = 12, - .width = 1, - }, [VCAP_KF_L2_MC_IS] = { .type = VCAP_FIELD_BIT, .offset = 13, @@ -2695,16 +2152,6 @@ static const struct vcap_field es2_ip4_other_keyfield[] = { .offset = 95, .width = 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 96, - .width = 1, - }, - [VCAP_KF_MIRROR_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 97, - .width = 2, - }, [VCAP_KF_IP4_IS] = { .type = VCAP_FIELD_BIT, .offset = 99, @@ -2763,16 +2210,6 @@ static const struct vcap_field es2_ip_7tuple_keyfield[] = { .offset = 0, .width = 1, }, - [VCAP_KF_ACL_GRP_ID] = { - .type = VCAP_FIELD_U32, - .offset = 1, - .width = 8, - }, - [VCAP_KF_PROT_ACTIVE] = { - .type = VCAP_FIELD_BIT, - .offset = 9, - .width = 1, - }, [VCAP_KF_L2_MC_IS] = { .type = VCAP_FIELD_BIT, .offset = 10, @@ -2848,16 +2285,6 @@ static const struct vcap_field es2_ip_7tuple_keyfield[] = { .offset = 92, .width = 1, }, - [VCAP_KF_ES0_ISDX_KEY_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 93, - .width = 1, - }, - [VCAP_KF_MIRROR_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 94, - .width = 2, - }, [VCAP_KF_L2_DMAC] = { .type = VCAP_FIELD_U48, .offset = 96, @@ -2970,6 +2397,124 @@ static const struct vcap_field es2_ip_7tuple_keyfield[] = { }, }; +static const struct vcap_field es2_ip6_std_keyfield[] = { + [VCAP_KF_TYPE] = { + .type = VCAP_FIELD_U32, + .offset = 0, + .width = 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] = { + .type = VCAP_FIELD_BIT, + .offset = 3, + .width = 1, + }, + [VCAP_KF_L2_MC_IS] = { + .type = VCAP_FIELD_BIT, + .offset = 13, + .width = 1, + }, + [VCAP_KF_L2_BC_IS] = { + .type = VCAP_FIELD_BIT, + .offset = 14, + .width = 1, + }, + [VCAP_KF_ISDX_GT0_IS] = { + .type = VCAP_FIELD_BIT, + .offset = 15, + .width = 1, + }, + [VCAP_KF_ISDX_CLS] = { + .type = VCAP_FIELD_U32, + .offset = 16, + .width = 12, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { + .type = VCAP_FIELD_BIT, + .offset = 28, + .width = 1, + }, + [VCAP_KF_8021Q_VID_CLS] = { + .type = VCAP_FIELD_U32, + .offset = 29, + .width = 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { + .type = VCAP_FIELD_U32, + .offset = 42, + .width = 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] = { + .type = VCAP_FIELD_U32, + .offset = 45, + .width = 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] = { + .type = VCAP_FIELD_BIT, + .offset = 77, + .width = 1, + }, + [VCAP_KF_IF_IGR_PORT] = { + .type = VCAP_FIELD_U32, + .offset = 78, + .width = 9, + }, + [VCAP_KF_8021Q_PCP_CLS] = { + .type = VCAP_FIELD_U32, + .offset = 87, + .width = 3, + }, + [VCAP_KF_8021Q_DEI_CLS] = { + .type = VCAP_FIELD_BIT, + .offset = 90, + .width = 1, + }, + [VCAP_KF_COSID_CLS] = { + .type = VCAP_FIELD_U32, + .offset = 91, + .width = 3, + }, + [VCAP_KF_L3_DPL_CLS] = { + .type = VCAP_FIELD_BIT, + .offset = 94, + .width = 1, + }, + [VCAP_KF_L3_RT_IS] = { + .type = VCAP_FIELD_BIT, + .offset = 95, + .width = 1, + }, + [VCAP_KF_L3_TTL_GT0] = { + .type = VCAP_FIELD_BIT, + .offset = 99, + .width = 1, + }, + [VCAP_KF_L3_IP6_SIP] = { + .type = VCAP_FIELD_U128, + .offset = 100, + .width = 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] = { + .type = VCAP_FIELD_BIT, + .offset = 228, + .width = 1, + }, + [VCAP_KF_L3_IP_PROTO] = { + .type = VCAP_FIELD_U32, + .offset = 229, + .width = 8, + }, + [VCAP_KF_L4_RNG] = { + .type = VCAP_FIELD_U32, + .offset = 237, + .width = 16, + }, + [VCAP_KF_L3_PAYLOAD] = { + .type = VCAP_FIELD_U48, + .offset = 253, + .width = 40, + }, +}; + static const struct vcap_field es2_ip4_vid_keyfield[] = { [VCAP_KF_LOOKUP_FIRST_IS] = { .type = VCAP_FIELD_BIT, @@ -3046,7 +2591,7 @@ static const struct vcap_field es2_ip4_vid_keyfield[] = { .offset = 48, .width = 1, }, - [VCAP_KF_MIRROR_ENA] = { + [VCAP_KF_MIRROR_PROBE] = { .type = VCAP_FIELD_U32, .offset = 49, .width = 2, @@ -3143,26 +2688,11 @@ static const struct vcap_field es2_ip6_vid_keyfield[] = { /* keyfield_set */ static const struct vcap_set is0_keyfield_set[] = { - [VCAP_KFS_MLL] = { - .type_id = 0, - .sw_per_item = 3, - .sw_cnt = 4, - }, - [VCAP_KFS_TRI_VID] = { - .type_id = 0, - .sw_per_item = 2, - .sw_cnt = 6, - }, [VCAP_KFS_LL_FULL] = { .type_id = 0, .sw_per_item = 6, .sw_cnt = 2, }, - [VCAP_KFS_NORMAL] = { - .type_id = 1, - .sw_per_item = 6, - .sw_cnt = 2, - }, [VCAP_KFS_NORMAL_7TUPLE] = { .type_id = 0, .sw_per_item = 12, @@ -3216,11 +2746,6 @@ static const struct vcap_set is2_keyfield_set[] = { .sw_per_item = 12, .sw_cnt = 1, }, - [VCAP_KFS_IP6_VID] = { - .type_id = 9, - .sw_per_item = 6, - .sw_cnt = 2, - }, }; static const struct vcap_set es2_keyfield_set[] = { @@ -3249,6 +2774,11 @@ static const struct vcap_set es2_keyfield_set[] = { .sw_per_item = 12, .sw_cnt = 1, }, + [VCAP_KFS_IP6_STD] = { + .type_id = 4, + .sw_per_item = 6, + .sw_cnt = 2, + }, [VCAP_KFS_IP4_VID] = { .type_id = -1, .sw_per_item = 3, @@ -3263,10 +2793,7 @@ static const struct vcap_set es2_keyfield_set[] = { /* keyfield_set map */ static const struct vcap_field *is0_keyfield_set_map[] = { - [VCAP_KFS_MLL] = is0_mll_keyfield, - [VCAP_KFS_TRI_VID] = is0_tri_vid_keyfield, [VCAP_KFS_LL_FULL] = is0_ll_full_keyfield, - [VCAP_KFS_NORMAL] = is0_normal_keyfield, [VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield, [VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield, [VCAP_KFS_PURE_5TUPLE_IP4] = is0_pure_5tuple_ip4_keyfield, @@ -3280,7 +2807,6 @@ static const struct vcap_field *is2_keyfield_set_map[] = { [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield, [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield, [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield, - [VCAP_KFS_IP6_VID] = is2_ip6_vid_keyfield, }; static const struct vcap_field *es2_keyfield_set_map[] = { @@ -3289,16 +2815,14 @@ static const struct vcap_field *es2_keyfield_set_map[] = { [VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield, [VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield, [VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield, + [VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield, [VCAP_KFS_IP4_VID] = es2_ip4_vid_keyfield, [VCAP_KFS_IP6_VID] = es2_ip6_vid_keyfield, }; /* keyfield_set map sizes */ static int is0_keyfield_set_map_size[] = { - [VCAP_KFS_MLL] = ARRAY_SIZE(is0_mll_keyfield), - [VCAP_KFS_TRI_VID] = ARRAY_SIZE(is0_tri_vid_keyfield), [VCAP_KFS_LL_FULL] = ARRAY_SIZE(is0_ll_full_keyfield), - [VCAP_KFS_NORMAL] = ARRAY_SIZE(is0_normal_keyfield), [VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield), [VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield), [VCAP_KFS_PURE_5TUPLE_IP4] = ARRAY_SIZE(is0_pure_5tuple_ip4_keyfield), @@ -3312,7 +2836,6 @@ static int is2_keyfield_set_map_size[] = { [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield), [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield), [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield), - [VCAP_KFS_IP6_VID] = ARRAY_SIZE(is2_ip6_vid_keyfield), }; static int es2_keyfield_set_map_size[] = { @@ -3321,387 +2844,12 @@ static int es2_keyfield_set_map_size[] = { [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield), [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield), + [VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield), [VCAP_KFS_IP4_VID] = ARRAY_SIZE(es2_ip4_vid_keyfield), [VCAP_KFS_IP6_VID] = ARRAY_SIZE(es2_ip6_vid_keyfield), }; /* actionfields */ -static const struct vcap_field is0_mlbs_actionfield[] = { - [VCAP_AF_TYPE] = { - .type = VCAP_FIELD_BIT, - .offset = 0, - .width = 1, - }, - [VCAP_AF_COSID_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 1, - .width = 1, - }, - [VCAP_AF_COSID_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 2, - .width = 3, - }, - [VCAP_AF_QOS_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 5, - .width = 1, - }, - [VCAP_AF_QOS_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 6, - .width = 3, - }, - [VCAP_AF_DP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 9, - .width = 1, - }, - [VCAP_AF_DP_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 10, - .width = 2, - }, - [VCAP_AF_MAP_LOOKUP_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 12, - .width = 2, - }, - [VCAP_AF_MAP_KEY] = { - .type = VCAP_FIELD_U32, - .offset = 14, - .width = 3, - }, - [VCAP_AF_MAP_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 17, - .width = 9, - }, - [VCAP_AF_CLS_VID_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 26, - .width = 3, - }, - [VCAP_AF_GVID_ADD_REPLACE_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 29, - .width = 3, - }, - [VCAP_AF_VID_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 32, - .width = 13, - }, - [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { - .type = VCAP_FIELD_BIT, - .offset = 45, - .width = 1, - }, - [VCAP_AF_ISDX_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 46, - .width = 12, - }, - [VCAP_AF_FWD_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 58, - .width = 1, - }, - [VCAP_AF_CPU_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 59, - .width = 1, - }, - [VCAP_AF_CPU_Q] = { - .type = VCAP_FIELD_U32, - .offset = 60, - .width = 3, - }, - [VCAP_AF_OAM_Y1731_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 63, - .width = 3, - }, - [VCAP_AF_OAM_TWAMP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 66, - .width = 1, - }, - [VCAP_AF_OAM_IP_BFD_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 67, - .width = 1, - }, - [VCAP_AF_TC_LABEL] = { - .type = VCAP_FIELD_U32, - .offset = 68, - .width = 3, - }, - [VCAP_AF_TTL_LABEL] = { - .type = VCAP_FIELD_U32, - .offset = 71, - .width = 3, - }, - [VCAP_AF_NUM_VLD_LABELS] = { - .type = VCAP_FIELD_U32, - .offset = 74, - .width = 2, - }, - [VCAP_AF_FWD_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 76, - .width = 3, - }, - [VCAP_AF_MPLS_OAM_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 79, - .width = 3, - }, - [VCAP_AF_MPLS_MEP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 82, - .width = 1, - }, - [VCAP_AF_MPLS_MIP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 83, - .width = 1, - }, - [VCAP_AF_MPLS_OAM_FLAVOR] = { - .type = VCAP_FIELD_BIT, - .offset = 84, - .width = 1, - }, - [VCAP_AF_MPLS_IP_CTRL_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 85, - .width = 1, - }, - [VCAP_AF_PAG_OVERRIDE_MASK] = { - .type = VCAP_FIELD_U32, - .offset = 86, - .width = 8, - }, - [VCAP_AF_PAG_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 94, - .width = 8, - }, - [VCAP_AF_S2_KEY_SEL_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 102, - .width = 1, - }, - [VCAP_AF_S2_KEY_SEL_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 103, - .width = 6, - }, - [VCAP_AF_PIPELINE_FORCE_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 109, - .width = 2, - }, - [VCAP_AF_PIPELINE_ACT_SEL] = { - .type = VCAP_FIELD_BIT, - .offset = 111, - .width = 1, - }, - [VCAP_AF_PIPELINE_PT] = { - .type = VCAP_FIELD_U32, - .offset = 112, - .width = 5, - }, - [VCAP_AF_NXT_KEY_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 117, - .width = 5, - }, - [VCAP_AF_NXT_NORM_W16_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 122, - .width = 5, - }, - [VCAP_AF_NXT_OFFSET_FROM_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 127, - .width = 2, - }, - [VCAP_AF_NXT_TYPE_AFTER_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 129, - .width = 2, - }, - [VCAP_AF_NXT_NORMALIZE] = { - .type = VCAP_FIELD_BIT, - .offset = 131, - .width = 1, - }, - [VCAP_AF_NXT_IDX_CTRL] = { - .type = VCAP_FIELD_U32, - .offset = 132, - .width = 3, - }, - [VCAP_AF_NXT_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 135, - .width = 12, - }, -}; - -static const struct vcap_field is0_mlbs_reduced_actionfield[] = { - [VCAP_AF_TYPE] = { - .type = VCAP_FIELD_BIT, - .offset = 0, - .width = 1, - }, - [VCAP_AF_COSID_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 1, - .width = 1, - }, - [VCAP_AF_COSID_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 2, - .width = 3, - }, - [VCAP_AF_QOS_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 5, - .width = 1, - }, - [VCAP_AF_QOS_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 6, - .width = 3, - }, - [VCAP_AF_DP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 9, - .width = 1, - }, - [VCAP_AF_DP_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 10, - .width = 2, - }, - [VCAP_AF_MAP_LOOKUP_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 12, - .width = 2, - }, - [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { - .type = VCAP_FIELD_BIT, - .offset = 14, - .width = 1, - }, - [VCAP_AF_ISDX_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 15, - .width = 12, - }, - [VCAP_AF_FWD_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 27, - .width = 1, - }, - [VCAP_AF_CPU_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 28, - .width = 1, - }, - [VCAP_AF_CPU_Q] = { - .type = VCAP_FIELD_U32, - .offset = 29, - .width = 3, - }, - [VCAP_AF_TC_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 32, - .width = 1, - }, - [VCAP_AF_TTL_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 33, - .width = 1, - }, - [VCAP_AF_FWD_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 34, - .width = 3, - }, - [VCAP_AF_MPLS_OAM_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 37, - .width = 3, - }, - [VCAP_AF_MPLS_MEP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 40, - .width = 1, - }, - [VCAP_AF_MPLS_MIP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 41, - .width = 1, - }, - [VCAP_AF_MPLS_OAM_FLAVOR] = { - .type = VCAP_FIELD_BIT, - .offset = 42, - .width = 1, - }, - [VCAP_AF_MPLS_IP_CTRL_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 43, - .width = 1, - }, - [VCAP_AF_PIPELINE_FORCE_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 44, - .width = 2, - }, - [VCAP_AF_PIPELINE_ACT_SEL] = { - .type = VCAP_FIELD_BIT, - .offset = 46, - .width = 1, - }, - [VCAP_AF_PIPELINE_PT_REDUCED] = { - .type = VCAP_FIELD_U32, - .offset = 47, - .width = 3, - }, - [VCAP_AF_NXT_KEY_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 50, - .width = 5, - }, - [VCAP_AF_NXT_NORM_W32_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 55, - .width = 2, - }, - [VCAP_AF_NXT_TYPE_AFTER_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 57, - .width = 2, - }, - [VCAP_AF_NXT_NORMALIZE] = { - .type = VCAP_FIELD_BIT, - .offset = 59, - .width = 1, - }, - [VCAP_AF_NXT_IDX_CTRL] = { - .type = VCAP_FIELD_U32, - .offset = 60, - .width = 3, - }, - [VCAP_AF_NXT_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 63, - .width = 12, - }, -}; - static const struct vcap_field is0_classification_actionfield[] = { [VCAP_AF_TYPE] = { .type = VCAP_FIELD_BIT, @@ -3718,16 +2866,6 @@ static const struct vcap_field is0_classification_actionfield[] = { .offset = 2, .width = 6, }, - [VCAP_AF_COSID_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 8, - .width = 1, - }, - [VCAP_AF_COSID_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 9, - .width = 3, - }, [VCAP_AF_QOS_ENA] = { .type = VCAP_FIELD_BIT, .offset = 12, @@ -3788,46 +2926,11 @@ static const struct vcap_field is0_classification_actionfield[] = { .offset = 39, .width = 3, }, - [VCAP_AF_GVID_ADD_REPLACE_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 42, - .width = 3, - }, [VCAP_AF_VID_VAL] = { .type = VCAP_FIELD_U32, .offset = 45, .width = 13, }, - [VCAP_AF_VLAN_POP_CNT_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 58, - .width = 1, - }, - [VCAP_AF_VLAN_POP_CNT] = { - .type = VCAP_FIELD_U32, - .offset = 59, - .width = 2, - }, - [VCAP_AF_VLAN_PUSH_CNT_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 61, - .width = 1, - }, - [VCAP_AF_VLAN_PUSH_CNT] = { - .type = VCAP_FIELD_U32, - .offset = 62, - .width = 2, - }, - [VCAP_AF_TPID_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 64, - .width = 2, - }, - [VCAP_AF_VLAN_WAS_TAGGED] = { - .type = VCAP_FIELD_U32, - .offset = 66, - .width = 2, - }, [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { .type = VCAP_FIELD_BIT, .offset = 68, @@ -3838,71 +2941,6 @@ static const struct vcap_field is0_classification_actionfield[] = { .offset = 69, .width = 12, }, - [VCAP_AF_RT_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 81, - .width = 2, - }, - [VCAP_AF_LPM_AFFIX_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 83, - .width = 1, - }, - [VCAP_AF_LPM_AFFIX_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 84, - .width = 10, - }, - [VCAP_AF_RLEG_DMAC_CHK_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 94, - .width = 1, - }, - [VCAP_AF_TTL_DECR_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 95, - .width = 1, - }, - [VCAP_AF_L3_MAC_UPDATE_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 96, - .width = 1, - }, - [VCAP_AF_FWD_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 97, - .width = 1, - }, - [VCAP_AF_CPU_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 98, - .width = 1, - }, - [VCAP_AF_CPU_Q] = { - .type = VCAP_FIELD_U32, - .offset = 99, - .width = 3, - }, - [VCAP_AF_MIP_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 102, - .width = 2, - }, - [VCAP_AF_OAM_Y1731_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 104, - .width = 3, - }, - [VCAP_AF_OAM_TWAMP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 107, - .width = 1, - }, - [VCAP_AF_OAM_IP_BFD_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 108, - .width = 1, - }, [VCAP_AF_PAG_OVERRIDE_MASK] = { .type = VCAP_FIELD_U32, .offset = 109, @@ -3913,76 +2951,6 @@ static const struct vcap_field is0_classification_actionfield[] = { .offset = 117, .width = 8, }, - [VCAP_AF_S2_KEY_SEL_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 125, - .width = 1, - }, - [VCAP_AF_S2_KEY_SEL_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 126, - .width = 6, - }, - [VCAP_AF_INJ_MASQ_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 132, - .width = 1, - }, - [VCAP_AF_INJ_MASQ_PORT] = { - .type = VCAP_FIELD_U32, - .offset = 133, - .width = 7, - }, - [VCAP_AF_LPORT_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 140, - .width = 1, - }, - [VCAP_AF_INJ_MASQ_LPORT] = { - .type = VCAP_FIELD_U32, - .offset = 141, - .width = 7, - }, - [VCAP_AF_PIPELINE_FORCE_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 148, - .width = 2, - }, - [VCAP_AF_PIPELINE_ACT_SEL] = { - .type = VCAP_FIELD_BIT, - .offset = 150, - .width = 1, - }, - [VCAP_AF_PIPELINE_PT] = { - .type = VCAP_FIELD_U32, - .offset = 151, - .width = 5, - }, - [VCAP_AF_NXT_KEY_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 156, - .width = 5, - }, - [VCAP_AF_NXT_NORM_W16_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 161, - .width = 5, - }, - [VCAP_AF_NXT_OFFSET_FROM_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 166, - .width = 2, - }, - [VCAP_AF_NXT_TYPE_AFTER_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 168, - .width = 2, - }, - [VCAP_AF_NXT_NORMALIZE] = { - .type = VCAP_FIELD_BIT, - .offset = 170, - .width = 1, - }, [VCAP_AF_NXT_IDX_CTRL] = { .type = VCAP_FIELD_U32, .offset = 171, @@ -4006,16 +2974,6 @@ static const struct vcap_field is0_full_actionfield[] = { .offset = 1, .width = 6, }, - [VCAP_AF_COSID_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 7, - .width = 1, - }, - [VCAP_AF_COSID_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 8, - .width = 3, - }, [VCAP_AF_QOS_ENA] = { .type = VCAP_FIELD_BIT, .offset = 11, @@ -4076,46 +3034,11 @@ static const struct vcap_field is0_full_actionfield[] = { .offset = 38, .width = 3, }, - [VCAP_AF_GVID_ADD_REPLACE_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 41, - .width = 3, - }, [VCAP_AF_VID_VAL] = { .type = VCAP_FIELD_U32, .offset = 44, .width = 13, }, - [VCAP_AF_VLAN_POP_CNT_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 57, - .width = 1, - }, - [VCAP_AF_VLAN_POP_CNT] = { - .type = VCAP_FIELD_U32, - .offset = 58, - .width = 2, - }, - [VCAP_AF_VLAN_PUSH_CNT_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 60, - .width = 1, - }, - [VCAP_AF_VLAN_PUSH_CNT] = { - .type = VCAP_FIELD_U32, - .offset = 61, - .width = 2, - }, - [VCAP_AF_TPID_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 63, - .width = 2, - }, - [VCAP_AF_VLAN_WAS_TAGGED] = { - .type = VCAP_FIELD_U32, - .offset = 65, - .width = 2, - }, [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { .type = VCAP_FIELD_BIT, .offset = 67, @@ -4136,126 +3059,6 @@ static const struct vcap_field is0_full_actionfield[] = { .offset = 83, .width = 65, }, - [VCAP_AF_RT_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 148, - .width = 2, - }, - [VCAP_AF_LPM_AFFIX_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 150, - .width = 1, - }, - [VCAP_AF_LPM_AFFIX_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 151, - .width = 10, - }, - [VCAP_AF_RLEG_DMAC_CHK_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 161, - .width = 1, - }, - [VCAP_AF_TTL_DECR_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 162, - .width = 1, - }, - [VCAP_AF_L3_MAC_UPDATE_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 163, - .width = 1, - }, - [VCAP_AF_CPU_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 164, - .width = 1, - }, - [VCAP_AF_CPU_Q] = { - .type = VCAP_FIELD_U32, - .offset = 165, - .width = 3, - }, - [VCAP_AF_MIP_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 168, - .width = 2, - }, - [VCAP_AF_OAM_Y1731_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 170, - .width = 3, - }, - [VCAP_AF_OAM_TWAMP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 173, - .width = 1, - }, - [VCAP_AF_OAM_IP_BFD_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 174, - .width = 1, - }, - [VCAP_AF_RSVD_LBL_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 175, - .width = 4, - }, - [VCAP_AF_TC_LABEL] = { - .type = VCAP_FIELD_U32, - .offset = 179, - .width = 3, - }, - [VCAP_AF_TTL_LABEL] = { - .type = VCAP_FIELD_U32, - .offset = 182, - .width = 3, - }, - [VCAP_AF_NUM_VLD_LABELS] = { - .type = VCAP_FIELD_U32, - .offset = 185, - .width = 2, - }, - [VCAP_AF_FWD_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 187, - .width = 3, - }, - [VCAP_AF_MPLS_OAM_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 190, - .width = 3, - }, - [VCAP_AF_MPLS_MEP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 193, - .width = 1, - }, - [VCAP_AF_MPLS_MIP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 194, - .width = 1, - }, - [VCAP_AF_MPLS_OAM_FLAVOR] = { - .type = VCAP_FIELD_BIT, - .offset = 195, - .width = 1, - }, - [VCAP_AF_MPLS_IP_CTRL_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 196, - .width = 1, - }, - [VCAP_AF_CUSTOM_ACE_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 197, - .width = 5, - }, - [VCAP_AF_CUSTOM_ACE_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 202, - .width = 2, - }, [VCAP_AF_PAG_OVERRIDE_MASK] = { .type = VCAP_FIELD_U32, .offset = 204, @@ -4266,86 +3069,6 @@ static const struct vcap_field is0_full_actionfield[] = { .offset = 212, .width = 8, }, - [VCAP_AF_S2_KEY_SEL_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 220, - .width = 1, - }, - [VCAP_AF_S2_KEY_SEL_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 221, - .width = 6, - }, - [VCAP_AF_INJ_MASQ_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 227, - .width = 1, - }, - [VCAP_AF_INJ_MASQ_PORT] = { - .type = VCAP_FIELD_U32, - .offset = 228, - .width = 7, - }, - [VCAP_AF_LPORT_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 235, - .width = 1, - }, - [VCAP_AF_INJ_MASQ_LPORT] = { - .type = VCAP_FIELD_U32, - .offset = 236, - .width = 7, - }, - [VCAP_AF_MATCH_ID] = { - .type = VCAP_FIELD_U32, - .offset = 243, - .width = 16, - }, - [VCAP_AF_MATCH_ID_MASK] = { - .type = VCAP_FIELD_U32, - .offset = 259, - .width = 16, - }, - [VCAP_AF_PIPELINE_FORCE_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 275, - .width = 2, - }, - [VCAP_AF_PIPELINE_ACT_SEL] = { - .type = VCAP_FIELD_BIT, - .offset = 277, - .width = 1, - }, - [VCAP_AF_PIPELINE_PT] = { - .type = VCAP_FIELD_U32, - .offset = 278, - .width = 5, - }, - [VCAP_AF_NXT_KEY_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 283, - .width = 5, - }, - [VCAP_AF_NXT_NORM_W16_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 288, - .width = 5, - }, - [VCAP_AF_NXT_OFFSET_FROM_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 293, - .width = 2, - }, - [VCAP_AF_NXT_TYPE_AFTER_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 295, - .width = 2, - }, - [VCAP_AF_NXT_NORMALIZE] = { - .type = VCAP_FIELD_BIT, - .offset = 297, - .width = 1, - }, [VCAP_AF_NXT_IDX_CTRL] = { .type = VCAP_FIELD_U32, .offset = 298, @@ -4364,16 +3087,6 @@ static const struct vcap_field is0_class_reduced_actionfield[] = { .offset = 0, .width = 1, }, - [VCAP_AF_COSID_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 1, - .width = 1, - }, - [VCAP_AF_COSID_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 2, - .width = 3, - }, [VCAP_AF_QOS_ENA] = { .type = VCAP_FIELD_BIT, .offset = 5, @@ -4409,46 +3122,11 @@ static const struct vcap_field is0_class_reduced_actionfield[] = { .offset = 17, .width = 3, }, - [VCAP_AF_GVID_ADD_REPLACE_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 20, - .width = 3, - }, [VCAP_AF_VID_VAL] = { .type = VCAP_FIELD_U32, .offset = 23, .width = 13, }, - [VCAP_AF_VLAN_POP_CNT_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 36, - .width = 1, - }, - [VCAP_AF_VLAN_POP_CNT] = { - .type = VCAP_FIELD_U32, - .offset = 37, - .width = 2, - }, - [VCAP_AF_VLAN_PUSH_CNT_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 39, - .width = 1, - }, - [VCAP_AF_VLAN_PUSH_CNT] = { - .type = VCAP_FIELD_U32, - .offset = 40, - .width = 2, - }, - [VCAP_AF_TPID_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 42, - .width = 2, - }, - [VCAP_AF_VLAN_WAS_TAGGED] = { - .type = VCAP_FIELD_U32, - .offset = 44, - .width = 2, - }, [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { .type = VCAP_FIELD_BIT, .offset = 46, @@ -4459,61 +3137,6 @@ static const struct vcap_field is0_class_reduced_actionfield[] = { .offset = 47, .width = 12, }, - [VCAP_AF_FWD_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 59, - .width = 1, - }, - [VCAP_AF_CPU_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 60, - .width = 1, - }, - [VCAP_AF_CPU_Q] = { - .type = VCAP_FIELD_U32, - .offset = 61, - .width = 3, - }, - [VCAP_AF_MIP_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 64, - .width = 2, - }, - [VCAP_AF_OAM_Y1731_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 66, - .width = 3, - }, - [VCAP_AF_LPORT_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 69, - .width = 1, - }, - [VCAP_AF_INJ_MASQ_LPORT] = { - .type = VCAP_FIELD_U32, - .offset = 70, - .width = 7, - }, - [VCAP_AF_PIPELINE_FORCE_ENA] = { - .type = VCAP_FIELD_U32, - .offset = 77, - .width = 2, - }, - [VCAP_AF_PIPELINE_ACT_SEL] = { - .type = VCAP_FIELD_BIT, - .offset = 79, - .width = 1, - }, - [VCAP_AF_PIPELINE_PT] = { - .type = VCAP_FIELD_U32, - .offset = 80, - .width = 5, - }, - [VCAP_AF_NXT_KEY_TYPE] = { - .type = VCAP_FIELD_U32, - .offset = 85, - .width = 5, - }, [VCAP_AF_NXT_IDX_CTRL] = { .type = VCAP_FIELD_U32, .offset = 90, @@ -4527,11 +3150,6 @@ static const struct vcap_field is0_class_reduced_actionfield[] = { }; static const struct vcap_field is2_base_type_actionfield[] = { - [VCAP_AF_IS_INNER_ACL] = { - .type = VCAP_FIELD_BIT, - .offset = 0, - .width = 1, - }, [VCAP_AF_PIPELINE_FORCE_ENA] = { .type = VCAP_FIELD_BIT, .offset = 1, @@ -4562,11 +3180,6 @@ static const struct vcap_field is2_base_type_actionfield[] = { .offset = 10, .width = 3, }, - [VCAP_AF_CPU_DIS] = { - .type = VCAP_FIELD_BIT, - .offset = 13, - .width = 1, - }, [VCAP_AF_LRN_DIS] = { .type = VCAP_FIELD_BIT, .offset = 14, @@ -4592,11 +3205,6 @@ static const struct vcap_field is2_base_type_actionfield[] = { .offset = 23, .width = 1, }, - [VCAP_AF_DLB_OFFSET] = { - .type = VCAP_FIELD_U32, - .offset = 24, - .width = 3, - }, [VCAP_AF_MASK_MODE] = { .type = VCAP_FIELD_U32, .offset = 27, @@ -4607,51 +3215,11 @@ static const struct vcap_field is2_base_type_actionfield[] = { .offset = 30, .width = 68, }, - [VCAP_AF_RSDX_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 98, - .width = 1, - }, - [VCAP_AF_RSDX_VAL] = { - .type = VCAP_FIELD_U32, - .offset = 99, - .width = 12, - }, [VCAP_AF_MIRROR_PROBE] = { .type = VCAP_FIELD_U32, .offset = 111, .width = 2, }, - [VCAP_AF_REW_CMD] = { - .type = VCAP_FIELD_U32, - .offset = 113, - .width = 11, - }, - [VCAP_AF_TTL_UPDATE_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 124, - .width = 1, - }, - [VCAP_AF_SAM_SEQ_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 125, - .width = 1, - }, - [VCAP_AF_TCP_UDP_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 126, - .width = 1, - }, - [VCAP_AF_TCP_UDP_DPORT] = { - .type = VCAP_FIELD_U32, - .offset = 127, - .width = 16, - }, - [VCAP_AF_TCP_UDP_SPORT] = { - .type = VCAP_FIELD_U32, - .offset = 143, - .width = 16, - }, [VCAP_AF_MATCH_ID] = { .type = VCAP_FIELD_U32, .offset = 159, @@ -4667,56 +3235,6 @@ static const struct vcap_field is2_base_type_actionfield[] = { .offset = 191, .width = 12, }, - [VCAP_AF_SWAP_MAC_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 203, - .width = 1, - }, - [VCAP_AF_ACL_RT_MODE] = { - .type = VCAP_FIELD_U32, - .offset = 204, - .width = 4, - }, - [VCAP_AF_ACL_MAC] = { - .type = VCAP_FIELD_U48, - .offset = 208, - .width = 48, - }, - [VCAP_AF_DMAC_OFFSET_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 256, - .width = 1, - }, - [VCAP_AF_PTP_MASTER_SEL] = { - .type = VCAP_FIELD_U32, - .offset = 257, - .width = 2, - }, - [VCAP_AF_LOG_MSG_INTERVAL] = { - .type = VCAP_FIELD_U32, - .offset = 259, - .width = 4, - }, - [VCAP_AF_SIP_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 263, - .width = 5, - }, - [VCAP_AF_RLEG_STAT_IDX] = { - .type = VCAP_FIELD_U32, - .offset = 268, - .width = 3, - }, - [VCAP_AF_IGR_ACL_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 271, - .width = 1, - }, - [VCAP_AF_EGR_ACL_ENA] = { - .type = VCAP_FIELD_BIT, - .offset = 272, - .width = 1, - }, }; static const struct vcap_field es2_base_type_actionfield[] = { @@ -4794,16 +3312,6 @@ static const struct vcap_field es2_base_type_actionfield[] = { /* actionfield_set */ static const struct vcap_set is0_actionfield_set[] = { - [VCAP_AFS_MLBS] = { - .type_id = 0, - .sw_per_item = 2, - .sw_cnt = 6, - }, - [VCAP_AFS_MLBS_REDUCED] = { - .type_id = 0, - .sw_per_item = 1, - .sw_cnt = 12, - }, [VCAP_AFS_CLASSIFICATION] = { .type_id = 1, .sw_per_item = 2, @@ -4839,8 +3347,6 @@ static const struct vcap_set es2_actionfield_set[] = { /* actionfield_set map */ static const struct vcap_field *is0_actionfield_set_map[] = { - [VCAP_AFS_MLBS] = is0_mlbs_actionfield, - [VCAP_AFS_MLBS_REDUCED] = is0_mlbs_reduced_actionfield, [VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield, [VCAP_AFS_FULL] = is0_full_actionfield, [VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield, @@ -4856,8 +3362,6 @@ static const struct vcap_field *es2_actionfield_set_map[] = { /* actionfield_set map size */ static int is0_actionfield_set_map_size[] = { - [VCAP_AFS_MLBS] = ARRAY_SIZE(is0_mlbs_actionfield), - [VCAP_AFS_MLBS_REDUCED] = ARRAY_SIZE(is0_mlbs_reduced_actionfield), [VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield), [VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield), [VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield), @@ -5244,17 +3748,22 @@ static const char * const vcap_keyfield_set_names[] = { [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER", [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP", [VCAP_KFS_IP4_VID] = "VCAP_KFS_IP4_VID", + [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER", [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD", + [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP", [VCAP_KFS_IP6_VID] = "VCAP_KFS_IP6_VID", [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE", + [VCAP_KFS_ISDX] = "VCAP_KFS_ISDX", [VCAP_KFS_LL_FULL] = "VCAP_KFS_LL_FULL", [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE", - [VCAP_KFS_MLL] = "VCAP_KFS_MLL", - [VCAP_KFS_NORMAL] = "VCAP_KFS_NORMAL", + [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC", + [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP", [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4", [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE", + [VCAP_KFS_OAM] = "VCAP_KFS_OAM", [VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4", - [VCAP_KFS_TRI_VID] = "VCAP_KFS_TRI_VID", + [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4", + [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6", }; /* Actionfieldset names */ @@ -5263,9 +3772,9 @@ static const char * const vcap_actionfield_set_names[] = { [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE", [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION", [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED", + [VCAP_AFS_ES0] = "VCAP_AFS_ES0", [VCAP_AFS_FULL] = "VCAP_AFS_FULL", - [VCAP_AFS_MLBS] = "VCAP_AFS_MLBS", - [VCAP_AFS_MLBS_REDUCED] = "VCAP_AFS_MLBS_REDUCED", + [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP", }; /* Keyfield names */ @@ -5285,6 +3794,7 @@ static const char * const vcap_keyfield_names[] = { [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1", [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2", [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS", + [VCAP_KF_8021Q_TPID] = "8021Q_TPID", [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0", [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1", [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2", @@ -5303,13 +3813,13 @@ static const char * const vcap_keyfield_names[] = { [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS", [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS", [VCAP_KF_COSID_CLS] = "COSID_CLS", - [VCAP_KF_DST_ENTRY] = "DST_ENTRY", [VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA", [VCAP_KF_ETYPE] = "ETYPE", [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS", - [VCAP_KF_ETYPE_MPLS] = "ETYPE_MPLS", + [VCAP_KF_HOST_MATCH] = "HOST_MATCH", [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK", [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG", + [VCAP_KF_IF_EGR_PORT_NO] = "IF_EGR_PORT_NO", [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT", [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK", [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3", @@ -5324,17 +3834,24 @@ static const char * const vcap_keyfield_names[] = { [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS", [VCAP_KF_L2_BC_IS] = "L2_BC_IS", [VCAP_KF_L2_DMAC] = "L2_DMAC", + [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE", [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS", + [VCAP_KF_L2_LLC] = "L2_LLC", [VCAP_KF_L2_MC_IS] = "L2_MC_IS", + [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0", + [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1", + [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2", [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE", [VCAP_KF_L2_SMAC] = "L2_SMAC", + [VCAP_KF_L2_SNAP] = "L2_SNAP", [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS", - [VCAP_KF_L3_DMAC_DIP_MATCH] = "L3_DMAC_DIP_MATCH", [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS", [VCAP_KF_L3_DSCP] = "L3_DSCP", [VCAP_KF_L3_DST_IS] = "L3_DST_IS", + [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT", [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE", [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN", + [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0", [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP", [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP", [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP", @@ -5343,9 +3860,10 @@ static const char * const vcap_keyfield_names[] = { [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS", [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD", [VCAP_KF_L3_RT_IS] = "L3_RT_IS", - [VCAP_KF_L3_SMAC_SIP_MATCH] = "L3_SMAC_SIP_MATCH", [VCAP_KF_L3_TOS] = "L3_TOS", [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0", + [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM", + [VCAP_KF_L4_1588_VER] = "L4_1588_VER", [VCAP_KF_L4_ACK] = "L4_ACK", [VCAP_KF_L4_DPORT] = "L4_DPORT", [VCAP_KF_L4_FIN] = "L4_FIN", @@ -5362,9 +3880,14 @@ static const char * const vcap_keyfield_names[] = { [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX", [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL", [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG", - [VCAP_KF_MIRROR_ENA] = "MIRROR_ENA", + [VCAP_KF_MIRROR_PROBE] = "MIRROR_PROBE", [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0", + [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED", + [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS", [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS", + [VCAP_KF_OAM_MEPID] = "OAM_MEPID", + [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE", + [VCAP_KF_OAM_VER] = "OAM_VER", [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS", [VCAP_KF_PROT_ACTIVE] = "PROT_ACTIVE", [VCAP_KF_TCP_IS] = "TCP_IS", @@ -5375,50 +3898,37 @@ static const char * const vcap_keyfield_names[] = { /* Actionfield names */ static const char * const vcap_actionfield_names[] = { [VCAP_AF_NO_VALUE] = "(None)", - [VCAP_AF_ACL_MAC] = "ACL_MAC", - [VCAP_AF_ACL_RT_MODE] = "ACL_RT_MODE", + [VCAP_AF_ACL_ID] = "ACL_ID", [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL", [VCAP_AF_CNT_ID] = "CNT_ID", [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM", [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM", - [VCAP_AF_COSID_ENA] = "COSID_ENA", - [VCAP_AF_COSID_VAL] = "COSID_VAL", [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA", - [VCAP_AF_CPU_DIS] = "CPU_DIS", - [VCAP_AF_CPU_ENA] = "CPU_ENA", - [VCAP_AF_CPU_Q] = "CPU_Q", + [VCAP_AF_CPU_QU] = "CPU_QU", [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM", - [VCAP_AF_CUSTOM_ACE_ENA] = "CUSTOM_ACE_ENA", - [VCAP_AF_CUSTOM_ACE_OFFSET] = "CUSTOM_ACE_OFFSET", + [VCAP_AF_DEI_A_VAL] = "DEI_A_VAL", + [VCAP_AF_DEI_B_VAL] = "DEI_B_VAL", + [VCAP_AF_DEI_C_VAL] = "DEI_C_VAL", [VCAP_AF_DEI_ENA] = "DEI_ENA", [VCAP_AF_DEI_VAL] = "DEI_VAL", - [VCAP_AF_DLB_OFFSET] = "DLB_OFFSET", - [VCAP_AF_DMAC_OFFSET_ENA] = "DMAC_OFFSET_ENA", [VCAP_AF_DP_ENA] = "DP_ENA", [VCAP_AF_DP_VAL] = "DP_VAL", [VCAP_AF_DSCP_ENA] = "DSCP_ENA", + [VCAP_AF_DSCP_SEL] = "DSCP_SEL", [VCAP_AF_DSCP_VAL] = "DSCP_VAL", - [VCAP_AF_EGR_ACL_ENA] = "EGR_ACL_ENA", [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD", - [VCAP_AF_FWD_DIS] = "FWD_DIS", + [VCAP_AF_ESDX] = "ESDX", + [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA", [VCAP_AF_FWD_MODE] = "FWD_MODE", - [VCAP_AF_FWD_TYPE] = "FWD_TYPE", - [VCAP_AF_GVID_ADD_REPLACE_SEL] = "GVID_ADD_REPLACE_SEL", + [VCAP_AF_FWD_SEL] = "FWD_SEL", [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE", + [VCAP_AF_HOST_MATCH] = "HOST_MATCH", [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL", - [VCAP_AF_IGR_ACL_ENA] = "IGR_ACL_ENA", - [VCAP_AF_INJ_MASQ_ENA] = "INJ_MASQ_ENA", - [VCAP_AF_INJ_MASQ_LPORT] = "INJ_MASQ_LPORT", - [VCAP_AF_INJ_MASQ_PORT] = "INJ_MASQ_PORT", [VCAP_AF_INTR_ENA] = "INTR_ENA", [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL", + [VCAP_AF_ISDX_ENA] = "ISDX_ENA", [VCAP_AF_ISDX_VAL] = "ISDX_VAL", - [VCAP_AF_IS_INNER_ACL] = "IS_INNER_ACL", - [VCAP_AF_L3_MAC_UPDATE_DIS] = "L3_MAC_UPDATE_DIS", - [VCAP_AF_LOG_MSG_INTERVAL] = "LOG_MSG_INTERVAL", - [VCAP_AF_LPM_AFFIX_ENA] = "LPM_AFFIX_ENA", - [VCAP_AF_LPM_AFFIX_VAL] = "LPM_AFFIX_VAL", - [VCAP_AF_LPORT_ENA] = "LPORT_ENA", + [VCAP_AF_LOOP_ENA] = "LOOP_ENA", [VCAP_AF_LRN_DIS] = "LRN_DIS", [VCAP_AF_MAP_IDX] = "MAP_IDX", [VCAP_AF_MAP_KEY] = "MAP_KEY", @@ -5426,71 +3936,53 @@ static const char * const vcap_actionfield_names[] = { [VCAP_AF_MASK_MODE] = "MASK_MODE", [VCAP_AF_MATCH_ID] = "MATCH_ID", [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK", - [VCAP_AF_MIP_SEL] = "MIP_SEL", + [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA", [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE", [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID", - [VCAP_AF_MPLS_IP_CTRL_ENA] = "MPLS_IP_CTRL_ENA", - [VCAP_AF_MPLS_MEP_ENA] = "MPLS_MEP_ENA", - [VCAP_AF_MPLS_MIP_ENA] = "MPLS_MIP_ENA", - [VCAP_AF_MPLS_OAM_FLAVOR] = "MPLS_OAM_FLAVOR", - [VCAP_AF_MPLS_OAM_TYPE] = "MPLS_OAM_TYPE", - [VCAP_AF_NUM_VLD_LABELS] = "NUM_VLD_LABELS", [VCAP_AF_NXT_IDX] = "NXT_IDX", [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL", - [VCAP_AF_NXT_KEY_TYPE] = "NXT_KEY_TYPE", - [VCAP_AF_NXT_NORMALIZE] = "NXT_NORMALIZE", - [VCAP_AF_NXT_NORM_W16_OFFSET] = "NXT_NORM_W16_OFFSET", - [VCAP_AF_NXT_NORM_W32_OFFSET] = "NXT_NORM_W32_OFFSET", - [VCAP_AF_NXT_OFFSET_FROM_TYPE] = "NXT_OFFSET_FROM_TYPE", - [VCAP_AF_NXT_TYPE_AFTER_OFFSET] = "NXT_TYPE_AFTER_OFFSET", - [VCAP_AF_OAM_IP_BFD_ENA] = "OAM_IP_BFD_ENA", - [VCAP_AF_OAM_TWAMP_ENA] = "OAM_TWAMP_ENA", - [VCAP_AF_OAM_Y1731_SEL] = "OAM_Y1731_SEL", [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK", [VCAP_AF_PAG_VAL] = "PAG_VAL", + [VCAP_AF_PCP_A_VAL] = "PCP_A_VAL", + [VCAP_AF_PCP_B_VAL] = "PCP_B_VAL", + [VCAP_AF_PCP_C_VAL] = "PCP_C_VAL", [VCAP_AF_PCP_ENA] = "PCP_ENA", [VCAP_AF_PCP_VAL] = "PCP_VAL", - [VCAP_AF_PIPELINE_ACT_SEL] = "PIPELINE_ACT_SEL", + [VCAP_AF_PIPELINE_ACT] = "PIPELINE_ACT", [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA", [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT", - [VCAP_AF_PIPELINE_PT_REDUCED] = "PIPELINE_PT_REDUCED", [VCAP_AF_POLICE_ENA] = "POLICE_ENA", [VCAP_AF_POLICE_IDX] = "POLICE_IDX", [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK", + [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY", + [VCAP_AF_POP_VAL] = "POP_VAL", [VCAP_AF_PORT_MASK] = "PORT_MASK", - [VCAP_AF_PTP_MASTER_SEL] = "PTP_MASTER_SEL", + [VCAP_AF_PUSH_CUSTOMER_TAG] = "PUSH_CUSTOMER_TAG", + [VCAP_AF_PUSH_INNER_TAG] = "PUSH_INNER_TAG", + [VCAP_AF_PUSH_OUTER_TAG] = "PUSH_OUTER_TAG", [VCAP_AF_QOS_ENA] = "QOS_ENA", [VCAP_AF_QOS_VAL] = "QOS_VAL", - [VCAP_AF_REW_CMD] = "REW_CMD", - [VCAP_AF_RLEG_DMAC_CHK_DIS] = "RLEG_DMAC_CHK_DIS", - [VCAP_AF_RLEG_STAT_IDX] = "RLEG_STAT_IDX", - [VCAP_AF_RSDX_ENA] = "RSDX_ENA", - [VCAP_AF_RSDX_VAL] = "RSDX_VAL", - [VCAP_AF_RSVD_LBL_VAL] = "RSVD_LBL_VAL", + [VCAP_AF_REW_OP] = "REW_OP", [VCAP_AF_RT_DIS] = "RT_DIS", - [VCAP_AF_RT_SEL] = "RT_SEL", - [VCAP_AF_S2_KEY_SEL_ENA] = "S2_KEY_SEL_ENA", - [VCAP_AF_S2_KEY_SEL_IDX] = "S2_KEY_SEL_IDX", - [VCAP_AF_SAM_SEQ_ENA] = "SAM_SEQ_ENA", - [VCAP_AF_SIP_IDX] = "SIP_IDX", - [VCAP_AF_SWAP_MAC_ENA] = "SWAP_MAC_ENA", - [VCAP_AF_TCP_UDP_DPORT] = "TCP_UDP_DPORT", - [VCAP_AF_TCP_UDP_ENA] = "TCP_UDP_ENA", - [VCAP_AF_TCP_UDP_SPORT] = "TCP_UDP_SPORT", - [VCAP_AF_TC_ENA] = "TC_ENA", - [VCAP_AF_TC_LABEL] = "TC_LABEL", - [VCAP_AF_TPID_SEL] = "TPID_SEL", - [VCAP_AF_TTL_DECR_DIS] = "TTL_DECR_DIS", - [VCAP_AF_TTL_ENA] = "TTL_ENA", - [VCAP_AF_TTL_LABEL] = "TTL_LABEL", - [VCAP_AF_TTL_UPDATE_ENA] = "TTL_UPDATE_ENA", + [VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA", + [VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL", + [VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL", + [VCAP_AF_TAG_A_TPID_SEL] = "TAG_A_TPID_SEL", + [VCAP_AF_TAG_A_VID_SEL] = "TAG_A_VID_SEL", + [VCAP_AF_TAG_B_DEI_SEL] = "TAG_B_DEI_SEL", + [VCAP_AF_TAG_B_PCP_SEL] = "TAG_B_PCP_SEL", + [VCAP_AF_TAG_B_TPID_SEL] = "TAG_B_TPID_SEL", + [VCAP_AF_TAG_B_VID_SEL] = "TAG_B_VID_SEL", + [VCAP_AF_TAG_C_DEI_SEL] = "TAG_C_DEI_SEL", + [VCAP_AF_TAG_C_PCP_SEL] = "TAG_C_PCP_SEL", + [VCAP_AF_TAG_C_TPID_SEL] = "TAG_C_TPID_SEL", + [VCAP_AF_TAG_C_VID_SEL] = "TAG_C_VID_SEL", [VCAP_AF_TYPE] = "TYPE", + [VCAP_AF_UNTAG_VID_ENA] = "UNTAG_VID_ENA", + [VCAP_AF_VID_A_VAL] = "VID_A_VAL", + [VCAP_AF_VID_B_VAL] = "VID_B_VAL", + [VCAP_AF_VID_C_VAL] = "VID_C_VAL", [VCAP_AF_VID_VAL] = "VID_VAL", - [VCAP_AF_VLAN_POP_CNT] = "VLAN_POP_CNT", - [VCAP_AF_VLAN_POP_CNT_ENA] = "VLAN_POP_CNT_ENA", - [VCAP_AF_VLAN_PUSH_CNT] = "VLAN_PUSH_CNT", - [VCAP_AF_VLAN_PUSH_CNT_ENA] = "VLAN_PUSH_CNT_ENA", - [VCAP_AF_VLAN_WAS_TAGGED] = "VLAN_WAS_TAGGED", }; /* VCAPs */ |