diff options
Diffstat (limited to 'drivers/net/wireless/realtek/rtw88/phy.c')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw88/phy.c | 1265 |
1 files changed, 684 insertions, 581 deletions
diff --git a/drivers/net/wireless/realtek/rtw88/phy.c b/drivers/net/wireless/realtek/rtw88/phy.c index 404d89432c96..4ec8dcf17361 100644 --- a/drivers/net/wireless/realtek/rtw88/phy.c +++ b/drivers/net/wireless/realtek/rtw88/phy.c @@ -65,6 +65,56 @@ static const u32 db_invert_table[12][8] = { 1995262315, 2511886432U, 3162277660U, 3981071706U} }; +u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M }; +u8 rtw_ofdm_rates[] = { + DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, + DESC_RATE18M, DESC_RATE24M, DESC_RATE36M, + DESC_RATE48M, DESC_RATE54M +}; +u8 rtw_ht_1s_rates[] = { + DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, + DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5, + DESC_RATEMCS6, DESC_RATEMCS7 +}; +u8 rtw_ht_2s_rates[] = { + DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10, + DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13, + DESC_RATEMCS14, DESC_RATEMCS15 +}; +u8 rtw_vht_1s_rates[] = { + DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, + DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3, + DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5, + DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7, + DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9 +}; +u8 rtw_vht_2s_rates[] = { + DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, + DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3, + DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5, + DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7, + DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9 +}; +u8 *rtw_rate_section[RTW_RATE_SECTION_MAX] = { + rtw_cck_rates, rtw_ofdm_rates, + rtw_ht_1s_rates, rtw_ht_2s_rates, + rtw_vht_1s_rates, rtw_vht_2s_rates +}; +u8 rtw_rate_size[RTW_RATE_SECTION_MAX] = { + ARRAY_SIZE(rtw_cck_rates), + ARRAY_SIZE(rtw_ofdm_rates), + ARRAY_SIZE(rtw_ht_1s_rates), + ARRAY_SIZE(rtw_ht_2s_rates), + ARRAY_SIZE(rtw_vht_1s_rates), + ARRAY_SIZE(rtw_vht_2s_rates) +}; +static const u8 rtw_cck_size = ARRAY_SIZE(rtw_cck_rates); +static const u8 rtw_ofdm_size = ARRAY_SIZE(rtw_ofdm_rates); +static const u8 rtw_ht_1s_size = ARRAY_SIZE(rtw_ht_1s_rates); +static const u8 rtw_ht_2s_size = ARRAY_SIZE(rtw_ht_2s_rates); +static const u8 rtw_vht_1s_size = ARRAY_SIZE(rtw_vht_1s_rates); +static const u8 rtw_vht_2s_size = ARRAY_SIZE(rtw_vht_2s_rates); + enum rtw_phy_band_type { PHY_BAND_2G = 0, PHY_BAND_5G = 1, @@ -601,14 +651,19 @@ bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, direct_addr = base_addr[rf_path] + (addr << 2); mask &= RFREG_MASK; - rtw_write32_mask(rtwdev, REG_RSV_CTRL, BITS_RFC_DIRECT, DISABLE_PI); - rtw_write32_mask(rtwdev, REG_WLRF1, BITS_RFC_DIRECT, DISABLE_PI); + if (addr == RF_CFGCH) { + rtw_write32_mask(rtwdev, REG_RSV_CTRL, BITS_RFC_DIRECT, DISABLE_PI); + rtw_write32_mask(rtwdev, REG_WLRF1, BITS_RFC_DIRECT, DISABLE_PI); + } + rtw_write32_mask(rtwdev, direct_addr, mask, data); udelay(1); - rtw_write32_mask(rtwdev, REG_RSV_CTRL, BITS_RFC_DIRECT, ENABLE_PI); - rtw_write32_mask(rtwdev, REG_WLRF1, BITS_RFC_DIRECT, ENABLE_PI); + if (addr == RF_CFGCH) { + rtw_write32_mask(rtwdev, REG_RSV_CTRL, BITS_RFC_DIRECT, ENABLE_PI); + rtw_write32_mask(rtwdev, REG_WLRF1, BITS_RFC_DIRECT, ENABLE_PI); + } return true; } @@ -714,6 +769,353 @@ void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl) } } +#define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8)) + +static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i) +{ + if (rtwdev->chip->is_pwr_by_rate_dec) + return bcd_to_dec_pwr_by_rate(hex, i); + + return (hex >> (i * 8)) & 0xFF; +} + +static void +rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev, + u32 addr, u32 mask, u32 val, u8 *rate, + u8 *pwr_by_rate, u8 *rate_num) +{ + int i; + + switch (addr) { + case 0xE00: + case 0x830: + rate[0] = DESC_RATE6M; + rate[1] = DESC_RATE9M; + rate[2] = DESC_RATE12M; + rate[3] = DESC_RATE18M; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xE04: + case 0x834: + rate[0] = DESC_RATE24M; + rate[1] = DESC_RATE36M; + rate[2] = DESC_RATE48M; + rate[3] = DESC_RATE54M; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xE08: + rate[0] = DESC_RATE1M; + pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1); + *rate_num = 1; + break; + case 0x86C: + if (mask == 0xffffff00) { + rate[0] = DESC_RATE2M; + rate[1] = DESC_RATE5_5M; + rate[2] = DESC_RATE11M; + for (i = 1; i < 4; ++i) + pwr_by_rate[i - 1] = + tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 3; + } else if (mask == 0x000000ff) { + rate[0] = DESC_RATE11M; + pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0); + *rate_num = 1; + } + break; + case 0xE10: + case 0x83C: + rate[0] = DESC_RATEMCS0; + rate[1] = DESC_RATEMCS1; + rate[2] = DESC_RATEMCS2; + rate[3] = DESC_RATEMCS3; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xE14: + case 0x848: + rate[0] = DESC_RATEMCS4; + rate[1] = DESC_RATEMCS5; + rate[2] = DESC_RATEMCS6; + rate[3] = DESC_RATEMCS7; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xE18: + case 0x84C: + rate[0] = DESC_RATEMCS8; + rate[1] = DESC_RATEMCS9; + rate[2] = DESC_RATEMCS10; + rate[3] = DESC_RATEMCS11; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xE1C: + case 0x868: + rate[0] = DESC_RATEMCS12; + rate[1] = DESC_RATEMCS13; + rate[2] = DESC_RATEMCS14; + rate[3] = DESC_RATEMCS15; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0x838: + rate[0] = DESC_RATE1M; + rate[1] = DESC_RATE2M; + rate[2] = DESC_RATE5_5M; + for (i = 1; i < 4; ++i) + pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev, + val, i); + *rate_num = 3; + break; + case 0xC20: + case 0xE20: + case 0x1820: + case 0x1A20: + rate[0] = DESC_RATE1M; + rate[1] = DESC_RATE2M; + rate[2] = DESC_RATE5_5M; + rate[3] = DESC_RATE11M; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC24: + case 0xE24: + case 0x1824: + case 0x1A24: + rate[0] = DESC_RATE6M; + rate[1] = DESC_RATE9M; + rate[2] = DESC_RATE12M; + rate[3] = DESC_RATE18M; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC28: + case 0xE28: + case 0x1828: + case 0x1A28: + rate[0] = DESC_RATE24M; + rate[1] = DESC_RATE36M; + rate[2] = DESC_RATE48M; + rate[3] = DESC_RATE54M; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC2C: + case 0xE2C: + case 0x182C: + case 0x1A2C: + rate[0] = DESC_RATEMCS0; + rate[1] = DESC_RATEMCS1; + rate[2] = DESC_RATEMCS2; + rate[3] = DESC_RATEMCS3; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC30: + case 0xE30: + case 0x1830: + case 0x1A30: + rate[0] = DESC_RATEMCS4; + rate[1] = DESC_RATEMCS5; + rate[2] = DESC_RATEMCS6; + rate[3] = DESC_RATEMCS7; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC34: + case 0xE34: + case 0x1834: + case 0x1A34: + rate[0] = DESC_RATEMCS8; + rate[1] = DESC_RATEMCS9; + rate[2] = DESC_RATEMCS10; + rate[3] = DESC_RATEMCS11; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC38: + case 0xE38: + case 0x1838: + case 0x1A38: + rate[0] = DESC_RATEMCS12; + rate[1] = DESC_RATEMCS13; + rate[2] = DESC_RATEMCS14; + rate[3] = DESC_RATEMCS15; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC3C: + case 0xE3C: + case 0x183C: + case 0x1A3C: + rate[0] = DESC_RATEVHT1SS_MCS0; + rate[1] = DESC_RATEVHT1SS_MCS1; + rate[2] = DESC_RATEVHT1SS_MCS2; + rate[3] = DESC_RATEVHT1SS_MCS3; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC40: + case 0xE40: + case 0x1840: + case 0x1A40: + rate[0] = DESC_RATEVHT1SS_MCS4; + rate[1] = DESC_RATEVHT1SS_MCS5; + rate[2] = DESC_RATEVHT1SS_MCS6; + rate[3] = DESC_RATEVHT1SS_MCS7; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC44: + case 0xE44: + case 0x1844: + case 0x1A44: + rate[0] = DESC_RATEVHT1SS_MCS8; + rate[1] = DESC_RATEVHT1SS_MCS9; + rate[2] = DESC_RATEVHT2SS_MCS0; + rate[3] = DESC_RATEVHT2SS_MCS1; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC48: + case 0xE48: + case 0x1848: + case 0x1A48: + rate[0] = DESC_RATEVHT2SS_MCS2; + rate[1] = DESC_RATEVHT2SS_MCS3; + rate[2] = DESC_RATEVHT2SS_MCS4; + rate[3] = DESC_RATEVHT2SS_MCS5; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xC4C: + case 0xE4C: + case 0x184C: + case 0x1A4C: + rate[0] = DESC_RATEVHT2SS_MCS6; + rate[1] = DESC_RATEVHT2SS_MCS7; + rate[2] = DESC_RATEVHT2SS_MCS8; + rate[3] = DESC_RATEVHT2SS_MCS9; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xCD8: + case 0xED8: + case 0x18D8: + case 0x1AD8: + rate[0] = DESC_RATEMCS16; + rate[1] = DESC_RATEMCS17; + rate[2] = DESC_RATEMCS18; + rate[3] = DESC_RATEMCS19; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xCDC: + case 0xEDC: + case 0x18DC: + case 0x1ADC: + rate[0] = DESC_RATEMCS20; + rate[1] = DESC_RATEMCS21; + rate[2] = DESC_RATEMCS22; + rate[3] = DESC_RATEMCS23; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xCE0: + case 0xEE0: + case 0x18E0: + case 0x1AE0: + rate[0] = DESC_RATEVHT3SS_MCS0; + rate[1] = DESC_RATEVHT3SS_MCS1; + rate[2] = DESC_RATEVHT3SS_MCS2; + rate[3] = DESC_RATEVHT3SS_MCS3; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xCE4: + case 0xEE4: + case 0x18E4: + case 0x1AE4: + rate[0] = DESC_RATEVHT3SS_MCS4; + rate[1] = DESC_RATEVHT3SS_MCS5; + rate[2] = DESC_RATEVHT3SS_MCS6; + rate[3] = DESC_RATEVHT3SS_MCS7; + for (i = 0; i < 4; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 4; + break; + case 0xCE8: + case 0xEE8: + case 0x18E8: + case 0x1AE8: + rate[0] = DESC_RATEVHT3SS_MCS8; + rate[1] = DESC_RATEVHT3SS_MCS9; + for (i = 0; i < 2; ++i) + pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); + *rate_num = 2; + break; + default: + rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr); + break; + } +} + +static void rtw_phy_store_tx_power_by_rate(struct rtw_dev *rtwdev, + u32 band, u32 rfpath, u32 txnum, + u32 regaddr, u32 bitmask, u32 data) +{ + struct rtw_hal *hal = &rtwdev->hal; + u8 rate_num = 0; + u8 rate; + u8 rates[RTW_RF_PATH_MAX] = {0}; + s8 offset; + s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0}; + int i; + + rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data, + rates, pwr_by_rate, &rate_num); + + if (WARN_ON(rfpath >= RTW_RF_PATH_MAX || + (band != PHY_BAND_2G && band != PHY_BAND_5G) || + rate_num > RTW_RF_PATH_MAX)) + return; + + for (i = 0; i < rate_num; i++) { + offset = pwr_by_rate[i]; + rate = rates[i]; + if (band == PHY_BAND_2G) + hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset; + else if (band == PHY_BAND_5G) + hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset; + else + continue; + } +} + void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl) { const struct phy_pg_cfg_pair *p = tbl->data; @@ -726,12 +1128,142 @@ void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl) msleep(50); continue; } - phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path, - p->tx_num, p->addr, p->bitmask, - p->data); + rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path, + p->tx_num, p->addr, p->bitmask, + p->data); } } +static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = { + 36, 38, 40, 42, 44, 46, 48, /* Band 1 */ + 52, 54, 56, 58, 60, 62, 64, /* Band 2 */ + 100, 102, 104, 106, 108, 110, 112, /* Band 3 */ + 116, 118, 120, 122, 124, 126, 128, /* Band 3 */ + 132, 134, 136, 138, 140, 142, 144, /* Band 3 */ + 149, 151, 153, 155, 157, 159, 161, /* Band 4 */ + 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */ + +static int rtw_channel_to_idx(u8 band, u8 channel) +{ + int ch_idx; + u8 n_channel; + + if (band == PHY_BAND_2G) { + ch_idx = channel - 1; + n_channel = RTW_MAX_CHANNEL_NUM_2G; + } else if (band == PHY_BAND_5G) { + n_channel = RTW_MAX_CHANNEL_NUM_5G; + for (ch_idx = 0; ch_idx < n_channel; ch_idx++) + if (rtw_channel_idx_5g[ch_idx] == channel) + break; + } else { + return -1; + } + + if (ch_idx >= n_channel) + return -1; + + return ch_idx; +} + +static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band, + u8 bw, u8 rs, u8 ch, s8 pwr_limit) +{ + struct rtw_hal *hal = &rtwdev->hal; + u8 max_power_index = rtwdev->chip->max_power_index; + s8 ww; + int ch_idx; + + pwr_limit = clamp_t(s8, pwr_limit, + -max_power_index, max_power_index); + ch_idx = rtw_channel_to_idx(band, ch); + + if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX || + rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) { + WARN(1, + "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n", + regd, band, bw, rs, ch_idx, pwr_limit); + return; + } + + if (band == PHY_BAND_2G) { + hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit; + ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx]; + ww = min_t(s8, ww, pwr_limit); + hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww; + } else if (band == PHY_BAND_5G) { + hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit; + ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx]; + ww = min_t(s8, ww, pwr_limit); + hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww; + } +} + +/* cross-reference 5G power limits if values are not assigned */ +static void +rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd, + u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht) +{ + struct rtw_hal *hal = &rtwdev->hal; + u8 max_power_index = rtwdev->chip->max_power_index; + s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx]; + s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx]; + + if (lmt_ht == lmt_vht) + return; + + if (lmt_ht == max_power_index) + hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht; + + else if (lmt_vht == max_power_index) + hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht; +} + +/* cross-reference power limits for ht and vht */ +static void +rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx) +{ + u8 rs_idx, rs_ht, rs_vht; + u8 rs_cmp[2][2] = {{RTW_RATE_SECTION_HT_1S, RTW_RATE_SECTION_VHT_1S}, + {RTW_RATE_SECTION_HT_2S, RTW_RATE_SECTION_VHT_2S} }; + + for (rs_idx = 0; rs_idx < 2; rs_idx++) { + rs_ht = rs_cmp[rs_idx][0]; + rs_vht = rs_cmp[rs_idx][1]; + + rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht); + } +} + +/* cross-reference power limits for 5G channels */ +static void +rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw) +{ + u8 ch_idx; + + for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++) + rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx); +} + +/* cross-reference power limits for 20/40M bandwidth */ +static void +rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd) +{ + u8 bw; + + for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++) + rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw); +} + +/* cross-reference power limits */ +static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev) +{ + u8 regd; + + for (regd = 0; regd < RTW_REGD_MAX; regd++) + rtw_xref_txpwr_lmt_by_bw(rtwdev, regd); +} + void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl) { @@ -741,10 +1273,11 @@ void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, BUILD_BUG_ON(sizeof(struct txpwr_lmt_cfg_pair) != sizeof(u8) * 6); for (; p < end; p++) { - phy_set_tx_power_limit(rtwdev, p->regd, p->band, - p->bw, p->rs, - p->ch, p->txpwr_lmt); + rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band, + p->bw, p->rs, p->ch, p->txpwr_lmt); } + + rtw_xref_txpwr_lmt(rtwdev); } void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl, @@ -819,93 +1352,6 @@ void rtw_phy_load_tables(struct rtw_dev *rtwdev) } } -#define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8)) - -#define RTW_MAX_POWER_INDEX 0x3F - -u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M }; -u8 rtw_ofdm_rates[] = { - DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, - DESC_RATE18M, DESC_RATE24M, DESC_RATE36M, - DESC_RATE48M, DESC_RATE54M -}; -u8 rtw_ht_1s_rates[] = { - DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, - DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5, - DESC_RATEMCS6, DESC_RATEMCS7 -}; -u8 rtw_ht_2s_rates[] = { - DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10, - DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13, - DESC_RATEMCS14, DESC_RATEMCS15 -}; -u8 rtw_vht_1s_rates[] = { - DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, - DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3, - DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5, - DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7, - DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9 -}; -u8 rtw_vht_2s_rates[] = { - DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, - DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3, - DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5, - DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7, - DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9 -}; - -static u8 rtw_cck_size = ARRAY_SIZE(rtw_cck_rates); -static u8 rtw_ofdm_size = ARRAY_SIZE(rtw_ofdm_rates); -static u8 rtw_ht_1s_size = ARRAY_SIZE(rtw_ht_1s_rates); -static u8 rtw_ht_2s_size = ARRAY_SIZE(rtw_ht_2s_rates); -static u8 rtw_vht_1s_size = ARRAY_SIZE(rtw_vht_1s_rates); -static u8 rtw_vht_2s_size = ARRAY_SIZE(rtw_vht_2s_rates); -u8 *rtw_rate_section[RTW_RATE_SECTION_MAX] = { - rtw_cck_rates, rtw_ofdm_rates, - rtw_ht_1s_rates, rtw_ht_2s_rates, - rtw_vht_1s_rates, rtw_vht_2s_rates -}; -u8 rtw_rate_size[RTW_RATE_SECTION_MAX] = { - ARRAY_SIZE(rtw_cck_rates), - ARRAY_SIZE(rtw_ofdm_rates), - ARRAY_SIZE(rtw_ht_1s_rates), - ARRAY_SIZE(rtw_ht_2s_rates), - ARRAY_SIZE(rtw_vht_1s_rates), - ARRAY_SIZE(rtw_vht_2s_rates) -}; - -static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = { - 36, 38, 40, 42, 44, 46, 48, /* Band 1 */ - 52, 54, 56, 58, 60, 62, 64, /* Band 2 */ - 100, 102, 104, 106, 108, 110, 112, /* Band 3 */ - 116, 118, 120, 122, 124, 126, 128, /* Band 3 */ - 132, 134, 136, 138, 140, 142, 144, /* Band 3 */ - 149, 151, 153, 155, 157, 159, 161, /* Band 4 */ - 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */ - -static int rtw_channel_to_idx(u8 band, u8 channel) -{ - int ch_idx; - u8 n_channel; - - if (band == PHY_BAND_2G) { - ch_idx = channel - 1; - n_channel = RTW_MAX_CHANNEL_NUM_2G; - } else if (band == PHY_BAND_5G) { - n_channel = RTW_MAX_CHANNEL_NUM_5G; - for (ch_idx = 0; ch_idx < n_channel; ch_idx++) - if (rtw_channel_idx_5g[ch_idx] == channel) - break; - } else { - return -1; - } - - if (ch_idx >= n_channel) - return -1; - - return ch_idx; -} - static u8 rtw_get_channel_group(u8 channel) { switch (channel) { @@ -995,10 +1441,10 @@ static u8 rtw_get_channel_group(u8 channel) } } -static u8 phy_get_2g_tx_power_index(struct rtw_dev *rtwdev, - struct rtw_2g_txpwr_idx *pwr_idx_2g, - enum rtw_bandwidth bandwidth, - u8 rate, u8 group) +static u8 rtw_phy_get_2g_tx_power_index(struct rtw_dev *rtwdev, + struct rtw_2g_txpwr_idx *pwr_idx_2g, + enum rtw_bandwidth bandwidth, + u8 rate, u8 group) { struct rtw_chip_info *chip = rtwdev->chip; u8 tx_power; @@ -1042,10 +1488,10 @@ static u8 phy_get_2g_tx_power_index(struct rtw_dev *rtwdev, return tx_power; } -static u8 phy_get_5g_tx_power_index(struct rtw_dev *rtwdev, - struct rtw_5g_txpwr_idx *pwr_idx_5g, - enum rtw_bandwidth bandwidth, - u8 rate, u8 group) +static u8 rtw_phy_get_5g_tx_power_index(struct rtw_dev *rtwdev, + struct rtw_5g_txpwr_idx *pwr_idx_5g, + enum rtw_bandwidth bandwidth, + u8 rate, u8 group) { struct rtw_chip_info *chip = rtwdev->chip; u8 tx_power; @@ -1096,81 +1542,112 @@ static u8 phy_get_5g_tx_power_index(struct rtw_dev *rtwdev, return tx_power; } -/* set tx power level by path for each rates, note that the order of the rates - * are *very* important, bacause 8822B/8821C combines every four bytes of tx - * power index into a four-byte power index register, and calls set_tx_agc to - * write these values into hardware - */ -static -void phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev, u8 ch, u8 path) +static s8 rtw_phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band, + enum rtw_bandwidth bw, u8 rf_path, + u8 rate, u8 channel, u8 regd) { struct rtw_hal *hal = &rtwdev->hal; + u8 *cch_by_bw = hal->cch_by_bw; + s8 power_limit = (s8)rtwdev->chip->max_power_index; u8 rs; + int ch_idx; + u8 cur_bw, cur_ch; + s8 cur_lmt; - /* do not need cck rates if we are not in 2.4G */ - if (hal->current_band_type == RTW_BAND_2G) + if (regd > RTW_REGD_WW) + return power_limit; + + if (rate >= DESC_RATE1M && rate <= DESC_RATE11M) rs = RTW_RATE_SECTION_CCK; - else + else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) rs = RTW_RATE_SECTION_OFDM; + else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7) + rs = RTW_RATE_SECTION_HT_1S; + else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) + rs = RTW_RATE_SECTION_HT_2S; + else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9) + rs = RTW_RATE_SECTION_VHT_1S; + else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9) + rs = RTW_RATE_SECTION_VHT_2S; + else + goto err; - for (; rs < RTW_RATE_SECTION_MAX; rs++) - phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs); -} + /* only 20M BW with cck and ofdm */ + if (rs == RTW_RATE_SECTION_CCK || rs == RTW_RATE_SECTION_OFDM) + bw = RTW_CHANNEL_WIDTH_20; -void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel) -{ - struct rtw_chip_info *chip = rtwdev->chip; - struct rtw_hal *hal = &rtwdev->hal; - u8 path; + /* only 20/40M BW with ht */ + if (rs == RTW_RATE_SECTION_HT_1S || rs == RTW_RATE_SECTION_HT_2S) + bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40); - mutex_lock(&hal->tx_power_mutex); + /* select min power limit among [20M BW ~ current BW] */ + for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) { + cur_ch = cch_by_bw[cur_bw]; - for (path = 0; path < hal->rf_path_num; path++) - phy_set_tx_power_level_by_path(rtwdev, channel, path); + ch_idx = rtw_channel_to_idx(band, cur_ch); + if (ch_idx < 0) + goto err; - chip->ops->set_tx_power_index(rtwdev); - mutex_unlock(&hal->tx_power_mutex); -} + cur_lmt = cur_ch <= RTW_MAX_CHANNEL_NUM_2G ? + hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] : + hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx]; + + power_limit = min_t(s8, cur_lmt, power_limit); + } + + return power_limit; -s8 phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band, - enum rtw_bandwidth bandwidth, u8 rf_path, - u8 rate, u8 channel, u8 regd); +err: + WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n", + band, bw, rf_path, rate, channel); + return (s8)rtwdev->chip->max_power_index; +} -static -u8 phy_get_tx_power_index(void *adapter, u8 rf_path, u8 rate, - enum rtw_bandwidth bandwidth, u8 channel, u8 regd) +void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw, + u8 ch, u8 regd, struct rtw_power_params *pwr_param) { - struct rtw_dev *rtwdev = adapter; struct rtw_hal *hal = &rtwdev->hal; struct rtw_txpwr_idx *pwr_idx; - u8 tx_power; - u8 group; - u8 band; - s8 offset, limit; + u8 group, band; + u8 *base = &pwr_param->pwr_base; + s8 *offset = &pwr_param->pwr_offset; + s8 *limit = &pwr_param->pwr_limit; - pwr_idx = &rtwdev->efuse.txpwr_idx_table[rf_path]; - group = rtw_get_channel_group(channel); + pwr_idx = &rtwdev->efuse.txpwr_idx_table[path]; + group = rtw_get_channel_group(ch); /* base power index for 2.4G/5G */ - if (channel <= 14) { + if (ch <= 14) { band = PHY_BAND_2G; - tx_power = phy_get_2g_tx_power_index(rtwdev, - &pwr_idx->pwr_idx_2g, - bandwidth, rate, group); - offset = hal->tx_pwr_by_rate_offset_2g[rf_path][rate]; + *base = rtw_phy_get_2g_tx_power_index(rtwdev, + &pwr_idx->pwr_idx_2g, + bw, rate, group); + *offset = hal->tx_pwr_by_rate_offset_2g[path][rate]; } else { band = PHY_BAND_5G; - tx_power = phy_get_5g_tx_power_index(rtwdev, - &pwr_idx->pwr_idx_5g, - bandwidth, rate, group); - offset = hal->tx_pwr_by_rate_offset_5g[rf_path][rate]; + *base = rtw_phy_get_5g_tx_power_index(rtwdev, + &pwr_idx->pwr_idx_5g, + bw, rate, group); + *offset = hal->tx_pwr_by_rate_offset_5g[path][rate]; } - limit = phy_get_tx_power_limit(rtwdev, band, bandwidth, rf_path, - rate, channel, regd); + *limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path, + rate, ch, regd); +} + +u8 +rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate, + enum rtw_bandwidth bandwidth, u8 channel, u8 regd) +{ + struct rtw_power_params pwr_param = {0}; + u8 tx_power; + s8 offset; + + rtw_get_tx_power_params(rtwdev, rf_path, rate, bandwidth, + channel, regd, &pwr_param); - if (offset > limit) - offset = limit; + tx_power = pwr_param.pwr_base; + offset = min_t(s8, pwr_param.pwr_offset, pwr_param.pwr_limit); tx_power += offset; @@ -1180,9 +1657,9 @@ u8 phy_get_tx_power_index(void *adapter, u8 rf_path, u8 rate, return tx_power; } -void phy_set_tx_power_index_by_rs(void *adapter, u8 ch, u8 path, u8 rs) +static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev *rtwdev, + u8 ch, u8 path, u8 rs) { - struct rtw_dev *rtwdev = adapter; struct rtw_hal *hal = &rtwdev->hal; u8 regd = rtwdev->regd.txpwr_regd; u8 *rates; @@ -1200,361 +1677,51 @@ void phy_set_tx_power_index_by_rs(void *adapter, u8 ch, u8 path, u8 rs) bw = hal->current_band_width; for (i = 0; i < size; i++) { rate = rates[i]; - pwr_idx = phy_get_tx_power_index(adapter, path, rate, bw, ch, - regd); + pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, rate, + bw, ch, regd); hal->tx_pwr_tbl[path][rate] = pwr_idx; } } -static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i) -{ - if (rtwdev->chip->is_pwr_by_rate_dec) - return bcd_to_dec_pwr_by_rate(hex, i); - else - return (hex >> (i * 8)) & 0xFF; -} - -static void phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev, - u32 addr, u32 mask, - u32 val, u8 *rate, - u8 *pwr_by_rate, u8 *rate_num) +/* set tx power level by path for each rates, note that the order of the rates + * are *very* important, bacause 8822B/8821C combines every four bytes of tx + * power index into a four-byte power index register, and calls set_tx_agc to + * write these values into hardware + */ +static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev, + u8 ch, u8 path) { - int i; + struct rtw_hal *hal = &rtwdev->hal; + u8 rs; - switch (addr) { - case 0xE00: - case 0x830: - rate[0] = DESC_RATE6M; - rate[1] = DESC_RATE9M; - rate[2] = DESC_RATE12M; - rate[3] = DESC_RATE18M; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xE04: - case 0x834: - rate[0] = DESC_RATE24M; - rate[1] = DESC_RATE36M; - rate[2] = DESC_RATE48M; - rate[3] = DESC_RATE54M; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xE08: - rate[0] = DESC_RATE1M; - pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1); - *rate_num = 1; - break; - case 0x86C: - if (mask == 0xffffff00) { - rate[0] = DESC_RATE2M; - rate[1] = DESC_RATE5_5M; - rate[2] = DESC_RATE11M; - for (i = 1; i < 4; ++i) - pwr_by_rate[i - 1] = - tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 3; - } else if (mask == 0x000000ff) { - rate[0] = DESC_RATE11M; - pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0); - *rate_num = 1; - } - break; - case 0xE10: - case 0x83C: - rate[0] = DESC_RATEMCS0; - rate[1] = DESC_RATEMCS1; - rate[2] = DESC_RATEMCS2; - rate[3] = DESC_RATEMCS3; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xE14: - case 0x848: - rate[0] = DESC_RATEMCS4; - rate[1] = DESC_RATEMCS5; - rate[2] = DESC_RATEMCS6; - rate[3] = DESC_RATEMCS7; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xE18: - case 0x84C: - rate[0] = DESC_RATEMCS8; - rate[1] = DESC_RATEMCS9; - rate[2] = DESC_RATEMCS10; - rate[3] = DESC_RATEMCS11; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xE1C: - case 0x868: - rate[0] = DESC_RATEMCS12; - rate[1] = DESC_RATEMCS13; - rate[2] = DESC_RATEMCS14; - rate[3] = DESC_RATEMCS15; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; + /* do not need cck rates if we are not in 2.4G */ + if (hal->current_band_type == RTW_BAND_2G) + rs = RTW_RATE_SECTION_CCK; + else + rs = RTW_RATE_SECTION_OFDM; - break; - case 0x838: - rate[0] = DESC_RATE1M; - rate[1] = DESC_RATE2M; - rate[2] = DESC_RATE5_5M; - for (i = 1; i < 4; ++i) - pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev, - val, i); - *rate_num = 3; - break; - case 0xC20: - case 0xE20: - case 0x1820: - case 0x1A20: - rate[0] = DESC_RATE1M; - rate[1] = DESC_RATE2M; - rate[2] = DESC_RATE5_5M; - rate[3] = DESC_RATE11M; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC24: - case 0xE24: - case 0x1824: - case 0x1A24: - rate[0] = DESC_RATE6M; - rate[1] = DESC_RATE9M; - rate[2] = DESC_RATE12M; - rate[3] = DESC_RATE18M; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC28: - case 0xE28: - case 0x1828: - case 0x1A28: - rate[0] = DESC_RATE24M; - rate[1] = DESC_RATE36M; - rate[2] = DESC_RATE48M; - rate[3] = DESC_RATE54M; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC2C: - case 0xE2C: - case 0x182C: - case 0x1A2C: - rate[0] = DESC_RATEMCS0; - rate[1] = DESC_RATEMCS1; - rate[2] = DESC_RATEMCS2; - rate[3] = DESC_RATEMCS3; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC30: - case 0xE30: - case 0x1830: - case 0x1A30: - rate[0] = DESC_RATEMCS4; - rate[1] = DESC_RATEMCS5; - rate[2] = DESC_RATEMCS6; - rate[3] = DESC_RATEMCS7; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC34: - case 0xE34: - case 0x1834: - case 0x1A34: - rate[0] = DESC_RATEMCS8; - rate[1] = DESC_RATEMCS9; - rate[2] = DESC_RATEMCS10; - rate[3] = DESC_RATEMCS11; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC38: - case 0xE38: - case 0x1838: - case 0x1A38: - rate[0] = DESC_RATEMCS12; - rate[1] = DESC_RATEMCS13; - rate[2] = DESC_RATEMCS14; - rate[3] = DESC_RATEMCS15; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC3C: - case 0xE3C: - case 0x183C: - case 0x1A3C: - rate[0] = DESC_RATEVHT1SS_MCS0; - rate[1] = DESC_RATEVHT1SS_MCS1; - rate[2] = DESC_RATEVHT1SS_MCS2; - rate[3] = DESC_RATEVHT1SS_MCS3; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC40: - case 0xE40: - case 0x1840: - case 0x1A40: - rate[0] = DESC_RATEVHT1SS_MCS4; - rate[1] = DESC_RATEVHT1SS_MCS5; - rate[2] = DESC_RATEVHT1SS_MCS6; - rate[3] = DESC_RATEVHT1SS_MCS7; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC44: - case 0xE44: - case 0x1844: - case 0x1A44: - rate[0] = DESC_RATEVHT1SS_MCS8; - rate[1] = DESC_RATEVHT1SS_MCS9; - rate[2] = DESC_RATEVHT2SS_MCS0; - rate[3] = DESC_RATEVHT2SS_MCS1; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC48: - case 0xE48: - case 0x1848: - case 0x1A48: - rate[0] = DESC_RATEVHT2SS_MCS2; - rate[1] = DESC_RATEVHT2SS_MCS3; - rate[2] = DESC_RATEVHT2SS_MCS4; - rate[3] = DESC_RATEVHT2SS_MCS5; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xC4C: - case 0xE4C: - case 0x184C: - case 0x1A4C: - rate[0] = DESC_RATEVHT2SS_MCS6; - rate[1] = DESC_RATEVHT2SS_MCS7; - rate[2] = DESC_RATEVHT2SS_MCS8; - rate[3] = DESC_RATEVHT2SS_MCS9; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xCD8: - case 0xED8: - case 0x18D8: - case 0x1AD8: - rate[0] = DESC_RATEMCS16; - rate[1] = DESC_RATEMCS17; - rate[2] = DESC_RATEMCS18; - rate[3] = DESC_RATEMCS19; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xCDC: - case 0xEDC: - case 0x18DC: - case 0x1ADC: - rate[0] = DESC_RATEMCS20; - rate[1] = DESC_RATEMCS21; - rate[2] = DESC_RATEMCS22; - rate[3] = DESC_RATEMCS23; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xCE0: - case 0xEE0: - case 0x18E0: - case 0x1AE0: - rate[0] = DESC_RATEVHT3SS_MCS0; - rate[1] = DESC_RATEVHT3SS_MCS1; - rate[2] = DESC_RATEVHT3SS_MCS2; - rate[3] = DESC_RATEVHT3SS_MCS3; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xCE4: - case 0xEE4: - case 0x18E4: - case 0x1AE4: - rate[0] = DESC_RATEVHT3SS_MCS4; - rate[1] = DESC_RATEVHT3SS_MCS5; - rate[2] = DESC_RATEVHT3SS_MCS6; - rate[3] = DESC_RATEVHT3SS_MCS7; - for (i = 0; i < 4; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 4; - break; - case 0xCE8: - case 0xEE8: - case 0x18E8: - case 0x1AE8: - rate[0] = DESC_RATEVHT3SS_MCS8; - rate[1] = DESC_RATEVHT3SS_MCS9; - for (i = 0; i < 2; ++i) - pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); - *rate_num = 2; - break; - default: - rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr); - break; - } + for (; rs < RTW_RATE_SECTION_MAX; rs++) + rtw_phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs); } -void phy_store_tx_power_by_rate(void *adapter, u32 band, u32 rfpath, u32 txnum, - u32 regaddr, u32 bitmask, u32 data) +void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel) { - struct rtw_dev *rtwdev = adapter; + struct rtw_chip_info *chip = rtwdev->chip; struct rtw_hal *hal = &rtwdev->hal; - u8 rate_num = 0; - u8 rate; - u8 rates[RTW_RF_PATH_MAX] = {0}; - s8 offset; - s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0}; - int i; + u8 path; - phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data, - rates, pwr_by_rate, &rate_num); + mutex_lock(&hal->tx_power_mutex); - if (WARN_ON(rfpath >= RTW_RF_PATH_MAX || - (band != PHY_BAND_2G && band != PHY_BAND_5G) || - rate_num > RTW_RF_PATH_MAX)) - return; + for (path = 0; path < hal->rf_path_num; path++) + rtw_phy_set_tx_power_level_by_path(rtwdev, channel, path); - for (i = 0; i < rate_num; i++) { - offset = pwr_by_rate[i]; - rate = rates[i]; - if (band == PHY_BAND_2G) - hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset; - else if (band == PHY_BAND_5G) - hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset; - else - continue; - } + chip->ops->set_tx_power_index(rtwdev); + mutex_unlock(&hal->tx_power_mutex); } -static -void phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path, - u8 rs, u8 size, u8 *rates) +static void +rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path, + u8 rs, u8 size, u8 *rates) { u8 rate; u8 base_idx, rate_idx; @@ -1580,36 +1747,35 @@ void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal) u8 path; for (path = 0; path < RTW_RF_PATH_MAX; path++) { - phy_tx_power_by_rate_config_by_path(hal, path, + rtw_phy_tx_power_by_rate_config_by_path(hal, path, RTW_RATE_SECTION_CCK, rtw_cck_size, rtw_cck_rates); - phy_tx_power_by_rate_config_by_path(hal, path, + rtw_phy_tx_power_by_rate_config_by_path(hal, path, RTW_RATE_SECTION_OFDM, rtw_ofdm_size, rtw_ofdm_rates); - phy_tx_power_by_rate_config_by_path(hal, path, + rtw_phy_tx_power_by_rate_config_by_path(hal, path, RTW_RATE_SECTION_HT_1S, rtw_ht_1s_size, rtw_ht_1s_rates); - phy_tx_power_by_rate_config_by_path(hal, path, + rtw_phy_tx_power_by_rate_config_by_path(hal, path, RTW_RATE_SECTION_HT_2S, rtw_ht_2s_size, rtw_ht_2s_rates); - phy_tx_power_by_rate_config_by_path(hal, path, + rtw_phy_tx_power_by_rate_config_by_path(hal, path, RTW_RATE_SECTION_VHT_1S, rtw_vht_1s_size, rtw_vht_1s_rates); - phy_tx_power_by_rate_config_by_path(hal, path, + rtw_phy_tx_power_by_rate_config_by_path(hal, path, RTW_RATE_SECTION_VHT_2S, rtw_vht_2s_size, rtw_vht_2s_rates); } } static void -phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs) +__rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs) { - s8 base, orig; + s8 base; u8 ch; for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) { base = hal->tx_pwr_by_rate_base_2g[0][rs]; - orig = hal->tx_pwr_limit_2g[regd][bw][rs][ch]; hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base; } @@ -1623,98 +1789,34 @@ void rtw_phy_tx_power_limit_config(struct rtw_hal *hal) { u8 regd, bw, rs; + /* default at channel 1 */ + hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1; + for (regd = 0; regd < RTW_REGD_MAX; regd++) for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) - phy_tx_power_limit_config(hal, regd, bw, rs); -} - -static s8 get_tx_power_limit(struct rtw_hal *hal, u8 bw, u8 rs, u8 ch, u8 regd) -{ - if (regd > RTW_REGD_WW) - return RTW_MAX_POWER_INDEX; - - return hal->tx_pwr_limit_2g[regd][bw][rs][ch]; -} - -s8 phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band, - enum rtw_bandwidth bw, u8 rf_path, - u8 rate, u8 channel, u8 regd) -{ - struct rtw_hal *hal = &rtwdev->hal; - s8 power_limit; - u8 rs; - int ch_idx; - - if (rate >= DESC_RATE1M && rate <= DESC_RATE11M) - rs = RTW_RATE_SECTION_CCK; - else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) - rs = RTW_RATE_SECTION_OFDM; - else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7) - rs = RTW_RATE_SECTION_HT_1S; - else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) - rs = RTW_RATE_SECTION_HT_2S; - else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9) - rs = RTW_RATE_SECTION_VHT_1S; - else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9) - rs = RTW_RATE_SECTION_VHT_2S; - else - goto err; - - ch_idx = rtw_channel_to_idx(band, channel); - if (ch_idx < 0) - goto err; - - power_limit = get_tx_power_limit(hal, bw, rs, ch_idx, regd); - - return power_limit; - -err: - WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n", - band, bw, rf_path, rate, channel); - return RTW_MAX_POWER_INDEX; + __rtw_phy_tx_power_limit_config(hal, regd, bw, rs); } -void phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band, - u8 bw, u8 rs, u8 ch, s8 pwr_limit) +static void rtw_phy_init_tx_power_limit(struct rtw_dev *rtwdev, + u8 regd, u8 bw, u8 rs) { struct rtw_hal *hal = &rtwdev->hal; - int ch_idx; - - pwr_limit = clamp_t(s8, pwr_limit, - -RTW_MAX_POWER_INDEX, RTW_MAX_POWER_INDEX); - ch_idx = rtw_channel_to_idx(band, ch); - - if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX || - rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) { - WARN(1, - "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n", - regd, band, bw, rs, ch_idx, pwr_limit); - return; - } - - if (band == PHY_BAND_2G) - hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit; - else if (band == PHY_BAND_5G) - hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit; -} - -static -void rtw_hw_tx_power_limit_init(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs) -{ + s8 max_power_index = (s8)rtwdev->chip->max_power_index; u8 ch; /* 2.4G channels */ for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) - hal->tx_pwr_limit_2g[regd][bw][rs][ch] = RTW_MAX_POWER_INDEX; + hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index; /* 5G channels */ for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) - hal->tx_pwr_limit_5g[regd][bw][rs][ch] = RTW_MAX_POWER_INDEX; + hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index; } -void rtw_hw_init_tx_power(struct rtw_hal *hal) +void rtw_phy_init_tx_power(struct rtw_dev *rtwdev) { + struct rtw_hal *hal = &rtwdev->hal; u8 regd, path, rate, rs, bw; /* init tx power by rate offset */ @@ -1729,5 +1831,6 @@ void rtw_hw_init_tx_power(struct rtw_hal *hal) for (regd = 0; regd < RTW_REGD_MAX; regd++) for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) - rtw_hw_tx_power_limit_init(hal, regd, bw, rs); + rtw_phy_init_tx_power_limit(rtwdev, regd, bw, + rs); } |