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path: root/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
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Diffstat (limited to 'drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c')
-rw-r--r--drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c37
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
index f35464653f34..43dede26cc7c 100644
--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
+++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
@@ -22,8 +22,13 @@
#include "pcie-mobiveil.h"
+#define REV_1_0 (0x10)
+
/* LUT and PF control registers */
#define PCIE_LUT_OFF 0x80000
+#define PCIE_LUT_GCR 0x28
+#define PCIE_LUT_GCR_RRE 0
+
#define PCIE_PF_OFF 0xc0000
#define PCIE_PF_INT_STAT 0x18
#define PF_INT_STAT_PABRST BIT(31)
@@ -40,6 +45,7 @@ struct ls_g4_pcie {
struct mobiveil_pcie pci;
struct delayed_work dwork;
int irq;
+ u8 rev;
};
static inline u32 ls_g4_pcie_lut_readl(struct ls_g4_pcie *pcie, u32 off)
@@ -75,6 +81,15 @@ static bool ls_g4_pcie_is_bridge(struct ls_g4_pcie *pcie)
return header_type == PCI_HEADER_TYPE_BRIDGE;
}
+static int ls_g4_pcie_host_init(struct mobiveil_pcie *pci)
+{
+ struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);
+
+ pcie->rev = mobiveil_csr_readb(pci, PCI_REVISION_ID);
+
+ return 0;
+}
+
static int ls_g4_pcie_link_up(struct mobiveil_pcie *pci)
{
struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);
@@ -212,12 +227,34 @@ static void ls_g4_pcie_reset(struct work_struct *work)
ls_g4_pcie_enable_interrupt(pcie);
}
+static int ls_g4_pcie_read_other_conf(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct mobiveil_pcie *pci = bus->sysdata;
+ struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);
+ int ret;
+
+ if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID)
+ ls_g4_pcie_lut_writel(pcie, PCIE_LUT_GCR,
+ 0 << PCIE_LUT_GCR_RRE);
+
+ ret = pci_generic_config_read(bus, devfn, where, size, val);
+
+ if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID)
+ ls_g4_pcie_lut_writel(pcie, PCIE_LUT_GCR,
+ 1 << PCIE_LUT_GCR_RRE);
+
+ return ret;
+}
+
static struct mobiveil_rp_ops ls_g4_pcie_rp_ops = {
.interrupt_init = ls_g4_pcie_interrupt_init,
+ .read_other_conf = ls_g4_pcie_read_other_conf,
};
static const struct mobiveil_pab_ops ls_g4_pcie_pab_ops = {
.link_up = ls_g4_pcie_link_up,
+ .host_init = ls_g4_pcie_host_init,
};
static int __init ls_g4_pcie_probe(struct platform_device *pdev)