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path: root/drivers/pci/host/pcie-designware.h
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Diffstat (limited to 'drivers/pci/host/pcie-designware.h')
-rw-r--r--drivers/pci/host/pcie-designware.h22
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index daf81f922cda..c6256751daff 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -14,15 +14,6 @@
#ifndef _PCIE_DESIGNWARE_H
#define _PCIE_DESIGNWARE_H
-struct pcie_port_info {
- u32 cfg0_size;
- u32 cfg1_size;
- u32 io_size;
- u32 mem_size;
- phys_addr_t io_bus_addr;
- phys_addr_t mem_bus_addr;
-};
-
/*
* Maximum number of MSI IRQs can be 256 per controller. But keep
* it 32 as of now. Probably we will never need more than 32. If needed,
@@ -38,17 +29,23 @@ struct pcie_port {
u64 cfg0_base;
u64 cfg0_mod_base;
void __iomem *va_cfg0_base;
+ u32 cfg0_size;
u64 cfg1_base;
u64 cfg1_mod_base;
void __iomem *va_cfg1_base;
+ u32 cfg1_size;
u64 io_base;
u64 io_mod_base;
+ phys_addr_t io_bus_addr;
+ u32 io_size;
u64 mem_base;
u64 mem_mod_base;
+ phys_addr_t mem_bus_addr;
+ u32 mem_size;
struct resource cfg;
struct resource io;
struct resource mem;
- struct pcie_port_info config;
+ struct resource busn;
int irq;
u32 lanes;
struct pcie_host_ops *ops;
@@ -73,7 +70,10 @@ struct pcie_host_ops {
void (*host_init)(struct pcie_port *pp);
void (*msi_set_irq)(struct pcie_port *pp, int irq);
void (*msi_clear_irq)(struct pcie_port *pp, int irq);
- u32 (*get_msi_data)(struct pcie_port *pp);
+ u32 (*get_msi_addr)(struct pcie_port *pp);
+ u32 (*get_msi_data)(struct pcie_port *pp, int pos);
+ void (*scan_bus)(struct pcie_port *pp);
+ int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
};
int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);