summaryrefslogtreecommitdiff
path: root/drivers/pinctrl/freescale
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/pinctrl/freescale')
-rw-r--r--drivers/pinctrl/freescale/Kconfig109
-rw-r--r--drivers/pinctrl/freescale/Makefile2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx-scmi.c357
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.c48
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1-core.c16
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1.c228
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx27.c350
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx8mq.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx8ulp.c1
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx91.c271
-rw-r--r--drivers/pinctrl/freescale/pinctrl-mxs.c18
11 files changed, 1032 insertions, 370 deletions
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 27bdc548f3a7..4c420b21b804 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -7,9 +7,20 @@ config PINCTRL_IMX
select PINCONF
select REGMAP
+config PINCTRL_IMX_SCMI
+ tristate "i.MX95 pinctrl driver using SCMI protocol interface"
+ depends on ARM_SCMI_PROTOCOL && OF
+ select PINMUX
+ select GENERIC_PINCONF
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ help
+ i.MX95 SCMI firmware provides pinctrl protocol. This driver
+ utilizes the SCMI interface to do pinctrl configuration.
+
config PINCTRL_IMX_SCU
tristate
- depends on IMX_SCU
+ depends on IMX_SCU || COMPILE_TEST
select PINCTRL_IMX
config PINCTRL_IMX1_CORE
@@ -19,14 +30,18 @@ config PINCTRL_IMX1_CORE
config PINCTRL_IMX1
bool "IMX1 pinctrl driver"
- depends on SOC_IMX1
+ depends on OF
+ depends on SOC_IMX1 || COMPILE_TEST
+ default SOC_IMX1
select PINCTRL_IMX1_CORE
help
Say Y here to enable the imx1 pinctrl driver
config PINCTRL_IMX27
bool "IMX27 pinctrl driver"
- depends on SOC_IMX27
+ depends on OF
+ depends on SOC_IMX27 || COMPILE_TEST
+ default SOC_IMX27
select PINCTRL_IMX1_CORE
help
Say Y here to enable the imx27 pinctrl driver
@@ -35,84 +50,107 @@ config PINCTRL_IMX27
config PINCTRL_IMX25
bool "IMX25 pinctrl driver"
depends on OF
- depends on SOC_IMX25
+ depends on SOC_IMX25 || COMPILE_TEST
+ default SOC_IMX25
select PINCTRL_IMX
help
Say Y here to enable the imx25 pinctrl driver
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
- depends on SOC_IMX35
+ depends on OF
+ depends on SOC_IMX35 || COMPILE_TEST
+ default SOC_IMX35
select PINCTRL_IMX
help
Say Y here to enable the imx35 pinctrl driver
config PINCTRL_IMX50
bool "IMX50 pinctrl driver"
- depends on SOC_IMX50
+ depends on OF
+ depends on SOC_IMX50 || COMPILE_TEST
+ default SOC_IMX50
select PINCTRL_IMX
help
Say Y here to enable the imx50 pinctrl driver
config PINCTRL_IMX51
bool "IMX51 pinctrl driver"
- depends on SOC_IMX51
+ depends on OF
+ depends on SOC_IMX51 || COMPILE_TEST
+ default SOC_IMX51
select PINCTRL_IMX
help
Say Y here to enable the imx51 pinctrl driver
config PINCTRL_IMX53
bool "IMX53 pinctrl driver"
- depends on SOC_IMX53
+ depends on OF
+ depends on SOC_IMX53 || COMPILE_TEST
+ default SOC_IMX53
select PINCTRL_IMX
help
Say Y here to enable the imx53 pinctrl driver
config PINCTRL_IMX6Q
bool "IMX6Q/DL pinctrl driver"
- depends on SOC_IMX6Q
+ depends on OF
+ depends on SOC_IMX6Q || COMPILE_TEST
+ default SOC_IMX6Q
select PINCTRL_IMX
help
Say Y here to enable the imx6q/dl pinctrl driver
config PINCTRL_IMX6SL
bool "IMX6SL pinctrl driver"
- depends on SOC_IMX6SL
+ depends on OF
+ depends on SOC_IMX6SL || COMPILE_TEST
+ default SOC_IMX6SL
select PINCTRL_IMX
help
Say Y here to enable the imx6sl pinctrl driver
config PINCTRL_IMX6SLL
bool "IMX6SLL pinctrl driver"
- depends on SOC_IMX6SLL
+ depends on OF
+ depends on SOC_IMX6SLL || COMPILE_TEST
+ default SOC_IMX6SLL
select PINCTRL_IMX
help
Say Y here to enable the imx6sll pinctrl driver
config PINCTRL_IMX6SX
bool "IMX6SX pinctrl driver"
- depends on SOC_IMX6SX
+ depends on OF
+ depends on SOC_IMX6SX || COMPILE_TEST
+ default SOC_IMX6SX
select PINCTRL_IMX
help
Say Y here to enable the imx6sx pinctrl driver
config PINCTRL_IMX6UL
bool "IMX6UL pinctrl driver"
- depends on SOC_IMX6UL
+ depends on OF
+ depends on SOC_IMX6UL || COMPILE_TEST
+ default SOC_IMX6UL
select PINCTRL_IMX
help
Say Y here to enable the imx6ul pinctrl driver
config PINCTRL_IMX7D
bool "IMX7D pinctrl driver"
- depends on SOC_IMX7D
+ depends on OF
+ depends on SOC_IMX7D || COMPILE_TEST
+ default SOC_IMX7D
select PINCTRL_IMX
help
Say Y here to enable the imx7d pinctrl driver
config PINCTRL_IMX7ULP
bool "IMX7ULP pinctrl driver"
- depends on SOC_IMX7ULP
+ depends on OF
+ depends on SOC_IMX7ULP || COMPILE_TEST
+ default SOC_IMX7ULP
select PINCTRL_IMX
help
Say Y here to enable the imx7ulp pinctrl driver
@@ -120,7 +158,7 @@ config PINCTRL_IMX7ULP
config PINCTRL_IMX8MM
tristate "IMX8MM pinctrl driver"
depends on OF
- depends on SOC_IMX8M
+ depends on SOC_IMX8M || COMPILE_TEST
select PINCTRL_IMX
help
Say Y here to enable the imx8mm pinctrl driver
@@ -128,7 +166,7 @@ config PINCTRL_IMX8MM
config PINCTRL_IMX8MN
tristate "IMX8MN pinctrl driver"
depends on OF
- depends on SOC_IMX8M
+ depends on SOC_IMX8M || COMPILE_TEST
select PINCTRL_IMX
help
Say Y here to enable the imx8mn pinctrl driver
@@ -136,7 +174,7 @@ config PINCTRL_IMX8MN
config PINCTRL_IMX8MP
tristate "IMX8MP pinctrl driver"
depends on OF
- depends on SOC_IMX8M
+ depends on SOC_IMX8M || COMPILE_TEST
select PINCTRL_IMX
help
Say Y here to enable the imx8mp pinctrl driver
@@ -144,56 +182,72 @@ config PINCTRL_IMX8MP
config PINCTRL_IMX8MQ
tristate "IMX8MQ pinctrl driver"
depends on OF
- depends on SOC_IMX8M
+ depends on SOC_IMX8M || COMPILE_TEST
select PINCTRL_IMX
help
Say Y here to enable the imx8mq pinctrl driver
config PINCTRL_IMX8QM
tristate "IMX8QM pinctrl driver"
- depends on IMX_SCU && ARCH_MXC && ARM64
+ depends on OF
+ depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST
select PINCTRL_IMX_SCU
help
Say Y here to enable the imx8qm pinctrl driver
config PINCTRL_IMX8QXP
tristate "IMX8QXP pinctrl driver"
- depends on IMX_SCU && ARCH_MXC && ARM64
+ depends on OF
+ depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST
select PINCTRL_IMX_SCU
help
Say Y here to enable the imx8qxp pinctrl driver
config PINCTRL_IMX8DXL
tristate "IMX8DXL pinctrl driver"
- depends on IMX_SCU && ARCH_MXC && ARM64
+ depends on OF
+ depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST
select PINCTRL_IMX_SCU
help
Say Y here to enable the imx8dxl pinctrl driver
config PINCTRL_IMX8ULP
tristate "IMX8ULP pinctrl driver"
- depends on ARCH_MXC
+ depends on OF
+ depends on ARCH_MXC || COMPILE_TEST
select PINCTRL_IMX
help
Say Y here to enable the imx8ulp pinctrl driver
config PINCTRL_IMXRT1050
bool "IMXRT1050 pinctrl driver"
- depends on ARCH_MXC
+ depends on OF
+ depends on SOC_IMXRT || COMPILE_TEST
+ default SOC_IMXRT
select PINCTRL_IMX
help
Say Y here to enable the imxrt1050 pinctrl driver
+config PINCTRL_IMX91
+ tristate "IMX91 pinctrl driver"
+ depends on ARCH_MXC
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx91 pinctrl driver
+
config PINCTRL_IMX93
tristate "IMX93 pinctrl driver"
- depends on ARCH_MXC
+ depends on OF
+ depends on ARCH_MXC || COMPILE_TEST
select PINCTRL_IMX
help
Say Y here to enable the imx93 pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
- depends on SOC_VF610
+ depends on OF
+ depends on SOC_VF610 || COMPILE_TEST
+ default SOC_VF610
select PINCTRL_IMX
help
Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
@@ -213,7 +267,8 @@ config PINCTRL_IMX28
config PINCTRL_IMXRT1170
bool "IMXRT1170 pinctrl driver"
- depends on ARCH_MXC
+ depends on OF
+ depends on SOC_IMXRT || COMPILE_TEST
select PINCTRL_IMX
help
Say Y here to enable the imxrt1170 pinctrl driver
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 647dff060477..d27085c2b4c4 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -2,6 +2,7 @@
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
+obj-$(CONFIG_PINCTRL_IMX_SCMI) += pinctrl-imx-scmi.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
@@ -25,6 +26,7 @@ obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o
obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
+obj-$(CONFIG_PINCTRL_IMX91) += pinctrl-imx91.o
obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx-scmi.c b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c
new file mode 100644
index 000000000000..8f15c4c4dc44
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx-scmi.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * System Control and Power Interface (SCMI) Protocol based i.MX pinctrl driver
+ *
+ * Copyright 2024 NXP
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/scmi_protocol.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "../pinctrl-utils.h"
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+
+#define DRV_NAME "scmi-pinctrl-imx"
+
+struct scmi_pinctrl_imx {
+ struct device *dev;
+ struct scmi_protocol_handle *ph;
+ struct pinctrl_dev *pctldev;
+ struct pinctrl_desc pctl_desc;
+ const struct scmi_pinctrl_proto_ops *ops;
+};
+
+/* SCMI pin control types, aligned with SCMI firmware */
+#define IMX_SCMI_NUM_CFG 4
+#define IMX_SCMI_PIN_MUX 192
+#define IMX_SCMI_PIN_CONFIG 193
+#define IMX_SCMI_PIN_DAISY_ID 194
+#define IMX_SCMI_PIN_DAISY_CFG 195
+
+#define IMX_SCMI_NO_PAD_CTL BIT(31)
+#define IMX_SCMI_PAD_SION BIT(30)
+#define IMX_SCMI_IOMUXC_CONFIG_SION BIT(4)
+
+#define IMX_SCMI_PIN_SIZE 24
+
+#define IMX95_DAISY_OFF 0x408
+
+static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map,
+ unsigned int *num_maps)
+{
+ struct pinctrl_map *new_map;
+ const __be32 *list;
+ unsigned long *configs = NULL;
+ unsigned long cfg[IMX_SCMI_NUM_CFG];
+ int map_num, size, pin_size, pin_id, num_pins;
+ int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val;
+ int i, j;
+ uint32_t ncfg;
+ static uint32_t daisy_off;
+
+ if (!daisy_off) {
+ if (of_machine_is_compatible("fsl,imx95")) {
+ daisy_off = IMX95_DAISY_OFF;
+ } else {
+ dev_err(pctldev->dev, "platform not support scmi pinctrl\n");
+ return -EINVAL;
+ }
+ }
+
+ list = of_get_property(np, "fsl,pins", &size);
+ if (!list) {
+ dev_err(pctldev->dev, "no fsl,pins property in node %pOF\n", np);
+ return -EINVAL;
+ }
+
+ pin_size = IMX_SCMI_PIN_SIZE;
+
+ if (!size || size % pin_size) {
+ dev_err(pctldev->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
+ return -EINVAL;
+ }
+
+ num_pins = size / pin_size;
+ map_num = num_pins;
+
+ new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
+ GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ *map = new_map;
+ *num_maps = map_num;
+
+ /* create config map */
+ for (i = 0; i < num_pins; i++) {
+ j = 0;
+ ncfg = IMX_SCMI_NUM_CFG;
+ mux_reg = be32_to_cpu(*list++);
+ conf_reg = be32_to_cpu(*list++);
+ input_reg = be32_to_cpu(*list++);
+ mux_val = be32_to_cpu(*list++);
+ input_val = be32_to_cpu(*list++);
+ conf_val = be32_to_cpu(*list++);
+ if (conf_val & IMX_SCMI_PAD_SION)
+ mux_val |= IMX_SCMI_IOMUXC_CONFIG_SION;
+
+ pin_id = mux_reg / 4;
+
+ cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_MUX, mux_val);
+
+ if (!conf_reg || (conf_val & IMX_SCMI_NO_PAD_CTL))
+ ncfg--;
+ else
+ cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_CONFIG, conf_val);
+
+ if (!input_reg) {
+ ncfg -= 2;
+ } else {
+ cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_ID,
+ (input_reg - daisy_off) / 4);
+ cfg[j++] = pinconf_to_config_packed(IMX_SCMI_PIN_DAISY_CFG, input_val);
+ }
+
+ configs = kmemdup_array(cfg, ncfg, sizeof(unsigned long), GFP_KERNEL);
+
+ new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_id);
+ new_map[i].data.configs.configs = configs;
+ new_map[i].data.configs.num_configs = ncfg;
+ }
+
+ return 0;
+}
+
+static void pinctrl_scmi_imx_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned int num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops pinctrl_scmi_imx_pinctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .dt_node_to_map = pinctrl_scmi_imx_dt_node_to_map,
+ .dt_free_map = pinctrl_scmi_imx_dt_free_map,
+};
+
+static int pinctrl_scmi_imx_func_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int selector, unsigned int group)
+{
+ /*
+ * For i.MX SCMI PINCTRL , postpone the mux setting
+ * until config is set as they can be set together
+ * in one IPC call
+ */
+ return 0;
+}
+
+static const struct pinmux_ops pinctrl_scmi_imx_pinmux_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = pinctrl_scmi_imx_func_set_mux,
+};
+
+static int pinctrl_scmi_imx_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ int ret;
+ struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ u32 config_type, val;
+
+ if (!config)
+ return -EINVAL;
+
+ config_type = pinconf_to_config_param(*config);
+
+ ret = pmx->ops->settings_get_one(pmx->ph, pin, PIN_TYPE, config_type, &val);
+ /* Convert SCMI error code to PINCTRL expected error code */
+ if (ret == -EOPNOTSUPP)
+ return -ENOTSUPP;
+ if (ret)
+ return ret;
+
+ *config = pinconf_to_config_packed(config_type, val);
+
+ dev_dbg(pmx->dev, "pin:%s, conf:0x%x", pin_get_name(pctldev, pin), val);
+
+ return 0;
+}
+
+static int pinctrl_scmi_imx_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct scmi_pinctrl_imx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ enum scmi_pinctrl_conf_type config_type[IMX_SCMI_NUM_CFG];
+ u32 config_value[IMX_SCMI_NUM_CFG];
+ enum scmi_pinctrl_conf_type *p_config_type = config_type;
+ u32 *p_config_value = config_value;
+ int ret;
+ int i;
+
+ if (!configs || !num_configs)
+ return -EINVAL;
+
+ if (num_configs > IMX_SCMI_NUM_CFG) {
+ dev_err(pmx->dev, "num_configs(%d) too large\n", num_configs);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_configs; i++) {
+ /* cast to avoid build warning */
+ p_config_type[i] =
+ (enum scmi_pinctrl_conf_type)pinconf_to_config_param(configs[i]);
+ p_config_value[i] = pinconf_to_config_argument(configs[i]);
+
+ dev_dbg(pmx->dev, "pin: %u, type: %u, val: 0x%x\n",
+ pin, p_config_type[i], p_config_value[i]);
+ }
+
+ ret = pmx->ops->settings_conf(pmx->ph, pin, PIN_TYPE, num_configs,
+ p_config_type, p_config_value);
+ if (ret)
+ dev_err(pmx->dev, "Error set config %d\n", ret);
+
+ return ret;
+}
+
+static void pinctrl_scmi_imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int pin_id)
+{
+ unsigned long config = pinconf_to_config_packed(IMX_SCMI_PIN_CONFIG, 0);
+ int ret;
+
+ ret = pinctrl_scmi_imx_pinconf_get(pctldev, pin_id, &config);
+ if (ret)
+ config = 0;
+ else
+ config = pinconf_to_config_argument(config);
+
+ seq_printf(s, "0x%lx", config);
+}
+
+static const struct pinconf_ops pinctrl_scmi_imx_pinconf_ops = {
+ .pin_config_get = pinctrl_scmi_imx_pinconf_get,
+ .pin_config_set = pinctrl_scmi_imx_pinconf_set,
+ .pin_config_dbg_show = pinctrl_scmi_imx_pinconf_dbg_show,
+};
+
+static int
+scmi_pinctrl_imx_get_pins(struct scmi_pinctrl_imx *pmx, struct pinctrl_desc *desc)
+{
+ struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ int ret, i;
+
+ npins = pmx->ops->count_get(pmx->ph, PIN_TYPE);
+ pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ for (i = 0; i < npins; i++) {
+ pins[i].number = i;
+ /* no need free name, firmware driver handles it */
+ ret = pmx->ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name);
+ if (ret)
+ return dev_err_probe(pmx->dev, ret,
+ "Can't get name for pin %d", i);
+ }
+
+ desc->npins = npins;
+ desc->pins = pins;
+ dev_dbg(pmx->dev, "got pins %u", npins);
+
+ return 0;
+}
+
+static const char * const scmi_pinctrl_imx_allowlist[] = {
+ "fsl,imx95",
+ NULL
+};
+
+static int scmi_pinctrl_imx_probe(struct scmi_device *sdev)
+{
+ struct device *dev = &sdev->dev;
+ const struct scmi_handle *handle = sdev->handle;
+ struct scmi_pinctrl_imx *pmx;
+ struct scmi_protocol_handle *ph;
+ const struct scmi_pinctrl_proto_ops *pinctrl_ops;
+ int ret;
+
+ if (!handle)
+ return -EINVAL;
+
+ if (!of_machine_compatible_match(scmi_pinctrl_imx_allowlist))
+ return -ENODEV;
+
+ pinctrl_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PINCTRL, &ph);
+ if (IS_ERR(pinctrl_ops))
+ return PTR_ERR(pinctrl_ops);
+
+ pmx = devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL);
+ if (!pmx)
+ return -ENOMEM;
+
+ pmx->ph = ph;
+ pmx->ops = pinctrl_ops;
+
+ pmx->dev = dev;
+ pmx->pctl_desc.name = DRV_NAME;
+ pmx->pctl_desc.owner = THIS_MODULE;
+ pmx->pctl_desc.pctlops = &pinctrl_scmi_imx_pinctrl_ops;
+ pmx->pctl_desc.pmxops = &pinctrl_scmi_imx_pinmux_ops;
+ pmx->pctl_desc.confops = &pinctrl_scmi_imx_pinconf_ops;
+
+ ret = scmi_pinctrl_imx_get_pins(pmx, &pmx->pctl_desc);
+ if (ret)
+ return ret;
+
+ pmx->dev = &sdev->dev;
+
+ ret = devm_pinctrl_register_and_init(dev, &pmx->pctl_desc, pmx,
+ &pmx->pctldev);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to register pinctrl\n");
+
+ return pinctrl_enable(pmx->pctldev);
+}
+
+static const struct scmi_device_id scmi_id_table[] = {
+ { SCMI_PROTOCOL_PINCTRL, "pinctrl-imx" },
+ { }
+};
+MODULE_DEVICE_TABLE(scmi, scmi_id_table);
+
+static struct scmi_driver scmi_pinctrl_imx_driver = {
+ .name = DRV_NAME,
+ .probe = scmi_pinctrl_imx_probe,
+ .id_table = scmi_id_table,
+};
+module_scmi_driver(scmi_pinctrl_imx_driver);
+
+MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
+MODULE_DESCRIPTION("i.MX SCMI pin controller driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 2d3d80921c0d..842a1e6cbfc4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -266,7 +266,7 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
npins = grp->grp.npins;
dev_dbg(ipctl->dev, "enable function %s group %s\n",
- func->name, grp->grp.name);
+ func->func.name, grp->grp.name);
for (i = 0; i < npins; i++) {
/*
@@ -580,7 +580,6 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
u32 index)
{
struct pinctrl_dev *pctl = ipctl->pctl;
- struct device_node *child;
struct function_desc *func;
struct group_desc *grp;
const char **group_names;
@@ -593,29 +592,27 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
return -EINVAL;
/* Initialise function */
- func->name = np->name;
- func->num_group_names = of_get_child_count(np);
- if (func->num_group_names == 0) {
+ func->func.name = np->name;
+ func->func.ngroups = of_get_child_count(np);
+ if (func->func.ngroups == 0) {
dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
return -EINVAL;
}
- group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
- sizeof(char *), GFP_KERNEL);
+ group_names = devm_kcalloc(ipctl->dev, func->func.ngroups,
+ sizeof(*func->func.groups), GFP_KERNEL);
if (!group_names)
return -ENOMEM;
i = 0;
- for_each_child_of_node(np, child)
+ for_each_child_of_node_scoped(np, child)
group_names[i++] = child->name;
- func->group_names = group_names;
+ func->func.groups = group_names;
i = 0;
- for_each_child_of_node(np, child) {
+ for_each_child_of_node_scoped(np, child) {
grp = devm_kzalloc(ipctl->dev, sizeof(*grp), GFP_KERNEL);
- if (!grp) {
- of_node_put(child);
+ if (!grp)
return -ENOMEM;
- }
mutex_lock(&ipctl->mutex);
radix_tree_insert(&pctl->pin_group_tree,
@@ -635,21 +632,13 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
*/
static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
{
- struct device_node *function_np;
- struct device_node *pinctrl_np;
-
- for_each_child_of_node(np, function_np) {
- if (of_property_read_bool(function_np, "fsl,pins")) {
- of_node_put(function_np);
+ for_each_child_of_node_scoped(np, function_np) {
+ if (of_property_present(function_np, "fsl,pins"))
return true;
- }
- for_each_child_of_node(function_np, pinctrl_np) {
- if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
- of_node_put(pinctrl_np);
- of_node_put(function_np);
+ for_each_child_of_node_scoped(function_np, pinctrl_np) {
+ if (of_property_present(pinctrl_np, "fsl,pins"))
return false;
- }
}
}
@@ -757,7 +746,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(ipctl->base))
return PTR_ERR(ipctl->base);
- if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ if (of_property_present(dev_np, "fsl,input-sel")) {
np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
if (!np) {
dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
@@ -815,14 +804,14 @@ int imx_pinctrl_probe(struct platform_device *pdev,
}
EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
-static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
+static int imx_pinctrl_suspend(struct device *dev)
{
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
return pinctrl_force_sleep(ipctl->pctl);
}
-static int __maybe_unused imx_pinctrl_resume(struct device *dev)
+static int imx_pinctrl_resume(struct device *dev)
{
struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
@@ -830,8 +819,7 @@ static int __maybe_unused imx_pinctrl_resume(struct device *dev)
}
const struct dev_pm_ops imx_pinctrl_pm_ops = {
- SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
- imx_pinctrl_resume)
+ LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend, imx_pinctrl_resume)
};
EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
index 90c696046b38..af1ccfc90bff 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
@@ -508,7 +508,6 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
struct imx1_pinctrl_soc_info *info,
u32 index)
{
- struct device_node *child;
struct imx1_pmx_func *func;
struct imx1_pin_group *grp;
int ret;
@@ -531,14 +530,12 @@ static int imx1_pinctrl_parse_functions(struct device_node *np,
if (!func->groups)
return -ENOMEM;
- for_each_child_of_node(np, child) {
+ for_each_child_of_node_scoped(np, child) {
func->groups[i] = child->name;
grp = &info->groups[grp_index++];
ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
- if (ret == -ENOMEM) {
- of_node_put(child);
+ if (ret == -ENOMEM)
return ret;
- }
}
return 0;
@@ -548,7 +545,6 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
{
struct device_node *np = pdev->dev.of_node;
- struct device_node *child;
int ret;
u32 nfuncs = 0;
u32 ngroups = 0;
@@ -557,7 +553,7 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
if (!np)
return -ENODEV;
- for_each_child_of_node(np, child) {
+ for_each_child_of_node_scoped(np, child) {
++nfuncs;
ngroups += of_get_child_count(child);
}
@@ -579,12 +575,10 @@ static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
if (!info->functions || !info->groups)
return -ENOMEM;
- for_each_child_of_node(np, child) {
+ for_each_child_of_node_scoped(np, child) {
ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
- if (ret == -ENOMEM) {
- of_node_put(child);
+ if (ret == -ENOMEM)
return -ENOMEM;
- }
}
return 0;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx1.c b/drivers/pinctrl/freescale/pinctrl-imx1.c
index 1e2b0fe9ffd6..bd39cadf1f34 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx1.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1.c
@@ -12,122 +12,122 @@
#include "pinctrl-imx1.h"
#define PAD_ID(port, pin) ((port) * 32 + (pin))
-#define PA 0
-#define PB 1
-#define PC 2
-#define PD 3
+#define IMX1_PA 0
+#define IMX1_PB 1
+#define IMX1_PC 2
+#define IMX1_PD 3
enum imx1_pads {
- MX1_PAD_A24 = PAD_ID(PA, 0),
- MX1_PAD_TIN = PAD_ID(PA, 1),
- MX1_PAD_PWMO = PAD_ID(PA, 2),
- MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
- MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
- MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
- MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
- MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
- MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
- MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
- MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
- MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
- MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
- MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
- MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
- MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
- MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
- MX1_PAD_DTACK = PAD_ID(PA, 17),
- MX1_PAD_BCLK = PAD_ID(PA, 18),
- MX1_PAD_LBA = PAD_ID(PA, 19),
- MX1_PAD_ECB = PAD_ID(PA, 20),
- MX1_PAD_A0 = PAD_ID(PA, 21),
- MX1_PAD_CS4 = PAD_ID(PA, 22),
- MX1_PAD_CS5 = PAD_ID(PA, 23),
- MX1_PAD_A16 = PAD_ID(PA, 24),
- MX1_PAD_A17 = PAD_ID(PA, 25),
- MX1_PAD_A18 = PAD_ID(PA, 26),
- MX1_PAD_A19 = PAD_ID(PA, 27),
- MX1_PAD_A20 = PAD_ID(PA, 28),
- MX1_PAD_A21 = PAD_ID(PA, 29),
- MX1_PAD_A22 = PAD_ID(PA, 30),
- MX1_PAD_A23 = PAD_ID(PA, 31),
- MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
- MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
- MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
- MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
- MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
- MX1_PAD_SD_CMD = PAD_ID(PB, 13),
- MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
- MX1_PAD_SIM_PD = PAD_ID(PB, 15),
- MX1_PAD_SIM_TX = PAD_ID(PB, 16),
- MX1_PAD_SIM_RX = PAD_ID(PB, 17),
- MX1_PAD_SIM_RST = PAD_ID(PB, 18),
- MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
- MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
- MX1_PAD_USBD_OE = PAD_ID(PB, 21),
- MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
- MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
- MX1_PAD_USBD_VP = PAD_ID(PB, 24),
- MX1_PAD_USBD_VM = PAD_ID(PB, 25),
- MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
- MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
- MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
- MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
- MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
- MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
- MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
- MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
- MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
- MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
- MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
- MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
- MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
- MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
- MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
- MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
- MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
- MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
- MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
- MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
- MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
- MX1_PAD_BT13 = PAD_ID(PC, 19),
- MX1_PAD_BT12 = PAD_ID(PC, 20),
- MX1_PAD_BT11 = PAD_ID(PC, 21),
- MX1_PAD_BT10 = PAD_ID(PC, 22),
- MX1_PAD_BT9 = PAD_ID(PC, 23),
- MX1_PAD_BT8 = PAD_ID(PC, 24),
- MX1_PAD_BT7 = PAD_ID(PC, 25),
- MX1_PAD_BT6 = PAD_ID(PC, 26),
- MX1_PAD_BT5 = PAD_ID(PC, 27),
- MX1_PAD_BT4 = PAD_ID(PC, 28),
- MX1_PAD_BT3 = PAD_ID(PC, 29),
- MX1_PAD_BT2 = PAD_ID(PC, 30),
- MX1_PAD_BT1 = PAD_ID(PC, 31),
- MX1_PAD_LSCLK = PAD_ID(PD, 6),
- MX1_PAD_REV = PAD_ID(PD, 7),
- MX1_PAD_CLS = PAD_ID(PD, 8),
- MX1_PAD_PS = PAD_ID(PD, 9),
- MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
- MX1_PAD_CONTRAST = PAD_ID(PD, 11),
- MX1_PAD_ACD_OE = PAD_ID(PD, 12),
- MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
- MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
- MX1_PAD_LD0 = PAD_ID(PD, 15),
- MX1_PAD_LD1 = PAD_ID(PD, 16),
- MX1_PAD_LD2 = PAD_ID(PD, 17),
- MX1_PAD_LD3 = PAD_ID(PD, 18),
- MX1_PAD_LD4 = PAD_ID(PD, 19),
- MX1_PAD_LD5 = PAD_ID(PD, 20),
- MX1_PAD_LD6 = PAD_ID(PD, 21),
- MX1_PAD_LD7 = PAD_ID(PD, 22),
- MX1_PAD_LD8 = PAD_ID(PD, 23),
- MX1_PAD_LD9 = PAD_ID(PD, 24),
- MX1_PAD_LD10 = PAD_ID(PD, 25),
- MX1_PAD_LD11 = PAD_ID(PD, 26),
- MX1_PAD_LD12 = PAD_ID(PD, 27),
- MX1_PAD_LD13 = PAD_ID(PD, 28),
- MX1_PAD_LD14 = PAD_ID(PD, 29),
- MX1_PAD_LD15 = PAD_ID(PD, 30),
- MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
+ MX1_PAD_A24 = PAD_ID(IMX1_PA, 0),
+ MX1_PAD_TIN = PAD_ID(IMX1_PA, 1),
+ MX1_PAD_PWMO = PAD_ID(IMX1_PA, 2),
+ MX1_PAD_CSI_MCLK = PAD_ID(IMX1_PA, 3),
+ MX1_PAD_CSI_D0 = PAD_ID(IMX1_PA, 4),
+ MX1_PAD_CSI_D1 = PAD_ID(IMX1_PA, 5),
+ MX1_PAD_CSI_D2 = PAD_ID(IMX1_PA, 6),
+ MX1_PAD_CSI_D3 = PAD_ID(IMX1_PA, 7),
+ MX1_PAD_CSI_D4 = PAD_ID(IMX1_PA, 8),
+ MX1_PAD_CSI_D5 = PAD_ID(IMX1_PA, 9),
+ MX1_PAD_CSI_D6 = PAD_ID(IMX1_PA, 10),
+ MX1_PAD_CSI_D7 = PAD_ID(IMX1_PA, 11),
+ MX1_PAD_CSI_VSYNC = PAD_ID(IMX1_PA, 12),
+ MX1_PAD_CSI_HSYNC = PAD_ID(IMX1_PA, 13),
+ MX1_PAD_CSI_PIXCLK = PAD_ID(IMX1_PA, 14),
+ MX1_PAD_I2C_SDA = PAD_ID(IMX1_PA, 15),
+ MX1_PAD_I2C_SCL = PAD_ID(IMX1_PA, 16),
+ MX1_PAD_DTACK = PAD_ID(IMX1_PA, 17),
+ MX1_PAD_BCLK = PAD_ID(IMX1_PA, 18),
+ MX1_PAD_LBA = PAD_ID(IMX1_PA, 19),
+ MX1_PAD_ECB = PAD_ID(IMX1_PA, 20),
+ MX1_PAD_A0 = PAD_ID(IMX1_PA, 21),
+ MX1_PAD_CS4 = PAD_ID(IMX1_PA, 22),
+ MX1_PAD_CS5 = PAD_ID(IMX1_PA, 23),
+ MX1_PAD_A16 = PAD_ID(IMX1_PA, 24),
+ MX1_PAD_A17 = PAD_ID(IMX1_PA, 25),
+ MX1_PAD_A18 = PAD_ID(IMX1_PA, 26),
+ MX1_PAD_A19 = PAD_ID(IMX1_PA, 27),
+ MX1_PAD_A20 = PAD_ID(IMX1_PA, 28),
+ MX1_PAD_A21 = PAD_ID(IMX1_PA, 29),
+ MX1_PAD_A22 = PAD_ID(IMX1_PA, 30),
+ MX1_PAD_A23 = PAD_ID(IMX1_PA, 31),
+ MX1_PAD_SD_DAT0 = PAD_ID(IMX1_PB, 8),
+ MX1_PAD_SD_DAT1 = PAD_ID(IMX1_PB, 9),
+ MX1_PAD_SD_DAT2 = PAD_ID(IMX1_PB, 10),
+ MX1_PAD_SD_DAT3 = PAD_ID(IMX1_PB, 11),
+ MX1_PAD_SD_SCLK = PAD_ID(IMX1_PB, 12),
+ MX1_PAD_SD_CMD = PAD_ID(IMX1_PB, 13),
+ MX1_PAD_SIM_SVEN = PAD_ID(IMX1_PB, 14),
+ MX1_PAD_SIM_PD = PAD_ID(IMX1_PB, 15),
+ MX1_PAD_SIM_TX = PAD_ID(IMX1_PB, 16),
+ MX1_PAD_SIM_RX = PAD_ID(IMX1_PB, 17),
+ MX1_PAD_SIM_RST = PAD_ID(IMX1_PB, 18),
+ MX1_PAD_SIM_CLK = PAD_ID(IMX1_PB, 19),
+ MX1_PAD_USBD_AFE = PAD_ID(IMX1_PB, 20),
+ MX1_PAD_USBD_OE = PAD_ID(IMX1_PB, 21),
+ MX1_PAD_USBD_RCV = PAD_ID(IMX1_PB, 22),
+ MX1_PAD_USBD_SUSPND = PAD_ID(IMX1_PB, 23),
+ MX1_PAD_USBD_VP = PAD_ID(IMX1_PB, 24),
+ MX1_PAD_USBD_VM = PAD_ID(IMX1_PB, 25),
+ MX1_PAD_USBD_VPO = PAD_ID(IMX1_PB, 26),
+ MX1_PAD_USBD_VMO = PAD_ID(IMX1_PB, 27),
+ MX1_PAD_UART2_CTS = PAD_ID(IMX1_PB, 28),
+ MX1_PAD_UART2_RTS = PAD_ID(IMX1_PB, 29),
+ MX1_PAD_UART2_TXD = PAD_ID(IMX1_PB, 30),
+ MX1_PAD_UART2_RXD = PAD_ID(IMX1_PB, 31),
+ MX1_PAD_SSI_RXFS = PAD_ID(IMX1_PC, 3),
+ MX1_PAD_SSI_RXCLK = PAD_ID(IMX1_PC, 4),
+ MX1_PAD_SSI_RXDAT = PAD_ID(IMX1_PC, 5),
+ MX1_PAD_SSI_TXDAT = PAD_ID(IMX1_PC, 6),
+ MX1_PAD_SSI_TXFS = PAD_ID(IMX1_PC, 7),
+ MX1_PAD_SSI_TXCLK = PAD_ID(IMX1_PC, 8),
+ MX1_PAD_UART1_CTS = PAD_ID(IMX1_PC, 9),
+ MX1_PAD_UART1_RTS = PAD_ID(IMX1_PC, 10),
+ MX1_PAD_UART1_TXD = PAD_ID(IMX1_PC, 11),
+ MX1_PAD_UART1_RXD = PAD_ID(IMX1_PC, 12),
+ MX1_PAD_SPI1_RDY = PAD_ID(IMX1_PC, 13),
+ MX1_PAD_SPI1_SCLK = PAD_ID(IMX1_PC, 14),
+ MX1_PAD_SPI1_SS = PAD_ID(IMX1_PC, 15),
+ MX1_PAD_SPI1_MISO = PAD_ID(IMX1_PC, 16),
+ MX1_PAD_SPI1_MOSI = PAD_ID(IMX1_PC, 17),
+ MX1_PAD_BT13 = PAD_ID(IMX1_PC, 19),
+ MX1_PAD_BT12 = PAD_ID(IMX1_PC, 20),
+ MX1_PAD_BT11 = PAD_ID(IMX1_PC, 21),
+ MX1_PAD_BT10 = PAD_ID(IMX1_PC, 22),
+ MX1_PAD_BT9 = PAD_ID(IMX1_PC, 23),
+ MX1_PAD_BT8 = PAD_ID(IMX1_PC, 24),
+ MX1_PAD_BT7 = PAD_ID(IMX1_PC, 25),
+ MX1_PAD_BT6 = PAD_ID(IMX1_PC, 26),
+ MX1_PAD_BT5 = PAD_ID(IMX1_PC, 27),
+ MX1_PAD_BT4 = PAD_ID(IMX1_PC, 28),
+ MX1_PAD_BT3 = PAD_ID(IMX1_PC, 29),
+ MX1_PAD_BT2 = PAD_ID(IMX1_PC, 30),
+ MX1_PAD_BT1 = PAD_ID(IMX1_PC, 31),
+ MX1_PAD_LSCLK = PAD_ID(IMX1_PD, 6),
+ MX1_PAD_REV = PAD_ID(IMX1_PD, 7),
+ MX1_PAD_CLS = PAD_ID(IMX1_PD, 8),
+ MX1_PAD_PS = PAD_ID(IMX1_PD, 9),
+ MX1_PAD_SPL_SPR = PAD_ID(IMX1_PD, 10),
+ MX1_PAD_CONTRAST = PAD_ID(IMX1_PD, 11),
+ MX1_PAD_ACD_OE = PAD_ID(IMX1_PD, 12),
+ MX1_PAD_LP_HSYNC = PAD_ID(IMX1_PD, 13),
+ MX1_PAD_FLM_VSYNC = PAD_ID(IMX1_PD, 14),
+ MX1_PAD_LD0 = PAD_ID(IMX1_PD, 15),
+ MX1_PAD_LD1 = PAD_ID(IMX1_PD, 16),
+ MX1_PAD_LD2 = PAD_ID(IMX1_PD, 17),
+ MX1_PAD_LD3 = PAD_ID(IMX1_PD, 18),
+ MX1_PAD_LD4 = PAD_ID(IMX1_PD, 19),
+ MX1_PAD_LD5 = PAD_ID(IMX1_PD, 20),
+ MX1_PAD_LD6 = PAD_ID(IMX1_PD, 21),
+ MX1_PAD_LD7 = PAD_ID(IMX1_PD, 22),
+ MX1_PAD_LD8 = PAD_ID(IMX1_PD, 23),
+ MX1_PAD_LD9 = PAD_ID(IMX1_PD, 24),
+ MX1_PAD_LD10 = PAD_ID(IMX1_PD, 25),
+ MX1_PAD_LD11 = PAD_ID(IMX1_PD, 26),
+ MX1_PAD_LD12 = PAD_ID(IMX1_PD, 27),
+ MX1_PAD_LD13 = PAD_ID(IMX1_PD, 28),
+ MX1_PAD_LD14 = PAD_ID(IMX1_PD, 29),
+ MX1_PAD_LD15 = PAD_ID(IMX1_PD, 30),
+ MX1_PAD_TMR2OUT = PAD_ID(IMX1_PD, 31),
};
/* Pad names for the pinmux subsystem */
diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c
index 1738df461235..afeb39957203 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx27.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx27.c
@@ -16,188 +16,188 @@
#include "pinctrl-imx1.h"
#define PAD_ID(port, pin) (port*32 + pin)
-#define PA 0
-#define PB 1
-#define PC 2
-#define PD 3
-#define PE 4
-#define PF 5
+#define MX27_PA 0
+#define MX27_PB 1
+#define MX27_PC 2
+#define MX27_PD 3
+#define MX27_PE 4
+#define MX27_PF 5
enum imx27_pads {
- MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
- MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
- MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
- MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
- MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
- MX27_PAD_LSCLK = PAD_ID(PA, 5),
- MX27_PAD_LD0 = PAD_ID(PA, 6),
- MX27_PAD_LD1 = PAD_ID(PA, 7),
- MX27_PAD_LD2 = PAD_ID(PA, 8),
- MX27_PAD_LD3 = PAD_ID(PA, 9),
- MX27_PAD_LD4 = PAD_ID(PA, 10),
- MX27_PAD_LD5 = PAD_ID(PA, 11),
- MX27_PAD_LD6 = PAD_ID(PA, 12),
- MX27_PAD_LD7 = PAD_ID(PA, 13),
- MX27_PAD_LD8 = PAD_ID(PA, 14),
- MX27_PAD_LD9 = PAD_ID(PA, 15),
- MX27_PAD_LD10 = PAD_ID(PA, 16),
- MX27_PAD_LD11 = PAD_ID(PA, 17),
- MX27_PAD_LD12 = PAD_ID(PA, 18),
- MX27_PAD_LD13 = PAD_ID(PA, 19),
- MX27_PAD_LD14 = PAD_ID(PA, 20),
- MX27_PAD_LD15 = PAD_ID(PA, 21),
- MX27_PAD_LD16 = PAD_ID(PA, 22),
- MX27_PAD_LD17 = PAD_ID(PA, 23),
- MX27_PAD_REV = PAD_ID(PA, 24),
- MX27_PAD_CLS = PAD_ID(PA, 25),
- MX27_PAD_PS = PAD_ID(PA, 26),
- MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
- MX27_PAD_HSYNC = PAD_ID(PA, 28),
- MX27_PAD_VSYNC = PAD_ID(PA, 29),
- MX27_PAD_CONTRAST = PAD_ID(PA, 30),
- MX27_PAD_OE_ACD = PAD_ID(PA, 31),
+ MX27_PAD_USBH2_CLK = PAD_ID(MX27_PA, 0),
+ MX27_PAD_USBH2_DIR = PAD_ID(MX27_PA, 1),
+ MX27_PAD_USBH2_DATA7 = PAD_ID(MX27_PA, 2),
+ MX27_PAD_USBH2_NXT = PAD_ID(MX27_PA, 3),
+ MX27_PAD_USBH2_STP = PAD_ID(MX27_PA, 4),
+ MX27_PAD_LSCLK = PAD_ID(MX27_PA, 5),
+ MX27_PAD_LD0 = PAD_ID(MX27_PA, 6),
+ MX27_PAD_LD1 = PAD_ID(MX27_PA, 7),
+ MX27_PAD_LD2 = PAD_ID(MX27_PA, 8),
+ MX27_PAD_LD3 = PAD_ID(MX27_PA, 9),
+ MX27_PAD_LD4 = PAD_ID(MX27_PA, 10),
+ MX27_PAD_LD5 = PAD_ID(MX27_PA, 11),
+ MX27_PAD_LD6 = PAD_ID(MX27_PA, 12),
+ MX27_PAD_LD7 = PAD_ID(MX27_PA, 13),
+ MX27_PAD_LD8 = PAD_ID(MX27_PA, 14),
+ MX27_PAD_LD9 = PAD_ID(MX27_PA, 15),
+ MX27_PAD_LD10 = PAD_ID(MX27_PA, 16),
+ MX27_PAD_LD11 = PAD_ID(MX27_PA, 17),
+ MX27_PAD_LD12 = PAD_ID(MX27_PA, 18),
+ MX27_PAD_LD13 = PAD_ID(MX27_PA, 19),
+ MX27_PAD_LD14 = PAD_ID(MX27_PA, 20),
+ MX27_PAD_LD15 = PAD_ID(MX27_PA, 21),
+ MX27_PAD_LD16 = PAD_ID(MX27_PA, 22),
+ MX27_PAD_LD17 = PAD_ID(MX27_PA, 23),
+ MX27_PAD_REV = PAD_ID(MX27_PA, 24),
+ MX27_PAD_CLS = PAD_ID(MX27_PA, 25),
+ MX27_PAD_PS = PAD_ID(MX27_PA, 26),
+ MX27_PAD_SPL_SPR = PAD_ID(MX27_PA, 27),
+ MX27_PAD_HSYNC = PAD_ID(MX27_PA, 28),
+ MX27_PAD_VSYNC = PAD_ID(MX27_PA, 29),
+ MX27_PAD_CONTRAST = PAD_ID(MX27_PA, 30),
+ MX27_PAD_OE_ACD = PAD_ID(MX27_PA, 31),
- MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
- MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
- MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
- MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
- MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
- MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
- MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
- MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
- MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
- MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
- MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
- MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
- MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
- MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
- MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
- MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
- MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
- MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
- MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
- MX27_PAD_USB_PWR = PAD_ID(PB, 23),
- MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
- MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
- MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
- MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
- MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
- MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
- MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
- MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
+ MX27_PAD_SD2_D0 = PAD_ID(MX27_PB, 4),
+ MX27_PAD_SD2_D1 = PAD_ID(MX27_PB, 5),
+ MX27_PAD_SD2_D2 = PAD_ID(MX27_PB, 6),
+ MX27_PAD_SD2_D3 = PAD_ID(MX27_PB, 7),
+ MX27_PAD_SD2_CMD = PAD_ID(MX27_PB, 8),
+ MX27_PAD_SD2_CLK = PAD_ID(MX27_PB, 9),
+ MX27_PAD_CSI_D0 = PAD_ID(MX27_PB, 10),
+ MX27_PAD_CSI_D1 = PAD_ID(MX27_PB, 11),
+ MX27_PAD_CSI_D2 = PAD_ID(MX27_PB, 12),
+ MX27_PAD_CSI_D3 = PAD_ID(MX27_PB, 13),
+ MX27_PAD_CSI_D4 = PAD_ID(MX27_PB, 14),
+ MX27_PAD_CSI_MCLK = PAD_ID(MX27_PB, 15),
+ MX27_PAD_CSI_PIXCLK = PAD_ID(MX27_PB, 16),
+ MX27_PAD_CSI_D5 = PAD_ID(MX27_PB, 17),
+ MX27_PAD_CSI_D6 = PAD_ID(MX27_PB, 18),
+ MX27_PAD_CSI_D7 = PAD_ID(MX27_PB, 19),
+ MX27_PAD_CSI_VSYNC = PAD_ID(MX27_PB, 20),
+ MX27_PAD_CSI_HSYNC = PAD_ID(MX27_PB, 21),
+ MX27_PAD_USBH1_SUSP = PAD_ID(MX27_PB, 22),
+ MX27_PAD_USB_PWR = PAD_ID(MX27_PB, 23),
+ MX27_PAD_USB_OC_B = PAD_ID(MX27_PB, 24),
+ MX27_PAD_USBH1_RCV = PAD_ID(MX27_PB, 25),
+ MX27_PAD_USBH1_FS = PAD_ID(MX27_PB, 26),
+ MX27_PAD_USBH1_OE_B = PAD_ID(MX27_PB, 27),
+ MX27_PAD_USBH1_TXDM = PAD_ID(MX27_PB, 28),
+ MX27_PAD_USBH1_TXDP = PAD_ID(MX27_PB, 29),
+ MX27_PAD_USBH1_RXDM = PAD_ID(MX27_PB, 30),
+ MX27_PAD_USBH1_RXDP = PAD_ID(MX27_PB, 31),
- MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
- MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
- MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
- MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
- MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
- MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
- MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
- MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
- MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
- MX27_PAD_TOUT = PAD_ID(PC, 14),
- MX27_PAD_TIN = PAD_ID(PC, 15),
- MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
- MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
- MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
- MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
- MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
- MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
- MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
- MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
- MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
- MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
- MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
- MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
- MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
- MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
- MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
- MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
+ MX27_PAD_I2C2_SDA = PAD_ID(MX27_PC, 5),
+ MX27_PAD_I2C2_SCL = PAD_ID(MX27_PC, 6),
+ MX27_PAD_USBOTG_DATA5 = PAD_ID(MX27_PC, 7),
+ MX27_PAD_USBOTG_DATA6 = PAD_ID(MX27_PC, 8),
+ MX27_PAD_USBOTG_DATA0 = PAD_ID(MX27_PC, 9),
+ MX27_PAD_USBOTG_DATA2 = PAD_ID(MX27_PC, 10),
+ MX27_PAD_USBOTG_DATA1 = PAD_ID(MX27_PC, 11),
+ MX27_PAD_USBOTG_DATA4 = PAD_ID(MX27_PC, 12),
+ MX27_PAD_USBOTG_DATA3 = PAD_ID(MX27_PC, 13),
+ MX27_PAD_TOUT = PAD_ID(MX27_PC, 14),
+ MX27_PAD_TIN = PAD_ID(MX27_PC, 15),
+ MX27_PAD_SSI4_FS = PAD_ID(MX27_PC, 16),
+ MX27_PAD_SSI4_RXDAT = PAD_ID(MX27_PC, 17),
+ MX27_PAD_SSI4_TXDAT = PAD_ID(MX27_PC, 18),
+ MX27_PAD_SSI4_CLK = PAD_ID(MX27_PC, 19),
+ MX27_PAD_SSI1_FS = PAD_ID(MX27_PC, 20),
+ MX27_PAD_SSI1_RXDAT = PAD_ID(MX27_PC, 21),
+ MX27_PAD_SSI1_TXDAT = PAD_ID(MX27_PC, 22),
+ MX27_PAD_SSI1_CLK = PAD_ID(MX27_PC, 23),
+ MX27_PAD_SSI2_FS = PAD_ID(MX27_PC, 24),
+ MX27_PAD_SSI2_RXDAT = PAD_ID(MX27_PC, 25),
+ MX27_PAD_SSI2_TXDAT = PAD_ID(MX27_PC, 26),
+ MX27_PAD_SSI2_CLK = PAD_ID(MX27_PC, 27),
+ MX27_PAD_SSI3_FS = PAD_ID(MX27_PC, 28),
+ MX27_PAD_SSI3_RXDAT = PAD_ID(MX27_PC, 29),
+ MX27_PAD_SSI3_TXDAT = PAD_ID(MX27_PC, 30),
+ MX27_PAD_SSI3_CLK = PAD_ID(MX27_PC, 31),
- MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
- MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
- MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
- MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
- MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
- MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
- MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
- MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
- MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
- MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
- MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
- MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
- MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
- MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
- MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
- MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
- MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
- MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
- MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
- MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
- MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
- MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
- MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
- MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
- MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
- MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
- MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
- MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
- MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
- MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
- MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
- MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
+ MX27_PAD_SD3_CMD = PAD_ID(MX27_PD, 0),
+ MX27_PAD_SD3_CLK = PAD_ID(MX27_PD, 1),
+ MX27_PAD_ATA_DATA0 = PAD_ID(MX27_PD, 2),
+ MX27_PAD_ATA_DATA1 = PAD_ID(MX27_PD, 3),
+ MX27_PAD_ATA_DATA2 = PAD_ID(MX27_PD, 4),
+ MX27_PAD_ATA_DATA3 = PAD_ID(MX27_PD, 5),
+ MX27_PAD_ATA_DATA4 = PAD_ID(MX27_PD, 6),
+ MX27_PAD_ATA_DATA5 = PAD_ID(MX27_PD, 7),
+ MX27_PAD_ATA_DATA6 = PAD_ID(MX27_PD, 8),
+ MX27_PAD_ATA_DATA7 = PAD_ID(MX27_PD, 9),
+ MX27_PAD_ATA_DATA8 = PAD_ID(MX27_PD, 10),
+ MX27_PAD_ATA_DATA9 = PAD_ID(MX27_PD, 11),
+ MX27_PAD_ATA_DATA10 = PAD_ID(MX27_PD, 12),
+ MX27_PAD_ATA_DATA11 = PAD_ID(MX27_PD, 13),
+ MX27_PAD_ATA_DATA12 = PAD_ID(MX27_PD, 14),
+ MX27_PAD_ATA_DATA13 = PAD_ID(MX27_PD, 15),
+ MX27_PAD_ATA_DATA14 = PAD_ID(MX27_PD, 16),
+ MX27_PAD_I2C_DATA = PAD_ID(MX27_PD, 17),
+ MX27_PAD_I2C_CLK = PAD_ID(MX27_PD, 18),
+ MX27_PAD_CSPI2_SS2 = PAD_ID(MX27_PD, 19),
+ MX27_PAD_CSPI2_SS1 = PAD_ID(MX27_PD, 20),
+ MX27_PAD_CSPI2_SS0 = PAD_ID(MX27_PD, 21),
+ MX27_PAD_CSPI2_SCLK = PAD_ID(MX27_PD, 22),
+ MX27_PAD_CSPI2_MISO = PAD_ID(MX27_PD, 23),
+ MX27_PAD_CSPI2_MOSI = PAD_ID(MX27_PD, 24),
+ MX27_PAD_CSPI1_RDY = PAD_ID(MX27_PD, 25),
+ MX27_PAD_CSPI1_SS2 = PAD_ID(MX27_PD, 26),
+ MX27_PAD_CSPI1_SS1 = PAD_ID(MX27_PD, 27),
+ MX27_PAD_CSPI1_SS0 = PAD_ID(MX27_PD, 28),
+ MX27_PAD_CSPI1_SCLK = PAD_ID(MX27_PD, 29),
+ MX27_PAD_CSPI1_MISO = PAD_ID(MX27_PD, 30),
+ MX27_PAD_CSPI1_MOSI = PAD_ID(MX27_PD, 31),
- MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
- MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
- MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
- MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
- MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
- MX27_PAD_PWMO = PAD_ID(PE, 5),
- MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
- MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
- MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
- MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
- MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
- MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
- MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
- MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
- MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
- MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
- MX27_PAD_RTCK = PAD_ID(PE, 16),
- MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
- MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
- MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
- MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
- MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
- MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
- MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
- MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
- MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
+ MX27_PAD_USBOTG_NXT = PAD_ID(MX27_PE, 0),
+ MX27_PAD_USBOTG_STP = PAD_ID(MX27_PE, 1),
+ MX27_PAD_USBOTG_DIR = PAD_ID(MX27_PE, 2),
+ MX27_PAD_UART2_CTS = PAD_ID(MX27_PE, 3),
+ MX27_PAD_UART2_RTS = PAD_ID(MX27_PE, 4),
+ MX27_PAD_PWMO = PAD_ID(MX27_PE, 5),
+ MX27_PAD_UART2_TXD = PAD_ID(MX27_PE, 6),
+ MX27_PAD_UART2_RXD = PAD_ID(MX27_PE, 7),
+ MX27_PAD_UART3_TXD = PAD_ID(MX27_PE, 8),
+ MX27_PAD_UART3_RXD = PAD_ID(MX27_PE, 9),
+ MX27_PAD_UART3_CTS = PAD_ID(MX27_PE, 10),
+ MX27_PAD_UART3_RTS = PAD_ID(MX27_PE, 11),
+ MX27_PAD_UART1_TXD = PAD_ID(MX27_PE, 12),
+ MX27_PAD_UART1_RXD = PAD_ID(MX27_PE, 13),
+ MX27_PAD_UART1_CTS = PAD_ID(MX27_PE, 14),
+ MX27_PAD_UART1_RTS = PAD_ID(MX27_PE, 15),
+ MX27_PAD_RTCK = PAD_ID(MX27_PE, 16),
+ MX27_PAD_RESET_OUT_B = PAD_ID(MX27_PE, 17),
+ MX27_PAD_SD1_D0 = PAD_ID(MX27_PE, 18),
+ MX27_PAD_SD1_D1 = PAD_ID(MX27_PE, 19),
+ MX27_PAD_SD1_D2 = PAD_ID(MX27_PE, 20),
+ MX27_PAD_SD1_D3 = PAD_ID(MX27_PE, 21),
+ MX27_PAD_SD1_CMD = PAD_ID(MX27_PE, 22),
+ MX27_PAD_SD1_CLK = PAD_ID(MX27_PE, 23),
+ MX27_PAD_USBOTG_CLK = PAD_ID(MX27_PE, 24),
+ MX27_PAD_USBOTG_DATA7 = PAD_ID(MX27_PE, 25),
- MX27_PAD_NFRB = PAD_ID(PF, 0),
- MX27_PAD_NFCLE = PAD_ID(PF, 1),
- MX27_PAD_NFWP_B = PAD_ID(PF, 2),
- MX27_PAD_NFCE_B = PAD_ID(PF, 3),
- MX27_PAD_NFALE = PAD_ID(PF, 4),
- MX27_PAD_NFRE_B = PAD_ID(PF, 5),
- MX27_PAD_NFWE_B = PAD_ID(PF, 6),
- MX27_PAD_PC_POE = PAD_ID(PF, 7),
- MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
- MX27_PAD_IOIS16 = PAD_ID(PF, 9),
- MX27_PAD_PC_RST = PAD_ID(PF, 10),
- MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
- MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
- MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
- MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
- MX27_PAD_CLKO = PAD_ID(PF, 15),
- MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
- MX27_PAD_PC_READY = PAD_ID(PF, 17),
- MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
- MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
- MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
- MX27_PAD_CS4_B = PAD_ID(PF, 21),
- MX27_PAD_CS5_B = PAD_ID(PF, 22),
- MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
+ MX27_PAD_NFRB = PAD_ID(MX27_PF, 0),
+ MX27_PAD_NFCLE = PAD_ID(MX27_PF, 1),
+ MX27_PAD_NFWP_B = PAD_ID(MX27_PF, 2),
+ MX27_PAD_NFCE_B = PAD_ID(MX27_PF, 3),
+ MX27_PAD_NFALE = PAD_ID(MX27_PF, 4),
+ MX27_PAD_NFRE_B = PAD_ID(MX27_PF, 5),
+ MX27_PAD_NFWE_B = PAD_ID(MX27_PF, 6),
+ MX27_PAD_PC_POE = PAD_ID(MX27_PF, 7),
+ MX27_PAD_PC_RW_B = PAD_ID(MX27_PF, 8),
+ MX27_PAD_IOIS16 = PAD_ID(MX27_PF, 9),
+ MX27_PAD_PC_RST = PAD_ID(MX27_PF, 10),
+ MX27_PAD_PC_BVD2 = PAD_ID(MX27_PF, 11),
+ MX27_PAD_PC_BVD1 = PAD_ID(MX27_PF, 12),
+ MX27_PAD_PC_VS2 = PAD_ID(MX27_PF, 13),
+ MX27_PAD_PC_VS1 = PAD_ID(MX27_PF, 14),
+ MX27_PAD_CLKO = PAD_ID(MX27_PF, 15),
+ MX27_PAD_PC_PWRON = PAD_ID(MX27_PF, 16),
+ MX27_PAD_PC_READY = PAD_ID(MX27_PF, 17),
+ MX27_PAD_PC_WAIT_B = PAD_ID(MX27_PF, 18),
+ MX27_PAD_PC_CD2_B = PAD_ID(MX27_PF, 19),
+ MX27_PAD_PC_CD1_B = PAD_ID(MX27_PF, 20),
+ MX27_PAD_CS4_B = PAD_ID(MX27_PF, 21),
+ MX27_PAD_CS5_B = PAD_ID(MX27_PF, 22),
+ MX27_PAD_ATA_DATA15 = PAD_ID(MX27_PF, 23),
};
/* Pad names for the pinmux subsystem */
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mq.c b/drivers/pinctrl/freescale/pinctrl-imx8mq.c
index 529eebe46298..e59e4fc80193 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx8mq.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx8mq.c
@@ -341,7 +341,7 @@ static struct platform_driver imx8mq_pinctrl_driver = {
.driver = {
.name = "imx8mq-pinctrl",
.of_match_table = imx8mq_pinctrl_of_match,
- .pm = &imx_pinctrl_pm_ops,
+ .pm = pm_sleep_ptr(&imx_pinctrl_pm_ops),
.suppress_bind_attrs = true,
},
.probe = imx8mq_pinctrl_probe,
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c
index 2e86ca9fc7ac..5632c7285147 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx8ulp.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx8ulp.c
@@ -252,6 +252,7 @@ static const struct of_device_id imx8ulp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8ulp-iomuxc1", },
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, imx8ulp_pinctrl_of_match);
static int imx8ulp_pinctrl_probe(struct platform_device *pdev)
{
diff --git a/drivers/pinctrl/freescale/pinctrl-imx91.c b/drivers/pinctrl/freescale/pinctrl-imx91.c
new file mode 100644
index 000000000000..5421141c586a
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx91.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <linux/init.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-imx.h"
+
+enum imx91_pads {
+ IMX91_PAD_DAP_TDI = 0,
+ IMX91_PAD_DAP_TMS_SWDIO = 1,
+ IMX91_PAD_DAP_TCLK_SWCLK = 2,
+ IMX91_PAD_DAP_TDO_TRACESWO = 3,
+ IMX91_PAD_GPIO_IO00 = 4,
+ IMX91_PAD_GPIO_IO01 = 5,
+ IMX91_PAD_GPIO_IO02 = 6,
+ IMX91_PAD_GPIO_IO03 = 7,
+ IMX91_PAD_GPIO_IO04 = 8,
+ IMX91_PAD_GPIO_IO05 = 9,
+ IMX91_PAD_GPIO_IO06 = 10,
+ IMX91_PAD_GPIO_IO07 = 11,
+ IMX91_PAD_GPIO_IO08 = 12,
+ IMX91_PAD_GPIO_IO09 = 13,
+ IMX91_PAD_GPIO_IO10 = 14,
+ IMX91_PAD_GPIO_IO11 = 15,
+ IMX91_PAD_GPIO_IO12 = 16,
+ IMX91_PAD_GPIO_IO13 = 17,
+ IMX91_PAD_GPIO_IO14 = 18,
+ IMX91_PAD_GPIO_IO15 = 19,
+ IMX91_PAD_GPIO_IO16 = 20,
+ IMX91_PAD_GPIO_IO17 = 21,
+ IMX91_PAD_GPIO_IO18 = 22,
+ IMX91_PAD_GPIO_IO19 = 23,
+ IMX91_PAD_GPIO_IO20 = 24,
+ IMX91_PAD_GPIO_IO21 = 25,
+ IMX91_PAD_GPIO_IO22 = 26,
+ IMX91_PAD_GPIO_IO23 = 27,
+ IMX91_PAD_GPIO_IO24 = 28,
+ IMX91_PAD_GPIO_IO25 = 29,
+ IMX91_PAD_GPIO_IO26 = 30,
+ IMX91_PAD_GPIO_IO27 = 31,
+ IMX91_PAD_GPIO_IO28 = 32,
+ IMX91_PAD_GPIO_IO29 = 33,
+ IMX91_PAD_CCM_CLKO1 = 34,
+ IMX91_PAD_CCM_CLKO2 = 35,
+ IMX91_PAD_CCM_CLKO3 = 36,
+ IMX91_PAD_CCM_CLKO4 = 37,
+ IMX91_PAD_ENET1_MDC = 38,
+ IMX91_PAD_ENET1_MDIO = 39,
+ IMX91_PAD_ENET1_TD3 = 40,
+ IMX91_PAD_ENET1_TD2 = 41,
+ IMX91_PAD_ENET1_TD1 = 42,
+ IMX91_PAD_ENET1_TD0 = 43,
+ IMX91_PAD_ENET1_TX_CTL = 44,
+ IMX91_PAD_ENET1_TXC = 45,
+ IMX91_PAD_ENET1_RX_CTL = 46,
+ IMX91_PAD_ENET1_RXC = 47,
+ IMX91_PAD_ENET1_RD0 = 48,
+ IMX91_PAD_ENET1_RD1 = 49,
+ IMX91_PAD_ENET1_RD2 = 50,
+ IMX91_PAD_ENET1_RD3 = 51,
+ IMX91_PAD_ENET2_MDC = 52,
+ IMX91_PAD_ENET2_MDIO = 53,
+ IMX91_PAD_ENET2_TD3 = 54,
+ IMX91_PAD_ENET2_TD2 = 55,
+ IMX91_PAD_ENET2_TD1 = 56,
+ IMX91_PAD_ENET2_TD0 = 57,
+ IMX91_PAD_ENET2_TX_CTL = 58,
+ IMX91_PAD_ENET2_TXC = 59,
+ IMX91_PAD_ENET2_RX_CTL = 60,
+ IMX91_PAD_ENET2_RXC = 61,
+ IMX91_PAD_ENET2_RD0 = 62,
+ IMX91_PAD_ENET2_RD1 = 63,
+ IMX91_PAD_ENET2_RD2 = 64,
+ IMX91_PAD_ENET2_RD3 = 65,
+ IMX91_PAD_SD1_CLK = 66,
+ IMX91_PAD_SD1_CMD = 67,
+ IMX91_PAD_SD1_DATA0 = 68,
+ IMX91_PAD_SD1_DATA1 = 69,
+ IMX91_PAD_SD1_DATA2 = 70,
+ IMX91_PAD_SD1_DATA3 = 71,
+ IMX91_PAD_SD1_DATA4 = 72,
+ IMX91_PAD_SD1_DATA5 = 73,
+ IMX91_PAD_SD1_DATA6 = 74,
+ IMX91_PAD_SD1_DATA7 = 75,
+ IMX91_PAD_SD1_STROBE = 76,
+ IMX91_PAD_SD2_VSELECT = 77,
+ IMX91_PAD_SD3_CLK = 78,
+ IMX91_PAD_SD3_CMD = 79,
+ IMX91_PAD_SD3_DATA0 = 80,
+ IMX91_PAD_SD3_DATA1 = 81,
+ IMX91_PAD_SD3_DATA2 = 82,
+ IMX91_PAD_SD3_DATA3 = 83,
+ IMX91_PAD_SD2_CD_B = 84,
+ IMX91_PAD_SD2_CLK = 85,
+ IMX91_PAD_SD2_CMD = 86,
+ IMX91_PAD_SD2_DATA0 = 87,
+ IMX91_PAD_SD2_DATA1 = 88,
+ IMX91_PAD_SD2_DATA2 = 89,
+ IMX91_PAD_SD2_DATA3 = 90,
+ IMX91_PAD_SD2_RESET_B = 91,
+ IMX91_PAD_I2C1_SCL = 92,
+ IMX91_PAD_I2C1_SDA = 93,
+ IMX91_PAD_I2C2_SCL = 94,
+ IMX91_PAD_I2C2_SDA = 95,
+ IMX91_PAD_UART1_RXD = 96,
+ IMX91_PAD_UART1_TXD = 97,
+ IMX91_PAD_UART2_RXD = 98,
+ IMX91_PAD_UART2_TXD = 99,
+ IMX91_PAD_PDM_CLK = 100,
+ IMX91_PAD_PDM_BIT_STREAM0 = 101,
+ IMX91_PAD_PDM_BIT_STREAM1 = 102,
+ IMX91_PAD_SAI1_TXFS = 103,
+ IMX91_PAD_SAI1_TXC = 104,
+ IMX91_PAD_SAI1_TXD0 = 105,
+ IMX91_PAD_SAI1_RXD0 = 106,
+ IMX91_PAD_WDOG_ANY = 107,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx91_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(IMX91_PAD_DAP_TDI),
+ IMX_PINCTRL_PIN(IMX91_PAD_DAP_TMS_SWDIO),
+ IMX_PINCTRL_PIN(IMX91_PAD_DAP_TCLK_SWCLK),
+ IMX_PINCTRL_PIN(IMX91_PAD_DAP_TDO_TRACESWO),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO00),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO01),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO02),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO03),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO04),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO05),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO06),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO07),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO08),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO09),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO10),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO11),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO12),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO13),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO14),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO15),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO16),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO17),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO18),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO19),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO20),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO21),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO22),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO23),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO24),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO25),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO26),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO27),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO28),
+ IMX_PINCTRL_PIN(IMX91_PAD_GPIO_IO29),
+ IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO1),
+ IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO2),
+ IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO3),
+ IMX_PINCTRL_PIN(IMX91_PAD_CCM_CLKO4),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_MDC),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_MDIO),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD3),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD2),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD1),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TD0),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TX_CTL),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_TXC),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RX_CTL),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RXC),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD0),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD1),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD2),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET1_RD3),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_MDC),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_MDIO),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD3),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD2),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD1),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TD0),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TX_CTL),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_TXC),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RX_CTL),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RXC),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD0),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD1),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD2),
+ IMX_PINCTRL_PIN(IMX91_PAD_ENET2_RD3),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA0),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA1),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA2),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA3),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA4),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA5),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA6),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_DATA7),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD1_STROBE),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD2_VSELECT),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA0),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA1),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA2),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD3_DATA3),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD2_CD_B),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA0),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA1),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA2),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD2_DATA3),
+ IMX_PINCTRL_PIN(IMX91_PAD_SD2_RESET_B),
+ IMX_PINCTRL_PIN(IMX91_PAD_I2C1_SCL),
+ IMX_PINCTRL_PIN(IMX91_PAD_I2C1_SDA),
+ IMX_PINCTRL_PIN(IMX91_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(IMX91_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(IMX91_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(IMX91_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(IMX91_PAD_UART2_RXD),
+ IMX_PINCTRL_PIN(IMX91_PAD_UART2_TXD),
+ IMX_PINCTRL_PIN(IMX91_PAD_PDM_CLK),
+ IMX_PINCTRL_PIN(IMX91_PAD_PDM_BIT_STREAM0),
+ IMX_PINCTRL_PIN(IMX91_PAD_PDM_BIT_STREAM1),
+ IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXFS),
+ IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXC),
+ IMX_PINCTRL_PIN(IMX91_PAD_SAI1_TXD0),
+ IMX_PINCTRL_PIN(IMX91_PAD_SAI1_RXD0),
+ IMX_PINCTRL_PIN(IMX91_PAD_WDOG_ANY),
+};
+
+static const struct imx_pinctrl_soc_info imx91_pinctrl_info = {
+ .pins = imx91_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx91_pinctrl_pads),
+ .flags = ZERO_OFFSET_VALID,
+};
+
+static int imx91_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx91_pinctrl_info);
+}
+
+static const struct of_device_id imx91_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx91-iomuxc", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx91_pinctrl_of_match);
+
+static struct platform_driver imx91_pinctrl_driver = {
+ .driver = {
+ .name = "imx91-pinctrl",
+ .of_match_table = imx91_pinctrl_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx91_pinctrl_probe,
+};
+
+static int __init imx91_pinctrl_init(void)
+{
+ return platform_driver_register(&imx91_pinctrl_driver);
+}
+arch_initcall(imx91_pinctrl_init);
+
+MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
+MODULE_DESCRIPTION("NXP i.MX91 pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c
index e77311f26262..edb242d30609 100644
--- a/drivers/pinctrl/freescale/pinctrl-mxs.c
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
@@ -413,8 +413,8 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
int ret;
u32 val;
- child = of_get_next_child(np, NULL);
- if (!child) {
+ val = of_get_child_count(np);
+ if (val == 0) {
dev_err(&pdev->dev, "no group is defined\n");
return -ENOENT;
}
@@ -490,16 +490,14 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
/* Get groups for each function */
idxf = 0;
fn = fnull;
- for_each_child_of_node(np, child) {
+ for_each_child_of_node_scoped(np, child) {
if (is_mxs_gpio(child))
continue;
if (of_property_read_u32(child, "reg", &val)) {
ret = mxs_pinctrl_parse_group(pdev, child,
idxg++, NULL);
- if (ret) {
- of_node_put(child);
+ if (ret)
return ret;
- }
continue;
}
@@ -509,19 +507,15 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
f->ngroups,
sizeof(*f->groups),
GFP_KERNEL);
- if (!f->groups) {
- of_node_put(child);
+ if (!f->groups)
return -ENOMEM;
- }
fn = child->name;
i = 0;
}
ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
&f->groups[i++]);
- if (ret) {
- of_node_put(child);
+ if (ret)
return ret;
- }
}
return 0;
generated by cgit (git 2.34.1) at 2025-07-31 01:48:49 +0000