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-rw-r--r--drivers/pinctrl/intel/Kconfig27
-rw-r--r--drivers/pinctrl/intel/Makefile4
-rw-r--r--drivers/pinctrl/intel/pinctrl-baytrail.c4
-rw-r--r--drivers/pinctrl/intel/pinctrl-cannonlake.c864
-rw-r--r--drivers/pinctrl/intel/pinctrl-cherryview.c21
-rw-r--r--drivers/pinctrl/intel/pinctrl-denverton.c302
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c232
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.h65
-rw-r--r--drivers/pinctrl/intel/pinctrl-lewisburg.c343
-rw-r--r--drivers/pinctrl/intel/pinctrl-merrifield.c6
-rw-r--r--drivers/pinctrl/intel/pinctrl-sunrisepoint.c1
11 files changed, 1786 insertions, 83 deletions
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 396830a41127..f30720a752f3 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -1,6 +1,7 @@
#
# Intel pin control drivers
#
+if (X86 || COMPILE_TEST)
config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
@@ -56,6 +57,22 @@ config PINCTRL_BROXTON
Broxton pinctrl driver provides an interface that allows
configuring of SoC pins and using them as GPIOs.
+config PINCTRL_CANNONLAKE
+ tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
+ depends on ACPI
+ select PINCTRL_INTEL
+ help
+ This pinctrl driver provides an interface that allows configuring
+ of Intel Cannon Lake PCH pins and using them as GPIOs.
+
+config PINCTRL_DENVERTON
+ tristate "Intel Denverton pinctrl and GPIO driver"
+ depends on ACPI
+ select PINCTRL_INTEL
+ help
+ This pinctrl driver provides an interface that allows configuring
+ of Intel Denverton SoC pins and using them as GPIOs.
+
config PINCTRL_GEMINILAKE
tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
depends on ACPI
@@ -64,6 +81,14 @@ config PINCTRL_GEMINILAKE
This pinctrl driver provides an interface that allows configuring
of Intel Gemini Lake SoC pins and using them as GPIOs.
+config PINCTRL_LEWISBURG
+ tristate "Intel Lewisburg pinctrl and GPIO driver"
+ depends on ACPI
+ select PINCTRL_INTEL
+ help
+ This pinctrl driver provides an interface that allows configuring
+ of Intel Lewisburg pins and using them as GPIOs.
+
config PINCTRL_SUNRISEPOINT
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
depends on ACPI
@@ -72,3 +97,5 @@ config PINCTRL_SUNRISEPOINT
Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
provides an interface that allows configuring of PCH pins and
using them as GPIOs.
+
+endif
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index 12f3af5b2ca5..624d367caa09 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
# Intel pin control drivers
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
@@ -5,5 +6,8 @@ obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
+obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
+obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o
obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
+obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index fa3c5758ac67..0f3a02495aeb 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -981,12 +981,12 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
*/
value = readl(reg) & BYT_PIN_MUX;
gpio_mux = byt_get_gpio_mux(vg, offset);
- if (WARN_ON(gpio_mux != value)) {
+ if (gpio_mux != value) {
value = readl(reg) & ~BYT_PIN_MUX;
value |= gpio_mux;
writel(value, reg);
- dev_warn(&vg->pdev->dev,
+ dev_warn(&vg->pdev->dev, FW_BUG
"pin %u forcibly re-configured as GPIO\n", offset);
}
diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c
new file mode 100644
index 000000000000..e130599be571
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c
@@ -0,0 +1,864 @@
+/*
+ * Intel Cannon Lake PCH pinctrl/GPIO driver
+ *
+ * Copyright (C) 2017, Intel Corporation
+ * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ * Mika Westerberg <mika.westerberg@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+#define CNL_PAD_OWN 0x020
+#define CNL_PADCFGLOCK 0x080
+#define CNL_HOSTSW_OWN 0x0b0
+#define CNL_GPI_IE 0x120
+
+#define CNL_GPP(r, s, e) \
+ { \
+ .reg_num = (r), \
+ .base = (s), \
+ .size = ((e) - (s) + 1), \
+ }
+
+#define CNL_COMMUNITY(b, s, e, g) \
+ { \
+ .barno = (b), \
+ .padown_offset = CNL_PAD_OWN, \
+ .padcfglock_offset = CNL_PADCFGLOCK, \
+ .hostown_offset = CNL_HOSTSW_OWN, \
+ .ie_offset = CNL_GPI_IE, \
+ .pin_base = (s), \
+ .npins = ((e) - (s) + 1), \
+ .gpps = (g), \
+ .ngpps = ARRAY_SIZE(g), \
+ }
+
+/* Cannon Lake-H */
+static const struct pinctrl_pin_desc cnlh_pins[] = {
+ /* GPP_A */
+ PINCTRL_PIN(0, "RCINB"),
+ PINCTRL_PIN(1, "LAD_0"),
+ PINCTRL_PIN(2, "LAD_1"),
+ PINCTRL_PIN(3, "LAD_2"),
+ PINCTRL_PIN(4, "LAD_3"),
+ PINCTRL_PIN(5, "LFRAMEB"),
+ PINCTRL_PIN(6, "SERIRQ"),
+ PINCTRL_PIN(7, "PIRQAB"),
+ PINCTRL_PIN(8, "CLKRUNB"),
+ PINCTRL_PIN(9, "CLKOUT_LPC_0"),
+ PINCTRL_PIN(10, "CLKOUT_LPC_1"),
+ PINCTRL_PIN(11, "PMEB"),
+ PINCTRL_PIN(12, "BM_BUSYB"),
+ PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
+ PINCTRL_PIN(14, "SUS_STATB"),
+ PINCTRL_PIN(15, "SUSACKB"),
+ PINCTRL_PIN(16, "CLKOUT_48"),
+ PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),
+ PINCTRL_PIN(18, "ISH_GP_0"),
+ PINCTRL_PIN(19, "ISH_GP_1"),
+ PINCTRL_PIN(20, "ISH_GP_2"),
+ PINCTRL_PIN(21, "ISH_GP_3"),
+ PINCTRL_PIN(22, "ISH_GP_4"),
+ PINCTRL_PIN(23, "ISH_GP_5"),
+ PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
+ /* GPP_B */
+ PINCTRL_PIN(25, "GSPI0_CS1B"),
+ PINCTRL_PIN(26, "GSPI1_CS1B"),
+ PINCTRL_PIN(27, "VRALERTB"),
+ PINCTRL_PIN(28, "CPU_GP_2"),
+ PINCTRL_PIN(29, "CPU_GP_3"),
+ PINCTRL_PIN(30, "SRCCLKREQB_0"),
+ PINCTRL_PIN(31, "SRCCLKREQB_1"),
+ PINCTRL_PIN(32, "SRCCLKREQB_2"),
+ PINCTRL_PIN(33, "SRCCLKREQB_3"),
+ PINCTRL_PIN(34, "SRCCLKREQB_4"),
+ PINCTRL_PIN(35, "SRCCLKREQB_5"),
+ PINCTRL_PIN(36, "SSP_MCLK"),
+ PINCTRL_PIN(37, "SLP_S0B"),
+ PINCTRL_PIN(38, "PLTRSTB"),
+ PINCTRL_PIN(39, "SPKR"),
+ PINCTRL_PIN(40, "GSPI0_CS0B"),
+ PINCTRL_PIN(41, "GSPI0_CLK"),
+ PINCTRL_PIN(42, "GSPI0_MISO"),
+ PINCTRL_PIN(43, "GSPI0_MOSI"),
+ PINCTRL_PIN(44, "GSPI1_CS0B"),
+ PINCTRL_PIN(45, "GSPI1_CLK"),
+ PINCTRL_PIN(46, "GSPI1_MISO"),
+ PINCTRL_PIN(47, "GSPI1_MOSI"),
+ PINCTRL_PIN(48, "SML1ALERTB"),
+ PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
+ /* GPP_C */
+ PINCTRL_PIN(51, "SMBCLK"),
+ PINCTRL_PIN(52, "SMBDATA"),
+ PINCTRL_PIN(53, "SMBALERTB"),
+ PINCTRL_PIN(54, "SML0CLK"),
+ PINCTRL_PIN(55, "SML0DATA"),
+ PINCTRL_PIN(56, "SML0ALERTB"),
+ PINCTRL_PIN(57, "SML1CLK"),
+ PINCTRL_PIN(58, "SML1DATA"),
+ PINCTRL_PIN(59, "UART0_RXD"),
+ PINCTRL_PIN(60, "UART0_TXD"),
+ PINCTRL_PIN(61, "UART0_RTSB"),
+ PINCTRL_PIN(62, "UART0_CTSB"),
+ PINCTRL_PIN(63, "UART1_RXD"),
+ PINCTRL_PIN(64, "UART1_TXD"),
+ PINCTRL_PIN(65, "UART1_RTSB"),
+ PINCTRL_PIN(66, "UART1_CTSB"),
+ PINCTRL_PIN(67, "I2C0_SDA"),
+ PINCTRL_PIN(68, "I2C0_SCL"),
+ PINCTRL_PIN(69, "I2C1_SDA"),
+ PINCTRL_PIN(70, "I2C1_SCL"),
+ PINCTRL_PIN(71, "UART2_RXD"),
+ PINCTRL_PIN(72, "UART2_TXD"),
+ PINCTRL_PIN(73, "UART2_RTSB"),
+ PINCTRL_PIN(74, "UART2_CTSB"),
+ /* GPP_D */
+ PINCTRL_PIN(75, "SPI1_CSB"),
+ PINCTRL_PIN(76, "SPI1_CLK"),
+ PINCTRL_PIN(77, "SPI1_MISO_IO_1"),
+ PINCTRL_PIN(78, "SPI1_MOSI_IO_0"),
+ PINCTRL_PIN(79, "ISH_I2C2_SDA"),
+ PINCTRL_PIN(80, "SSP2_SFRM"),
+ PINCTRL_PIN(81, "SSP2_TXD"),
+ PINCTRL_PIN(82, "SSP2_RXD"),
+ PINCTRL_PIN(83, "SSP2_SCLK"),
+ PINCTRL_PIN(84, "ISH_SPI_CSB"),
+ PINCTRL_PIN(85, "ISH_SPI_CLK"),
+ PINCTRL_PIN(86, "ISH_SPI_MISO"),
+ PINCTRL_PIN(87, "ISH_SPI_MOSI"),
+ PINCTRL_PIN(88, "ISH_UART0_RXD"),
+ PINCTRL_PIN(89, "ISH_UART0_TXD"),
+ PINCTRL_PIN(90, "ISH_UART0_RTSB"),
+ PINCTRL_PIN(91, "ISH_UART0_CTSB"),
+ PINCTRL_PIN(92, "DMIC_CLK_1"),
+ PINCTRL_PIN(93, "DMIC_DATA_1"),
+ PINCTRL_PIN(94, "DMIC_CLK_0"),
+ PINCTRL_PIN(95, "DMIC_DATA_0"),
+ PINCTRL_PIN(96, "SPI1_IO_2"),
+ PINCTRL_PIN(97, "SPI1_IO_3"),
+ PINCTRL_PIN(98, "ISH_I2C2_SCL"),
+ /* GPP_G */
+ PINCTRL_PIN(99, "SD3_CMD"),
+ PINCTRL_PIN(100, "SD3_D0"),
+ PINCTRL_PIN(101, "SD3_D1"),
+ PINCTRL_PIN(102, "SD3_D2"),
+ PINCTRL_PIN(103, "SD3_D3"),
+ PINCTRL_PIN(104, "SD3_CDB"),
+ PINCTRL_PIN(105, "SD3_CLK"),
+ PINCTRL_PIN(106, "SD3_WP"),
+ /* AZA */
+ PINCTRL_PIN(107, "HDA_BCLK"),
+ PINCTRL_PIN(108, "HDA_RSTB"),
+ PINCTRL_PIN(109, "HDA_SYNC"),
+ PINCTRL_PIN(110, "HDA_SDO"),
+ PINCTRL_PIN(111, "HDA_SDI_0"),
+ PINCTRL_PIN(112, "HDA_SDI_1"),
+ PINCTRL_PIN(113, "SSP1_SFRM"),
+ PINCTRL_PIN(114, "SSP1_TXD"),
+ /* vGPIO */
+ PINCTRL_PIN(115, "CNV_BTEN"),
+ PINCTRL_PIN(116, "CNV_GNEN"),
+ PINCTRL_PIN(117, "CNV_WFEN"),
+ PINCTRL_PIN(118, "CNV_WCEN"),
+ PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"),
+ PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"),
+ PINCTRL_PIN(121, "vSD3_CD_B"),
+ PINCTRL_PIN(122, "CNV_BT_IF_SELECT"),
+ PINCTRL_PIN(123, "vCNV_BT_UART_TXD"),
+ PINCTRL_PIN(124, "vCNV_BT_UART_RXD"),
+ PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"),
+ PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"),
+ PINCTRL_PIN(127, "vCNV_MFUART1_TXD"),
+ PINCTRL_PIN(128, "vCNV_MFUART1_RXD"),
+ PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"),
+ PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"),
+ PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"),
+ PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"),
+ PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"),
+ PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"),
+ PINCTRL_PIN(135, "vUART0_TXD"),
+ PINCTRL_PIN(136, "vUART0_RXD"),
+ PINCTRL_PIN(137, "vUART0_CTS_B"),
+ PINCTRL_PIN(138, "vUART0_RTSB"),
+ PINCTRL_PIN(139, "vISH_UART0_TXD"),
+ PINCTRL_PIN(140, "vISH_UART0_RXD"),
+ PINCTRL_PIN(141, "vISH_UART0_CTS_B"),
+ PINCTRL_PIN(142, "vISH_UART0_RTSB"),
+ PINCTRL_PIN(143, "vISH_UART1_TXD"),
+ PINCTRL_PIN(144, "vISH_UART1_RXD"),
+ PINCTRL_PIN(145, "vISH_UART1_CTS_B"),
+ PINCTRL_PIN(146, "vISH_UART1_RTS_B"),
+ PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"),
+ PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"),
+ PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"),
+ PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"),
+ PINCTRL_PIN(151, "vSSP2_SCLK"),
+ PINCTRL_PIN(152, "vSSP2_SFRM"),
+ PINCTRL_PIN(153, "vSSP2_TXD"),
+ PINCTRL_PIN(154, "vSSP2_RXD"),
+ /* GPP_K */
+ PINCTRL_PIN(155, "FAN_TACH_0"),
+ PINCTRL_PIN(156, "FAN_TACH_1"),
+ PINCTRL_PIN(157, "FAN_TACH_2"),
+ PINCTRL_PIN(158, "FAN_TACH_3"),
+ PINCTRL_PIN(159, "FAN_TACH_4"),
+ PINCTRL_PIN(160, "FAN_TACH_5"),
+ PINCTRL_PIN(161, "FAN_TACH_6"),
+ PINCTRL_PIN(162, "FAN_TACH_7"),
+ PINCTRL_PIN(163, "FAN_PWM_0"),
+ PINCTRL_PIN(164, "FAN_PWM_1"),
+ PINCTRL_PIN(165, "FAN_PWM_2"),
+ PINCTRL_PIN(166, "FAN_PWM_3"),
+ PINCTRL_PIN(167, "GSXDOUT"),
+ PINCTRL_PIN(168, "GSXSLOAD"),
+ PINCTRL_PIN(169, "GSXDIN"),
+ PINCTRL_PIN(170, "GSXSRESETB"),
+ PINCTRL_PIN(171, "GSXCLK"),
+ PINCTRL_PIN(172, "ADR_COMPLETE"),
+ PINCTRL_PIN(173, "NMIB"),
+ PINCTRL_PIN(174, "SMIB"),
+ PINCTRL_PIN(175, "CORE_VID_0"),
+ PINCTRL_PIN(176, "CORE_VID_1"),
+ PINCTRL_PIN(177, "IMGCLKOUT_0"),
+ PINCTRL_PIN(178, "IMGCLKOUT_1"),
+ /* GPP_H */
+ PINCTRL_PIN(179, "SRCCLKREQB_6"),
+ PINCTRL_PIN(180, "SRCCLKREQB_7"),
+ PINCTRL_PIN(181, "SRCCLKREQB_8"),
+ PINCTRL_PIN(182, "SRCCLKREQB_9"),
+ PINCTRL_PIN(183, "SRCCLKREQB_10"),
+ PINCTRL_PIN(184, "SRCCLKREQB_11"),
+ PINCTRL_PIN(185, "SRCCLKREQB_12"),
+ PINCTRL_PIN(186, "SRCCLKREQB_13"),
+ PINCTRL_PIN(187, "SRCCLKREQB_14"),
+ PINCTRL_PIN(188, "SRCCLKREQB_15"),
+ PINCTRL_PIN(189, "SML2CLK"),
+ PINCTRL_PIN(190, "SML2DATA"),
+ PINCTRL_PIN(191, "SML2ALERTB"),
+ PINCTRL_PIN(192, "SML3CLK"),
+ PINCTRL_PIN(193, "SML3DATA"),
+ PINCTRL_PIN(194, "SML3ALERTB"),
+ PINCTRL_PIN(195, "SML4CLK"),
+ PINCTRL_PIN(196, "SML4DATA"),
+ PINCTRL_PIN(197, "SML4ALERTB"),
+ PINCTRL_PIN(198, "ISH_I2C0_SDA"),
+ PINCTRL_PIN(199, "ISH_I2C0_SCL"),
+ PINCTRL_PIN(200, "ISH_I2C1_SDA"),
+ PINCTRL_PIN(201, "ISH_I2C1_SCL"),
+ PINCTRL_PIN(202, "TIME_SYNC_0"),
+ /* GPP_E */
+ PINCTRL_PIN(203, "SATAXPCIE_0"),
+ PINCTRL_PIN(204, "SATAXPCIE_1"),
+ PINCTRL_PIN(205, "SATAXPCIE_2"),
+ PINCTRL_PIN(206, "CPU_GP_0"),
+ PINCTRL_PIN(207, "SATA_DEVSLP_0"),
+ PINCTRL_PIN(208, "SATA_DEVSLP_1"),
+ PINCTRL_PIN(209, "SATA_DEVSLP_2"),
+ PINCTRL_PIN(210, "CPU_GP_1"),
+ PINCTRL_PIN(211, "SATA_LEDB"),
+ PINCTRL_PIN(212, "USB2_OCB_0"),
+ PINCTRL_PIN(213, "USB2_OCB_1"),
+ PINCTRL_PIN(214, "USB2_OCB_2"),
+ PINCTRL_PIN(215, "USB2_OCB_3"),
+ /* GPP_F */
+ PINCTRL_PIN(216, "SATAXPCIE_3"),
+ PINCTRL_PIN(217, "SATAXPCIE_4"),
+ PINCTRL_PIN(218, "SATAXPCIE_5"),
+ PINCTRL_PIN(219, "SATAXPCIE_6"),
+ PINCTRL_PIN(220, "SATAXPCIE_7"),
+ PINCTRL_PIN(221, "SATA_DEVSLP_3"),
+ PINCTRL_PIN(222, "SATA_DEVSLP_4"),
+ PINCTRL_PIN(223, "SATA_DEVSLP_5"),
+ PINCTRL_PIN(224, "SATA_DEVSLP_6"),
+ PINCTRL_PIN(225, "SATA_DEVSLP_7"),
+ PINCTRL_PIN(226, "SATA_SCLOCK"),
+ PINCTRL_PIN(227, "SATA_SLOAD"),
+ PINCTRL_PIN(228, "SATA_SDATAOUT1"),
+ PINCTRL_PIN(229, "SATA_SDATAOUT0"),
+ PINCTRL_PIN(230, "EXT_PWR_GATEB"),
+ PINCTRL_PIN(231, "USB2_OCB_4"),
+ PINCTRL_PIN(232, "USB2_OCB_5"),
+ PINCTRL_PIN(233, "USB2_OCB_6"),
+ PINCTRL_PIN(234, "USB2_OCB_7"),
+ PINCTRL_PIN(235, "L_VDDEN"),
+ PINCTRL_PIN(236, "L_BKLTEN"),
+ PINCTRL_PIN(237, "L_BKLTCTL"),
+ PINCTRL_PIN(238, "DDPF_CTRLCLK"),
+ PINCTRL_PIN(239, "DDPF_CTRLDATA"),
+ /* SPI */
+ PINCTRL_PIN(240, "SPI0_IO_2"),
+ PINCTRL_PIN(241, "SPI0_IO_3"),
+ PINCTRL_PIN(242, "SPI0_MOSI_IO_0"),
+ PINCTRL_PIN(243, "SPI0_MISO_IO_1"),
+ PINCTRL_PIN(244, "SPI0_TPM_CSB"),
+ PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"),
+ PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"),
+ PINCTRL_PIN(247, "SPI0_CLK"),
+ PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"),
+ /* CPU */
+ PINCTRL_PIN(249, "HDACPU_SDI"),
+ PINCTRL_PIN(250, "HDACPU_SDO"),
+ PINCTRL_PIN(251, "HDACPU_SCLK"),
+ PINCTRL_PIN(252, "PM_SYNC"),
+ PINCTRL_PIN(253, "PECI"),
+ PINCTRL_PIN(254, "CPUPWRGD"),
+ PINCTRL_PIN(255, "THRMTRIPB"),
+ PINCTRL_PIN(256, "PLTRST_CPUB"),
+ PINCTRL_PIN(257, "PM_DOWN"),
+ PINCTRL_PIN(258, "TRIGGER_IN"),
+ PINCTRL_PIN(259, "TRIGGER_OUT"),
+ /* JTAG */
+ PINCTRL_PIN(260, "JTAG_TDO"),
+ PINCTRL_PIN(261, "JTAGX"),
+ PINCTRL_PIN(262, "PRDYB"),
+ PINCTRL_PIN(263, "PREQB"),
+ PINCTRL_PIN(264, "CPU_TRSTB"),
+ PINCTRL_PIN(265, "JTAG_TDI"),
+ PINCTRL_PIN(266, "JTAG_TMS"),
+ PINCTRL_PIN(267, "JTAG_TCK"),
+ PINCTRL_PIN(268, "ITP_PMODE"),
+ /* GPP_I */
+ PINCTRL_PIN(269, "DDSP_HPD_0"),
+ PINCTRL_PIN(270, "DDSP_HPD_1"),
+ PINCTRL_PIN(271, "DDSP_HPD_2"),
+ PINCTRL_PIN(272, "DDSP_HPD_3"),
+ PINCTRL_PIN(273, "EDP_HPD"),
+ PINCTRL_PIN(274, "DDPB_CTRLCLK"),
+ PINCTRL_PIN(275, "DDPB_CTRLDATA"),
+ PINCTRL_PIN(276, "DDPC_CTRLCLK"),
+ PINCTRL_PIN(277, "DDPC_CTRLDATA"),
+ PINCTRL_PIN(278, "DDPD_CTRLCLK"),
+ PINCTRL_PIN(279, "DDPD_CTRLDATA"),
+ PINCTRL_PIN(280, "M2_SKT2_CFG_0"),
+ PINCTRL_PIN(281, "M2_SKT2_CFG_1"),
+ PINCTRL_PIN(282, "M2_SKT2_CFG_2"),
+ PINCTRL_PIN(283, "M2_SKT2_CFG_3"),
+ PINCTRL_PIN(284, "SYS_PWROK"),
+ PINCTRL_PIN(285, "SYS_RESETB"),
+ PINCTRL_PIN(286, "MLK_RSTB"),
+ /* GPP_J */
+ PINCTRL_PIN(287, "CNV_PA_BLANKING"),
+ PINCTRL_PIN(288, "CNV_GNSS_FTA"),
+ PINCTRL_PIN(289, "CNV_GNSS_SYSCK"),
+ PINCTRL_PIN(290, "CNV_RF_RESET_B"),
+ PINCTRL_PIN(291, "CNV_BRI_DT"),
+ PINCTRL_PIN(292, "CNV_BRI_RSP"),
+ PINCTRL_PIN(293, "CNV_RGI_DT"),
+ PINCTRL_PIN(294, "CNV_RGI_RSP"),
+ PINCTRL_PIN(295, "CNV_MFUART2_RXD"),
+ PINCTRL_PIN(296, "CNV_MFUART2_TXD"),
+ PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"),
+ PINCTRL_PIN(298, "A4WP_PRESENT"),
+};
+
+static const struct intel_padgroup cnlh_community0_gpps[] = {
+ CNL_GPP(0, 0, 24), /* GPP_A */
+ CNL_GPP(1, 25, 50), /* GPP_B */
+};
+
+static const struct intel_padgroup cnlh_community1_gpps[] = {
+ CNL_GPP(0, 51, 74), /* GPP_C */
+ CNL_GPP(1, 75, 98), /* GPP_D */
+ CNL_GPP(2, 99, 106), /* GPP_G */
+ CNL_GPP(3, 107, 114), /* AZA */
+ CNL_GPP(4, 115, 146), /* vGPIO_0 */
+ CNL_GPP(5, 147, 154), /* vGPIO_1 */
+};
+
+static const struct intel_padgroup cnlh_community3_gpps[] = {
+ CNL_GPP(0, 155, 178), /* GPP_K */
+ CNL_GPP(1, 179, 202), /* GPP_H */
+ CNL_GPP(2, 203, 215), /* GPP_E */
+ CNL_GPP(3, 216, 239), /* GPP_F */
+ CNL_GPP(4, 240, 248), /* SPI */
+};
+
+static const struct intel_padgroup cnlh_community4_gpps[] = {
+ CNL_GPP(0, 249, 259), /* CPU */
+ CNL_GPP(1, 260, 268), /* JTAG */
+ CNL_GPP(2, 269, 286), /* GPP_I */
+ CNL_GPP(3, 287, 298), /* GPP_J */
+};
+
+static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
+static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 };
+static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 };
+
+static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 };
+static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 };
+static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 };
+
+static const unsigned int cnlh_i2c0_pins[] = { 67, 68 };
+static const unsigned int cnlh_i2c1_pins[] = { 69, 70 };
+static const unsigned int cnlh_i2c2_pins[] = { 88, 89 };
+static const unsigned int cnlh_i2c3_pins[] = { 79, 98 };
+
+static const struct intel_pingroup cnlh_groups[] = {
+ PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1),
+ PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1),
+ PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3),
+ PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1),
+ PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1),
+ PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1),
+ PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1),
+ PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1),
+ PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3),
+ PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2),
+};
+
+static const char * const cnlh_spi0_groups[] = { "spi0_grp" };
+static const char * const cnlh_spi1_groups[] = { "spi1_grp" };
+static const char * const cnlh_spi2_groups[] = { "spi2_grp" };
+static const char * const cnlh_uart0_groups[] = { "uart0_grp" };
+static const char * const cnlh_uart1_groups[] = { "uart1_grp" };
+static const char * const cnlh_uart2_groups[] = { "uart2_grp" };
+static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" };
+static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" };
+static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" };
+static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" };
+
+static const struct intel_function cnlh_functions[] = {
+ FUNCTION("spi0", cnlh_spi0_groups),
+ FUNCTION("spi1", cnlh_spi1_groups),
+ FUNCTION("spi2", cnlh_spi2_groups),
+ FUNCTION("uart0", cnlh_uart0_groups),
+ FUNCTION("uart1", cnlh_uart1_groups),
+ FUNCTION("uart2", cnlh_uart2_groups),
+ FUNCTION("i2c0", cnlh_i2c0_groups),
+ FUNCTION("i2c1", cnlh_i2c1_groups),
+ FUNCTION("i2c2", cnlh_i2c2_groups),
+ FUNCTION("i2c3", cnlh_i2c3_groups),
+};
+
+static const struct intel_community cnlh_communities[] = {
+ CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
+ CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
+ /*
+ * ACPI MMIO resources are returned in reverse order for
+ * communities 3 and 4.
+ */
+ CNL_COMMUNITY(3, 155, 248, cnlh_community3_gpps),
+ CNL_COMMUNITY(2, 249, 298, cnlh_community4_gpps),
+};
+
+static const struct intel_pinctrl_soc_data cnlh_soc_data = {
+ .pins = cnlh_pins,
+ .npins = ARRAY_SIZE(cnlh_pins),
+ .groups = cnlh_groups,
+ .ngroups = ARRAY_SIZE(cnlh_groups),
+ .functions = cnlh_functions,
+ .nfunctions = ARRAY_SIZE(cnlh_functions),
+ .communities = cnlh_communities,
+ .ncommunities = ARRAY_SIZE(cnlh_communities),
+};
+
+/* Cannon Lake-LP */
+static const struct pinctrl_pin_desc cnllp_pins[] = {
+ /* GPP_A */
+ PINCTRL_PIN(0, "RCINB"),
+ PINCTRL_PIN(1, "LAD_0"),
+ PINCTRL_PIN(2, "LAD_1"),
+ PINCTRL_PIN(3, "LAD_2"),
+ PINCTRL_PIN(4, "LAD_3"),
+ PINCTRL_PIN(5, "LFRAMEB"),
+ PINCTRL_PIN(6, "SERIRQ"),
+ PINCTRL_PIN(7, "PIRQAB"),
+ PINCTRL_PIN(8, "CLKRUNB"),
+ PINCTRL_PIN(9, "CLKOUT_LPC_0"),
+ PINCTRL_PIN(10, "CLKOUT_LPC_1"),
+ PINCTRL_PIN(11, "PMEB"),
+ PINCTRL_PIN(12, "BM_BUSYB"),
+ PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
+ PINCTRL_PIN(14, "SUS_STATB"),
+ PINCTRL_PIN(15, "SUSACKB"),
+ PINCTRL_PIN(16, "SD_1P8_SEL"),
+ PINCTRL_PIN(17, "SD_PWR_EN_B"),
+ PINCTRL_PIN(18, "ISH_GP_0"),
+ PINCTRL_PIN(19, "ISH_GP_1"),
+ PINCTRL_PIN(20, "ISH_GP_2"),
+ PINCTRL_PIN(21, "ISH_GP_3"),
+ PINCTRL_PIN(22, "ISH_GP_4"),
+ PINCTRL_PIN(23, "ISH_GP_5"),
+ PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
+ /* GPP_B */
+ PINCTRL_PIN(25, "CORE_VID_0"),
+ PINCTRL_PIN(26, "CORE_VID_1"),
+ PINCTRL_PIN(27, "VRALERTB"),
+ PINCTRL_PIN(28, "CPU_GP_2"),
+ PINCTRL_PIN(29, "CPU_GP_3"),
+ PINCTRL_PIN(30, "SRCCLKREQB_0"),
+ PINCTRL_PIN(31, "SRCCLKREQB_1"),
+ PINCTRL_PIN(32, "SRCCLKREQB_2"),
+ PINCTRL_PIN(33, "SRCCLKREQB_3"),
+ PINCTRL_PIN(34, "SRCCLKREQB_4"),
+ PINCTRL_PIN(35, "SRCCLKREQB_5"),
+ PINCTRL_PIN(36, "EXT_PWR_GATEB"),
+ PINCTRL_PIN(37, "SLP_S0B"),
+ PINCTRL_PIN(38, "PLTRSTB"),
+ PINCTRL_PIN(39, "SPKR"),
+ PINCTRL_PIN(40, "GSPI0_CS0B"),
+ PINCTRL_PIN(41, "GSPI0_CLK"),
+ PINCTRL_PIN(42, "GSPI0_MISO"),
+ PINCTRL_PIN(43, "GSPI0_MOSI"),
+ PINCTRL_PIN(44, "GSPI1_CS0B"),
+ PINCTRL_PIN(45, "GSPI1_CLK"),
+ PINCTRL_PIN(46, "GSPI1_MISO"),
+ PINCTRL_PIN(47, "GSPI1_MOSI"),
+ PINCTRL_PIN(48, "SML1ALERTB"),
+ PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
+ PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
+ /* GPP_G */
+ PINCTRL_PIN(51, "SD3_CMD"),
+ PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"),
+ PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"),
+ PINCTRL_PIN(54, "SD3_D2"),
+ PINCTRL_PIN(55, "SD3_D3"),
+ PINCTRL_PIN(56, "SD3_CDB"),
+ PINCTRL_PIN(57, "SD3_CLK"),
+ PINCTRL_PIN(58, "SD3_WP"),
+ /* SPI */
+ PINCTRL_PIN(59, "SPI0_IO_2"),
+ PINCTRL_PIN(60, "SPI0_IO_3"),
+ PINCTRL_PIN(61, "SPI0_MOSI_IO_0"),
+ PINCTRL_PIN(62, "SPI0_MISO_IO_1"),
+ PINCTRL_PIN(63, "SPI0_TPM_CSB"),
+ PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"),
+ PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"),
+ PINCTRL_PIN(66, "SPI0_CLK"),
+ PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"),
+ /* GPP_D */
+ PINCTRL_PIN(68, "SPI1_CSB"),
+ PINCTRL_PIN(69, "SPI1_CLK"),
+ PINCTRL_PIN(70, "SPI1_MISO_IO_1"),
+ PINCTRL_PIN(71, "SPI1_MOSI_IO_0"),
+ PINCTRL_PIN(72, "IMGCLKOUT_0"),
+ PINCTRL_PIN(73, "ISH_I2C0_SDA"),
+ PINCTRL_PIN(74, "ISH_I2C0_SCL"),
+ PINCTRL_PIN(75, "ISH_I2C1_SDA"),
+ PINCTRL_PIN(76, "ISH_I2C1_SCL"),
+ PINCTRL_PIN(77, "ISH_SPI_CSB"),
+ PINCTRL_PIN(78, "ISH_SPI_CLK"),
+ PINCTRL_PIN(79, "ISH_SPI_MISO"),
+ PINCTRL_PIN(80, "ISH_SPI_MOSI"),
+ PINCTRL_PIN(81, "ISH_UART0_RXD"),
+ PINCTRL_PIN(82, "ISH_UART0_TXD"),
+ PINCTRL_PIN(83, "ISH_UART0_RTSB"),
+ PINCTRL_PIN(84, "ISH_UART0_CTSB"),
+ PINCTRL_PIN(85, "DMIC_CLK_1"),
+ PINCTRL_PIN(86, "DMIC_DATA_1"),
+ PINCTRL_PIN(87, "DMIC_CLK_0"),
+ PINCTRL_PIN(88, "DMIC_DATA_0"),
+ PINCTRL_PIN(89, "SPI1_IO_2"),
+ PINCTRL_PIN(90, "SPI1_IO_3"),
+ PINCTRL_PIN(91, "SSP_MCLK"),
+ PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"),
+ /* GPP_F */
+ PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"),
+ PINCTRL_PIN(94, "CNV_GNSS_FTA"),
+ PINCTRL_PIN(95, "CNV_GNSS_SYSCK"),
+ PINCTRL_PIN(96, "EMMC_HIP_MON"),
+ PINCTRL_PIN(97, "CNV_BRI_DT"),
+ PINCTRL_PIN(98, "CNV_BRI_RSP"),
+ PINCTRL_PIN(99, "CNV_RGI_DT"),
+ PINCTRL_PIN(100, "CNV_RGI_RSP"),
+ PINCTRL_PIN(101, "CNV_MFUART2_RXD"),
+ PINCTRL_PIN(102, "CNV_MFUART2_TXD"),
+ PINCTRL_PIN(103, "GPP_F_10"),
+ PINCTRL_PIN(104, "EMMC_CMD"),
+ PINCTRL_PIN(105, "EMMC_DATA_0"),
+ PINCTRL_PIN(106, "EMMC_DATA_1"),
+ PINCTRL_PIN(107, "EMMC_DATA_2"),
+ PINCTRL_PIN(108, "EMMC_DATA_3"),
+ PINCTRL_PIN(109, "EMMC_DATA_4"),
+ PINCTRL_PIN(110, "EMMC_DATA_5"),
+ PINCTRL_PIN(111, "EMMC_DATA_6"),
+ PINCTRL_PIN(112, "EMMC_DATA_7"),
+ PINCTRL_PIN(113, "EMMC_RCLK"),
+ PINCTRL_PIN(114, "EMMC_CLK"),
+ PINCTRL_PIN(115, "EMMC_RESETB"),
+ PINCTRL_PIN(116, "A4WP_PRESENT"),
+ /* GPP_H */
+ PINCTRL_PIN(117, "SSP2_SCLK"),
+ PINCTRL_PIN(118, "SSP2_SFRM"),
+ PINCTRL_PIN(119, "SSP2_TXD"),
+ PINCTRL_PIN(120, "SSP2_RXD"),
+ PINCTRL_PIN(121, "I2C2_SDA"),
+ PINCTRL_PIN(122, "I2C2_SCL"),
+ PINCTRL_PIN(123, "I2C3_SDA"),
+ PINCTRL_PIN(124, "I2C3_SCL"),
+ PINCTRL_PIN(125, "I2C4_SDA"),
+ PINCTRL_PIN(126, "I2C4_SCL"),
+ PINCTRL_PIN(127, "I2C5_SDA"),
+ PINCTRL_PIN(128, "I2C5_SCL"),
+ PINCTRL_PIN(129, "M2_SKT2_CFG_0"),
+ PINCTRL_PIN(130, "M2_SKT2_CFG_1"),
+ PINCTRL_PIN(131, "M2_SKT2_CFG_2"),
+ PINCTRL_PIN(132, "M2_SKT2_CFG_3"),
+ PINCTRL_PIN(133, "DDPF_CTRLCLK"),
+ PINCTRL_PIN(134, "DDPF_CTRLDATA"),
+ PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"),
+ PINCTRL_PIN(136, "TIMESYNC_0"),
+ PINCTRL_PIN(137, "IMGCLKOUT_1"),
+ PINCTRL_PIN(138, "GPPC_H_21"),
+ PINCTRL_PIN(139, "GPPC_H_22"),
+ PINCTRL_PIN(140, "GPPC_H_23"),
+ /* vGPIO */
+ PINCTRL_PIN(141, "CNV_BTEN"),
+ PINCTRL_PIN(142, "CNV_GNEN"),
+ PINCTRL_PIN(143, "CNV_WFEN"),
+ PINCTRL_PIN(144, "CNV_WCEN"),
+ PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
+ PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
+ PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
+ PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
+ PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
+ PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
+ PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
+ PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
+ PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
+ PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
+ PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"),
+ PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"),
+ PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"),
+ PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"),
+ PINCTRL_PIN(159, "vUART0_TXD"),
+ PINCTRL_PIN(160, "vUART0_RXD"),
+ PINCTRL_PIN(161, "vUART0_CTS_B"),
+ PINCTRL_PIN(162, "vUART0_RTS_B"),
+ PINCTRL_PIN(163, "vISH_UART0_TXD"),
+ PINCTRL_PIN(164, "vISH_UART0_RXD"),
+ PINCTRL_PIN(165, "vISH_UART0_CTS_B"),
+ PINCTRL_PIN(166, "vISH_UART0_RTS_B"),
+ PINCTRL_PIN(167, "vISH_UART1_TXD"),
+ PINCTRL_PIN(168, "vISH_UART1_RXD"),
+ PINCTRL_PIN(169, "vISH_UART1_CTS_B"),
+ PINCTRL_PIN(170, "vISH_UART1_RTS_B"),
+ PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"),
+ PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"),
+ PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"),
+ PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"),
+ PINCTRL_PIN(175, "vSSP2_SCLK"),
+ PINCTRL_PIN(176, "vSSP2_SFRM"),
+ PINCTRL_PIN(177, "vSSP2_TXD"),
+ PINCTRL_PIN(178, "vSSP2_RXD"),
+ PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"),
+ PINCTRL_PIN(180, "vSD3_CD_B"),
+ /* GPP_C */
+ PINCTRL_PIN(181, "SMBCLK"),
+ PINCTRL_PIN(182, "SMBDATA"),
+ PINCTRL_PIN(183, "SMBALERTB"),
+ PINCTRL_PIN(184, "SML0CLK"),
+ PINCTRL_PIN(185, "SML0DATA"),
+ PINCTRL_PIN(186, "SML0ALERTB"),
+ PINCTRL_PIN(187, "SML1CLK"),
+ PINCTRL_PIN(188, "SML1DATA"),
+ PINCTRL_PIN(189, "UART0_RXD"),
+ PINCTRL_PIN(190, "UART0_TXD"),
+ PINCTRL_PIN(191, "UART0_RTSB"),
+ PINCTRL_PIN(192, "UART0_CTSB"),
+ PINCTRL_PIN(193, "UART1_RXD"),
+ PINCTRL_PIN(194, "UART1_TXD"),
+ PINCTRL_PIN(195, "UART1_RTSB"),
+ PINCTRL_PIN(196, "UART1_CTSB"),
+ PINCTRL_PIN(197, "I2C0_SDA"),
+ PINCTRL_PIN(198, "I2C0_SCL"),
+ PINCTRL_PIN(199, "I2C1_SDA"),
+ PINCTRL_PIN(200, "I2C1_SCL"),
+ PINCTRL_PIN(201, "UART2_RXD"),
+ PINCTRL_PIN(202, "UART2_TXD"),
+ PINCTRL_PIN(203, "UART2_RTSB"),
+ PINCTRL_PIN(204, "UART2_CTSB"),
+ /* GPP_E */
+ PINCTRL_PIN(205, "SATAXPCIE_0"),
+ PINCTRL_PIN(206, "SATAXPCIE_1"),
+ PINCTRL_PIN(207, "SATAXPCIE_2"),
+ PINCTRL_PIN(208, "CPU_GP_0"),
+ PINCTRL_PIN(209, "SATA_DEVSLP_0"),
+ PINCTRL_PIN(210, "SATA_DEVSLP_1"),
+ PINCTRL_PIN(211, "SATA_DEVSLP_2"),
+ PINCTRL_PIN(212, "CPU_GP_1"),
+ PINCTRL_PIN(213, "SATA_LEDB"),
+ PINCTRL_PIN(214, "USB2_OCB_0"),
+ PINCTRL_PIN(215, "USB2_OCB_1"),
+ PINCTRL_PIN(216, "USB2_OCB_2"),
+ PINCTRL_PIN(217, "USB2_OCB_3"),
+ PINCTRL_PIN(218, "DDSP_HPD_0"),
+ PINCTRL_PIN(219, "DDSP_HPD_1"),
+ PINCTRL_PIN(220, "DDSP_HPD_2"),
+ PINCTRL_PIN(221, "DDSP_HPD_3"),
+ PINCTRL_PIN(222, "EDP_HPD"),
+ PINCTRL_PIN(223, "DDPB_CTRLCLK"),
+ PINCTRL_PIN(224, "DDPB_CTRLDATA"),
+ PINCTRL_PIN(225, "DDPC_CTRLCLK"),
+ PINCTRL_PIN(226, "DDPC_CTRLDATA"),
+ PINCTRL_PIN(227, "DDPD_CTRLCLK"),
+ PINCTRL_PIN(228, "DDPD_CTRLDATA"),
+ /* JTAG */
+ PINCTRL_PIN(229, "JTAG_TDO"),
+ PINCTRL_PIN(230, "JTAGX"),
+ PINCTRL_PIN(231, "PRDYB"),
+ PINCTRL_PIN(232, "PREQB"),
+ PINCTRL_PIN(233, "CPU_TRSTB"),
+ PINCTRL_PIN(234, "JTAG_TDI"),
+ PINCTRL_PIN(235, "JTAG_TMS"),
+ PINCTRL_PIN(236, "JTAG_TCK"),
+ PINCTRL_PIN(237, "ITP_PMODE"),
+ /* HVCMOS */
+ PINCTRL_PIN(238, "L_BKLTEN"),
+ PINCTRL_PIN(239, "L_BKLTCTL"),
+ PINCTRL_PIN(240, "L_VDDEN"),
+ PINCTRL_PIN(241, "SYS_PWROK"),
+ PINCTRL_PIN(242, "SYS_RESETB"),
+ PINCTRL_PIN(243, "MLK_RSTB"),
+};
+
+static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 };
+static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 };
+static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 };
+static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 };
+static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 };
+static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
+
+static const unsigned int cnllp_i2c0_pins[] = { 197, 198 };
+static const unsigned int cnllp_i2c1_pins[] = { 199, 200 };
+static const unsigned int cnllp_i2c2_pins[] = { 121, 122 };
+static const unsigned int cnllp_i2c3_pins[] = { 123, 124 };
+static const unsigned int cnllp_i2c4_pins[] = { 125, 126 };
+static const unsigned int cnllp_i2c5_pins[] = { 127, 128 };
+
+static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 };
+static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 };
+static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 };
+
+static const struct intel_pingroup cnllp_groups[] = {
+ PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes),
+ PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes),
+ PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes),
+ PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1),
+ PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1),
+ PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1),
+ PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1),
+ PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1),
+ PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1),
+ PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1),
+ PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1),
+ PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1),
+};
+
+static const char * const cnllp_spi0_groups[] = { "spi0_grp" };
+static const char * const cnllp_spi1_groups[] = { "spi1_grp" };
+static const char * const cnllp_spi2_groups[] = { "spi2_grp" };
+static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" };
+static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" };
+static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" };
+static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" };
+static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" };
+static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" };
+static const char * const cnllp_uart0_groups[] = { "uart0_grp" };
+static const char * const cnllp_uart1_groups[] = { "uart1_grp" };
+static const char * const cnllp_uart2_groups[] = { "uart2_grp" };
+
+static const struct intel_function cnllp_functions[] = {
+ FUNCTION("spi0", cnllp_spi0_groups),
+ FUNCTION("spi1", cnllp_spi1_groups),
+ FUNCTION("spi2", cnllp_spi2_groups),
+ FUNCTION("i2c0", cnllp_i2c0_groups),
+ FUNCTION("i2c1", cnllp_i2c1_groups),
+ FUNCTION("i2c2", cnllp_i2c2_groups),
+ FUNCTION("i2c3", cnllp_i2c3_groups),
+ FUNCTION("i2c4", cnllp_i2c4_groups),
+ FUNCTION("i2c5", cnllp_i2c5_groups),
+ FUNCTION("uart0", cnllp_uart0_groups),
+ FUNCTION("uart1", cnllp_uart1_groups),
+ FUNCTION("uart2", cnllp_uart2_groups),
+};
+
+static const struct intel_padgroup cnllp_community0_gpps[] = {
+ CNL_GPP(0, 0, 24), /* GPP_A */
+ CNL_GPP(1, 25, 50), /* GPP_B */
+ CNL_GPP(2, 51, 58), /* GPP_G */
+ CNL_GPP(3, 59, 67), /* SPI */
+};
+
+static const struct intel_padgroup cnllp_community1_gpps[] = {
+ CNL_GPP(0, 68, 92), /* GPP_D */
+ CNL_GPP(1, 93, 116), /* GPP_F */
+ CNL_GPP(2, 117, 140), /* GPP_H */
+ CNL_GPP(3, 141, 172), /* vGPIO */
+ CNL_GPP(4, 173, 180), /* vGPIO */
+};
+
+static const struct intel_padgroup cnllp_community4_gpps[] = {
+ CNL_GPP(0, 181, 204), /* GPP_C */
+ CNL_GPP(1, 205, 228), /* GPP_E */
+ CNL_GPP(2, 229, 237), /* JTAG */
+ CNL_GPP(3, 238, 243), /* HVCMOS */
+};
+
+static const struct intel_community cnllp_communities[] = {
+ CNL_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
+ CNL_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
+ CNL_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
+};
+
+static const struct intel_pinctrl_soc_data cnllp_soc_data = {
+ .pins = cnllp_pins,
+ .npins = ARRAY_SIZE(cnllp_pins),
+ .groups = cnllp_groups,
+ .ngroups = ARRAY_SIZE(cnllp_groups),
+ .functions = cnllp_functions,
+ .nfunctions = ARRAY_SIZE(cnllp_functions),
+ .communities = cnllp_communities,
+ .ncommunities = ARRAY_SIZE(cnllp_communities),
+};
+
+static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
+ { "INT3450", (kernel_ulong_t)&cnlh_soc_data },
+ { "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
+
+static int cnl_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct intel_pinctrl_soc_data *soc_data;
+ const struct acpi_device_id *id;
+
+ id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev);
+ if (!id || !id->driver_data)
+ return -ENODEV;
+
+ soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
+ return intel_pinctrl_probe(pdev, soc_data);
+}
+
+static const struct dev_pm_ops cnl_pinctrl_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
+ intel_pinctrl_resume)
+};
+
+static struct platform_driver cnl_pinctrl_driver = {
+ .probe = cnl_pinctrl_probe,
+ .driver = {
+ .name = "cannonlake-pinctrl",
+ .acpi_match_table = cnl_pinctrl_acpi_match,
+ .pm = &cnl_pinctrl_pm_ops,
+ },
+};
+
+module_platform_driver(cnl_pinctrl_driver);
+
+MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
+MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index 20f1b4493994..fadbca907c7c 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -1548,6 +1548,13 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
},
},
{
+ .ident = "HP Chromebook 11 G5 (Setzer)",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "HP"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
+ },
+ },
+ {
.ident = "Acer Chromebook R11 (Cyan)",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
@@ -1570,6 +1577,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
struct gpio_chip *chip = &pctrl->chip;
bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
int ret, i, offset;
+ int irq_base;
*chip = chv_gpio_chip;
@@ -1615,7 +1623,18 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
/* Clear all interrupts */
chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
- ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
+ if (!need_valid_mask) {
+ irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
+ chip->ngpio, NUMA_NO_NODE);
+ if (irq_base < 0) {
+ dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
+ return irq_base;
+ }
+ } else {
+ irq_base = 0;
+ }
+
+ ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, irq_base,
handle_bad_irq, IRQ_TYPE_NONE);
if (ret) {
dev_err(pctrl->dev, "failed to add IRQ chip\n");
diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c
new file mode 100644
index 000000000000..4500880240f2
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-denverton.c
@@ -0,0 +1,302 @@
+/*
+ * Intel Denverton SoC pinctrl/GPIO driver
+ *
+ * Copyright (C) 2017, Intel Corporation
+ * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+#define DNV_PAD_OWN 0x020
+#define DNV_HOSTSW_OWN 0x0C0
+#define DNV_PADCFGLOCK 0x090
+#define DNV_GPI_IE 0x120
+
+#define DNV_GPP(n, s, e) \
+ { \
+ .reg_num = (n), \
+ .base = (s), \
+ .size = ((e) - (s) + 1), \
+ }
+
+#define DNV_COMMUNITY(b, s, e, g) \
+ { \
+ .barno = (b), \
+ .padown_offset = DNV_PAD_OWN, \
+ .padcfglock_offset = DNV_PADCFGLOCK, \
+ .hostown_offset = DNV_HOSTSW_OWN, \
+ .ie_offset = DNV_GPI_IE, \
+ .pin_base = (s), \
+ .npins = ((e) - (s) + 1), \
+ .gpps = (g), \
+ .ngpps = ARRAY_SIZE(g), \
+ }
+
+static const struct pinctrl_pin_desc dnv_pins[] = {
+ /* North ALL */
+ PINCTRL_PIN(0, "GBE0_SDP0"),
+ PINCTRL_PIN(1, "GBE1_SDP0"),
+ PINCTRL_PIN(2, "GBE0_SDP1"),
+ PINCTRL_PIN(3, "GBE1_SDP1"),
+ PINCTRL_PIN(4, "GBE0_SDP2"),
+ PINCTRL_PIN(5, "GBE1_SDP2"),
+ PINCTRL_PIN(6, "GBE0_SDP3"),
+ PINCTRL_PIN(7, "GBE1_SDP3"),
+ PINCTRL_PIN(8, "GBE2_LED0"),
+ PINCTRL_PIN(9, "GBE2_LED1"),
+ PINCTRL_PIN(10, "GBE0_I2C_CLK"),
+ PINCTRL_PIN(11, "GBE0_I2C_DATA"),
+ PINCTRL_PIN(12, "GBE1_I2C_CLK"),
+ PINCTRL_PIN(13, "GBE1_I2C_DATA"),
+ PINCTRL_PIN(14, "NCSI_RXD0"),
+ PINCTRL_PIN(15, "NCSI_CLK_IN"),
+ PINCTRL_PIN(16, "NCSI_RXD1"),
+ PINCTRL_PIN(17, "NCSI_CRS_DV"),
+ PINCTRL_PIN(18, "NCSI_ARB_IN"),
+ PINCTRL_PIN(19, "NCSI_TX_EN"),
+ PINCTRL_PIN(20, "NCSI_TXD0"),
+ PINCTRL_PIN(21, "NCSI_TXD1"),
+ PINCTRL_PIN(22, "NCSI_ARB_OUT"),
+ PINCTRL_PIN(23, "GBE0_LED0"),
+ PINCTRL_PIN(24, "GBE0_LED1"),
+ PINCTRL_PIN(25, "GBE1_LED0"),
+ PINCTRL_PIN(26, "GBE1_LED1"),
+ PINCTRL_PIN(27, "GPIO_0"),
+ PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
+ PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
+ PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
+ PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
+ PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
+ PINCTRL_PIN(33, "GPIO_1"),
+ PINCTRL_PIN(34, "GPIO_2"),
+ PINCTRL_PIN(35, "SVID_ALERT_N"),
+ PINCTRL_PIN(36, "SVID_DATA"),
+ PINCTRL_PIN(37, "SVID_CLK"),
+ PINCTRL_PIN(38, "THERMTRIP_N"),
+ PINCTRL_PIN(39, "PROCHOT_N"),
+ PINCTRL_PIN(40, "MEMHOT_N"),
+ /* South DFX */
+ PINCTRL_PIN(41, "DFX_PORT_CLK0"),
+ PINCTRL_PIN(42, "DFX_PORT_CLK1"),
+ PINCTRL_PIN(43, "DFX_PORT0"),
+ PINCTRL_PIN(44, "DFX_PORT1"),
+ PINCTRL_PIN(45, "DFX_PORT2"),
+ PINCTRL_PIN(46, "DFX_PORT3"),
+ PINCTRL_PIN(47, "DFX_PORT4"),
+ PINCTRL_PIN(48, "DFX_PORT5"),
+ PINCTRL_PIN(49, "DFX_PORT6"),
+ PINCTRL_PIN(50, "DFX_PORT7"),
+ PINCTRL_PIN(51, "DFX_PORT8"),
+ PINCTRL_PIN(52, "DFX_PORT9"),
+ PINCTRL_PIN(53, "DFX_PORT10"),
+ PINCTRL_PIN(54, "DFX_PORT11"),
+ PINCTRL_PIN(55, "DFX_PORT12"),
+ PINCTRL_PIN(56, "DFX_PORT13"),
+ PINCTRL_PIN(57, "DFX_PORT14"),
+ PINCTRL_PIN(58, "DFX_PORT15"),
+ /* South GPP0 */
+ PINCTRL_PIN(59, "GPIO_12"),
+ PINCTRL_PIN(60, "SMB5_GBE_ALRT_N"),
+ PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
+ PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
+ PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
+ PINCTRL_PIN(64, "UART0_RXD"),
+ PINCTRL_PIN(65, "UART0_TXD"),
+ PINCTRL_PIN(66, "SMB5_GBE_CLK"),
+ PINCTRL_PIN(67, "SMB5_GBE_DATA"),
+ PINCTRL_PIN(68, "ERROR2_N"),
+ PINCTRL_PIN(69, "ERROR1_N"),
+ PINCTRL_PIN(70, "ERROR0_N"),
+ PINCTRL_PIN(71, "IERR_N"),
+ PINCTRL_PIN(72, "MCERR_N"),
+ PINCTRL_PIN(73, "SMB0_LEG_CLK"),
+ PINCTRL_PIN(74, "SMB0_LEG_DATA"),
+ PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"),
+ PINCTRL_PIN(76, "SMB1_HOST_DATA"),
+ PINCTRL_PIN(77, "SMB1_HOST_CLK"),
+ PINCTRL_PIN(78, "SMB2_PECI_DATA"),
+ PINCTRL_PIN(79, "SMB2_PECI_CLK"),
+ PINCTRL_PIN(80, "SMB4_CSME0_DATA"),
+ PINCTRL_PIN(81, "SMB4_CSME0_CLK"),
+ PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"),
+ PINCTRL_PIN(83, "USB_OC0_N"),
+ PINCTRL_PIN(84, "FLEX_CLK_SE0"),
+ PINCTRL_PIN(85, "FLEX_CLK_SE1"),
+ PINCTRL_PIN(86, "GPIO_4"),
+ PINCTRL_PIN(87, "GPIO_5"),
+ PINCTRL_PIN(88, "GPIO_6"),
+ PINCTRL_PIN(89, "GPIO_7"),
+ PINCTRL_PIN(90, "SATA0_LED_N"),
+ PINCTRL_PIN(91, "SATA1_LED_N"),
+ PINCTRL_PIN(92, "SATA_PDETECT0"),
+ PINCTRL_PIN(93, "SATA_PDETECT1"),
+ PINCTRL_PIN(94, "SATA0_SDOUT"),
+ PINCTRL_PIN(95, "SATA1_SDOUT"),
+ PINCTRL_PIN(96, "UART1_RXD"),
+ PINCTRL_PIN(97, "UART1_TXD"),
+ PINCTRL_PIN(98, "GPIO_8"),
+ PINCTRL_PIN(99, "GPIO_9"),
+ PINCTRL_PIN(100, "TCK"),
+ PINCTRL_PIN(101, "TRST_N"),
+ PINCTRL_PIN(102, "TMS"),
+ PINCTRL_PIN(103, "TDI"),
+ PINCTRL_PIN(104, "TDO"),
+ PINCTRL_PIN(105, "CX_PRDY_N"),
+ PINCTRL_PIN(106, "CX_PREQ_N"),
+ PINCTRL_PIN(107, "CTBTRIGINOUT"),
+ PINCTRL_PIN(108, "CTBTRIGOUT"),
+ PINCTRL_PIN(109, "DFX_SPARE2"),
+ PINCTRL_PIN(110, "DFX_SPARE3"),
+ PINCTRL_PIN(111, "DFX_SPARE4"),
+ /* South GPP1 */
+ PINCTRL_PIN(112, "SUSPWRDNACK"),
+ PINCTRL_PIN(113, "PMU_SUSCLK"),
+ PINCTRL_PIN(114, "ADR_TRIGGER"),
+ PINCTRL_PIN(115, "PMU_SLP_S45_N"),
+ PINCTRL_PIN(116, "PMU_SLP_S3_N"),
+ PINCTRL_PIN(117, "PMU_WAKE_N"),
+ PINCTRL_PIN(118, "PMU_PWRBTN_N"),
+ PINCTRL_PIN(119, "PMU_RESETBUTTON_N"),
+ PINCTRL_PIN(120, "PMU_PLTRST_N"),
+ PINCTRL_PIN(121, "SUS_STAT_N"),
+ PINCTRL_PIN(122, "SLP_S0IX_N"),
+ PINCTRL_PIN(123, "SPI_CS0_N"),
+ PINCTRL_PIN(124, "SPI_CS1_N"),
+ PINCTRL_PIN(125, "SPI_MOSI_IO0"),
+ PINCTRL_PIN(126, "SPI_MISO_IO1"),
+ PINCTRL_PIN(127, "SPI_IO2"),
+ PINCTRL_PIN(128, "SPI_IO3"),
+ PINCTRL_PIN(129, "SPI_CLK"),
+ PINCTRL_PIN(130, "SPI_CLK_LOOPBK"),
+ PINCTRL_PIN(131, "ESPI_IO0"),
+ PINCTRL_PIN(132, "ESPI_IO1"),
+ PINCTRL_PIN(133, "ESPI_IO2"),
+ PINCTRL_PIN(134, "ESPI_IO3"),
+ PINCTRL_PIN(135, "ESPI_CS0_N"),
+ PINCTRL_PIN(136, "ESPI_CLK"),
+ PINCTRL_PIN(137, "ESPI_RST_N"),
+ PINCTRL_PIN(138, "ESPI_ALRT0_N"),
+ PINCTRL_PIN(139, "GPIO_10"),
+ PINCTRL_PIN(140, "GPIO_11"),
+ PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
+ PINCTRL_PIN(142, "EMMC_CMD"),
+ PINCTRL_PIN(143, "EMMC_STROBE"),
+ PINCTRL_PIN(144, "EMMC_CLK"),
+ PINCTRL_PIN(145, "EMMC_D0"),
+ PINCTRL_PIN(146, "EMMC_D1"),
+ PINCTRL_PIN(147, "EMMC_D2"),
+ PINCTRL_PIN(148, "EMMC_D3"),
+ PINCTRL_PIN(149, "EMMC_D4"),
+ PINCTRL_PIN(150, "EMMC_D5"),
+ PINCTRL_PIN(151, "EMMC_D6"),
+ PINCTRL_PIN(152, "EMMC_D7"),
+ PINCTRL_PIN(153, "GPIO_3"),
+};
+
+static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
+static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
+static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
+static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
+static const unsigned int dnv_uart2_modes[] = { 1, 1, 2, 2 };
+static const unsigned int dnv_emmc_pins[] = {
+ 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
+};
+
+static const struct intel_pingroup dnv_groups[] = {
+ PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes),
+ PIN_GROUP("uart1_grp", dnv_uart1_pins, 1),
+ PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes),
+ PIN_GROUP("emmc_grp", dnv_emmc_pins, 1),
+};
+
+static const char * const dnv_uart0_groups[] = { "uart0_grp" };
+static const char * const dnv_uart1_groups[] = { "uart1_grp" };
+static const char * const dnv_uart2_groups[] = { "uart2_grp" };
+static const char * const dnv_emmc_groups[] = { "emmc_grp" };
+
+static const struct intel_function dnv_functions[] = {
+ FUNCTION("uart0", dnv_uart0_groups),
+ FUNCTION("uart1", dnv_uart1_groups),
+ FUNCTION("uart2", dnv_uart2_groups),
+ FUNCTION("emmc", dnv_emmc_groups),
+};
+
+static const struct intel_padgroup dnv_north_gpps[] = {
+ DNV_GPP(0, 0, 31), /* North ALL_0 */
+ DNV_GPP(1, 32, 40), /* North ALL_1 */
+};
+
+static const struct intel_padgroup dnv_south_gpps[] = {
+ DNV_GPP(0, 41, 58), /* South DFX */
+ DNV_GPP(1, 59, 90), /* South GPP0_0 */
+ DNV_GPP(2, 91, 111), /* South GPP0_1 */
+ DNV_GPP(3, 112, 143), /* South GPP1_0 */
+ DNV_GPP(4, 144, 153), /* South GPP1_1 */
+};
+
+static const struct intel_community dnv_communities[] = {
+ DNV_COMMUNITY(0, 0, 40, dnv_north_gpps),
+ DNV_COMMUNITY(1, 41, 153, dnv_south_gpps),
+};
+
+static const struct intel_pinctrl_soc_data dnv_soc_data = {
+ .pins = dnv_pins,
+ .npins = ARRAY_SIZE(dnv_pins),
+ .groups = dnv_groups,
+ .ngroups = ARRAY_SIZE(dnv_groups),
+ .functions = dnv_functions,
+ .nfunctions = ARRAY_SIZE(dnv_functions),
+ .communities = dnv_communities,
+ .ncommunities = ARRAY_SIZE(dnv_communities),
+};
+
+static int dnv_pinctrl_probe(struct platform_device *pdev)
+{
+ return intel_pinctrl_probe(pdev, &dnv_soc_data);
+}
+
+static const struct dev_pm_ops dnv_pinctrl_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
+ intel_pinctrl_resume)
+};
+
+static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
+ { "INTC3000" },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
+
+static struct platform_driver dnv_pinctrl_driver = {
+ .probe = dnv_pinctrl_probe,
+ .driver = {
+ .name = "denverton-pinctrl",
+ .acpi_match_table = dnv_pinctrl_acpi_match,
+ .pm = &dnv_pinctrl_pm_ops,
+ },
+};
+
+static int __init dnv_pinctrl_init(void)
+{
+ return platform_driver_register(&dnv_pinctrl_driver);
+}
+subsys_initcall(dnv_pinctrl_init);
+
+static void __exit dnv_pinctrl_exit(void)
+{
+ platform_driver_unregister(&dnv_pinctrl_driver);
+}
+module_exit(dnv_pinctrl_exit);
+
+MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
+MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 592b465e981e..71df0f70b61f 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -117,6 +117,7 @@ struct intel_pinctrl {
};
#define pin_to_padno(c, p) ((p) - (c)->pin_base)
+#define padgroup_offset(g, p) ((p) - (g)->base)
static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
unsigned pin)
@@ -135,6 +136,22 @@ static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
return NULL;
}
+static const struct intel_padgroup *
+intel_community_get_padgroup(const struct intel_community *community,
+ unsigned pin)
+{
+ int i;
+
+ for (i = 0; i < community->ngpps; i++) {
+ const struct intel_padgroup *padgrp = &community->gpps[i];
+
+ if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
+ return padgrp;
+ }
+
+ return NULL;
+}
+
static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
unsigned reg)
{
@@ -158,7 +175,8 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
{
const struct intel_community *community;
- unsigned padno, gpp, offset, group;
+ const struct intel_padgroup *padgrp;
+ unsigned gpp, offset, gpp_offset;
void __iomem *padown;
community = intel_get_community(pctrl, pin);
@@ -167,19 +185,23 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
if (!community->padown_offset)
return true;
- padno = pin_to_padno(community, pin);
- group = padno / community->gpp_size;
- gpp = PADOWN_GPP(padno % community->gpp_size);
- offset = community->padown_offset + 0x10 * group + gpp * 4;
+ padgrp = intel_community_get_padgroup(community, pin);
+ if (!padgrp)
+ return false;
+
+ gpp_offset = padgroup_offset(padgrp, pin);
+ gpp = PADOWN_GPP(gpp_offset);
+ offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
padown = community->regs + offset;
- return !(readl(padown) & PADOWN_MASK(padno));
+ return !(readl(padown) & PADOWN_MASK(gpp_offset));
}
static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
{
const struct intel_community *community;
- unsigned padno, gpp, offset;
+ const struct intel_padgroup *padgrp;
+ unsigned offset, gpp_offset;
void __iomem *hostown;
community = intel_get_community(pctrl, pin);
@@ -188,18 +210,22 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
if (!community->hostown_offset)
return false;
- padno = pin_to_padno(community, pin);
- gpp = padno / community->gpp_size;
- offset = community->hostown_offset + gpp * 4;
+ padgrp = intel_community_get_padgroup(community, pin);
+ if (!padgrp)
+ return true;
+
+ gpp_offset = padgroup_offset(padgrp, pin);
+ offset = community->hostown_offset + padgrp->reg_num * 4;
hostown = community->regs + offset;
- return !(readl(hostown) & BIT(padno % community->gpp_size));
+ return !(readl(hostown) & BIT(gpp_offset));
}
static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
{
struct intel_community *community;
- unsigned padno, gpp, offset;
+ const struct intel_padgroup *padgrp;
+ unsigned offset, gpp_offset;
u32 value;
community = intel_get_community(pctrl, pin);
@@ -208,22 +234,25 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
if (!community->padcfglock_offset)
return false;
- padno = pin_to_padno(community, pin);
- gpp = padno / community->gpp_size;
+ padgrp = intel_community_get_padgroup(community, pin);
+ if (!padgrp)
+ return true;
+
+ gpp_offset = padgroup_offset(padgrp, pin);
/*
* If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
* the pad is considered unlocked. Any other case means that it is
* either fully or partially locked and we don't touch it.
*/
- offset = community->padcfglock_offset + gpp * 8;
+ offset = community->padcfglock_offset + padgrp->reg_num * 8;
value = readl(community->regs + offset);
- if (value & BIT(pin % community->gpp_size))
+ if (value & BIT(gpp_offset))
return true;
- offset = community->padcfglock_offset + 4 + gpp * 8;
+ offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
value = readl(community->regs + offset);
- if (value & BIT(pin % community->gpp_size))
+ if (value & BIT(gpp_offset))
return true;
return false;
@@ -369,7 +398,11 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
value = readl(padcfg0);
value &= ~PADCFG0_PMODE_MASK;
- value |= grp->mode << PADCFG0_PMODE_SHIFT;
+
+ if (grp->modes)
+ value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
+ else
+ value |= grp->mode << PADCFG0_PMODE_SHIFT;
writel(value, padcfg0);
}
@@ -718,33 +751,38 @@ static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
void __iomem *reg;
+ u32 padcfg0;
reg = intel_get_padcfg(pctrl, offset, PADCFG0);
if (!reg)
return -EINVAL;
- return !!(readl(reg) & PADCFG0_GPIORXSTATE);
+ padcfg0 = readl(reg);
+ if (!(padcfg0 & PADCFG0_GPIOTXDIS))
+ return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
+
+ return !!(padcfg0 & PADCFG0_GPIORXSTATE);
}
static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
+ unsigned long flags;
void __iomem *reg;
+ u32 padcfg0;
reg = intel_get_padcfg(pctrl, offset, PADCFG0);
- if (reg) {
- unsigned long flags;
- u32 padcfg0;
+ if (!reg)
+ return;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
- padcfg0 = readl(reg);
- if (value)
- padcfg0 |= PADCFG0_GPIOTXSTATE;
- else
- padcfg0 &= ~PADCFG0_GPIOTXSTATE;
- writel(padcfg0, reg);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
- }
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+ padcfg0 = readl(reg);
+ if (value)
+ padcfg0 |= PADCFG0_GPIOTXSTATE;
+ else
+ padcfg0 &= ~PADCFG0_GPIOTXSTATE;
+ writel(padcfg0, reg);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -777,18 +815,22 @@ static void intel_gpio_irq_ack(struct irq_data *d)
const struct intel_community *community;
unsigned pin = irqd_to_hwirq(d);
- raw_spin_lock(&pctrl->lock);
-
community = intel_get_community(pctrl, pin);
if (community) {
- unsigned padno = pin_to_padno(community, pin);
- unsigned gpp_offset = padno % community->gpp_size;
- unsigned gpp = padno / community->gpp_size;
+ const struct intel_padgroup *padgrp;
+ unsigned gpp, gpp_offset;
+
+ padgrp = intel_community_get_padgroup(community, pin);
+ if (!padgrp)
+ return;
+ gpp = padgrp->reg_num;
+ gpp_offset = padgroup_offset(padgrp, pin);
+
+ raw_spin_lock(&pctrl->lock);
writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
+ raw_spin_unlock(&pctrl->lock);
}
-
- raw_spin_unlock(&pctrl->lock);
}
static void intel_gpio_irq_enable(struct irq_data *d)
@@ -797,27 +839,30 @@ static void intel_gpio_irq_enable(struct irq_data *d)
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
const struct intel_community *community;
unsigned pin = irqd_to_hwirq(d);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&pctrl->lock, flags);
community = intel_get_community(pctrl, pin);
if (community) {
- unsigned padno = pin_to_padno(community, pin);
- unsigned gpp_size = community->gpp_size;
- unsigned gpp_offset = padno % gpp_size;
- unsigned gpp = padno / gpp_size;
+ const struct intel_padgroup *padgrp;
+ unsigned gpp, gpp_offset;
+ unsigned long flags;
u32 value;
+ padgrp = intel_community_get_padgroup(community, pin);
+ if (!padgrp)
+ return;
+
+ gpp = padgrp->reg_num;
+ gpp_offset = padgroup_offset(padgrp, pin);
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
/* Clear interrupt status first to avoid unexpected interrupt */
writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
value = readl(community->regs + community->ie_offset + gpp * 4);
value |= BIT(gpp_offset);
writel(value, community->regs + community->ie_offset + gpp * 4);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
-
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
@@ -826,28 +871,33 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
const struct intel_community *community;
unsigned pin = irqd_to_hwirq(d);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&pctrl->lock, flags);
community = intel_get_community(pctrl, pin);
if (community) {
- unsigned padno = pin_to_padno(community, pin);
- unsigned gpp_offset = padno % community->gpp_size;
- unsigned gpp = padno / community->gpp_size;
+ const struct intel_padgroup *padgrp;
+ unsigned gpp, gpp_offset;
+ unsigned long flags;
void __iomem *reg;
u32 value;
+ padgrp = intel_community_get_padgroup(community, pin);
+ if (!padgrp)
+ return;
+
+ gpp = padgrp->reg_num;
+ gpp_offset = padgroup_offset(padgrp, pin);
+
reg = community->regs + community->ie_offset + gpp * 4;
+
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
value = readl(reg);
if (mask)
value &= ~BIT(gpp_offset);
else
value |= BIT(gpp_offset);
writel(value, reg);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
-
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void intel_gpio_irq_mask(struct irq_data *d)
@@ -938,23 +988,20 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
int gpp;
for (gpp = 0; gpp < community->ngpps; gpp++) {
+ const struct intel_padgroup *padgrp = &community->gpps[gpp];
unsigned long pending, enabled, gpp_offset;
- pending = readl(community->regs + GPI_IS + gpp * 4);
+ pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4);
enabled = readl(community->regs + community->ie_offset +
- gpp * 4);
+ padgrp->reg_num * 4);
/* Only interrupts that are enabled */
pending &= enabled;
- for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
+ for_each_set_bit(gpp_offset, &pending, padgrp->size) {
unsigned padno, irq;
- /*
- * The last group in community can have less pins
- * than NPADS_IN_GPP.
- */
- padno = gpp_offset + gpp * community->gpp_size;
+ padno = padgrp->base - community->pin_base + gpp_offset;
if (padno >= community->npins)
break;
@@ -993,6 +1040,7 @@ static struct irq_chip intel_gpio_irqchip = {
.irq_unmask = intel_gpio_irq_unmask,
.irq_set_type = intel_gpio_irq_type,
.irq_set_wake = intel_gpio_irq_wake,
+ .flags = IRQCHIP_MASK_ON_SUSPEND,
};
static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
@@ -1045,6 +1093,56 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
return 0;
}
+static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
+ struct intel_community *community)
+{
+ struct intel_padgroup *gpps;
+ unsigned npins = community->npins;
+ unsigned padown_num = 0;
+ size_t ngpps, i;
+
+ if (community->gpps)
+ ngpps = community->ngpps;
+ else
+ ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
+
+ gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
+ if (!gpps)
+ return -ENOMEM;
+
+ for (i = 0; i < ngpps; i++) {
+ if (community->gpps) {
+ gpps[i] = community->gpps[i];
+ } else {
+ unsigned gpp_size = community->gpp_size;
+
+ gpps[i].reg_num = i;
+ gpps[i].base = community->pin_base + i * gpp_size;
+ gpps[i].size = min(gpp_size, npins);
+ npins -= gpps[i].size;
+ }
+
+ if (gpps[i].size > 32)
+ return -EINVAL;
+
+ gpps[i].padown_num = padown_num;
+
+ /*
+ * In older hardware the number of padown registers per
+ * group is fixed regardless of the group size.
+ */
+ if (community->gpp_num_padown_regs)
+ padown_num += community->gpp_num_padown_regs;
+ else
+ padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
+ }
+
+ community->ngpps = ngpps;
+ community->gpps = gpps;
+
+ return 0;
+}
+
static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
{
#ifdef CONFIG_PM_SLEEP
@@ -1142,8 +1240,10 @@ int intel_pinctrl_probe(struct platform_device *pdev,
community->regs = regs;
community->pad_regs = regs + padbar;
- community->ngpps = DIV_ROUND_UP(community->npins,
- community->gpp_size);
+
+ ret = intel_pinctrl_add_padgroups(pctrl, community);
+ if (ret)
+ return ret;
}
irq = platform_get_irq(pdev, 0);
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index fe9521f345b5..7fdb07753c2d 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -22,13 +22,16 @@ struct device;
* @name: Name of the groups
* @pins: All pins in this group
* @npins: Number of pins in this groups
- * @mode: Native mode in which the group is muxed out @pins
+ * @mode: Native mode in which the group is muxed out @pins. Used if @modes
+ * is %NULL.
+ * @modes: If not %NULL this will hold mode for each pin in @pins
*/
struct intel_pingroup {
const char *name;
const unsigned *pins;
size_t npins;
unsigned short mode;
+ const unsigned *modes;
};
/**
@@ -44,6 +47,23 @@ struct intel_function {
};
/**
+ * struct intel_padgroup - Hardware pad group information
+ * @reg_num: GPI_IS register number
+ * @base: Starting pin of this group
+ * @size: Size of this group (maximum is 32).
+ * @padown_num: PAD_OWN register number (assigned by the core driver)
+ *
+ * If pad groups of a community are not the same size, use this structure
+ * to specify them.
+ */
+struct intel_padgroup {
+ unsigned reg_num;
+ unsigned base;
+ unsigned size;
+ unsigned padown_num;
+};
+
+/**
* struct intel_community - Intel pin community description
* @barno: MMIO BAR number where registers for this community reside
* @padown_offset: Register offset of PAD_OWN register from @regs. If %0
@@ -56,13 +76,22 @@ struct intel_function {
* @ie_offset: Register offset of GPI_IE from @regs.
* @pin_base: Starting pin of pins in this community
* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
- * HOSTSW_OWN, GPI_IS, GPI_IE, etc.
+ * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL.
+ * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
+ * minimum. Use %0 if the number of registers can be
+ * determined by the size of the group.
* @npins: Number of pins in this community
* @features: Additional features supported by the hardware
+ * @gpps: Pad groups if the controller has variable size pad groups
+ * @ngpps: Number of pad groups in this community
* @regs: Community specific common registers (reserved for core driver)
* @pad_regs: Community specific pad registers (reserved for core driver)
- * @ngpps: Number of groups (hw groups) in this community (reserved for
- * core driver)
+ *
+ * Most Intel GPIO host controllers this driver supports each pad group is
+ * of equal size (except the last one). In that case the driver can just
+ * fill in @gpp_size field and let the core driver to handle the rest. If
+ * the controller has pad groups of variable size the client driver can
+ * pass custom @gpps and @ngpps instead.
*/
struct intel_community {
unsigned barno;
@@ -72,23 +101,37 @@ struct intel_community {
unsigned ie_offset;
unsigned pin_base;
unsigned gpp_size;
+ unsigned gpp_num_padown_regs;
size_t npins;
unsigned features;
+ const struct intel_padgroup *gpps;
+ size_t ngpps;
+ /* Reserved for the core driver */
void __iomem *regs;
void __iomem *pad_regs;
- size_t ngpps;
};
/* Additional features supported by the hardware */
#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
#define PINCTRL_FEATURE_1K_PD BIT(1)
-#define PIN_GROUP(n, p, m) \
- { \
- .name = (n), \
- .pins = (p), \
- .npins = ARRAY_SIZE((p)), \
- .mode = (m), \
+/**
+ * PIN_GROUP - Declare a pin group
+ * @n: Name of the group
+ * @p: An array of pins this group consists
+ * @m: Mode which the pins are put when this group is active. Can be either
+ * a single integer or an array of integers in which case mode is per
+ * pin.
+ */
+#define PIN_GROUP(n, p, m) \
+ { \
+ .name = (n), \
+ .pins = (p), \
+ .npins = ARRAY_SIZE((p)), \
+ .mode = __builtin_choose_expr( \
+ __builtin_constant_p((m)), (m), 0), \
+ .modes = __builtin_choose_expr( \
+ __builtin_constant_p((m)), NULL, (m)), \
}
#define FUNCTION(n, g) \
diff --git a/drivers/pinctrl/intel/pinctrl-lewisburg.c b/drivers/pinctrl/intel/pinctrl-lewisburg.c
new file mode 100644
index 000000000000..14d56ea6cfdc
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-lewisburg.c
@@ -0,0 +1,343 @@
+/*
+ * Intel Lewisburg pinctrl/GPIO driver
+ *
+ * Copyright (C) 2017, Intel Corporation
+ * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+#define LBG_PAD_OWN 0x020
+#define LBG_PADCFGLOCK 0x060
+#define LBG_HOSTSW_OWN 0x080
+#define LBG_GPI_IE 0x110
+
+#define LBG_COMMUNITY(b, s, e) \
+ { \
+ .barno = (b), \
+ .padown_offset = LBG_PAD_OWN, \
+ .padcfglock_offset = LBG_PADCFGLOCK, \
+ .hostown_offset = LBG_HOSTSW_OWN, \
+ .ie_offset = LBG_GPI_IE, \
+ .gpp_size = 24, \
+ .pin_base = (s), \
+ .npins = ((e) - (s) + 1), \
+ }
+
+static const struct pinctrl_pin_desc lbg_pins[] = {
+ /* GPP_A */
+ PINCTRL_PIN(0, "RCINB"),
+ PINCTRL_PIN(1, "LAD_0"),
+ PINCTRL_PIN(2, "LAD_1"),
+ PINCTRL_PIN(3, "LAD_2"),
+ PINCTRL_PIN(4, "LAD_3"),
+ PINCTRL_PIN(5, "LFRAMEB"),
+ PINCTRL_PIN(6, "SERIRQ"),
+ PINCTRL_PIN(7, "PIRQAB"),
+ PINCTRL_PIN(8, "CLKRUNB"),
+ PINCTRL_PIN(9, "CLKOUT_LPC_0"),
+ PINCTRL_PIN(10, "CLKOUT_LPC_1"),
+ PINCTRL_PIN(11, "PMEB"),
+ PINCTRL_PIN(12, "BM_BUSYB"),
+ PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
+ PINCTRL_PIN(14, "ESPI_RESETB"),
+ PINCTRL_PIN(15, "SUSACKB"),
+ PINCTRL_PIN(16, "CLKOUT_LPC_2"),
+ PINCTRL_PIN(17, "GPP_A_17"),
+ PINCTRL_PIN(18, "GPP_A_18"),
+ PINCTRL_PIN(19, "GPP_A_19"),
+ PINCTRL_PIN(20, "GPP_A_20"),
+ PINCTRL_PIN(21, "GPP_A_21"),
+ PINCTRL_PIN(22, "GPP_A_22"),
+ PINCTRL_PIN(23, "GPP_A_23"),
+ /* GPP_B */
+ PINCTRL_PIN(24, "CORE_VID_0"),
+ PINCTRL_PIN(25, "CORE_VID_1"),
+ PINCTRL_PIN(26, "VRALERTB"),
+ PINCTRL_PIN(27, "CPU_GP_2"),
+ PINCTRL_PIN(28, "CPU_GP_3"),
+ PINCTRL_PIN(29, "SRCCLKREQB_0"),
+ PINCTRL_PIN(30, "SRCCLKREQB_1"),
+ PINCTRL_PIN(31, "SRCCLKREQB_2"),
+ PINCTRL_PIN(32, "SRCCLKREQB_3"),
+ PINCTRL_PIN(33, "SRCCLKREQB_4"),
+ PINCTRL_PIN(34, "SRCCLKREQB_5"),
+ PINCTRL_PIN(35, "GPP_B_11"),
+ PINCTRL_PIN(36, "GLB_RST_WARN_N"),
+ PINCTRL_PIN(37, "PLTRSTB"),
+ PINCTRL_PIN(38, "SPKR"),
+ PINCTRL_PIN(39, "GPP_B_15"),
+ PINCTRL_PIN(40, "GPP_B_16"),
+ PINCTRL_PIN(41, "GPP_B_17"),
+ PINCTRL_PIN(42, "GPP_B_18"),
+ PINCTRL_PIN(43, "GPP_B_19"),
+ PINCTRL_PIN(44, "GPP_B_20"),
+ PINCTRL_PIN(45, "GPP_B_21"),
+ PINCTRL_PIN(46, "GPP_B_22"),
+ PINCTRL_PIN(47, "SML1ALERTB"),
+ /* GPP_F */
+ PINCTRL_PIN(48, "SATAXPCIE_3"),
+ PINCTRL_PIN(49, "SATAXPCIE_4"),
+ PINCTRL_PIN(50, "SATAXPCIE_5"),
+ PINCTRL_PIN(51, "SATAXPCIE_6"),
+ PINCTRL_PIN(52, "SATAXPCIE_7"),
+ PINCTRL_PIN(53, "SATA_DEVSLP_3"),
+ PINCTRL_PIN(54, "SATA_DEVSLP_4"),
+ PINCTRL_PIN(55, "SATA_DEVSLP_5"),
+ PINCTRL_PIN(56, "SATA_DEVSLP_6"),
+ PINCTRL_PIN(57, "SATA_DEVSLP_7"),
+ PINCTRL_PIN(58, "SATA_SCLOCK"),
+ PINCTRL_PIN(59, "SATA_SLOAD"),
+ PINCTRL_PIN(60, "SATA_SDATAOUT1"),
+ PINCTRL_PIN(61, "SATA_SDATAOUT0"),
+ PINCTRL_PIN(62, "SSATA_LEDB"),
+ PINCTRL_PIN(63, "USB2_OCB_4"),
+ PINCTRL_PIN(64, "USB2_OCB_5"),
+ PINCTRL_PIN(65, "USB2_OCB_6"),
+ PINCTRL_PIN(66, "USB2_OCB_7"),
+ PINCTRL_PIN(67, "GBE_SMBUS_CLK"),
+ PINCTRL_PIN(68, "GBE_SMBDATA"),
+ PINCTRL_PIN(69, "GBE_SMBALRTN"),
+ PINCTRL_PIN(70, "SSATA_SCLOCK"),
+ PINCTRL_PIN(71, "SSATA_SLOAD"),
+ /* GPP_C */
+ PINCTRL_PIN(72, "SMBCLK"),
+ PINCTRL_PIN(73, "SMBDATA"),
+ PINCTRL_PIN(74, "SMBALERTB"),
+ PINCTRL_PIN(75, "SML0CLK"),
+ PINCTRL_PIN(76, "SML0DATA"),
+ PINCTRL_PIN(77, "SML0ALERTB"),
+ PINCTRL_PIN(78, "SML1CLK"),
+ PINCTRL_PIN(79, "SML1DATA"),
+ PINCTRL_PIN(80, "GPP_C_8"),
+ PINCTRL_PIN(81, "GPP_C_9"),
+ PINCTRL_PIN(82, "GPP_C_10"),
+ PINCTRL_PIN(83, "GPP_C_11"),
+ PINCTRL_PIN(84, "GPP_C_12"),
+ PINCTRL_PIN(85, "GPP_C_13"),
+ PINCTRL_PIN(86, "GPP_C_14"),
+ PINCTRL_PIN(87, "GPP_C_15"),
+ PINCTRL_PIN(88, "GPP_C_16"),
+ PINCTRL_PIN(89, "GPP_C_17"),
+ PINCTRL_PIN(90, "GPP_C_18"),
+ PINCTRL_PIN(91, "GPP_C_19"),
+ PINCTRL_PIN(92, "GPP_C_20"),
+ PINCTRL_PIN(93, "GPP_C_21"),
+ PINCTRL_PIN(94, "GPP_C_22"),
+ PINCTRL_PIN(95, "GPP_C_23"),
+ /* GPP_D */
+ PINCTRL_PIN(96, "GPP_D_0"),
+ PINCTRL_PIN(97, "GPP_D_1"),
+ PINCTRL_PIN(98, "GPP_D_2"),
+ PINCTRL_PIN(99, "GPP_D_3"),
+ PINCTRL_PIN(100, "GPP_D_4"),
+ PINCTRL_PIN(101, "SSP0_SFRM"),
+ PINCTRL_PIN(102, "SSP0_TXD"),
+ PINCTRL_PIN(103, "SSP0_RXD"),
+ PINCTRL_PIN(104, "SSP0_SCLK"),
+ PINCTRL_PIN(105, "SSATA_DEVSLP_3"),
+ PINCTRL_PIN(106, "SSATA_DEVSLP_4"),
+ PINCTRL_PIN(107, "SSATA_DEVSLP_5"),
+ PINCTRL_PIN(108, "SSATA_SDATAOUT1"),
+ PINCTRL_PIN(109, "SML0BCLK_SML0BCLKIE"),
+ PINCTRL_PIN(110, "SML0BDATA_SML0BDATAIE"),
+ PINCTRL_PIN(111, "SSATA_SDATAOUT0"),
+ PINCTRL_PIN(112, "SML0BALERTB_SML0BALERTBIE"),
+ PINCTRL_PIN(113, "DMIC_CLK_1"),
+ PINCTRL_PIN(114, "DMIC_DATA_1"),
+ PINCTRL_PIN(115, "DMIC_CLK_0"),
+ PINCTRL_PIN(116, "DMIC_DATA_0"),
+ PINCTRL_PIN(117, "IE_UART_RXD"),
+ PINCTRL_PIN(118, "IE_UART_TXD"),
+ PINCTRL_PIN(119, "GPP_D_23"),
+ /* GPP_E */
+ PINCTRL_PIN(120, "SATAXPCIE_0"),
+ PINCTRL_PIN(121, "SATAXPCIE_1"),
+ PINCTRL_PIN(122, "SATAXPCIE_2"),
+ PINCTRL_PIN(123, "CPU_GP_0"),
+ PINCTRL_PIN(124, "SATA_DEVSLP_0"),
+ PINCTRL_PIN(125, "SATA_DEVSLP_1"),
+ PINCTRL_PIN(126, "SATA_DEVSLP_2"),
+ PINCTRL_PIN(127, "CPU_GP_1"),
+ PINCTRL_PIN(128, "SATA_LEDB"),
+ PINCTRL_PIN(129, "USB2_OCB_0"),
+ PINCTRL_PIN(130, "USB2_OCB_1"),
+ PINCTRL_PIN(131, "USB2_OCB_2"),
+ PINCTRL_PIN(132, "USB2_OCB_3"),
+ /* GPP_I */
+ PINCTRL_PIN(133, "GBE_TDO"),
+ PINCTRL_PIN(134, "GBE_TCK"),
+ PINCTRL_PIN(135, "GBE_TMS"),
+ PINCTRL_PIN(136, "GBE_TDI"),
+ PINCTRL_PIN(137, "DO_RESET_INB"),
+ PINCTRL_PIN(138, "DO_RESET_OUTB"),
+ PINCTRL_PIN(139, "RESET_DONE"),
+ PINCTRL_PIN(140, "GBE_TRST_N"),
+ PINCTRL_PIN(141, "GBE_PCI_DIS"),
+ PINCTRL_PIN(142, "GBE_LAN_DIS"),
+ PINCTRL_PIN(143, "GPP_I_10"),
+ PINCTRL_PIN(144, "GPIO_RCOMP_3P3"),
+ /* GPP_J */
+ PINCTRL_PIN(145, "GBE_LED_0_0"),
+ PINCTRL_PIN(146, "GBE_LED_0_1"),
+ PINCTRL_PIN(147, "GBE_LED_1_0"),
+ PINCTRL_PIN(148, "GBE_LED_1_1"),
+ PINCTRL_PIN(149, "GBE_LED_2_0"),
+ PINCTRL_PIN(150, "GBE_LED_2_1"),
+ PINCTRL_PIN(151, "GBE_LED_3_0"),
+ PINCTRL_PIN(152, "GBE_LED_3_1"),
+ PINCTRL_PIN(153, "GBE_SCL_0"),
+ PINCTRL_PIN(154, "GBE_SDA_0"),
+ PINCTRL_PIN(155, "GBE_SCL_1"),
+ PINCTRL_PIN(156, "GBE_SDA_1"),
+ PINCTRL_PIN(157, "GBE_SCL_2"),
+ PINCTRL_PIN(158, "GBE_SDA_2"),
+ PINCTRL_PIN(159, "GBE_SCL_3"),
+ PINCTRL_PIN(160, "GBE_SDA_3"),
+ PINCTRL_PIN(161, "GBE_SDP_0_0"),
+ PINCTRL_PIN(162, "GBE_SDP_0_1"),
+ PINCTRL_PIN(163, "GBE_SDP_1_0"),
+ PINCTRL_PIN(164, "GBE_SDP_1_1"),
+ PINCTRL_PIN(165, "GBE_SDP_2_0"),
+ PINCTRL_PIN(166, "GBE_SDP_2_1"),
+ PINCTRL_PIN(167, "GBE_SDP_3_0"),
+ PINCTRL_PIN(168, "GBE_SDP_3_1"),
+ /* GPP_K */
+ PINCTRL_PIN(169, "GBE_RMIICLK"),
+ PINCTRL_PIN(170, "GBE_RMII_TXD_0"),
+ PINCTRL_PIN(171, "GBE_RMII_TXD_1"),
+ PINCTRL_PIN(172, "GBE_RMII_TX_EN"),
+ PINCTRL_PIN(173, "GBE_RMII_CRS_DV"),
+ PINCTRL_PIN(174, "GBE_RMII_RXD_0"),
+ PINCTRL_PIN(175, "GBE_RMII_RXD_1"),
+ PINCTRL_PIN(176, "GBE_RMII_RX_ER"),
+ PINCTRL_PIN(177, "GBE_RMII_ARBIN"),
+ PINCTRL_PIN(178, "GBE_RMII_ARB_OUT"),
+ PINCTRL_PIN(179, "PE_RST_N"),
+ PINCTRL_PIN(180, "GPIO_RCOMP_1P8_3P3"),
+ /* GPP_G */
+ PINCTRL_PIN(181, "FAN_TACH_0"),
+ PINCTRL_PIN(182, "FAN_TACH_1"),
+ PINCTRL_PIN(183, "FAN_TACH_2"),
+ PINCTRL_PIN(184, "FAN_TACH_3"),
+ PINCTRL_PIN(185, "FAN_TACH_4"),
+ PINCTRL_PIN(186, "FAN_TACH_5"),
+ PINCTRL_PIN(187, "FAN_TACH_6"),
+ PINCTRL_PIN(188, "FAN_TACH_7"),
+ PINCTRL_PIN(189, "FAN_PWM_0"),
+ PINCTRL_PIN(190, "FAN_PWM_1"),
+ PINCTRL_PIN(191, "FAN_PWM_2"),
+ PINCTRL_PIN(192, "FAN_PWM_3"),
+ PINCTRL_PIN(193, "GSXDOUT"),
+ PINCTRL_PIN(194, "GSXSLOAD"),
+ PINCTRL_PIN(195, "GSXDIN"),
+ PINCTRL_PIN(196, "GSXSRESETB"),
+ PINCTRL_PIN(197, "GSXCLK"),
+ PINCTRL_PIN(198, "ADR_COMPLETE"),
+ PINCTRL_PIN(199, "NMIB"),
+ PINCTRL_PIN(200, "SMIB"),
+ PINCTRL_PIN(201, "SSATA_DEVSLP_0"),
+ PINCTRL_PIN(202, "SSATA_DEVSLP_1"),
+ PINCTRL_PIN(203, "SSATA_DEVSLP_2"),
+ PINCTRL_PIN(204, "SSATAXPCIE0_SSATAGP0"),
+ /* GPP_H */
+ PINCTRL_PIN(205, "SRCCLKREQB_6"),
+ PINCTRL_PIN(206, "SRCCLKREQB_7"),
+ PINCTRL_PIN(207, "SRCCLKREQB_8"),
+ PINCTRL_PIN(208, "SRCCLKREQB_9"),
+ PINCTRL_PIN(209, "SRCCLKREQB_10"),
+ PINCTRL_PIN(210, "SRCCLKREQB_11"),
+ PINCTRL_PIN(211, "SRCCLKREQB_12"),
+ PINCTRL_PIN(212, "SRCCLKREQB_13"),
+ PINCTRL_PIN(213, "SRCCLKREQB_14"),
+ PINCTRL_PIN(214, "SRCCLKREQB_15"),
+ PINCTRL_PIN(215, "SML2CLK"),
+ PINCTRL_PIN(216, "SML2DATA"),
+ PINCTRL_PIN(217, "SML2ALERTB"),
+ PINCTRL_PIN(218, "SML3CLK"),
+ PINCTRL_PIN(219, "SML3DATA"),
+ PINCTRL_PIN(220, "SML3ALERTB"),
+ PINCTRL_PIN(221, "SML4CLK"),
+ PINCTRL_PIN(222, "SML4DATA"),
+ PINCTRL_PIN(223, "SML4ALERTB"),
+ PINCTRL_PIN(224, "SSATAXPCIE1_SSATAGP1"),
+ PINCTRL_PIN(225, "SSATAXPCIE2_SSATAGP2"),
+ PINCTRL_PIN(226, "SSATAXPCIE3_SSATAGP3"),
+ PINCTRL_PIN(227, "SSATAXPCIE4_SSATAGP4"),
+ PINCTRL_PIN(228, "SSATAXPCIE5_SSATAGP5"),
+ /* GPP_L */
+ PINCTRL_PIN(229, "VISA2CH0_D0"),
+ PINCTRL_PIN(230, "VISA2CH0_D1"),
+ PINCTRL_PIN(231, "VISA2CH0_D2"),
+ PINCTRL_PIN(232, "VISA2CH0_D3"),
+ PINCTRL_PIN(233, "VISA2CH0_D4"),
+ PINCTRL_PIN(234, "VISA2CH0_D5"),
+ PINCTRL_PIN(235, "VISA2CH0_D6"),
+ PINCTRL_PIN(236, "VISA2CH0_D7"),
+ PINCTRL_PIN(237, "VISA2CH0_CLK"),
+ PINCTRL_PIN(238, "VISA2CH1_D0"),
+ PINCTRL_PIN(239, "VISA2CH1_D1"),
+ PINCTRL_PIN(240, "VISA2CH1_D2"),
+ PINCTRL_PIN(241, "VISA2CH1_D3"),
+ PINCTRL_PIN(242, "VISA2CH1_D4"),
+ PINCTRL_PIN(243, "VISA2CH1_D5"),
+ PINCTRL_PIN(244, "VISA2CH1_D6"),
+ PINCTRL_PIN(245, "VISA2CH1_D7"),
+ PINCTRL_PIN(246, "VISA2CH1_CLK"),
+};
+
+static const struct intel_community lbg_communities[] = {
+ LBG_COMMUNITY(0, 0, 71),
+ LBG_COMMUNITY(1, 72, 132),
+ LBG_COMMUNITY(3, 133, 144),
+ LBG_COMMUNITY(4, 145, 180),
+ LBG_COMMUNITY(5, 181, 246),
+};
+
+static const struct intel_pinctrl_soc_data lbg_soc_data = {
+ .pins = lbg_pins,
+ .npins = ARRAY_SIZE(lbg_pins),
+ .communities = lbg_communities,
+ .ncommunities = ARRAY_SIZE(lbg_communities),
+};
+
+static int lbg_pinctrl_probe(struct platform_device *pdev)
+{
+ return intel_pinctrl_probe(pdev, &lbg_soc_data);
+}
+
+static const struct dev_pm_ops lbg_pinctrl_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
+ intel_pinctrl_resume)
+};
+
+static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
+ { "INT3536" },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, lbg_pinctrl_acpi_match);
+
+static struct platform_driver lbg_pinctrl_driver = {
+ .probe = lbg_pinctrl_probe,
+ .driver = {
+ .name = "lewisburg-pinctrl",
+ .acpi_match_table = lbg_pinctrl_acpi_match,
+ .pm = &lbg_pinctrl_pm_ops,
+ },
+};
+
+module_platform_driver(lbg_pinctrl_driver);
+
+MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
+MODULE_DESCRIPTION("Intel Lewisburg pinctrl/GPIO driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c
index 4d4ef42a39b5..86c4b3fab7b0 100644
--- a/drivers/pinctrl/intel/pinctrl-merrifield.c
+++ b/drivers/pinctrl/intel/pinctrl-merrifield.c
@@ -343,9 +343,9 @@ static const struct pinctrl_pin_desc mrfld_pins[] = {
static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
-static const unsigned int mrfld_uart0_pins[] = { 124, 125, 126, 127 };
-static const unsigned int mrfld_uart1_pins[] = { 128, 129, 130, 131 };
-static const unsigned int mrfld_uart2_pins[] = { 132, 133, 134, 135 };
+static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
+static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
+static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
static const unsigned int mrfld_pwm0_pins[] = { 144 };
static const unsigned int mrfld_pwm1_pins[] = { 145 };
static const unsigned int mrfld_pwm2_pins[] = { 132 };
diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
index 9877526c0807..8870a4100164 100644
--- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
@@ -31,6 +31,7 @@
.hostown_offset = SPT_HOSTSW_OWN, \
.ie_offset = SPT_GPI_IE, \
.gpp_size = 24, \
+ .gpp_num_padown_regs = 4, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
}
generated by cgit (git 2.34.1) at 2025-04-25 06:15:11 +0000