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-rw-r--r--drivers/pinctrl/mvebu/Kconfig12
-rw-r--r--drivers/pinctrl/mvebu/Makefile2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-37xx.c238
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-ap806.c140
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-cp110.c687
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.c6
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.h2
7 files changed, 1073 insertions, 14 deletions
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 5bade32d3089..d9773b77ff9f 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -1,5 +1,3 @@
-if PLAT_ORION
-
config PINCTRL_MVEBU
bool
select PINMUX
@@ -30,6 +28,14 @@ config PINCTRL_ARMADA_39X
bool
select PINCTRL_MVEBU
+config PINCTRL_ARMADA_AP806
+ bool
+ select PINCTRL_MVEBU
+
+config PINCTRL_ARMADA_CP110
+ bool
+ select PINCTRL_MVEBU
+
config PINCTRL_ARMADA_XP
bool
select PINCTRL_MVEBU
@@ -38,8 +44,6 @@ config PINCTRL_ORION
bool
select PINCTRL_MVEBU
-endif
-
config PINCTRL_ARMADA_37XX
bool
select GENERIC_PINCONF
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 60c245a60f39..5b03fd55e28d 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -5,6 +5,8 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
+obj-$(CONFIG_PINCTRL_ARMADA_AP806) += pinctrl-armada-ap806.o
+obj-$(CONFIG_PINCTRL_ARMADA_CP110) += pinctrl-armada-cp110.o
obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
obj-$(CONFIG_PINCTRL_ARMADA_37XX) += pinctrl-armada-37xx.o
obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5c96f5558310..f024e25787fc 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -13,7 +13,9 @@
#include <linux/gpio/driver.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_device.h>
+#include <linux/of_irq.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
@@ -30,6 +32,11 @@
#define OUTPUT_CTL 0x20
#define SELECTION 0x30
+#define IRQ_EN 0x0
+#define IRQ_POL 0x08
+#define IRQ_STATUS 0x10
+#define IRQ_WKUP 0x18
+
#define NB_FUNCS 2
#define GPIO_PER_REG 32
@@ -75,9 +82,12 @@ struct armada_37xx_pmx_func {
struct armada_37xx_pinctrl {
struct regmap *regmap;
+ void __iomem *base;
const struct armada_37xx_pin_data *data;
struct device *dev;
struct gpio_chip gpio_chip;
+ struct irq_chip irq_chip;
+ spinlock_t irq_lock;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct armada_37xx_pin_group *groups;
@@ -147,8 +157,9 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
- PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19),
- BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"),
+ PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
+ BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
+ 18, 2, "gpio", "uart"),
PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
@@ -159,8 +170,8 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
- PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"),
- PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
+ PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
+ PIN_GRP_EXTRA("rgmii", 6, 12, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
@@ -346,6 +357,14 @@ static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
return armada_37xx_pmx_set_by_name(pctldev, name, grp);
}
+static inline void armada_37xx_irq_update_reg(unsigned int *reg,
+ struct irq_data *d)
+{
+ int offset = irqd_to_hwirq(d);
+
+ armada_37xx_update_reg(reg, offset);
+}
+
static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
@@ -468,6 +487,214 @@ static const struct gpio_chip armada_37xx_gpiolib_chip = {
.owner = THIS_MODULE,
};
+static void armada_37xx_irq_ack(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 reg = IRQ_STATUS;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(&reg, d);
+ spin_lock_irqsave(&info->irq_lock, flags);
+ writel(d->mask, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+}
+
+static void armada_37xx_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(&reg, d);
+ spin_lock_irqsave(&info->irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val & ~d->mask, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+}
+
+static void armada_37xx_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_EN;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(&reg, d);
+ spin_lock_irqsave(&info->irq_lock, flags);
+ val = readl(info->base + reg);
+ writel(val | d->mask, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+}
+
+static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_WKUP;
+ unsigned long flags;
+
+ armada_37xx_irq_update_reg(&reg, d);
+ spin_lock_irqsave(&info->irq_lock, flags);
+ val = readl(info->base + reg);
+ if (on)
+ val |= d->mask;
+ else
+ val &= ~d->mask;
+ writel(val, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+
+ return 0;
+}
+
+static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
+ u32 val, reg = IRQ_POL;
+ unsigned long flags;
+
+ spin_lock_irqsave(&info->irq_lock, flags);
+ armada_37xx_irq_update_reg(&reg, d);
+ val = readl(info->base + reg);
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ val &= ~d->mask;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ val |= d->mask;
+ break;
+ default:
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+ return -EINVAL;
+ }
+ writel(val, info->base + reg);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+
+ return 0;
+}
+
+
+static void armada_37xx_irq_handler(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
+ struct irq_domain *d = gc->irqdomain;
+ int i;
+
+ chained_irq_enter(chip, desc);
+ for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
+ u32 status;
+ unsigned long flags;
+
+ spin_lock_irqsave(&info->irq_lock, flags);
+ status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
+ /* Manage only the interrupt that was enabled */
+ status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+ while (status) {
+ u32 hwirq = ffs(status) - 1;
+ u32 virq = irq_find_mapping(d, hwirq +
+ i * GPIO_PER_REG);
+
+ generic_handle_irq(virq);
+
+ /* Update status in case a new IRQ appears */
+ spin_lock_irqsave(&info->irq_lock, flags);
+ status = readl_relaxed(info->base +
+ IRQ_STATUS + 4 * i);
+ /* Manage only the interrupt that was enabled */
+ status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
+ spin_unlock_irqrestore(&info->irq_lock, flags);
+ }
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static int armada_37xx_irqchip_register(struct platform_device *pdev,
+ struct armada_37xx_pinctrl *info)
+{
+ struct device_node *np = info->dev->of_node;
+ int nrirqs = info->data->nr_pins;
+ struct gpio_chip *gc = &info->gpio_chip;
+ struct irq_chip *irqchip = &info->irq_chip;
+ struct resource res;
+ int ret = -ENODEV, i, nr_irq_parent;
+
+ /* Check if we have at least one gpio-controller child node */
+ for_each_child_of_node(info->dev->of_node, np) {
+ if (of_property_read_bool(np, "gpio-controller")) {
+ ret = 0;
+ break;
+ }
+ };
+ if (ret)
+ return ret;
+
+ nr_irq_parent = of_irq_count(np);
+ spin_lock_init(&info->irq_lock);
+
+ if (!nr_irq_parent) {
+ dev_err(&pdev->dev, "Invalid or no IRQ\n");
+ return 0;
+ }
+
+ if (of_address_to_resource(info->dev->of_node, 1, &res)) {
+ dev_err(info->dev, "cannot find IO resource\n");
+ return -ENOENT;
+ }
+
+ info->base = devm_ioremap_resource(info->dev, &res);
+ if (IS_ERR(info->base))
+ return PTR_ERR(info->base);
+
+ irqchip->irq_ack = armada_37xx_irq_ack;
+ irqchip->irq_mask = armada_37xx_irq_mask;
+ irqchip->irq_unmask = armada_37xx_irq_unmask;
+ irqchip->irq_set_wake = armada_37xx_irq_set_wake;
+ irqchip->irq_set_type = armada_37xx_irq_set_type;
+ irqchip->name = info->data->name;
+
+ ret = gpiochip_irqchip_add(gc, irqchip, 0,
+ handle_edge_irq, IRQ_TYPE_NONE);
+ if (ret) {
+ dev_info(&pdev->dev, "could not add irqchip\n");
+ return ret;
+ }
+
+ /*
+ * Many interrupts are connected to the parent interrupt
+ * controller. But we do not take advantage of this and use
+ * the chained irq with all of them.
+ */
+ for (i = 0; i < nrirqs; i++) {
+ struct irq_data *d = irq_get_irq_data(gc->irq_base + i);
+
+ /*
+ * The mask field is a "precomputed bitmask for
+ * accessing the chip registers" which was introduced
+ * for the generic irqchip framework. As we don't use
+ * this framework, we can reuse this field for our own
+ * usage.
+ */
+ d->mask = BIT(i % GPIO_PER_REG);
+ }
+
+ for (i = 0; i < nr_irq_parent; i++) {
+ int irq = irq_of_parse_and_map(np, i);
+
+ if (irq < 0)
+ continue;
+
+ gpiochip_set_chained_irqchip(gc, irqchip, irq,
+ armada_37xx_irq_handler);
+ }
+
+ return 0;
+}
+
static int armada_37xx_gpiochip_register(struct platform_device *pdev,
struct armada_37xx_pinctrl *info)
{
@@ -496,6 +723,9 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev,
ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
if (ret)
return ret;
+ ret = armada_37xx_irqchip_register(pdev, info);
+ if (ret)
+ return ret;
return 0;
}
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
new file mode 100644
index 000000000000..66e442260a4e
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c
@@ -0,0 +1,140 @@
+/*
+ * Marvell Armada ap806 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Hanna Hawa <hannah@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode armada_ap806_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "clk"),
+ MPP_FUNCTION(3, "spi0", "clk")),
+ MPP_MODE(1,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "cmd"),
+ MPP_FUNCTION(3, "spi0", "miso")),
+ MPP_MODE(2,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "d0"),
+ MPP_FUNCTION(3, "spi0", "mosi")),
+ MPP_MODE(3,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "d1"),
+ MPP_FUNCTION(3, "spi0", "cs0n")),
+ MPP_MODE(4,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "d2"),
+ MPP_FUNCTION(3, "i2c0", "sda")),
+ MPP_MODE(5,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "d3"),
+ MPP_FUNCTION(3, "i2c0", "sdk")),
+ MPP_MODE(6,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "ds")),
+ MPP_MODE(7,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "d4"),
+ MPP_FUNCTION(3, "uart1", "rxd")),
+ MPP_MODE(8,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "d5"),
+ MPP_FUNCTION(3, "uart1", "txd")),
+ MPP_MODE(9,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "d6"),
+ MPP_FUNCTION(3, "spi0", "cs1n")),
+ MPP_MODE(10,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "d7")),
+ MPP_MODE(11,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(3, "uart0", "txd")),
+ MPP_MODE(12,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "pw_off"),
+ MPP_FUNCTION(2, "sdio", "hw_rst")),
+ MPP_MODE(13,
+ MPP_FUNCTION(0, "gpio", NULL)),
+ MPP_MODE(14,
+ MPP_FUNCTION(0, "gpio", NULL)),
+ MPP_MODE(15,
+ MPP_FUNCTION(0, "gpio", NULL)),
+ MPP_MODE(16,
+ MPP_FUNCTION(0, "gpio", NULL)),
+ MPP_MODE(17,
+ MPP_FUNCTION(0, "gpio", NULL)),
+ MPP_MODE(18,
+ MPP_FUNCTION(0, "gpio", NULL)),
+ MPP_MODE(19,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(3, "uart0", "rxd"),
+ MPP_FUNCTION(4, "sdio", "pw_off")),
+};
+
+static struct mvebu_pinctrl_soc_info armada_ap806_pinctrl_info;
+
+static const struct of_device_id armada_ap806_pinctrl_of_match[] = {
+ {
+ .compatible = "marvell,ap806-pinctrl",
+ },
+ { },
+};
+
+static const struct mvebu_mpp_ctrl armada_ap806_mpp_controls[] = {
+ MPP_FUNC_CTRL(0, 19, NULL, mvebu_regmap_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range armada_ap806_mpp_gpio_ranges[] = {
+ MPP_GPIO_RANGE(0, 0, 0, 20),
+};
+
+static int armada_ap806_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc = &armada_ap806_pinctrl_info;
+ const struct of_device_id *match =
+ of_match_device(armada_ap806_pinctrl_of_match, &pdev->dev);
+
+ if (!match || !pdev->dev.parent)
+ return -ENODEV;
+
+ soc->variant = 0; /* no variants for Armada AP806 */
+ soc->controls = armada_ap806_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(armada_ap806_mpp_controls);
+ soc->gpioranges = armada_ap806_mpp_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(armada_ap806_mpp_gpio_ranges);
+ soc->modes = armada_ap806_mpp_modes;
+ soc->nmodes = armada_ap806_mpp_controls[0].npins;
+
+ pdev->dev.platform_data = soc;
+
+ return mvebu_pinctrl_simple_regmap_probe(pdev, pdev->dev.parent, 0);
+}
+
+static struct platform_driver armada_ap806_pinctrl_driver = {
+ .driver = {
+ .name = "armada-ap806-pinctrl",
+ .of_match_table = of_match_ptr(armada_ap806_pinctrl_of_match),
+ },
+ .probe = armada_ap806_pinctrl_probe,
+};
+
+builtin_platform_driver(armada_ap806_pinctrl_driver);
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
new file mode 100644
index 000000000000..7f85beb45482
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
@@ -0,0 +1,687 @@
+/*
+ * Marvell Armada CP110 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2017 Marvell
+ *
+ * Hanna Hawa <hannah@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-mvebu.h"
+
+/*
+ * Even if the pin controller is the same the MMP available depend on the SoC
+ * integration.
+ * - In Armada7K (single CP) almost all the MPPs are available (except the
+ * MMP 39 to 43)
+ * - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
+ * CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
+ * V_ARMADA_8K_CPS) set which MPP is available to the CPx.
+ * The x_PLUS enum mean that the MPP available for CPx and for Armada70x0
+ */
+enum {
+ V_ARMADA_7K = BIT(0),
+ V_ARMADA_8K_CPM = BIT(1),
+ V_ARMADA_8K_CPS = BIT(2),
+ V_ARMADA_7K_8K_CPM = (V_ARMADA_7K | V_ARMADA_8K_CPM),
+ V_ARMADA_7K_8K_CPS = (V_ARMADA_7K | V_ARMADA_8K_CPS),
+};
+
+static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ale1"),
+ MPP_FUNCTION(2, "au", "i2smclk"),
+ MPP_FUNCTION(3, "ge0", "rxd3"),
+ MPP_FUNCTION(4, "tdm", "pclk"),
+ MPP_FUNCTION(6, "ptp", "pulse"),
+ MPP_FUNCTION(7, "mss_i2c", "sda"),
+ MPP_FUNCTION(8, "uart0", "rxd"),
+ MPP_FUNCTION(9, "sata0", "present_act"),
+ MPP_FUNCTION(10, "ge", "mdio")),
+ MPP_MODE(1,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ale0"),
+ MPP_FUNCTION(2, "au", "i2sdo_spdifo"),
+ MPP_FUNCTION(3, "ge0", "rxd2"),
+ MPP_FUNCTION(4, "tdm", "drx"),
+ MPP_FUNCTION(6, "ptp", "clk"),
+ MPP_FUNCTION(7, "mss_i2c", "sck"),
+ MPP_FUNCTION(8, "uart0", "txd"),
+ MPP_FUNCTION(9, "sata1", "present_act"),
+ MPP_FUNCTION(10, "ge", "mdc")),
+ MPP_MODE(2,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad15"),
+ MPP_FUNCTION(2, "au", "i2sextclk"),
+ MPP_FUNCTION(3, "ge0", "rxd1"),
+ MPP_FUNCTION(4, "tdm", "dtx"),
+ MPP_FUNCTION(5, "mss_uart", "rxd"),
+ MPP_FUNCTION(6, "ptp", "pclk_out"),
+ MPP_FUNCTION(7, "i2c1", "sck"),
+ MPP_FUNCTION(8, "uart1", "rxd"),
+ MPP_FUNCTION(9, "sata0", "present_act"),
+ MPP_FUNCTION(10, "xg", "mdc")),
+ MPP_MODE(3,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad14"),
+ MPP_FUNCTION(2, "au", "i2slrclk"),
+ MPP_FUNCTION(3, "ge0", "rxd0"),
+ MPP_FUNCTION(4, "tdm", "fsync"),
+ MPP_FUNCTION(5, "mss_uart", "txd"),
+ MPP_FUNCTION(6, "pcie", "rstoutn"),
+ MPP_FUNCTION(7, "i2c1", "sda"),
+ MPP_FUNCTION(8, "uart1", "txd"),
+ MPP_FUNCTION(9, "sata1", "present_act"),
+ MPP_FUNCTION(10, "xg", "mdio")),
+ MPP_MODE(4,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad13"),
+ MPP_FUNCTION(2, "au", "i2sbclk"),
+ MPP_FUNCTION(3, "ge0", "rxctl"),
+ MPP_FUNCTION(4, "tdm", "rstn"),
+ MPP_FUNCTION(5, "mss_uart", "rxd"),
+ MPP_FUNCTION(6, "uart1", "cts"),
+ MPP_FUNCTION(7, "pcie0", "clkreq"),
+ MPP_FUNCTION(8, "uart3", "rxd"),
+ MPP_FUNCTION(10, "ge", "mdc")),
+ MPP_MODE(5,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad12"),
+ MPP_FUNCTION(2, "au", "i2sdi"),
+ MPP_FUNCTION(3, "ge0", "rxclk"),
+ MPP_FUNCTION(4, "tdm", "intn"),
+ MPP_FUNCTION(5, "mss_uart", "txd"),
+ MPP_FUNCTION(6, "uart1", "rts"),
+ MPP_FUNCTION(7, "pcie1", "clkreq"),
+ MPP_FUNCTION(8, "uart3", "txd"),
+ MPP_FUNCTION(10, "ge", "mdio")),
+ MPP_MODE(6,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad11"),
+ MPP_FUNCTION(3, "ge0", "txd3"),
+ MPP_FUNCTION(4, "spi0", "csn2"),
+ MPP_FUNCTION(5, "au", "i2sextclk"),
+ MPP_FUNCTION(6, "sata1", "present_act"),
+ MPP_FUNCTION(7, "pcie2", "clkreq"),
+ MPP_FUNCTION(8, "uart0", "rxd"),
+ MPP_FUNCTION(9, "ptp", "pulse")),
+ MPP_MODE(7,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad10"),
+ MPP_FUNCTION(3, "ge0", "txd2"),
+ MPP_FUNCTION(4, "spi0", "csn1"),
+ MPP_FUNCTION(5, "spi1", "csn1"),
+ MPP_FUNCTION(6, "sata0", "present_act"),
+ MPP_FUNCTION(7, "led", "data"),
+ MPP_FUNCTION(8, "uart0", "txd"),
+ MPP_FUNCTION(9, "ptp", "clk")),
+ MPP_MODE(8,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad9"),
+ MPP_FUNCTION(3, "ge0", "txd1"),
+ MPP_FUNCTION(4, "spi0", "csn0"),
+ MPP_FUNCTION(5, "spi1", "csn0"),
+ MPP_FUNCTION(6, "uart0", "cts"),
+ MPP_FUNCTION(7, "led", "stb"),
+ MPP_FUNCTION(8, "uart2", "rxd"),
+ MPP_FUNCTION(9, "ptp", "pclk_out"),
+ MPP_FUNCTION(10, "synce1", "clk")),
+ MPP_MODE(9,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad8"),
+ MPP_FUNCTION(3, "ge0", "txd0"),
+ MPP_FUNCTION(4, "spi0", "mosi"),
+ MPP_FUNCTION(5, "spi1", "mosi"),
+ MPP_FUNCTION(7, "pcie", "rstoutn"),
+ MPP_FUNCTION(10, "synce2", "clk")),
+ MPP_MODE(10,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "readyn"),
+ MPP_FUNCTION(3, "ge0", "txctl"),
+ MPP_FUNCTION(4, "spi0", "miso"),
+ MPP_FUNCTION(5, "spi1", "miso"),
+ MPP_FUNCTION(6, "uart0", "cts"),
+ MPP_FUNCTION(7, "sata1", "present_act")),
+ MPP_MODE(11,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "wen1"),
+ MPP_FUNCTION(3, "ge0", "txclkout"),
+ MPP_FUNCTION(4, "spi0", "clk"),
+ MPP_FUNCTION(5, "spi1", "clk"),
+ MPP_FUNCTION(6, "uart0", "rts"),
+ MPP_FUNCTION(7, "led", "clk"),
+ MPP_FUNCTION(8, "uart2", "txd"),
+ MPP_FUNCTION(9, "sata0", "present_act")),
+ MPP_MODE(12,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "clk_out"),
+ MPP_FUNCTION(2, "nf", "rbn1"),
+ MPP_FUNCTION(3, "spi1", "csn1"),
+ MPP_FUNCTION(4, "ge0", "rxclk")),
+ MPP_MODE(13,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "burstn"),
+ MPP_FUNCTION(2, "nf", "rbn0"),
+ MPP_FUNCTION(3, "spi1", "miso"),
+ MPP_FUNCTION(4, "ge0", "rxctl"),
+ MPP_FUNCTION(8, "mss_spi", "miso")),
+ MPP_MODE(14,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "bootcsn"),
+ MPP_FUNCTION(2, "dev", "csn0"),
+ MPP_FUNCTION(3, "spi1", "csn0"),
+ MPP_FUNCTION(4, "spi0", "csn3"),
+ MPP_FUNCTION(5, "au", "i2sextclk"),
+ MPP_FUNCTION(6, "spi0", "miso"),
+ MPP_FUNCTION(7, "sata0", "present_act"),
+ MPP_FUNCTION(8, "mss_spi", "csn")),
+ MPP_MODE(15,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad7"),
+ MPP_FUNCTION(3, "spi1", "mosi"),
+ MPP_FUNCTION(6, "spi0", "mosi"),
+ MPP_FUNCTION(8, "mss_spi", "mosi"),
+ MPP_FUNCTION(11, "ptp", "pulse_cp2cp")),
+ MPP_MODE(16,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad6"),
+ MPP_FUNCTION(3, "spi1", "clk"),
+ MPP_FUNCTION(8, "mss_spi", "clk")),
+ MPP_MODE(17,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad5"),
+ MPP_FUNCTION(4, "ge0", "txd3")),
+ MPP_MODE(18,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad4"),
+ MPP_FUNCTION(4, "ge0", "txd2"),
+ MPP_FUNCTION(11, "ptp", "clk_cp2cp")),
+ MPP_MODE(19,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad3"),
+ MPP_FUNCTION(4, "ge0", "txd1"),
+ MPP_FUNCTION(11, "wakeup", "out_cp2cp")),
+ MPP_MODE(20,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad2"),
+ MPP_FUNCTION(4, "ge0", "txd0")),
+ MPP_MODE(21,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad1"),
+ MPP_FUNCTION(4, "ge0", "txctl"),
+ MPP_FUNCTION(11, "sei", "in_cp2cp")),
+ MPP_MODE(22,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "ad0"),
+ MPP_FUNCTION(4, "ge0", "txclkout"),
+ MPP_FUNCTION(11, "wakeup", "in_cp2cp")),
+ MPP_MODE(23,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "a1"),
+ MPP_FUNCTION(5, "au", "i2smclk"),
+ MPP_FUNCTION(11, "link", "rd_in_cp2cp")),
+ MPP_MODE(24,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "a0"),
+ MPP_FUNCTION(5, "au", "i2slrclk")),
+ MPP_MODE(25,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "oen"),
+ MPP_FUNCTION(5, "au", "i2sdo_spdifo")),
+ MPP_MODE(26,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "wen0"),
+ MPP_FUNCTION(5, "au", "i2sbclk")),
+ MPP_MODE(27,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "csn0"),
+ MPP_FUNCTION(2, "spi1", "miso"),
+ MPP_FUNCTION(3, "mss_gpio4", NULL),
+ MPP_FUNCTION(4, "ge0", "rxd3"),
+ MPP_FUNCTION(5, "spi0", "csn4"),
+ MPP_FUNCTION(8, "ge", "mdio"),
+ MPP_FUNCTION(9, "sata0", "present_act"),
+ MPP_FUNCTION(10, "uart0", "rts"),
+ MPP_FUNCTION(11, "rei", "in_cp2cp")),
+ MPP_MODE(28,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "csn1"),
+ MPP_FUNCTION(2, "spi1", "csn0"),
+ MPP_FUNCTION(3, "mss_gpio5", NULL),
+ MPP_FUNCTION(4, "ge0", "rxd2"),
+ MPP_FUNCTION(5, "spi0", "csn5"),
+ MPP_FUNCTION(6, "pcie2", "clkreq"),
+ MPP_FUNCTION(7, "ptp", "pulse"),
+ MPP_FUNCTION(8, "ge", "mdc"),
+ MPP_FUNCTION(9, "sata1", "present_act"),
+ MPP_FUNCTION(10, "uart0", "cts"),
+ MPP_FUNCTION(11, "led", "data")),
+ MPP_MODE(29,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "csn2"),
+ MPP_FUNCTION(2, "spi1", "mosi"),
+ MPP_FUNCTION(3, "mss_gpio6", NULL),
+ MPP_FUNCTION(4, "ge0", "rxd1"),
+ MPP_FUNCTION(5, "spi0", "csn6"),
+ MPP_FUNCTION(6, "pcie1", "clkreq"),
+ MPP_FUNCTION(7, "ptp", "clk"),
+ MPP_FUNCTION(8, "mss_i2c", "sda"),
+ MPP_FUNCTION(9, "sata0", "present_act"),
+ MPP_FUNCTION(10, "uart0", "rxd"),
+ MPP_FUNCTION(11, "led", "stb")),
+ MPP_MODE(30,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "csn3"),
+ MPP_FUNCTION(2, "spi1", "clk"),
+ MPP_FUNCTION(3, "mss_gpio7", NULL),
+ MPP_FUNCTION(4, "ge0", "rxd0"),
+ MPP_FUNCTION(5, "spi0", "csn7"),
+ MPP_FUNCTION(6, "pcie0", "clkreq"),
+ MPP_FUNCTION(7, "ptp", "pclk_out"),
+ MPP_FUNCTION(8, "mss_i2c", "sck"),
+ MPP_FUNCTION(9, "sata1", "present_act"),
+ MPP_FUNCTION(10, "uart0", "txd"),
+ MPP_FUNCTION(11, "led", "clk")),
+ MPP_MODE(31,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "dev", "a2"),
+ MPP_FUNCTION(3, "mss_gpio4", NULL),
+ MPP_FUNCTION(6, "pcie", "rstoutn"),
+ MPP_FUNCTION(8, "ge", "mdc")),
+ MPP_MODE(32,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "mii", "col"),
+ MPP_FUNCTION(2, "mii", "txerr"),
+ MPP_FUNCTION(3, "mss_spi", "miso"),
+ MPP_FUNCTION(4, "tdm", "drx"),
+ MPP_FUNCTION(5, "au", "i2sextclk"),
+ MPP_FUNCTION(6, "au", "i2sdi"),
+ MPP_FUNCTION(7, "ge", "mdio"),
+ MPP_FUNCTION(8, "sdio", "v18_en"),
+ MPP_FUNCTION(9, "pcie1", "clkreq"),
+ MPP_FUNCTION(10, "mss_gpio0", NULL)),
+ MPP_MODE(33,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "mii", "txclk"),
+ MPP_FUNCTION(2, "sdio", "pwr10"),
+ MPP_FUNCTION(3, "mss_spi", "csn"),
+ MPP_FUNCTION(4, "tdm", "fsync"),
+ MPP_FUNCTION(5, "au", "i2smclk"),
+ MPP_FUNCTION(6, "sdio", "bus_pwr"),
+ MPP_FUNCTION(8, "xg", "mdio"),
+ MPP_FUNCTION(9, "pcie2", "clkreq"),
+ MPP_FUNCTION(10, "mss_gpio1", NULL)),
+ MPP_MODE(34,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "mii", "rxerr"),
+ MPP_FUNCTION(2, "sdio", "pwr11"),
+ MPP_FUNCTION(3, "mss_spi", "mosi"),
+ MPP_FUNCTION(4, "tdm", "dtx"),
+ MPP_FUNCTION(5, "au", "i2slrclk"),
+ MPP_FUNCTION(6, "sdio", "wr_protect"),
+ MPP_FUNCTION(7, "ge", "mdc"),
+ MPP_FUNCTION(9, "pcie0", "clkreq"),
+ MPP_FUNCTION(10, "mss_gpio2", NULL)),
+ MPP_MODE(35,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sata1", "present_act"),
+ MPP_FUNCTION(2, "i2c1", "sda"),
+ MPP_FUNCTION(3, "mss_spi", "clk"),
+ MPP_FUNCTION(4, "tdm", "pclk"),
+ MPP_FUNCTION(5, "au", "i2sdo_spdifo"),
+ MPP_FUNCTION(6, "sdio", "card_detect"),
+ MPP_FUNCTION(7, "xg", "mdio"),
+ MPP_FUNCTION(8, "ge", "mdio"),
+ MPP_FUNCTION(9, "pcie", "rstoutn"),
+ MPP_FUNCTION(10, "mss_gpio3", NULL)),
+ MPP_MODE(36,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "synce2", "clk"),
+ MPP_FUNCTION(2, "i2c1", "sck"),
+ MPP_FUNCTION(3, "ptp", "clk"),
+ MPP_FUNCTION(4, "synce1", "clk"),
+ MPP_FUNCTION(5, "au", "i2sbclk"),
+ MPP_FUNCTION(6, "sata0", "present_act"),
+ MPP_FUNCTION(7, "xg", "mdc"),
+ MPP_FUNCTION(8, "ge", "mdc"),
+ MPP_FUNCTION(9, "pcie2", "clkreq"),
+ MPP_FUNCTION(10, "mss_gpio5", NULL)),
+ MPP_MODE(37,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "uart2", "rxd"),
+ MPP_FUNCTION(2, "i2c0", "sck"),
+ MPP_FUNCTION(3, "ptp", "pclk_out"),
+ MPP_FUNCTION(4, "tdm", "intn"),
+ MPP_FUNCTION(5, "mss_i2c", "sck"),
+ MPP_FUNCTION(6, "sata1", "present_act"),
+ MPP_FUNCTION(7, "ge", "mdc"),
+ MPP_FUNCTION(8, "xg", "mdc"),
+ MPP_FUNCTION(9, "pcie1", "clkreq"),
+ MPP_FUNCTION(10, "mss_gpio6", NULL),
+ MPP_FUNCTION(11, "link", "rd_out_cp2cp")),
+ MPP_MODE(38,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "uart2", "txd"),
+ MPP_FUNCTION(2, "i2c0", "sda"),
+ MPP_FUNCTION(3, "ptp", "pulse"),
+ MPP_FUNCTION(4, "tdm", "rstn"),
+ MPP_FUNCTION(5, "mss_i2c", "sda"),
+ MPP_FUNCTION(6, "sata0", "present_act"),
+ MPP_FUNCTION(7, "ge", "mdio"),
+ MPP_FUNCTION(8, "xg", "mdio"),
+ MPP_FUNCTION(9, "au", "i2sextclk"),
+ MPP_FUNCTION(10, "mss_gpio7", NULL),
+ MPP_FUNCTION(11, "ptp", "pulse_cp2cp")),
+ MPP_MODE(39,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "wr_protect"),
+ MPP_FUNCTION(4, "au", "i2sbclk"),
+ MPP_FUNCTION(5, "ptp", "clk"),
+ MPP_FUNCTION(6, "spi0", "csn1"),
+ MPP_FUNCTION(9, "sata1", "present_act"),
+ MPP_FUNCTION(10, "mss_gpio0", NULL)),
+ MPP_MODE(40,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "pwr11"),
+ MPP_FUNCTION(2, "synce1", "clk"),
+ MPP_FUNCTION(3, "mss_i2c", "sda"),
+ MPP_FUNCTION(4, "au", "i2sdo_spdifo"),
+ MPP_FUNCTION(5, "ptp", "pclk_out"),
+ MPP_FUNCTION(6, "spi0", "clk"),
+ MPP_FUNCTION(7, "uart1", "txd"),
+ MPP_FUNCTION(8, "ge", "mdio"),
+ MPP_FUNCTION(9, "sata0", "present_act"),
+ MPP_FUNCTION(10, "mss_gpio1", NULL)),
+ MPP_MODE(41,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "pwr10"),
+ MPP_FUNCTION(2, "sdio", "bus_pwr"),
+ MPP_FUNCTION(3, "mss_i2c", "sck"),
+ MPP_FUNCTION(4, "au", "i2slrclk"),
+ MPP_FUNCTION(5, "ptp", "pulse"),
+ MPP_FUNCTION(6, "spi0", "mosi"),
+ MPP_FUNCTION(7, "uart1", "rxd"),
+ MPP_FUNCTION(8, "ge", "mdc"),
+ MPP_FUNCTION(9, "sata1", "present_act"),
+ MPP_FUNCTION(10, "mss_gpio2", NULL),
+ MPP_FUNCTION(11, "rei", "out_cp2cp")),
+ MPP_MODE(42,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "v18_en"),
+ MPP_FUNCTION(2, "sdio", "wr_protect"),
+ MPP_FUNCTION(3, "synce2", "clk"),
+ MPP_FUNCTION(4, "au", "i2smclk"),
+ MPP_FUNCTION(5, "mss_uart", "txd"),
+ MPP_FUNCTION(6, "spi0", "miso"),
+ MPP_FUNCTION(7, "uart1", "cts"),
+ MPP_FUNCTION(8, "xg", "mdc"),
+ MPP_FUNCTION(9, "sata0", "present_act"),
+ MPP_FUNCTION(10, "mss_gpio4", NULL)),
+ MPP_MODE(43,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "sdio", "card_detect"),
+ MPP_FUNCTION(3, "synce1", "clk"),
+ MPP_FUNCTION(4, "au", "i2sextclk"),
+ MPP_FUNCTION(5, "mss_uart", "rxd"),
+ MPP_FUNCTION(6, "spi0", "csn0"),
+ MPP_FUNCTION(7, "uart1", "rts"),
+ MPP_FUNCTION(8, "xg", "mdio"),
+ MPP_FUNCTION(9, "sata1", "present_act"),
+ MPP_FUNCTION(10, "mss_gpio5", NULL),
+ MPP_FUNCTION(11, "wakeup", "out_cp2cp")),
+ MPP_MODE(44,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "txd2"),
+ MPP_FUNCTION(7, "uart0", "rts"),
+ MPP_FUNCTION(11, "ptp", "clk_cp2cp")),
+ MPP_MODE(45,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "txd3"),
+ MPP_FUNCTION(7, "uart0", "txd"),
+ MPP_FUNCTION(9, "pcie", "rstoutn")),
+ MPP_MODE(46,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "txd1"),
+ MPP_FUNCTION(7, "uart1", "rts")),
+ MPP_MODE(47,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "txd0"),
+ MPP_FUNCTION(5, "spi1", "clk"),
+ MPP_FUNCTION(7, "uart1", "txd"),
+ MPP_FUNCTION(8, "ge", "mdc")),
+ MPP_MODE(48,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "txctl_txen"),
+ MPP_FUNCTION(5, "spi1", "mosi"),
+ MPP_FUNCTION(8, "xg", "mdc"),
+ MPP_FUNCTION(11, "wakeup", "in_cp2cp")),
+ MPP_MODE(49,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "txclkout"),
+ MPP_FUNCTION(2, "mii", "crs"),
+ MPP_FUNCTION(5, "spi1", "miso"),
+ MPP_FUNCTION(7, "uart1", "rxd"),
+ MPP_FUNCTION(8, "ge", "mdio"),
+ MPP_FUNCTION(9, "pcie0", "clkreq"),
+ MPP_FUNCTION(10, "sdio", "v18_en"),
+ MPP_FUNCTION(11, "sei", "out_cp2cp")),
+ MPP_MODE(50,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "rxclk"),
+ MPP_FUNCTION(2, "mss_i2c", "sda"),
+ MPP_FUNCTION(5, "spi1", "csn0"),
+ MPP_FUNCTION(6, "uart2", "txd"),
+ MPP_FUNCTION(7, "uart0", "rxd"),
+ MPP_FUNCTION(8, "xg", "mdio"),
+ MPP_FUNCTION(10, "sdio", "pwr11")),
+ MPP_MODE(51,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "rxd0"),
+ MPP_FUNCTION(2, "mss_i2c", "sck"),
+ MPP_FUNCTION(5, "spi1", "csn1"),
+ MPP_FUNCTION(6, "uart2", "rxd"),
+ MPP_FUNCTION(7, "uart0", "cts"),
+ MPP_FUNCTION(10, "sdio", "pwr10")),
+ MPP_MODE(52,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "rxd1"),
+ MPP_FUNCTION(2, "synce1", "clk"),
+ MPP_FUNCTION(4, "synce2", "clk"),
+ MPP_FUNCTION(5, "spi1", "csn2"),
+ MPP_FUNCTION(7, "uart1", "cts"),
+ MPP_FUNCTION(8, "led", "clk"),
+ MPP_FUNCTION(9, "pcie", "rstoutn"),
+ MPP_FUNCTION(10, "pcie0", "clkreq")),
+ MPP_MODE(53,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "rxd2"),
+ MPP_FUNCTION(3, "ptp", "clk"),
+ MPP_FUNCTION(5, "spi1", "csn3"),
+ MPP_FUNCTION(7, "uart1", "rxd"),
+ MPP_FUNCTION(8, "led", "stb"),
+ MPP_FUNCTION(11, "sdio", "led")),
+ MPP_MODE(54,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "rxd3"),
+ MPP_FUNCTION(2, "synce2", "clk"),
+ MPP_FUNCTION(3, "ptp", "pclk_out"),
+ MPP_FUNCTION(4, "synce1", "clk"),
+ MPP_FUNCTION(8, "led", "data"),
+ MPP_FUNCTION(10, "sdio", "hw_rst"),
+ MPP_FUNCTION(11, "sdio", "wr_protect")),
+ MPP_MODE(55,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "ge1", "rxctl_rxdv"),
+ MPP_FUNCTION(3, "ptp", "pulse"),
+ MPP_FUNCTION(10, "sdio", "led"),
+ MPP_FUNCTION(11, "sdio", "card_detect")),
+ MPP_MODE(56,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(4, "tdm", "drx"),
+ MPP_FUNCTION(5, "au", "i2sdo_spdifo"),
+ MPP_FUNCTION(6, "spi0", "clk"),
+ MPP_FUNCTION(7, "uart1", "rxd"),
+ MPP_FUNCTION(9, "sata1", "present_act"),
+ MPP_FUNCTION(14, "sdio", "clk")),
+ MPP_MODE(57,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(2, "mss_i2c", "sda"),
+ MPP_FUNCTION(3, "ptp", "pclk_out"),
+ MPP_FUNCTION(4, "tdm", "intn"),
+ MPP_FUNCTION(5, "au", "i2sbclk"),
+ MPP_FUNCTION(6, "spi0", "mosi"),
+ MPP_FUNCTION(7, "uart1", "txd"),
+ MPP_FUNCTION(9, "sata0", "present_act"),
+ MPP_FUNCTION(14, "sdio", "cmd")),
+ MPP_MODE(58,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(2, "mss_i2c", "sck"),
+ MPP_FUNCTION(3, "ptp", "clk"),
+ MPP_FUNCTION(4, "tdm", "rstn"),
+ MPP_FUNCTION(5, "au", "i2sdi"),
+ MPP_FUNCTION(6, "spi0", "miso"),
+ MPP_FUNCTION(7, "uart1", "cts"),
+ MPP_FUNCTION(8, "led", "clk"),
+ MPP_FUNCTION(14, "sdio", "d0")),
+ MPP_MODE(59,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "mss_gpio7", NULL),
+ MPP_FUNCTION(2, "synce2", "clk"),
+ MPP_FUNCTION(4, "tdm", "fsync"),
+ MPP_FUNCTION(5, "au", "i2slrclk"),
+ MPP_FUNCTION(6, "spi0", "csn0"),
+ MPP_FUNCTION(7, "uart0", "cts"),
+ MPP_FUNCTION(8, "led", "stb"),
+ MPP_FUNCTION(9, "uart1", "txd"),
+ MPP_FUNCTION(14, "sdio", "d1")),
+ MPP_MODE(60,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "mss_gpio6", NULL),
+ MPP_FUNCTION(3, "ptp", "pulse"),
+ MPP_FUNCTION(4, "tdm", "dtx"),
+ MPP_FUNCTION(5, "au", "i2smclk"),
+ MPP_FUNCTION(6, "spi0", "csn1"),
+ MPP_FUNCTION(7, "uart0", "rts"),
+ MPP_FUNCTION(8, "led", "data"),
+ MPP_FUNCTION(9, "uart1", "rxd"),
+ MPP_FUNCTION(14, "sdio", "d2")),
+ MPP_MODE(61,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "mss_gpio5", NULL),
+ MPP_FUNCTION(3, "ptp", "clk"),
+ MPP_FUNCTION(4, "tdm", "pclk"),
+ MPP_FUNCTION(5, "au", "i2sextclk"),
+ MPP_FUNCTION(6, "spi0", "csn2"),
+ MPP_FUNCTION(7, "uart0", "txd"),
+ MPP_FUNCTION(8, "uart2", "txd"),
+ MPP_FUNCTION(9, "sata1", "present_act"),
+ MPP_FUNCTION(10, "ge", "mdio"),
+ MPP_FUNCTION(14, "sdio", "d3")),
+ MPP_MODE(62,
+ MPP_FUNCTION(0, "gpio", NULL),
+ MPP_FUNCTION(1, "mss_gpio4", NULL),
+ MPP_FUNCTION(2, "synce1", "clk"),
+ MPP_FUNCTION(3, "ptp", "pclk_out"),
+ MPP_FUNCTION(5, "sata1", "present_act"),
+ MPP_FUNCTION(6, "spi0", "csn3"),
+ MPP_FUNCTION(7, "uart0", "rxd"),
+ MPP_FUNCTION(8, "uart2", "rxd"),
+ MPP_FUNCTION(9, "sata0", "present_act"),
+ MPP_FUNCTION(10, "ge", "mdc")),
+};
+
+static const struct of_device_id armada_cp110_pinctrl_of_match[] = {
+ {
+ .compatible = "marvell,armada-7k-pinctrl",
+ .data = (void *) V_ARMADA_7K,
+ },
+ {
+ .compatible = "marvell,armada-8k-cpm-pinctrl",
+ .data = (void *) V_ARMADA_8K_CPM,
+ },
+ {
+ .compatible = "marvell,armada-8k-cps-pinctrl",
+ .data = (void *) V_ARMADA_8K_CPS,
+ },
+ { },
+};
+
+static const struct mvebu_mpp_ctrl armada_cp110_mpp_controls[] = {
+ MPP_FUNC_CTRL(0, 62, NULL, mvebu_regmap_mpp_ctrl),
+};
+
+static void mvebu_pinctrl_assign_variant(struct mvebu_mpp_mode *m,
+ u8 variant)
+{
+ struct mvebu_mpp_ctrl_setting *s;
+
+ for (s = m->settings ; s->name ; s++)
+ s->variant = variant;
+}
+
+static int armada_cp110_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mvebu_pinctrl_soc_info *soc;
+ const struct of_device_id *match =
+ of_match_device(armada_cp110_pinctrl_of_match, &pdev->dev);
+ int i;
+
+ if (!pdev->dev.parent)
+ return -ENODEV;
+
+ soc = devm_kzalloc(&pdev->dev,
+ sizeof(struct mvebu_pinctrl_soc_info), GFP_KERNEL);
+ if (!soc)
+ return -ENOMEM;
+
+ soc->variant = (unsigned long) match->data & 0xff;
+ soc->controls = armada_cp110_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(armada_cp110_mpp_controls);
+ soc->modes = armada_cp110_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(armada_cp110_mpp_modes);
+ for (i = 0; i < ARRAY_SIZE(armada_cp110_mpp_modes); i++) {
+ struct mvebu_mpp_mode *m = &armada_cp110_mpp_modes[i];
+
+ switch (i) {
+ case 0 ... 31:
+ mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPS);
+ break;
+ case 32 ... 38:
+ mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM);
+ break;
+ case 39 ... 43:
+ mvebu_pinctrl_assign_variant(m, V_ARMADA_8K_CPM);
+ break;
+ case 44 ... 62:
+ mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM);
+ break;
+ }
+ }
+ pdev->dev.platform_data = soc;
+
+ return mvebu_pinctrl_simple_regmap_probe(pdev, pdev->dev.parent, 0);
+}
+
+static struct platform_driver armada_cp110_pinctrl_driver = {
+ .driver = {
+ .name = "armada-cp110-pinctrl",
+ .of_match_table = of_match_ptr(armada_cp110_pinctrl_of_match),
+ },
+ .probe = armada_cp110_pinctrl_probe,
+};
+
+builtin_platform_driver(armada_cp110_pinctrl_driver);
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index e4dda12d371a..163d4614b0f8 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -810,21 +810,17 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
}
int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
- struct device *syscon_dev)
+ struct device *syscon_dev, u32 offset)
{
struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
struct mvebu_mpp_ctrl_data *mpp_data;
struct regmap *regmap;
- u32 offset;
int i;
regmap = syscon_node_to_regmap(syscon_dev->of_node);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- if (of_property_read_u32(pdev->dev.of_node, "offset", &offset))
- return -EINVAL;
-
mpp_data = devm_kcalloc(&pdev->dev, soc->ncontrols, sizeof(*mpp_data),
GFP_KERNEL);
if (!mpp_data)
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
index c90704e74884..75bba436bf59 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.h
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
@@ -210,6 +210,6 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
int mvebu_pinctrl_probe(struct platform_device *pdev);
int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev);
int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev,
- struct device *syscon_dev);
+ struct device *syscon_dev, u32 offset);
#endif
generated by cgit (git 2.34.1) at 2025-05-12 23:04:57 +0000