diff options
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed.c | 13 | ||||
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-intel.c | 16 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt8195.c | 4 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl-amd.c | 1 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl-single.c | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/Kconfig | 5 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/Makefile | 1 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 653 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-samsung.c | 10 |
10 files changed, 30 insertions, 677 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 3945612900e6..9c6ee46ac7a0 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -93,10 +93,19 @@ static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx, static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx, const struct aspeed_sig_expr *expr) { + int ret; + pr_debug("Disabling signal %s for %s\n", expr->signal, expr->function); - return aspeed_sig_expr_set(ctx, expr, false); + ret = aspeed_sig_expr_eval(ctx, expr, true); + if (ret < 0) + return ret; + + if (ret) + return aspeed_sig_expr_set(ctx, expr, false); + + return 0; } /** @@ -114,7 +123,7 @@ static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx, int ret = 0; if (!exprs) - return true; + return -EINVAL; while (*exprs && !ret) { ret = aspeed_sig_expr_disable(ctx, *exprs); diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index cc3aaba24188..e49f271de936 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1709,6 +1709,12 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_ EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); #ifdef CONFIG_PM_SLEEP +static bool __intel_gpio_is_direct_irq(u32 value) +{ + return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && + (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO); +} + static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) { const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin); @@ -1742,8 +1748,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int * See https://bugzilla.kernel.org/show_bug.cgi?id=214749. */ value = readl(intel_get_padcfg(pctrl, pin, PADCFG0)); - if ((value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) && - (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO)) + if (__intel_gpio_is_direct_irq(value)) return true; return false; @@ -1873,7 +1878,12 @@ int intel_pinctrl_resume_noirq(struct device *dev) for (i = 0; i < pctrl->soc->npins; i++) { const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i]; - if (!intel_pinctrl_should_save(pctrl, desc->number)) + if (!(intel_pinctrl_should_save(pctrl, desc->number) || + /* + * If the firmware mangled the register contents too much, + * check the saved value for the Direct IRQ mode. + */ + __intel_gpio_is_direct_irq(pads[i].padcfg0))) continue; intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index 89557c7ed2ab..09c4dcef9338 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -659,7 +659,7 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = { PIN_FIELD_BASE(10, 10, 4, 0x010, 0x10, 9, 3), PIN_FIELD_BASE(11, 11, 4, 0x000, 0x10, 24, 3), PIN_FIELD_BASE(12, 12, 4, 0x010, 0x10, 12, 3), - PIN_FIELD_BASE(13, 13, 4, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(13, 13, 4, 0x000, 0x10, 27, 3), PIN_FIELD_BASE(14, 14, 4, 0x010, 0x10, 15, 3), PIN_FIELD_BASE(15, 15, 4, 0x010, 0x10, 0, 3), PIN_FIELD_BASE(16, 16, 4, 0x010, 0x10, 18, 3), @@ -708,7 +708,7 @@ static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = { PIN_FIELD_BASE(78, 78, 3, 0x000, 0x10, 15, 3), PIN_FIELD_BASE(79, 79, 3, 0x000, 0x10, 18, 3), PIN_FIELD_BASE(80, 80, 3, 0x000, 0x10, 21, 3), - PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 28, 3), + PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 24, 3), PIN_FIELD_BASE(82, 82, 3, 0x000, 0x10, 27, 3), PIN_FIELD_BASE(83, 83, 3, 0x010, 0x10, 0, 3), PIN_FIELD_BASE(84, 84, 3, 0x010, 0x10, 3, 3), diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 9bc6e3922e78..32c3edaf9038 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -365,6 +365,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) } else { debounce_enable = " ∅"; + time = 0; } snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit); seq_printf(s, "debounce %s (🕑 %sus)| ", debounce_enable, debounce_value); diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 99c3745da456..190923757cda 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -372,6 +372,8 @@ static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, if (!pcs->fmask) return 0; function = pinmux_generic_get_function(pctldev, fselector); + if (!function) + return -EINVAL; func = function->data; if (!func) return -EINVAL; diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c index c3c8c34148f1..e22d03ce292e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -105,7 +105,7 @@ static const struct pinctrl_pin_desc sm8450_lpi_pins[] = { static const char * const swr_tx_clk_groups[] = { "gpio0" }; static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; static const char * const swr_rx_clk_groups[] = { "gpio3" }; -static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5", "gpio15" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; static const char * const dmic1_clk_groups[] = { "gpio6" }; static const char * const dmic1_data_groups[] = { "gpio7" }; static const char * const dmic2_clk_groups[] = { "gpio8" }; diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig index 7b0576f71376..697ff7812d8e 100644 --- a/drivers/pinctrl/samsung/Kconfig +++ b/drivers/pinctrl/samsung/Kconfig @@ -23,11 +23,6 @@ config PINCTRL_EXYNOS_ARM64 bool "ARMv8-specific pinctrl driver for Samsung Exynos SoCs" if COMPILE_TEST depends on PINCTRL_EXYNOS -config PINCTRL_S3C24XX - bool "Samsung S3C24XX SoC pinctrl driver" - depends on ARCH_S3C24XX || (COMPILE_TEST && OF) - select PINCTRL_SAMSUNG - config PINCTRL_S3C64XX bool "Samsung S3C64XX SoC pinctrl driver" depends on ARCH_S3C64XX || (COMPILE_TEST && OF) diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile index ed951df6a112..4dd4a92ab6cc 100644 --- a/drivers/pinctrl/samsung/Makefile +++ b/drivers/pinctrl/samsung/Makefile @@ -5,5 +5,4 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o obj-$(CONFIG_PINCTRL_EXYNOS_ARM) += pinctrl-exynos-arm.o obj-$(CONFIG_PINCTRL_EXYNOS_ARM64) += pinctrl-exynos-arm64.o -obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c deleted file mode 100644 index 625cb1065eaf..000000000000 --- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c +++ /dev/null @@ -1,653 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// S3C24XX specific support for Samsung pinctrl/gpiolib driver. -// -// Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> -// -// This file contains the SamsungS3C24XX specific information required by the -// Samsung pinctrl/gpiolib driver. It also includes the implementation of -// external gpio and wakeup interrupt support. - -#include <linux/init.h> -#include <linux/device.h> -#include <linux/interrupt.h> -#include <linux/irqdomain.h> -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/irqchip/chained_irq.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/err.h> - -#include "pinctrl-samsung.h" - -#define NUM_EINT 24 -#define NUM_EINT_IRQ 6 -#define EINT_MAX_PER_GROUP 8 - -#define EINTPEND_REG 0xa8 -#define EINTMASK_REG 0xa4 - -#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP)) -#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88) -#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4) - -#define EINT_LEVEL_LOW 0 -#define EINT_LEVEL_HIGH 1 -#define EINT_EDGE_FALLING 2 -#define EINT_EDGE_RISING 4 -#define EINT_EDGE_BOTH 6 -#define EINT_MASK 0xf - -static const struct samsung_pin_bank_type bank_type_1bit = { - .fld_width = { 1, 1, }, - .reg_offset = { 0x00, 0x04, }, -}; - -static const struct samsung_pin_bank_type bank_type_2bit = { - .fld_width = { 2, 1, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, }, -}; - -#define PIN_BANK_A(pins, reg, id) \ - { \ - .type = &bank_type_1bit, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_NONE, \ - .name = id \ - } - -#define PIN_BANK_2BIT(pins, reg, id) \ - { \ - .type = &bank_type_2bit, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_NONE, \ - .name = id \ - } - -#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\ - { \ - .type = &bank_type_2bit, \ - .pctl_offset = reg, \ - .nr_pins = pins, \ - .eint_type = EINT_TYPE_WKUP, \ - .eint_func = 2, \ - .eint_mask = emask, \ - .eint_offset = eoffs, \ - .name = id \ - } - -/** - * struct s3c24xx_eint_data - EINT common data - * @drvdata: pin controller driver data - * @domains: IRQ domains of particular EINT interrupts - * @parents: mapped parent irqs in the main interrupt controller - */ -struct s3c24xx_eint_data { - struct samsung_pinctrl_drv_data *drvdata; - struct irq_domain *domains[NUM_EINT]; - int parents[NUM_EINT_IRQ]; -}; - -/** - * struct s3c24xx_eint_domain_data - per irq-domain data - * @bank: pin bank related to the domain - * @eint_data: common data - * @eint0_3_parent_only: live eints 0-3 only in the main intc - */ -struct s3c24xx_eint_domain_data { - struct samsung_pin_bank *bank; - struct s3c24xx_eint_data *eint_data; - bool eint0_3_parent_only; -}; - -static int s3c24xx_eint_get_trigger(unsigned int type) -{ - switch (type) { - case IRQ_TYPE_EDGE_RISING: - return EINT_EDGE_RISING; - case IRQ_TYPE_EDGE_FALLING: - return EINT_EDGE_FALLING; - case IRQ_TYPE_EDGE_BOTH: - return EINT_EDGE_BOTH; - case IRQ_TYPE_LEVEL_HIGH: - return EINT_LEVEL_HIGH; - case IRQ_TYPE_LEVEL_LOW: - return EINT_LEVEL_LOW; - default: - return -EINVAL; - } -} - -static void s3c24xx_eint_set_handler(struct irq_data *d, unsigned int type) -{ - /* Edge- and level-triggered interrupts need different handlers */ - if (type & IRQ_TYPE_EDGE_BOTH) - irq_set_handler_locked(d, handle_edge_irq); - else - irq_set_handler_locked(d, handle_level_irq); -} - -static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, - struct samsung_pin_bank *bank, int pin) -{ - const struct samsung_pin_bank_type *bank_type = bank->type; - unsigned long flags; - void __iomem *reg; - u8 shift; - u32 mask; - u32 val; - - /* Make sure that pin is configured as interrupt */ - reg = d->virt_base + bank->pctl_offset; - shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; - mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; - - raw_spin_lock_irqsave(&bank->slock, flags); - - val = readl(reg); - val &= ~(mask << shift); - val |= bank->eint_func << shift; - writel(val, reg); - - raw_spin_unlock_irqrestore(&bank->slock, flags); -} - -static int s3c24xx_eint_type(struct irq_data *data, unsigned int type) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - int index = bank->eint_offset + data->hwirq; - void __iomem *reg; - int trigger; - u8 shift; - u32 val; - - trigger = s3c24xx_eint_get_trigger(type); - if (trigger < 0) { - dev_err(d->dev, "unsupported external interrupt type\n"); - return -EINVAL; - } - - s3c24xx_eint_set_handler(data, type); - - /* Set up interrupt trigger */ - reg = d->virt_base + EINT_REG(index); - shift = EINT_OFFS(index); - - val = readl(reg); - val &= ~(EINT_MASK << shift); - val |= trigger << shift; - writel(val, reg); - - s3c24xx_eint_set_function(d, bank, data->hwirq); - - return 0; -} - -/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */ - -static void s3c2410_eint0_3_ack(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; - struct s3c24xx_eint_data *eint_data = ddata->eint_data; - int parent_irq = eint_data->parents[data->hwirq]; - struct irq_chip *parent_chip = irq_get_chip(parent_irq); - - parent_chip->irq_ack(irq_get_irq_data(parent_irq)); -} - -static void s3c2410_eint0_3_mask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; - struct s3c24xx_eint_data *eint_data = ddata->eint_data; - int parent_irq = eint_data->parents[data->hwirq]; - struct irq_chip *parent_chip = irq_get_chip(parent_irq); - - parent_chip->irq_mask(irq_get_irq_data(parent_irq)); -} - -static void s3c2410_eint0_3_unmask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data; - struct s3c24xx_eint_data *eint_data = ddata->eint_data; - int parent_irq = eint_data->parents[data->hwirq]; - struct irq_chip *parent_chip = irq_get_chip(parent_irq); - - parent_chip->irq_unmask(irq_get_irq_data(parent_irq)); -} - -static struct irq_chip s3c2410_eint0_3_chip = { - .name = "s3c2410-eint0_3", - .irq_ack = s3c2410_eint0_3_ack, - .irq_mask = s3c2410_eint0_3_mask, - .irq_unmask = s3c2410_eint0_3_unmask, - .irq_set_type = s3c24xx_eint_type, -}; - -static void s3c2410_demux_eint0_3(struct irq_desc *desc) -{ - struct irq_data *data = irq_desc_get_irq_data(desc); - struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc); - int ret; - - /* the first 4 eints have a simple 1 to 1 mapping */ - ret = generic_handle_domain_irq(eint_data->domains[data->hwirq], data->hwirq); - /* Something must be really wrong if an unmapped EINT is unmasked */ - BUG_ON(ret); -} - -/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */ - -static void s3c2412_eint0_3_ack(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - - unsigned long bitval = 1UL << data->hwirq; - writel(bitval, d->virt_base + EINTPEND_REG); -} - -static void s3c2412_eint0_3_mask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long mask; - - mask = readl(d->virt_base + EINTMASK_REG); - mask |= (1UL << data->hwirq); - writel(mask, d->virt_base + EINTMASK_REG); -} - -static void s3c2412_eint0_3_unmask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned long mask; - - mask = readl(d->virt_base + EINTMASK_REG); - mask &= ~(1UL << data->hwirq); - writel(mask, d->virt_base + EINTMASK_REG); -} - -static struct irq_chip s3c2412_eint0_3_chip = { - .name = "s3c2412-eint0_3", - .irq_ack = s3c2412_eint0_3_ack, - .irq_mask = s3c2412_eint0_3_mask, - .irq_unmask = s3c2412_eint0_3_unmask, - .irq_set_type = s3c24xx_eint_type, -}; - -static void s3c2412_demux_eint0_3(struct irq_desc *desc) -{ - struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc); - struct irq_data *data = irq_desc_get_irq_data(desc); - struct irq_chip *chip = irq_data_get_irq_chip(data); - int ret; - - chained_irq_enter(chip, desc); - - /* the first 4 eints have a simple 1 to 1 mapping */ - ret = generic_handle_domain_irq(eint_data->domains[data->hwirq], data->hwirq); - /* Something must be really wrong if an unmapped EINT is unmasked */ - BUG_ON(ret); - - chained_irq_exit(chip, desc); -} - -/* Handling of all other eints */ - -static void s3c24xx_eint_ack(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned char index = bank->eint_offset + data->hwirq; - - writel(1UL << index, d->virt_base + EINTPEND_REG); -} - -static void s3c24xx_eint_mask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned char index = bank->eint_offset + data->hwirq; - unsigned long mask; - - mask = readl(d->virt_base + EINTMASK_REG); - mask |= (1UL << index); - writel(mask, d->virt_base + EINTMASK_REG); -} - -static void s3c24xx_eint_unmask(struct irq_data *data) -{ - struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); - struct samsung_pinctrl_drv_data *d = bank->drvdata; - unsigned char index = bank->eint_offset + data->hwirq; - unsigned long mask; - - mask = readl(d->virt_base + EINTMASK_REG); - mask &= ~(1UL << index); - writel(mask, d->virt_base + EINTMASK_REG); -} - -static struct irq_chip s3c24xx_eint_chip = { - .name = "s3c-eint", - .irq_ack = s3c24xx_eint_ack, - .irq_mask = s3c24xx_eint_mask, - .irq_unmask = s3c24xx_eint_unmask, - .irq_set_type = s3c24xx_eint_type, -}; - -static inline void s3c24xx_demux_eint(struct irq_desc *desc, - u32 offset, u32 range) -{ - struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - struct samsung_pinctrl_drv_data *d = data->drvdata; - unsigned int pend, mask; - - chained_irq_enter(chip, desc); - - pend = readl(d->virt_base + EINTPEND_REG); - mask = readl(d->virt_base + EINTMASK_REG); - - pend &= ~mask; - pend &= range; - - while (pend) { - unsigned int irq; - int ret; - - irq = __ffs(pend); - pend &= ~(1 << irq); - ret = generic_handle_domain_irq(data->domains[irq], irq - offset); - /* Something is really wrong if an unmapped EINT is unmasked */ - BUG_ON(ret); - } - - chained_irq_exit(chip, desc); -} - -static void s3c24xx_demux_eint4_7(struct irq_desc *desc) -{ - s3c24xx_demux_eint(desc, 0, 0xf0); -} - -static void s3c24xx_demux_eint8_23(struct irq_desc *desc) -{ - s3c24xx_demux_eint(desc, 8, 0xffff00); -} - -static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = { - s3c2410_demux_eint0_3, - s3c2410_demux_eint0_3, - s3c2410_demux_eint0_3, - s3c2410_demux_eint0_3, - s3c24xx_demux_eint4_7, - s3c24xx_demux_eint8_23, -}; - -static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = { - s3c2412_demux_eint0_3, - s3c2412_demux_eint0_3, - s3c2412_demux_eint0_3, - s3c2412_demux_eint0_3, - s3c24xx_demux_eint4_7, - s3c24xx_demux_eint8_23, -}; - -static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct s3c24xx_eint_domain_data *ddata = h->host_data; - struct samsung_pin_bank *bank = ddata->bank; - - if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) - return -EINVAL; - - if (hw <= 3) { - if (ddata->eint0_3_parent_only) - irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip, - handle_edge_irq); - else - irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip, - handle_edge_irq); - } else { - irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, - handle_edge_irq); - } - irq_set_chip_data(virq, bank); - return 0; -} - -static const struct irq_domain_ops s3c24xx_gpf_irq_ops = { - .map = s3c24xx_gpf_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct s3c24xx_eint_domain_data *ddata = h->host_data; - struct samsung_pin_bank *bank = ddata->bank; - - if (!(bank->eint_mask & (1 << (bank->eint_offset + hw)))) - return -EINVAL; - - irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq); - irq_set_chip_data(virq, bank); - return 0; -} - -static const struct irq_domain_ops s3c24xx_gpg_irq_ops = { - .map = s3c24xx_gpg_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - -static const struct of_device_id s3c24xx_eint_irq_ids[] = { - { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 }, - { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 }, - { } -}; - -static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d) -{ - struct device *dev = d->dev; - const struct of_device_id *match; - struct device_node *eint_np = NULL; - struct device_node *np; - struct samsung_pin_bank *bank; - struct s3c24xx_eint_data *eint_data; - const struct irq_domain_ops *ops; - unsigned int i; - bool eint0_3_parent_only; - irq_flow_handler_t *handlers; - - for_each_child_of_node(dev->of_node, np) { - match = of_match_node(s3c24xx_eint_irq_ids, np); - if (match) { - eint_np = np; - eint0_3_parent_only = (bool)match->data; - break; - } - } - if (!eint_np) - return -ENODEV; - - eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL); - if (!eint_data) { - of_node_put(eint_np); - return -ENOMEM; - } - - eint_data->drvdata = d; - - handlers = eint0_3_parent_only ? s3c2410_eint_handlers - : s3c2412_eint_handlers; - for (i = 0; i < NUM_EINT_IRQ; ++i) { - unsigned int irq; - - irq = irq_of_parse_and_map(eint_np, i); - if (!irq) { - dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i); - of_node_put(eint_np); - return -ENXIO; - } - - eint_data->parents[i] = irq; - irq_set_chained_handler_and_data(irq, handlers[i], eint_data); - } - of_node_put(eint_np); - - bank = d->pin_banks; - for (i = 0; i < d->nr_banks; ++i, ++bank) { - struct s3c24xx_eint_domain_data *ddata; - unsigned int mask; - unsigned int irq; - unsigned int pin; - - if (bank->eint_type != EINT_TYPE_WKUP) - continue; - - ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); - if (!ddata) - return -ENOMEM; - - ddata->bank = bank; - ddata->eint_data = eint_data; - ddata->eint0_3_parent_only = eint0_3_parent_only; - - ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops - : &s3c24xx_gpg_irq_ops; - - bank->irq_domain = irq_domain_create_linear(bank->fwnode, - bank->nr_pins, ops, ddata); - if (!bank->irq_domain) { - dev_err(dev, "wkup irq domain add failed\n"); - return -ENXIO; - } - - irq = bank->eint_offset; - mask = bank->eint_mask; - for (pin = 0; mask; ++pin, mask >>= 1) { - if (irq >= NUM_EINT) - break; - if (!(mask & 1)) - continue; - eint_data->domains[irq] = bank->irq_domain; - ++irq; - } - } - - return 0; -} - -static const struct samsung_pin_bank_data s3c2412_pin_banks[] __initconst = { - PIN_BANK_A(23, 0x000, "gpa"), - PIN_BANK_2BIT(11, 0x010, "gpb"), - PIN_BANK_2BIT(16, 0x020, "gpc"), - PIN_BANK_2BIT(16, 0x030, "gpd"), - PIN_BANK_2BIT(16, 0x040, "gpe"), - PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), - PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), - PIN_BANK_2BIT(11, 0x070, "gph"), - PIN_BANK_2BIT(13, 0x080, "gpj"), -}; - -static const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = { - { - .pin_banks = s3c2412_pin_banks, - .nr_banks = ARRAY_SIZE(s3c2412_pin_banks), - .eint_wkup_init = s3c24xx_eint_init, - }, -}; - -const struct samsung_pinctrl_of_match_data s3c2412_of_data __initconst = { - .ctrl = s3c2412_pin_ctrl, - .num_ctrl = ARRAY_SIZE(s3c2412_pin_ctrl), -}; - -static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = { - PIN_BANK_A(27, 0x000, "gpa"), - PIN_BANK_2BIT(11, 0x010, "gpb"), - PIN_BANK_2BIT(16, 0x020, "gpc"), - PIN_BANK_2BIT(16, 0x030, "gpd"), - PIN_BANK_2BIT(16, 0x040, "gpe"), - PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), - PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00), - PIN_BANK_2BIT(15, 0x070, "gph"), - PIN_BANK_2BIT(16, 0x0e0, "gpk"), - PIN_BANK_2BIT(14, 0x0f0, "gpl"), - PIN_BANK_2BIT(2, 0x100, "gpm"), -}; - -static const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = { - { - .pin_banks = s3c2416_pin_banks, - .nr_banks = ARRAY_SIZE(s3c2416_pin_banks), - .eint_wkup_init = s3c24xx_eint_init, - }, -}; - -const struct samsung_pinctrl_of_match_data s3c2416_of_data __initconst = { - .ctrl = s3c2416_pin_ctrl, - .num_ctrl = ARRAY_SIZE(s3c2416_pin_ctrl), -}; - -static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = { - PIN_BANK_A(25, 0x000, "gpa"), - PIN_BANK_2BIT(11, 0x010, "gpb"), - PIN_BANK_2BIT(16, 0x020, "gpc"), - PIN_BANK_2BIT(16, 0x030, "gpd"), - PIN_BANK_2BIT(16, 0x040, "gpe"), - PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), - PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), - PIN_BANK_2BIT(11, 0x070, "gph"), - PIN_BANK_2BIT(13, 0x0d0, "gpj"), -}; - -static const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = { - { - .pin_banks = s3c2440_pin_banks, - .nr_banks = ARRAY_SIZE(s3c2440_pin_banks), - .eint_wkup_init = s3c24xx_eint_init, - }, -}; - -const struct samsung_pinctrl_of_match_data s3c2440_of_data __initconst = { - .ctrl = s3c2440_pin_ctrl, - .num_ctrl = ARRAY_SIZE(s3c2440_pin_ctrl), -}; - -static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = { - PIN_BANK_A(28, 0x000, "gpa"), - PIN_BANK_2BIT(11, 0x010, "gpb"), - PIN_BANK_2BIT(16, 0x020, "gpc"), - PIN_BANK_2BIT(16, 0x030, "gpd"), - PIN_BANK_2BIT(16, 0x040, "gpe"), - PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff), - PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00), - PIN_BANK_2BIT(15, 0x070, "gph"), - PIN_BANK_2BIT(16, 0x0d0, "gpj"), - PIN_BANK_2BIT(16, 0x0e0, "gpk"), - PIN_BANK_2BIT(15, 0x0f0, "gpl"), - PIN_BANK_2BIT(2, 0x100, "gpm"), -}; - -static const struct samsung_pin_ctrl s3c2450_pin_ctrl[] __initconst = { - { - .pin_banks = s3c2450_pin_banks, - .nr_banks = ARRAY_SIZE(s3c2450_pin_banks), - .eint_wkup_init = s3c24xx_eint_init, - }, -}; - -const struct samsung_pinctrl_of_match_data s3c2450_of_data __initconst = { - .ctrl = s3c2450_pin_ctrl, - .num_ctrl = ARRAY_SIZE(s3c2450_pin_ctrl), -}; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 5736761927cb..514001e448b9 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1324,16 +1324,6 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { { .compatible = "samsung,s3c64xx-pinctrl", .data = &s3c64xx_of_data }, #endif -#ifdef CONFIG_PINCTRL_S3C24XX - { .compatible = "samsung,s3c2412-pinctrl", - .data = &s3c2412_of_data }, - { .compatible = "samsung,s3c2416-pinctrl", - .data = &s3c2416_of_data }, - { .compatible = "samsung,s3c2440-pinctrl", - .data = &s3c2440_of_data }, - { .compatible = "samsung,s3c2450-pinctrl", - .data = &s3c2450_of_data }, -#endif {}, }; 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