diff options
Diffstat (limited to 'drivers/staging/comedi/drivers/ni_mio_common.c')
| -rw-r--r-- | drivers/staging/comedi/drivers/ni_mio_common.c | 4866 |
1 files changed, 2443 insertions, 2423 deletions
diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c index 7ffdcc07ef92..297c95d2e0a3 100644 --- a/drivers/staging/comedi/drivers/ni_mio_common.c +++ b/drivers/staging/comedi/drivers/ni_mio_common.c @@ -194,113 +194,6 @@ static const struct comedi_lrange *const ni_range_lkup[] = { [ai_gain_6143] = &range_bipolar5 }; -static int ni_dio_insn_config(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static int ni_dio_insn_bits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static int ni_cdio_cmdtest(struct comedi_device *dev, - struct comedi_subdevice *s, struct comedi_cmd *cmd); -static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s); -static int ni_cdio_cancel(struct comedi_device *dev, - struct comedi_subdevice *s); -static void handle_cdio_interrupt(struct comedi_device *dev); -static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, - unsigned int trignum); - -static int ni_serial_insn_config(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static int ni_serial_hw_readwrite8(struct comedi_device *dev, - struct comedi_subdevice *s, - unsigned char data_out, - unsigned char *data_in); -static int ni_serial_sw_readwrite8(struct comedi_device *dev, - struct comedi_subdevice *s, - unsigned char data_out, - unsigned char *data_in); - -static int ni_calib_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static int ni_calib_insn_write(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); - -static int ni_eeprom_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data); - -static int ni_pfi_insn_bits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static int ni_pfi_insn_config(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, - unsigned chan); - -static void ni_rtsi_init(struct comedi_device *dev); -static int ni_rtsi_insn_bits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static int ni_rtsi_insn_config(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); - -static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s); -static int ni_read_eeprom(struct comedi_device *dev, int addr); - -#ifndef PCIDMA -static void ni_handle_fifo_half_full(struct comedi_device *dev); -static int ni_ao_fifo_half_empty(struct comedi_device *dev, - struct comedi_subdevice *s); -#endif -static void ni_handle_fifo_dregs(struct comedi_device *dev); -static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, - unsigned int trignum); -static void ni_load_channelgain_list(struct comedi_device *dev, - unsigned int n_chan, unsigned int *list); -static void shutdown_ai_command(struct comedi_device *dev); - -static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, - unsigned int trignum); - -static int ni_8255_callback(int dir, int port, int data, unsigned long arg); - -#ifdef PCIDMA -static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s); -static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s); -#endif -static void handle_gpct_interrupt(struct comedi_device *dev, - unsigned short counter_index); - -static int init_cs5529(struct comedi_device *dev); -static int cs5529_do_conversion(struct comedi_device *dev, - unsigned short *data); -static int cs5529_ai_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static void cs5529_config_write(struct comedi_device *dev, unsigned int value, - unsigned int reg_select_bits); - -static int ni_m_series_pwm_config(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); -static int ni_6143_pwm_config(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data); - -static int ni_set_master_clock(struct comedi_device *dev, unsigned source, - unsigned period_ns); -static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status); -static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status); - enum aimodes { AIMODE_NONE = 0, AIMODE_HALF_FULL = 1, @@ -330,10 +223,8 @@ static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index) switch (counter_index) { case 0: return NI_GPCT0_SUBDEV; - break; case 1: return NI_GPCT1_SUBDEV; - break; default: break; } @@ -353,12 +244,394 @@ enum timebase_nanoseconds { static const int num_adc_stages_611x = 3; -static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, - unsigned ai_mite_status); -static void handle_b_interrupt(struct comedi_device *dev, unsigned short status, - unsigned ao_mite_status); -static void get_last_sample_611x(struct comedi_device *dev); -static void get_last_sample_6143(struct comedi_device *dev); +static void ni_writel(struct comedi_device *dev, uint32_t data, int reg) +{ + if (dev->mmio) + writel(data, dev->mmio + reg); + + outl(data, dev->iobase + reg); +} + +static void ni_writew(struct comedi_device *dev, uint16_t data, int reg) +{ + if (dev->mmio) + writew(data, dev->mmio + reg); + + outw(data, dev->iobase + reg); +} + +static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg) +{ + if (dev->mmio) + writeb(data, dev->mmio + reg); + + outb(data, dev->iobase + reg); +} + +static uint32_t ni_readl(struct comedi_device *dev, int reg) +{ + if (dev->mmio) + return readl(dev->mmio + reg); + + return inl(dev->iobase + reg); +} + +static uint16_t ni_readw(struct comedi_device *dev, int reg) +{ + if (dev->mmio) + return readw(dev->mmio + reg); + + return inw(dev->iobase + reg); +} + +static uint8_t ni_readb(struct comedi_device *dev, int reg) +{ + if (dev->mmio) + return readb(dev->mmio + reg); + + return inb(dev->iobase + reg); +} + +/* + * We automatically take advantage of STC registers that can be + * read/written directly in the I/O space of the board. + * + * The AT-MIO and DAQCard devices map the low 8 STC registers to + * iobase+reg*2. + * + * Most PCIMIO devices also map the low 8 STC registers but the + * 611x devices map the read registers to iobase+(addr-1)*2. + * For now non-windowed STC access is disabled if a PCIMIO device + * is detected (devpriv->mite has been initialized). + * + * The M series devices do not used windowed registers for the + * STC registers. The functions below handle the mapping of the + * windowed STC registers to the m series register offsets. + */ + +static void m_series_stc_writel(struct comedi_device *dev, + uint32_t data, int reg) +{ + unsigned offset; + + switch (reg) { + case AI_SC_Load_A_Registers: + offset = M_Offset_AI_SC_Load_A; + break; + case AI_SI_Load_A_Registers: + offset = M_Offset_AI_SI_Load_A; + break; + case AO_BC_Load_A_Register: + offset = M_Offset_AO_BC_Load_A; + break; + case AO_UC_Load_A_Register: + offset = M_Offset_AO_UC_Load_A; + break; + case AO_UI_Load_A_Register: + offset = M_Offset_AO_UI_Load_A; + break; + case G_Load_A_Register(0): + offset = M_Offset_G0_Load_A; + break; + case G_Load_A_Register(1): + offset = M_Offset_G1_Load_A; + break; + case G_Load_B_Register(0): + offset = M_Offset_G0_Load_B; + break; + case G_Load_B_Register(1): + offset = M_Offset_G1_Load_B; + break; + default: + dev_warn(dev->class_dev, + "%s: bug! unhandled register=0x%x in switch\n", + __func__, reg); + return; + } + ni_writel(dev, data, offset); +} + +static void m_series_stc_writew(struct comedi_device *dev, + uint16_t data, int reg) +{ + unsigned offset; + + switch (reg) { + case ADC_FIFO_Clear: + offset = M_Offset_AI_FIFO_Clear; + break; + case AI_Command_1_Register: + offset = M_Offset_AI_Command_1; + break; + case AI_Command_2_Register: + offset = M_Offset_AI_Command_2; + break; + case AI_Mode_1_Register: + offset = M_Offset_AI_Mode_1; + break; + case AI_Mode_2_Register: + offset = M_Offset_AI_Mode_2; + break; + case AI_Mode_3_Register: + offset = M_Offset_AI_Mode_3; + break; + case AI_Output_Control_Register: + offset = M_Offset_AI_Output_Control; + break; + case AI_Personal_Register: + offset = M_Offset_AI_Personal; + break; + case AI_SI2_Load_A_Register: + /* this is a 32 bit register on m series boards */ + ni_writel(dev, data, M_Offset_AI_SI2_Load_A); + return; + case AI_SI2_Load_B_Register: + /* this is a 32 bit register on m series boards */ + ni_writel(dev, data, M_Offset_AI_SI2_Load_B); + return; + case AI_START_STOP_Select_Register: + offset = M_Offset_AI_START_STOP_Select; + break; + case AI_Trigger_Select_Register: + offset = M_Offset_AI_Trigger_Select; + break; + case Analog_Trigger_Etc_Register: + offset = M_Offset_Analog_Trigger_Etc; + break; + case AO_Command_1_Register: + offset = M_Offset_AO_Command_1; + break; + case AO_Command_2_Register: + offset = M_Offset_AO_Command_2; + break; + case AO_Mode_1_Register: + offset = M_Offset_AO_Mode_1; + break; + case AO_Mode_2_Register: + offset = M_Offset_AO_Mode_2; + break; + case AO_Mode_3_Register: + offset = M_Offset_AO_Mode_3; + break; + case AO_Output_Control_Register: + offset = M_Offset_AO_Output_Control; + break; + case AO_Personal_Register: + offset = M_Offset_AO_Personal; + break; + case AO_Start_Select_Register: + offset = M_Offset_AO_Start_Select; + break; + case AO_Trigger_Select_Register: + offset = M_Offset_AO_Trigger_Select; + break; + case Clock_and_FOUT_Register: + offset = M_Offset_Clock_and_FOUT; + break; + case Configuration_Memory_Clear: + offset = M_Offset_Configuration_Memory_Clear; + break; + case DAC_FIFO_Clear: + offset = M_Offset_AO_FIFO_Clear; + break; + case DIO_Control_Register: + dev_dbg(dev->class_dev, + "%s: FIXME: register 0x%x does not map cleanly on to m-series boards\n", + __func__, reg); + return; + case G_Autoincrement_Register(0): + offset = M_Offset_G0_Autoincrement; + break; + case G_Autoincrement_Register(1): + offset = M_Offset_G1_Autoincrement; + break; + case G_Command_Register(0): + offset = M_Offset_G0_Command; + break; + case G_Command_Register(1): + offset = M_Offset_G1_Command; + break; + case G_Input_Select_Register(0): + offset = M_Offset_G0_Input_Select; + break; + case G_Input_Select_Register(1): + offset = M_Offset_G1_Input_Select; + break; + case G_Mode_Register(0): + offset = M_Offset_G0_Mode; + break; + case G_Mode_Register(1): + offset = M_Offset_G1_Mode; + break; + case Interrupt_A_Ack_Register: + offset = M_Offset_Interrupt_A_Ack; + break; + case Interrupt_A_Enable_Register: + offset = M_Offset_Interrupt_A_Enable; + break; + case Interrupt_B_Ack_Register: + offset = M_Offset_Interrupt_B_Ack; + break; + case Interrupt_B_Enable_Register: + offset = M_Offset_Interrupt_B_Enable; + break; + case Interrupt_Control_Register: + offset = M_Offset_Interrupt_Control; + break; + case IO_Bidirection_Pin_Register: + offset = M_Offset_IO_Bidirection_Pin; + break; + case Joint_Reset_Register: + offset = M_Offset_Joint_Reset; + break; + case RTSI_Trig_A_Output_Register: + offset = M_Offset_RTSI_Trig_A_Output; + break; + case RTSI_Trig_B_Output_Register: + offset = M_Offset_RTSI_Trig_B_Output; + break; + case RTSI_Trig_Direction_Register: + offset = M_Offset_RTSI_Trig_Direction; + break; + /* + * FIXME: DIO_Output_Register (16 bit reg) is replaced by + * M_Offset_Static_Digital_Output (32 bit) and + * M_Offset_SCXI_Serial_Data_Out (8 bit) + */ + default: + dev_warn(dev->class_dev, + "%s: bug! unhandled register=0x%x in switch\n", + __func__, reg); + return; + } + ni_writew(dev, data, offset); +} + +static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg) +{ + unsigned offset; + + switch (reg) { + case G_HW_Save_Register(0): + offset = M_Offset_G0_HW_Save; + break; + case G_HW_Save_Register(1): + offset = M_Offset_G1_HW_Save; + break; + case G_Save_Register(0): + offset = M_Offset_G0_Save; + break; + case G_Save_Register(1): + offset = M_Offset_G1_Save; + break; + default: + dev_warn(dev->class_dev, + "%s: bug! unhandled register=0x%x in switch\n", + __func__, reg); + return 0; + } + return ni_readl(dev, offset); +} + +static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg) +{ + unsigned offset; + + switch (reg) { + case AI_Status_1_Register: + offset = M_Offset_AI_Status_1; + break; + case AO_Status_1_Register: + offset = M_Offset_AO_Status_1; + break; + case AO_Status_2_Register: + offset = M_Offset_AO_Status_2; + break; + case DIO_Serial_Input_Register: + return ni_readb(dev, M_Offset_SCXI_Serial_Data_In); + case Joint_Status_1_Register: + offset = M_Offset_Joint_Status_1; + break; + case Joint_Status_2_Register: + offset = M_Offset_Joint_Status_2; + break; + case G_Status_Register: + offset = M_Offset_G01_Status; + break; + default: + dev_warn(dev->class_dev, + "%s: bug! unhandled register=0x%x in switch\n", + __func__, reg); + return 0; + } + return ni_readw(dev, offset); +} + +static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg) +{ + struct ni_private *devpriv = dev->private; + unsigned long flags; + + if (devpriv->is_m_series) { + m_series_stc_writew(dev, data, reg); + } else { + spin_lock_irqsave(&devpriv->window_lock, flags); + if (!devpriv->mite && reg < 8) { + ni_writew(dev, data, reg * 2); + } else { + ni_writew(dev, reg, Window_Address); + ni_writew(dev, data, Window_Data); + } + spin_unlock_irqrestore(&devpriv->window_lock, flags); + } +} + +static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg) +{ + struct ni_private *devpriv = dev->private; + + if (devpriv->is_m_series) { + m_series_stc_writel(dev, data, reg); + } else { + ni_stc_writew(dev, data >> 16, reg); + ni_stc_writew(dev, data & 0xffff, reg + 1); + } +} + +static uint16_t ni_stc_readw(struct comedi_device *dev, int reg) +{ + struct ni_private *devpriv = dev->private; + unsigned long flags; + uint16_t val; + + if (devpriv->is_m_series) { + val = m_series_stc_readw(dev, reg); + } else { + spin_lock_irqsave(&devpriv->window_lock, flags); + if (!devpriv->mite && reg < 8) { + val = ni_readw(dev, reg * 2); + } else { + ni_writew(dev, reg, Window_Address); + val = ni_readw(dev, Window_Data); + } + spin_unlock_irqrestore(&devpriv->window_lock, flags); + } + return val; +} + +static uint32_t ni_stc_readl(struct comedi_device *dev, int reg) +{ + struct ni_private *devpriv = dev->private; + uint32_t val; + + if (devpriv->is_m_series) { + val = m_series_stc_readl(dev, reg); + } else { + val = ni_stc_readw(dev, reg) << 16; + val |= ni_stc_readw(dev, reg + 1); + } + return val; +} static inline void ni_set_bitfield(struct comedi_device *dev, int reg, unsigned bit_mask, unsigned bit_values) @@ -371,34 +644,34 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg, case Interrupt_A_Enable_Register: devpriv->int_a_enable_reg &= ~bit_mask; devpriv->int_a_enable_reg |= bit_values & bit_mask; - devpriv->stc_writew(dev, devpriv->int_a_enable_reg, - Interrupt_A_Enable_Register); + ni_stc_writew(dev, devpriv->int_a_enable_reg, + Interrupt_A_Enable_Register); break; case Interrupt_B_Enable_Register: devpriv->int_b_enable_reg &= ~bit_mask; devpriv->int_b_enable_reg |= bit_values & bit_mask; - devpriv->stc_writew(dev, devpriv->int_b_enable_reg, - Interrupt_B_Enable_Register); + ni_stc_writew(dev, devpriv->int_b_enable_reg, + Interrupt_B_Enable_Register); break; case IO_Bidirection_Pin_Register: devpriv->io_bidirection_pin_reg &= ~bit_mask; devpriv->io_bidirection_pin_reg |= bit_values & bit_mask; - devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg, - IO_Bidirection_Pin_Register); + ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, + IO_Bidirection_Pin_Register); break; case AI_AO_Select: devpriv->ai_ao_select_reg &= ~bit_mask; devpriv->ai_ao_select_reg |= bit_values & bit_mask; - ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select); + ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select); break; case G0_G1_Select: devpriv->g0_g1_select_reg &= ~bit_mask; devpriv->g0_g1_select_reg |= bit_values & bit_mask; - ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select); + ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select); break; default: - printk("Warning %s() called with invalid register\n", __func__); - printk("reg is %d\n", reg); + dev_err(dev->class_dev, + "%s called with invalid register %d\n", __func__, reg); break; } mmiowb(); @@ -406,8 +679,6 @@ static inline void ni_set_bitfield(struct comedi_device *dev, int reg, } #ifdef PCIDMA -static int ni_ai_drain_dma(struct comedi_device *dev); - /* DMA channel setup */ /* negative channel means no channel */ @@ -472,7 +743,7 @@ static inline void ni_set_cdo_dma_channel(struct comedi_device *dev, (ni_stc_dma_channel_select_bitfield(mite_channel) << CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask; } - ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select); + ni_writeb(dev, devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select); mmiowb(); spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); } @@ -488,8 +759,8 @@ static int ni_request_ai_mite_channel(struct comedi_device *dev) mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); if (devpriv->ai_mite_chan == NULL) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); - comedi_error(dev, - "failed to reserve mite dma channel for analog input."); + dev_err(dev->class_dev, + "failed to reserve mite dma channel for analog input\n"); return -EBUSY; } devpriv->ai_mite_chan->dir = COMEDI_INPUT; @@ -509,8 +780,8 @@ static int ni_request_ao_mite_channel(struct comedi_device *dev) mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); if (devpriv->ao_mite_chan == NULL) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); - comedi_error(dev, - "failed to reserve mite dma channel for analog outut."); + dev_err(dev->class_dev, + "failed to reserve mite dma channel for analog outut\n"); return -EBUSY; } devpriv->ao_mite_chan->dir = COMEDI_OUTPUT; @@ -535,8 +806,8 @@ static int ni_request_gpct_mite_channel(struct comedi_device *dev, devpriv->gpct_mite_ring[gpct_index]); if (mite_chan == NULL) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); - comedi_error(dev, - "failed to reserve mite dma channel for counter."); + dev_err(dev->class_dev, + "failed to reserve mite dma channel for counter\n"); return -EBUSY; } mite_chan->dir = direction; @@ -561,8 +832,8 @@ static int ni_request_cdo_mite_channel(struct comedi_device *dev) mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); if (devpriv->cdo_mite_chan == NULL) { spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); - comedi_error(dev, - "failed to reserve mite dma channel for correlated digital outut."); + dev_err(dev->class_dev, + "failed to reserve mite dma channel for correlated digital output\n"); return -EBUSY; } devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT; @@ -643,100 +914,71 @@ static void ni_release_cdo_mite_channel(struct comedi_device *dev) #endif /* PCIDMA */ } -/* e-series boards use the second irq signals to generate dma requests for their counters */ #ifdef PCIDMA static void ni_e_series_enable_second_irq(struct comedi_device *dev, unsigned gpct_index, short enable) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; + uint16_t val = 0; + int reg; - if (board->reg_type & ni_reg_m_series_mask) + if (devpriv->is_m_series || gpct_index > 1) return; - switch (gpct_index) { - case 0: - if (enable) { - devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable, - Second_IRQ_A_Enable_Register); - } else { - devpriv->stc_writew(dev, 0, - Second_IRQ_A_Enable_Register); - } - break; - case 1: - if (enable) { - devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable, - Second_IRQ_B_Enable_Register); - } else { - devpriv->stc_writew(dev, 0, - Second_IRQ_B_Enable_Register); - } - break; - default: - BUG(); - break; + + /* + * e-series boards use the second irq signals to generate + * dma requests for their counters + */ + if (gpct_index == 0) { + reg = Second_IRQ_A_Enable_Register; + if (enable) + val = G0_Gate_Second_Irq_Enable; + } else { + reg = Second_IRQ_B_Enable_Register; + if (enable) + val = G1_Gate_Second_Irq_Enable; } + ni_stc_writew(dev, val, reg); } #endif /* PCIDMA */ static void ni_clear_ai_fifo(struct comedi_device *dev) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; static const int timeout = 10000; int i; - if (board->reg_type == ni_reg_6143) { + if (devpriv->is_6143) { /* Flush the 6143 data FIFO */ - ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */ - ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */ + ni_writel(dev, 0x10, AIFIFO_Control_6143); + ni_writel(dev, 0x00, AIFIFO_Control_6143); /* Wait for complete */ for (i = 0; i < timeout; i++) { - if (!(ni_readl(AIFIFO_Status_6143) & 0x10)) + if (!(ni_readl(dev, AIFIFO_Status_6143) & 0x10)) break; udelay(1); } - if (i == timeout) { - comedi_error(dev, "FIFO flush timeout."); - } + if (i == timeout) + dev_err(dev->class_dev, "FIFO flush timeout\n"); } else { - devpriv->stc_writew(dev, 1, ADC_FIFO_Clear); - if (board->reg_type == ni_reg_625x) { - ni_writeb(0, M_Offset_Static_AI_Control(0)); - ni_writeb(1, M_Offset_Static_AI_Control(0)); + ni_stc_writew(dev, 1, ADC_FIFO_Clear); + if (devpriv->is_625x) { + ni_writeb(dev, 0, M_Offset_Static_AI_Control(0)); + ni_writeb(dev, 1, M_Offset_Static_AI_Control(0)); #if 0 /* the NI example code does 3 convert pulses for 625x boards, but that appears to be wrong in practice. */ - devpriv->stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); - devpriv->stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); - devpriv->stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); + ni_stc_writew(dev, AI_CONVERT_Pulse, + AI_Command_1_Register); + ni_stc_writew(dev, AI_CONVERT_Pulse, + AI_Command_1_Register); + ni_stc_writew(dev, AI_CONVERT_Pulse, + AI_Command_1_Register); #endif } } } -static void win_out2(struct comedi_device *dev, uint32_t data, int reg) -{ - struct ni_private *devpriv = dev->private; - - devpriv->stc_writew(dev, data >> 16, reg); - devpriv->stc_writew(dev, data & 0xffff, reg + 1); -} - -static uint32_t win_in2(struct comedi_device *dev, int reg) -{ - struct ni_private *devpriv = dev->private; - uint32_t bits; - - bits = devpriv->stc_readw(dev, reg) << 16; - bits |= devpriv->stc_readw(dev, reg + 1); - return bits; -} - -#define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr) static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, int addr) { @@ -744,8 +986,8 @@ static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data, unsigned long flags; spin_lock_irqsave(&devpriv->window_lock, flags); - ni_writew(addr, AO_Window_Address_611x); - ni_writew(data, AO_Window_Data_611x); + ni_writew(dev, addr, AO_Window_Address_611x); + ni_writew(dev, data, AO_Window_Data_611x); spin_unlock_irqrestore(&devpriv->window_lock, flags); } @@ -756,8 +998,8 @@ static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data, unsigned long flags; spin_lock_irqsave(&devpriv->window_lock, flags); - ni_writew(addr, AO_Window_Address_611x); - ni_writel(data, AO_Window_Data_611x); + ni_writew(dev, addr, AO_Window_Address_611x); + ni_writel(dev, data, AO_Window_Data_611x); spin_unlock_irqrestore(&devpriv->window_lock, flags); } @@ -768,8 +1010,8 @@ static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr) unsigned short data; spin_lock_irqsave(&devpriv->window_lock, flags); - ni_writew(addr, AO_Window_Address_611x); - data = ni_readw(AO_Window_Data_611x); + ni_writew(dev, addr, AO_Window_Address_611x); + data = ni_readw(dev, AO_Window_Data_611x); spin_unlock_irqrestore(&devpriv->window_lock, flags); return data; } @@ -796,83 +1038,58 @@ static inline void ni_set_bits(struct comedi_device *dev, int reg, ni_set_bitfield(dev, reg, bits, bit_values); } -static irqreturn_t ni_E_interrupt(int irq, void *d) +#ifdef PCIDMA +static void ni_sync_ai_dma(struct comedi_device *dev) { - struct comedi_device *dev = d; struct ni_private *devpriv = dev->private; - unsigned short a_status; - unsigned short b_status; - unsigned int ai_mite_status = 0; - unsigned int ao_mite_status = 0; + struct comedi_subdevice *s = dev->read_subdev; unsigned long flags; -#ifdef PCIDMA - struct mite_struct *mite = devpriv->mite; -#endif - - if (!dev->attached) - return IRQ_NONE; - smp_mb(); /* make sure dev->attached is checked before handler does anything else. */ - - /* lock to avoid race with comedi_poll */ - spin_lock_irqsave(&dev->spinlock, flags); - a_status = devpriv->stc_readw(dev, AI_Status_1_Register); - b_status = devpriv->stc_readw(dev, AO_Status_1_Register); -#ifdef PCIDMA - if (mite) { - unsigned long flags_too; - - spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); - if (devpriv->ai_mite_chan) { - ai_mite_status = mite_get_status(devpriv->ai_mite_chan); - if (ai_mite_status & CHSR_LINKC) - writel(CHOR_CLRLC, - devpriv->mite->mite_io_addr + - MITE_CHOR(devpriv-> - ai_mite_chan->channel)); - } - if (devpriv->ao_mite_chan) { - ao_mite_status = mite_get_status(devpriv->ao_mite_chan); - if (ao_mite_status & CHSR_LINKC) - writel(CHOR_CLRLC, - mite->mite_io_addr + - MITE_CHOR(devpriv-> - ao_mite_chan->channel)); - } - spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); - } -#endif - ack_a_interrupt(dev, a_status); - ack_b_interrupt(dev, b_status); - if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT)) - handle_a_interrupt(dev, a_status, ai_mite_status); - if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT)) - handle_b_interrupt(dev, b_status, ao_mite_status); - handle_gpct_interrupt(dev, 0); - handle_gpct_interrupt(dev, 1); - handle_cdio_interrupt(dev); - spin_unlock_irqrestore(&dev->spinlock, flags); - return IRQ_HANDLED; + spin_lock_irqsave(&devpriv->mite_channel_lock, flags); + if (devpriv->ai_mite_chan) + mite_sync_input_dma(devpriv->ai_mite_chan, s); + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); } -#ifdef PCIDMA -static void ni_sync_ai_dma(struct comedi_device *dev) +static int ni_ai_drain_dma(struct comedi_device *dev) { struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV]; + int i; + static const int timeout = 10000; unsigned long flags; + int retval = 0; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - if (devpriv->ai_mite_chan) - mite_sync_input_dma(devpriv->ai_mite_chan, s); + if (devpriv->ai_mite_chan) { + for (i = 0; i < timeout; i++) { + if ((ni_stc_readw(dev, AI_Status_1_Register) & + AI_FIFO_Empty_St) + && mite_bytes_in_transit(devpriv->ai_mite_chan) == + 0) + break; + udelay(5); + } + if (i == timeout) { + dev_err(dev->class_dev, "%s timed out\n", __func__); + dev_err(dev->class_dev, + "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n", + mite_bytes_in_transit(devpriv->ai_mite_chan), + ni_stc_readw(dev, AI_Status_1_Register)); + retval = -1; + } + } spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); + + ni_sync_ai_dma(dev); + + return retval; } static void mite_handle_b_linkc(struct mite_struct *mite, struct comedi_device *dev) { struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV]; + struct comedi_subdevice *s = dev->write_subdev; unsigned long flags; spin_lock_irqsave(&devpriv->mite_channel_lock, flags); @@ -883,13 +1100,13 @@ static void mite_handle_b_linkc(struct mite_struct *mite, static int ni_ao_wait_for_dma_load(struct comedi_device *dev) { - struct ni_private *devpriv = dev->private; static const int timeout = 10000; int i; + for (i = 0; i < timeout; i++) { unsigned short b_status; - b_status = devpriv->stc_readw(dev, AO_Status_1_Register); + b_status = ni_stc_readw(dev, AO_Status_1_Register); if (b_status & AO_FIFO_Half_Full_St) break; /* if we poll too often, the pci bus activity seems @@ -897,247 +1114,19 @@ static int ni_ao_wait_for_dma_load(struct comedi_device *dev) udelay(10); } if (i == timeout) { - comedi_error(dev, "timed out waiting for dma load"); + dev_err(dev->class_dev, "timed out waiting for dma load\n"); return -EPIPE; } return 0; } - #endif /* PCIDMA */ -static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s) -{ - struct ni_private *devpriv = dev->private; - - if (devpriv->aimode == AIMODE_SCAN) { -#ifdef PCIDMA - static const int timeout = 10; - int i; - - for (i = 0; i < timeout; i++) { - ni_sync_ai_dma(dev); - if ((s->async->events & COMEDI_CB_EOS)) - break; - udelay(1); - } -#else - ni_handle_fifo_dregs(dev); - s->async->events |= COMEDI_CB_EOS; -#endif - } - /* handle special case of single scan using AI_End_On_End_Of_Scan */ - if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) - shutdown_ai_command(dev); -} - -static void shutdown_ai_command(struct comedi_device *dev) -{ - struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV]; - -#ifdef PCIDMA - ni_ai_drain_dma(dev); -#endif - ni_handle_fifo_dregs(dev); - get_last_sample_611x(dev); - get_last_sample_6143(dev); - - s->async->events |= COMEDI_CB_EOA; -} - -static void handle_gpct_interrupt(struct comedi_device *dev, - unsigned short counter_index) -{ -#ifdef PCIDMA - struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s; - - s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)]; - - ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], - s); - cfc_handle_events(dev, s); -#endif -} - -static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status) -{ - struct ni_private *devpriv = dev->private; - unsigned short ack = 0; - - if (a_status & AI_SC_TC_St) - ack |= AI_SC_TC_Interrupt_Ack; - if (a_status & AI_START1_St) - ack |= AI_START1_Interrupt_Ack; - if (a_status & AI_START_St) - ack |= AI_START_Interrupt_Ack; - if (a_status & AI_STOP_St) - /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */ - ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */; - if (ack) - devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register); -} - -static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, - unsigned ai_mite_status) -{ - struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV]; - - /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */ - if (s->type == COMEDI_SUBD_UNUSED) - return; - -#ifdef PCIDMA - if (ai_mite_status & CHSR_LINKC) - ni_sync_ai_dma(dev); - - if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | - CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | - CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { - printk - ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n", - ai_mite_status); - s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; - /* disable_irq(dev->irq); */ - } -#endif - - /* test for all uncommon interrupt events at the same time */ - if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St | - AI_SC_TC_St | AI_START1_St)) { - if (status == 0xffff) { - printk - ("ni_mio_common: a_status=0xffff. Card removed?\n"); - /* we probably aren't even running a command now, - * so it's a good idea to be careful. */ - if (comedi_is_subdevice_running(s)) { - s->async->events |= - COMEDI_CB_ERROR | COMEDI_CB_EOA; - cfc_handle_events(dev, s); - } - return; - } - if (status & (AI_Overrun_St | AI_Overflow_St | - AI_SC_TC_Error_St)) { - printk("ni_mio_common: ai error a_status=%04x\n", - status); - - shutdown_ai_command(dev); - - s->async->events |= COMEDI_CB_ERROR; - if (status & (AI_Overrun_St | AI_Overflow_St)) - s->async->events |= COMEDI_CB_OVERFLOW; - - cfc_handle_events(dev, s); - return; - } - if (status & AI_SC_TC_St) { - if (!devpriv->ai_continuous) - shutdown_ai_command(dev); - } - } -#ifndef PCIDMA - if (status & AI_FIFO_Half_Full_St) { - int i; - static const int timeout = 10; - /* pcmcia cards (at least 6036) seem to stop producing interrupts if we - *fail to get the fifo less than half full, so loop to be sure.*/ - for (i = 0; i < timeout; ++i) { - ni_handle_fifo_half_full(dev); - if ((devpriv->stc_readw(dev, - AI_Status_1_Register) & - AI_FIFO_Half_Full_St) == 0) - break; - } - } -#endif /* !PCIDMA */ - - if ((status & AI_STOP_St)) - ni_handle_eos(dev, s); - - cfc_handle_events(dev, s); -} - -static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) -{ - struct ni_private *devpriv = dev->private; - unsigned short ack = 0; - - if (b_status & AO_BC_TC_St) - ack |= AO_BC_TC_Interrupt_Ack; - if (b_status & AO_Overrun_St) - ack |= AO_Error_Interrupt_Ack; - if (b_status & AO_START_St) - ack |= AO_START_Interrupt_Ack; - if (b_status & AO_START1_St) - ack |= AO_START1_Interrupt_Ack; - if (b_status & AO_UC_TC_St) - ack |= AO_UC_TC_Interrupt_Ack; - if (b_status & AO_UI2_TC_St) - ack |= AO_UI2_TC_Interrupt_Ack; - if (b_status & AO_UPDATE_St) - ack |= AO_UPDATE_Interrupt_Ack; - if (ack) - devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register); -} - -static void handle_b_interrupt(struct comedi_device *dev, - unsigned short b_status, unsigned ao_mite_status) -{ - struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV]; - /* unsigned short ack=0; */ - -#ifdef PCIDMA - /* Currently, mite.c requires us to handle LINKC */ - if (ao_mite_status & CHSR_LINKC) - mite_handle_b_linkc(devpriv->mite, dev); - - if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | - CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | - CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { - printk - ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n", - ao_mite_status); - s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; - } -#endif - - if (b_status == 0xffff) - return; - if (b_status & AO_Overrun_St) { - printk - ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n", - b_status, devpriv->stc_readw(dev, AO_Status_2_Register)); - s->async->events |= COMEDI_CB_OVERFLOW; - } - - if (b_status & AO_BC_TC_St) - s->async->events |= COMEDI_CB_EOA; - -#ifndef PCIDMA - if (b_status & AO_FIFO_Request_St) { - int ret; - - ret = ni_ao_fifo_half_empty(dev, s); - if (!ret) { - printk("ni_mio_common: AO buffer underrun\n"); - ni_set_bits(dev, Interrupt_B_Enable_Register, - AO_FIFO_Interrupt_Enable | - AO_Error_Interrupt_Enable, 0); - s->async->events |= COMEDI_CB_OVERFLOW; - } - } -#endif - - cfc_handle_events(dev, s); -} #ifndef PCIDMA static void ni_ao_fifo_load(struct comedi_device *dev, struct comedi_subdevice *s, int n) { - const struct ni_board_struct *board = comedi_board(dev); + struct ni_private *devpriv = dev->private; struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; int chan; @@ -1155,10 +1144,10 @@ static void ni_ao_fifo_load(struct comedi_device *dev, range = CR_RANGE(cmd->chanlist[chan]); - if (board->reg_type & ni_reg_6xxx_mask) { + if (devpriv->is_6xxx) { packed_data = d & 0xffff; /* 6711 only has 16 bit wide ao fifo */ - if (board->reg_type != ni_reg_6711) { + if (!devpriv->is_6711) { err &= comedi_buf_get(s, &d); if (err == 0) break; @@ -1166,9 +1155,9 @@ static void ni_ao_fifo_load(struct comedi_device *dev, i++; packed_data |= (d << 16) & 0xffff0000; } - ni_writel(packed_data, DAC_FIFO_Data_611x); + ni_writel(dev, packed_data, DAC_FIFO_Data_611x); } else { - ni_writew(d, DAC_FIFO_Data); + ni_writew(dev, d, DAC_FIFO_Data); } chan++; chan %= cmd->chanlist_len; @@ -1225,8 +1214,8 @@ static int ni_ao_prep_fifo(struct comedi_device *dev, int n; /* reset fifo */ - devpriv->stc_writew(dev, 1, DAC_FIFO_Clear); - if (board->reg_type & ni_reg_6xxx_mask) + ni_stc_writew(dev, 1, DAC_FIFO_Clear); + if (devpriv->is_6xxx) ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); /* load some data */ @@ -1246,17 +1235,16 @@ static int ni_ao_prep_fifo(struct comedi_device *dev, static void ni_ai_fifo_read(struct comedi_device *dev, struct comedi_subdevice *s, int n) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; struct comedi_async *async = s->async; int i; - if (board->reg_type == ni_reg_611x) { + if (devpriv->is_611x) { unsigned short data[2]; u32 dl; for (i = 0; i < n / 2; i++) { - dl = ni_readl(ADC_FIFO_Data_611x); + dl = ni_readl(dev, ADC_FIFO_Data_611x); /* This may get the hi/lo data in the wrong order */ data[0] = (dl >> 16) & 0xffff; data[1] = dl & 0xffff; @@ -1264,17 +1252,17 @@ static void ni_ai_fifo_read(struct comedi_device *dev, } /* Check if there's a single sample stuck in the FIFO */ if (n % 2) { - dl = ni_readl(ADC_FIFO_Data_611x); + dl = ni_readl(dev, ADC_FIFO_Data_611x); data[0] = dl & 0xffff; cfc_write_to_buffer(s, data[0]); } - } else if (board->reg_type == ni_reg_6143) { + } else if (devpriv->is_6143) { unsigned short data[2]; u32 dl; /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */ for (i = 0; i < n / 2; i++) { - dl = ni_readl(AIFIFO_Data_6143); + dl = ni_readl(dev, AIFIFO_Data_6143); data[0] = (dl >> 16) & 0xffff; data[1] = dl & 0xffff; @@ -1282,21 +1270,23 @@ static void ni_ai_fifo_read(struct comedi_device *dev, } if (n % 2) { /* Assume there is a single sample stuck in the FIFO */ - ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ - dl = ni_readl(AIFIFO_Data_6143); + /* Get stranded sample into FIFO */ + ni_writel(dev, 0x01, AIFIFO_Control_6143); + dl = ni_readl(dev, AIFIFO_Data_6143); data[0] = (dl >> 16) & 0xffff; cfc_write_to_buffer(s, data[0]); } } else { if (n > sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0])) { - comedi_error(dev, "bug! ai_fifo_buffer too small"); + dev_err(dev->class_dev, + "bug! ai_fifo_buffer too small\n"); async->events |= COMEDI_CB_ERROR; return; } for (i = 0; i < n; i++) { devpriv->ai_fifo_buffer[i] = - ni_readw(ADC_FIFO_Data_Register); + ni_readw(dev, ADC_FIFO_Data_Register); } cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, n * @@ -1307,7 +1297,7 @@ static void ni_ai_fifo_read(struct comedi_device *dev, static void ni_handle_fifo_half_full(struct comedi_device *dev) { const struct ni_board_struct *board = comedi_board(dev); - struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV]; + struct comedi_subdevice *s = dev->read_subdev; int n; n = board->ai_fifo_depth / 2; @@ -1316,70 +1306,32 @@ static void ni_handle_fifo_half_full(struct comedi_device *dev) } #endif -#ifdef PCIDMA -static int ni_ai_drain_dma(struct comedi_device *dev) -{ - struct ni_private *devpriv = dev->private; - int i; - static const int timeout = 10000; - unsigned long flags; - int retval = 0; - - spin_lock_irqsave(&devpriv->mite_channel_lock, flags); - if (devpriv->ai_mite_chan) { - for (i = 0; i < timeout; i++) { - if ((devpriv->stc_readw(dev, - AI_Status_1_Register) & - AI_FIFO_Empty_St) - && mite_bytes_in_transit(devpriv->ai_mite_chan) == - 0) - break; - udelay(5); - } - if (i == timeout) { - printk("ni_mio_common: wait for dma drain timed out\n"); - printk - ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n", - mite_bytes_in_transit(devpriv->ai_mite_chan), - devpriv->stc_readw(dev, AI_Status_1_Register)); - retval = -1; - } - } - spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); - - ni_sync_ai_dma(dev); - - return retval; -} -#endif /* Empties the AI fifo */ static void ni_handle_fifo_dregs(struct comedi_device *dev) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV]; + struct comedi_subdevice *s = dev->read_subdev; unsigned short data[2]; u32 dl; unsigned short fifo_empty; int i; - if (board->reg_type == ni_reg_611x) { - while ((devpriv->stc_readw(dev, - AI_Status_1_Register) & + if (devpriv->is_611x) { + while ((ni_stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St) == 0) { - dl = ni_readl(ADC_FIFO_Data_611x); + dl = ni_readl(dev, ADC_FIFO_Data_611x); /* This may get the hi/lo data in the wrong order */ data[0] = (dl >> 16); data[1] = (dl & 0xffff); cfc_write_array_to_buffer(s, data, sizeof(data)); } - } else if (board->reg_type == ni_reg_6143) { + } else if (devpriv->is_6143) { i = 0; - while (ni_readl(AIFIFO_Status_6143) & 0x04) { - dl = ni_readl(AIFIFO_Data_6143); + while (ni_readl(dev, AIFIFO_Status_6143) & 0x04) { + dl = ni_readl(dev, AIFIFO_Data_6143); /* This may get the hi/lo data in the wrong order */ data[0] = (dl >> 16); @@ -1388,30 +1340,29 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev) i += 2; } /* Check if stranded sample is present */ - if (ni_readl(AIFIFO_Status_6143) & 0x01) { - ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ - dl = ni_readl(AIFIFO_Data_6143); + if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) { + /* Get stranded sample into FIFO */ + ni_writel(dev, 0x01, AIFIFO_Control_6143); + dl = ni_readl(dev, AIFIFO_Data_6143); data[0] = (dl >> 16) & 0xffff; cfc_write_to_buffer(s, data[0]); } } else { - fifo_empty = - devpriv->stc_readw(dev, - AI_Status_1_Register) & AI_FIFO_Empty_St; + fifo_empty = ni_stc_readw(dev, AI_Status_1_Register) & + AI_FIFO_Empty_St; while (fifo_empty == 0) { for (i = 0; i < sizeof(devpriv->ai_fifo_buffer) / sizeof(devpriv->ai_fifo_buffer[0]); i++) { - fifo_empty = - devpriv->stc_readw(dev, - AI_Status_1_Register) & - AI_FIFO_Empty_St; + fifo_empty = ni_stc_readw(dev, + AI_Status_1_Register) & + AI_FIFO_Empty_St; if (fifo_empty) break; devpriv->ai_fifo_buffer[i] = - ni_readw(ADC_FIFO_Data_Register); + ni_readw(dev, ADC_FIFO_Data_Register); } cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer, i * @@ -1423,18 +1374,17 @@ static void ni_handle_fifo_dregs(struct comedi_device *dev) static void get_last_sample_611x(struct comedi_device *dev) { - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv __maybe_unused = dev->private; - struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV]; + struct ni_private *devpriv = dev->private; + struct comedi_subdevice *s = dev->read_subdev; unsigned short data; u32 dl; - if (board->reg_type != ni_reg_611x) + if (!devpriv->is_611x) return; /* Check if there's a single sample stuck in the FIFO */ - if (ni_readb(XXX_Status) & 0x80) { - dl = ni_readl(ADC_FIFO_Data_611x); + if (ni_readb(dev, XXX_Status) & 0x80) { + dl = ni_readl(dev, ADC_FIFO_Data_611x); data = (dl & 0xffff); cfc_write_to_buffer(s, data); } @@ -1442,19 +1392,19 @@ static void get_last_sample_611x(struct comedi_device *dev) static void get_last_sample_6143(struct comedi_device *dev) { - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv __maybe_unused = dev->private; - struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV]; + struct ni_private *devpriv = dev->private; + struct comedi_subdevice *s = dev->read_subdev; unsigned short data; u32 dl; - if (board->reg_type != ni_reg_6143) + if (!devpriv->is_6143) return; /* Check if there's a single sample stuck in the FIFO */ - if (ni_readl(AIFIFO_Status_6143) & 0x01) { - ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ - dl = ni_readl(AIFIFO_Data_6143); + if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) { + /* Get stranded sample into FIFO */ + ni_writel(dev, 0x01, AIFIFO_Control_6143); + dl = ni_readl(dev, AIFIFO_Data_6143); /* This may get the hi/lo data in the wrong order */ data = (dl >> 16) & 0xffff; @@ -1462,6 +1412,232 @@ static void get_last_sample_6143(struct comedi_device *dev) } } +static void shutdown_ai_command(struct comedi_device *dev) +{ + struct comedi_subdevice *s = dev->read_subdev; + +#ifdef PCIDMA + ni_ai_drain_dma(dev); +#endif + ni_handle_fifo_dregs(dev); + get_last_sample_611x(dev); + get_last_sample_6143(dev); + + s->async->events |= COMEDI_CB_EOA; +} + +static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s) +{ + struct ni_private *devpriv = dev->private; + + if (devpriv->aimode == AIMODE_SCAN) { +#ifdef PCIDMA + static const int timeout = 10; + int i; + + for (i = 0; i < timeout; i++) { + ni_sync_ai_dma(dev); + if ((s->async->events & COMEDI_CB_EOS)) + break; + udelay(1); + } +#else + ni_handle_fifo_dregs(dev); + s->async->events |= COMEDI_CB_EOS; +#endif + } + /* handle special case of single scan using AI_End_On_End_Of_Scan */ + if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) + shutdown_ai_command(dev); +} + +static void handle_gpct_interrupt(struct comedi_device *dev, + unsigned short counter_index) +{ +#ifdef PCIDMA + struct ni_private *devpriv = dev->private; + struct comedi_subdevice *s; + + s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)]; + + ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], + s); + cfc_handle_events(dev, s); +#endif +} + +static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status) +{ + unsigned short ack = 0; + + if (a_status & AI_SC_TC_St) + ack |= AI_SC_TC_Interrupt_Ack; + if (a_status & AI_START1_St) + ack |= AI_START1_Interrupt_Ack; + if (a_status & AI_START_St) + ack |= AI_START_Interrupt_Ack; + if (a_status & AI_STOP_St) + /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */ + ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */; + if (ack) + ni_stc_writew(dev, ack, Interrupt_A_Ack_Register); +} + +static void handle_a_interrupt(struct comedi_device *dev, unsigned short status, + unsigned ai_mite_status) +{ + struct comedi_subdevice *s = dev->read_subdev; + struct comedi_cmd *cmd = &s->async->cmd; + + /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */ + if (s->type == COMEDI_SUBD_UNUSED) + return; + +#ifdef PCIDMA + if (ai_mite_status & CHSR_LINKC) + ni_sync_ai_dma(dev); + + if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | + CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | + CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { + dev_err(dev->class_dev, + "unknown mite interrupt (ai_mite_status=%08x)\n", + ai_mite_status); + s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; + /* disable_irq(dev->irq); */ + } +#endif + + /* test for all uncommon interrupt events at the same time */ + if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St | + AI_SC_TC_St | AI_START1_St)) { + if (status == 0xffff) { + dev_err(dev->class_dev, "Card removed?\n"); + /* we probably aren't even running a command now, + * so it's a good idea to be careful. */ + if (comedi_is_subdevice_running(s)) { + s->async->events |= + COMEDI_CB_ERROR | COMEDI_CB_EOA; + cfc_handle_events(dev, s); + } + return; + } + if (status & (AI_Overrun_St | AI_Overflow_St | + AI_SC_TC_Error_St)) { + dev_err(dev->class_dev, "ai error a_status=%04x\n", + status); + + shutdown_ai_command(dev); + + s->async->events |= COMEDI_CB_ERROR; + if (status & (AI_Overrun_St | AI_Overflow_St)) + s->async->events |= COMEDI_CB_OVERFLOW; + + cfc_handle_events(dev, s); + return; + } + if (status & AI_SC_TC_St) { + if (cmd->stop_src == TRIG_COUNT) + shutdown_ai_command(dev); + } + } +#ifndef PCIDMA + if (status & AI_FIFO_Half_Full_St) { + int i; + static const int timeout = 10; + /* pcmcia cards (at least 6036) seem to stop producing interrupts if we + *fail to get the fifo less than half full, so loop to be sure.*/ + for (i = 0; i < timeout; ++i) { + ni_handle_fifo_half_full(dev); + if ((ni_stc_readw(dev, AI_Status_1_Register) & + AI_FIFO_Half_Full_St) == 0) + break; + } + } +#endif /* !PCIDMA */ + + if ((status & AI_STOP_St)) + ni_handle_eos(dev, s); + + cfc_handle_events(dev, s); +} + +static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status) +{ + unsigned short ack = 0; + + if (b_status & AO_BC_TC_St) + ack |= AO_BC_TC_Interrupt_Ack; + if (b_status & AO_Overrun_St) + ack |= AO_Error_Interrupt_Ack; + if (b_status & AO_START_St) + ack |= AO_START_Interrupt_Ack; + if (b_status & AO_START1_St) + ack |= AO_START1_Interrupt_Ack; + if (b_status & AO_UC_TC_St) + ack |= AO_UC_TC_Interrupt_Ack; + if (b_status & AO_UI2_TC_St) + ack |= AO_UI2_TC_Interrupt_Ack; + if (b_status & AO_UPDATE_St) + ack |= AO_UPDATE_Interrupt_Ack; + if (ack) + ni_stc_writew(dev, ack, Interrupt_B_Ack_Register); +} + +static void handle_b_interrupt(struct comedi_device *dev, + unsigned short b_status, unsigned ao_mite_status) +{ + struct comedi_subdevice *s = dev->write_subdev; + /* unsigned short ack=0; */ + +#ifdef PCIDMA + /* Currently, mite.c requires us to handle LINKC */ + if (ao_mite_status & CHSR_LINKC) { + struct ni_private *devpriv = dev->private; + + mite_handle_b_linkc(devpriv->mite, dev); + } + + if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY | + CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR | + CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) { + dev_err(dev->class_dev, + "unknown mite interrupt (ao_mite_status=%08x)\n", + ao_mite_status); + s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR; + } +#endif + + if (b_status == 0xffff) + return; + if (b_status & AO_Overrun_St) { + dev_err(dev->class_dev, + "AO FIFO underrun status=0x%04x status2=0x%04x\n", + b_status, ni_stc_readw(dev, AO_Status_2_Register)); + s->async->events |= COMEDI_CB_OVERFLOW; + } + + if (b_status & AO_BC_TC_St) + s->async->events |= COMEDI_CB_EOA; + +#ifndef PCIDMA + if (b_status & AO_FIFO_Request_St) { + int ret; + + ret = ni_ao_fifo_half_empty(dev, s); + if (!ret) { + dev_err(dev->class_dev, "AO buffer underrun\n"); + ni_set_bits(dev, Interrupt_B_Enable_Register, + AO_FIFO_Interrupt_Enable | + AO_Error_Interrupt_Enable, 0); + s->async->events |= COMEDI_CB_OVERFLOW; + } + } +#endif + + cfc_handle_events(dev, s); +} + static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s, void *data, unsigned int num_bytes, unsigned int chan_index) @@ -1494,16 +1670,14 @@ static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s, static int ni_ai_setup_MITE_dma(struct comedi_device *dev) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV]; + struct comedi_subdevice *s = dev->read_subdev; int retval; unsigned long flags; retval = ni_request_ai_mite_channel(dev); if (retval) return retval; -/* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */ /* write alloc the entire buffer */ comedi_buf_write_alloc(s, s->async->prealloc_bufsz); @@ -1514,18 +1688,13 @@ static int ni_ai_setup_MITE_dma(struct comedi_device *dev) return -EIO; } - switch (board->reg_type) { - case ni_reg_611x: - case ni_reg_6143: + if (devpriv->is_611x || devpriv->is_6143) mite_prep_dma(devpriv->ai_mite_chan, 32, 16); - break; - case ni_reg_628x: + else if (devpriv->is_628x) mite_prep_dma(devpriv->ai_mite_chan, 32, 32); - break; - default: + else mite_prep_dma(devpriv->ai_mite_chan, 16, 16); - break; - } + /*start the MITE */ mite_dma_arm(devpriv->ai_mite_chan); spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); @@ -1535,9 +1704,8 @@ static int ni_ai_setup_MITE_dma(struct comedi_device *dev) static int ni_ao_setup_MITE_dma(struct comedi_device *dev) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV]; + struct comedi_subdevice *s = dev->write_subdev; int retval; unsigned long flags; @@ -1550,7 +1718,7 @@ static int ni_ao_setup_MITE_dma(struct comedi_device *dev) spin_lock_irqsave(&devpriv->mite_channel_lock, flags); if (devpriv->ao_mite_chan) { - if (board->reg_type & (ni_reg_611x | ni_reg_6713)) { + if (devpriv->is_611x || devpriv->is_6713) { mite_prep_dma(devpriv->ao_mite_chan, 32, 32); } else { /* doing 32 instead of 16 bit wide transfers from memory @@ -1575,13 +1743,12 @@ static int ni_ao_setup_MITE_dma(struct comedi_device *dev) static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; ni_release_ai_mite_channel(dev); /* ai configuration */ - devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset, - Joint_Reset_Register); + ni_stc_writew(dev, AI_Configuration_Start | AI_Reset, + Joint_Reset_Register); ni_set_bits(dev, Interrupt_A_Enable_Register, AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable | @@ -1591,56 +1758,58 @@ static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) ni_clear_ai_fifo(dev); - if (board->reg_type != ni_reg_6143) - ni_writeb(0, Misc_Command); + if (!devpriv->is_6143) + ni_writeb(dev, 0, Misc_Command); - devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */ - devpriv->stc_writew(dev, - AI_Start_Stop | AI_Mode_1_Reserved - /*| AI_Trigger_Once */ , - AI_Mode_1_Register); - devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register); + ni_stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */ + ni_stc_writew(dev, AI_Start_Stop | AI_Mode_1_Reserved + /*| AI_Trigger_Once */, + AI_Mode_1_Register); + ni_stc_writew(dev, 0x0000, AI_Mode_2_Register); /* generate FIFO interrupts on non-empty */ - devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register); - if (board->reg_type == ni_reg_611x) { - devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width | - AI_SOC_Polarity | - AI_LOCALMUX_CLK_Pulse_Width, - AI_Personal_Register); - devpriv->stc_writew(dev, - AI_SCAN_IN_PROG_Output_Select(3) | - AI_EXTMUX_CLK_Output_Select(0) | - AI_LOCALMUX_CLK_Output_Select(2) | - AI_SC_TC_Output_Select(3) | - AI_CONVERT_Output_Select - (AI_CONVERT_Output_Enable_High), - AI_Output_Control_Register); - } else if (board->reg_type == ni_reg_6143) { - devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width | - AI_SOC_Polarity | - AI_LOCALMUX_CLK_Pulse_Width, - AI_Personal_Register); - devpriv->stc_writew(dev, - AI_SCAN_IN_PROG_Output_Select(3) | - AI_EXTMUX_CLK_Output_Select(0) | - AI_LOCALMUX_CLK_Output_Select(2) | - AI_SC_TC_Output_Select(3) | - AI_CONVERT_Output_Select - (AI_CONVERT_Output_Enable_Low), - AI_Output_Control_Register); + ni_stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register); + if (devpriv->is_611x) { + ni_stc_writew(dev, + AI_SHIFTIN_Pulse_Width | + AI_SOC_Polarity | + AI_LOCALMUX_CLK_Pulse_Width, + AI_Personal_Register); + ni_stc_writew(dev, + AI_SCAN_IN_PROG_Output_Select(3) | + AI_EXTMUX_CLK_Output_Select(0) | + AI_LOCALMUX_CLK_Output_Select(2) | + AI_SC_TC_Output_Select(3) | + AI_CONVERT_Output_Select + (AI_CONVERT_Output_Enable_High), + AI_Output_Control_Register); + } else if (devpriv->is_6143) { + ni_stc_writew(dev, AI_SHIFTIN_Pulse_Width | + AI_SOC_Polarity | + AI_LOCALMUX_CLK_Pulse_Width, + AI_Personal_Register); + ni_stc_writew(dev, + AI_SCAN_IN_PROG_Output_Select(3) | + AI_EXTMUX_CLK_Output_Select(0) | + AI_LOCALMUX_CLK_Output_Select(2) | + AI_SC_TC_Output_Select(3) | + AI_CONVERT_Output_Select + (AI_CONVERT_Output_Enable_Low), + AI_Output_Control_Register); } else { unsigned ai_output_control_bits; - devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width | - AI_SOC_Polarity | - AI_CONVERT_Pulse_Width | - AI_LOCALMUX_CLK_Pulse_Width, - AI_Personal_Register); + + ni_stc_writew(dev, + AI_SHIFTIN_Pulse_Width | + AI_SOC_Polarity | + AI_CONVERT_Pulse_Width | + AI_LOCALMUX_CLK_Pulse_Width, + AI_Personal_Register); ai_output_control_bits = AI_SCAN_IN_PROG_Output_Select(3) | AI_EXTMUX_CLK_Output_Select(0) | AI_LOCALMUX_CLK_Output_Select(2) | AI_SC_TC_Output_Select(3); - if (board->reg_type == ni_reg_622x) + if (devpriv->is_622x) ai_output_control_bits |= AI_CONVERT_Output_Select (AI_CONVERT_Output_Enable_High); @@ -1648,8 +1817,8 @@ static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) ai_output_control_bits |= AI_CONVERT_Output_Select (AI_CONVERT_Output_Enable_Low); - devpriv->stc_writew(dev, ai_output_control_bits, - AI_Output_Control_Register); + ni_stc_writew(dev, ai_output_control_bits, + AI_Output_Control_Register); } /* the following registers should not be changed, because there * are no backup registers in devpriv. If you want to change @@ -1659,9 +1828,17 @@ static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s) * AI_Personal_Register * AI_Output_Control_Register */ - devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */ - - devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); + ni_stc_writew(dev, + AI_SC_TC_Error_Confirm | + AI_START_Interrupt_Ack | + AI_START2_Interrupt_Ack | + AI_START1_Interrupt_Ack | + AI_SC_TC_Interrupt_Ack | + AI_Error_Interrupt_Ack | + AI_STOP_Interrupt_Ack, + Interrupt_A_Ack_Register); /* clear interrupts */ + + ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); return 0; } @@ -1678,127 +1855,26 @@ static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s) #else ni_sync_ai_dma(dev); #endif - count = s->async->buf_write_count - s->async->buf_read_count; + count = comedi_buf_n_bytes_ready(s); spin_unlock_irqrestore(&dev->spinlock, flags); return count; } -static int ni_ai_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, struct comedi_insn *insn, - unsigned int *data) -{ - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv = dev->private; - int i, n; - const unsigned int mask = (1 << board->adbits) - 1; - unsigned signbits; - unsigned short d; - unsigned long dl; - - ni_load_channelgain_list(dev, 1, &insn->chanspec); - - ni_clear_ai_fifo(dev); - - signbits = devpriv->ai_offset[0]; - if (board->reg_type == ni_reg_611x) { - for (n = 0; n < num_adc_stages_611x; n++) { - devpriv->stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); - udelay(1); - } - for (n = 0; n < insn->n; n++) { - devpriv->stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); - /* The 611x has screwy 32-bit FIFOs. */ - d = 0; - for (i = 0; i < NI_TIMEOUT; i++) { - if (ni_readb(XXX_Status) & 0x80) { - d = (ni_readl(ADC_FIFO_Data_611x) >> 16) - & 0xffff; - break; - } - if (!(devpriv->stc_readw(dev, - AI_Status_1_Register) & - AI_FIFO_Empty_St)) { - d = ni_readl(ADC_FIFO_Data_611x) & - 0xffff; - break; - } - } - if (i == NI_TIMEOUT) { - printk - ("ni_mio_common: timeout in 611x ni_ai_insn_read\n"); - return -ETIME; - } - d += signbits; - data[n] = d; - } - } else if (board->reg_type == ni_reg_6143) { - for (n = 0; n < insn->n; n++) { - devpriv->stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); - - /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */ - dl = 0; - for (i = 0; i < NI_TIMEOUT; i++) { - if (ni_readl(AIFIFO_Status_6143) & 0x01) { - ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */ - dl = ni_readl(AIFIFO_Data_6143); - break; - } - } - if (i == NI_TIMEOUT) { - printk - ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n"); - return -ETIME; - } - data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF; - } - } else { - for (n = 0; n < insn->n; n++) { - devpriv->stc_writew(dev, AI_CONVERT_Pulse, - AI_Command_1_Register); - for (i = 0; i < NI_TIMEOUT; i++) { - if (!(devpriv->stc_readw(dev, - AI_Status_1_Register) & - AI_FIFO_Empty_St)) - break; - } - if (i == NI_TIMEOUT) { - printk - ("ni_mio_common: timeout in ni_ai_insn_read\n"); - return -ETIME; - } - if (board->reg_type & ni_reg_m_series_mask) { - data[n] = - ni_readl(M_Offset_AI_FIFO_Data) & mask; - } else { - d = ni_readw(ADC_FIFO_Data_Register); - d += signbits; /* subtle: needs to be short addition */ - data[n] = d; - } - } - } - return insn->n; -} - static void ni_prime_channelgain_list(struct comedi_device *dev) { - struct ni_private *devpriv = dev->private; int i; - devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register); + ni_stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register); for (i = 0; i < NI_TIMEOUT; ++i) { - if (!(devpriv->stc_readw(dev, - AI_Status_1_Register) & + if (!(ni_stc_readw(dev, AI_Status_1_Register) & AI_FIFO_Empty_St)) { - devpriv->stc_writew(dev, 1, ADC_FIFO_Clear); + ni_stc_writew(dev, 1, ADC_FIFO_Clear); return; } udelay(1); } - printk("ni_mio_common: timeout loading channel/gain list\n"); + dev_err(dev->class_dev, "timeout loading channel/gain list\n"); } static void ni_m_series_load_channelgain_list(struct comedi_device *dev, @@ -1809,15 +1885,14 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, struct ni_private *devpriv = dev->private; unsigned int chan, range, aref; unsigned int i; - unsigned offset; unsigned int dither; unsigned range_code; - devpriv->stc_writew(dev, 1, Configuration_Memory_Clear); + ni_stc_writew(dev, 1, Configuration_Memory_Clear); -/* offset = 1 << (board->adbits - 1); */ if ((list[0] & CR_ALT_SOURCE)) { unsigned bypass_bits; + chan = CR_CHAN(list[0]); range = CR_RANGE(list[0]); range_code = ni_gainlkup[board->gainlkup][range]; @@ -1835,20 +1910,20 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, bypass_bits |= MSeries_AI_Bypass_Dither_Bit; /* don't use 2's complement encoding */ bypass_bits |= MSeries_AI_Bypass_Polarity_Bit; - ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass); + ni_writel(dev, bypass_bits, M_Offset_AI_Config_FIFO_Bypass); } else { - ni_writel(0, M_Offset_AI_Config_FIFO_Bypass); + ni_writel(dev, 0, M_Offset_AI_Config_FIFO_Bypass); } - offset = 0; for (i = 0; i < n_chan; i++) { unsigned config_bits = 0; + chan = CR_CHAN(list[i]); aref = CR_AREF(list[i]); range = CR_RANGE(list[i]); dither = ((list[i] & CR_ALT_FILTER) != 0); range_code = ni_gainlkup[board->gainlkup][range]; - devpriv->ai_offset[i] = offset; + devpriv->ai_offset[i] = 0; switch (aref) { case AREF_DIFF: config_bits |= @@ -1875,7 +1950,7 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, config_bits |= MSeries_AI_Config_Dither_Bit; /* don't use 2's complement encoding */ config_bits |= MSeries_AI_Config_Polarity_Bit; - ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data); + ni_writew(dev, config_bits, M_Offset_AI_Config_FIFO_Data); } ni_prime_channelgain_list(dev); } @@ -1910,22 +1985,22 @@ static void ni_m_series_load_channelgain_list(struct comedi_device *dev, * valid channels are 0-3 */ static void ni_load_channelgain_list(struct comedi_device *dev, + struct comedi_subdevice *s, unsigned int n_chan, unsigned int *list) { const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; + unsigned int offset = (s->maxdata + 1) >> 1; unsigned int chan, range, aref; unsigned int i; unsigned int hi, lo; - unsigned offset; unsigned int dither; - if (board->reg_type & ni_reg_m_series_mask) { + if (devpriv->is_m_series) { ni_m_series_load_channelgain_list(dev, n_chan, list); return; } - if (n_chan == 1 && (board->reg_type != ni_reg_611x) - && (board->reg_type != ni_reg_6143)) { + if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) { if (devpriv->changain_state && devpriv->changain_spec == list[0]) { /* ready to go. */ @@ -1937,61 +2012,58 @@ static void ni_load_channelgain_list(struct comedi_device *dev, devpriv->changain_state = 0; } - devpriv->stc_writew(dev, 1, Configuration_Memory_Clear); + ni_stc_writew(dev, 1, Configuration_Memory_Clear); /* Set up Calibration mode if required */ - if (board->reg_type == ni_reg_6143) { + if (devpriv->is_6143) { if ((list[0] & CR_ALT_SOURCE) && !devpriv->ai_calib_source_enabled) { /* Strobe Relay enable bit */ - ni_writew(devpriv->ai_calib_source | - Calibration_Channel_6143_RelayOn, + ni_writew(dev, devpriv->ai_calib_source | + Calibration_Channel_6143_RelayOn, Calibration_Channel_6143); - ni_writew(devpriv->ai_calib_source, + ni_writew(dev, devpriv->ai_calib_source, Calibration_Channel_6143); devpriv->ai_calib_source_enabled = 1; msleep_interruptible(100); /* Allow relays to change */ } else if (!(list[0] & CR_ALT_SOURCE) && devpriv->ai_calib_source_enabled) { /* Strobe Relay disable bit */ - ni_writew(devpriv->ai_calib_source | - Calibration_Channel_6143_RelayOff, + ni_writew(dev, devpriv->ai_calib_source | + Calibration_Channel_6143_RelayOff, Calibration_Channel_6143); - ni_writew(devpriv->ai_calib_source, + ni_writew(dev, devpriv->ai_calib_source, Calibration_Channel_6143); devpriv->ai_calib_source_enabled = 0; msleep_interruptible(100); /* Allow relays to change */ } } - offset = 1 << (board->adbits - 1); for (i = 0; i < n_chan; i++) { - if ((board->reg_type != ni_reg_6143) - && (list[i] & CR_ALT_SOURCE)) { + if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE)) chan = devpriv->ai_calib_source; - } else { + else chan = CR_CHAN(list[i]); - } aref = CR_AREF(list[i]); range = CR_RANGE(list[i]); dither = ((list[i] & CR_ALT_FILTER) != 0); /* fix the external/internal range differences */ range = ni_gainlkup[board->gainlkup][range]; - if (board->reg_type == ni_reg_611x) + if (devpriv->is_611x) devpriv->ai_offset[i] = offset; else devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset; hi = 0; if ((list[i] & CR_ALT_SOURCE)) { - if (board->reg_type == ni_reg_611x) - ni_writew(CR_CHAN(list[i]) & 0x0003, + if (devpriv->is_611x) + ni_writew(dev, CR_CHAN(list[i]) & 0x0003, Calibration_Channel_Select_611x); } else { - if (board->reg_type == ni_reg_611x) + if (devpriv->is_611x) aref = AREF_DIFF; - else if (board->reg_type == ni_reg_6143) + else if (devpriv->is_6143) aref = AREF_OTHER; switch (aref) { case AREF_DIFF: @@ -2009,33 +2081,132 @@ static void ni_load_channelgain_list(struct comedi_device *dev, } hi |= AI_CONFIG_CHANNEL(chan); - ni_writew(hi, Configuration_Memory_High); + ni_writew(dev, hi, Configuration_Memory_High); - if (board->reg_type != ni_reg_6143) { + if (!devpriv->is_6143) { lo = range; if (i == n_chan - 1) lo |= AI_LAST_CHANNEL; if (dither) lo |= AI_DITHER; - ni_writew(lo, Configuration_Memory_Low); + ni_writew(dev, lo, Configuration_Memory_Low); } } /* prime the channel/gain list */ - if ((board->reg_type != ni_reg_611x) - && (board->reg_type != ni_reg_6143)) { + if (!devpriv->is_611x && !devpriv->is_6143) ni_prime_channelgain_list(dev); +} + +static int ni_ai_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct ni_private *devpriv = dev->private; + unsigned int mask = (s->maxdata + 1) >> 1; + int i, n; + unsigned signbits; + unsigned short d; + unsigned long dl; + + ni_load_channelgain_list(dev, s, 1, &insn->chanspec); + + ni_clear_ai_fifo(dev); + + signbits = devpriv->ai_offset[0]; + if (devpriv->is_611x) { + for (n = 0; n < num_adc_stages_611x; n++) { + ni_stc_writew(dev, AI_CONVERT_Pulse, + AI_Command_1_Register); + udelay(1); + } + for (n = 0; n < insn->n; n++) { + ni_stc_writew(dev, AI_CONVERT_Pulse, + AI_Command_1_Register); + /* The 611x has screwy 32-bit FIFOs. */ + d = 0; + for (i = 0; i < NI_TIMEOUT; i++) { + if (ni_readb(dev, XXX_Status) & 0x80) { + d = ni_readl(dev, ADC_FIFO_Data_611x); + d >>= 16; + d &= 0xffff; + break; + } + if (!(ni_stc_readw(dev, AI_Status_1_Register) & + AI_FIFO_Empty_St)) { + d = ni_readl(dev, ADC_FIFO_Data_611x); + d &= 0xffff; + break; + } + } + if (i == NI_TIMEOUT) { + dev_err(dev->class_dev, "%s timeout\n", + __func__); + return -ETIME; + } + d += signbits; + data[n] = d; + } + } else if (devpriv->is_6143) { + for (n = 0; n < insn->n; n++) { + ni_stc_writew(dev, AI_CONVERT_Pulse, + AI_Command_1_Register); + + /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */ + dl = 0; + for (i = 0; i < NI_TIMEOUT; i++) { + if (ni_readl(dev, AIFIFO_Status_6143) & 0x01) { + /* Get stranded sample into FIFO */ + ni_writel(dev, 0x01, + AIFIFO_Control_6143); + dl = ni_readl(dev, AIFIFO_Data_6143); + break; + } + } + if (i == NI_TIMEOUT) { + dev_err(dev->class_dev, "%s timeout\n", + __func__); + return -ETIME; + } + data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF; + } + } else { + for (n = 0; n < insn->n; n++) { + ni_stc_writew(dev, AI_CONVERT_Pulse, + AI_Command_1_Register); + for (i = 0; i < NI_TIMEOUT; i++) { + if (!(ni_stc_readw(dev, AI_Status_1_Register) & + AI_FIFO_Empty_St)) + break; + } + if (i == NI_TIMEOUT) { + dev_err(dev->class_dev, "%s timeout\n", + __func__); + return -ETIME; + } + if (devpriv->is_m_series) { + dl = ni_readl(dev, M_Offset_AI_FIFO_Data); + dl &= mask; + data[n] = dl; + } else { + d = ni_readw(dev, ADC_FIFO_Data_Register); + d += signbits; /* subtle: needs to be short addition */ + data[n] = d; + } + } } + return insn->n; } static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec, - int round_mode) + unsigned int flags) { struct ni_private *devpriv = dev->private; int divider; - switch (round_mode) { + switch (flags & TRIG_ROUND_MASK) { case TRIG_ROUND_NEAREST: default: divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns; @@ -2061,17 +2232,13 @@ static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev, unsigned num_channels) { const struct ni_board_struct *board = comedi_board(dev); + struct ni_private *devpriv = dev->private; - switch (board->reg_type) { - case ni_reg_611x: - case ni_reg_6143: - /* simultaneously-sampled inputs */ + /* simultaneously-sampled inputs */ + if (devpriv->is_611x || devpriv->is_6143) return board->ai_speed; - break; - default: - /* multiplexed inputs */ - break; - } + + /* multiplexed inputs */ return board->ai_speed * num_channels; } @@ -2095,8 +2262,7 @@ static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, TRIG_TIMER | TRIG_EXT); sources = TRIG_TIMER | TRIG_EXT; - if (board->reg_type == ni_reg_611x || - board->reg_type == ni_reg_6143) + if (devpriv->is_611x || devpriv->is_6143) sources |= TRIG_NOW; err |= cfc_check_trigger_src(&cmd->convert_src, sources); @@ -2153,8 +2319,7 @@ static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, } if (cmd->convert_src == TRIG_TIMER) { - if ((board->reg_type == ni_reg_611x) - || (board->reg_type == ni_reg_6143)) { + if (devpriv->is_611x || devpriv->is_6143) { err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); } else { err |= cfc_check_trigger_arg_min(&cmd->convert_arg, @@ -2179,7 +2344,7 @@ static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, if (cmd->stop_src == TRIG_COUNT) { unsigned int max_count = 0x01000000; - if (board->reg_type == ni_reg_611x) + if (devpriv->is_611x) max_count -= num_adc_stages_611x; err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count); err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); @@ -2198,22 +2363,17 @@ static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, cmd->scan_begin_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->scan_begin_arg, - cmd-> - flags & - TRIG_ROUND_MASK)); + cmd->flags)); if (tmp != cmd->scan_begin_arg) err++; } if (cmd->convert_src == TRIG_TIMER) { - if ((board->reg_type != ni_reg_611x) - && (board->reg_type != ni_reg_6143)) { + if (!devpriv->is_611x && !devpriv->is_6143) { tmp = cmd->convert_arg; cmd->convert_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->convert_arg, - cmd-> - flags & - TRIG_ROUND_MASK)); + cmd->flags)); if (tmp != cmd->convert_arg) err++; if (cmd->scan_begin_src == TRIG_TIMER && @@ -2232,9 +2392,25 @@ static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, return 0; } +static int ni_ai_inttrig(struct comedi_device *dev, + struct comedi_subdevice *s, + unsigned int trig_num) +{ + struct ni_private *devpriv = dev->private; + struct comedi_cmd *cmd = &s->async->cmd; + + if (trig_num != cmd->start_arg) + return -EINVAL; + + ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, + AI_Command_2_Register); + s->async->inttrig = NULL; + + return 1; +} + static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; const struct comedi_cmd *cmd = &s->async->cmd; int timer; @@ -2245,29 +2421,30 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) int interrupt_a_enable = 0; if (dev->irq == 0) { - comedi_error(dev, "cannot run command without an irq"); + dev_err(dev->class_dev, "cannot run command without an irq\n"); return -EIO; } ni_clear_ai_fifo(dev); - ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist); + ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist); /* start configuration */ - devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register); + ni_stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register); /* disable analog triggering for now, since it * interferes with the use of pfi0 */ devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable; - devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, - Analog_Trigger_Etc_Register); + ni_stc_writew(dev, devpriv->an_trig_etc_reg, + Analog_Trigger_Etc_Register); switch (cmd->start_src) { case TRIG_INT: case TRIG_NOW: - devpriv->stc_writew(dev, AI_START2_Select(0) | - AI_START1_Sync | AI_START1_Edge | - AI_START1_Select(0), - AI_Trigger_Select_Register); + ni_stc_writew(dev, + AI_START2_Select(0) | + AI_START1_Sync | AI_START1_Edge | + AI_START1_Select(0), + AI_Trigger_Select_Register); break; case TRIG_EXT: { @@ -2279,8 +2456,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) bits |= AI_START1_Polarity; if (cmd->start_arg & CR_EDGE) bits |= AI_START1_Edge; - devpriv->stc_writew(dev, bits, - AI_Trigger_Select_Register); + ni_stc_writew(dev, bits, AI_Trigger_Select_Register); break; } } @@ -2288,37 +2464,34 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) mode2 &= ~AI_Pre_Trigger; mode2 &= ~AI_SC_Initial_Load_Source; mode2 &= ~AI_SC_Reload_Mode; - devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); + ni_stc_writew(dev, mode2, AI_Mode_2_Register); - if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x) - || (board->reg_type == ni_reg_6143)) { + if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) { start_stop_select |= AI_STOP_Polarity; start_stop_select |= AI_STOP_Select(31); /* logic low */ start_stop_select |= AI_STOP_Sync; } else { start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */ } - devpriv->stc_writew(dev, start_stop_select, - AI_START_STOP_Select_Register); + ni_stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register); devpriv->ai_cmd2 = 0; switch (cmd->stop_src) { case TRIG_COUNT: stop_count = cmd->stop_arg - 1; - if (board->reg_type == ni_reg_611x) { + if (devpriv->is_611x) { /* have to take 3 stage adc pipeline into account */ stop_count += num_adc_stages_611x; } /* stage number of scans */ - devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers); + ni_stc_writel(dev, stop_count, AI_SC_Load_A_Registers); mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once; - devpriv->stc_writew(dev, mode1, AI_Mode_1_Register); + ni_stc_writew(dev, mode1, AI_Mode_1_Register); /* load SC (Scan Count) */ - devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register); + ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register); - devpriv->ai_continuous = 0; if (stop_count == 0) { devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan; interrupt_a_enable |= AI_STOP_Interrupt_Enable; @@ -2330,16 +2503,13 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) break; case TRIG_NONE: /* stage number of scans */ - devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers); + ni_stc_writel(dev, 0, AI_SC_Load_A_Registers); mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous; - devpriv->stc_writew(dev, mode1, AI_Mode_1_Register); + ni_stc_writew(dev, mode1, AI_Mode_1_Register); /* load SC (Scan Count) */ - devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register); - - devpriv->ai_continuous = 1; - + ni_stc_writew(dev, AI_SC_Load, AI_Command_1_Register); break; } @@ -2360,20 +2530,20 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) AI_STOP_Select=19 external pin (configuration mem) */ start_stop_select |= AI_START_Edge | AI_START_Sync; - devpriv->stc_writew(dev, start_stop_select, - AI_START_STOP_Select_Register); + ni_stc_writew(dev, start_stop_select, + AI_START_STOP_Select_Register); mode2 |= AI_SI_Reload_Mode(0); /* AI_SI_Initial_Load_Source=A */ mode2 &= ~AI_SI_Initial_Load_Source; /* mode2 |= AI_SC_Reload_Mode; */ - devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); + ni_stc_writew(dev, mode2, AI_Mode_2_Register); /* load SI */ timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, TRIG_ROUND_NEAREST); - devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers); - devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register); + ni_stc_writel(dev, timer, AI_SI_Load_A_Registers); + ni_stc_writew(dev, AI_SI_Load, AI_Command_1_Register); break; case TRIG_EXT: if (cmd->scan_begin_arg & CR_EDGE) @@ -2387,7 +2557,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) start_stop_select |= AI_START_Sync; start_stop_select |= AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg)); - devpriv->stc_writew(dev, start_stop_select, + ni_stc_writew(dev, start_stop_select, AI_START_STOP_Select_Register); break; } @@ -2400,31 +2570,32 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) else timer = ni_ns_to_timer(dev, cmd->convert_arg, TRIG_ROUND_NEAREST); - devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */ - devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register); + /* 0,0 does not work */ + ni_stc_writew(dev, 1, AI_SI2_Load_A_Register); + ni_stc_writew(dev, timer, AI_SI2_Load_B_Register); /* AI_SI2_Reload_Mode = alternate */ /* AI_SI2_Initial_Load_Source = A */ mode2 &= ~AI_SI2_Initial_Load_Source; mode2 |= AI_SI2_Reload_Mode; - devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); + ni_stc_writew(dev, mode2, AI_Mode_2_Register); /* AI_SI2_Load */ - devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register); + ni_stc_writew(dev, AI_SI2_Load, AI_Command_1_Register); mode2 |= AI_SI2_Reload_Mode; /* alternate */ mode2 |= AI_SI2_Initial_Load_Source; /* B */ - devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); + ni_stc_writew(dev, mode2, AI_Mode_2_Register); break; case TRIG_EXT: mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg); if ((cmd->convert_arg & CR_INVERT) == 0) mode1 |= AI_CONVERT_Source_Polarity; - devpriv->stc_writew(dev, mode1, AI_Mode_1_Register); + ni_stc_writew(dev, mode1, AI_Mode_1_Register); mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable; - devpriv->stc_writew(dev, mode2, AI_Mode_2_Register); + ni_stc_writew(dev, mode2, AI_Mode_2_Register); break; } @@ -2451,25 +2622,25 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) case AIMODE_HALF_FULL: /*generate FIFO interrupts and DMA requests on half-full */ #ifdef PCIDMA - devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E, - AI_Mode_3_Register); + ni_stc_writew(dev, AI_FIFO_Mode_HF_to_E, + AI_Mode_3_Register); #else - devpriv->stc_writew(dev, AI_FIFO_Mode_HF, - AI_Mode_3_Register); + ni_stc_writew(dev, AI_FIFO_Mode_HF, + AI_Mode_3_Register); #endif break; case AIMODE_SAMPLE: /*generate FIFO interrupts on non-empty */ - devpriv->stc_writew(dev, AI_FIFO_Mode_NE, - AI_Mode_3_Register); + ni_stc_writew(dev, AI_FIFO_Mode_NE, + AI_Mode_3_Register); break; case AIMODE_SCAN: #ifdef PCIDMA - devpriv->stc_writew(dev, AI_FIFO_Mode_NE, - AI_Mode_3_Register); + ni_stc_writew(dev, AI_FIFO_Mode_NE, + AI_Mode_3_Register); #else - devpriv->stc_writew(dev, AI_FIFO_Mode_HF, - AI_Mode_3_Register); + ni_stc_writew(dev, AI_FIFO_Mode_HF, + AI_Mode_3_Register); #endif interrupt_a_enable |= AI_STOP_Interrupt_Enable; break; @@ -2477,7 +2648,16 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) break; } - devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */ + /* clear interrupts */ + ni_stc_writew(dev, + AI_Error_Interrupt_Ack | + AI_STOP_Interrupt_Ack | + AI_START_Interrupt_Ack | + AI_START2_Interrupt_Ack | + AI_START1_Interrupt_Ack | + AI_SC_TC_Interrupt_Ack | + AI_SC_TC_Error_Confirm, + Interrupt_A_Ack_Register); ni_set_bits(dev, Interrupt_A_Enable_Register, interrupt_a_enable, 1); @@ -2489,25 +2669,26 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) } /* end configuration */ - devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); + ni_stc_writew(dev, AI_Configuration_End, Joint_Reset_Register); switch (cmd->scan_begin_src) { case TRIG_TIMER: - devpriv->stc_writew(dev, - AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | - AI_SC_Arm, AI_Command_1_Register); + ni_stc_writew(dev, + AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm, + AI_Command_1_Register); break; case TRIG_EXT: /* XXX AI_SI_Arm? */ - devpriv->stc_writew(dev, - AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | - AI_SC_Arm, AI_Command_1_Register); + ni_stc_writew(dev, + AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm, + AI_Command_1_Register); break; } #ifdef PCIDMA { int retval = ni_ai_setup_MITE_dma(dev); + if (retval) return retval; } @@ -2515,8 +2696,8 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) if (cmd->start_src == TRIG_NOW) { /* AI_START1_Pulse */ - devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, - AI_Command_2_Register); + ni_stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, + AI_Command_2_Register); s->async->inttrig = NULL; } else if (cmd->start_src == TRIG_EXT) { s->async->inttrig = NULL; @@ -2527,43 +2708,18 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) return 0; } -static int ni_ai_inttrig(struct comedi_device *dev, - struct comedi_subdevice *s, - unsigned int trig_num) -{ - struct ni_private *devpriv = dev->private; - struct comedi_cmd *cmd = &s->async->cmd; - - if (trig_num != cmd->start_arg) - return -EINVAL; - - devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2, - AI_Command_2_Register); - s->async->inttrig = NULL; - - return 1; -} - -static int ni_ai_config_analog_trig(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data); - static int ni_ai_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, struct comedi_insn *insn, unsigned int *data) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; if (insn->n < 1) return -EINVAL; switch (data[0]) { - case INSN_CONFIG_ANALOG_TRIG: - return ni_ai_config_analog_trig(dev, s, insn, data); case INSN_CONFIG_ALT_SOURCE: - if (board->reg_type & ni_reg_m_series_mask) { + if (devpriv->is_m_series) { if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask | MSeries_AI_Bypass_Cal_Sel_Neg_Mask | MSeries_AI_Bypass_Mode_Mux_Mask | @@ -2571,7 +2727,7 @@ static int ni_ai_insn_config(struct comedi_device *dev, return -EINVAL; } devpriv->ai_calib_source = data[1]; - } else if (board->reg_type == ni_reg_6143) { + } else if (devpriv->is_6143) { unsigned int calib_source; calib_source = data[1] & 0xf; @@ -2580,7 +2736,7 @@ static int ni_ai_insn_config(struct comedi_device *dev, return -EINVAL; devpriv->ai_calib_source = calib_source; - ni_writew(calib_source, Calibration_Channel_6143); + ni_writew(dev, calib_source, Calibration_Channel_6143); } else { unsigned int calib_source; unsigned int calib_source_adjust; @@ -2591,8 +2747,8 @@ static int ni_ai_insn_config(struct comedi_device *dev, if (calib_source >= 8) return -EINVAL; devpriv->ai_calib_source = calib_source; - if (board->reg_type == ni_reg_611x) { - ni_writeb(calib_source_adjust, + if (devpriv->is_611x) { + ni_writeb(dev, calib_source_adjust, Cal_Gain_Select_611x); } } @@ -2604,127 +2760,30 @@ static int ni_ai_insn_config(struct comedi_device *dev, return -EINVAL; } -static int ni_ai_config_analog_trig(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv = dev->private; - unsigned int a, b, modebits; - int err = 0; - - /* data[1] is flags - * data[2] is analog line - * data[3] is set level - * data[4] is reset level */ - if (!board->has_analog_trig) - return -EINVAL; - if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) { - data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff); - err++; - } - if (data[2] >= board->n_adchan) { - data[2] = board->n_adchan - 1; - err++; - } - if (data[3] > 255) { /* a */ - data[3] = 255; - err++; - } - if (data[4] > 255) { /* b */ - data[4] = 255; - err++; - } - /* - * 00 ignore - * 01 set - * 10 reset - * - * modes: - * 1 level: +b- +a- - * high mode 00 00 01 10 - * low mode 00 00 10 01 - * 2 level: (a<b) - * hysteresis low mode 10 00 00 01 - * hysteresis high mode 01 00 00 10 - * middle mode 10 01 01 10 - */ - - a = data[3]; - b = data[4]; - modebits = data[1] & 0xff; - if (modebits & 0xf0) { - /* two level mode */ - if (b < a) { - /* swap order */ - a = data[4]; - b = data[3]; - modebits = - ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4); - } - devpriv->atrig_low = a; - devpriv->atrig_high = b; - switch (modebits) { - case 0x81: /* low hysteresis mode */ - devpriv->atrig_mode = 6; - break; - case 0x42: /* high hysteresis mode */ - devpriv->atrig_mode = 3; - break; - case 0x96: /* middle window mode */ - devpriv->atrig_mode = 2; - break; - default: - data[1] &= ~0xff; - err++; - } - } else { - /* one level mode */ - if (b != 0) { - data[4] = 0; - err++; - } - switch (modebits) { - case 0x06: /* high window mode */ - devpriv->atrig_high = a; - devpriv->atrig_mode = 0; - break; - case 0x09: /* low window mode */ - devpriv->atrig_low = a; - devpriv->atrig_mode = 1; - break; - default: - data[1] &= ~0xff; - err++; - } - } - if (err) - return -EAGAIN; - return 5; -} - -/* munge data from unsigned to 2's complement for analog output bipolar modes */ static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s, void *data, unsigned int num_bytes, unsigned int chan_index) { - const struct ni_board_struct *board = comedi_board(dev); - struct comedi_async *async = s->async; - struct comedi_cmd *cmd = &async->cmd; - unsigned int length = num_bytes / sizeof(short); - unsigned int offset = 1 << (board->aobits - 1); + struct comedi_cmd *cmd = &s->async->cmd; + unsigned int length = num_bytes / bytes_per_sample(s); unsigned short *array = data; - unsigned int range; unsigned int i; for (i = 0; i < length; i++) { - range = CR_RANGE(cmd->chanlist[chan_index]); - if (board->ao_unipolar == 0 || (range & 1) == 0) - array[i] -= offset; + unsigned int range = CR_RANGE(cmd->chanlist[chan_index]); + unsigned short val = array[i]; + + /* + * Munge data from unsigned to two's complement for + * bipolar ranges. + */ + if (comedi_range_is_bipolar(s, range)) + val = comedi_offset_munge(s, val); #ifdef PCIDMA - array[i] = cpu_to_le16(array[i]); + val = cpu_to_le16(val); #endif + array[i] = val; + chan_index++; chan_index %= cmd->chanlist_len; } @@ -2735,7 +2794,6 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, unsigned int chanspec[], unsigned int n_chans, int timed) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; unsigned int range; unsigned int chan; @@ -2744,15 +2802,16 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, int invert = 0; if (timed) { - for (i = 0; i < board->n_aochan; ++i) { + for (i = 0; i < s->n_chan; ++i) { devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit; - ni_writeb(devpriv->ao_conf[i], + ni_writeb(dev, devpriv->ao_conf[i], M_Offset_AO_Config_Bank(i)); - ni_writeb(0xf, M_Offset_AO_Waveform_Order(i)); + ni_writeb(dev, 0xf, M_Offset_AO_Waveform_Order(i)); } } for (i = 0; i < n_chans; i++) { const struct comedi_krange *krange; + chan = CR_CHAN(chanspec[i]); range = CR_RANGE(chanspec[i]); krange = s->range_table->range + range; @@ -2761,25 +2820,28 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, switch (krange->max - krange->min) { case 20000000: conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; - ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan)); + ni_writeb(dev, 0, + M_Offset_AO_Reference_Attenuation(chan)); break; case 10000000: conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; - ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan)); + ni_writeb(dev, 0, + M_Offset_AO_Reference_Attenuation(chan)); break; case 4000000: conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits; - ni_writeb(MSeries_Attenuate_x5_Bit, + ni_writeb(dev, MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan)); break; case 2000000: conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits; - ni_writeb(MSeries_Attenuate_x5_Bit, + ni_writeb(dev, MSeries_Attenuate_x5_Bit, M_Offset_AO_Reference_Attenuation(chan)); break; default: - printk("%s: bug! unhandled ao reference voltage\n", - __func__); + dev_err(dev->class_dev, + "%s: bug! unhandled ao reference voltage\n", + __func__); break; } switch (krange->max + krange->min) { @@ -2790,15 +2852,16 @@ static int ni_m_series_ao_config_chanlist(struct comedi_device *dev, conf |= MSeries_AO_DAC_Offset_5V_Bits; break; default: - printk("%s: bug! unhandled ao offset voltage\n", - __func__); + dev_err(dev->class_dev, + "%s: bug! unhandled ao offset voltage\n", + __func__); break; } if (timed) conf |= MSeries_AO_Update_Timed_Bit; - ni_writeb(conf, M_Offset_AO_Config_Bank(chan)); + ni_writeb(dev, conf, M_Offset_AO_Config_Bank(chan)); devpriv->ao_conf[chan] = conf; - ni_writeb(i, M_Offset_AO_Waveform_Order(chan)); + ni_writeb(dev, i, M_Offset_AO_Waveform_Order(chan)); } return invert; } @@ -2808,7 +2871,6 @@ static int ni_old_ao_config_chanlist(struct comedi_device *dev, unsigned int chanspec[], unsigned int n_chans) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; unsigned int range; unsigned int chan; @@ -2821,19 +2883,14 @@ static int ni_old_ao_config_chanlist(struct comedi_device *dev, range = CR_RANGE(chanspec[i]); conf = AO_Channel(chan); - if (board->ao_unipolar) { - if ((range & 1) == 0) { - conf |= AO_Bipolar; - invert = (1 << (board->aobits - 1)); - } else { - invert = 0; - } - if (range & 2) - conf |= AO_Ext_Ref; - } else { + if (comedi_range_is_bipolar(s, range)) { conf |= AO_Bipolar; - invert = (1 << (board->aobits - 1)); + invert = (s->maxdata + 1) >> 1; + } else { + invert = 0; } + if (comedi_range_is_external(s, range)) + conf |= AO_Ext_Ref; /* not all boards can deglitch, but this shouldn't hurt */ if (chanspec[i] & CR_DEGLITCH) @@ -2844,7 +2901,7 @@ static int ni_old_ao_config_chanlist(struct comedi_device *dev, conf |= (CR_AREF(chanspec[i]) == AREF_OTHER) ? AO_Ground_Ref : 0; - ni_writew(conf, AO_Configuration); + ni_writew(dev, conf, AO_Configuration); devpriv->ao_conf[chan] = conf; } return invert; @@ -2855,9 +2912,9 @@ static int ni_ao_config_chanlist(struct comedi_device *dev, unsigned int chanspec[], unsigned int n_chans, int timed) { - const struct ni_board_struct *board = comedi_board(dev); + struct ni_private *devpriv = dev->private; - if (board->reg_type & ni_reg_m_series_mask) + if (devpriv->is_m_series) return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans, timed); else @@ -2865,56 +2922,75 @@ static int ni_ao_config_chanlist(struct comedi_device *dev, } static int ni_ao_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, struct comedi_insn *insn, + struct comedi_subdevice *s, + struct comedi_insn *insn, unsigned int *data) { struct ni_private *devpriv = dev->private; + unsigned int chan = CR_CHAN(insn->chanspec); + int i; - data[0] = devpriv->ao[CR_CHAN(insn->chanspec)]; + for (i = 0; i < insn->n; i++) + data[i] = devpriv->ao[chan]; - return 1; + return insn->n; } static int ni_ao_insn_write(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; unsigned int chan = CR_CHAN(insn->chanspec); - unsigned int invert; - - invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); - - devpriv->ao[chan] = data[0]; - - if (board->reg_type & ni_reg_m_series_mask) { - ni_writew(data[0], M_Offset_DAC_Direct_Data(chan)); - } else - ni_writew(data[0] ^ invert, - (chan) ? DAC1_Direct_Data : DAC0_Direct_Data); + unsigned int range = CR_RANGE(insn->chanspec); + int reg; + int i; - return 1; -} + if (devpriv->is_6xxx) { + ni_ao_win_outw(dev, 1 << chan, AO_Immediate_671x); -static int ni_ao_insn_write_671x(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) -{ - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv = dev->private; - unsigned int chan = CR_CHAN(insn->chanspec); - unsigned int invert; - - ao_win_out(1 << chan, AO_Immediate_671x); - invert = 1 << (board->aobits - 1); + reg = DACx_Direct_Data_671x(chan); + } else if (devpriv->is_m_series) { + reg = M_Offset_DAC_Direct_Data(chan); + } else { + reg = (chan) ? DAC1_Direct_Data : DAC0_Direct_Data; + } ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); - devpriv->ao[chan] = data[0]; - ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan)); + for (i = 0; i < insn->n; i++) { + unsigned int val = data[i]; + + devpriv->ao[chan] = val; + + if (devpriv->is_6xxx) { + /* + * 6xxx boards have bipolar outputs, munge the + * unsigned comedi values to 2's complement + */ + val = comedi_offset_munge(s, val); + + ni_ao_win_outw(dev, val, reg); + } else if (devpriv->is_m_series) { + /* + * M-series boards use offset binary values for + * bipolar and uinpolar outputs + */ + ni_writew(dev, val, reg); + } else { + /* + * Non-M series boards need two's complement values + * for bipolar ranges. + */ + if (comedi_range_is_bipolar(s, range)) + val = comedi_offset_munge(s, val); + + ni_writew(dev, val, reg); + } + } - return 1; + return insn->n; } static int ni_ao_insn_config(struct comedi_device *dev, @@ -2937,7 +3013,6 @@ static int ni_ao_insn_config(struct comedi_device *dev, break; default: return -EINVAL; - break; } return 0; default: @@ -2951,7 +3026,6 @@ static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int trig_num) { - const struct ni_board_struct *board __maybe_unused = comedi_board(dev); struct ni_private *devpriv = dev->private; struct comedi_cmd *cmd = &s->async->cmd; int ret; @@ -2971,8 +3045,8 @@ static int ni_ao_inttrig(struct comedi_device *dev, AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0); interrupt_b_bits = AO_Error_Interrupt_Enable; #ifdef PCIDMA - devpriv->stc_writew(dev, 1, DAC_FIFO_Clear); - if (board->reg_type & ni_reg_6xxx_mask) + ni_stc_writew(dev, 1, DAC_FIFO_Clear); + if (devpriv->is_6xxx) ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x); ret = ni_ao_setup_MITE_dma(dev); if (ret) @@ -2988,35 +3062,36 @@ static int ni_ao_inttrig(struct comedi_device *dev, interrupt_b_bits |= AO_FIFO_Interrupt_Enable; #endif - devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE, - AO_Mode_3_Register); - devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); + ni_stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE, + AO_Mode_3_Register); + ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); /* wait for DACs to be loaded */ for (i = 0; i < timeout; i++) { udelay(1); - if ((devpriv->stc_readw(dev, - Joint_Status_2_Register) & + if ((ni_stc_readw(dev, Joint_Status_2_Register) & AO_TMRDACWRs_In_Progress_St) == 0) break; } if (i == timeout) { - comedi_error(dev, - "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear"); + dev_err(dev->class_dev, + "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n"); return -EIO; } - /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */ - devpriv->stc_writew(dev, AO_Error_Interrupt_Ack, - Interrupt_B_Ack_Register); + /* + * stc manual says we are need to clear error interrupt after + * AO_TMRDACWRs_In_Progress_St clears + */ + ni_stc_writew(dev, AO_Error_Interrupt_Ack, Interrupt_B_Ack_Register); ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1); - devpriv->stc_writew(dev, - devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm - | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode, - AO_Command_1_Register); + ni_stc_writew(dev, devpriv->ao_cmd1 | + AO_UI_Arm | AO_UC_Arm | AO_BC_Arm | + AO_DAC1_Update_Mode | AO_DAC0_Update_Mode, + AO_Command_1_Register); - devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse, - AO_Command_2_Register); + ni_stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse, + AO_Command_2_Register); return 0; } @@ -3031,16 +3106,16 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) unsigned trigvar; if (dev->irq == 0) { - comedi_error(dev, "cannot run command without an irq"); + dev_err(dev->class_dev, "cannot run command without an irq\n"); return -EIO; } - devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); + ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); - devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register); + ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register); - if (board->reg_type & ni_reg_6xxx_mask) { - ao_win_out(CLEAR_WG, AO_Misc_611x); + if (devpriv->is_6xxx) { + ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x); bits = 0; for (i = 0; i < cmd->chanlist_len; i++) { @@ -3048,9 +3123,9 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) chan = CR_CHAN(cmd->chanlist[i]); bits |= 1 << chan; - ao_win_out(chan, AO_Waveform_Generation_611x); + ni_ao_win_outw(dev, chan, AO_Waveform_Generation_611x); } - ao_win_out(bits, AO_Timed_611x); + ni_ao_win_outw(dev, bits, AO_Timed_611x); } ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1); @@ -3062,15 +3137,15 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->ao_mode1 &= ~AO_Continuous; devpriv->ao_mode1 |= AO_Trigger_Once; } - devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); + ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); switch (cmd->start_src) { case TRIG_INT: case TRIG_NOW: devpriv->ao_trigger_select &= ~(AO_START1_Polarity | AO_START1_Select(-1)); devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync; - devpriv->stc_writew(dev, devpriv->ao_trigger_select, - AO_Trigger_Select_Register); + ni_stc_writew(dev, devpriv->ao_trigger_select, + AO_Trigger_Select_Register); break; case TRIG_EXT: devpriv->ao_trigger_select = @@ -3079,52 +3154,50 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ if (cmd->start_arg & CR_EDGE) devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */ - devpriv->stc_writew(dev, devpriv->ao_trigger_select, - AO_Trigger_Select_Register); + ni_stc_writew(dev, devpriv->ao_trigger_select, + AO_Trigger_Select_Register); break; default: BUG(); break; } devpriv->ao_mode3 &= ~AO_Trigger_Length; - devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); + ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); - devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); + ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source; - devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); if (cmd->stop_src == TRIG_NONE) - devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register); + ni_stc_writel(dev, 0xffffff, AO_BC_Load_A_Register); else - devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register); - devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register); + ni_stc_writel(dev, 0, AO_BC_Load_A_Register); + ni_stc_writew(dev, AO_BC_Load, AO_Command_1_Register); devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source; - devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); switch (cmd->stop_src) { case TRIG_COUNT: - if (board->reg_type & ni_reg_m_series_mask) { + if (devpriv->is_m_series) { /* this is how the NI example code does it for m-series boards, verified correct with 6259 */ - devpriv->stc_writel(dev, cmd->stop_arg - 1, - AO_UC_Load_A_Register); - devpriv->stc_writew(dev, AO_UC_Load, - AO_Command_1_Register); + ni_stc_writel(dev, cmd->stop_arg - 1, + AO_UC_Load_A_Register); + ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); } else { - devpriv->stc_writel(dev, cmd->stop_arg, - AO_UC_Load_A_Register); - devpriv->stc_writew(dev, AO_UC_Load, - AO_Command_1_Register); - devpriv->stc_writel(dev, cmd->stop_arg - 1, - AO_UC_Load_A_Register); + ni_stc_writel(dev, cmd->stop_arg, + AO_UC_Load_A_Register); + ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); + ni_stc_writel(dev, cmd->stop_arg - 1, + AO_UC_Load_A_Register); } break; case TRIG_NONE: - devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); - devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register); - devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); + ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); + ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); + ni_stc_writel(dev, 0xffffff, AO_UC_Load_A_Register); break; default: - devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register); - devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register); - devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register); + ni_stc_writel(dev, 0, AO_UC_Load_A_Register); + ni_stc_writew(dev, AO_UC_Load, AO_Command_1_Register); + ni_stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register); } devpriv->ao_mode1 &= @@ -3136,9 +3209,9 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, TRIG_ROUND_NEAREST); - devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register); - devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register); - devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register); + ni_stc_writel(dev, 1, AO_UI_Load_A_Register); + ni_stc_writew(dev, AO_UI_Load, AO_Command_1_Register); + ni_stc_writel(dev, trigvar, AO_UI_Load_A_Register); break; case TRIG_EXT: devpriv->ao_mode1 |= @@ -3151,40 +3224,38 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) BUG(); break; } - devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); - devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); + ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); + ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); devpriv->ao_mode2 &= ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source); - devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); if (cmd->scan_end_arg > 1) { devpriv->ao_mode1 |= AO_Multiple_Channels; - devpriv->stc_writew(dev, - AO_Number_Of_Channels(cmd->scan_end_arg - - 1) | - AO_UPDATE_Output_Select - (AO_Update_Output_High_Z), - AO_Output_Control_Register); + ni_stc_writew(dev, + AO_Number_Of_Channels(cmd->scan_end_arg - 1) | + AO_UPDATE_Output_Select(AO_Update_Output_High_Z), + AO_Output_Control_Register); } else { unsigned bits; + devpriv->ao_mode1 &= ~AO_Multiple_Channels; bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z); - if (board->reg_type & - (ni_reg_m_series_mask | ni_reg_6xxx_mask)) { + if (devpriv->is_m_series || devpriv->is_6xxx) { bits |= AO_Number_Of_Channels(0); } else { bits |= AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0])); } - devpriv->stc_writew(dev, bits, AO_Output_Control_Register); + ni_stc_writew(dev, bits, AO_Output_Control_Register); } - devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); + ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); - devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode, - AO_Command_1_Register); + ni_stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode, + AO_Command_1_Register); devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error; - devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); + ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask; #ifdef PCIDMA @@ -3193,7 +3264,7 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) devpriv->ao_mode2 |= AO_FIFO_Mode_HF; #endif devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable; - devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width | AO_TMRDACWR_Pulse_Width; @@ -3204,18 +3275,18 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) #if 0 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281, verified with bus analyzer. */ - if (board->reg_type & ni_reg_m_series_mask) + if (devpriv->is_m_series) bits |= AO_Number_Of_DAC_Packages; #endif - devpriv->stc_writew(dev, bits, AO_Personal_Register); + ni_stc_writew(dev, bits, AO_Personal_Register); /* enable sending of ao dma requests */ - devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register); + ni_stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register); - devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); + ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); if (cmd->stop_src == TRIG_COUNT) { - devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack, - Interrupt_B_Ack_Register); + ni_stc_writew(dev, AO_BC_TC_Interrupt_Ack, + Interrupt_B_Ack_Register); ni_set_bits(dev, Interrupt_B_Enable_Register, AO_BC_TC_Interrupt_Enable, 1); } @@ -3299,9 +3370,7 @@ static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, cmd->scan_begin_arg = ni_timer_to_ns(dev, ni_ns_to_timer(dev, cmd->scan_begin_arg, - cmd-> - flags & - TRIG_ROUND_MASK)); + cmd->flags)); if (tmp != cmd->scan_begin_arg) err++; } @@ -3313,51 +3382,45 @@ static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s, static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; - /* devpriv->ao0p=0x0000; */ - /* ni_writew(devpriv->ao0p,AO_Configuration); */ - - /* devpriv->ao1p=AO_Channel(1); */ - /* ni_writew(devpriv->ao1p,AO_Configuration); */ - ni_release_ao_mite_channel(dev); - devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); - devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register); + ni_stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register); + ni_stc_writew(dev, AO_Disarm, AO_Command_1_Register); ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0); - devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register); - devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register); - devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width | - AO_TMRDACWR_Pulse_Width, AO_Personal_Register); - devpriv->stc_writew(dev, 0, AO_Output_Control_Register); - devpriv->stc_writew(dev, 0, AO_Start_Select_Register); + ni_stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register); + ni_stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register); + ni_stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width | + AO_TMRDACWR_Pulse_Width, AO_Personal_Register); + ni_stc_writew(dev, 0, AO_Output_Control_Register); + ni_stc_writew(dev, 0, AO_Start_Select_Register); devpriv->ao_cmd1 = 0; - devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register); + ni_stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register); devpriv->ao_cmd2 = 0; - devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); + ni_stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register); devpriv->ao_mode1 = 0; - devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); + ni_stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register); devpriv->ao_mode2 = 0; - devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); - if (board->reg_type & ni_reg_m_series_mask) + ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register); + if (devpriv->is_m_series) devpriv->ao_mode3 = AO_Last_Gate_Disable; else devpriv->ao_mode3 = 0; - devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); + ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register); devpriv->ao_trigger_select = 0; - devpriv->stc_writew(dev, devpriv->ao_trigger_select, - AO_Trigger_Select_Register); - if (board->reg_type & ni_reg_6xxx_mask) { + ni_stc_writew(dev, devpriv->ao_trigger_select, + AO_Trigger_Select_Register); + if (devpriv->is_6xxx) { unsigned immediate_bits = 0; unsigned i; + for (i = 0; i < s->n_chan; ++i) immediate_bits |= 1 << i; - ao_win_out(immediate_bits, AO_Immediate_671x); - ao_win_out(CLEAR_WG, AO_Misc_611x); + ni_ao_win_outw(dev, immediate_bits, AO_Immediate_671x); + ni_ao_win_outw(dev, CLEAR_WG, AO_Misc_611x); } - devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); + ni_stc_writew(dev, AO_Configuration_End, Joint_Reset_Register); return 0; } @@ -3378,7 +3441,7 @@ static int ni_dio_insn_config(struct comedi_device *dev, devpriv->dio_control &= ~DIO_Pins_Dir_Mask; devpriv->dio_control |= DIO_Pins_Dir(s->io_bits); - devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register); + ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); return insn->n; } @@ -3397,11 +3460,10 @@ static int ni_dio_insn_bits(struct comedi_device *dev, if (comedi_dio_update_state(s, data)) { devpriv->dio_output &= ~DIO_Parallel_Data_Mask; devpriv->dio_output |= DIO_Parallel_Data_Out(s->state); - devpriv->stc_writew(dev, devpriv->dio_output, - DIO_Output_Register); + ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register); } - data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register); + data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register); return insn->n; } @@ -3411,14 +3473,13 @@ static int ni_m_series_dio_insn_config(struct comedi_device *dev, struct comedi_insn *insn, unsigned int *data) { - struct ni_private *devpriv __maybe_unused = dev->private; int ret; ret = comedi_dio_insn_config(dev, s, insn, data, 0); if (ret) return ret; - ni_writel(s->io_bits, M_Offset_DIO_Direction); + ni_writel(dev, s->io_bits, M_Offset_DIO_Direction); return insn->n; } @@ -3428,12 +3489,10 @@ static int ni_m_series_dio_insn_bits(struct comedi_device *dev, struct comedi_insn *insn, unsigned int *data) { - struct ni_private *devpriv __maybe_unused = dev->private; - if (comedi_dio_update_state(s, data)) - ni_writel(s->state, M_Offset_Static_Digital_Output); + ni_writel(dev, s->state, M_Offset_Static_Digital_Output); - data[1] = ni_readl(M_Offset_Static_Digital_Input); + data[1] = ni_readl(dev, M_Offset_Static_Digital_Input); return insn->n; } @@ -3508,57 +3567,18 @@ static int ni_cdio_cmdtest(struct comedi_device *dev, return 0; } -static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) -{ - struct ni_private *devpriv __maybe_unused = dev->private; - const struct comedi_cmd *cmd = &s->async->cmd; - unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit; - int retval; - - ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command); - switch (cmd->scan_begin_src) { - case TRIG_EXT: - cdo_mode_bits |= - CR_CHAN(cmd->scan_begin_arg) & - CDO_Sample_Source_Select_Mask; - break; - default: - BUG(); - break; - } - if (cmd->scan_begin_arg & CR_INVERT) - cdo_mode_bits |= CDO_Polarity_Bit; - ni_writel(cdo_mode_bits, M_Offset_CDO_Mode); - if (s->io_bits) { - ni_writel(s->state, M_Offset_CDO_FIFO_Data); - ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command); - ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable); - } else { - comedi_error(dev, - "attempted to run digital output command with no lines configured as outputs"); - return -EIO; - } - retval = ni_request_cdo_mite_channel(dev); - if (retval < 0) - return retval; - - s->async->inttrig = ni_cdo_inttrig; - - return 0; -} - static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s, unsigned int trig_num) { + struct comedi_cmd *cmd = &s->async->cmd; + const unsigned timeout = 1000; + int retval = 0; + unsigned i; #ifdef PCIDMA struct ni_private *devpriv = dev->private; unsigned long flags; #endif - struct comedi_cmd *cmd = &s->async->cmd; - int retval = 0; - unsigned i; - const unsigned timeout = 1000; if (trig_num != cmd->start_arg) return -EINVAL; @@ -3574,7 +3594,7 @@ static int ni_cdo_inttrig(struct comedi_device *dev, mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); mite_dma_arm(devpriv->cdo_mite_chan); } else { - comedi_error(dev, "BUG: no cdo mite channel?"); + dev_err(dev->class_dev, "BUG: no cdo mite channel?\n"); retval = -EIO; } spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); @@ -3583,53 +3603,88 @@ static int ni_cdo_inttrig(struct comedi_device *dev, #endif /* * XXX not sure what interrupt C group does -* ni_writeb(Interrupt_Group_C_Enable_Bit, +* ni_writeb(dev, Interrupt_Group_C_Enable_Bit, * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo */ for (i = 0; i < timeout; ++i) { - if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit) + if (ni_readl(dev, M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit) break; udelay(10); } if (i == timeout) { - comedi_error(dev, "dma failed to fill cdo fifo!"); - ni_cdio_cancel(dev, s); + dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n"); + s->cancel(dev, s); return -EIO; } - ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit | - CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, + ni_writel(dev, CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit | + CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, M_Offset_CDIO_Command); return retval; } -static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) +static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) { - struct ni_private *devpriv __maybe_unused = dev->private; + const struct comedi_cmd *cmd = &s->async->cmd; + unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit; + int retval; + + ni_writel(dev, CDO_Reset_Bit, M_Offset_CDIO_Command); + switch (cmd->scan_begin_src) { + case TRIG_EXT: + cdo_mode_bits |= + CR_CHAN(cmd->scan_begin_arg) & + CDO_Sample_Source_Select_Mask; + break; + default: + BUG(); + break; + } + if (cmd->scan_begin_arg & CR_INVERT) + cdo_mode_bits |= CDO_Polarity_Bit; + ni_writel(dev, cdo_mode_bits, M_Offset_CDO_Mode); + if (s->io_bits) { + ni_writel(dev, s->state, M_Offset_CDO_FIFO_Data); + ni_writel(dev, CDO_SW_Update_Bit, M_Offset_CDIO_Command); + ni_writel(dev, s->io_bits, M_Offset_CDO_Mask_Enable); + } else { + dev_err(dev->class_dev, + "attempted to run digital output command with no lines configured as outputs\n"); + return -EIO; + } + retval = ni_request_cdo_mite_channel(dev); + if (retval < 0) + return retval; + + s->async->inttrig = ni_cdo_inttrig; - ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit | - CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit | - CDO_FIFO_Request_Interrupt_Enable_Clear_Bit, + return 0; +} + +static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) +{ + ni_writel(dev, CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit | + CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit | + CDO_FIFO_Request_Interrupt_Enable_Clear_Bit, M_Offset_CDIO_Command); /* -* XXX not sure what interrupt C group does ni_writeb(0, +* XXX not sure what interrupt C group does ni_writeb(dev, 0, * M_Offset_Interrupt_C_Enable); */ - ni_writel(0, M_Offset_CDO_Mask_Enable); + ni_writel(dev, 0, M_Offset_CDO_Mask_Enable); ni_release_cdo_mite_channel(dev); return 0; } static void handle_cdio_interrupt(struct comedi_device *dev) { - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv __maybe_unused = dev->private; + struct ni_private *devpriv = dev->private; unsigned cdio_status; struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV]; #ifdef PCIDMA unsigned long flags; #endif - if ((board->reg_type & ni_reg_m_series_mask) == 0) + if (!devpriv->is_m_series) return; #ifdef PCIDMA spin_lock_irqsave(&devpriv->mite_channel_lock, flags); @@ -3646,112 +3701,21 @@ static void handle_cdio_interrupt(struct comedi_device *dev) spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); #endif - cdio_status = ni_readl(M_Offset_CDIO_Status); + cdio_status = ni_readl(dev, M_Offset_CDIO_Status); if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) { - /* printk("cdio error: statux=0x%x\n", cdio_status); */ - ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */ + /* XXX just guessing this is needed and does something useful */ + ni_writel(dev, CDO_Error_Interrupt_Confirm_Bit, + M_Offset_CDIO_Command); s->async->events |= COMEDI_CB_OVERFLOW; } if (cdio_status & CDO_FIFO_Empty_Bit) { - /* printk("cdio fifo empty\n"); */ - ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit, + ni_writel(dev, CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit, M_Offset_CDIO_Command); /* s->async->events |= COMEDI_CB_EOA; */ } cfc_handle_events(dev, s); } -static int ni_serial_insn_config(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) -{ - struct ni_private *devpriv = dev->private; - int err = insn->n; - unsigned char byte_out, byte_in = 0; - - if (insn->n != 2) - return -EINVAL; - - switch (data[0]) { - case INSN_CONFIG_SERIAL_CLOCK: - devpriv->serial_hw_mode = 1; - devpriv->dio_control |= DIO_HW_Serial_Enable; - - if (data[1] == SERIAL_DISABLED) { - devpriv->serial_hw_mode = 0; - devpriv->dio_control &= ~(DIO_HW_Serial_Enable | - DIO_Software_Serial_Control); - data[1] = SERIAL_DISABLED; - devpriv->serial_interval_ns = data[1]; - } else if (data[1] <= SERIAL_600NS) { - /* Warning: this clock speed is too fast to reliably - control SCXI. */ - devpriv->dio_control &= ~DIO_HW_Serial_Timebase; - devpriv->clock_and_fout |= Slow_Internal_Timebase; - devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2; - data[1] = SERIAL_600NS; - devpriv->serial_interval_ns = data[1]; - } else if (data[1] <= SERIAL_1_2US) { - devpriv->dio_control &= ~DIO_HW_Serial_Timebase; - devpriv->clock_and_fout |= Slow_Internal_Timebase | - DIO_Serial_Out_Divide_By_2; - data[1] = SERIAL_1_2US; - devpriv->serial_interval_ns = data[1]; - } else if (data[1] <= SERIAL_10US) { - devpriv->dio_control |= DIO_HW_Serial_Timebase; - devpriv->clock_and_fout |= Slow_Internal_Timebase | - DIO_Serial_Out_Divide_By_2; - /* Note: DIO_Serial_Out_Divide_By_2 only affects - 600ns/1.2us. If you turn divide_by_2 off with the - slow clock, you will still get 10us, except then - all your delays are wrong. */ - data[1] = SERIAL_10US; - devpriv->serial_interval_ns = data[1]; - } else { - devpriv->dio_control &= ~(DIO_HW_Serial_Enable | - DIO_Software_Serial_Control); - devpriv->serial_hw_mode = 0; - data[1] = (data[1] / 1000) * 1000; - devpriv->serial_interval_ns = data[1]; - } - - devpriv->stc_writew(dev, devpriv->dio_control, - DIO_Control_Register); - devpriv->stc_writew(dev, devpriv->clock_and_fout, - Clock_and_FOUT_Register); - return 1; - - break; - - case INSN_CONFIG_BIDIRECTIONAL_DATA: - - if (devpriv->serial_interval_ns == 0) - return -EINVAL; - - byte_out = data[1] & 0xFF; - - if (devpriv->serial_hw_mode) { - err = ni_serial_hw_readwrite8(dev, s, byte_out, - &byte_in); - } else if (devpriv->serial_interval_ns > 0) { - err = ni_serial_sw_readwrite8(dev, s, byte_out, - &byte_in); - } else { - printk("ni_serial_insn_config: serial disabled!\n"); - return -EINVAL; - } - if (err < 0) - return err; - data[1] = byte_in & 0xFF; - return insn->n; - - break; - default: - return -EINVAL; - } - -} - static int ni_serial_hw_readwrite8(struct comedi_device *dev, struct comedi_subdevice *s, unsigned char data_out, @@ -3763,28 +3727,27 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, devpriv->dio_output &= ~DIO_Serial_Data_Mask; devpriv->dio_output |= DIO_Serial_Data_Out(data_out); - devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register); + ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register); - status1 = devpriv->stc_readw(dev, Joint_Status_1_Register); + status1 = ni_stc_readw(dev, Joint_Status_1_Register); if (status1 & DIO_Serial_IO_In_Progress_St) { err = -EBUSY; goto Error; } devpriv->dio_control |= DIO_HW_Serial_Start; - devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register); + ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); devpriv->dio_control &= ~DIO_HW_Serial_Start; /* Wait until STC says we're done, but don't loop infinitely. */ - while ((status1 = - devpriv->stc_readw(dev, - Joint_Status_1_Register)) & + while ((status1 = ni_stc_readw(dev, Joint_Status_1_Register)) & DIO_Serial_IO_In_Progress_St) { /* Delay one bit per loop */ udelay((devpriv->serial_interval_ns + 999) / 1000); if (--count < 0) { - printk - ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n"); + dev_err(dev->class_dev, + "%s: SPI serial I/O didn't finish in time!\n", + __func__); err = -ETIME; goto Error; } @@ -3795,10 +3758,10 @@ static int ni_serial_hw_readwrite8(struct comedi_device *dev, udelay((devpriv->serial_interval_ns + 999) / 1000); if (data_in != NULL) - *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register); + *data_in = ni_stc_readw(dev, DIO_Serial_Input_Register); Error: - devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register); + ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); return err; } @@ -3821,29 +3784,23 @@ static int ni_serial_sw_readwrite8(struct comedi_device *dev, devpriv->dio_output &= ~DIO_SDOUT; if (data_out & mask) devpriv->dio_output |= DIO_SDOUT; - devpriv->stc_writew(dev, devpriv->dio_output, - DIO_Output_Register); + ni_stc_writew(dev, devpriv->dio_output, DIO_Output_Register); /* Assert SDCLK (active low, inverted), wait for half of the delay, deassert SDCLK, and wait for the other half. */ devpriv->dio_control |= DIO_Software_Serial_Control; - devpriv->stc_writew(dev, devpriv->dio_control, - DIO_Control_Register); + ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); udelay((devpriv->serial_interval_ns + 999) / 2000); devpriv->dio_control &= ~DIO_Software_Serial_Control; - devpriv->stc_writew(dev, devpriv->dio_control, - DIO_Control_Register); + ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); udelay((devpriv->serial_interval_ns + 999) / 2000); /* Input current bit */ - if (devpriv->stc_readw(dev, - DIO_Parallel_Input_Register) & DIO_SDIN) { - /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */ + if (ni_stc_readw(dev, DIO_Parallel_Input_Register) & DIO_SDIN) input |= mask; - } } if (data_in) @@ -3852,14 +3809,96 @@ static int ni_serial_sw_readwrite8(struct comedi_device *dev, return 0; } -static void mio_common_detach(struct comedi_device *dev) +static int ni_serial_insn_config(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { struct ni_private *devpriv = dev->private; + int err = insn->n; + unsigned char byte_out, byte_in = 0; - if (devpriv) { - if (devpriv->counter_dev) - ni_gpct_device_destroy(devpriv->counter_dev); + if (insn->n != 2) + return -EINVAL; + + switch (data[0]) { + case INSN_CONFIG_SERIAL_CLOCK: + devpriv->serial_hw_mode = 1; + devpriv->dio_control |= DIO_HW_Serial_Enable; + + if (data[1] == SERIAL_DISABLED) { + devpriv->serial_hw_mode = 0; + devpriv->dio_control &= ~(DIO_HW_Serial_Enable | + DIO_Software_Serial_Control); + data[1] = SERIAL_DISABLED; + devpriv->serial_interval_ns = data[1]; + } else if (data[1] <= SERIAL_600NS) { + /* Warning: this clock speed is too fast to reliably + control SCXI. */ + devpriv->dio_control &= ~DIO_HW_Serial_Timebase; + devpriv->clock_and_fout |= Slow_Internal_Timebase; + devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2; + data[1] = SERIAL_600NS; + devpriv->serial_interval_ns = data[1]; + } else if (data[1] <= SERIAL_1_2US) { + devpriv->dio_control &= ~DIO_HW_Serial_Timebase; + devpriv->clock_and_fout |= Slow_Internal_Timebase | + DIO_Serial_Out_Divide_By_2; + data[1] = SERIAL_1_2US; + devpriv->serial_interval_ns = data[1]; + } else if (data[1] <= SERIAL_10US) { + devpriv->dio_control |= DIO_HW_Serial_Timebase; + devpriv->clock_and_fout |= Slow_Internal_Timebase | + DIO_Serial_Out_Divide_By_2; + /* Note: DIO_Serial_Out_Divide_By_2 only affects + 600ns/1.2us. If you turn divide_by_2 off with the + slow clock, you will still get 10us, except then + all your delays are wrong. */ + data[1] = SERIAL_10US; + devpriv->serial_interval_ns = data[1]; + } else { + devpriv->dio_control &= ~(DIO_HW_Serial_Enable | + DIO_Software_Serial_Control); + devpriv->serial_hw_mode = 0; + data[1] = (data[1] / 1000) * 1000; + devpriv->serial_interval_ns = data[1]; + } + + ni_stc_writew(dev, devpriv->dio_control, DIO_Control_Register); + ni_stc_writew(dev, devpriv->clock_and_fout, + Clock_and_FOUT_Register); + return 1; + + break; + + case INSN_CONFIG_BIDIRECTIONAL_DATA: + + if (devpriv->serial_interval_ns == 0) + return -EINVAL; + + byte_out = data[1] & 0xFF; + + if (devpriv->serial_hw_mode) { + err = ni_serial_hw_readwrite8(dev, s, byte_out, + &byte_in); + } else if (devpriv->serial_interval_ns > 0) { + err = ni_serial_sw_readwrite8(dev, s, byte_out, + &byte_in); + } else { + dev_err(dev->class_dev, "%s: serial disabled!\n", + __func__); + return -EINVAL; + } + if (err < 0) + return err; + data[1] = byte_in & 0xFF; + return insn->n; + + break; + default: + return -EINVAL; } + } static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s) @@ -3870,12 +3909,13 @@ static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s) ni_ao_win_outw(dev, AO_Channel(i) | 0x0, AO_Configuration_2_67xx); } - ao_win_out(0x0, AO_Later_Single_Point_Updates); + ni_ao_win_outw(dev, 0x0, AO_Later_Single_Point_Updates); } static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg) { unsigned stc_register; + switch (reg) { case NITIO_G0_AUTO_INC: stc_register = G_Autoincrement_Register(0); @@ -3960,7 +4000,6 @@ static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg) __func__, reg); BUG(); return 0; - break; } return stc_register; } @@ -3969,7 +4008,6 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; - struct ni_private *devpriv = dev->private; unsigned stc_register; /* bits in the join reset register which are relevant to counters */ static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset; @@ -3981,28 +4019,28 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, switch (reg) { /* m-series-only registers */ case NITIO_G0_CNT_MODE: - ni_writew(bits, M_Offset_G0_Counting_Mode); + ni_writew(dev, bits, M_Offset_G0_Counting_Mode); break; case NITIO_G1_CNT_MODE: - ni_writew(bits, M_Offset_G1_Counting_Mode); + ni_writew(dev, bits, M_Offset_G1_Counting_Mode); break; case NITIO_G0_GATE2: - ni_writew(bits, M_Offset_G0_Second_Gate); + ni_writew(dev, bits, M_Offset_G0_Second_Gate); break; case NITIO_G1_GATE2: - ni_writew(bits, M_Offset_G1_Second_Gate); + ni_writew(dev, bits, M_Offset_G1_Second_Gate); break; case NITIO_G0_DMA_CFG: - ni_writew(bits, M_Offset_G0_DMA_Config); + ni_writew(dev, bits, M_Offset_G0_DMA_Config); break; case NITIO_G1_DMA_CFG: - ni_writew(bits, M_Offset_G1_DMA_Config); + ni_writew(dev, bits, M_Offset_G1_DMA_Config); break; case NITIO_G0_ABZ: - ni_writew(bits, M_Offset_G0_MSeries_ABZ); + ni_writew(dev, bits, M_Offset_G0_MSeries_ABZ); break; case NITIO_G1_ABZ: - ni_writew(bits, M_Offset_G1_MSeries_ABZ); + ni_writew(dev, bits, M_Offset_G1_MSeries_ABZ); break; /* 32 bit registers */ @@ -4011,7 +4049,7 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, case NITIO_G0_LOADB: case NITIO_G1_LOADB: stc_register = ni_gpct_to_stc_register(reg); - devpriv->stc_writel(dev, bits, stc_register); + ni_stc_writel(dev, bits, stc_register); break; /* 16 bit registers */ @@ -4030,7 +4068,7 @@ static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits, /* fall-through */ default: stc_register = ni_gpct_to_stc_register(reg); - devpriv->stc_writew(dev, bits, stc_register); + ni_stc_writew(dev, bits, stc_register); } } @@ -4038,15 +4076,14 @@ static unsigned ni_gpct_read_register(struct ni_gpct *counter, enum ni_gpct_register reg) { struct comedi_device *dev = counter->counter_dev->dev; - struct ni_private *devpriv = dev->private; unsigned stc_register; switch (reg) { /* m-series only registers */ case NITIO_G0_DMA_STATUS: - return ni_readw(M_Offset_G0_DMA_Status); + return ni_readw(dev, M_Offset_G0_DMA_Status); case NITIO_G1_DMA_STATUS: - return ni_readw(M_Offset_G1_DMA_Status); + return ni_readw(dev, M_Offset_G1_DMA_Status); /* 32 bit registers */ case NITIO_G0_HW_SAVE: @@ -4054,506 +4091,101 @@ static unsigned ni_gpct_read_register(struct ni_gpct *counter, case NITIO_G0_SW_SAVE: case NITIO_G1_SW_SAVE: stc_register = ni_gpct_to_stc_register(reg); - return devpriv->stc_readl(dev, stc_register); + return ni_stc_readl(dev, stc_register); /* 16 bit registers */ default: stc_register = ni_gpct_to_stc_register(reg); - return devpriv->stc_readw(dev, stc_register); - break; + return ni_stc_readw(dev, stc_register); } return 0; } static int ni_freq_out_insn_read(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { struct ni_private *devpriv = dev->private; + unsigned int val = devpriv->clock_and_fout & FOUT_Divider_mask; + int i; - data[0] = devpriv->clock_and_fout & FOUT_Divider_mask; - return 1; + for (i = 0; i < insn->n; i++) + data[i] = val; + + return insn->n; } static int ni_freq_out_insn_write(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { struct ni_private *devpriv = dev->private; - devpriv->clock_and_fout &= ~FOUT_Enable; - devpriv->stc_writew(dev, devpriv->clock_and_fout, - Clock_and_FOUT_Register); - devpriv->clock_and_fout &= ~FOUT_Divider_mask; - devpriv->clock_and_fout |= FOUT_Divider(data[0]); - devpriv->clock_and_fout |= FOUT_Enable; - devpriv->stc_writew(dev, devpriv->clock_and_fout, - Clock_and_FOUT_Register); - return insn->n; -} + if (insn->n) { + devpriv->clock_and_fout &= ~FOUT_Enable; + ni_stc_writew(dev, devpriv->clock_and_fout, + Clock_and_FOUT_Register); + devpriv->clock_and_fout &= ~FOUT_Divider_mask; -static int ni_set_freq_out_clock(struct comedi_device *dev, - unsigned int clock_source) -{ - struct ni_private *devpriv = dev->private; + /* use the last data value to set the fout divider */ + devpriv->clock_and_fout |= FOUT_Divider(data[insn->n - 1]); - switch (clock_source) { - case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC: - devpriv->clock_and_fout &= ~FOUT_Timebase_Select; - break; - case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC: - devpriv->clock_and_fout |= FOUT_Timebase_Select; - break; - default: - return -EINVAL; - } - devpriv->stc_writew(dev, devpriv->clock_and_fout, - Clock_and_FOUT_Register); - return 3; -} - -static void ni_get_freq_out_clock(struct comedi_device *dev, - unsigned int *clock_source, - unsigned int *clock_period_ns) -{ - struct ni_private *devpriv = dev->private; - - if (devpriv->clock_and_fout & FOUT_Timebase_Select) { - *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC; - *clock_period_ns = TIMEBASE_2_NS; - } else { - *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC; - *clock_period_ns = TIMEBASE_1_NS * 2; + devpriv->clock_and_fout |= FOUT_Enable; + ni_stc_writew(dev, devpriv->clock_and_fout, + Clock_and_FOUT_Register); } + return insn->n; } static int ni_freq_out_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { + struct ni_private *devpriv = dev->private; + switch (data[0]) { case INSN_CONFIG_SET_CLOCK_SRC: - return ni_set_freq_out_clock(dev, data[1]); + switch (data[1]) { + case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC: + devpriv->clock_and_fout &= ~FOUT_Timebase_Select; + break; + case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC: + devpriv->clock_and_fout |= FOUT_Timebase_Select; + break; + default: + return -EINVAL; + } + ni_stc_writew(dev, devpriv->clock_and_fout, + Clock_and_FOUT_Register); break; case INSN_CONFIG_GET_CLOCK_SRC: - ni_get_freq_out_clock(dev, &data[1], &data[2]); - return 3; - default: + if (devpriv->clock_and_fout & FOUT_Timebase_Select) { + data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC; + data[2] = TIMEBASE_2_NS; + } else { + data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC; + data[2] = TIMEBASE_1_NS * 2; + } break; - } - return -EINVAL; -} - -static int ni_alloc_private(struct comedi_device *dev) -{ - struct ni_private *devpriv; - - devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); - if (!devpriv) - return -ENOMEM; - - spin_lock_init(&devpriv->window_lock); - spin_lock_init(&devpriv->soft_reg_copy_lock); - spin_lock_init(&devpriv->mite_channel_lock); - - return 0; -}; - -static int ni_E_init(struct comedi_device *dev) -{ - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv = dev->private; - struct comedi_subdevice *s; - unsigned j; - enum ni_gpct_variant counter_variant; - int ret; - - if (board->n_aochan > MAX_N_AO_CHAN) { - printk("bug! n_aochan > MAX_N_AO_CHAN\n"); + default: return -EINVAL; } - - ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES); - if (ret) - return ret; - - /* analog input subdevice */ - - s = &dev->subdevices[NI_AI_SUBDEV]; - dev->read_subdev = s; - if (board->n_adchan) { - s->type = COMEDI_SUBD_AI; - s->subdev_flags = - SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ; - if (board->reg_type != ni_reg_611x) - s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER; - if (board->adbits > 16) - s->subdev_flags |= SDF_LSAMPL; - if (board->reg_type & ni_reg_m_series_mask) - s->subdev_flags |= SDF_SOFT_CALIBRATED; - s->n_chan = board->n_adchan; - s->len_chanlist = 512; - s->maxdata = (1 << board->adbits) - 1; - s->range_table = ni_range_lkup[board->gainlkup]; - s->insn_read = &ni_ai_insn_read; - s->insn_config = &ni_ai_insn_config; - s->do_cmdtest = &ni_ai_cmdtest; - s->do_cmd = &ni_ai_cmd; - s->cancel = &ni_ai_reset; - s->poll = &ni_ai_poll; - s->munge = &ni_ai_munge; -#ifdef PCIDMA - s->async_dma_dir = DMA_FROM_DEVICE; -#endif - } else { - s->type = COMEDI_SUBD_UNUSED; - } - - /* analog output subdevice */ - - s = &dev->subdevices[NI_AO_SUBDEV]; - if (board->n_aochan) { - s->type = COMEDI_SUBD_AO; - s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND; - if (board->reg_type & ni_reg_m_series_mask) - s->subdev_flags |= SDF_SOFT_CALIBRATED; - s->n_chan = board->n_aochan; - s->maxdata = (1 << board->aobits) - 1; - s->range_table = board->ao_range_table; - s->insn_read = &ni_ao_insn_read; - if (board->reg_type & ni_reg_6xxx_mask) - s->insn_write = &ni_ao_insn_write_671x; - else - s->insn_write = &ni_ao_insn_write; - s->insn_config = &ni_ao_insn_config; -#ifdef PCIDMA - if (board->n_aochan) { - s->async_dma_dir = DMA_TO_DEVICE; -#else - if (board->ao_fifo_depth) { -#endif - dev->write_subdev = s; - s->subdev_flags |= SDF_CMD_WRITE; - s->do_cmd = &ni_ao_cmd; - s->do_cmdtest = &ni_ao_cmdtest; - s->len_chanlist = board->n_aochan; - if ((board->reg_type & ni_reg_m_series_mask) == 0) - s->munge = ni_ao_munge; - } - s->cancel = &ni_ao_reset; - } else { - s->type = COMEDI_SUBD_UNUSED; - } - if ((board->reg_type & ni_reg_67xx_mask)) - init_ao_67xx(dev, s); - - /* digital i/o subdevice */ - - s = &dev->subdevices[NI_DIO_SUBDEV]; - s->type = COMEDI_SUBD_DIO; - s->subdev_flags = SDF_WRITABLE | SDF_READABLE; - s->maxdata = 1; - s->io_bits = 0; /* all bits input */ - s->range_table = &range_digital; - s->n_chan = board->num_p0_dio_channels; - if (board->reg_type & ni_reg_m_series_mask) { - s->subdev_flags |= - SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */; - s->insn_bits = &ni_m_series_dio_insn_bits; - s->insn_config = &ni_m_series_dio_insn_config; - s->do_cmd = &ni_cdio_cmd; - s->do_cmdtest = &ni_cdio_cmdtest; - s->cancel = &ni_cdio_cancel; - s->async_dma_dir = DMA_BIDIRECTIONAL; - s->len_chanlist = s->n_chan; - - ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command); - ni_writel(s->io_bits, M_Offset_DIO_Direction); - } else { - s->insn_bits = &ni_dio_insn_bits; - s->insn_config = &ni_dio_insn_config; - devpriv->dio_control = DIO_Pins_Dir(s->io_bits); - ni_writew(devpriv->dio_control, DIO_Control_Register); - } - - /* 8255 device */ - s = &dev->subdevices[NI_8255_DIO_SUBDEV]; - if (board->has_8255) { - ret = subdev_8255_init(dev, s, ni_8255_callback, - (unsigned long)dev); - if (ret) - return ret; - } else { - s->type = COMEDI_SUBD_UNUSED; - } - - /* formerly general purpose counter/timer device, but no longer used */ - s = &dev->subdevices[NI_UNUSED_SUBDEV]; - s->type = COMEDI_SUBD_UNUSED; - - /* calibration subdevice -- ai and ao */ - s = &dev->subdevices[NI_CALIBRATION_SUBDEV]; - s->type = COMEDI_SUBD_CALIB; - if (board->reg_type & ni_reg_m_series_mask) { - /* internal PWM analog output used for AI nonlinearity calibration */ - s->subdev_flags = SDF_INTERNAL; - s->insn_config = &ni_m_series_pwm_config; - s->n_chan = 1; - s->maxdata = 0; - ni_writel(0x0, M_Offset_Cal_PWM); - } else if (board->reg_type == ni_reg_6143) { - /* internal PWM analog output used for AI nonlinearity calibration */ - s->subdev_flags = SDF_INTERNAL; - s->insn_config = &ni_6143_pwm_config; - s->n_chan = 1; - s->maxdata = 0; - } else { - s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL; - s->insn_read = &ni_calib_insn_read; - s->insn_write = &ni_calib_insn_write; - caldac_setup(dev, s); - } - - /* EEPROM */ - s = &dev->subdevices[NI_EEPROM_SUBDEV]; - s->type = COMEDI_SUBD_MEMORY; - s->subdev_flags = SDF_READABLE | SDF_INTERNAL; - s->maxdata = 0xff; - if (board->reg_type & ni_reg_m_series_mask) { - s->n_chan = M_SERIES_EEPROM_SIZE; - s->insn_read = &ni_m_series_eeprom_insn_read; - } else { - s->n_chan = 512; - s->insn_read = &ni_eeprom_insn_read; - } - - /* PFI */ - s = &dev->subdevices[NI_PFI_DIO_SUBDEV]; - s->type = COMEDI_SUBD_DIO; - s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; - if (board->reg_type & ni_reg_m_series_mask) { - unsigned i; - s->n_chan = 16; - ni_writew(s->state, M_Offset_PFI_DO); - for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { - ni_writew(devpriv->pfi_output_select_reg[i], - M_Offset_PFI_Output_Select(i + 1)); - } - } else { - s->n_chan = 10; - } - s->maxdata = 1; - if (board->reg_type & ni_reg_m_series_mask) - s->insn_bits = &ni_pfi_insn_bits; - s->insn_config = &ni_pfi_insn_config; - ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0); - - /* cs5529 calibration adc */ - s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV]; - if (board->reg_type & ni_reg_67xx_mask) { - s->type = COMEDI_SUBD_AI; - s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL; - /* one channel for each analog output channel */ - s->n_chan = board->n_aochan; - s->maxdata = (1 << 16) - 1; - s->range_table = &range_unknown; /* XXX */ - s->insn_read = cs5529_ai_insn_read; - s->insn_config = NULL; - init_cs5529(dev); - } else { - s->type = COMEDI_SUBD_UNUSED; - } - - /* Serial */ - s = &dev->subdevices[NI_SERIAL_SUBDEV]; - s->type = COMEDI_SUBD_SERIAL; - s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; - s->n_chan = 1; - s->maxdata = 0xff; - s->insn_config = ni_serial_insn_config; - devpriv->serial_interval_ns = 0; - devpriv->serial_hw_mode = 0; - - /* RTSI */ - s = &dev->subdevices[NI_RTSI_SUBDEV]; - s->type = COMEDI_SUBD_DIO; - s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; - s->n_chan = 8; - s->maxdata = 1; - s->insn_bits = ni_rtsi_insn_bits; - s->insn_config = ni_rtsi_insn_config; - ni_rtsi_init(dev); - - if (board->reg_type & ni_reg_m_series_mask) - counter_variant = ni_gpct_variant_m_series; - else - counter_variant = ni_gpct_variant_e_series; - devpriv->counter_dev = ni_gpct_device_construct(dev, - &ni_gpct_write_register, - &ni_gpct_read_register, - counter_variant, - NUM_GPCT); - if (!devpriv->counter_dev) - return -ENOMEM; - - /* General purpose counters */ - for (j = 0; j < NUM_GPCT; ++j) { - s = &dev->subdevices[NI_GPCT_SUBDEV(j)]; - s->type = COMEDI_SUBD_COUNTER; - s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL; - s->n_chan = 3; - if (board->reg_type & ni_reg_m_series_mask) - s->maxdata = 0xffffffff; - else - s->maxdata = 0xffffff; - s->insn_read = ni_tio_insn_read; - s->insn_write = ni_tio_insn_read; - s->insn_config = ni_tio_insn_config; -#ifdef PCIDMA - s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */; - s->do_cmd = &ni_gpct_cmd; - s->len_chanlist = 1; - s->do_cmdtest = ni_tio_cmdtest; - s->cancel = &ni_gpct_cancel; - s->async_dma_dir = DMA_BIDIRECTIONAL; -#endif - s->private = &devpriv->counter_dev->counters[j]; - - devpriv->counter_dev->counters[j].chip_index = 0; - devpriv->counter_dev->counters[j].counter_index = j; - ni_tio_init_counter(&devpriv->counter_dev->counters[j]); - } - - /* Frequency output */ - s = &dev->subdevices[NI_FREQ_OUT_SUBDEV]; - s->type = COMEDI_SUBD_COUNTER; - s->subdev_flags = SDF_READABLE | SDF_WRITABLE; - s->n_chan = 1; - s->maxdata = 0xf; - s->insn_read = &ni_freq_out_insn_read; - s->insn_write = &ni_freq_out_insn_write; - s->insn_config = &ni_freq_out_insn_config; - - /* ai configuration */ - s = &dev->subdevices[NI_AI_SUBDEV]; - ni_ai_reset(dev, s); - if ((board->reg_type & ni_reg_6xxx_mask) == 0) { - /* BEAM is this needed for PCI-6143 ?? */ - devpriv->clock_and_fout = - Slow_Internal_Time_Divide_By_2 | - Slow_Internal_Timebase | - Clock_To_Board_Divide_By_2 | - Clock_To_Board | - AI_Output_Divide_By_2 | AO_Output_Divide_By_2; - } else { - devpriv->clock_and_fout = - Slow_Internal_Time_Divide_By_2 | - Slow_Internal_Timebase | - Clock_To_Board_Divide_By_2 | Clock_To_Board; - } - devpriv->stc_writew(dev, devpriv->clock_and_fout, - Clock_and_FOUT_Register); - - /* analog output configuration */ - s = &dev->subdevices[NI_AO_SUBDEV]; - ni_ao_reset(dev, s); - - if (dev->irq) { - devpriv->stc_writew(dev, - (IRQ_POLARITY ? Interrupt_Output_Polarity : - 0) | (Interrupt_Output_On_3_Pins & 0) | - Interrupt_A_Enable | Interrupt_B_Enable | - Interrupt_A_Output_Select(interrupt_pin - (dev->irq)) | - Interrupt_B_Output_Select(interrupt_pin - (dev->irq)), - Interrupt_Control_Register); - } - - /* DMA setup */ - ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select); - ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select); - - if (board->reg_type & ni_reg_6xxx_mask) { - ni_writeb(0, Magic_611x); - } else if (board->reg_type & ni_reg_m_series_mask) { - int channel; - for (channel = 0; channel < board->n_aochan; ++channel) { - ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel)); - ni_writeb(0x0, - M_Offset_AO_Reference_Attenuation(channel)); - } - ni_writeb(0x0, M_Offset_AO_Calibration); - } - - return 0; + return insn->n; } static int ni_8255_callback(int dir, int port, int data, unsigned long arg) { struct comedi_device *dev = (struct comedi_device *)arg; - struct ni_private *devpriv __maybe_unused = dev->private; if (dir) { - ni_writeb(data, Port_A + 2 * port); + ni_writeb(dev, data, Port_A + 2 * port); return 0; - } else { - return ni_readb(Port_A + 2 * port); } -} -/* - presents the EEPROM as a subdevice -*/ - -static int ni_eeprom_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) -{ - data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec)); - - return 1; -} - -/* - reads bytes out of eeprom -*/ - -static int ni_read_eeprom(struct comedi_device *dev, int addr) -{ - struct ni_private *devpriv __maybe_unused = dev->private; - int bit; - int bitstring; - - bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff); - ni_writeb(0x04, Serial_Command); - for (bit = 0x8000; bit; bit >>= 1) { - ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0), - Serial_Command); - ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0), - Serial_Command); - } - bitstring = 0; - for (bit = 0x80; bit; bit >>= 1) { - ni_writeb(0x04, Serial_Command); - ni_writeb(0x05, Serial_Command); - bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0); - } - ni_writeb(0x00, Serial_Command); - - return bitstring; -} - -static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - struct ni_private *devpriv = dev->private; - - data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)]; - - return 1; + return ni_readb(dev, Port_A + 2 * port); } static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data) @@ -4567,7 +4199,8 @@ static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data) static int ni_m_series_pwm_config(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { struct ni_private *devpriv = dev->private; unsigned up_count, down_count; @@ -4590,7 +4223,6 @@ static int ni_m_series_pwm_config(struct comedi_device *dev, break; default: return -EINVAL; - break; } switch (data[3]) { case TRIG_ROUND_NEAREST: @@ -4608,7 +4240,6 @@ static int ni_m_series_pwm_config(struct comedi_device *dev, break; default: return -EINVAL; - break; } if (up_count * devpriv->clock_ns != data[2] || down_count * devpriv->clock_ns != data[4]) { @@ -4616,26 +4247,24 @@ static int ni_m_series_pwm_config(struct comedi_device *dev, data[4] = down_count * devpriv->clock_ns; return -EAGAIN; } - ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) | - MSeries_Cal_PWM_Low_Time_Bits(down_count), + ni_writel(dev, MSeries_Cal_PWM_High_Time_Bits(up_count) | + MSeries_Cal_PWM_Low_Time_Bits(down_count), M_Offset_Cal_PWM); devpriv->pwm_up_count = up_count; devpriv->pwm_down_count = down_count; return 5; - break; case INSN_CONFIG_GET_PWM_OUTPUT: return ni_get_pwm_config(dev, data); - break; default: return -EINVAL; - break; } return 0; } static int ni_6143_pwm_config(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { struct ni_private *devpriv = dev->private; unsigned up_count, down_count; @@ -4658,7 +4287,6 @@ static int ni_6143_pwm_config(struct comedi_device *dev, break; default: return -EINVAL; - break; } switch (data[3]) { case TRIG_ROUND_NEAREST: @@ -4676,7 +4304,6 @@ static int ni_6143_pwm_config(struct comedi_device *dev, break; default: return -EINVAL; - break; } if (up_count * devpriv->clock_ns != data[2] || down_count * devpriv->clock_ns != data[4]) { @@ -4684,51 +4311,66 @@ static int ni_6143_pwm_config(struct comedi_device *dev, data[4] = down_count * devpriv->clock_ns; return -EAGAIN; } - ni_writel(up_count, Calibration_HighTime_6143); + ni_writel(dev, up_count, Calibration_HighTime_6143); devpriv->pwm_up_count = up_count; - ni_writel(down_count, Calibration_LowTime_6143); + ni_writel(dev, down_count, Calibration_LowTime_6143); devpriv->pwm_down_count = down_count; return 5; - break; case INSN_CONFIG_GET_PWM_OUTPUT: return ni_get_pwm_config(dev, data); default: return -EINVAL; - break; } return 0; } -static void ni_write_caldac(struct comedi_device *dev, int addr, int val); -/* - calibration subdevice -*/ -static int ni_calib_insn_write(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int pack_mb88341(int addr, int val, int *bitstring) { - ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]); + /* + Fujitsu MB 88341 + Note that address bits are reversed. Thanks to + Ingo Keen for noticing this. - return 1; + Note also that the 88341 expects address values from + 1-12, whereas we use channel numbers 0-11. The NI + docs use 1-12, also, so be careful here. + */ + addr++; + *bitstring = ((addr & 0x1) << 11) | + ((addr & 0x2) << 9) | + ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff); + return 12; } -static int ni_calib_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int pack_dac8800(int addr, int val, int *bitstring) { - struct ni_private *devpriv = dev->private; + *bitstring = ((addr & 0x7) << 8) | (val & 0xff); + return 11; +} - data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)]; +static int pack_dac8043(int addr, int val, int *bitstring) +{ + *bitstring = val & 0xfff; + return 12; +} - return 1; +static int pack_ad8522(int addr, int val, int *bitstring) +{ + *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000); + return 16; } -static int pack_mb88341(int addr, int val, int *bitstring); -static int pack_dac8800(int addr, int val, int *bitstring); -static int pack_dac8043(int addr, int val, int *bitstring); -static int pack_ad8522(int addr, int val, int *bitstring); -static int pack_ad8804(int addr, int val, int *bitstring); -static int pack_ad8842(int addr, int val, int *bitstring); +static int pack_ad8804(int addr, int val, int *bitstring) +{ + *bitstring = ((addr & 0xf) << 8) | (val & 0xff); + return 12; +} + +static int pack_ad8842(int addr, int val, int *bitstring) +{ + *bitstring = ((addr + 1) << 8) | (val & 0xff); + return 12; +} struct caldac_struct { int n_chans; @@ -4746,6 +4388,64 @@ static struct caldac_struct caldacs[] = { [ad8804_debug] = {16, 8, pack_ad8804}, }; +static void ni_write_caldac(struct comedi_device *dev, int addr, int val) +{ + const struct ni_board_struct *board = comedi_board(dev); + struct ni_private *devpriv = dev->private; + unsigned int loadbit = 0, bits = 0, bit, bitstring = 0; + int i; + int type; + + if (devpriv->caldacs[addr] == val) + return; + devpriv->caldacs[addr] = val; + + for (i = 0; i < 3; i++) { + type = board->caldac[i]; + if (type == caldac_none) + break; + if (addr < caldacs[type].n_chans) { + bits = caldacs[type].packbits(addr, val, &bitstring); + loadbit = SerDacLd(i); + break; + } + addr -= caldacs[type].n_chans; + } + + for (bit = 1 << (bits - 1); bit; bit >>= 1) { + ni_writeb(dev, ((bit & bitstring) ? 0x02 : 0), Serial_Command); + udelay(1); + ni_writeb(dev, 1 | ((bit & bitstring) ? 0x02 : 0), + Serial_Command); + udelay(1); + } + ni_writeb(dev, loadbit, Serial_Command); + udelay(1); + ni_writeb(dev, 0, Serial_Command); +} + +static int ni_calib_insn_write(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]); + + return 1; +} + +static int ni_calib_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct ni_private *devpriv = dev->private; + + data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)]; + + return 1; +} + static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) { const struct ni_board_struct *board = comedi_board(dev); @@ -4777,7 +4477,8 @@ static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) unsigned int *maxdata_list; if (n_chans > MAX_N_CALDACS) - printk("BUG! MAX_N_CALDACS too small\n"); + dev_err(dev->class_dev, + "BUG! MAX_N_CALDACS too small\n"); s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list; chan = 0; for (i = 0; i < n_dacs; i++) { @@ -4800,221 +4501,106 @@ static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s) } } -static void ni_write_caldac(struct comedi_device *dev, int addr, int val) +static int ni_read_eeprom(struct comedi_device *dev, int addr) { - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv = dev->private; - unsigned int loadbit = 0, bits = 0, bit, bitstring = 0; - int i; - int type; - - /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */ - if (devpriv->caldacs[addr] == val) - return; - devpriv->caldacs[addr] = val; + int bit; + int bitstring; - for (i = 0; i < 3; i++) { - type = board->caldac[i]; - if (type == caldac_none) - break; - if (addr < caldacs[type].n_chans) { - bits = caldacs[type].packbits(addr, val, &bitstring); - loadbit = SerDacLd(i); - /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */ - break; - } - addr -= caldacs[type].n_chans; + bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff); + ni_writeb(dev, 0x04, Serial_Command); + for (bit = 0x8000; bit; bit >>= 1) { + ni_writeb(dev, 0x04 | ((bit & bitstring) ? 0x02 : 0), + Serial_Command); + ni_writeb(dev, 0x05 | ((bit & bitstring) ? 0x02 : 0), + Serial_Command); } - - for (bit = 1 << (bits - 1); bit; bit >>= 1) { - ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command); - udelay(1); - ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command); - udelay(1); + bitstring = 0; + for (bit = 0x80; bit; bit >>= 1) { + ni_writeb(dev, 0x04, Serial_Command); + ni_writeb(dev, 0x05, Serial_Command); + bitstring |= ((ni_readb(dev, XXX_Status) & PROMOUT) ? bit : 0); } - ni_writeb(loadbit, Serial_Command); - udelay(1); - ni_writeb(0, Serial_Command); -} - -static int pack_mb88341(int addr, int val, int *bitstring) -{ - /* - Fujitsu MB 88341 - Note that address bits are reversed. Thanks to - Ingo Keen for noticing this. - - Note also that the 88341 expects address values from - 1-12, whereas we use channel numbers 0-11. The NI - docs use 1-12, also, so be careful here. - */ - addr++; - *bitstring = ((addr & 0x1) << 11) | - ((addr & 0x2) << 9) | - ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff); - return 12; -} - -static int pack_dac8800(int addr, int val, int *bitstring) -{ - *bitstring = ((addr & 0x7) << 8) | (val & 0xff); - return 11; -} - -static int pack_dac8043(int addr, int val, int *bitstring) -{ - *bitstring = val & 0xfff; - return 12; -} + ni_writeb(dev, 0x00, Serial_Command); -static int pack_ad8522(int addr, int val, int *bitstring) -{ - *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000); - return 16; + return bitstring; } -static int pack_ad8804(int addr, int val, int *bitstring) +static int ni_eeprom_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { - *bitstring = ((addr & 0xf) << 8) | (val & 0xff); - return 12; -} + data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec)); -static int pack_ad8842(int addr, int val, int *bitstring) -{ - *bitstring = ((addr + 1) << 8) | (val & 0xff); - return 12; + return 1; } -#if 0 -/* - * Read the GPCTs current value. - */ -static int GPCT_G_Watch(struct comedi_device *dev, int chan) +static int ni_m_series_eeprom_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { - unsigned int hi1, hi2, lo; - - devpriv->gpct_command[chan] &= ~G_Save_Trace; - devpriv->stc_writew(dev, devpriv->gpct_command[chan], - G_Command_Register(chan)); - - devpriv->gpct_command[chan] |= G_Save_Trace; - devpriv->stc_writew(dev, devpriv->gpct_command[chan], - G_Command_Register(chan)); + struct ni_private *devpriv = dev->private; - /* This procedure is used because the two registers cannot - * be read atomically. */ - do { - hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan)); - lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan)); - hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan)); - } while (hi1 != hi2); + data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)]; - return (hi1 << 16) | lo; + return 1; } -static void GPCT_Reset(struct comedi_device *dev, int chan) +static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, + unsigned chan) { - int temp_ack_reg = 0; - - /* printk("GPCT_Reset..."); */ - devpriv->gpct_cur_operation[chan] = GPCT_RESET; - + /* pre-m-series boards have fixed signals on pfi pins */ switch (chan) { case 0: - devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register); - ni_set_bits(dev, Interrupt_A_Enable_Register, - G0_TC_Interrupt_Enable, 0); - ni_set_bits(dev, Interrupt_A_Enable_Register, - G0_Gate_Interrupt_Enable, 0); - temp_ack_reg |= G0_Gate_Error_Confirm; - temp_ack_reg |= G0_TC_Error_Confirm; - temp_ack_reg |= G0_TC_Interrupt_Ack; - temp_ack_reg |= G0_Gate_Interrupt_Ack; - devpriv->stc_writew(dev, temp_ack_reg, - Interrupt_A_Ack_Register); - - /* problem...this interferes with the other ctr... */ - devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable; - devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, - Analog_Trigger_Etc_Register); - break; + return NI_PFI_OUTPUT_AI_START1; case 1: - devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register); - ni_set_bits(dev, Interrupt_B_Enable_Register, - G1_TC_Interrupt_Enable, 0); - ni_set_bits(dev, Interrupt_B_Enable_Register, - G0_Gate_Interrupt_Enable, 0); - temp_ack_reg |= G1_Gate_Error_Confirm; - temp_ack_reg |= G1_TC_Error_Confirm; - temp_ack_reg |= G1_TC_Interrupt_Ack; - temp_ack_reg |= G1_Gate_Interrupt_Ack; - devpriv->stc_writew(dev, temp_ack_reg, - Interrupt_B_Ack_Register); - - devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable; - devpriv->stc_writew(dev, devpriv->an_trig_etc_reg, - Analog_Trigger_Etc_Register); + return NI_PFI_OUTPUT_AI_START2; + case 2: + return NI_PFI_OUTPUT_AI_CONVERT; + case 3: + return NI_PFI_OUTPUT_G_SRC1; + case 4: + return NI_PFI_OUTPUT_G_GATE1; + case 5: + return NI_PFI_OUTPUT_AO_UPDATE_N; + case 6: + return NI_PFI_OUTPUT_AO_START1; + case 7: + return NI_PFI_OUTPUT_AI_START_PULSE; + case 8: + return NI_PFI_OUTPUT_G_SRC0; + case 9: + return NI_PFI_OUTPUT_G_GATE0; + default: + dev_err(dev->class_dev, + "%s: bug, unhandled case in switch.\n", __func__); break; } - - devpriv->gpct_mode[chan] = 0; - devpriv->gpct_input_select[chan] = 0; - devpriv->gpct_command[chan] = 0; - - devpriv->gpct_command[chan] |= G_Synchronized_Gate; - - devpriv->stc_writew(dev, devpriv->gpct_mode[chan], - G_Mode_Register(chan)); - devpriv->stc_writew(dev, devpriv->gpct_input_select[chan], - G_Input_Select_Register(chan)); - devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan)); - - /* printk("exit GPCT_Reset\n"); */ + return 0; } -#endif - -#ifdef PCIDMA -static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s) +static int ni_old_set_pfi_routing(struct comedi_device *dev, + unsigned chan, unsigned source) { - struct ni_gpct *counter = s->private; - int retval; - - retval = ni_request_gpct_mite_channel(dev, counter->counter_index, - COMEDI_INPUT); - if (retval) { - comedi_error(dev, - "no dma channel available for use by counter"); - return retval; - } - ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL); - ni_e_series_enable_second_irq(dev, counter->counter_index, 1); - - return ni_tio_cmd(dev, s); + /* pre-m-series boards have fixed signals on pfi pins */ + if (source != ni_old_get_pfi_routing(dev, chan)) + return -EINVAL; + return 2; } -#endif -#ifdef PCIDMA -static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s) +static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev, + unsigned chan) { - struct ni_gpct *counter = s->private; - int retval; + struct ni_private *devpriv = dev->private; + const unsigned array_offset = chan / 3; - retval = ni_tio_cancel(counter); - ni_e_series_enable_second_irq(dev, counter->counter_index, 0); - ni_release_gpct_mite_channel(dev, counter->counter_index); - return retval; + return MSeries_PFI_Output_Select_Source(chan, + devpriv->pfi_output_select_reg[array_offset]); } -#endif - -/* - * - * Programmable Function Inputs - * - */ -static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan, - unsigned source) +static int ni_m_series_set_pfi_routing(struct comedi_device *dev, + unsigned chan, unsigned source) { struct ni_private *devpriv = dev->private; unsigned pfi_reg_index; @@ -5028,132 +4614,51 @@ static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan, ~MSeries_PFI_Output_Select_Mask(chan); devpriv->pfi_output_select_reg[array_offset] |= MSeries_PFI_Output_Select_Bits(chan, source); - ni_writew(devpriv->pfi_output_select_reg[array_offset], + ni_writew(dev, devpriv->pfi_output_select_reg[array_offset], M_Offset_PFI_Output_Select(pfi_reg_index)); return 2; } -static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan, - unsigned source) +static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan) { - /* pre-m-series boards have fixed signals on pfi pins */ - if (source != ni_old_get_pfi_routing(dev, chan)) - return -EINVAL; - return 2; + struct ni_private *devpriv = dev->private; + + return (devpriv->is_m_series) + ? ni_m_series_get_pfi_routing(dev, chan) + : ni_old_get_pfi_routing(dev, chan); } static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan, unsigned source) { - const struct ni_board_struct *board = comedi_board(dev); - - if (board->reg_type & ni_reg_m_series_mask) - return ni_m_series_set_pfi_routing(dev, chan, source); - else - return ni_old_set_pfi_routing(dev, chan, source); -} - -static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev, - unsigned chan) -{ struct ni_private *devpriv = dev->private; - const unsigned array_offset = chan / 3; - - return MSeries_PFI_Output_Select_Source(chan, - devpriv-> - pfi_output_select_reg - [array_offset]); -} - -static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan) -{ - /* pre-m-series boards have fixed signals on pfi pins */ - switch (chan) { - case 0: - return NI_PFI_OUTPUT_AI_START1; - break; - case 1: - return NI_PFI_OUTPUT_AI_START2; - break; - case 2: - return NI_PFI_OUTPUT_AI_CONVERT; - break; - case 3: - return NI_PFI_OUTPUT_G_SRC1; - break; - case 4: - return NI_PFI_OUTPUT_G_GATE1; - break; - case 5: - return NI_PFI_OUTPUT_AO_UPDATE_N; - break; - case 6: - return NI_PFI_OUTPUT_AO_START1; - break; - case 7: - return NI_PFI_OUTPUT_AI_START_PULSE; - break; - case 8: - return NI_PFI_OUTPUT_G_SRC0; - break; - case 9: - return NI_PFI_OUTPUT_G_GATE0; - break; - default: - printk("%s: bug, unhandled case in switch.\n", __func__); - break; - } - return 0; -} - -static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan) -{ - const struct ni_board_struct *board = comedi_board(dev); - if (board->reg_type & ni_reg_m_series_mask) - return ni_m_series_get_pfi_routing(dev, chan); - else - return ni_old_get_pfi_routing(dev, chan); + return (devpriv->is_m_series) + ? ni_m_series_set_pfi_routing(dev, chan, source) + : ni_old_set_pfi_routing(dev, chan, source); } -static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel, +static int ni_config_filter(struct comedi_device *dev, + unsigned pfi_channel, enum ni_pfi_filter_select filter) { - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv __maybe_unused = dev->private; + struct ni_private *devpriv = dev->private; unsigned bits; - if ((board->reg_type & ni_reg_m_series_mask) == 0) + if (!devpriv->is_m_series) return -ENOTSUPP; - bits = ni_readl(M_Offset_PFI_Filter); + + bits = ni_readl(dev, M_Offset_PFI_Filter); bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel); bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter); - ni_writel(bits, M_Offset_PFI_Filter); + ni_writel(dev, bits, M_Offset_PFI_Filter); return 0; } -static int ni_pfi_insn_bits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) -{ - const struct ni_board_struct *board = comedi_board(dev); - struct ni_private *devpriv __maybe_unused = dev->private; - - if (!(board->reg_type & ni_reg_m_series_mask)) - return -ENOTSUPP; - - if (comedi_dio_update_state(s, data)) - ni_writew(s->state, M_Offset_PFI_DO); - - data[1] = ni_readw(M_Offset_PFI_DI); - - return insn->n; -} - static int ni_pfi_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { struct ni_private *devpriv = dev->private; unsigned int chan; @@ -5175,78 +4680,178 @@ static int ni_pfi_insn_config(struct comedi_device *dev, (devpriv->io_bidirection_pin_reg & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT; return 0; - break; case INSN_CONFIG_SET_ROUTING: return ni_set_pfi_routing(dev, chan, data[1]); - break; case INSN_CONFIG_GET_ROUTING: data[1] = ni_get_pfi_routing(dev, chan); break; case INSN_CONFIG_FILTER: return ni_config_filter(dev, chan, data[1]); - break; default: return -EINVAL; } return 0; } -/* - * - * NI RTSI Bus Functions - * - */ -static void ni_rtsi_init(struct comedi_device *dev) +static int ni_pfi_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; - /* Initialises the RTSI bus signal switch to a default state */ + if (!devpriv->is_m_series) + return -ENOTSUPP; - /* Set clock mode to internal */ - devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit; - if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) - printk("ni_set_master_clock failed, bug?"); - /* default internal lines routing to RTSI bus lines */ - devpriv->rtsi_trig_a_output_reg = - RTSI_Trig_Output_Bits(0, - NI_RTSI_OUTPUT_ADR_START1) | - RTSI_Trig_Output_Bits(1, - NI_RTSI_OUTPUT_ADR_START2) | - RTSI_Trig_Output_Bits(2, - NI_RTSI_OUTPUT_SCLKG) | - RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN); - devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg, - RTSI_Trig_A_Output_Register); - devpriv->rtsi_trig_b_output_reg = - RTSI_Trig_Output_Bits(4, - NI_RTSI_OUTPUT_DA_START1) | - RTSI_Trig_Output_Bits(5, - NI_RTSI_OUTPUT_G_SRC0) | - RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0); - if (board->reg_type & ni_reg_m_series_mask) - devpriv->rtsi_trig_b_output_reg |= - RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC); - devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg, - RTSI_Trig_B_Output_Register); + if (comedi_dio_update_state(s, data)) + ni_writew(dev, s->state, M_Offset_PFI_DO); -/* -* Sets the source and direction of the 4 on board lines -* devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register); -*/ + data[1] = ni_readw(dev, M_Offset_PFI_DI); + + return insn->n; } -static int ni_rtsi_insn_bits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int cs5529_wait_for_idle(struct comedi_device *dev) { - data[1] = 0; + unsigned short status; + const int timeout = HZ; + int i; + for (i = 0; i < timeout; i++) { + status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); + if ((status & CSS_ADC_BUSY) == 0) + break; + set_current_state(TASK_INTERRUPTIBLE); + if (schedule_timeout(1)) + return -EIO; + } + if (i == timeout) { + dev_err(dev->class_dev, "%s timeout\n", __func__); + return -ETIME; + } + return 0; +} + +static void cs5529_command(struct comedi_device *dev, unsigned short value) +{ + static const int timeout = 100; + int i; + + ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx); + /* give time for command to start being serially clocked into cs5529. + * this insures that the CSS_ADC_BUSY bit will get properly + * set before we exit this function. + */ + for (i = 0; i < timeout; i++) { + if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY)) + break; + udelay(1); + } + if (i == timeout) + dev_err(dev->class_dev, + "possible problem - never saw adc go busy?\n"); +} + +static int cs5529_do_conversion(struct comedi_device *dev, + unsigned short *data) +{ + int retval; + unsigned short status; + + cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION); + retval = cs5529_wait_for_idle(dev); + if (retval) { + dev_err(dev->class_dev, + "timeout or signal in cs5529_do_conversion()\n"); + return -ETIME; + } + status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); + if (status & CSS_OSC_DETECT) { + dev_err(dev->class_dev, + "cs5529 conversion error, status CSS_OSC_DETECT\n"); + return -EIO; + } + if (status & CSS_OVERRANGE) { + dev_err(dev->class_dev, + "cs5529 conversion error, overrange (ignoring)\n"); + } + if (data) { + *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx); + /* cs5529 returns 16 bit signed data in bipolar mode */ + *data ^= (1 << 15); + } + return 0; +} + +static int cs5529_ai_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + int n, retval; + unsigned short sample; + unsigned int channel_select; + const unsigned int INTERNAL_REF = 0x1000; + + /* Set calibration adc source. Docs lie, reference select bits 8 to 11 + * do nothing. bit 12 seems to chooses internal reference voltage, bit + * 13 causes the adc input to go overrange (maybe reads external reference?) */ + if (insn->chanspec & CR_ALT_SOURCE) + channel_select = INTERNAL_REF; + else + channel_select = CR_CHAN(insn->chanspec); + ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx); + + for (n = 0; n < insn->n; n++) { + retval = cs5529_do_conversion(dev, &sample); + if (retval < 0) + return retval; + data[n] = sample; + } return insn->n; } -/* Find best multiplier/divider to try and get the PLL running at 80 MHz - * given an arbitrary frequency input clock */ +static void cs5529_config_write(struct comedi_device *dev, unsigned int value, + unsigned int reg_select_bits) +{ + ni_ao_win_outw(dev, ((value >> 16) & 0xff), + CAL_ADC_Config_Data_High_Word_67xx); + ni_ao_win_outw(dev, (value & 0xffff), + CAL_ADC_Config_Data_Low_Word_67xx); + reg_select_bits &= CSCMD_REGISTER_SELECT_MASK; + cs5529_command(dev, CSCMD_COMMAND | reg_select_bits); + if (cs5529_wait_for_idle(dev)) + dev_err(dev->class_dev, + "timeout or signal in %s\n", __func__); +} + +static int init_cs5529(struct comedi_device *dev) +{ + unsigned int config_bits = + CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES; + +#if 1 + /* do self-calibration */ + cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, + CSCMD_CONFIG_REGISTER); + /* need to force a conversion for calibration to run */ + cs5529_do_conversion(dev, NULL); +#else + /* force gain calibration to 1 */ + cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER); + cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, + CSCMD_CONFIG_REGISTER); + if (cs5529_wait_for_idle(dev)) + dev_err(dev->class_dev, + "timeout or signal in %s\n", __func__); +#endif + return 0; +} + +/* + * Find best multiplier/divider to try and get the PLL running at 80 MHz + * given an arbitrary frequency input clock. + */ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, unsigned *freq_divider, unsigned *freq_multiplier, @@ -5266,6 +4871,7 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, static const unsigned target_picosec = 12500; static const unsigned fudge_factor_80_to_20Mhz = 4; int best_period_picosec = 0; + for (div = 1; div <= max_div; ++div) { for (mult = 1; mult <= max_mult; ++mult) { unsigned new_period_ps = @@ -5278,10 +4884,9 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, } } } - if (best_period_picosec == 0) { - printk("%s: bug, failed to find pll parameters\n", __func__); + if (best_period_picosec == 0) return -EIO; - } + *freq_divider = best_div; *freq_multiplier = best_mult; *actual_period_ns = @@ -5290,16 +4895,6 @@ static int ni_mseries_get_pll_parameters(unsigned reference_period_ns, return 0; } -static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev) -{ - const struct ni_board_struct *board = comedi_board(dev); - - if (board->reg_type & ni_reg_m_series_mask) - return 8; - else - return 7; -} - static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, unsigned source, unsigned period_ns) { @@ -5317,15 +4912,14 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, period_ns = 100; /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */ if (period_ns < min_period_ns || period_ns > max_period_ns) { - printk - ("%s: you must specify an input clock frequency between %i and %i nanosec " - "for the phased-lock loop.\n", __func__, - min_period_ns, max_period_ns); + dev_err(dev->class_dev, + "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n", + __func__, min_period_ns, max_period_ns); return -EINVAL; } devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; - devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); + ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, + RTSI_Trig_Direction_Register); pll_control_bits = MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits; devpriv->clock_and_fout2 |= @@ -5335,26 +4929,17 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK: devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_Star_Trigger_Bits; - retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider, - &freq_multiplier, - &devpriv->clock_ns); - if (retval < 0) - return retval; break; case NI_MIO_PLL_PXI10_CLOCK: /* pxi clock is 10MHz */ devpriv->clock_and_fout2 |= MSeries_PLL_In_Source_Select_PXI_Clock10; - retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider, - &freq_multiplier, - &devpriv->clock_ns); - if (retval < 0) - return retval; break; default: { unsigned rtsi_channel; static const unsigned max_rtsi_channel = 7; + for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel; ++rtsi_channel) { if (source == @@ -5367,81 +4952,78 @@ static int ni_mseries_set_pll_master_clock(struct comedi_device *dev, } if (rtsi_channel > max_rtsi_channel) return -EINVAL; - retval = ni_mseries_get_pll_parameters(period_ns, - &freq_divider, - &freq_multiplier, - &devpriv-> - clock_ns); - if (retval < 0) - return retval; } break; } - ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2); + retval = ni_mseries_get_pll_parameters(period_ns, + &freq_divider, + &freq_multiplier, + &devpriv->clock_ns); + if (retval < 0) { + dev_err(dev->class_dev, + "%s: bug, failed to find pll parameters\n", __func__); + return retval; + } + + ni_writew(dev, devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2); pll_control_bits |= MSeries_PLL_Divisor_Bits(freq_divider) | MSeries_PLL_Multiplier_Bits(freq_multiplier); - /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n", - * freq_divider, freq_multiplier, pll_control_bits); */ - /* printk("clock_ns=%d\n", devpriv->clock_ns); */ - ni_writew(pll_control_bits, M_Offset_PLL_Control); + ni_writew(dev, pll_control_bits, M_Offset_PLL_Control); devpriv->clock_source = source; /* it seems to typically take a few hundred microseconds for PLL to lock */ for (i = 0; i < timeout; ++i) { - if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) + if (ni_readw(dev, M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) break; udelay(1); } if (i == timeout) { - printk - ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n", - __func__, source, period_ns); + dev_err(dev->class_dev, + "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n", + __func__, source, period_ns); return -ETIMEDOUT; } return 3; } -static int ni_set_master_clock(struct comedi_device *dev, unsigned source, - unsigned period_ns) +static int ni_set_master_clock(struct comedi_device *dev, + unsigned source, unsigned period_ns) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; if (source == NI_MIO_INTERNAL_CLOCK) { devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit; - devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); + ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, + RTSI_Trig_Direction_Register); devpriv->clock_ns = TIMEBASE_1_NS; - if (board->reg_type & ni_reg_m_series_mask) { + if (devpriv->is_m_series) { devpriv->clock_and_fout2 &= ~(MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit); - ni_writew(devpriv->clock_and_fout2, + ni_writew(dev, devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2); - ni_writew(0, M_Offset_PLL_Control); + ni_writew(dev, 0, M_Offset_PLL_Control); } devpriv->clock_source = source; } else { - if (board->reg_type & ni_reg_m_series_mask) { + if (devpriv->is_m_series) { return ni_mseries_set_pll_master_clock(dev, source, period_ns); } else { if (source == NI_MIO_RTSI_CLOCK) { devpriv->rtsi_trig_direction_reg |= Use_RTSI_Clock_Bit; - devpriv->stc_writew(dev, - devpriv-> - rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); + ni_stc_writew(dev, + devpriv->rtsi_trig_direction_reg, + RTSI_Trig_Direction_Register); if (period_ns == 0) { - printk - ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n", - __func__); + dev_err(dev->class_dev, + "%s: we don't handle an unspecified clock period correctly yet, returning error\n", + __func__); return -EINVAL; - } else { - devpriv->clock_ns = period_ns; } + devpriv->clock_ns = period_ns; devpriv->clock_source = source; } else return -EINVAL; @@ -5450,21 +5032,27 @@ static int ni_set_master_clock(struct comedi_device *dev, unsigned source, return 3; } -static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan, - unsigned source) +static unsigned num_configurable_rtsi_channels(struct comedi_device *dev) { - const struct ni_board_struct *board = comedi_board(dev); + struct ni_private *devpriv = dev->private; + + return (devpriv->is_m_series) ? 8 : 7; +} + +static int ni_valid_rtsi_output_source(struct comedi_device *dev, + unsigned chan, unsigned source) +{ + struct ni_private *devpriv = dev->private; if (chan >= num_configurable_rtsi_channels(dev)) { if (chan == old_RTSI_clock_channel) { if (source == NI_RTSI_OUTPUT_RTSI_OSC) return 1; - else { - printk - ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n", - __func__, chan, old_RTSI_clock_channel); - return 0; - } + + dev_err(dev->class_dev, + "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n", + __func__, chan, old_RTSI_clock_channel); + return 0; } return 0; } @@ -5479,21 +5067,15 @@ static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan, case NI_RTSI_OUTPUT_RGOUT0: case NI_RTSI_OUTPUT_RTSI_BRD_0: return 1; - break; case NI_RTSI_OUTPUT_RTSI_OSC: - if (board->reg_type & ni_reg_m_series_mask) - return 1; - else - return 0; - break; + return (devpriv->is_m_series) ? 1 : 0; default: return 0; - break; } } -static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan, - unsigned source) +static int ni_set_rtsi_routing(struct comedi_device *dev, + unsigned chan, unsigned source) { struct ni_private *devpriv = dev->private; @@ -5503,14 +5085,14 @@ static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan, devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan); devpriv->rtsi_trig_a_output_reg |= RTSI_Trig_Output_Bits(chan, source); - devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg, - RTSI_Trig_A_Output_Register); + ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, + RTSI_Trig_A_Output_Register); } else if (chan < 8) { devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan); devpriv->rtsi_trig_b_output_reg |= RTSI_Trig_Output_Bits(chan, source); - devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg, - RTSI_Trig_B_Output_Register); + ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, + RTSI_Trig_B_Output_Register); } return 2; } @@ -5528,16 +5110,17 @@ static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan) } else { if (chan == old_RTSI_clock_channel) return NI_RTSI_OUTPUT_RTSI_OSC; - printk("%s: bug! should never get here?\n", __func__); + dev_err(dev->class_dev, "%s: bug! should never get here?\n", + __func__); return 0; } } static int ni_rtsi_insn_config(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { - const struct ni_board_struct *board = comedi_board(dev); struct ni_private *devpriv = dev->private; unsigned int chan = CR_CHAN(insn->chanspec); @@ -5545,33 +5128,30 @@ static int ni_rtsi_insn_config(struct comedi_device *dev, case INSN_CONFIG_DIO_OUTPUT: if (chan < num_configurable_rtsi_channels(dev)) { devpriv->rtsi_trig_direction_reg |= - RTSI_Output_Bit(chan, - (board->reg_type & ni_reg_m_series_mask) != 0); + RTSI_Output_Bit(chan, devpriv->is_m_series); } else if (chan == old_RTSI_clock_channel) { devpriv->rtsi_trig_direction_reg |= Drive_RTSI_Clock_Bit; } - devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); + ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, + RTSI_Trig_Direction_Register); break; case INSN_CONFIG_DIO_INPUT: if (chan < num_configurable_rtsi_channels(dev)) { devpriv->rtsi_trig_direction_reg &= - ~RTSI_Output_Bit(chan, - (board->reg_type & ni_reg_m_series_mask) != 0); + ~RTSI_Output_Bit(chan, devpriv->is_m_series); } else if (chan == old_RTSI_clock_channel) { devpriv->rtsi_trig_direction_reg &= ~Drive_RTSI_Clock_Bit; } - devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg, - RTSI_Trig_Direction_Register); + ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, + RTSI_Trig_Direction_Register); break; case INSN_CONFIG_DIO_QUERY: if (chan < num_configurable_rtsi_channels(dev)) { data[1] = (devpriv->rtsi_trig_direction_reg & - RTSI_Output_Bit(chan, - (board->reg_type & ni_reg_m_series_mask) != 0)) + RTSI_Output_Bit(chan, devpriv->is_m_series)) ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT; } else if (chan == old_RTSI_clock_channel) { @@ -5581,160 +5161,600 @@ static int ni_rtsi_insn_config(struct comedi_device *dev, ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT; } return 2; - break; case INSN_CONFIG_SET_CLOCK_SRC: return ni_set_master_clock(dev, data[1], data[2]); - break; case INSN_CONFIG_GET_CLOCK_SRC: data[1] = devpriv->clock_source; data[2] = devpriv->clock_ns; return 3; - break; case INSN_CONFIG_SET_ROUTING: return ni_set_rtsi_routing(dev, chan, data[1]); - break; case INSN_CONFIG_GET_ROUTING: data[1] = ni_get_rtsi_routing(dev, chan); return 2; - break; default: return -EINVAL; - break; } return 1; } -static int cs5529_wait_for_idle(struct comedi_device *dev) +static int ni_rtsi_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { - unsigned short status; - const int timeout = HZ; - int i; + data[1] = 0; - for (i = 0; i < timeout; i++) { - status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); - if ((status & CSS_ADC_BUSY) == 0) - break; - set_current_state(TASK_INTERRUPTIBLE); - if (schedule_timeout(1)) - return -EIO; + return insn->n; +} + +static void ni_rtsi_init(struct comedi_device *dev) +{ + struct ni_private *devpriv = dev->private; + + /* Initialises the RTSI bus signal switch to a default state */ + + /* Set clock mode to internal */ + devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit; + if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) + dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n"); + /* default internal lines routing to RTSI bus lines */ + devpriv->rtsi_trig_a_output_reg = + RTSI_Trig_Output_Bits(0, + NI_RTSI_OUTPUT_ADR_START1) | + RTSI_Trig_Output_Bits(1, + NI_RTSI_OUTPUT_ADR_START2) | + RTSI_Trig_Output_Bits(2, + NI_RTSI_OUTPUT_SCLKG) | + RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN); + ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, + RTSI_Trig_A_Output_Register); + devpriv->rtsi_trig_b_output_reg = + RTSI_Trig_Output_Bits(4, + NI_RTSI_OUTPUT_DA_START1) | + RTSI_Trig_Output_Bits(5, + NI_RTSI_OUTPUT_G_SRC0) | + RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0); + if (devpriv->is_m_series) + devpriv->rtsi_trig_b_output_reg |= + RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC); + ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, + RTSI_Trig_B_Output_Register); + +/* +* Sets the source and direction of the 4 on board lines +* ni_stc_writew(dev, 0x0000, RTSI_Board_Register); +*/ +} + +#ifdef PCIDMA +static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s) +{ + struct ni_gpct *counter = s->private; + int retval; + + retval = ni_request_gpct_mite_channel(dev, counter->counter_index, + COMEDI_INPUT); + if (retval) { + dev_err(dev->class_dev, + "no dma channel available for use by counter\n"); + return retval; } -/* printk("looped %i times waiting for idle\n", i); */ - if (i == timeout) { - printk("%s: %s: timeout\n", __FILE__, __func__); - return -ETIME; + ni_tio_acknowledge(counter); + ni_e_series_enable_second_irq(dev, counter->counter_index, 1); + + return ni_tio_cmd(dev, s); +} + +static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s) +{ + struct ni_gpct *counter = s->private; + int retval; + + retval = ni_tio_cancel(counter); + ni_e_series_enable_second_irq(dev, counter->counter_index, 0); + ni_release_gpct_mite_channel(dev, counter->counter_index); + return retval; +} +#endif + +#if 0 +/* + * Read the GPCTs current value. + */ +static int GPCT_G_Watch(struct comedi_device *dev, int chan) +{ + unsigned int hi1, hi2, lo; + + devpriv->gpct_command[chan] &= ~G_Save_Trace; + ni_stc_writew(dev, devpriv->gpct_command[chan], + G_Command_Register(chan)); + + devpriv->gpct_command[chan] |= G_Save_Trace; + ni_stc_writew(dev, devpriv->gpct_command[chan], + G_Command_Register(chan)); + + /* This procedure is used because the two registers cannot + * be read atomically. */ + do { + hi1 = ni_stc_readw(dev, G_Save_Register_High(chan)); + lo = ni_stc_readw(dev, G_Save_Register_Low(chan)); + hi2 = ni_stc_readw(dev, G_Save_Register_High(chan)); + } while (hi1 != hi2); + + return (hi1 << 16) | lo; +} + +static void GPCT_Reset(struct comedi_device *dev, int chan) +{ + int temp_ack_reg = 0; + + devpriv->gpct_cur_operation[chan] = GPCT_RESET; + + switch (chan) { + case 0: + ni_stc_writew(dev, G0_Reset, Joint_Reset_Register); + ni_set_bits(dev, Interrupt_A_Enable_Register, + G0_TC_Interrupt_Enable, 0); + ni_set_bits(dev, Interrupt_A_Enable_Register, + G0_Gate_Interrupt_Enable, 0); + temp_ack_reg |= G0_Gate_Error_Confirm; + temp_ack_reg |= G0_TC_Error_Confirm; + temp_ack_reg |= G0_TC_Interrupt_Ack; + temp_ack_reg |= G0_Gate_Interrupt_Ack; + ni_stc_writew(dev, temp_ack_reg, Interrupt_A_Ack_Register); + + /* problem...this interferes with the other ctr... */ + devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable; + ni_stc_writew(dev, devpriv->an_trig_etc_reg, + Analog_Trigger_Etc_Register); + break; + case 1: + ni_stc_writew(dev, G1_Reset, Joint_Reset_Register); + ni_set_bits(dev, Interrupt_B_Enable_Register, + G1_TC_Interrupt_Enable, 0); + ni_set_bits(dev, Interrupt_B_Enable_Register, + G0_Gate_Interrupt_Enable, 0); + temp_ack_reg |= G1_Gate_Error_Confirm; + temp_ack_reg |= G1_TC_Error_Confirm; + temp_ack_reg |= G1_TC_Interrupt_Ack; + temp_ack_reg |= G1_Gate_Interrupt_Ack; + ni_stc_writew(dev, temp_ack_reg, Interrupt_B_Ack_Register); + + devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable; + ni_stc_writew(dev, devpriv->an_trig_etc_reg, + Analog_Trigger_Etc_Register); + break; } - return 0; + + devpriv->gpct_mode[chan] = 0; + devpriv->gpct_input_select[chan] = 0; + devpriv->gpct_command[chan] = 0; + + devpriv->gpct_command[chan] |= G_Synchronized_Gate; + + ni_stc_writew(dev, devpriv->gpct_mode[chan], G_Mode_Register(chan)); + ni_stc_writew(dev, devpriv->gpct_input_select[chan], + G_Input_Select_Register(chan)); + ni_stc_writew(dev, 0, G_Autoincrement_Register(chan)); } +#endif -static void cs5529_command(struct comedi_device *dev, unsigned short value) +static irqreturn_t ni_E_interrupt(int irq, void *d) { - static const int timeout = 100; - int i; + struct comedi_device *dev = d; + unsigned short a_status; + unsigned short b_status; + unsigned int ai_mite_status = 0; + unsigned int ao_mite_status = 0; + unsigned long flags; +#ifdef PCIDMA + struct ni_private *devpriv = dev->private; + struct mite_struct *mite = devpriv->mite; +#endif - ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx); - /* give time for command to start being serially clocked into cs5529. - * this insures that the CSS_ADC_BUSY bit will get properly - * set before we exit this function. - */ - for (i = 0; i < timeout; i++) { - if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY)) - break; - udelay(1); + if (!dev->attached) + return IRQ_NONE; + smp_mb(); /* make sure dev->attached is checked before handler does anything else. */ + + /* lock to avoid race with comedi_poll */ + spin_lock_irqsave(&dev->spinlock, flags); + a_status = ni_stc_readw(dev, AI_Status_1_Register); + b_status = ni_stc_readw(dev, AO_Status_1_Register); +#ifdef PCIDMA + if (mite) { + struct ni_private *devpriv = dev->private; + unsigned long flags_too; + + spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); + if (devpriv->ai_mite_chan) { + ai_mite_status = mite_get_status(devpriv->ai_mite_chan); + if (ai_mite_status & CHSR_LINKC) + writel(CHOR_CLRLC, + devpriv->mite->mite_io_addr + + MITE_CHOR(devpriv-> + ai_mite_chan->channel)); + } + if (devpriv->ao_mite_chan) { + ao_mite_status = mite_get_status(devpriv->ao_mite_chan); + if (ao_mite_status & CHSR_LINKC) + writel(CHOR_CLRLC, + mite->mite_io_addr + + MITE_CHOR(devpriv-> + ao_mite_chan->channel)); + } + spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); } -/* printk("looped %i times writing command to cs5529\n", i); */ - if (i == timeout) - comedi_error(dev, "possible problem - never saw adc go busy?"); +#endif + ack_a_interrupt(dev, a_status); + ack_b_interrupt(dev, b_status); + if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT)) + handle_a_interrupt(dev, a_status, ai_mite_status); + if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT)) + handle_b_interrupt(dev, b_status, ao_mite_status); + handle_gpct_interrupt(dev, 0); + handle_gpct_interrupt(dev, 1); + handle_cdio_interrupt(dev); + + spin_unlock_irqrestore(&dev->spinlock, flags); + return IRQ_HANDLED; } -/* write to cs5529 register */ -static void cs5529_config_write(struct comedi_device *dev, unsigned int value, - unsigned int reg_select_bits) +static int ni_alloc_private(struct comedi_device *dev) { - ni_ao_win_outw(dev, ((value >> 16) & 0xff), - CAL_ADC_Config_Data_High_Word_67xx); - ni_ao_win_outw(dev, (value & 0xffff), - CAL_ADC_Config_Data_Low_Word_67xx); - reg_select_bits &= CSCMD_REGISTER_SELECT_MASK; - cs5529_command(dev, CSCMD_COMMAND | reg_select_bits); - if (cs5529_wait_for_idle(dev)) - comedi_error(dev, "time or signal in cs5529_config_write()"); + struct ni_private *devpriv; + + devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); + if (!devpriv) + return -ENOMEM; + + spin_lock_init(&devpriv->window_lock); + spin_lock_init(&devpriv->soft_reg_copy_lock); + spin_lock_init(&devpriv->mite_channel_lock); + + return 0; } -static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data) +static int ni_E_init(struct comedi_device *dev, + unsigned interrupt_pin, unsigned irq_polarity) { - int retval; - unsigned short status; + const struct ni_board_struct *board = comedi_board(dev); + struct ni_private *devpriv = dev->private; + struct comedi_subdevice *s; + int ret; + int i; - cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION); - retval = cs5529_wait_for_idle(dev); - if (retval) { - comedi_error(dev, - "timeout or signal in cs5529_do_conversion()"); - return -ETIME; + if (board->n_aochan > MAX_N_AO_CHAN) { + dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n"); + return -EINVAL; } - status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx); - if (status & CSS_OSC_DETECT) { - printk - ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n"); - return -EIO; + + /* initialize clock dividers */ + devpriv->clock_and_fout = Slow_Internal_Time_Divide_By_2 | + Slow_Internal_Timebase | + Clock_To_Board_Divide_By_2 | + Clock_To_Board; + if (!devpriv->is_6xxx) { + /* BEAM is this needed for PCI-6143 ?? */ + devpriv->clock_and_fout |= (AI_Output_Divide_By_2 | + AO_Output_Divide_By_2); } - if (status & CSS_OVERRANGE) { - printk - ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n"); + ni_stc_writew(dev, devpriv->clock_and_fout, Clock_and_FOUT_Register); + + ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES); + if (ret) + return ret; + + /* Analog Input subdevice */ + s = &dev->subdevices[NI_AI_SUBDEV]; + if (board->n_adchan) { + s->type = COMEDI_SUBD_AI; + s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER; + if (!devpriv->is_611x) + s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER; + if (board->ai_maxdata > 0xffff) + s->subdev_flags |= SDF_LSAMPL; + if (devpriv->is_m_series) + s->subdev_flags |= SDF_SOFT_CALIBRATED; + s->n_chan = board->n_adchan; + s->maxdata = board->ai_maxdata; + s->range_table = ni_range_lkup[board->gainlkup]; + s->insn_read = ni_ai_insn_read; + s->insn_config = ni_ai_insn_config; + if (dev->irq) { + dev->read_subdev = s; + s->subdev_flags |= SDF_CMD_READ; + s->len_chanlist = 512; + s->do_cmdtest = ni_ai_cmdtest; + s->do_cmd = ni_ai_cmd; + s->cancel = ni_ai_reset; + s->poll = ni_ai_poll; + s->munge = ni_ai_munge; + + if (devpriv->mite) + s->async_dma_dir = DMA_FROM_DEVICE; + } + + /* reset the analog input configuration */ + ni_ai_reset(dev, s); + } else { + s->type = COMEDI_SUBD_UNUSED; } - if (data) { - *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx); - /* cs5529 returns 16 bit signed data in bipolar mode */ - *data ^= (1 << 15); + + /* Analog Output subdevice */ + s = &dev->subdevices[NI_AO_SUBDEV]; + if (board->n_aochan) { + s->type = COMEDI_SUBD_AO; + s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND; + if (devpriv->is_m_series) + s->subdev_flags |= SDF_SOFT_CALIBRATED; + s->n_chan = board->n_aochan; + s->maxdata = board->ao_maxdata; + s->range_table = board->ao_range_table; + s->insn_read = ni_ao_insn_read; + s->insn_write = ni_ao_insn_write; + s->insn_config = ni_ao_insn_config; + + /* + * Along with the IRQ we need either a FIFO or DMA for + * async command support. + */ + if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) { + dev->write_subdev = s; + s->subdev_flags |= SDF_CMD_WRITE; + s->len_chanlist = s->n_chan; + s->do_cmdtest = ni_ao_cmdtest; + s->do_cmd = ni_ao_cmd; + s->cancel = ni_ao_reset; + if (!devpriv->is_m_series) + s->munge = ni_ao_munge; + + if (devpriv->mite) + s->async_dma_dir = DMA_TO_DEVICE; + } + + if (devpriv->is_67xx) + init_ao_67xx(dev, s); + + /* reset the analog output configuration */ + ni_ao_reset(dev, s); + } else { + s->type = COMEDI_SUBD_UNUSED; } - return 0; -} -static int cs5529_ai_insn_read(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) -{ - int n, retval; - unsigned short sample; - unsigned int channel_select; - const unsigned int INTERNAL_REF = 0x1000; + /* Digital I/O subdevice */ + s = &dev->subdevices[NI_DIO_SUBDEV]; + s->type = COMEDI_SUBD_DIO; + s->subdev_flags = SDF_WRITABLE | SDF_READABLE; + s->n_chan = board->has_32dio_chan ? 32 : 8; + s->maxdata = 1; + s->range_table = &range_digital; + if (devpriv->is_m_series) { + s->subdev_flags |= SDF_LSAMPL; + s->insn_bits = ni_m_series_dio_insn_bits; + s->insn_config = ni_m_series_dio_insn_config; + if (dev->irq) { + s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */; + s->len_chanlist = s->n_chan; + s->do_cmdtest = ni_cdio_cmdtest; + s->do_cmd = ni_cdio_cmd; + s->cancel = ni_cdio_cancel; + + /* M-series boards use DMA */ + s->async_dma_dir = DMA_BIDIRECTIONAL; + } - /* Set calibration adc source. Docs lie, reference select bits 8 to 11 - * do nothing. bit 12 seems to chooses internal reference voltage, bit - * 13 causes the adc input to go overrange (maybe reads external reference?) */ - if (insn->chanspec & CR_ALT_SOURCE) - channel_select = INTERNAL_REF; - else - channel_select = CR_CHAN(insn->chanspec); - ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx); + /* reset DIO and set all channels to inputs */ + ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit, + M_Offset_CDIO_Command); + ni_writel(dev, s->io_bits, M_Offset_DIO_Direction); + } else { + s->insn_bits = ni_dio_insn_bits; + s->insn_config = ni_dio_insn_config; - for (n = 0; n < insn->n; n++) { - retval = cs5529_do_conversion(dev, &sample); - if (retval < 0) - return retval; - data[n] = sample; + /* set all channels to inputs */ + devpriv->dio_control = DIO_Pins_Dir(s->io_bits); + ni_writew(dev, devpriv->dio_control, DIO_Control_Register); } - return insn->n; -} -static int init_cs5529(struct comedi_device *dev) -{ - unsigned int config_bits = - CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES; + /* 8255 device */ + s = &dev->subdevices[NI_8255_DIO_SUBDEV]; + if (board->has_8255) { + ret = subdev_8255_init(dev, s, ni_8255_callback, + (unsigned long)dev); + if (ret) + return ret; + } else { + s->type = COMEDI_SUBD_UNUSED; + } -#if 1 - /* do self-calibration */ - cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN, - CSCMD_CONFIG_REGISTER); - /* need to force a conversion for calibration to run */ - cs5529_do_conversion(dev, NULL); -#else - /* force gain calibration to 1 */ - cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER); - cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET, - CSCMD_CONFIG_REGISTER); - if (cs5529_wait_for_idle(dev)) - comedi_error(dev, "timeout or signal in init_cs5529()\n"); + /* formerly general purpose counter/timer device, but no longer used */ + s = &dev->subdevices[NI_UNUSED_SUBDEV]; + s->type = COMEDI_SUBD_UNUSED; + + /* Calibration subdevice */ + s = &dev->subdevices[NI_CALIBRATION_SUBDEV]; + s->type = COMEDI_SUBD_CALIB; + s->subdev_flags = SDF_INTERNAL; + s->n_chan = 1; + s->maxdata = 0; + if (devpriv->is_m_series) { + /* internal PWM output used for AI nonlinearity calibration */ + s->insn_config = ni_m_series_pwm_config; + + ni_writel(dev, 0x0, M_Offset_Cal_PWM); + } else if (devpriv->is_6143) { + /* internal PWM output used for AI nonlinearity calibration */ + s->insn_config = ni_6143_pwm_config; + } else { + s->subdev_flags |= SDF_WRITABLE; + s->insn_read = ni_calib_insn_read; + s->insn_write = ni_calib_insn_write; + + /* setup the caldacs and find the real n_chan and maxdata */ + caldac_setup(dev, s); + } + + /* EEPROM subdevice */ + s = &dev->subdevices[NI_EEPROM_SUBDEV]; + s->type = COMEDI_SUBD_MEMORY; + s->subdev_flags = SDF_READABLE | SDF_INTERNAL; + s->maxdata = 0xff; + if (devpriv->is_m_series) { + s->n_chan = M_SERIES_EEPROM_SIZE; + s->insn_read = ni_m_series_eeprom_insn_read; + } else { + s->n_chan = 512; + s->insn_read = ni_eeprom_insn_read; + } + + /* Digital I/O (PFI) subdevice */ + s = &dev->subdevices[NI_PFI_DIO_SUBDEV]; + s->type = COMEDI_SUBD_DIO; + s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; + s->maxdata = 1; + if (devpriv->is_m_series) { + s->n_chan = 16; + s->insn_bits = ni_pfi_insn_bits; + + ni_writew(dev, s->state, M_Offset_PFI_DO); + for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) { + ni_writew(dev, devpriv->pfi_output_select_reg[i], + M_Offset_PFI_Output_Select(i + 1)); + } + } else { + s->n_chan = 10; + } + s->insn_config = ni_pfi_insn_config; + + ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0); + + /* cs5529 calibration adc */ + s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV]; + if (devpriv->is_67xx) { + s->type = COMEDI_SUBD_AI; + s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL; + /* one channel for each analog output channel */ + s->n_chan = board->n_aochan; + s->maxdata = (1 << 16) - 1; + s->range_table = &range_unknown; /* XXX */ + s->insn_read = cs5529_ai_insn_read; + s->insn_config = NULL; + init_cs5529(dev); + } else { + s->type = COMEDI_SUBD_UNUSED; + } + + /* Serial */ + s = &dev->subdevices[NI_SERIAL_SUBDEV]; + s->type = COMEDI_SUBD_SERIAL; + s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; + s->n_chan = 1; + s->maxdata = 0xff; + s->insn_config = ni_serial_insn_config; + devpriv->serial_interval_ns = 0; + devpriv->serial_hw_mode = 0; + + /* RTSI */ + s = &dev->subdevices[NI_RTSI_SUBDEV]; + s->type = COMEDI_SUBD_DIO; + s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; + s->n_chan = 8; + s->maxdata = 1; + s->insn_bits = ni_rtsi_insn_bits; + s->insn_config = ni_rtsi_insn_config; + ni_rtsi_init(dev); + + /* allocate and initialize the gpct counter device */ + devpriv->counter_dev = ni_gpct_device_construct(dev, + ni_gpct_write_register, + ni_gpct_read_register, + (devpriv->is_m_series) + ? ni_gpct_variant_m_series + : ni_gpct_variant_e_series, + NUM_GPCT); + if (!devpriv->counter_dev) + return -ENOMEM; + + /* Counter (gpct) subdevices */ + for (i = 0; i < NUM_GPCT; ++i) { + struct ni_gpct *gpct = &devpriv->counter_dev->counters[i]; + + /* setup and initialize the counter */ + gpct->chip_index = 0; + gpct->counter_index = i; + ni_tio_init_counter(gpct); + + s = &dev->subdevices[NI_GPCT_SUBDEV(i)]; + s->type = COMEDI_SUBD_COUNTER; + s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL; + s->n_chan = 3; + s->maxdata = (devpriv->is_m_series) ? 0xffffffff + : 0x00ffffff; + s->insn_read = ni_tio_insn_read; + s->insn_write = ni_tio_insn_read; + s->insn_config = ni_tio_insn_config; +#ifdef PCIDMA + if (dev->irq && devpriv->mite) { + s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */; + s->len_chanlist = 1; + s->do_cmdtest = ni_tio_cmdtest; + s->do_cmd = ni_gpct_cmd; + s->cancel = ni_gpct_cancel; + + s->async_dma_dir = DMA_BIDIRECTIONAL; + } #endif + s->private = gpct; + } + + /* Frequency output subdevice */ + s = &dev->subdevices[NI_FREQ_OUT_SUBDEV]; + s->type = COMEDI_SUBD_COUNTER; + s->subdev_flags = SDF_READABLE | SDF_WRITABLE; + s->n_chan = 1; + s->maxdata = 0xf; + s->insn_read = ni_freq_out_insn_read; + s->insn_write = ni_freq_out_insn_write; + s->insn_config = ni_freq_out_insn_config; + + if (dev->irq) { + ni_stc_writew(dev, + (irq_polarity ? Interrupt_Output_Polarity : 0) | + (Interrupt_Output_On_3_Pins & 0) | + Interrupt_A_Enable | Interrupt_B_Enable | + Interrupt_A_Output_Select(interrupt_pin) | + Interrupt_B_Output_Select(interrupt_pin), + Interrupt_Control_Register); + } + + /* DMA setup */ + ni_writeb(dev, devpriv->ai_ao_select_reg, AI_AO_Select); + ni_writeb(dev, devpriv->g0_g1_select_reg, G0_G1_Select); + + if (devpriv->is_6xxx) { + ni_writeb(dev, 0, Magic_611x); + } else if (devpriv->is_m_series) { + int channel; + + for (channel = 0; channel < board->n_aochan; ++channel) { + ni_writeb(dev, 0xf, + M_Offset_AO_Waveform_Order(channel)); + ni_writeb(dev, 0x0, + M_Offset_AO_Reference_Attenuation(channel)); + } + ni_writeb(dev, 0x0, M_Offset_AO_Calibration); + } + return 0; } + +static void mio_common_detach(struct comedi_device *dev) +{ + struct ni_private *devpriv = dev->private; + + if (devpriv) { + if (devpriv->counter_dev) + ni_gpct_device_destroy(devpriv->counter_dev); + } +} |